19d26e4fcSRobert Mustacchi /****************************************************************************** 29d26e4fcSRobert Mustacchi 3*df36e06dSRobert Mustacchi Copyright (c) 2013-2018, Intel Corporation 49d26e4fcSRobert Mustacchi All rights reserved. 59d26e4fcSRobert Mustacchi 69d26e4fcSRobert Mustacchi Redistribution and use in source and binary forms, with or without 79d26e4fcSRobert Mustacchi modification, are permitted provided that the following conditions are met: 89d26e4fcSRobert Mustacchi 99d26e4fcSRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 109d26e4fcSRobert Mustacchi this list of conditions and the following disclaimer. 119d26e4fcSRobert Mustacchi 129d26e4fcSRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 139d26e4fcSRobert Mustacchi notice, this list of conditions and the following disclaimer in the 149d26e4fcSRobert Mustacchi documentation and/or other materials provided with the distribution. 159d26e4fcSRobert Mustacchi 169d26e4fcSRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 179d26e4fcSRobert Mustacchi contributors may be used to endorse or promote products derived from 189d26e4fcSRobert Mustacchi this software without specific prior written permission. 199d26e4fcSRobert Mustacchi 209d26e4fcSRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 219d26e4fcSRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 229d26e4fcSRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 239d26e4fcSRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 249d26e4fcSRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 259d26e4fcSRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 269d26e4fcSRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 279d26e4fcSRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 289d26e4fcSRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 299d26e4fcSRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 309d26e4fcSRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 319d26e4fcSRobert Mustacchi 329d26e4fcSRobert Mustacchi ******************************************************************************/ 333d75a287SRobert Mustacchi /*$FreeBSD$*/ 349d26e4fcSRobert Mustacchi 359d26e4fcSRobert Mustacchi #ifndef _I40E_ADMINQ_CMD_H_ 369d26e4fcSRobert Mustacchi #define _I40E_ADMINQ_CMD_H_ 379d26e4fcSRobert Mustacchi 389d26e4fcSRobert Mustacchi /* This header file defines the i40e Admin Queue commands and is shared between 399d26e4fcSRobert Mustacchi * i40e Firmware and Software. 409d26e4fcSRobert Mustacchi * 419d26e4fcSRobert Mustacchi * This file needs to comply with the Linux Kernel coding style. 429d26e4fcSRobert Mustacchi */ 439d26e4fcSRobert Mustacchi 4493f1cac5SPaul Winder 459d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MAJOR 0x0001 46*df36e06dSRobert Mustacchi #define I40E_FW_API_VERSION_MINOR_X722 0x000A 47*df36e06dSRobert Mustacchi #define I40E_FW_API_VERSION_MINOR_X710 0x000A 4893f1cac5SPaul Winder 4993f1cac5SPaul Winder #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 5093f1cac5SPaul Winder I40E_FW_API_VERSION_MINOR_X710 : \ 5193f1cac5SPaul Winder I40E_FW_API_VERSION_MINOR_X722) 5293f1cac5SPaul Winder 5393f1cac5SPaul Winder /* API version 1.7 implements additional link and PHY-specific APIs */ 5493f1cac5SPaul Winder #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 55*df36e06dSRobert Mustacchi /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ 56*df36e06dSRobert Mustacchi #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 57*df36e06dSRobert Mustacchi /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 58*df36e06dSRobert Mustacchi #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 59*df36e06dSRobert Mustacchi /* API version 1.10 for X722 devices adds ability to request FEC encoding */ 60*df36e06dSRobert Mustacchi #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A 619d26e4fcSRobert Mustacchi 629d26e4fcSRobert Mustacchi struct i40e_aq_desc { 639d26e4fcSRobert Mustacchi __le16 flags; 649d26e4fcSRobert Mustacchi __le16 opcode; 659d26e4fcSRobert Mustacchi __le16 datalen; 669d26e4fcSRobert Mustacchi __le16 retval; 679d26e4fcSRobert Mustacchi __le32 cookie_high; 689d26e4fcSRobert Mustacchi __le32 cookie_low; 699d26e4fcSRobert Mustacchi union { 709d26e4fcSRobert Mustacchi struct { 719d26e4fcSRobert Mustacchi __le32 param0; 729d26e4fcSRobert Mustacchi __le32 param1; 739d26e4fcSRobert Mustacchi __le32 param2; 749d26e4fcSRobert Mustacchi __le32 param3; 759d26e4fcSRobert Mustacchi } internal; 769d26e4fcSRobert Mustacchi struct { 779d26e4fcSRobert Mustacchi __le32 param0; 789d26e4fcSRobert Mustacchi __le32 param1; 799d26e4fcSRobert Mustacchi __le32 addr_high; 809d26e4fcSRobert Mustacchi __le32 addr_low; 819d26e4fcSRobert Mustacchi } external; 829d26e4fcSRobert Mustacchi u8 raw[16]; 839d26e4fcSRobert Mustacchi } params; 849d26e4fcSRobert Mustacchi }; 859d26e4fcSRobert Mustacchi 869d26e4fcSRobert Mustacchi /* Flags sub-structure 879d26e4fcSRobert Mustacchi * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 889d26e4fcSRobert Mustacchi * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 899d26e4fcSRobert Mustacchi */ 909d26e4fcSRobert Mustacchi 919d26e4fcSRobert Mustacchi /* command flags and offsets*/ 929d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD_SHIFT 0 939d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP_SHIFT 1 949d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR_SHIFT 2 959d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE_SHIFT 3 969d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB_SHIFT 9 979d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD_SHIFT 10 989d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC_SHIFT 11 999d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF_SHIFT 12 1009d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI_SHIFT 13 1019d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI_SHIFT 14 1029d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE_SHIFT 15 1039d26e4fcSRobert Mustacchi 1049d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 1059d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 1069d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 1079d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 1089d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 1099d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 1109d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 1119d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 1129d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 1139d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 1149d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 1159d26e4fcSRobert Mustacchi 1169d26e4fcSRobert Mustacchi /* error codes */ 1179d26e4fcSRobert Mustacchi enum i40e_admin_queue_err { 1189d26e4fcSRobert Mustacchi I40E_AQ_RC_OK = 0, /* success */ 1199d26e4fcSRobert Mustacchi I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 1209d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOENT = 2, /* No such element */ 1219d26e4fcSRobert Mustacchi I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 1229d26e4fcSRobert Mustacchi I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 1239d26e4fcSRobert Mustacchi I40E_AQ_RC_EIO = 5, /* I/O error */ 1249d26e4fcSRobert Mustacchi I40E_AQ_RC_ENXIO = 6, /* No such resource */ 1259d26e4fcSRobert Mustacchi I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 1269d26e4fcSRobert Mustacchi I40E_AQ_RC_EAGAIN = 8, /* Try again */ 1279d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 1289d26e4fcSRobert Mustacchi I40E_AQ_RC_EACCES = 10, /* Permission denied */ 1299d26e4fcSRobert Mustacchi I40E_AQ_RC_EFAULT = 11, /* Bad address */ 1309d26e4fcSRobert Mustacchi I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1319d26e4fcSRobert Mustacchi I40E_AQ_RC_EEXIST = 13, /* object already exists */ 1329d26e4fcSRobert Mustacchi I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 1339d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 1349d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 1359d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1369d26e4fcSRobert Mustacchi I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 1379d26e4fcSRobert Mustacchi I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 1389d26e4fcSRobert Mustacchi I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 1399d26e4fcSRobert Mustacchi I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1409d26e4fcSRobert Mustacchi I40E_AQ_RC_EFBIG = 22, /* File too large */ 1419d26e4fcSRobert Mustacchi }; 1429d26e4fcSRobert Mustacchi 1439d26e4fcSRobert Mustacchi /* Admin Queue command opcodes */ 1449d26e4fcSRobert Mustacchi enum i40e_admin_queue_opc { 1459d26e4fcSRobert Mustacchi /* aq commands */ 1469d26e4fcSRobert Mustacchi i40e_aqc_opc_get_version = 0x0001, 1479d26e4fcSRobert Mustacchi i40e_aqc_opc_driver_version = 0x0002, 1489d26e4fcSRobert Mustacchi i40e_aqc_opc_queue_shutdown = 0x0003, 1499d26e4fcSRobert Mustacchi i40e_aqc_opc_set_pf_context = 0x0004, 1509d26e4fcSRobert Mustacchi 1519d26e4fcSRobert Mustacchi /* resource ownership */ 1529d26e4fcSRobert Mustacchi i40e_aqc_opc_request_resource = 0x0008, 1539d26e4fcSRobert Mustacchi i40e_aqc_opc_release_resource = 0x0009, 1549d26e4fcSRobert Mustacchi 1559d26e4fcSRobert Mustacchi i40e_aqc_opc_list_func_capabilities = 0x000A, 1569d26e4fcSRobert Mustacchi i40e_aqc_opc_list_dev_capabilities = 0x000B, 1579d26e4fcSRobert Mustacchi 1583d75a287SRobert Mustacchi /* Proxy commands */ 1593d75a287SRobert Mustacchi i40e_aqc_opc_set_proxy_config = 0x0104, 1603d75a287SRobert Mustacchi i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 1613d75a287SRobert Mustacchi 1629d26e4fcSRobert Mustacchi /* LAA */ 1639d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_read = 0x0107, 1649d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_write = 0x0108, 1659d26e4fcSRobert Mustacchi 1669d26e4fcSRobert Mustacchi /* PXE */ 1679d26e4fcSRobert Mustacchi i40e_aqc_opc_clear_pxe_mode = 0x0110, 1689d26e4fcSRobert Mustacchi 1693d75a287SRobert Mustacchi /* WoL commands */ 1703d75a287SRobert Mustacchi i40e_aqc_opc_set_wol_filter = 0x0120, 1713d75a287SRobert Mustacchi i40e_aqc_opc_get_wake_reason = 0x0121, 172*df36e06dSRobert Mustacchi i40e_aqc_opc_clear_all_wol_filters = 0x025E, 1733d75a287SRobert Mustacchi 1749d26e4fcSRobert Mustacchi /* internal switch commands */ 1759d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_config = 0x0200, 1769d26e4fcSRobert Mustacchi i40e_aqc_opc_add_statistics = 0x0201, 1779d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_statistics = 0x0202, 1789d26e4fcSRobert Mustacchi i40e_aqc_opc_set_port_parameters = 0x0203, 1799d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 1803d75a287SRobert Mustacchi i40e_aqc_opc_set_switch_config = 0x0205, 181396505afSPaul Winder i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 182396505afSPaul Winder i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 183396505afSPaul Winder 1849d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vsi = 0x0210, 1859d26e4fcSRobert Mustacchi i40e_aqc_opc_update_vsi_parameters = 0x0211, 1869d26e4fcSRobert Mustacchi i40e_aqc_opc_get_vsi_parameters = 0x0212, 1879d26e4fcSRobert Mustacchi 1889d26e4fcSRobert Mustacchi i40e_aqc_opc_add_pv = 0x0220, 1899d26e4fcSRobert Mustacchi i40e_aqc_opc_update_pv_parameters = 0x0221, 1909d26e4fcSRobert Mustacchi i40e_aqc_opc_get_pv_parameters = 0x0222, 1919d26e4fcSRobert Mustacchi 1929d26e4fcSRobert Mustacchi i40e_aqc_opc_add_veb = 0x0230, 1939d26e4fcSRobert Mustacchi i40e_aqc_opc_update_veb_parameters = 0x0231, 1949d26e4fcSRobert Mustacchi i40e_aqc_opc_get_veb_parameters = 0x0232, 1959d26e4fcSRobert Mustacchi 1969d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_element = 0x0243, 1979d26e4fcSRobert Mustacchi 1989d26e4fcSRobert Mustacchi i40e_aqc_opc_add_macvlan = 0x0250, 1999d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_macvlan = 0x0251, 2009d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vlan = 0x0252, 2019d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_vlan = 0x0253, 2029d26e4fcSRobert Mustacchi i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 2039d26e4fcSRobert Mustacchi i40e_aqc_opc_add_tag = 0x0255, 2049d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_tag = 0x0256, 2059d26e4fcSRobert Mustacchi i40e_aqc_opc_add_multicast_etag = 0x0257, 2069d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_multicast_etag = 0x0258, 2079d26e4fcSRobert Mustacchi i40e_aqc_opc_update_tag = 0x0259, 2089d26e4fcSRobert Mustacchi i40e_aqc_opc_add_control_packet_filter = 0x025A, 2099d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_control_packet_filter = 0x025B, 2109d26e4fcSRobert Mustacchi i40e_aqc_opc_add_cloud_filters = 0x025C, 2119d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_cloud_filters = 0x025D, 2123d75a287SRobert Mustacchi i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 213*df36e06dSRobert Mustacchi i40e_aqc_opc_replace_cloud_filters = 0x025F, 2149d26e4fcSRobert Mustacchi 2159d26e4fcSRobert Mustacchi i40e_aqc_opc_add_mirror_rule = 0x0260, 2169d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_mirror_rule = 0x0261, 2179d26e4fcSRobert Mustacchi 2189d26e4fcSRobert Mustacchi /* DCB commands */ 2199d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 2209d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_updated = 0x0302, 22193f1cac5SPaul Winder i40e_aqc_opc_set_dcb_parameters = 0x0303, 2229d26e4fcSRobert Mustacchi 2239d26e4fcSRobert Mustacchi /* TX scheduler */ 2249d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 2259d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 2269d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 2279d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_bw_config = 0x0408, 2289d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 2299d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 2309d26e4fcSRobert Mustacchi 2319d26e4fcSRobert Mustacchi i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 2329d26e4fcSRobert Mustacchi i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 2339d26e4fcSRobert Mustacchi i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 2349d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 2359d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 2369d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 2379d26e4fcSRobert Mustacchi i40e_aqc_opc_query_port_ets_config = 0x0419, 2389d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 2399d26e4fcSRobert Mustacchi i40e_aqc_opc_suspend_port_tx = 0x041B, 2409d26e4fcSRobert Mustacchi i40e_aqc_opc_resume_port_tx = 0x041C, 2419d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_partition_bw = 0x041D, 2429d26e4fcSRobert Mustacchi /* hmc */ 2439d26e4fcSRobert Mustacchi i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 2449d26e4fcSRobert Mustacchi i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 2459d26e4fcSRobert Mustacchi 2469d26e4fcSRobert Mustacchi /* phy commands*/ 2479d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_abilities = 0x0600, 2489d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_config = 0x0601, 2499d26e4fcSRobert Mustacchi i40e_aqc_opc_set_mac_config = 0x0603, 2509d26e4fcSRobert Mustacchi i40e_aqc_opc_set_link_restart_an = 0x0605, 2519d26e4fcSRobert Mustacchi i40e_aqc_opc_get_link_status = 0x0607, 2529d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_int_mask = 0x0613, 2539d26e4fcSRobert Mustacchi i40e_aqc_opc_get_local_advt_reg = 0x0614, 2549d26e4fcSRobert Mustacchi i40e_aqc_opc_set_local_advt_reg = 0x0615, 2559d26e4fcSRobert Mustacchi i40e_aqc_opc_get_partner_advt = 0x0616, 2569d26e4fcSRobert Mustacchi i40e_aqc_opc_set_lb_modes = 0x0618, 2579d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_wol_caps = 0x0621, 2589d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_debug = 0x0622, 2599d26e4fcSRobert Mustacchi i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 2603d75a287SRobert Mustacchi i40e_aqc_opc_run_phy_activity = 0x0626, 261286d309cSRobert Mustacchi i40e_aqc_opc_set_phy_register = 0x0628, 262286d309cSRobert Mustacchi i40e_aqc_opc_get_phy_register = 0x0629, 2639d26e4fcSRobert Mustacchi 2649d26e4fcSRobert Mustacchi /* NVM commands */ 2659d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_read = 0x0701, 2669d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_erase = 0x0702, 2679d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_update = 0x0703, 2689d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_read = 0x0704, 2699d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_write = 0x0705, 27093f1cac5SPaul Winder i40e_aqc_opc_nvm_progress = 0x0706, 2719d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_post_update = 0x0720, 2723d75a287SRobert Mustacchi i40e_aqc_opc_thermal_sensor = 0x0721, 2739d26e4fcSRobert Mustacchi 2749d26e4fcSRobert Mustacchi /* virtualization commands */ 2759d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_pf = 0x0801, 2769d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_vf = 0x0802, 2779d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_peer = 0x0803, 2789d26e4fcSRobert Mustacchi 2799d26e4fcSRobert Mustacchi /* alternate structure */ 2809d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write = 0x0900, 2819d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_indirect = 0x0901, 2829d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read = 0x0902, 2839d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read_indirect = 0x0903, 2849d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_done = 0x0904, 2859d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_set_mode = 0x0905, 2869d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_clear_port = 0x0906, 2879d26e4fcSRobert Mustacchi 2889d26e4fcSRobert Mustacchi /* LLDP commands */ 2899d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_get_mib = 0x0A00, 2909d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_mib = 0x0A01, 2919d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_add_tlv = 0x0A02, 2929d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_tlv = 0x0A03, 2939d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 2949d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop = 0x0A05, 2959d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_start = 0x0A06, 2969d26e4fcSRobert Mustacchi i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2979d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 2989d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 299*df36e06dSRobert Mustacchi i40e_aqc_opc_lldp_restore = 0x0A0A, 3009d26e4fcSRobert Mustacchi 3019d26e4fcSRobert Mustacchi /* Tunnel commands */ 3029d26e4fcSRobert Mustacchi i40e_aqc_opc_add_udp_tunnel = 0x0B00, 3039d26e4fcSRobert Mustacchi i40e_aqc_opc_del_udp_tunnel = 0x0B01, 3049d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_key = 0x0B02, 3059d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_lut = 0x0B03, 3069d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_key = 0x0B04, 3079d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_lut = 0x0B05, 3089d26e4fcSRobert Mustacchi 3099d26e4fcSRobert Mustacchi /* Async Events */ 3109d26e4fcSRobert Mustacchi i40e_aqc_opc_event_lan_overflow = 0x1001, 3119d26e4fcSRobert Mustacchi 3129d26e4fcSRobert Mustacchi /* OEM commands */ 3139d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_parameter_change = 0xFE00, 3149d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_device_status_change = 0xFE01, 3159d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 3169d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 3179d26e4fcSRobert Mustacchi 3189d26e4fcSRobert Mustacchi /* debug commands */ 3199d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_read_reg = 0xFF03, 3209d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_write_reg = 0xFF04, 3219d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_modify_reg = 0xFF07, 3229d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_dump_internals = 0xFF08, 3239d26e4fcSRobert Mustacchi }; 3249d26e4fcSRobert Mustacchi 3259d26e4fcSRobert Mustacchi /* command structures and indirect data structures */ 3269d26e4fcSRobert Mustacchi 3279d26e4fcSRobert Mustacchi /* Structure naming conventions: 3289d26e4fcSRobert Mustacchi * - no suffix for direct command descriptor structures 3299d26e4fcSRobert Mustacchi * - _data for indirect sent data 3309d26e4fcSRobert Mustacchi * - _resp for indirect return data (data which is both will use _data) 3319d26e4fcSRobert Mustacchi * - _completion for direct return data 3329d26e4fcSRobert Mustacchi * - _element_ for repeated elements (may also be _data or _resp) 3339d26e4fcSRobert Mustacchi * 3349d26e4fcSRobert Mustacchi * Command structures are expected to overlay the params.raw member of the basic 3359d26e4fcSRobert Mustacchi * descriptor, and as such cannot exceed 16 bytes in length. 3369d26e4fcSRobert Mustacchi */ 3379d26e4fcSRobert Mustacchi 3389d26e4fcSRobert Mustacchi /* This macro is used to generate a compilation error if a structure 3399d26e4fcSRobert Mustacchi * is not exactly the correct length. It gives a divide by zero error if the 3409d26e4fcSRobert Mustacchi * structure is not of the correct size, otherwise it creates an enum that is 3419d26e4fcSRobert Mustacchi * never used. 3429d26e4fcSRobert Mustacchi */ 3439d26e4fcSRobert Mustacchi #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 3449d26e4fcSRobert Mustacchi { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 3459d26e4fcSRobert Mustacchi 3469d26e4fcSRobert Mustacchi /* This macro is used extensively to ensure that command structures are 16 3479d26e4fcSRobert Mustacchi * bytes in length as they have to map to the raw array of that size. 3489d26e4fcSRobert Mustacchi */ 3499d26e4fcSRobert Mustacchi #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 3509d26e4fcSRobert Mustacchi 3519d26e4fcSRobert Mustacchi /* internal (0x00XX) commands */ 3529d26e4fcSRobert Mustacchi 3539d26e4fcSRobert Mustacchi /* Get version (direct 0x0001) */ 3549d26e4fcSRobert Mustacchi struct i40e_aqc_get_version { 3559d26e4fcSRobert Mustacchi __le32 rom_ver; 3569d26e4fcSRobert Mustacchi __le32 fw_build; 3579d26e4fcSRobert Mustacchi __le16 fw_major; 3589d26e4fcSRobert Mustacchi __le16 fw_minor; 3599d26e4fcSRobert Mustacchi __le16 api_major; 3609d26e4fcSRobert Mustacchi __le16 api_minor; 3619d26e4fcSRobert Mustacchi }; 3629d26e4fcSRobert Mustacchi 3639d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 3649d26e4fcSRobert Mustacchi 3659d26e4fcSRobert Mustacchi /* Send driver version (indirect 0x0002) */ 3669d26e4fcSRobert Mustacchi struct i40e_aqc_driver_version { 3679d26e4fcSRobert Mustacchi u8 driver_major_ver; 3689d26e4fcSRobert Mustacchi u8 driver_minor_ver; 3699d26e4fcSRobert Mustacchi u8 driver_build_ver; 3709d26e4fcSRobert Mustacchi u8 driver_subbuild_ver; 3719d26e4fcSRobert Mustacchi u8 reserved[4]; 3729d26e4fcSRobert Mustacchi __le32 address_high; 3739d26e4fcSRobert Mustacchi __le32 address_low; 3749d26e4fcSRobert Mustacchi }; 3759d26e4fcSRobert Mustacchi 3769d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 3779d26e4fcSRobert Mustacchi 3789d26e4fcSRobert Mustacchi /* Queue Shutdown (direct 0x0003) */ 3799d26e4fcSRobert Mustacchi struct i40e_aqc_queue_shutdown { 3809d26e4fcSRobert Mustacchi __le32 driver_unloading; 3819d26e4fcSRobert Mustacchi #define I40E_AQ_DRIVER_UNLOADING 0x1 3829d26e4fcSRobert Mustacchi u8 reserved[12]; 3839d26e4fcSRobert Mustacchi }; 3849d26e4fcSRobert Mustacchi 3859d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 3869d26e4fcSRobert Mustacchi 3879d26e4fcSRobert Mustacchi /* Set PF context (0x0004, direct) */ 3889d26e4fcSRobert Mustacchi struct i40e_aqc_set_pf_context { 3899d26e4fcSRobert Mustacchi u8 pf_id; 3909d26e4fcSRobert Mustacchi u8 reserved[15]; 3919d26e4fcSRobert Mustacchi }; 3929d26e4fcSRobert Mustacchi 3939d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 3949d26e4fcSRobert Mustacchi 3959d26e4fcSRobert Mustacchi /* Request resource ownership (direct 0x0008) 3969d26e4fcSRobert Mustacchi * Release resource ownership (direct 0x0009) 3979d26e4fcSRobert Mustacchi */ 3989d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM 1 3999d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_SDP 2 4009d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_READ 1 4019d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 4029d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 4039d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 4049d26e4fcSRobert Mustacchi 4059d26e4fcSRobert Mustacchi struct i40e_aqc_request_resource { 4069d26e4fcSRobert Mustacchi __le16 resource_id; 4079d26e4fcSRobert Mustacchi __le16 access_type; 4089d26e4fcSRobert Mustacchi __le32 timeout; 4099d26e4fcSRobert Mustacchi __le32 resource_number; 4109d26e4fcSRobert Mustacchi u8 reserved[4]; 4119d26e4fcSRobert Mustacchi }; 4129d26e4fcSRobert Mustacchi 4139d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 4149d26e4fcSRobert Mustacchi 4159d26e4fcSRobert Mustacchi /* Get function capabilities (indirect 0x000A) 4169d26e4fcSRobert Mustacchi * Get device capabilities (indirect 0x000B) 4179d26e4fcSRobert Mustacchi */ 4189d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilites { 4199d26e4fcSRobert Mustacchi u8 command_flags; 4209d26e4fcSRobert Mustacchi #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 4219d26e4fcSRobert Mustacchi u8 pf_index; 4229d26e4fcSRobert Mustacchi u8 reserved[2]; 4239d26e4fcSRobert Mustacchi __le32 count; 4249d26e4fcSRobert Mustacchi __le32 addr_high; 4259d26e4fcSRobert Mustacchi __le32 addr_low; 4269d26e4fcSRobert Mustacchi }; 4279d26e4fcSRobert Mustacchi 4289d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 4299d26e4fcSRobert Mustacchi 4309d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilities_element_resp { 4319d26e4fcSRobert Mustacchi __le16 id; 4329d26e4fcSRobert Mustacchi u8 major_rev; 4339d26e4fcSRobert Mustacchi u8 minor_rev; 4349d26e4fcSRobert Mustacchi __le32 number; 4359d26e4fcSRobert Mustacchi __le32 logical_id; 4369d26e4fcSRobert Mustacchi __le32 phys_id; 4379d26e4fcSRobert Mustacchi u8 reserved[16]; 4389d26e4fcSRobert Mustacchi }; 4399d26e4fcSRobert Mustacchi 4409d26e4fcSRobert Mustacchi /* list of caps */ 4419d26e4fcSRobert Mustacchi 4429d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 4439d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 4449d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 4459d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 4469d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 4479d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 4483d75a287SRobert Mustacchi #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 4499d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SRIOV 0x0012 4509d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF 0x0013 4519d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VMDQ 0x0014 4529d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBG 0x0015 4539d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBR 0x0016 4549d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VSI 0x0017 4559d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_DCB 0x0018 4569d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FCOE 0x0021 4579d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ISCSI 0x0022 4589d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RSS 0x0040 4599d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RXQ 0x0041 4609d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_TXQ 0x0042 4619d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MSIX 0x0043 4629d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 4639d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 4649d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_1588 0x0046 4659d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_IWARP 0x0051 4669d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_LED 0x0061 4679d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SDP 0x0062 4689d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MDIO 0x0063 4693d75a287SRobert Mustacchi #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 4703d75a287SRobert Mustacchi #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 4719d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLEX10 0x00F1 4729d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_CEM 0x00F2 4739d26e4fcSRobert Mustacchi 4749d26e4fcSRobert Mustacchi /* Set CPPM Configuration (direct 0x0103) */ 4759d26e4fcSRobert Mustacchi struct i40e_aqc_cppm_configuration { 4769d26e4fcSRobert Mustacchi __le16 command_flags; 4779d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_LTRC 0x0800 4789d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTH 0x1000 4799d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 4809d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_HPTC 0x4000 4819d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMARC 0x8000 4829d26e4fcSRobert Mustacchi __le16 ttlx; 4839d26e4fcSRobert Mustacchi __le32 dmacr; 4849d26e4fcSRobert Mustacchi __le16 dmcth; 4859d26e4fcSRobert Mustacchi u8 hptc; 4869d26e4fcSRobert Mustacchi u8 reserved; 4879d26e4fcSRobert Mustacchi __le32 pfltrc; 4889d26e4fcSRobert Mustacchi }; 4899d26e4fcSRobert Mustacchi 4909d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 4919d26e4fcSRobert Mustacchi 4929d26e4fcSRobert Mustacchi /* Set ARP Proxy command / response (indirect 0x0104) */ 4939d26e4fcSRobert Mustacchi struct i40e_aqc_arp_proxy_data { 4949d26e4fcSRobert Mustacchi __le16 command_flags; 4953d75a287SRobert Mustacchi #define I40E_AQ_ARP_INIT_IPV4 0x0800 4963d75a287SRobert Mustacchi #define I40E_AQ_ARP_UNSUP_CTL 0x1000 4973d75a287SRobert Mustacchi #define I40E_AQ_ARP_ENA 0x2000 4983d75a287SRobert Mustacchi #define I40E_AQ_ARP_ADD_IPV4 0x4000 4993d75a287SRobert Mustacchi #define I40E_AQ_ARP_DEL_IPV4 0x8000 5009d26e4fcSRobert Mustacchi __le16 table_id; 5013d75a287SRobert Mustacchi __le32 enabled_offloads; 5023d75a287SRobert Mustacchi #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 5033d75a287SRobert Mustacchi #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 5049d26e4fcSRobert Mustacchi __le32 ip_addr; 5059d26e4fcSRobert Mustacchi u8 mac_addr[6]; 5069d26e4fcSRobert Mustacchi u8 reserved[2]; 5079d26e4fcSRobert Mustacchi }; 5089d26e4fcSRobert Mustacchi 5099d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 5109d26e4fcSRobert Mustacchi 5119d26e4fcSRobert Mustacchi /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 5129d26e4fcSRobert Mustacchi struct i40e_aqc_ns_proxy_data { 5139d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_0; 5149d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_1; 5159d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_0; 5169d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_1; 5179d26e4fcSRobert Mustacchi __le16 control; 5183d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_0 0x0001 5193d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_0 0x0002 5203d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_1 0x0004 5213d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_1 0x0008 5223d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 5233d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 5243d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 5253d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 5263d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 5273d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 5283d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 5293d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 5303d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 5319d26e4fcSRobert Mustacchi u8 mac_addr_0[6]; 5329d26e4fcSRobert Mustacchi u8 mac_addr_1[6]; 5339d26e4fcSRobert Mustacchi u8 local_mac_addr[6]; 5349d26e4fcSRobert Mustacchi u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 5359d26e4fcSRobert Mustacchi u8 ipv6_addr_1[16]; 5369d26e4fcSRobert Mustacchi }; 5379d26e4fcSRobert Mustacchi 5389d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 5399d26e4fcSRobert Mustacchi 5409d26e4fcSRobert Mustacchi /* Manage LAA Command (0x0106) - obsolete */ 5419d26e4fcSRobert Mustacchi struct i40e_aqc_mng_laa { 5429d26e4fcSRobert Mustacchi __le16 command_flags; 5439d26e4fcSRobert Mustacchi #define I40E_AQ_LAA_FLAG_WR 0x8000 5449d26e4fcSRobert Mustacchi u8 reserved[2]; 5459d26e4fcSRobert Mustacchi __le32 sal; 5469d26e4fcSRobert Mustacchi __le16 sah; 5479d26e4fcSRobert Mustacchi u8 reserved2[6]; 5489d26e4fcSRobert Mustacchi }; 5499d26e4fcSRobert Mustacchi 5509d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 5519d26e4fcSRobert Mustacchi 5529d26e4fcSRobert Mustacchi /* Manage MAC Address Read Command (indirect 0x0107) */ 5539d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read { 5549d26e4fcSRobert Mustacchi __le16 command_flags; 5559d26e4fcSRobert Mustacchi #define I40E_AQC_LAN_ADDR_VALID 0x10 5569d26e4fcSRobert Mustacchi #define I40E_AQC_SAN_ADDR_VALID 0x20 5579d26e4fcSRobert Mustacchi #define I40E_AQC_PORT_ADDR_VALID 0x40 5589d26e4fcSRobert Mustacchi #define I40E_AQC_WOL_ADDR_VALID 0x80 5599d26e4fcSRobert Mustacchi #define I40E_AQC_MC_MAG_EN_VALID 0x100 5603d75a287SRobert Mustacchi #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 5613d75a287SRobert Mustacchi #define I40E_AQC_ADDR_VALID_MASK 0x3F0 5629d26e4fcSRobert Mustacchi u8 reserved[6]; 5639d26e4fcSRobert Mustacchi __le32 addr_high; 5649d26e4fcSRobert Mustacchi __le32 addr_low; 5659d26e4fcSRobert Mustacchi }; 5669d26e4fcSRobert Mustacchi 5679d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 5689d26e4fcSRobert Mustacchi 5699d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read_data { 5709d26e4fcSRobert Mustacchi u8 pf_lan_mac[6]; 5719d26e4fcSRobert Mustacchi u8 pf_san_mac[6]; 5729d26e4fcSRobert Mustacchi u8 port_mac[6]; 5739d26e4fcSRobert Mustacchi u8 pf_wol_mac[6]; 5749d26e4fcSRobert Mustacchi }; 5759d26e4fcSRobert Mustacchi 5769d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 5779d26e4fcSRobert Mustacchi 5789d26e4fcSRobert Mustacchi /* Manage MAC Address Write Command (0x0108) */ 5799d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_write { 5809d26e4fcSRobert Mustacchi __le16 command_flags; 5813d75a287SRobert Mustacchi #define I40E_AQC_MC_MAG_EN 0x0100 5823d75a287SRobert Mustacchi #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 5839d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 5849d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 5859d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_PORT 0x8000 5869d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 5879d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_MASK 0xC000 5889d26e4fcSRobert Mustacchi 5899d26e4fcSRobert Mustacchi __le16 mac_sah; 5909d26e4fcSRobert Mustacchi __le32 mac_sal; 5919d26e4fcSRobert Mustacchi u8 reserved[8]; 5929d26e4fcSRobert Mustacchi }; 5939d26e4fcSRobert Mustacchi 5949d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 5959d26e4fcSRobert Mustacchi 5969d26e4fcSRobert Mustacchi /* PXE commands (0x011x) */ 5979d26e4fcSRobert Mustacchi 5989d26e4fcSRobert Mustacchi /* Clear PXE Command and response (direct 0x0110) */ 5999d26e4fcSRobert Mustacchi struct i40e_aqc_clear_pxe { 6009d26e4fcSRobert Mustacchi u8 rx_cnt; 6019d26e4fcSRobert Mustacchi u8 reserved[15]; 6029d26e4fcSRobert Mustacchi }; 6039d26e4fcSRobert Mustacchi 6049d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 6059d26e4fcSRobert Mustacchi 6063d75a287SRobert Mustacchi /* Set WoL Filter (0x0120) */ 6073d75a287SRobert Mustacchi 6083d75a287SRobert Mustacchi struct i40e_aqc_set_wol_filter { 6093d75a287SRobert Mustacchi __le16 filter_index; 6103d75a287SRobert Mustacchi #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 6113d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 6123d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 6133d75a287SRobert Mustacchi I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 6143d75a287SRobert Mustacchi 6153d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 6163d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 6173d75a287SRobert Mustacchi I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 6183d75a287SRobert Mustacchi __le16 cmd_flags; 6193d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER 0x8000 6203d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 6213d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 6223d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 6233d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 6243d75a287SRobert Mustacchi __le16 valid_flags; 6253d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 6263d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 6273d75a287SRobert Mustacchi u8 reserved[2]; 6283d75a287SRobert Mustacchi __le32 address_high; 6293d75a287SRobert Mustacchi __le32 address_low; 6303d75a287SRobert Mustacchi }; 6313d75a287SRobert Mustacchi 6323d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 6333d75a287SRobert Mustacchi 6343d75a287SRobert Mustacchi struct i40e_aqc_set_wol_filter_data { 6353d75a287SRobert Mustacchi u8 filter[128]; 6363d75a287SRobert Mustacchi u8 mask[16]; 6373d75a287SRobert Mustacchi }; 6383d75a287SRobert Mustacchi 6393d75a287SRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 6403d75a287SRobert Mustacchi 6413d75a287SRobert Mustacchi /* Get Wake Reason (0x0121) */ 6423d75a287SRobert Mustacchi 6433d75a287SRobert Mustacchi struct i40e_aqc_get_wake_reason_completion { 6443d75a287SRobert Mustacchi u8 reserved_1[2]; 6453d75a287SRobert Mustacchi __le16 wake_reason; 6463d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 6473d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 6483d75a287SRobert Mustacchi I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 6493d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 6503d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 6513d75a287SRobert Mustacchi I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 6523d75a287SRobert Mustacchi u8 reserved_2[12]; 6533d75a287SRobert Mustacchi }; 6543d75a287SRobert Mustacchi 6553d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 6563d75a287SRobert Mustacchi 6579d26e4fcSRobert Mustacchi /* Switch configuration commands (0x02xx) */ 6589d26e4fcSRobert Mustacchi 6599d26e4fcSRobert Mustacchi /* Used by many indirect commands that only pass an seid and a buffer in the 6609d26e4fcSRobert Mustacchi * command 6619d26e4fcSRobert Mustacchi */ 6629d26e4fcSRobert Mustacchi struct i40e_aqc_switch_seid { 6639d26e4fcSRobert Mustacchi __le16 seid; 6649d26e4fcSRobert Mustacchi u8 reserved[6]; 6659d26e4fcSRobert Mustacchi __le32 addr_high; 6669d26e4fcSRobert Mustacchi __le32 addr_low; 6679d26e4fcSRobert Mustacchi }; 6689d26e4fcSRobert Mustacchi 6699d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 6709d26e4fcSRobert Mustacchi 6719d26e4fcSRobert Mustacchi /* Get Switch Configuration command (indirect 0x0200) 6729d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 6739d26e4fcSRobert Mustacchi */ 6749d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp { 6759d26e4fcSRobert Mustacchi __le16 num_reported; 6769d26e4fcSRobert Mustacchi __le16 num_total; 6779d26e4fcSRobert Mustacchi u8 reserved[12]; 6789d26e4fcSRobert Mustacchi }; 6799d26e4fcSRobert Mustacchi 6809d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 6819d26e4fcSRobert Mustacchi 6829d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp { 6839d26e4fcSRobert Mustacchi u8 element_type; 6849d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_MAC 1 6859d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PF 2 6869d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VF 3 6879d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_EMP 4 6889d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_BMC 5 6899d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PV 16 6909d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VEB 17 6919d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PA 18 6929d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VSI 19 6939d26e4fcSRobert Mustacchi u8 revision; 6949d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_REV_1 1 6959d26e4fcSRobert Mustacchi __le16 seid; 6969d26e4fcSRobert Mustacchi __le16 uplink_seid; 6979d26e4fcSRobert Mustacchi __le16 downlink_seid; 6989d26e4fcSRobert Mustacchi u8 reserved[3]; 6999d26e4fcSRobert Mustacchi u8 connection_type; 7009d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_REGULAR 0x1 7019d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 7029d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_CASCADED 0x3 7039d26e4fcSRobert Mustacchi __le16 scheduler_id; 7049d26e4fcSRobert Mustacchi __le16 element_info; 7059d26e4fcSRobert Mustacchi }; 7069d26e4fcSRobert Mustacchi 7079d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 7089d26e4fcSRobert Mustacchi 7099d26e4fcSRobert Mustacchi /* Get Switch Configuration (indirect 0x0200) 7109d26e4fcSRobert Mustacchi * an array of elements are returned in the response buffer 7119d26e4fcSRobert Mustacchi * the first in the array is the header, remainder are elements 7129d26e4fcSRobert Mustacchi */ 7139d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_resp { 7149d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp header; 7159d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp element[1]; 7169d26e4fcSRobert Mustacchi }; 7179d26e4fcSRobert Mustacchi 7189d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 7199d26e4fcSRobert Mustacchi 7209d26e4fcSRobert Mustacchi /* Add Statistics (direct 0x0201) 7219d26e4fcSRobert Mustacchi * Remove Statistics (direct 0x0202) 7229d26e4fcSRobert Mustacchi */ 7239d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_statistics { 7249d26e4fcSRobert Mustacchi __le16 seid; 7259d26e4fcSRobert Mustacchi __le16 vlan; 7269d26e4fcSRobert Mustacchi __le16 stat_index; 7279d26e4fcSRobert Mustacchi u8 reserved[10]; 7289d26e4fcSRobert Mustacchi }; 7299d26e4fcSRobert Mustacchi 7309d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 7319d26e4fcSRobert Mustacchi 7329d26e4fcSRobert Mustacchi /* Set Port Parameters command (direct 0x0203) */ 7339d26e4fcSRobert Mustacchi struct i40e_aqc_set_port_parameters { 7349d26e4fcSRobert Mustacchi __le16 command_flags; 7359d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 7369d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 7379d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 7389d26e4fcSRobert Mustacchi __le16 bad_frame_vsi; 7393d75a287SRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 7403d75a287SRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 7419d26e4fcSRobert Mustacchi __le16 default_seid; /* reserved for command */ 7429d26e4fcSRobert Mustacchi u8 reserved[10]; 7439d26e4fcSRobert Mustacchi }; 7449d26e4fcSRobert Mustacchi 7459d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 7469d26e4fcSRobert Mustacchi 7479d26e4fcSRobert Mustacchi /* Get Switch Resource Allocation (indirect 0x0204) */ 7489d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_resource_alloc { 7499d26e4fcSRobert Mustacchi u8 num_entries; /* reserved for command */ 7509d26e4fcSRobert Mustacchi u8 reserved[7]; 7519d26e4fcSRobert Mustacchi __le32 addr_high; 7529d26e4fcSRobert Mustacchi __le32 addr_low; 7539d26e4fcSRobert Mustacchi }; 7549d26e4fcSRobert Mustacchi 7559d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 7569d26e4fcSRobert Mustacchi 7579d26e4fcSRobert Mustacchi /* expect an array of these structs in the response buffer */ 7589d26e4fcSRobert Mustacchi struct i40e_aqc_switch_resource_alloc_element_resp { 7599d26e4fcSRobert Mustacchi u8 resource_type; 7609d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 7619d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 7629d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 7639d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 7649d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 7659d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 7669d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 7679d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 7689d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 7699d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 7709d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 7719d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 7729d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 7739d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 7749d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 7759d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 7769d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 7779d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 7789d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 7799d26e4fcSRobert Mustacchi u8 reserved1; 7809d26e4fcSRobert Mustacchi __le16 guaranteed; 7819d26e4fcSRobert Mustacchi __le16 total; 7829d26e4fcSRobert Mustacchi __le16 used; 7839d26e4fcSRobert Mustacchi __le16 total_unalloced; 7849d26e4fcSRobert Mustacchi u8 reserved2[6]; 7859d26e4fcSRobert Mustacchi }; 7869d26e4fcSRobert Mustacchi 7879d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 7889d26e4fcSRobert Mustacchi 7893d75a287SRobert Mustacchi /* Set Switch Configuration (direct 0x0205) */ 7903d75a287SRobert Mustacchi struct i40e_aqc_set_switch_config { 7913d75a287SRobert Mustacchi __le16 flags; 7923d75a287SRobert Mustacchi /* flags used for both fields below */ 7933d75a287SRobert Mustacchi #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 7943d75a287SRobert Mustacchi #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 79593f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 7963d75a287SRobert Mustacchi __le16 valid_flags; 79793f1cac5SPaul Winder /* The ethertype in switch_tag is dropped on ingress and used 79893f1cac5SPaul Winder * internally by the switch. Set this to zero for the default 79993f1cac5SPaul Winder * of 0x88a8 (802.1ad). Should be zero for firmware API 80093f1cac5SPaul Winder * versions lower than 1.7. 80193f1cac5SPaul Winder */ 80293f1cac5SPaul Winder __le16 switch_tag; 80393f1cac5SPaul Winder /* The ethertypes in first_tag and second_tag are used to 80493f1cac5SPaul Winder * match the outer and inner VLAN tags (respectively) when HW 80593f1cac5SPaul Winder * double VLAN tagging is enabled via the set port parameters 80693f1cac5SPaul Winder * AQ command. Otherwise these are both ignored. Set them to 80793f1cac5SPaul Winder * zero for their defaults of 0x8100 (802.1Q). Should be zero 80893f1cac5SPaul Winder * for firmware API versions lower than 1.7. 80993f1cac5SPaul Winder */ 81093f1cac5SPaul Winder __le16 first_tag; 81193f1cac5SPaul Winder __le16 second_tag; 81293f1cac5SPaul Winder /* Next byte is split into following: 81393f1cac5SPaul Winder * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 81493f1cac5SPaul Winder * Bit 6 : 0 : Destination Port, 1: source port 81593f1cac5SPaul Winder * Bit 5..4 : L4 type 81693f1cac5SPaul Winder * 0: rsvd 81793f1cac5SPaul Winder * 1: TCP 81893f1cac5SPaul Winder * 2: UDP 81993f1cac5SPaul Winder * 3: Both TCP and UDP 82093f1cac5SPaul Winder * Bits 3:0 Mode 82193f1cac5SPaul Winder * 0: default mode 82293f1cac5SPaul Winder * 1: L4 port only mode 82393f1cac5SPaul Winder * 2: non-tunneled mode 82493f1cac5SPaul Winder * 3: tunneled mode 82593f1cac5SPaul Winder */ 82693f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 82793f1cac5SPaul Winder 82893f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 82993f1cac5SPaul Winder 83093f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 83193f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 83293f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 83393f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 83493f1cac5SPaul Winder 83593f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 83693f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 83793f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 83893f1cac5SPaul Winder #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 83993f1cac5SPaul Winder u8 mode; 84093f1cac5SPaul Winder u8 rsvd5[5]; 8413d75a287SRobert Mustacchi }; 8423d75a287SRobert Mustacchi 8433d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 8443d75a287SRobert Mustacchi 845396505afSPaul Winder /* Read Receive control registers (direct 0x0206) 846396505afSPaul Winder * Write Receive control registers (direct 0x0207) 847396505afSPaul Winder * used for accessing Rx control registers that can be 848396505afSPaul Winder * slow and need special handling when under high Rx load 849396505afSPaul Winder */ 850396505afSPaul Winder struct i40e_aqc_rx_ctl_reg_read_write { 851396505afSPaul Winder __le32 reserved1; 852396505afSPaul Winder __le32 address; 853396505afSPaul Winder __le32 reserved2; 854396505afSPaul Winder __le32 value; 855396505afSPaul Winder }; 856396505afSPaul Winder 857396505afSPaul Winder I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 858396505afSPaul Winder 8599d26e4fcSRobert Mustacchi /* Add VSI (indirect 0x0210) 8609d26e4fcSRobert Mustacchi * this indirect command uses struct i40e_aqc_vsi_properties_data 8619d26e4fcSRobert Mustacchi * as the indirect buffer (128 bytes) 8629d26e4fcSRobert Mustacchi * 8639d26e4fcSRobert Mustacchi * Update VSI (indirect 0x211) 8649d26e4fcSRobert Mustacchi * uses the same data structure as Add VSI 8659d26e4fcSRobert Mustacchi * 8669d26e4fcSRobert Mustacchi * Get VSI (indirect 0x0212) 8679d26e4fcSRobert Mustacchi * uses the same completion and data structure as Add VSI 8689d26e4fcSRobert Mustacchi */ 8699d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi { 8709d26e4fcSRobert Mustacchi __le16 uplink_seid; 8719d26e4fcSRobert Mustacchi u8 connection_type; 8729d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 8739d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 8749d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 8759d26e4fcSRobert Mustacchi u8 reserved1; 8769d26e4fcSRobert Mustacchi u8 vf_id; 8779d26e4fcSRobert Mustacchi u8 reserved2; 8789d26e4fcSRobert Mustacchi __le16 vsi_flags; 8799d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_SHIFT 0x0 8809d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 8819d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VF 0x0 8829d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 8839d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_PF 0x2 8849d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 8859d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 8869d26e4fcSRobert Mustacchi __le32 addr_high; 8879d26e4fcSRobert Mustacchi __le32 addr_low; 8889d26e4fcSRobert Mustacchi }; 8899d26e4fcSRobert Mustacchi 8909d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 8919d26e4fcSRobert Mustacchi 8929d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi_completion { 8939d26e4fcSRobert Mustacchi __le16 seid; 8949d26e4fcSRobert Mustacchi __le16 vsi_number; 8959d26e4fcSRobert Mustacchi __le16 vsi_used; 8969d26e4fcSRobert Mustacchi __le16 vsi_free; 8979d26e4fcSRobert Mustacchi __le32 addr_high; 8989d26e4fcSRobert Mustacchi __le32 addr_low; 8999d26e4fcSRobert Mustacchi }; 9009d26e4fcSRobert Mustacchi 9019d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 9029d26e4fcSRobert Mustacchi 9039d26e4fcSRobert Mustacchi struct i40e_aqc_vsi_properties_data { 9049d26e4fcSRobert Mustacchi /* first 96 byte are written by SW */ 9059d26e4fcSRobert Mustacchi __le16 valid_sections; 9069d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 9079d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 9089d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 9099d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 9109d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 9119d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 9129d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 9139d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 9149d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 9159d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 9169d26e4fcSRobert Mustacchi /* switch section */ 9179d26e4fcSRobert Mustacchi __le16 switch_id; /* 12bit id combined with flags below */ 9189d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 9199d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 9209d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 9219d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 9229d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 9239d26e4fcSRobert Mustacchi u8 sw_reserved[2]; 9249d26e4fcSRobert Mustacchi /* security section */ 9259d26e4fcSRobert Mustacchi u8 sec_flags; 9269d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 9279d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 9289d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 9299d26e4fcSRobert Mustacchi u8 sec_reserved; 9309d26e4fcSRobert Mustacchi /* VLAN section */ 9319d26e4fcSRobert Mustacchi __le16 pvid; /* VLANS include priority bits */ 9329d26e4fcSRobert Mustacchi __le16 fcoe_pvid; 9339d26e4fcSRobert Mustacchi u8 port_vlan_flags; 9349d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 9359d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 9369d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_MODE_SHIFT) 9379d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 9389d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 9399d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 9409d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 9419d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 9429d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 9439d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 9449d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 9459d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 9469d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 9479d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 9489d26e4fcSRobert Mustacchi u8 pvlan_reserved[3]; 9499d26e4fcSRobert Mustacchi /* ingress egress up sections */ 9509d26e4fcSRobert Mustacchi __le32 ingress_table; /* bitmap, 3 bits per up */ 9519d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 9529d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 9539d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 9549d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 9559d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 9569d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 9579d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 9589d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 9599d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 9609d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 9619d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 9629d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 9639d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 9649d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 9659d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 9669d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 9679d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 9689d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 9699d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 9709d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 9719d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 9729d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 9739d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 9749d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 9759d26e4fcSRobert Mustacchi __le32 egress_table; /* same defines as for ingress table */ 9769d26e4fcSRobert Mustacchi /* cascaded PV section */ 9779d26e4fcSRobert Mustacchi __le16 cas_pv_tag; 9789d26e4fcSRobert Mustacchi u8 cas_pv_flags; 9799d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 9809d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 9819d26e4fcSRobert Mustacchi I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 9829d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 9839d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 9849d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 9859d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 9869d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 9879d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 9889d26e4fcSRobert Mustacchi u8 cas_pv_reserved; 9899d26e4fcSRobert Mustacchi /* queue mapping section */ 9909d26e4fcSRobert Mustacchi __le16 mapping_flags; 9919d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 9929d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 9939d26e4fcSRobert Mustacchi __le16 queue_mapping[16]; 9949d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 9959d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 9969d26e4fcSRobert Mustacchi __le16 tc_mapping[8]; 9979d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 9989d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 9999d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 10009d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 10019d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 10029d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 10039d26e4fcSRobert Mustacchi /* queueing option section */ 10049d26e4fcSRobert Mustacchi u8 queueing_opt_flags; 10059d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 10069d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 10079d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 10089d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 10099d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 10109d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 10119d26e4fcSRobert Mustacchi u8 queueing_opt_reserved[3]; 10129d26e4fcSRobert Mustacchi /* scheduler section */ 10139d26e4fcSRobert Mustacchi u8 up_enable_bits; 10149d26e4fcSRobert Mustacchi u8 sched_reserved; 10159d26e4fcSRobert Mustacchi /* outer up section */ 10163d75a287SRobert Mustacchi __le32 outer_up_table; /* same structure and defines as ingress tbl */ 10179d26e4fcSRobert Mustacchi u8 cmd_reserved[8]; 10189d26e4fcSRobert Mustacchi /* last 32 bytes are written by FW */ 10199d26e4fcSRobert Mustacchi __le16 qs_handle[8]; 10209d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 10219d26e4fcSRobert Mustacchi __le16 stat_counter_idx; 10229d26e4fcSRobert Mustacchi __le16 sched_id; 10239d26e4fcSRobert Mustacchi u8 resp_reserved[12]; 10249d26e4fcSRobert Mustacchi }; 10259d26e4fcSRobert Mustacchi 10269d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 10279d26e4fcSRobert Mustacchi 10289d26e4fcSRobert Mustacchi /* Add Port Virtualizer (direct 0x0220) 10299d26e4fcSRobert Mustacchi * also used for update PV (direct 0x0221) but only flags are used 10309d26e4fcSRobert Mustacchi * (IS_CTRL_PORT only works on add PV) 10319d26e4fcSRobert Mustacchi */ 10329d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv { 10339d26e4fcSRobert Mustacchi __le16 command_flags; 10349d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 10359d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 10369d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 10379d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 10389d26e4fcSRobert Mustacchi __le16 uplink_seid; 10399d26e4fcSRobert Mustacchi __le16 connected_seid; 10409d26e4fcSRobert Mustacchi u8 reserved[10]; 10419d26e4fcSRobert Mustacchi }; 10429d26e4fcSRobert Mustacchi 10439d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 10449d26e4fcSRobert Mustacchi 10459d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv_completion { 10469d26e4fcSRobert Mustacchi /* reserved for update; for add also encodes error if rc == ENOSPC */ 10479d26e4fcSRobert Mustacchi __le16 pv_seid; 10489d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 10499d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 10509d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 10519d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 10529d26e4fcSRobert Mustacchi u8 reserved[14]; 10539d26e4fcSRobert Mustacchi }; 10549d26e4fcSRobert Mustacchi 10559d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 10569d26e4fcSRobert Mustacchi 10579d26e4fcSRobert Mustacchi /* Get PV Params (direct 0x0222) 10589d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 10599d26e4fcSRobert Mustacchi */ 10609d26e4fcSRobert Mustacchi 10619d26e4fcSRobert Mustacchi struct i40e_aqc_get_pv_params_completion { 10629d26e4fcSRobert Mustacchi __le16 seid; 10639d26e4fcSRobert Mustacchi __le16 default_stag; 10649d26e4fcSRobert Mustacchi __le16 pv_flags; /* same flags as add_pv */ 10659d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_PV_TYPE 0x1 10669d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 10679d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 10689d26e4fcSRobert Mustacchi u8 reserved[8]; 10699d26e4fcSRobert Mustacchi __le16 default_port_seid; 10709d26e4fcSRobert Mustacchi }; 10719d26e4fcSRobert Mustacchi 10729d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 10739d26e4fcSRobert Mustacchi 10749d26e4fcSRobert Mustacchi /* Add VEB (direct 0x0230) */ 10759d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb { 10769d26e4fcSRobert Mustacchi __le16 uplink_seid; 10779d26e4fcSRobert Mustacchi __le16 downlink_seid; 10789d26e4fcSRobert Mustacchi __le16 veb_flags; 10799d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_FLOATING 0x1 10809d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 10819d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 10829d26e4fcSRobert Mustacchi I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 10839d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 10849d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 10853d75a287SRobert Mustacchi #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 10863d75a287SRobert Mustacchi #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 10879d26e4fcSRobert Mustacchi u8 enable_tcs; 10889d26e4fcSRobert Mustacchi u8 reserved[9]; 10899d26e4fcSRobert Mustacchi }; 10909d26e4fcSRobert Mustacchi 10919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 10929d26e4fcSRobert Mustacchi 10939d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb_completion { 10949d26e4fcSRobert Mustacchi u8 reserved[6]; 10959d26e4fcSRobert Mustacchi __le16 switch_seid; 10969d26e4fcSRobert Mustacchi /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 10979d26e4fcSRobert Mustacchi __le16 veb_seid; 10989d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 10999d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 11009d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 11019d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 11029d26e4fcSRobert Mustacchi __le16 statistic_index; 11039d26e4fcSRobert Mustacchi __le16 vebs_used; 11049d26e4fcSRobert Mustacchi __le16 vebs_free; 11059d26e4fcSRobert Mustacchi }; 11069d26e4fcSRobert Mustacchi 11079d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 11089d26e4fcSRobert Mustacchi 11099d26e4fcSRobert Mustacchi /* Get VEB Parameters (direct 0x0232) 11109d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 11119d26e4fcSRobert Mustacchi */ 11129d26e4fcSRobert Mustacchi struct i40e_aqc_get_veb_parameters_completion { 11139d26e4fcSRobert Mustacchi __le16 seid; 11149d26e4fcSRobert Mustacchi __le16 switch_id; 11159d26e4fcSRobert Mustacchi __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 11169d26e4fcSRobert Mustacchi __le16 statistic_index; 11179d26e4fcSRobert Mustacchi __le16 vebs_used; 11189d26e4fcSRobert Mustacchi __le16 vebs_free; 11199d26e4fcSRobert Mustacchi u8 reserved[4]; 11209d26e4fcSRobert Mustacchi }; 11219d26e4fcSRobert Mustacchi 11229d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 11239d26e4fcSRobert Mustacchi 11249d26e4fcSRobert Mustacchi /* Delete Element (direct 0x0243) 11259d26e4fcSRobert Mustacchi * uses the generic i40e_aqc_switch_seid 11269d26e4fcSRobert Mustacchi */ 11279d26e4fcSRobert Mustacchi 11289d26e4fcSRobert Mustacchi /* Add MAC-VLAN (indirect 0x0250) */ 11299d26e4fcSRobert Mustacchi 11309d26e4fcSRobert Mustacchi /* used for the command for most vlan commands */ 11319d26e4fcSRobert Mustacchi struct i40e_aqc_macvlan { 11329d26e4fcSRobert Mustacchi __le16 num_addresses; 11339d26e4fcSRobert Mustacchi __le16 seid[3]; 11349d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 11359d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 11369d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 11379d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 11389d26e4fcSRobert Mustacchi __le32 addr_high; 11399d26e4fcSRobert Mustacchi __le32 addr_low; 11409d26e4fcSRobert Mustacchi }; 11419d26e4fcSRobert Mustacchi 11429d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 11439d26e4fcSRobert Mustacchi 11449d26e4fcSRobert Mustacchi /* indirect data for command and response */ 11459d26e4fcSRobert Mustacchi struct i40e_aqc_add_macvlan_element_data { 11469d26e4fcSRobert Mustacchi u8 mac_addr[6]; 11479d26e4fcSRobert Mustacchi __le16 vlan_tag; 11489d26e4fcSRobert Mustacchi __le16 flags; 11499d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 11509d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 11519d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 11529d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 11533d75a287SRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 11549d26e4fcSRobert Mustacchi __le16 queue_number; 11559d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 11569d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 11579d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 11589d26e4fcSRobert Mustacchi /* response section */ 11599d26e4fcSRobert Mustacchi u8 match_method; 11609d26e4fcSRobert Mustacchi #define I40E_AQC_MM_PERFECT_MATCH 0x01 11619d26e4fcSRobert Mustacchi #define I40E_AQC_MM_HASH_MATCH 0x02 11629d26e4fcSRobert Mustacchi #define I40E_AQC_MM_ERR_NO_RES 0xFF 11639d26e4fcSRobert Mustacchi u8 reserved1[3]; 11649d26e4fcSRobert Mustacchi }; 11659d26e4fcSRobert Mustacchi 11669d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_macvlan_completion { 11679d26e4fcSRobert Mustacchi __le16 perfect_mac_used; 11689d26e4fcSRobert Mustacchi __le16 perfect_mac_free; 11699d26e4fcSRobert Mustacchi __le16 unicast_hash_free; 11709d26e4fcSRobert Mustacchi __le16 multicast_hash_free; 11719d26e4fcSRobert Mustacchi __le32 addr_high; 11729d26e4fcSRobert Mustacchi __le32 addr_low; 11739d26e4fcSRobert Mustacchi }; 11749d26e4fcSRobert Mustacchi 11759d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 11769d26e4fcSRobert Mustacchi 11779d26e4fcSRobert Mustacchi /* Remove MAC-VLAN (indirect 0x0251) 11789d26e4fcSRobert Mustacchi * uses i40e_aqc_macvlan for the descriptor 11799d26e4fcSRobert Mustacchi * data points to an array of num_addresses of elements 11809d26e4fcSRobert Mustacchi */ 11819d26e4fcSRobert Mustacchi 11829d26e4fcSRobert Mustacchi struct i40e_aqc_remove_macvlan_element_data { 11839d26e4fcSRobert Mustacchi u8 mac_addr[6]; 11849d26e4fcSRobert Mustacchi __le16 vlan_tag; 11859d26e4fcSRobert Mustacchi u8 flags; 11869d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 11879d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 11889d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 11899d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 11909d26e4fcSRobert Mustacchi u8 reserved[3]; 11919d26e4fcSRobert Mustacchi /* reply section */ 11929d26e4fcSRobert Mustacchi u8 error_code; 11939d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 11949d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 11959d26e4fcSRobert Mustacchi u8 reply_reserved[3]; 11969d26e4fcSRobert Mustacchi }; 11979d26e4fcSRobert Mustacchi 11989d26e4fcSRobert Mustacchi /* Add VLAN (indirect 0x0252) 11999d26e4fcSRobert Mustacchi * Remove VLAN (indirect 0x0253) 12009d26e4fcSRobert Mustacchi * use the generic i40e_aqc_macvlan for the command 12019d26e4fcSRobert Mustacchi */ 12029d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_element_data { 12039d26e4fcSRobert Mustacchi __le16 vlan_tag; 12049d26e4fcSRobert Mustacchi u8 vlan_flags; 12059d26e4fcSRobert Mustacchi /* flags for add VLAN */ 12069d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_LOCAL 0x1 12079d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 12089d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 12099d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 12109d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 12119d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 12129d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_SHIFT 3 12139d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 12149d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 12159d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 12169d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 12179d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 12189d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 12199d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_ALL 0x1 12209d26e4fcSRobert Mustacchi u8 reserved; 12219d26e4fcSRobert Mustacchi u8 result; 12229d26e4fcSRobert Mustacchi /* flags for add VLAN */ 12239d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 12249d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 12259d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 12269d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 12279d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 12289d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 12299d26e4fcSRobert Mustacchi u8 reserved1[3]; 12309d26e4fcSRobert Mustacchi }; 12319d26e4fcSRobert Mustacchi 12329d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_completion { 12339d26e4fcSRobert Mustacchi u8 reserved[4]; 12349d26e4fcSRobert Mustacchi __le16 vlans_used; 12359d26e4fcSRobert Mustacchi __le16 vlans_free; 12369d26e4fcSRobert Mustacchi __le32 addr_high; 12379d26e4fcSRobert Mustacchi __le32 addr_low; 12389d26e4fcSRobert Mustacchi }; 12399d26e4fcSRobert Mustacchi 12409d26e4fcSRobert Mustacchi /* Set VSI Promiscuous Modes (direct 0x0254) */ 12419d26e4fcSRobert Mustacchi struct i40e_aqc_set_vsi_promiscuous_modes { 12429d26e4fcSRobert Mustacchi __le16 promiscuous_flags; 12439d26e4fcSRobert Mustacchi __le16 valid_flags; 12449d26e4fcSRobert Mustacchi /* flags used for both fields above */ 12459d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 12469d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 12479d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 12489d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_DEFAULT 0x08 12499d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 12503d75a287SRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 12519d26e4fcSRobert Mustacchi __le16 seid; 12529d26e4fcSRobert Mustacchi #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 12539d26e4fcSRobert Mustacchi __le16 vlan_tag; 12549d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 12559d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 12569d26e4fcSRobert Mustacchi u8 reserved[8]; 12579d26e4fcSRobert Mustacchi }; 12589d26e4fcSRobert Mustacchi 12599d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 12609d26e4fcSRobert Mustacchi 12619d26e4fcSRobert Mustacchi /* Add S/E-tag command (direct 0x0255) 12629d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 12639d26e4fcSRobert Mustacchi */ 12649d26e4fcSRobert Mustacchi struct i40e_aqc_add_tag { 12659d26e4fcSRobert Mustacchi __le16 flags; 12669d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 12679d26e4fcSRobert Mustacchi __le16 seid; 12689d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 12699d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 12709d26e4fcSRobert Mustacchi I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 12719d26e4fcSRobert Mustacchi __le16 tag; 12729d26e4fcSRobert Mustacchi __le16 queue_number; 12739d26e4fcSRobert Mustacchi u8 reserved[8]; 12749d26e4fcSRobert Mustacchi }; 12759d26e4fcSRobert Mustacchi 12769d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 12779d26e4fcSRobert Mustacchi 12789d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_tag_completion { 12799d26e4fcSRobert Mustacchi u8 reserved[12]; 12809d26e4fcSRobert Mustacchi __le16 tags_used; 12819d26e4fcSRobert Mustacchi __le16 tags_free; 12829d26e4fcSRobert Mustacchi }; 12839d26e4fcSRobert Mustacchi 12849d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 12859d26e4fcSRobert Mustacchi 12869d26e4fcSRobert Mustacchi /* Remove S/E-tag command (direct 0x0256) 12879d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 12889d26e4fcSRobert Mustacchi */ 12899d26e4fcSRobert Mustacchi struct i40e_aqc_remove_tag { 12909d26e4fcSRobert Mustacchi __le16 seid; 12919d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 12929d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 12939d26e4fcSRobert Mustacchi I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 12949d26e4fcSRobert Mustacchi __le16 tag; 12959d26e4fcSRobert Mustacchi u8 reserved[12]; 12969d26e4fcSRobert Mustacchi }; 12979d26e4fcSRobert Mustacchi 12989d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 12999d26e4fcSRobert Mustacchi 13009d26e4fcSRobert Mustacchi /* Add multicast E-Tag (direct 0x0257) 13019d26e4fcSRobert Mustacchi * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 13029d26e4fcSRobert Mustacchi * and no external data 13039d26e4fcSRobert Mustacchi */ 13049d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag { 13059d26e4fcSRobert Mustacchi __le16 pv_seid; 13069d26e4fcSRobert Mustacchi __le16 etag; 13079d26e4fcSRobert Mustacchi u8 num_unicast_etags; 13089d26e4fcSRobert Mustacchi u8 reserved[3]; 13099d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte s-tags */ 13109d26e4fcSRobert Mustacchi __le32 addr_low; 13119d26e4fcSRobert Mustacchi }; 13129d26e4fcSRobert Mustacchi 13139d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 13149d26e4fcSRobert Mustacchi 13159d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag_completion { 13169d26e4fcSRobert Mustacchi u8 reserved[4]; 13179d26e4fcSRobert Mustacchi __le16 mcast_etags_used; 13189d26e4fcSRobert Mustacchi __le16 mcast_etags_free; 13199d26e4fcSRobert Mustacchi __le32 addr_high; 13209d26e4fcSRobert Mustacchi __le32 addr_low; 13219d26e4fcSRobert Mustacchi 13229d26e4fcSRobert Mustacchi }; 13239d26e4fcSRobert Mustacchi 13249d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 13259d26e4fcSRobert Mustacchi 13269d26e4fcSRobert Mustacchi /* Update S/E-Tag (direct 0x0259) */ 13279d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag { 13289d26e4fcSRobert Mustacchi __le16 seid; 13299d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 13309d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 13319d26e4fcSRobert Mustacchi I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 13329d26e4fcSRobert Mustacchi __le16 old_tag; 13339d26e4fcSRobert Mustacchi __le16 new_tag; 13349d26e4fcSRobert Mustacchi u8 reserved[10]; 13359d26e4fcSRobert Mustacchi }; 13369d26e4fcSRobert Mustacchi 13379d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 13389d26e4fcSRobert Mustacchi 13399d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag_completion { 13409d26e4fcSRobert Mustacchi u8 reserved[12]; 13419d26e4fcSRobert Mustacchi __le16 tags_used; 13429d26e4fcSRobert Mustacchi __le16 tags_free; 13439d26e4fcSRobert Mustacchi }; 13449d26e4fcSRobert Mustacchi 13459d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 13469d26e4fcSRobert Mustacchi 13479d26e4fcSRobert Mustacchi /* Add Control Packet filter (direct 0x025A) 13489d26e4fcSRobert Mustacchi * Remove Control Packet filter (direct 0x025B) 13499d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_oveb_cloud, 13509d26e4fcSRobert Mustacchi * and the generic direct completion structure 13519d26e4fcSRobert Mustacchi */ 13529d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter { 13539d26e4fcSRobert Mustacchi u8 mac[6]; 13549d26e4fcSRobert Mustacchi __le16 etype; 13559d26e4fcSRobert Mustacchi __le16 flags; 13569d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 13579d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 13589d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 13599d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 13609d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 13619d26e4fcSRobert Mustacchi __le16 seid; 13629d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 13639d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 13649d26e4fcSRobert Mustacchi I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 13659d26e4fcSRobert Mustacchi __le16 queue; 13669d26e4fcSRobert Mustacchi u8 reserved[2]; 13679d26e4fcSRobert Mustacchi }; 13689d26e4fcSRobert Mustacchi 13699d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 13709d26e4fcSRobert Mustacchi 13719d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter_completion { 13729d26e4fcSRobert Mustacchi __le16 mac_etype_used; 13739d26e4fcSRobert Mustacchi __le16 etype_used; 13749d26e4fcSRobert Mustacchi __le16 mac_etype_free; 13759d26e4fcSRobert Mustacchi __le16 etype_free; 13769d26e4fcSRobert Mustacchi u8 reserved[8]; 13779d26e4fcSRobert Mustacchi }; 13789d26e4fcSRobert Mustacchi 13799d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 13809d26e4fcSRobert Mustacchi 13819d26e4fcSRobert Mustacchi /* Add Cloud filters (indirect 0x025C) 13829d26e4fcSRobert Mustacchi * Remove Cloud filters (indirect 0x025D) 13839d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_remove_cloud_filters, 13849d26e4fcSRobert Mustacchi * and the generic indirect completion structure 13859d26e4fcSRobert Mustacchi */ 13869d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters { 13879d26e4fcSRobert Mustacchi u8 num_filters; 13889d26e4fcSRobert Mustacchi u8 reserved; 13899d26e4fcSRobert Mustacchi __le16 seid; 13909d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 13919d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 13929d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1393*df36e06dSRobert Mustacchi u8 big_buffer_flag; 1394*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1 1395*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1396*df36e06dSRobert Mustacchi u8 reserved2[3]; 13979d26e4fcSRobert Mustacchi __le32 addr_high; 13989d26e4fcSRobert Mustacchi __le32 addr_low; 13999d26e4fcSRobert Mustacchi }; 14009d26e4fcSRobert Mustacchi 14019d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 14029d26e4fcSRobert Mustacchi 1403*df36e06dSRobert Mustacchi struct i40e_aqc_cloud_filters_element_data { 14049d26e4fcSRobert Mustacchi u8 outer_mac[6]; 14059d26e4fcSRobert Mustacchi u8 inner_mac[6]; 14069d26e4fcSRobert Mustacchi __le16 inner_vlan; 14079d26e4fcSRobert Mustacchi union { 14089d26e4fcSRobert Mustacchi struct { 14099d26e4fcSRobert Mustacchi u8 reserved[12]; 14109d26e4fcSRobert Mustacchi u8 data[4]; 14119d26e4fcSRobert Mustacchi } v4; 14129d26e4fcSRobert Mustacchi struct { 14139d26e4fcSRobert Mustacchi u8 data[16]; 14149d26e4fcSRobert Mustacchi } v6; 1415*df36e06dSRobert Mustacchi struct { 1416*df36e06dSRobert Mustacchi __le16 data[8]; 1417*df36e06dSRobert Mustacchi } raw_v6; 14189d26e4fcSRobert Mustacchi } ipaddr; 14199d26e4fcSRobert Mustacchi __le16 flags; 14209d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 14219d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 14229d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 14239d26e4fcSRobert Mustacchi /* 0x0000 reserved */ 1424*df36e06dSRobert Mustacchi /* 0x0001 reserved */ 14259d26e4fcSRobert Mustacchi /* 0x0002 reserved */ 14269d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 14279d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 14289d26e4fcSRobert Mustacchi /* 0x0005 reserved */ 14299d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 14309d26e4fcSRobert Mustacchi /* 0x0007 reserved */ 14319d26e4fcSRobert Mustacchi /* 0x0008 reserved */ 14329d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 14339d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 14349d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 14359d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1436*df36e06dSRobert Mustacchi /* 0x000D reserved */ 1437*df36e06dSRobert Mustacchi /* 0x000E reserved */ 1438*df36e06dSRobert Mustacchi /* 0x000F reserved */ 1439*df36e06dSRobert Mustacchi /* 0x0010 to 0x0017 is for custom filters */ 1440*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1441*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1442*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 14439d26e4fcSRobert Mustacchi 14449d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 14459d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 14469d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 14479d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 14489d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 14499d26e4fcSRobert Mustacchi 14509d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 14519d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 14523d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 14539d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 14543d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 14559d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 14563d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 14573d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 14583d75a287SRobert Mustacchi 14593d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 14603d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 14613d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 14629d26e4fcSRobert Mustacchi 14639d26e4fcSRobert Mustacchi __le32 tenant_id; 14649d26e4fcSRobert Mustacchi u8 reserved[4]; 14659d26e4fcSRobert Mustacchi __le16 queue_number; 14669d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 14679d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 14689d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 14699d26e4fcSRobert Mustacchi u8 reserved2[14]; 14709d26e4fcSRobert Mustacchi /* response section */ 14719d26e4fcSRobert Mustacchi u8 allocation_result; 14729d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 14739d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 14749d26e4fcSRobert Mustacchi u8 response_reserved[7]; 14759d26e4fcSRobert Mustacchi }; 14769d26e4fcSRobert Mustacchi 1477*df36e06dSRobert Mustacchi /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when 1478*df36e06dSRobert Mustacchi * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. 1479*df36e06dSRobert Mustacchi */ 1480*df36e06dSRobert Mustacchi struct i40e_aqc_add_rm_cloud_filt_elem_ext { 1481*df36e06dSRobert Mustacchi struct i40e_aqc_cloud_filters_element_data element; 1482*df36e06dSRobert Mustacchi u16 general_fields[32]; 1483*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1484*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1485*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1486*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1487*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1488*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1489*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1490*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1491*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1492*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1493*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1494*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1495*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1496*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1497*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1498*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1499*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1500*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1501*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1502*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1503*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1504*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1505*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1506*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1507*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1508*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1509*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1510*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1511*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1512*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1513*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1514*df36e06dSRobert Mustacchi }; 1515*df36e06dSRobert Mustacchi 1516*df36e06dSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1517*df36e06dSRobert Mustacchi 1518*df36e06dSRobert Mustacchi /* i40e_aqc_cloud_filters_element_bb is used when 1519*df36e06dSRobert Mustacchi * I40E_AQC_CLOUD_CMD_BB flag is set. 1520*df36e06dSRobert Mustacchi */ 1521*df36e06dSRobert Mustacchi struct i40e_aqc_cloud_filters_element_bb { 1522*df36e06dSRobert Mustacchi struct i40e_aqc_cloud_filters_element_data element; 1523*df36e06dSRobert Mustacchi u16 general_fields[32]; 1524*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1525*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1526*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1527*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1528*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1529*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1530*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1531*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1532*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1533*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1534*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1535*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1536*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1537*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1538*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1539*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1540*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1541*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1542*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1543*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1544*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1545*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1546*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1547*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1548*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1549*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1550*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1551*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1552*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1553*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1554*df36e06dSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1555*df36e06dSRobert Mustacchi }; 1556*df36e06dSRobert Mustacchi 1557*df36e06dSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1558*df36e06dSRobert Mustacchi 15599d26e4fcSRobert Mustacchi struct i40e_aqc_remove_cloud_filters_completion { 15609d26e4fcSRobert Mustacchi __le16 perfect_ovlan_used; 15619d26e4fcSRobert Mustacchi __le16 perfect_ovlan_free; 15629d26e4fcSRobert Mustacchi __le16 vlan_used; 15639d26e4fcSRobert Mustacchi __le16 vlan_free; 15649d26e4fcSRobert Mustacchi __le32 addr_high; 15659d26e4fcSRobert Mustacchi __le32 addr_low; 15669d26e4fcSRobert Mustacchi }; 15679d26e4fcSRobert Mustacchi 15689d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 15699d26e4fcSRobert Mustacchi 1570*df36e06dSRobert Mustacchi /* Replace filter Command 0x025F 1571*df36e06dSRobert Mustacchi * uses the i40e_aqc_replace_cloud_filters, 1572*df36e06dSRobert Mustacchi * and the generic indirect completion structure 1573*df36e06dSRobert Mustacchi */ 1574*df36e06dSRobert Mustacchi struct i40e_filter_data { 1575*df36e06dSRobert Mustacchi u8 filter_type; 1576*df36e06dSRobert Mustacchi u8 input[3]; 1577*df36e06dSRobert Mustacchi }; 1578*df36e06dSRobert Mustacchi 1579*df36e06dSRobert Mustacchi I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1580*df36e06dSRobert Mustacchi 1581*df36e06dSRobert Mustacchi struct i40e_aqc_replace_cloud_filters_cmd { 1582*df36e06dSRobert Mustacchi u8 valid_flags; 1583*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_L1_FILTER 0x0 1584*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1585*df36e06dSRobert Mustacchi #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1586*df36e06dSRobert Mustacchi #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1587*df36e06dSRobert Mustacchi #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1588*df36e06dSRobert Mustacchi u8 old_filter_type; 1589*df36e06dSRobert Mustacchi u8 new_filter_type; 1590*df36e06dSRobert Mustacchi u8 tr_bit; 1591*df36e06dSRobert Mustacchi u8 tr_bit2; 1592*df36e06dSRobert Mustacchi u8 reserved[3]; 1593*df36e06dSRobert Mustacchi __le32 addr_high; 1594*df36e06dSRobert Mustacchi __le32 addr_low; 1595*df36e06dSRobert Mustacchi }; 1596*df36e06dSRobert Mustacchi 1597*df36e06dSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1598*df36e06dSRobert Mustacchi 1599*df36e06dSRobert Mustacchi struct i40e_aqc_replace_cloud_filters_cmd_buf { 1600*df36e06dSRobert Mustacchi u8 data[32]; 1601*df36e06dSRobert Mustacchi /* Filter type INPUT codes*/ 1602*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1603*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL) 1604*df36e06dSRobert Mustacchi 1605*df36e06dSRobert Mustacchi /* Field Vector offsets */ 1606*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1607*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1608*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1609*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1610*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1611*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1612*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1613*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1614*df36e06dSRobert Mustacchi /* big FLU */ 1615*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1616*df36e06dSRobert Mustacchi /* big FLU */ 1617*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1618*df36e06dSRobert Mustacchi 1619*df36e06dSRobert Mustacchi #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1620*df36e06dSRobert Mustacchi struct i40e_filter_data filters[8]; 1621*df36e06dSRobert Mustacchi }; 1622*df36e06dSRobert Mustacchi 1623*df36e06dSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1624*df36e06dSRobert Mustacchi 16259d26e4fcSRobert Mustacchi /* Add Mirror Rule (indirect or direct 0x0260) 16269d26e4fcSRobert Mustacchi * Delete Mirror Rule (indirect or direct 0x0261) 16279d26e4fcSRobert Mustacchi * note: some rule types (4,5) do not use an external buffer. 16289d26e4fcSRobert Mustacchi * take care to set the flags correctly. 16299d26e4fcSRobert Mustacchi */ 16309d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule { 16319d26e4fcSRobert Mustacchi __le16 seid; 16329d26e4fcSRobert Mustacchi __le16 rule_type; 16339d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 16349d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 16359d26e4fcSRobert Mustacchi I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 16369d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 16379d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 16389d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 16399d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 16409d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 16419d26e4fcSRobert Mustacchi __le16 num_entries; 16429d26e4fcSRobert Mustacchi __le16 destination; /* VSI for add, rule id for delete */ 16439d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 16449d26e4fcSRobert Mustacchi __le32 addr_low; 16459d26e4fcSRobert Mustacchi }; 16469d26e4fcSRobert Mustacchi 16479d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 16489d26e4fcSRobert Mustacchi 16499d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule_completion { 16509d26e4fcSRobert Mustacchi u8 reserved[2]; 16519d26e4fcSRobert Mustacchi __le16 rule_id; /* only used on add */ 16529d26e4fcSRobert Mustacchi __le16 mirror_rules_used; 16539d26e4fcSRobert Mustacchi __le16 mirror_rules_free; 16549d26e4fcSRobert Mustacchi __le32 addr_high; 16559d26e4fcSRobert Mustacchi __le32 addr_low; 16569d26e4fcSRobert Mustacchi }; 16579d26e4fcSRobert Mustacchi 16589d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 16599d26e4fcSRobert Mustacchi 16609d26e4fcSRobert Mustacchi /* DCB 0x03xx*/ 16619d26e4fcSRobert Mustacchi 16629d26e4fcSRobert Mustacchi /* PFC Ignore (direct 0x0301) 16639d26e4fcSRobert Mustacchi * the command and response use the same descriptor structure 16649d26e4fcSRobert Mustacchi */ 16659d26e4fcSRobert Mustacchi struct i40e_aqc_pfc_ignore { 16669d26e4fcSRobert Mustacchi u8 tc_bitmap; 16679d26e4fcSRobert Mustacchi u8 command_flags; /* unused on response */ 16689d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_SET 0x80 16699d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 16709d26e4fcSRobert Mustacchi u8 reserved[14]; 16719d26e4fcSRobert Mustacchi }; 16729d26e4fcSRobert Mustacchi 16739d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 16749d26e4fcSRobert Mustacchi 16759d26e4fcSRobert Mustacchi /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 16769d26e4fcSRobert Mustacchi * with no parameters 16779d26e4fcSRobert Mustacchi */ 16789d26e4fcSRobert Mustacchi 16799d26e4fcSRobert Mustacchi /* TX scheduler 0x04xx */ 16809d26e4fcSRobert Mustacchi 16819d26e4fcSRobert Mustacchi /* Almost all the indirect commands use 16829d26e4fcSRobert Mustacchi * this generic struct to pass the SEID in param0 16839d26e4fcSRobert Mustacchi */ 16849d26e4fcSRobert Mustacchi struct i40e_aqc_tx_sched_ind { 16859d26e4fcSRobert Mustacchi __le16 vsi_seid; 16869d26e4fcSRobert Mustacchi u8 reserved[6]; 16879d26e4fcSRobert Mustacchi __le32 addr_high; 16889d26e4fcSRobert Mustacchi __le32 addr_low; 16899d26e4fcSRobert Mustacchi }; 16909d26e4fcSRobert Mustacchi 16919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 16929d26e4fcSRobert Mustacchi 16939d26e4fcSRobert Mustacchi /* Several commands respond with a set of queue set handles */ 16949d26e4fcSRobert Mustacchi struct i40e_aqc_qs_handles_resp { 16959d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 16969d26e4fcSRobert Mustacchi }; 16979d26e4fcSRobert Mustacchi 16989d26e4fcSRobert Mustacchi /* Configure VSI BW limits (direct 0x0400) */ 16999d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_bw_limit { 17009d26e4fcSRobert Mustacchi __le16 vsi_seid; 17019d26e4fcSRobert Mustacchi u8 reserved[2]; 17029d26e4fcSRobert Mustacchi __le16 credit; 17039d26e4fcSRobert Mustacchi u8 reserved1[2]; 17049d26e4fcSRobert Mustacchi u8 max_credit; /* 0-3, limit = 2^max */ 17059d26e4fcSRobert Mustacchi u8 reserved2[7]; 17069d26e4fcSRobert Mustacchi }; 17079d26e4fcSRobert Mustacchi 17089d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 17099d26e4fcSRobert Mustacchi 17109d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 17119d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 17129d26e4fcSRobert Mustacchi */ 17139d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_ets_sla_bw_data { 17149d26e4fcSRobert Mustacchi u8 tc_valid_bits; 17159d26e4fcSRobert Mustacchi u8 reserved[15]; 17169d26e4fcSRobert Mustacchi __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 17179d26e4fcSRobert Mustacchi 17189d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 17199d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 17209d26e4fcSRobert Mustacchi u8 reserved1[28]; 17219d26e4fcSRobert Mustacchi }; 17229d26e4fcSRobert Mustacchi 17239d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 17249d26e4fcSRobert Mustacchi 17259d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 17269d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 17279d26e4fcSRobert Mustacchi */ 17289d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_tc_bw_data { 17299d26e4fcSRobert Mustacchi u8 tc_valid_bits; 17309d26e4fcSRobert Mustacchi u8 reserved[3]; 17319d26e4fcSRobert Mustacchi u8 tc_bw_credits[8]; 17329d26e4fcSRobert Mustacchi u8 reserved1[4]; 17339d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 17349d26e4fcSRobert Mustacchi }; 17359d26e4fcSRobert Mustacchi 17369d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 17379d26e4fcSRobert Mustacchi 17389d26e4fcSRobert Mustacchi /* Query vsi bw configuration (indirect 0x0408) */ 17399d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_bw_config_resp { 17409d26e4fcSRobert Mustacchi u8 tc_valid_bits; 17419d26e4fcSRobert Mustacchi u8 tc_suspended_bits; 17429d26e4fcSRobert Mustacchi u8 reserved[14]; 17439d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 17449d26e4fcSRobert Mustacchi u8 reserved1[4]; 17459d26e4fcSRobert Mustacchi __le16 port_bw_limit; 17469d26e4fcSRobert Mustacchi u8 reserved2[2]; 17479d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 17489d26e4fcSRobert Mustacchi u8 reserved3[23]; 17499d26e4fcSRobert Mustacchi }; 17509d26e4fcSRobert Mustacchi 17519d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 17529d26e4fcSRobert Mustacchi 17539d26e4fcSRobert Mustacchi /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 17549d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_ets_sla_config_resp { 17559d26e4fcSRobert Mustacchi u8 tc_valid_bits; 17569d26e4fcSRobert Mustacchi u8 reserved[3]; 17579d26e4fcSRobert Mustacchi u8 share_credits[8]; 17589d26e4fcSRobert Mustacchi __le16 credits[8]; 17599d26e4fcSRobert Mustacchi 17609d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 17619d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 17629d26e4fcSRobert Mustacchi }; 17639d26e4fcSRobert Mustacchi 17649d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 17659d26e4fcSRobert Mustacchi 17669d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 17679d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_limit { 17689d26e4fcSRobert Mustacchi __le16 seid; 17699d26e4fcSRobert Mustacchi u8 reserved[2]; 17709d26e4fcSRobert Mustacchi __le16 credit; 17719d26e4fcSRobert Mustacchi u8 reserved1[2]; 17729d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 17739d26e4fcSRobert Mustacchi u8 reserved2[7]; 17749d26e4fcSRobert Mustacchi }; 17759d26e4fcSRobert Mustacchi 17769d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 17779d26e4fcSRobert Mustacchi 17789d26e4fcSRobert Mustacchi /* Enable Physical Port ETS (indirect 0x0413) 17799d26e4fcSRobert Mustacchi * Modify Physical Port ETS (indirect 0x0414) 17809d26e4fcSRobert Mustacchi * Disable Physical Port ETS (indirect 0x0415) 17819d26e4fcSRobert Mustacchi */ 17829d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_data { 17839d26e4fcSRobert Mustacchi u8 reserved[4]; 17849d26e4fcSRobert Mustacchi u8 tc_valid_bits; 17859d26e4fcSRobert Mustacchi u8 seepage; 17869d26e4fcSRobert Mustacchi #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 17879d26e4fcSRobert Mustacchi u8 tc_strict_priority_flags; 17889d26e4fcSRobert Mustacchi u8 reserved1[17]; 17899d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 17909d26e4fcSRobert Mustacchi u8 reserved2[96]; 17919d26e4fcSRobert Mustacchi }; 17929d26e4fcSRobert Mustacchi 17939d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 17949d26e4fcSRobert Mustacchi 17959d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 17969d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 17979d26e4fcSRobert Mustacchi u8 tc_valid_bits; 17989d26e4fcSRobert Mustacchi u8 reserved[15]; 17999d26e4fcSRobert Mustacchi __le16 tc_bw_credit[8]; 18009d26e4fcSRobert Mustacchi 18019d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 18029d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 18039d26e4fcSRobert Mustacchi u8 reserved1[28]; 18049d26e4fcSRobert Mustacchi }; 18059d26e4fcSRobert Mustacchi 18063d75a287SRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, 18073d75a287SRobert Mustacchi i40e_aqc_configure_switching_comp_ets_bw_limit_data); 18089d26e4fcSRobert Mustacchi 18099d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Allocation per Tc 18109d26e4fcSRobert Mustacchi * (indirect 0x0417) 18119d26e4fcSRobert Mustacchi */ 18129d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_config_data { 18139d26e4fcSRobert Mustacchi u8 tc_valid_bits; 18149d26e4fcSRobert Mustacchi u8 reserved[2]; 18159d26e4fcSRobert Mustacchi u8 absolute_credits; /* bool */ 18169d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 18179d26e4fcSRobert Mustacchi u8 reserved1[20]; 18189d26e4fcSRobert Mustacchi }; 18199d26e4fcSRobert Mustacchi 18209d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 18219d26e4fcSRobert Mustacchi 18229d26e4fcSRobert Mustacchi /* Query Switching Component Configuration (indirect 0x0418) */ 18239d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_ets_config_resp { 18249d26e4fcSRobert Mustacchi u8 tc_valid_bits; 18259d26e4fcSRobert Mustacchi u8 reserved[35]; 18269d26e4fcSRobert Mustacchi __le16 port_bw_limit; 18279d26e4fcSRobert Mustacchi u8 reserved1[2]; 18289d26e4fcSRobert Mustacchi u8 tc_bw_max; /* 0-3, limit = 2^max */ 18299d26e4fcSRobert Mustacchi u8 reserved2[23]; 18309d26e4fcSRobert Mustacchi }; 18319d26e4fcSRobert Mustacchi 18329d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 18339d26e4fcSRobert Mustacchi 18349d26e4fcSRobert Mustacchi /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 18359d26e4fcSRobert Mustacchi struct i40e_aqc_query_port_ets_config_resp { 18369d26e4fcSRobert Mustacchi u8 reserved[4]; 18379d26e4fcSRobert Mustacchi u8 tc_valid_bits; 18389d26e4fcSRobert Mustacchi u8 reserved1; 18399d26e4fcSRobert Mustacchi u8 tc_strict_priority_bits; 18409d26e4fcSRobert Mustacchi u8 reserved2; 18419d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 18429d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 18439d26e4fcSRobert Mustacchi 18449d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 18459d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 18469d26e4fcSRobert Mustacchi u8 reserved3[32]; 18479d26e4fcSRobert Mustacchi }; 18489d26e4fcSRobert Mustacchi 18499d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 18509d26e4fcSRobert Mustacchi 18519d26e4fcSRobert Mustacchi /* Query Switching Component Bandwidth Allocation per Traffic Type 18529d26e4fcSRobert Mustacchi * (indirect 0x041A) 18539d26e4fcSRobert Mustacchi */ 18549d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_bw_config_resp { 18559d26e4fcSRobert Mustacchi u8 tc_valid_bits; 18569d26e4fcSRobert Mustacchi u8 reserved[2]; 18579d26e4fcSRobert Mustacchi u8 absolute_credits_enable; /* bool */ 18589d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 18599d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 18609d26e4fcSRobert Mustacchi 18619d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 18629d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 18639d26e4fcSRobert Mustacchi }; 18649d26e4fcSRobert Mustacchi 18659d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 18669d26e4fcSRobert Mustacchi 18679d26e4fcSRobert Mustacchi /* Suspend/resume port TX traffic 18689d26e4fcSRobert Mustacchi * (direct 0x041B and 0x041C) uses the generic SEID struct 18699d26e4fcSRobert Mustacchi */ 18709d26e4fcSRobert Mustacchi 18719d26e4fcSRobert Mustacchi /* Configure partition BW 18729d26e4fcSRobert Mustacchi * (indirect 0x041D) 18739d26e4fcSRobert Mustacchi */ 18749d26e4fcSRobert Mustacchi struct i40e_aqc_configure_partition_bw_data { 18759d26e4fcSRobert Mustacchi __le16 pf_valid_bits; 18769d26e4fcSRobert Mustacchi u8 min_bw[16]; /* guaranteed bandwidth */ 18779d26e4fcSRobert Mustacchi u8 max_bw[16]; /* bandwidth limit */ 18789d26e4fcSRobert Mustacchi }; 18799d26e4fcSRobert Mustacchi 18809d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 18819d26e4fcSRobert Mustacchi 18829d26e4fcSRobert Mustacchi /* Get and set the active HMC resource profile and status. 18839d26e4fcSRobert Mustacchi * (direct 0x0500) and (direct 0x0501) 18849d26e4fcSRobert Mustacchi */ 18859d26e4fcSRobert Mustacchi struct i40e_aq_get_set_hmc_resource_profile { 18869d26e4fcSRobert Mustacchi u8 pm_profile; 18879d26e4fcSRobert Mustacchi u8 pe_vf_enabled; 18889d26e4fcSRobert Mustacchi u8 reserved[14]; 18899d26e4fcSRobert Mustacchi }; 18909d26e4fcSRobert Mustacchi 18919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 18929d26e4fcSRobert Mustacchi 18939d26e4fcSRobert Mustacchi enum i40e_aq_hmc_profile { 18943d75a287SRobert Mustacchi /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 18959d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_DEFAULT = 1, 18969d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_FAVOR_VF = 2, 18979d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_EQUAL = 3, 18989d26e4fcSRobert Mustacchi }; 18999d26e4fcSRobert Mustacchi 19009d26e4fcSRobert Mustacchi /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 19019d26e4fcSRobert Mustacchi 19029d26e4fcSRobert Mustacchi /* set in param0 for get phy abilities to report qualified modules */ 19039d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 19049d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 19059d26e4fcSRobert Mustacchi 19069d26e4fcSRobert Mustacchi enum i40e_aq_phy_type { 19079d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SGMII = 0x0, 19089d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_KX = 0x1, 19099d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 19109d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KR = 0x3, 19119d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 19129d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XAUI = 0x5, 19139d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XFI = 0x6, 19149d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SFI = 0x7, 19159d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLAUI = 0x8, 19169d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLPPI = 0x9, 19179d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 19189d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 19199d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_AOC = 0xC, 19209d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_AOC = 0xD, 192193f1cac5SPaul Winder I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 192293f1cac5SPaul Winder I40E_PHY_TYPE_UNSUPPORTED = 0xF, 19239d26e4fcSRobert Mustacchi I40E_PHY_TYPE_100BASE_TX = 0x11, 19249d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T = 0x12, 19259d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_T = 0x13, 19269d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SR = 0x14, 19279d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_LR = 0x15, 19289d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 19299d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 19309d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 19319d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 19329d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 19339d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_SX = 0x1B, 19349d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_LX = 0x1C, 19359d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 19369d26e4fcSRobert Mustacchi I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 19373d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_KR = 0x1F, 19383d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_CR = 0x20, 19393d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_SR = 0x21, 19403d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_LR = 0x22, 194193f1cac5SPaul Winder I40E_PHY_TYPE_25GBASE_AOC = 0x23, 194293f1cac5SPaul Winder I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1943*df36e06dSRobert Mustacchi I40E_PHY_TYPE_2_5GBASE_T = 0x30, 1944*df36e06dSRobert Mustacchi I40E_PHY_TYPE_5GBASE_T = 0x31, 194593f1cac5SPaul Winder I40E_PHY_TYPE_MAX, 194693f1cac5SPaul Winder I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 194793f1cac5SPaul Winder I40E_PHY_TYPE_EMPTY = 0xFE, 194893f1cac5SPaul Winder I40E_PHY_TYPE_DEFAULT = 0xFF, 194993f1cac5SPaul Winder }; 195093f1cac5SPaul Winder 195193f1cac5SPaul Winder #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 195293f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 195393f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 195493f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 195593f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 195693f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 195793f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_XFI) | \ 195893f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_SFI) | \ 195993f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 196093f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 196193f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 196293f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 196393f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 196493f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 196593f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 196693f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 196793f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 196893f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 196993f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 197093f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 197193f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 197293f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 197393f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 197493f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 197593f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 197693f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 197793f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 197893f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 197993f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 198093f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 198193f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 198293f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 198393f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 198493f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 198593f1cac5SPaul Winder BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1986*df36e06dSRobert Mustacchi BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 1987*df36e06dSRobert Mustacchi BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 1988*df36e06dSRobert Mustacchi BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 19899d26e4fcSRobert Mustacchi 1990*df36e06dSRobert Mustacchi #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 19919d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_100MB_SHIFT 0x1 19929d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 19939d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_10GB_SHIFT 0x3 19949d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_40GB_SHIFT 0x4 19959d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_20GB_SHIFT 0x5 19963d75a287SRobert Mustacchi #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1997*df36e06dSRobert Mustacchi #define I40E_LINK_SPEED_5GB_SHIFT 0x7 19989d26e4fcSRobert Mustacchi 19999d26e4fcSRobert Mustacchi enum i40e_aq_link_speed { 20009d26e4fcSRobert Mustacchi I40E_LINK_SPEED_UNKNOWN = 0, 20019d26e4fcSRobert Mustacchi I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 20029d26e4fcSRobert Mustacchi I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 2003*df36e06dSRobert Mustacchi I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 2004*df36e06dSRobert Mustacchi I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 20059d26e4fcSRobert Mustacchi I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 20069d26e4fcSRobert Mustacchi I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 20073d75a287SRobert Mustacchi I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 20083d75a287SRobert Mustacchi I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 20099d26e4fcSRobert Mustacchi }; 20109d26e4fcSRobert Mustacchi 20119d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc { 20129d26e4fcSRobert Mustacchi u8 oui[3]; 20139d26e4fcSRobert Mustacchi u8 reserved1; 20149d26e4fcSRobert Mustacchi u8 part_number[16]; 20159d26e4fcSRobert Mustacchi u8 revision[4]; 20169d26e4fcSRobert Mustacchi u8 reserved2[8]; 20179d26e4fcSRobert Mustacchi }; 20189d26e4fcSRobert Mustacchi 20199d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 20209d26e4fcSRobert Mustacchi 20219d26e4fcSRobert Mustacchi struct i40e_aq_get_phy_abilities_resp { 20229d26e4fcSRobert Mustacchi __le32 phy_type; /* bitmap using the above enum for offsets */ 20239d26e4fcSRobert Mustacchi u8 link_speed; /* bitmap using the above enum bit patterns */ 20249d26e4fcSRobert Mustacchi u8 abilities; 20259d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 20269d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 20279d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 20289d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLED 0x08 20299d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_AN_ENABLED 0x10 20309d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 20313d75a287SRobert Mustacchi #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 20323d75a287SRobert Mustacchi #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 20339d26e4fcSRobert Mustacchi __le16 eee_capability; 2034*df36e06dSRobert Mustacchi #define I40E_AQ_EEE_AUTO 0x0001 20359d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_100BASE_TX 0x0002 20369d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_T 0x0004 20379d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_T 0x0008 20389d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_KX 0x0010 20399d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KX4 0x0020 20409d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KR 0x0040 2041*df36e06dSRobert Mustacchi #define I40E_AQ_EEE_2_5GBASE_T 0x0100 2042*df36e06dSRobert Mustacchi #define I40E_AQ_EEE_5GBASE_T 0x0200 20439d26e4fcSRobert Mustacchi __le32 eeer_val; 20449d26e4fcSRobert Mustacchi u8 d3_lpan; 20459d26e4fcSRobert Mustacchi #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 20463d75a287SRobert Mustacchi u8 phy_type_ext; 20473d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 20483d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 20493d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 20503d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 205193f1cac5SPaul Winder #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 205293f1cac5SPaul Winder #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2053*df36e06dSRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 2054*df36e06dSRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 205593f1cac5SPaul Winder u8 fec_cfg_curr_mod_ext_info; 205693f1cac5SPaul Winder #define I40E_AQ_ENABLE_FEC_KR 0x01 205793f1cac5SPaul Winder #define I40E_AQ_ENABLE_FEC_RS 0x02 205893f1cac5SPaul Winder #define I40E_AQ_REQUEST_FEC_KR 0x04 205993f1cac5SPaul Winder #define I40E_AQ_REQUEST_FEC_RS 0x08 206093f1cac5SPaul Winder #define I40E_AQ_ENABLE_FEC_AUTO 0x10 206193f1cac5SPaul Winder #define I40E_AQ_FEC 206293f1cac5SPaul Winder #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 206393f1cac5SPaul Winder #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 206493f1cac5SPaul Winder 20653d75a287SRobert Mustacchi u8 ext_comp_code; 20669d26e4fcSRobert Mustacchi u8 phy_id[4]; 20679d26e4fcSRobert Mustacchi u8 module_type[3]; 20689d26e4fcSRobert Mustacchi u8 qualified_module_count; 20699d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_MAX_QMS 16 20709d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 20719d26e4fcSRobert Mustacchi }; 20729d26e4fcSRobert Mustacchi 20739d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 20749d26e4fcSRobert Mustacchi 20759d26e4fcSRobert Mustacchi /* Set PHY Config (direct 0x0601) */ 20769d26e4fcSRobert Mustacchi struct i40e_aq_set_phy_config { /* same bits as above in all */ 20779d26e4fcSRobert Mustacchi __le32 phy_type; 20789d26e4fcSRobert Mustacchi u8 link_speed; 20799d26e4fcSRobert Mustacchi u8 abilities; 20809d26e4fcSRobert Mustacchi /* bits 0-2 use the values from get_phy_abilities_resp */ 20819d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_LINK 0x08 20829d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_AN 0x10 20839d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 20849d26e4fcSRobert Mustacchi __le16 eee_capability; 20859d26e4fcSRobert Mustacchi __le32 eeer; 20869d26e4fcSRobert Mustacchi u8 low_power_ctrl; 20873d75a287SRobert Mustacchi u8 phy_type_ext; 20883d75a287SRobert Mustacchi u8 fec_config; 2089*df36e06dSRobert Mustacchi #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2090*df36e06dSRobert Mustacchi #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2091*df36e06dSRobert Mustacchi #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2092*df36e06dSRobert Mustacchi #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2093*df36e06dSRobert Mustacchi #define I40E_AQ_SET_FEC_AUTO BIT(4) 209493f1cac5SPaul Winder #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 209593f1cac5SPaul Winder #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 20963d75a287SRobert Mustacchi u8 reserved; 20979d26e4fcSRobert Mustacchi }; 20989d26e4fcSRobert Mustacchi 20999d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 21009d26e4fcSRobert Mustacchi 21019d26e4fcSRobert Mustacchi /* Set MAC Config command data structure (direct 0x0603) */ 21029d26e4fcSRobert Mustacchi struct i40e_aq_set_mac_config { 21039d26e4fcSRobert Mustacchi __le16 max_frame_size; 21049d26e4fcSRobert Mustacchi u8 params; 2105*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2106*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2107*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2108*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2109*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2110*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2111*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2112*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2113*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2114*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2115*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2116*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2117*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2118*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2119*df36e06dSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 21209d26e4fcSRobert Mustacchi u8 tx_timer_priority; /* bitmap */ 21219d26e4fcSRobert Mustacchi __le16 tx_timer_value; 21229d26e4fcSRobert Mustacchi __le16 fc_refresh_threshold; 21239d26e4fcSRobert Mustacchi u8 reserved[8]; 21249d26e4fcSRobert Mustacchi }; 21259d26e4fcSRobert Mustacchi 21269d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 21279d26e4fcSRobert Mustacchi 21289d26e4fcSRobert Mustacchi /* Restart Auto-Negotiation (direct 0x605) */ 21299d26e4fcSRobert Mustacchi struct i40e_aqc_set_link_restart_an { 21309d26e4fcSRobert Mustacchi u8 command; 21319d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_RESTART_AN 0x02 21329d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLE 0x04 21339d26e4fcSRobert Mustacchi u8 reserved[15]; 21349d26e4fcSRobert Mustacchi }; 21359d26e4fcSRobert Mustacchi 21369d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 21379d26e4fcSRobert Mustacchi 21389d26e4fcSRobert Mustacchi /* Get Link Status cmd & response data structure (direct 0x0607) */ 21399d26e4fcSRobert Mustacchi struct i40e_aqc_get_link_status { 21409d26e4fcSRobert Mustacchi __le16 command_flags; /* only field set on command */ 21419d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_MASK 0x3 21429d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_NOP 0x0 21439d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_DISABLE 0x2 21449d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_ENABLE 0x3 21459d26e4fcSRobert Mustacchi /* only response uses this flag */ 21469d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_IS_ENABLED 0x1 21479d26e4fcSRobert Mustacchi u8 phy_type; /* i40e_aq_phy_type */ 21489d26e4fcSRobert Mustacchi u8 link_speed; /* i40e_aq_link_speed */ 21499d26e4fcSRobert Mustacchi u8 link_info; 21509d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 21519d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_FUNCTION 0x01 21529d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT 0x02 21539d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_TX 0x04 21549d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_RX 0x08 21559d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_REMOTE 0x10 21569d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_PORT 0x20 21579d26e4fcSRobert Mustacchi #define I40E_AQ_MEDIA_AVAILABLE 0x40 21589d26e4fcSRobert Mustacchi #define I40E_AQ_SIGNAL_DETECT 0x80 21599d26e4fcSRobert Mustacchi u8 an_info; 21609d26e4fcSRobert Mustacchi #define I40E_AQ_AN_COMPLETED 0x01 21619d26e4fcSRobert Mustacchi #define I40E_AQ_LP_AN_ABILITY 0x02 21629d26e4fcSRobert Mustacchi #define I40E_AQ_PD_FAULT 0x04 21639d26e4fcSRobert Mustacchi #define I40E_AQ_FEC_EN 0x08 21649d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LOW_POWER 0x10 21659d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_TX 0x20 21669d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_RX 0x40 21679d26e4fcSRobert Mustacchi #define I40E_AQ_QUALIFIED_MODULE 0x80 21689d26e4fcSRobert Mustacchi u8 ext_info; 21699d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 21709d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 21719d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_SHIFT 0x02 21729d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 21739d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_ACTIVE 0x00 21749d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_DRAINED 0x01 21759d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_FLUSHED 0x03 21769d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FORCED_40G 0x10 21773d75a287SRobert Mustacchi /* 25G Error Codes */ 21783d75a287SRobert Mustacchi #define I40E_AQ_25G_NO_ERR 0X00 21793d75a287SRobert Mustacchi #define I40E_AQ_25G_NOT_PRESENT 0X01 21803d75a287SRobert Mustacchi #define I40E_AQ_25G_NVM_CRC_ERR 0X02 21813d75a287SRobert Mustacchi #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 21823d75a287SRobert Mustacchi #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 21833d75a287SRobert Mustacchi #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 21849d26e4fcSRobert Mustacchi u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 218593f1cac5SPaul Winder /* Since firmware API 1.7 loopback field keeps power class info as well */ 218693f1cac5SPaul Winder #define I40E_AQ_LOOPBACK_MASK 0x07 218793f1cac5SPaul Winder #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 218893f1cac5SPaul Winder #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 21899d26e4fcSRobert Mustacchi __le16 max_frame_size; 21909d26e4fcSRobert Mustacchi u8 config; 21913d75a287SRobert Mustacchi #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 21923d75a287SRobert Mustacchi #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 21939d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_CRC_ENA 0x04 21949d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_PACING_MASK 0x78 219593f1cac5SPaul Winder union { 219693f1cac5SPaul Winder struct { 219793f1cac5SPaul Winder u8 power_desc; 21983d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_1 0x00 21993d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_2 0x01 22003d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_3 0x02 22013d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_4 0x03 22023d75a287SRobert Mustacchi #define I40E_AQ_PWR_CLASS_MASK 0x03 220393f1cac5SPaul Winder u8 reserved[4]; 220493f1cac5SPaul Winder }; 220593f1cac5SPaul Winder struct { 220693f1cac5SPaul Winder u8 link_type[4]; 220793f1cac5SPaul Winder u8 link_type_ext; 220893f1cac5SPaul Winder }; 220993f1cac5SPaul Winder }; 22109d26e4fcSRobert Mustacchi }; 22119d26e4fcSRobert Mustacchi 22129d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 22139d26e4fcSRobert Mustacchi 22149d26e4fcSRobert Mustacchi /* Set event mask command (direct 0x613) */ 22159d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_int_mask { 22169d26e4fcSRobert Mustacchi u8 reserved[8]; 22179d26e4fcSRobert Mustacchi __le16 event_mask; 22189d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 22199d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MEDIA_NA 0x0004 22209d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_FAULT 0x0008 22219d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 22229d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 22239d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 22249d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 22259d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 22269d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 22279d26e4fcSRobert Mustacchi u8 reserved1[6]; 22289d26e4fcSRobert Mustacchi }; 22299d26e4fcSRobert Mustacchi 22309d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 22319d26e4fcSRobert Mustacchi 22329d26e4fcSRobert Mustacchi /* Get Local AN advt register (direct 0x0614) 22339d26e4fcSRobert Mustacchi * Set Local AN advt register (direct 0x0615) 22349d26e4fcSRobert Mustacchi * Get Link Partner AN advt register (direct 0x0616) 22359d26e4fcSRobert Mustacchi */ 22369d26e4fcSRobert Mustacchi struct i40e_aqc_an_advt_reg { 22379d26e4fcSRobert Mustacchi __le32 local_an_reg0; 22389d26e4fcSRobert Mustacchi __le16 local_an_reg1; 22399d26e4fcSRobert Mustacchi u8 reserved[10]; 22409d26e4fcSRobert Mustacchi }; 22419d26e4fcSRobert Mustacchi 22429d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 22439d26e4fcSRobert Mustacchi 22449d26e4fcSRobert Mustacchi /* Set Loopback mode (0x0618) */ 22459d26e4fcSRobert Mustacchi struct i40e_aqc_set_lb_mode { 224693f1cac5SPaul Winder u8 lb_level; 224793f1cac5SPaul Winder #define I40E_AQ_LB_NONE 0 224893f1cac5SPaul Winder #define I40E_AQ_LB_MAC 1 224993f1cac5SPaul Winder #define I40E_AQ_LB_SERDES 2 225093f1cac5SPaul Winder #define I40E_AQ_LB_PHY_INT 3 225193f1cac5SPaul Winder #define I40E_AQ_LB_PHY_EXT 4 2252*df36e06dSRobert Mustacchi #define I40E_AQ_LB_BASE_T_PCS 5 2253*df36e06dSRobert Mustacchi #define I40E_AQ_LB_BASE_T_EXT 6 22549d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_LOCAL 0x01 22559d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_REMOTE 0x02 22569d26e4fcSRobert Mustacchi #define I40E_AQ_LB_MAC_LOCAL 0x04 225793f1cac5SPaul Winder u8 lb_type; 225893f1cac5SPaul Winder #define I40E_AQ_LB_LOCAL 0 225993f1cac5SPaul Winder #define I40E_AQ_LB_FAR 0x01 226093f1cac5SPaul Winder u8 speed; 226193f1cac5SPaul Winder #define I40E_AQ_LB_SPEED_NONE 0 226293f1cac5SPaul Winder #define I40E_AQ_LB_SPEED_1G 1 226393f1cac5SPaul Winder #define I40E_AQ_LB_SPEED_10G 2 226493f1cac5SPaul Winder #define I40E_AQ_LB_SPEED_40G 3 226593f1cac5SPaul Winder #define I40E_AQ_LB_SPEED_20G 4 226693f1cac5SPaul Winder u8 force_speed; 226793f1cac5SPaul Winder u8 reserved[12]; 22689d26e4fcSRobert Mustacchi }; 22699d26e4fcSRobert Mustacchi 22709d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 22719d26e4fcSRobert Mustacchi 22729d26e4fcSRobert Mustacchi /* Set PHY Debug command (0x0622) */ 22739d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_debug { 22749d26e4fcSRobert Mustacchi u8 command_flags; 22759d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 22769d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 22779d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 22789d26e4fcSRobert Mustacchi I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 22799d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 22809d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 22819d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 22823d75a287SRobert Mustacchi /* Disable link manageability on a single port */ 22839d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 22843d75a287SRobert Mustacchi /* Disable link manageability on all ports needs both bits 4 and 5 */ 22853d75a287SRobert Mustacchi #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 22869d26e4fcSRobert Mustacchi u8 reserved[15]; 22879d26e4fcSRobert Mustacchi }; 22889d26e4fcSRobert Mustacchi 22899d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 22909d26e4fcSRobert Mustacchi 22919d26e4fcSRobert Mustacchi enum i40e_aq_phy_reg_type { 22929d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_INTERNAL = 0x1, 22939d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 22949d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 22959d26e4fcSRobert Mustacchi }; 22969d26e4fcSRobert Mustacchi 2297*df36e06dSRobert Mustacchi #pragma pack(1) 22983d75a287SRobert Mustacchi /* Run PHY Activity (0x0626) */ 22993d75a287SRobert Mustacchi struct i40e_aqc_run_phy_activity { 2300*df36e06dSRobert Mustacchi u8 cmd_flags; 2301*df36e06dSRobert Mustacchi __le16 activity_id; 2302*df36e06dSRobert Mustacchi #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10 2303*df36e06dSRobert Mustacchi u8 reserved; 2304*df36e06dSRobert Mustacchi union { 2305*df36e06dSRobert Mustacchi struct { 2306*df36e06dSRobert Mustacchi __le32 dnl_opcode; 2307*df36e06dSRobert Mustacchi #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a 2308*df36e06dSRobert Mustacchi #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b 2309*df36e06dSRobert Mustacchi #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b 2310*df36e06dSRobert Mustacchi __le32 data; 2311*df36e06dSRobert Mustacchi u8 reserved2[4]; 2312*df36e06dSRobert Mustacchi } cmd; 2313*df36e06dSRobert Mustacchi struct { 2314*df36e06dSRobert Mustacchi __le32 cmd_status; 2315*df36e06dSRobert Mustacchi #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4 2316*df36e06dSRobert Mustacchi #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF 2317*df36e06dSRobert Mustacchi __le32 data0; 2318*df36e06dSRobert Mustacchi __le32 data1; 2319*df36e06dSRobert Mustacchi } resp; 2320*df36e06dSRobert Mustacchi } params; 23213d75a287SRobert Mustacchi }; 2322*df36e06dSRobert Mustacchi #pragma pack() 23233d75a287SRobert Mustacchi 2324*df36e06dSRobert Mustacchi /* 2325*df36e06dSRobert Mustacchi * Unfortunately, for some reason smatch cannot parse the following correctly 2326*df36e06dSRobert Mustacchi * and emits divide by zero expressions when it shouldn't. Until this is fixed, 2327*df36e06dSRobert Mustacchi * for the time being comment out the check. 2328*df36e06dSRobert Mustacchi */ 2329*df36e06dSRobert Mustacchi #ifndef __sun__ 23303d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2331*df36e06dSRobert Mustacchi #endif 2332286d309cSRobert Mustacchi 2333286d309cSRobert Mustacchi /* Set PHY Register command (0x0628) */ 2334286d309cSRobert Mustacchi /* Get PHY Register command (0x0629) */ 2335286d309cSRobert Mustacchi struct i40e_aqc_phy_register_access { 2336286d309cSRobert Mustacchi u8 phy_interface; 2337286d309cSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2338286d309cSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2339286d309cSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2340286d309cSRobert Mustacchi u8 dev_addres; 2341*df36e06dSRobert Mustacchi u8 cmd_flags; 2342*df36e06dSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01 2343*df36e06dSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02 2344*df36e06dSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2 2345*df36e06dSRobert Mustacchi #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \ 2346*df36e06dSRobert Mustacchi I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) 2347*df36e06dSRobert Mustacchi u8 reserved1; 2348*df36e06dSRobert Mustacchi __le32 reg_address; 2349*df36e06dSRobert Mustacchi __le32 reg_value; 2350286d309cSRobert Mustacchi u8 reserved2[4]; 2351286d309cSRobert Mustacchi }; 2352286d309cSRobert Mustacchi 2353286d309cSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2354286d309cSRobert Mustacchi 23559d26e4fcSRobert Mustacchi /* NVM Read command (indirect 0x0701) 23569d26e4fcSRobert Mustacchi * NVM Erase commands (direct 0x0702) 23579d26e4fcSRobert Mustacchi * NVM Update commands (indirect 0x0703) 23589d26e4fcSRobert Mustacchi */ 23599d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_update { 23609d26e4fcSRobert Mustacchi u8 command_flags; 236193f1cac5SPaul Winder #define I40E_AQ_NVM_LAST_CMD 0x01 2362*df36e06dSRobert Mustacchi #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2363*df36e06dSRobert Mustacchi #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 236493f1cac5SPaul Winder #define I40E_AQ_NVM_FLASH_ONLY 0x80 236593f1cac5SPaul Winder #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 236693f1cac5SPaul Winder #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 236793f1cac5SPaul Winder #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 236893f1cac5SPaul Winder #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 23699d26e4fcSRobert Mustacchi u8 module_pointer; 23709d26e4fcSRobert Mustacchi __le16 length; 23719d26e4fcSRobert Mustacchi __le32 offset; 23729d26e4fcSRobert Mustacchi __le32 addr_high; 23739d26e4fcSRobert Mustacchi __le32 addr_low; 23749d26e4fcSRobert Mustacchi }; 23759d26e4fcSRobert Mustacchi 23769d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 23779d26e4fcSRobert Mustacchi 23789d26e4fcSRobert Mustacchi /* NVM Config Read (indirect 0x0704) */ 23799d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_read { 23809d26e4fcSRobert Mustacchi __le16 cmd_flags; 23819d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 23829d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 23839d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 23849d26e4fcSRobert Mustacchi __le16 element_count; 23853d75a287SRobert Mustacchi __le16 element_id; /* Feature/field ID */ 23869d26e4fcSRobert Mustacchi __le16 element_id_msw; /* MSWord of field ID */ 23879d26e4fcSRobert Mustacchi __le32 address_high; 23889d26e4fcSRobert Mustacchi __le32 address_low; 23899d26e4fcSRobert Mustacchi }; 23909d26e4fcSRobert Mustacchi 23919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 23929d26e4fcSRobert Mustacchi 23939d26e4fcSRobert Mustacchi /* NVM Config Write (indirect 0x0705) */ 23949d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_write { 23959d26e4fcSRobert Mustacchi __le16 cmd_flags; 23969d26e4fcSRobert Mustacchi __le16 element_count; 23979d26e4fcSRobert Mustacchi u8 reserved[4]; 23989d26e4fcSRobert Mustacchi __le32 address_high; 23999d26e4fcSRobert Mustacchi __le32 address_low; 24009d26e4fcSRobert Mustacchi }; 24019d26e4fcSRobert Mustacchi 24029d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 24039d26e4fcSRobert Mustacchi 24049d26e4fcSRobert Mustacchi /* Used for 0x0704 as well as for 0x0705 commands */ 24059d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 24063d75a287SRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 24073d75a287SRobert Mustacchi (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 24083d75a287SRobert Mustacchi #define I40E_AQ_ANVM_FEATURE 0 24093d75a287SRobert Mustacchi #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 24109d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_feature { 24119d26e4fcSRobert Mustacchi __le16 feature_id; 24129d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 24139d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 24149d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 24159d26e4fcSRobert Mustacchi __le16 feature_options; 24169d26e4fcSRobert Mustacchi __le16 feature_selection; 24179d26e4fcSRobert Mustacchi }; 24189d26e4fcSRobert Mustacchi 24199d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 24209d26e4fcSRobert Mustacchi 24219d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_immediate_field { 24229d26e4fcSRobert Mustacchi __le32 field_id; 24239d26e4fcSRobert Mustacchi __le32 field_value; 24249d26e4fcSRobert Mustacchi __le16 field_options; 24259d26e4fcSRobert Mustacchi __le16 reserved; 24269d26e4fcSRobert Mustacchi }; 24279d26e4fcSRobert Mustacchi 24289d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 24299d26e4fcSRobert Mustacchi 24309d26e4fcSRobert Mustacchi /* OEM Post Update (indirect 0x0720) 24319d26e4fcSRobert Mustacchi * no command data struct used 24329d26e4fcSRobert Mustacchi */ 24333d75a287SRobert Mustacchi struct i40e_aqc_nvm_oem_post_update { 24349d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 24359d26e4fcSRobert Mustacchi u8 sel_data; 24369d26e4fcSRobert Mustacchi u8 reserved[7]; 24379d26e4fcSRobert Mustacchi }; 24389d26e4fcSRobert Mustacchi 24399d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 24409d26e4fcSRobert Mustacchi 24419d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_oem_post_update_buffer { 24429d26e4fcSRobert Mustacchi u8 str_len; 24439d26e4fcSRobert Mustacchi u8 dev_addr; 24449d26e4fcSRobert Mustacchi __le16 eeprom_addr; 24459d26e4fcSRobert Mustacchi u8 data[36]; 24469d26e4fcSRobert Mustacchi }; 24479d26e4fcSRobert Mustacchi 24489d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 24499d26e4fcSRobert Mustacchi 24503d75a287SRobert Mustacchi /* Thermal Sensor (indirect 0x0721) 24513d75a287SRobert Mustacchi * read or set thermal sensor configs and values 24523d75a287SRobert Mustacchi * takes a sensor and command specific data buffer, not detailed here 24533d75a287SRobert Mustacchi */ 24543d75a287SRobert Mustacchi struct i40e_aqc_thermal_sensor { 24553d75a287SRobert Mustacchi u8 sensor_action; 24563d75a287SRobert Mustacchi #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 24573d75a287SRobert Mustacchi #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 24583d75a287SRobert Mustacchi #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 24593d75a287SRobert Mustacchi u8 reserved[7]; 24603d75a287SRobert Mustacchi __le32 addr_high; 24613d75a287SRobert Mustacchi __le32 addr_low; 24623d75a287SRobert Mustacchi }; 24633d75a287SRobert Mustacchi 24643d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 24653d75a287SRobert Mustacchi 24669d26e4fcSRobert Mustacchi /* Send to PF command (indirect 0x0801) id is only used by PF 24679d26e4fcSRobert Mustacchi * Send to VF command (indirect 0x0802) id is only used by PF 24689d26e4fcSRobert Mustacchi * Send to Peer PF command (indirect 0x0803) 24699d26e4fcSRobert Mustacchi */ 24709d26e4fcSRobert Mustacchi struct i40e_aqc_pf_vf_message { 24719d26e4fcSRobert Mustacchi __le32 id; 24729d26e4fcSRobert Mustacchi u8 reserved[4]; 24739d26e4fcSRobert Mustacchi __le32 addr_high; 24749d26e4fcSRobert Mustacchi __le32 addr_low; 24759d26e4fcSRobert Mustacchi }; 24769d26e4fcSRobert Mustacchi 24779d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 24789d26e4fcSRobert Mustacchi 24799d26e4fcSRobert Mustacchi /* Alternate structure */ 24809d26e4fcSRobert Mustacchi 24819d26e4fcSRobert Mustacchi /* Direct write (direct 0x0900) 24829d26e4fcSRobert Mustacchi * Direct read (direct 0x0902) 24839d26e4fcSRobert Mustacchi */ 24849d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write { 24859d26e4fcSRobert Mustacchi __le32 address0; 24869d26e4fcSRobert Mustacchi __le32 data0; 24879d26e4fcSRobert Mustacchi __le32 address1; 24889d26e4fcSRobert Mustacchi __le32 data1; 24899d26e4fcSRobert Mustacchi }; 24909d26e4fcSRobert Mustacchi 24919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 24929d26e4fcSRobert Mustacchi 24939d26e4fcSRobert Mustacchi /* Indirect write (indirect 0x0901) 24949d26e4fcSRobert Mustacchi * Indirect read (indirect 0x0903) 24959d26e4fcSRobert Mustacchi */ 24969d26e4fcSRobert Mustacchi 24979d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_ind_write { 24989d26e4fcSRobert Mustacchi __le32 address; 24999d26e4fcSRobert Mustacchi __le32 length; 25009d26e4fcSRobert Mustacchi __le32 addr_high; 25019d26e4fcSRobert Mustacchi __le32 addr_low; 25029d26e4fcSRobert Mustacchi }; 25039d26e4fcSRobert Mustacchi 25049d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 25059d26e4fcSRobert Mustacchi 25069d26e4fcSRobert Mustacchi /* Done alternate write (direct 0x0904) 25079d26e4fcSRobert Mustacchi * uses i40e_aq_desc 25089d26e4fcSRobert Mustacchi */ 25099d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write_done { 25109d26e4fcSRobert Mustacchi __le16 cmd_flags; 25119d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 25129d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 25139d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 25149d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 25159d26e4fcSRobert Mustacchi u8 reserved[14]; 25169d26e4fcSRobert Mustacchi }; 25179d26e4fcSRobert Mustacchi 25189d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 25199d26e4fcSRobert Mustacchi 25209d26e4fcSRobert Mustacchi /* Set OEM mode (direct 0x0905) */ 25219d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_set_mode { 25229d26e4fcSRobert Mustacchi __le32 mode; 25239d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_NONE 0 25249d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_OEM 1 25259d26e4fcSRobert Mustacchi u8 reserved[12]; 25269d26e4fcSRobert Mustacchi }; 25279d26e4fcSRobert Mustacchi 25289d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 25299d26e4fcSRobert Mustacchi 25309d26e4fcSRobert Mustacchi /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 25319d26e4fcSRobert Mustacchi 25329d26e4fcSRobert Mustacchi /* async events 0x10xx */ 25339d26e4fcSRobert Mustacchi 25349d26e4fcSRobert Mustacchi /* Lan Queue Overflow Event (direct, 0x1001) */ 25359d26e4fcSRobert Mustacchi struct i40e_aqc_lan_overflow { 25369d26e4fcSRobert Mustacchi __le32 prtdcb_rupto; 25379d26e4fcSRobert Mustacchi __le32 otx_ctl; 25389d26e4fcSRobert Mustacchi u8 reserved[8]; 25399d26e4fcSRobert Mustacchi }; 25409d26e4fcSRobert Mustacchi 25419d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 25429d26e4fcSRobert Mustacchi 25439d26e4fcSRobert Mustacchi /* Get LLDP MIB (indirect 0x0A00) */ 25449d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_get_mib { 25459d26e4fcSRobert Mustacchi u8 type; 25469d26e4fcSRobert Mustacchi u8 reserved1; 25479d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 25489d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL 0x0 25499d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_REMOTE 0x1 25509d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 25519d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 25529d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 25539d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 25549d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 25559d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_SHIFT 0x4 25569d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 25579d26e4fcSRobert Mustacchi /* TX pause flags use I40E_AQ_LINK_TX_* above */ 25589d26e4fcSRobert Mustacchi __le16 local_len; 25599d26e4fcSRobert Mustacchi __le16 remote_len; 25609d26e4fcSRobert Mustacchi u8 reserved2[2]; 25619d26e4fcSRobert Mustacchi __le32 addr_high; 25629d26e4fcSRobert Mustacchi __le32 addr_low; 25639d26e4fcSRobert Mustacchi }; 25649d26e4fcSRobert Mustacchi 25659d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 25669d26e4fcSRobert Mustacchi 25679d26e4fcSRobert Mustacchi /* Configure LLDP MIB Change Event (direct 0x0A01) 25689d26e4fcSRobert Mustacchi * also used for the event (with type in the command field) 25699d26e4fcSRobert Mustacchi */ 25709d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_mib { 25719d26e4fcSRobert Mustacchi u8 command; 25729d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 25739d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 25749d26e4fcSRobert Mustacchi u8 reserved[7]; 25759d26e4fcSRobert Mustacchi __le32 addr_high; 25769d26e4fcSRobert Mustacchi __le32 addr_low; 25779d26e4fcSRobert Mustacchi }; 25789d26e4fcSRobert Mustacchi 25799d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 25809d26e4fcSRobert Mustacchi 25819d26e4fcSRobert Mustacchi /* Add LLDP TLV (indirect 0x0A02) 25829d26e4fcSRobert Mustacchi * Delete LLDP TLV (indirect 0x0A04) 25839d26e4fcSRobert Mustacchi */ 25849d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_add_tlv { 25859d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 25869d26e4fcSRobert Mustacchi u8 reserved1[1]; 25879d26e4fcSRobert Mustacchi __le16 len; 25889d26e4fcSRobert Mustacchi u8 reserved2[4]; 25899d26e4fcSRobert Mustacchi __le32 addr_high; 25909d26e4fcSRobert Mustacchi __le32 addr_low; 25919d26e4fcSRobert Mustacchi }; 25929d26e4fcSRobert Mustacchi 25939d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 25949d26e4fcSRobert Mustacchi 25959d26e4fcSRobert Mustacchi /* Update LLDP TLV (indirect 0x0A03) */ 25969d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_tlv { 25979d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 25989d26e4fcSRobert Mustacchi u8 reserved; 25999d26e4fcSRobert Mustacchi __le16 old_len; 26009d26e4fcSRobert Mustacchi __le16 new_offset; 26019d26e4fcSRobert Mustacchi __le16 new_len; 26029d26e4fcSRobert Mustacchi __le32 addr_high; 26039d26e4fcSRobert Mustacchi __le32 addr_low; 26049d26e4fcSRobert Mustacchi }; 26059d26e4fcSRobert Mustacchi 26069d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 26079d26e4fcSRobert Mustacchi 26089d26e4fcSRobert Mustacchi /* Stop LLDP (direct 0x0A05) */ 26099d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop { 26109d26e4fcSRobert Mustacchi u8 command; 2611*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_STOP 0x0 2612*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2613*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 26149d26e4fcSRobert Mustacchi u8 reserved[15]; 26159d26e4fcSRobert Mustacchi }; 26169d26e4fcSRobert Mustacchi 26179d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 26189d26e4fcSRobert Mustacchi 26199d26e4fcSRobert Mustacchi /* Start LLDP (direct 0x0A06) */ 26209d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_start { 26219d26e4fcSRobert Mustacchi u8 command; 2622*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_START 0x1 2623*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 26249d26e4fcSRobert Mustacchi u8 reserved[15]; 26259d26e4fcSRobert Mustacchi }; 26269d26e4fcSRobert Mustacchi 26279d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 26289d26e4fcSRobert Mustacchi 262993f1cac5SPaul Winder /* Set DCB (direct 0x0303) */ 263093f1cac5SPaul Winder struct i40e_aqc_set_dcb_parameters { 263193f1cac5SPaul Winder u8 command; 263293f1cac5SPaul Winder #define I40E_AQ_DCB_SET_AGENT 0x1 263393f1cac5SPaul Winder #define I40E_DCB_VALID 0x1 263493f1cac5SPaul Winder u8 valid_flags; 263593f1cac5SPaul Winder u8 reserved[14]; 263693f1cac5SPaul Winder }; 263793f1cac5SPaul Winder 263893f1cac5SPaul Winder I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 263993f1cac5SPaul Winder 26409d26e4fcSRobert Mustacchi /* Get CEE DCBX Oper Config (0x0A07) 26419d26e4fcSRobert Mustacchi * uses the generic descriptor struct 26429d26e4fcSRobert Mustacchi * returns below as indirect response 26439d26e4fcSRobert Mustacchi */ 26449d26e4fcSRobert Mustacchi 26459d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 26469d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 26479d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 26489d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 26499d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 26509d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 26519d26e4fcSRobert Mustacchi 26529d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 26539d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 26549d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 26559d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 26569d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 26579d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 26589d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 26599d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 26609d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 26619d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 26629d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 26639d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 26649d26e4fcSRobert Mustacchi 26659d26e4fcSRobert Mustacchi /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 26669d26e4fcSRobert Mustacchi * word boundary layout issues, which the Linux compilers silently deal 26679d26e4fcSRobert Mustacchi * with by adding padding, making the actual struct larger than designed. 26689d26e4fcSRobert Mustacchi * However, the FW compiler for the NIC is less lenient and complains 26699d26e4fcSRobert Mustacchi * about the struct. Hence, the struct defined here has an extra byte in 26709d26e4fcSRobert Mustacchi * fields reserved3 and reserved4 to directly acknowledge that padding, 26719d26e4fcSRobert Mustacchi * and the new length is used in the length check macro. 26729d26e4fcSRobert Mustacchi */ 26739d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 26749d26e4fcSRobert Mustacchi u8 reserved1; 26759d26e4fcSRobert Mustacchi u8 oper_num_tc; 26769d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 26779d26e4fcSRobert Mustacchi u8 reserved2; 26789d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 26799d26e4fcSRobert Mustacchi u8 oper_pfc_en; 26809d26e4fcSRobert Mustacchi u8 reserved3[2]; 26819d26e4fcSRobert Mustacchi __le16 oper_app_prio; 26829d26e4fcSRobert Mustacchi u8 reserved4[2]; 26839d26e4fcSRobert Mustacchi __le16 tlv_status; 26849d26e4fcSRobert Mustacchi }; 26859d26e4fcSRobert Mustacchi 26869d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 26879d26e4fcSRobert Mustacchi 26889d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_resp { 26899d26e4fcSRobert Mustacchi u8 oper_num_tc; 26909d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 26919d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 26929d26e4fcSRobert Mustacchi u8 oper_pfc_en; 26939d26e4fcSRobert Mustacchi __le16 oper_app_prio; 26949d26e4fcSRobert Mustacchi __le32 tlv_status; 26959d26e4fcSRobert Mustacchi u8 reserved[12]; 26969d26e4fcSRobert Mustacchi }; 26979d26e4fcSRobert Mustacchi 26989d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 26999d26e4fcSRobert Mustacchi 27009d26e4fcSRobert Mustacchi /* Set Local LLDP MIB (indirect 0x0A08) 27019d26e4fcSRobert Mustacchi * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 27029d26e4fcSRobert Mustacchi */ 27039d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_set_local_mib { 27049d26e4fcSRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 27053d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 27063d75a287SRobert Mustacchi SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 27073d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 27083d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 27093d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 27103d75a287SRobert Mustacchi SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 27113d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 27129d26e4fcSRobert Mustacchi u8 type; 27139d26e4fcSRobert Mustacchi u8 reserved0; 27149d26e4fcSRobert Mustacchi __le16 length; 27159d26e4fcSRobert Mustacchi u8 reserved1[4]; 27169d26e4fcSRobert Mustacchi __le32 address_high; 27179d26e4fcSRobert Mustacchi __le32 address_low; 27189d26e4fcSRobert Mustacchi }; 27199d26e4fcSRobert Mustacchi 27209d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 27219d26e4fcSRobert Mustacchi 27223d75a287SRobert Mustacchi struct i40e_aqc_lldp_set_local_mib_resp { 27233d75a287SRobert Mustacchi #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 27243d75a287SRobert Mustacchi u8 status; 27253d75a287SRobert Mustacchi u8 reserved[15]; 27263d75a287SRobert Mustacchi }; 27273d75a287SRobert Mustacchi 27283d75a287SRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 27293d75a287SRobert Mustacchi 27309d26e4fcSRobert Mustacchi /* Stop/Start LLDP Agent (direct 0x0A09) 27319d26e4fcSRobert Mustacchi * Used for stopping/starting specific LLDP agent. e.g. DCBx 27329d26e4fcSRobert Mustacchi */ 27339d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop_start_specific_agent { 27349d26e4fcSRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 27353d75a287SRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 27363d75a287SRobert Mustacchi (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 27379d26e4fcSRobert Mustacchi u8 command; 27389d26e4fcSRobert Mustacchi u8 reserved[15]; 27399d26e4fcSRobert Mustacchi }; 27409d26e4fcSRobert Mustacchi 27419d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 27429d26e4fcSRobert Mustacchi 2743*df36e06dSRobert Mustacchi /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2744*df36e06dSRobert Mustacchi struct i40e_aqc_lldp_restore { 2745*df36e06dSRobert Mustacchi u8 command; 2746*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2747*df36e06dSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2748*df36e06dSRobert Mustacchi u8 reserved[15]; 2749*df36e06dSRobert Mustacchi }; 2750*df36e06dSRobert Mustacchi 2751*df36e06dSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2752*df36e06dSRobert Mustacchi 27539d26e4fcSRobert Mustacchi /* Add Udp Tunnel command and completion (direct 0x0B00) */ 27549d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel { 27559d26e4fcSRobert Mustacchi __le16 udp_port; 27569d26e4fcSRobert Mustacchi u8 reserved0[3]; 27579d26e4fcSRobert Mustacchi u8 protocol_type; 27589d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 27599d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 27609d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 27613d75a287SRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 27629d26e4fcSRobert Mustacchi u8 reserved1[10]; 27639d26e4fcSRobert Mustacchi }; 27649d26e4fcSRobert Mustacchi 27659d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 27669d26e4fcSRobert Mustacchi 27679d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel_completion { 27683d75a287SRobert Mustacchi __le16 udp_port; 27699d26e4fcSRobert Mustacchi u8 filter_entry_index; 27709d26e4fcSRobert Mustacchi u8 multiple_pfs; 27719d26e4fcSRobert Mustacchi #define I40E_AQC_SINGLE_PF 0x0 27729d26e4fcSRobert Mustacchi #define I40E_AQC_MULTIPLE_PFS 0x1 27739d26e4fcSRobert Mustacchi u8 total_filters; 27749d26e4fcSRobert Mustacchi u8 reserved[11]; 27759d26e4fcSRobert Mustacchi }; 27769d26e4fcSRobert Mustacchi 27779d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 27789d26e4fcSRobert Mustacchi 27799d26e4fcSRobert Mustacchi /* remove UDP Tunnel command (0x0B01) */ 27809d26e4fcSRobert Mustacchi struct i40e_aqc_remove_udp_tunnel { 27819d26e4fcSRobert Mustacchi u8 reserved[2]; 27829d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 27839d26e4fcSRobert Mustacchi u8 reserved2[13]; 27849d26e4fcSRobert Mustacchi }; 27859d26e4fcSRobert Mustacchi 27869d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 27879d26e4fcSRobert Mustacchi 27889d26e4fcSRobert Mustacchi struct i40e_aqc_del_udp_tunnel_completion { 27899d26e4fcSRobert Mustacchi __le16 udp_port; 27909d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 27919d26e4fcSRobert Mustacchi u8 multiple_pfs; 27929d26e4fcSRobert Mustacchi u8 total_filters_used; 27939d26e4fcSRobert Mustacchi u8 reserved1[11]; 27949d26e4fcSRobert Mustacchi }; 27959d26e4fcSRobert Mustacchi 27969d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 27979d26e4fcSRobert Mustacchi 27989d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key { 27999d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 28009d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 28019d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 28029d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 28039d26e4fcSRobert Mustacchi __le16 vsi_id; 28049d26e4fcSRobert Mustacchi u8 reserved[6]; 28059d26e4fcSRobert Mustacchi __le32 addr_high; 28069d26e4fcSRobert Mustacchi __le32 addr_low; 28079d26e4fcSRobert Mustacchi }; 28089d26e4fcSRobert Mustacchi 28099d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 28109d26e4fcSRobert Mustacchi 28119d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key_data { 28129d26e4fcSRobert Mustacchi u8 standard_rss_key[0x28]; 28139d26e4fcSRobert Mustacchi u8 extended_hash_key[0xc]; 28149d26e4fcSRobert Mustacchi }; 28159d26e4fcSRobert Mustacchi 28169d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 28179d26e4fcSRobert Mustacchi 28189d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_lut { 28199d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 28209d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 28219d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 28229d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 28239d26e4fcSRobert Mustacchi __le16 vsi_id; 28249d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 28259d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 28269d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 28279d26e4fcSRobert Mustacchi 28289d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 28299d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 28309d26e4fcSRobert Mustacchi __le16 flags; 28319d26e4fcSRobert Mustacchi u8 reserved[4]; 28329d26e4fcSRobert Mustacchi __le32 addr_high; 28339d26e4fcSRobert Mustacchi __le32 addr_low; 28349d26e4fcSRobert Mustacchi }; 28359d26e4fcSRobert Mustacchi 28369d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 28379d26e4fcSRobert Mustacchi 28389d26e4fcSRobert Mustacchi /* tunnel key structure 0x0B10 */ 28399d26e4fcSRobert Mustacchi 28409d26e4fcSRobert Mustacchi struct i40e_aqc_tunnel_key_structure { 28419d26e4fcSRobert Mustacchi u8 key1_off; 28429d26e4fcSRobert Mustacchi u8 key2_off; 28439d26e4fcSRobert Mustacchi u8 key1_len; /* 0 to 15 */ 28449d26e4fcSRobert Mustacchi u8 key2_len; /* 0 to 15 */ 28459d26e4fcSRobert Mustacchi u8 flags; 28469d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 28479d26e4fcSRobert Mustacchi /* response flags */ 28489d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 28499d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 28509d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 28519d26e4fcSRobert Mustacchi u8 network_key_index; 28529d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 28539d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 28549d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 28559d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 28569d26e4fcSRobert Mustacchi u8 reserved[10]; 28579d26e4fcSRobert Mustacchi }; 28589d26e4fcSRobert Mustacchi 28599d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 28609d26e4fcSRobert Mustacchi 28619d26e4fcSRobert Mustacchi /* OEM mode commands (direct 0xFE0x) */ 28629d26e4fcSRobert Mustacchi struct i40e_aqc_oem_param_change { 28639d26e4fcSRobert Mustacchi __le32 param_type; 28649d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 28659d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 28669d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_MAC 2 28679d26e4fcSRobert Mustacchi __le32 param_value1; 28689d26e4fcSRobert Mustacchi __le16 param_value2; 28699d26e4fcSRobert Mustacchi u8 reserved[6]; 28709d26e4fcSRobert Mustacchi }; 28719d26e4fcSRobert Mustacchi 28729d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 28739d26e4fcSRobert Mustacchi 28749d26e4fcSRobert Mustacchi struct i40e_aqc_oem_state_change { 28759d26e4fcSRobert Mustacchi __le32 state; 28769d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 28779d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_UP 0x1 28789d26e4fcSRobert Mustacchi u8 reserved[12]; 28799d26e4fcSRobert Mustacchi }; 28809d26e4fcSRobert Mustacchi 28819d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 28829d26e4fcSRobert Mustacchi 28839d26e4fcSRobert Mustacchi /* Initialize OCSD (0xFE02, direct) */ 28849d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocsd_initialize { 28859d26e4fcSRobert Mustacchi u8 type_status; 28869d26e4fcSRobert Mustacchi u8 reserved1[3]; 28879d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_high; 28889d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_low; 28899d26e4fcSRobert Mustacchi __le32 requested_update_interval; 28909d26e4fcSRobert Mustacchi }; 28919d26e4fcSRobert Mustacchi 28929d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 28939d26e4fcSRobert Mustacchi 28949d26e4fcSRobert Mustacchi /* Initialize OCBB (0xFE03, direct) */ 28959d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocbb_initialize { 28969d26e4fcSRobert Mustacchi u8 type_status; 28979d26e4fcSRobert Mustacchi u8 reserved1[3]; 28989d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_high; 28999d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_low; 29009d26e4fcSRobert Mustacchi u8 reserved2[4]; 29019d26e4fcSRobert Mustacchi }; 29029d26e4fcSRobert Mustacchi 29039d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 29049d26e4fcSRobert Mustacchi 29059d26e4fcSRobert Mustacchi /* debug commands */ 29069d26e4fcSRobert Mustacchi 29079d26e4fcSRobert Mustacchi /* get device id (0xFF00) uses the generic structure */ 29089d26e4fcSRobert Mustacchi 29099d26e4fcSRobert Mustacchi /* set test more (0xFF01, internal) */ 29109d26e4fcSRobert Mustacchi 29119d26e4fcSRobert Mustacchi struct i40e_acq_set_test_mode { 29129d26e4fcSRobert Mustacchi u8 mode; 29139d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_PARTIAL 0 29149d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_FULL 1 29159d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_NVM 2 29169d26e4fcSRobert Mustacchi u8 reserved[3]; 29179d26e4fcSRobert Mustacchi u8 command; 29189d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_OPEN 0 29199d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_CLOSE 1 29209d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_INC 2 29219d26e4fcSRobert Mustacchi u8 reserved2[3]; 29229d26e4fcSRobert Mustacchi __le32 address_high; 29239d26e4fcSRobert Mustacchi __le32 address_low; 29249d26e4fcSRobert Mustacchi }; 29259d26e4fcSRobert Mustacchi 29269d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 29279d26e4fcSRobert Mustacchi 29289d26e4fcSRobert Mustacchi /* Debug Read Register command (0xFF03) 29299d26e4fcSRobert Mustacchi * Debug Write Register command (0xFF04) 29309d26e4fcSRobert Mustacchi */ 29319d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_read_write { 29329d26e4fcSRobert Mustacchi __le32 reserved; 29339d26e4fcSRobert Mustacchi __le32 address; 29349d26e4fcSRobert Mustacchi __le32 value_high; 29359d26e4fcSRobert Mustacchi __le32 value_low; 29369d26e4fcSRobert Mustacchi }; 29379d26e4fcSRobert Mustacchi 29389d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 29399d26e4fcSRobert Mustacchi 29409d26e4fcSRobert Mustacchi /* Scatter/gather Reg Read (indirect 0xFF05) 29419d26e4fcSRobert Mustacchi * Scatter/gather Reg Write (indirect 0xFF06) 29429d26e4fcSRobert Mustacchi */ 29439d26e4fcSRobert Mustacchi 29449d26e4fcSRobert Mustacchi /* i40e_aq_desc is used for the command */ 29459d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_sg_element_data { 29469d26e4fcSRobert Mustacchi __le32 address; 29479d26e4fcSRobert Mustacchi __le32 value; 29489d26e4fcSRobert Mustacchi }; 29499d26e4fcSRobert Mustacchi 29509d26e4fcSRobert Mustacchi /* Debug Modify register (direct 0xFF07) */ 29519d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_reg { 29529d26e4fcSRobert Mustacchi __le32 address; 29539d26e4fcSRobert Mustacchi __le32 value; 29549d26e4fcSRobert Mustacchi __le32 clear_mask; 29559d26e4fcSRobert Mustacchi __le32 set_mask; 29569d26e4fcSRobert Mustacchi }; 29579d26e4fcSRobert Mustacchi 29589d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 29599d26e4fcSRobert Mustacchi 29609d26e4fcSRobert Mustacchi /* dump internal data (0xFF08, indirect) */ 29619d26e4fcSRobert Mustacchi 29629d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_AUX 0 29639d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 29649d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_TXSCHED 2 29659d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_HMC 3 29669d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC0 4 29679d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC1 5 29689d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC2 6 29699d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC3 7 29709d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_DCB 8 29719d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 29729d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 29739d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_ALTRAM 11 29749d26e4fcSRobert Mustacchi 29759d26e4fcSRobert Mustacchi struct i40e_aqc_debug_dump_internals { 29769d26e4fcSRobert Mustacchi u8 cluster_id; 29779d26e4fcSRobert Mustacchi u8 table_id; 29789d26e4fcSRobert Mustacchi __le16 data_size; 29799d26e4fcSRobert Mustacchi __le32 idx; 29809d26e4fcSRobert Mustacchi __le32 address_high; 29819d26e4fcSRobert Mustacchi __le32 address_low; 29829d26e4fcSRobert Mustacchi }; 29839d26e4fcSRobert Mustacchi 29849d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 29859d26e4fcSRobert Mustacchi 29869d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_internals { 29879d26e4fcSRobert Mustacchi u8 cluster_id; 29889d26e4fcSRobert Mustacchi u8 cluster_specific_params[7]; 29899d26e4fcSRobert Mustacchi __le32 address_high; 29909d26e4fcSRobert Mustacchi __le32 address_low; 29919d26e4fcSRobert Mustacchi }; 29929d26e4fcSRobert Mustacchi 29939d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 29949d26e4fcSRobert Mustacchi 29953d75a287SRobert Mustacchi #endif /* _I40E_ADMINQ_CMD_H_ */ 2996