1*9d26e4fcSRobert Mustacchi /****************************************************************************** 2*9d26e4fcSRobert Mustacchi 3*9d26e4fcSRobert Mustacchi Copyright (c) 2013-2015, Intel Corporation 4*9d26e4fcSRobert Mustacchi All rights reserved. 5*9d26e4fcSRobert Mustacchi 6*9d26e4fcSRobert Mustacchi Redistribution and use in source and binary forms, with or without 7*9d26e4fcSRobert Mustacchi modification, are permitted provided that the following conditions are met: 8*9d26e4fcSRobert Mustacchi 9*9d26e4fcSRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 10*9d26e4fcSRobert Mustacchi this list of conditions and the following disclaimer. 11*9d26e4fcSRobert Mustacchi 12*9d26e4fcSRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 13*9d26e4fcSRobert Mustacchi notice, this list of conditions and the following disclaimer in the 14*9d26e4fcSRobert Mustacchi documentation and/or other materials provided with the distribution. 15*9d26e4fcSRobert Mustacchi 16*9d26e4fcSRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 17*9d26e4fcSRobert Mustacchi contributors may be used to endorse or promote products derived from 18*9d26e4fcSRobert Mustacchi this software without specific prior written permission. 19*9d26e4fcSRobert Mustacchi 20*9d26e4fcSRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21*9d26e4fcSRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22*9d26e4fcSRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23*9d26e4fcSRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24*9d26e4fcSRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25*9d26e4fcSRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26*9d26e4fcSRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27*9d26e4fcSRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28*9d26e4fcSRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29*9d26e4fcSRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30*9d26e4fcSRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 31*9d26e4fcSRobert Mustacchi 32*9d26e4fcSRobert Mustacchi ******************************************************************************/ 33*9d26e4fcSRobert Mustacchi /*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 284049 2015-06-05 22:52:42Z jfv $*/ 34*9d26e4fcSRobert Mustacchi 35*9d26e4fcSRobert Mustacchi #ifndef _I40E_ADMINQ_CMD_H_ 36*9d26e4fcSRobert Mustacchi #define _I40E_ADMINQ_CMD_H_ 37*9d26e4fcSRobert Mustacchi 38*9d26e4fcSRobert Mustacchi /* This header file defines the i40e Admin Queue commands and is shared between 39*9d26e4fcSRobert Mustacchi * i40e Firmware and Software. 40*9d26e4fcSRobert Mustacchi * 41*9d26e4fcSRobert Mustacchi * This file needs to comply with the Linux Kernel coding style. 42*9d26e4fcSRobert Mustacchi */ 43*9d26e4fcSRobert Mustacchi 44*9d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MAJOR 0x0001 45*9d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 46*9d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MINOR 0x0003 47*9d26e4fcSRobert Mustacchi #else 48*9d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MINOR 0x0004 49*9d26e4fcSRobert Mustacchi #endif 50*9d26e4fcSRobert Mustacchi 51*9d26e4fcSRobert Mustacchi struct i40e_aq_desc { 52*9d26e4fcSRobert Mustacchi __le16 flags; 53*9d26e4fcSRobert Mustacchi __le16 opcode; 54*9d26e4fcSRobert Mustacchi __le16 datalen; 55*9d26e4fcSRobert Mustacchi __le16 retval; 56*9d26e4fcSRobert Mustacchi __le32 cookie_high; 57*9d26e4fcSRobert Mustacchi __le32 cookie_low; 58*9d26e4fcSRobert Mustacchi union { 59*9d26e4fcSRobert Mustacchi struct { 60*9d26e4fcSRobert Mustacchi __le32 param0; 61*9d26e4fcSRobert Mustacchi __le32 param1; 62*9d26e4fcSRobert Mustacchi __le32 param2; 63*9d26e4fcSRobert Mustacchi __le32 param3; 64*9d26e4fcSRobert Mustacchi } internal; 65*9d26e4fcSRobert Mustacchi struct { 66*9d26e4fcSRobert Mustacchi __le32 param0; 67*9d26e4fcSRobert Mustacchi __le32 param1; 68*9d26e4fcSRobert Mustacchi __le32 addr_high; 69*9d26e4fcSRobert Mustacchi __le32 addr_low; 70*9d26e4fcSRobert Mustacchi } external; 71*9d26e4fcSRobert Mustacchi u8 raw[16]; 72*9d26e4fcSRobert Mustacchi } params; 73*9d26e4fcSRobert Mustacchi }; 74*9d26e4fcSRobert Mustacchi 75*9d26e4fcSRobert Mustacchi /* Flags sub-structure 76*9d26e4fcSRobert Mustacchi * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 77*9d26e4fcSRobert Mustacchi * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 78*9d26e4fcSRobert Mustacchi */ 79*9d26e4fcSRobert Mustacchi 80*9d26e4fcSRobert Mustacchi /* command flags and offsets*/ 81*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD_SHIFT 0 82*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP_SHIFT 1 83*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR_SHIFT 2 84*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE_SHIFT 3 85*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB_SHIFT 9 86*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD_SHIFT 10 87*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC_SHIFT 11 88*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF_SHIFT 12 89*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI_SHIFT 13 90*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI_SHIFT 14 91*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE_SHIFT 15 92*9d26e4fcSRobert Mustacchi 93*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 94*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 95*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 96*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 97*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 98*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 99*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 100*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 101*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 102*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 103*9d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 104*9d26e4fcSRobert Mustacchi 105*9d26e4fcSRobert Mustacchi /* error codes */ 106*9d26e4fcSRobert Mustacchi enum i40e_admin_queue_err { 107*9d26e4fcSRobert Mustacchi I40E_AQ_RC_OK = 0, /* success */ 108*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 109*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOENT = 2, /* No such element */ 110*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 111*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 112*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EIO = 5, /* I/O error */ 113*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ENXIO = 6, /* No such resource */ 114*9d26e4fcSRobert Mustacchi I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 115*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EAGAIN = 8, /* Try again */ 116*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 117*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EACCES = 10, /* Permission denied */ 118*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EFAULT = 11, /* Bad address */ 119*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 120*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EEXIST = 13, /* object already exists */ 121*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 122*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 123*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 124*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 125*9d26e4fcSRobert Mustacchi I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 126*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 127*9d26e4fcSRobert Mustacchi I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 128*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 129*9d26e4fcSRobert Mustacchi I40E_AQ_RC_EFBIG = 22, /* File too large */ 130*9d26e4fcSRobert Mustacchi }; 131*9d26e4fcSRobert Mustacchi 132*9d26e4fcSRobert Mustacchi /* Admin Queue command opcodes */ 133*9d26e4fcSRobert Mustacchi enum i40e_admin_queue_opc { 134*9d26e4fcSRobert Mustacchi /* aq commands */ 135*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_version = 0x0001, 136*9d26e4fcSRobert Mustacchi i40e_aqc_opc_driver_version = 0x0002, 137*9d26e4fcSRobert Mustacchi i40e_aqc_opc_queue_shutdown = 0x0003, 138*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_pf_context = 0x0004, 139*9d26e4fcSRobert Mustacchi 140*9d26e4fcSRobert Mustacchi /* resource ownership */ 141*9d26e4fcSRobert Mustacchi i40e_aqc_opc_request_resource = 0x0008, 142*9d26e4fcSRobert Mustacchi i40e_aqc_opc_release_resource = 0x0009, 143*9d26e4fcSRobert Mustacchi 144*9d26e4fcSRobert Mustacchi i40e_aqc_opc_list_func_capabilities = 0x000A, 145*9d26e4fcSRobert Mustacchi i40e_aqc_opc_list_dev_capabilities = 0x000B, 146*9d26e4fcSRobert Mustacchi 147*9d26e4fcSRobert Mustacchi /* LAA */ 148*9d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_read = 0x0107, 149*9d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_write = 0x0108, 150*9d26e4fcSRobert Mustacchi 151*9d26e4fcSRobert Mustacchi /* PXE */ 152*9d26e4fcSRobert Mustacchi i40e_aqc_opc_clear_pxe_mode = 0x0110, 153*9d26e4fcSRobert Mustacchi 154*9d26e4fcSRobert Mustacchi /* internal switch commands */ 155*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_config = 0x0200, 156*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_statistics = 0x0201, 157*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_statistics = 0x0202, 158*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_port_parameters = 0x0203, 159*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 160*9d26e4fcSRobert Mustacchi 161*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vsi = 0x0210, 162*9d26e4fcSRobert Mustacchi i40e_aqc_opc_update_vsi_parameters = 0x0211, 163*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_vsi_parameters = 0x0212, 164*9d26e4fcSRobert Mustacchi 165*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_pv = 0x0220, 166*9d26e4fcSRobert Mustacchi i40e_aqc_opc_update_pv_parameters = 0x0221, 167*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_pv_parameters = 0x0222, 168*9d26e4fcSRobert Mustacchi 169*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_veb = 0x0230, 170*9d26e4fcSRobert Mustacchi i40e_aqc_opc_update_veb_parameters = 0x0231, 171*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_veb_parameters = 0x0232, 172*9d26e4fcSRobert Mustacchi 173*9d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_element = 0x0243, 174*9d26e4fcSRobert Mustacchi 175*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_macvlan = 0x0250, 176*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_macvlan = 0x0251, 177*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vlan = 0x0252, 178*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_vlan = 0x0253, 179*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 180*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_tag = 0x0255, 181*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_tag = 0x0256, 182*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_multicast_etag = 0x0257, 183*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_multicast_etag = 0x0258, 184*9d26e4fcSRobert Mustacchi i40e_aqc_opc_update_tag = 0x0259, 185*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_control_packet_filter = 0x025A, 186*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_control_packet_filter = 0x025B, 187*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_cloud_filters = 0x025C, 188*9d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_cloud_filters = 0x025D, 189*9d26e4fcSRobert Mustacchi 190*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_mirror_rule = 0x0260, 191*9d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_mirror_rule = 0x0261, 192*9d26e4fcSRobert Mustacchi 193*9d26e4fcSRobert Mustacchi /* DCB commands */ 194*9d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 195*9d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_updated = 0x0302, 196*9d26e4fcSRobert Mustacchi 197*9d26e4fcSRobert Mustacchi /* TX scheduler */ 198*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 199*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 200*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 201*9d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_bw_config = 0x0408, 202*9d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 203*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 204*9d26e4fcSRobert Mustacchi 205*9d26e4fcSRobert Mustacchi i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 206*9d26e4fcSRobert Mustacchi i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 207*9d26e4fcSRobert Mustacchi i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 208*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 209*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 210*9d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 211*9d26e4fcSRobert Mustacchi i40e_aqc_opc_query_port_ets_config = 0x0419, 212*9d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 213*9d26e4fcSRobert Mustacchi i40e_aqc_opc_suspend_port_tx = 0x041B, 214*9d26e4fcSRobert Mustacchi i40e_aqc_opc_resume_port_tx = 0x041C, 215*9d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_partition_bw = 0x041D, 216*9d26e4fcSRobert Mustacchi 217*9d26e4fcSRobert Mustacchi /* hmc */ 218*9d26e4fcSRobert Mustacchi i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 219*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 220*9d26e4fcSRobert Mustacchi 221*9d26e4fcSRobert Mustacchi /* phy commands*/ 222*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_abilities = 0x0600, 223*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_config = 0x0601, 224*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_mac_config = 0x0603, 225*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_link_restart_an = 0x0605, 226*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_link_status = 0x0607, 227*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_int_mask = 0x0613, 228*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_local_advt_reg = 0x0614, 229*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_local_advt_reg = 0x0615, 230*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_partner_advt = 0x0616, 231*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_lb_modes = 0x0618, 232*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_wol_caps = 0x0621, 233*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_debug = 0x0622, 234*9d26e4fcSRobert Mustacchi i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 235*9d26e4fcSRobert Mustacchi 236*9d26e4fcSRobert Mustacchi /* NVM commands */ 237*9d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_read = 0x0701, 238*9d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_erase = 0x0702, 239*9d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_update = 0x0703, 240*9d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_read = 0x0704, 241*9d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_write = 0x0705, 242*9d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_post_update = 0x0720, 243*9d26e4fcSRobert Mustacchi 244*9d26e4fcSRobert Mustacchi /* virtualization commands */ 245*9d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_pf = 0x0801, 246*9d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_vf = 0x0802, 247*9d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_peer = 0x0803, 248*9d26e4fcSRobert Mustacchi 249*9d26e4fcSRobert Mustacchi /* alternate structure */ 250*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write = 0x0900, 251*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_indirect = 0x0901, 252*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read = 0x0902, 253*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read_indirect = 0x0903, 254*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_done = 0x0904, 255*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_set_mode = 0x0905, 256*9d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_clear_port = 0x0906, 257*9d26e4fcSRobert Mustacchi 258*9d26e4fcSRobert Mustacchi /* LLDP commands */ 259*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_get_mib = 0x0A00, 260*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_mib = 0x0A01, 261*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_add_tlv = 0x0A02, 262*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_tlv = 0x0A03, 263*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 264*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop = 0x0A05, 265*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_start = 0x0A06, 266*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 267*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 268*9d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 269*9d26e4fcSRobert Mustacchi 270*9d26e4fcSRobert Mustacchi /* Tunnel commands */ 271*9d26e4fcSRobert Mustacchi i40e_aqc_opc_add_udp_tunnel = 0x0B00, 272*9d26e4fcSRobert Mustacchi i40e_aqc_opc_del_udp_tunnel = 0x0B01, 273*9d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 274*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_key = 0x0B02, 275*9d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_lut = 0x0B03, 276*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_key = 0x0B04, 277*9d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_lut = 0x0B05, 278*9d26e4fcSRobert Mustacchi #endif 279*9d26e4fcSRobert Mustacchi 280*9d26e4fcSRobert Mustacchi /* Async Events */ 281*9d26e4fcSRobert Mustacchi i40e_aqc_opc_event_lan_overflow = 0x1001, 282*9d26e4fcSRobert Mustacchi 283*9d26e4fcSRobert Mustacchi /* OEM commands */ 284*9d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_parameter_change = 0xFE00, 285*9d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_device_status_change = 0xFE01, 286*9d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 287*9d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 288*9d26e4fcSRobert Mustacchi 289*9d26e4fcSRobert Mustacchi /* debug commands */ 290*9d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_read_reg = 0xFF03, 291*9d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_write_reg = 0xFF04, 292*9d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_modify_reg = 0xFF07, 293*9d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_dump_internals = 0xFF08, 294*9d26e4fcSRobert Mustacchi }; 295*9d26e4fcSRobert Mustacchi 296*9d26e4fcSRobert Mustacchi /* command structures and indirect data structures */ 297*9d26e4fcSRobert Mustacchi 298*9d26e4fcSRobert Mustacchi /* Structure naming conventions: 299*9d26e4fcSRobert Mustacchi * - no suffix for direct command descriptor structures 300*9d26e4fcSRobert Mustacchi * - _data for indirect sent data 301*9d26e4fcSRobert Mustacchi * - _resp for indirect return data (data which is both will use _data) 302*9d26e4fcSRobert Mustacchi * - _completion for direct return data 303*9d26e4fcSRobert Mustacchi * - _element_ for repeated elements (may also be _data or _resp) 304*9d26e4fcSRobert Mustacchi * 305*9d26e4fcSRobert Mustacchi * Command structures are expected to overlay the params.raw member of the basic 306*9d26e4fcSRobert Mustacchi * descriptor, and as such cannot exceed 16 bytes in length. 307*9d26e4fcSRobert Mustacchi */ 308*9d26e4fcSRobert Mustacchi 309*9d26e4fcSRobert Mustacchi /* This macro is used to generate a compilation error if a structure 310*9d26e4fcSRobert Mustacchi * is not exactly the correct length. It gives a divide by zero error if the 311*9d26e4fcSRobert Mustacchi * structure is not of the correct size, otherwise it creates an enum that is 312*9d26e4fcSRobert Mustacchi * never used. 313*9d26e4fcSRobert Mustacchi */ 314*9d26e4fcSRobert Mustacchi #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 315*9d26e4fcSRobert Mustacchi { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 316*9d26e4fcSRobert Mustacchi 317*9d26e4fcSRobert Mustacchi /* This macro is used extensively to ensure that command structures are 16 318*9d26e4fcSRobert Mustacchi * bytes in length as they have to map to the raw array of that size. 319*9d26e4fcSRobert Mustacchi */ 320*9d26e4fcSRobert Mustacchi #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 321*9d26e4fcSRobert Mustacchi 322*9d26e4fcSRobert Mustacchi /* internal (0x00XX) commands */ 323*9d26e4fcSRobert Mustacchi 324*9d26e4fcSRobert Mustacchi /* Get version (direct 0x0001) */ 325*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_version { 326*9d26e4fcSRobert Mustacchi __le32 rom_ver; 327*9d26e4fcSRobert Mustacchi __le32 fw_build; 328*9d26e4fcSRobert Mustacchi __le16 fw_major; 329*9d26e4fcSRobert Mustacchi __le16 fw_minor; 330*9d26e4fcSRobert Mustacchi __le16 api_major; 331*9d26e4fcSRobert Mustacchi __le16 api_minor; 332*9d26e4fcSRobert Mustacchi }; 333*9d26e4fcSRobert Mustacchi 334*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 335*9d26e4fcSRobert Mustacchi 336*9d26e4fcSRobert Mustacchi /* Send driver version (indirect 0x0002) */ 337*9d26e4fcSRobert Mustacchi struct i40e_aqc_driver_version { 338*9d26e4fcSRobert Mustacchi u8 driver_major_ver; 339*9d26e4fcSRobert Mustacchi u8 driver_minor_ver; 340*9d26e4fcSRobert Mustacchi u8 driver_build_ver; 341*9d26e4fcSRobert Mustacchi u8 driver_subbuild_ver; 342*9d26e4fcSRobert Mustacchi u8 reserved[4]; 343*9d26e4fcSRobert Mustacchi __le32 address_high; 344*9d26e4fcSRobert Mustacchi __le32 address_low; 345*9d26e4fcSRobert Mustacchi }; 346*9d26e4fcSRobert Mustacchi 347*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 348*9d26e4fcSRobert Mustacchi 349*9d26e4fcSRobert Mustacchi /* Queue Shutdown (direct 0x0003) */ 350*9d26e4fcSRobert Mustacchi struct i40e_aqc_queue_shutdown { 351*9d26e4fcSRobert Mustacchi __le32 driver_unloading; 352*9d26e4fcSRobert Mustacchi #define I40E_AQ_DRIVER_UNLOADING 0x1 353*9d26e4fcSRobert Mustacchi u8 reserved[12]; 354*9d26e4fcSRobert Mustacchi }; 355*9d26e4fcSRobert Mustacchi 356*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 357*9d26e4fcSRobert Mustacchi 358*9d26e4fcSRobert Mustacchi /* Set PF context (0x0004, direct) */ 359*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_pf_context { 360*9d26e4fcSRobert Mustacchi u8 pf_id; 361*9d26e4fcSRobert Mustacchi u8 reserved[15]; 362*9d26e4fcSRobert Mustacchi }; 363*9d26e4fcSRobert Mustacchi 364*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 365*9d26e4fcSRobert Mustacchi 366*9d26e4fcSRobert Mustacchi /* Request resource ownership (direct 0x0008) 367*9d26e4fcSRobert Mustacchi * Release resource ownership (direct 0x0009) 368*9d26e4fcSRobert Mustacchi */ 369*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM 1 370*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_SDP 2 371*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_READ 1 372*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 373*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 374*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 375*9d26e4fcSRobert Mustacchi 376*9d26e4fcSRobert Mustacchi struct i40e_aqc_request_resource { 377*9d26e4fcSRobert Mustacchi __le16 resource_id; 378*9d26e4fcSRobert Mustacchi __le16 access_type; 379*9d26e4fcSRobert Mustacchi __le32 timeout; 380*9d26e4fcSRobert Mustacchi __le32 resource_number; 381*9d26e4fcSRobert Mustacchi u8 reserved[4]; 382*9d26e4fcSRobert Mustacchi }; 383*9d26e4fcSRobert Mustacchi 384*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 385*9d26e4fcSRobert Mustacchi 386*9d26e4fcSRobert Mustacchi /* Get function capabilities (indirect 0x000A) 387*9d26e4fcSRobert Mustacchi * Get device capabilities (indirect 0x000B) 388*9d26e4fcSRobert Mustacchi */ 389*9d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilites { 390*9d26e4fcSRobert Mustacchi u8 command_flags; 391*9d26e4fcSRobert Mustacchi #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 392*9d26e4fcSRobert Mustacchi u8 pf_index; 393*9d26e4fcSRobert Mustacchi u8 reserved[2]; 394*9d26e4fcSRobert Mustacchi __le32 count; 395*9d26e4fcSRobert Mustacchi __le32 addr_high; 396*9d26e4fcSRobert Mustacchi __le32 addr_low; 397*9d26e4fcSRobert Mustacchi }; 398*9d26e4fcSRobert Mustacchi 399*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 400*9d26e4fcSRobert Mustacchi 401*9d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilities_element_resp { 402*9d26e4fcSRobert Mustacchi __le16 id; 403*9d26e4fcSRobert Mustacchi u8 major_rev; 404*9d26e4fcSRobert Mustacchi u8 minor_rev; 405*9d26e4fcSRobert Mustacchi __le32 number; 406*9d26e4fcSRobert Mustacchi __le32 logical_id; 407*9d26e4fcSRobert Mustacchi __le32 phys_id; 408*9d26e4fcSRobert Mustacchi u8 reserved[16]; 409*9d26e4fcSRobert Mustacchi }; 410*9d26e4fcSRobert Mustacchi 411*9d26e4fcSRobert Mustacchi /* list of caps */ 412*9d26e4fcSRobert Mustacchi 413*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 414*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 415*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 416*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 417*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 418*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 419*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SRIOV 0x0012 420*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF 0x0013 421*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VMDQ 0x0014 422*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBG 0x0015 423*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBR 0x0016 424*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VSI 0x0017 425*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_DCB 0x0018 426*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FCOE 0x0021 427*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ISCSI 0x0022 428*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RSS 0x0040 429*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RXQ 0x0041 430*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_TXQ 0x0042 431*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MSIX 0x0043 432*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 433*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 434*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_1588 0x0046 435*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_IWARP 0x0051 436*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_LED 0x0061 437*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SDP 0x0062 438*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MDIO 0x0063 439*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLEX10 0x00F1 440*9d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_CEM 0x00F2 441*9d26e4fcSRobert Mustacchi 442*9d26e4fcSRobert Mustacchi /* Set CPPM Configuration (direct 0x0103) */ 443*9d26e4fcSRobert Mustacchi struct i40e_aqc_cppm_configuration { 444*9d26e4fcSRobert Mustacchi __le16 command_flags; 445*9d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_LTRC 0x0800 446*9d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTH 0x1000 447*9d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 448*9d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_HPTC 0x4000 449*9d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMARC 0x8000 450*9d26e4fcSRobert Mustacchi __le16 ttlx; 451*9d26e4fcSRobert Mustacchi __le32 dmacr; 452*9d26e4fcSRobert Mustacchi __le16 dmcth; 453*9d26e4fcSRobert Mustacchi u8 hptc; 454*9d26e4fcSRobert Mustacchi u8 reserved; 455*9d26e4fcSRobert Mustacchi __le32 pfltrc; 456*9d26e4fcSRobert Mustacchi }; 457*9d26e4fcSRobert Mustacchi 458*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 459*9d26e4fcSRobert Mustacchi 460*9d26e4fcSRobert Mustacchi /* Set ARP Proxy command / response (indirect 0x0104) */ 461*9d26e4fcSRobert Mustacchi struct i40e_aqc_arp_proxy_data { 462*9d26e4fcSRobert Mustacchi __le16 command_flags; 463*9d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_INIT_IPV4 0x0008 464*9d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_UNSUP_CTL 0x0010 465*9d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_ENA 0x0020 466*9d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_ADD_IPV4 0x0040 467*9d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_DEL_IPV4 0x0080 468*9d26e4fcSRobert Mustacchi __le16 table_id; 469*9d26e4fcSRobert Mustacchi __le32 pfpm_proxyfc; 470*9d26e4fcSRobert Mustacchi __le32 ip_addr; 471*9d26e4fcSRobert Mustacchi u8 mac_addr[6]; 472*9d26e4fcSRobert Mustacchi u8 reserved[2]; 473*9d26e4fcSRobert Mustacchi }; 474*9d26e4fcSRobert Mustacchi 475*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 476*9d26e4fcSRobert Mustacchi 477*9d26e4fcSRobert Mustacchi /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 478*9d26e4fcSRobert Mustacchi struct i40e_aqc_ns_proxy_data { 479*9d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_0; 480*9d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_1; 481*9d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_0; 482*9d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_1; 483*9d26e4fcSRobert Mustacchi __le16 control; 484*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_0 0x0100 485*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_0 0x0200 486*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_1 0x0400 487*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_1 0x0800 488*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 489*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 490*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 491*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 492*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 493*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 494*9d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 495*9d26e4fcSRobert Mustacchi u8 mac_addr_0[6]; 496*9d26e4fcSRobert Mustacchi u8 mac_addr_1[6]; 497*9d26e4fcSRobert Mustacchi u8 local_mac_addr[6]; 498*9d26e4fcSRobert Mustacchi u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 499*9d26e4fcSRobert Mustacchi u8 ipv6_addr_1[16]; 500*9d26e4fcSRobert Mustacchi }; 501*9d26e4fcSRobert Mustacchi 502*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 503*9d26e4fcSRobert Mustacchi 504*9d26e4fcSRobert Mustacchi /* Manage LAA Command (0x0106) - obsolete */ 505*9d26e4fcSRobert Mustacchi struct i40e_aqc_mng_laa { 506*9d26e4fcSRobert Mustacchi __le16 command_flags; 507*9d26e4fcSRobert Mustacchi #define I40E_AQ_LAA_FLAG_WR 0x8000 508*9d26e4fcSRobert Mustacchi u8 reserved[2]; 509*9d26e4fcSRobert Mustacchi __le32 sal; 510*9d26e4fcSRobert Mustacchi __le16 sah; 511*9d26e4fcSRobert Mustacchi u8 reserved2[6]; 512*9d26e4fcSRobert Mustacchi }; 513*9d26e4fcSRobert Mustacchi 514*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 515*9d26e4fcSRobert Mustacchi 516*9d26e4fcSRobert Mustacchi /* Manage MAC Address Read Command (indirect 0x0107) */ 517*9d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read { 518*9d26e4fcSRobert Mustacchi __le16 command_flags; 519*9d26e4fcSRobert Mustacchi #define I40E_AQC_LAN_ADDR_VALID 0x10 520*9d26e4fcSRobert Mustacchi #define I40E_AQC_SAN_ADDR_VALID 0x20 521*9d26e4fcSRobert Mustacchi #define I40E_AQC_PORT_ADDR_VALID 0x40 522*9d26e4fcSRobert Mustacchi #define I40E_AQC_WOL_ADDR_VALID 0x80 523*9d26e4fcSRobert Mustacchi #define I40E_AQC_MC_MAG_EN_VALID 0x100 524*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADDR_VALID_MASK 0x1F0 525*9d26e4fcSRobert Mustacchi u8 reserved[6]; 526*9d26e4fcSRobert Mustacchi __le32 addr_high; 527*9d26e4fcSRobert Mustacchi __le32 addr_low; 528*9d26e4fcSRobert Mustacchi }; 529*9d26e4fcSRobert Mustacchi 530*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 531*9d26e4fcSRobert Mustacchi 532*9d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read_data { 533*9d26e4fcSRobert Mustacchi u8 pf_lan_mac[6]; 534*9d26e4fcSRobert Mustacchi u8 pf_san_mac[6]; 535*9d26e4fcSRobert Mustacchi u8 port_mac[6]; 536*9d26e4fcSRobert Mustacchi u8 pf_wol_mac[6]; 537*9d26e4fcSRobert Mustacchi }; 538*9d26e4fcSRobert Mustacchi 539*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 540*9d26e4fcSRobert Mustacchi 541*9d26e4fcSRobert Mustacchi /* Manage MAC Address Write Command (0x0108) */ 542*9d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_write { 543*9d26e4fcSRobert Mustacchi __le16 command_flags; 544*9d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 545*9d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 546*9d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_PORT 0x8000 547*9d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 548*9d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_MASK 0xC000 549*9d26e4fcSRobert Mustacchi 550*9d26e4fcSRobert Mustacchi __le16 mac_sah; 551*9d26e4fcSRobert Mustacchi __le32 mac_sal; 552*9d26e4fcSRobert Mustacchi u8 reserved[8]; 553*9d26e4fcSRobert Mustacchi }; 554*9d26e4fcSRobert Mustacchi 555*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 556*9d26e4fcSRobert Mustacchi 557*9d26e4fcSRobert Mustacchi /* PXE commands (0x011x) */ 558*9d26e4fcSRobert Mustacchi 559*9d26e4fcSRobert Mustacchi /* Clear PXE Command and response (direct 0x0110) */ 560*9d26e4fcSRobert Mustacchi struct i40e_aqc_clear_pxe { 561*9d26e4fcSRobert Mustacchi u8 rx_cnt; 562*9d26e4fcSRobert Mustacchi u8 reserved[15]; 563*9d26e4fcSRobert Mustacchi }; 564*9d26e4fcSRobert Mustacchi 565*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 566*9d26e4fcSRobert Mustacchi 567*9d26e4fcSRobert Mustacchi /* Switch configuration commands (0x02xx) */ 568*9d26e4fcSRobert Mustacchi 569*9d26e4fcSRobert Mustacchi /* Used by many indirect commands that only pass an seid and a buffer in the 570*9d26e4fcSRobert Mustacchi * command 571*9d26e4fcSRobert Mustacchi */ 572*9d26e4fcSRobert Mustacchi struct i40e_aqc_switch_seid { 573*9d26e4fcSRobert Mustacchi __le16 seid; 574*9d26e4fcSRobert Mustacchi u8 reserved[6]; 575*9d26e4fcSRobert Mustacchi __le32 addr_high; 576*9d26e4fcSRobert Mustacchi __le32 addr_low; 577*9d26e4fcSRobert Mustacchi }; 578*9d26e4fcSRobert Mustacchi 579*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 580*9d26e4fcSRobert Mustacchi 581*9d26e4fcSRobert Mustacchi /* Get Switch Configuration command (indirect 0x0200) 582*9d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 583*9d26e4fcSRobert Mustacchi */ 584*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp { 585*9d26e4fcSRobert Mustacchi __le16 num_reported; 586*9d26e4fcSRobert Mustacchi __le16 num_total; 587*9d26e4fcSRobert Mustacchi u8 reserved[12]; 588*9d26e4fcSRobert Mustacchi }; 589*9d26e4fcSRobert Mustacchi 590*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 591*9d26e4fcSRobert Mustacchi 592*9d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp { 593*9d26e4fcSRobert Mustacchi u8 element_type; 594*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_MAC 1 595*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PF 2 596*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VF 3 597*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_EMP 4 598*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_BMC 5 599*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PV 16 600*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VEB 17 601*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PA 18 602*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VSI 19 603*9d26e4fcSRobert Mustacchi u8 revision; 604*9d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_REV_1 1 605*9d26e4fcSRobert Mustacchi __le16 seid; 606*9d26e4fcSRobert Mustacchi __le16 uplink_seid; 607*9d26e4fcSRobert Mustacchi __le16 downlink_seid; 608*9d26e4fcSRobert Mustacchi u8 reserved[3]; 609*9d26e4fcSRobert Mustacchi u8 connection_type; 610*9d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_REGULAR 0x1 611*9d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 612*9d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_CASCADED 0x3 613*9d26e4fcSRobert Mustacchi __le16 scheduler_id; 614*9d26e4fcSRobert Mustacchi __le16 element_info; 615*9d26e4fcSRobert Mustacchi }; 616*9d26e4fcSRobert Mustacchi 617*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 618*9d26e4fcSRobert Mustacchi 619*9d26e4fcSRobert Mustacchi /* Get Switch Configuration (indirect 0x0200) 620*9d26e4fcSRobert Mustacchi * an array of elements are returned in the response buffer 621*9d26e4fcSRobert Mustacchi * the first in the array is the header, remainder are elements 622*9d26e4fcSRobert Mustacchi */ 623*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_resp { 624*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp header; 625*9d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp element[1]; 626*9d26e4fcSRobert Mustacchi }; 627*9d26e4fcSRobert Mustacchi 628*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 629*9d26e4fcSRobert Mustacchi 630*9d26e4fcSRobert Mustacchi /* Add Statistics (direct 0x0201) 631*9d26e4fcSRobert Mustacchi * Remove Statistics (direct 0x0202) 632*9d26e4fcSRobert Mustacchi */ 633*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_statistics { 634*9d26e4fcSRobert Mustacchi __le16 seid; 635*9d26e4fcSRobert Mustacchi __le16 vlan; 636*9d26e4fcSRobert Mustacchi __le16 stat_index; 637*9d26e4fcSRobert Mustacchi u8 reserved[10]; 638*9d26e4fcSRobert Mustacchi }; 639*9d26e4fcSRobert Mustacchi 640*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 641*9d26e4fcSRobert Mustacchi 642*9d26e4fcSRobert Mustacchi /* Set Port Parameters command (direct 0x0203) */ 643*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_port_parameters { 644*9d26e4fcSRobert Mustacchi __le16 command_flags; 645*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 646*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 647*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 648*9d26e4fcSRobert Mustacchi __le16 bad_frame_vsi; 649*9d26e4fcSRobert Mustacchi __le16 default_seid; /* reserved for command */ 650*9d26e4fcSRobert Mustacchi u8 reserved[10]; 651*9d26e4fcSRobert Mustacchi }; 652*9d26e4fcSRobert Mustacchi 653*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 654*9d26e4fcSRobert Mustacchi 655*9d26e4fcSRobert Mustacchi /* Get Switch Resource Allocation (indirect 0x0204) */ 656*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_resource_alloc { 657*9d26e4fcSRobert Mustacchi u8 num_entries; /* reserved for command */ 658*9d26e4fcSRobert Mustacchi u8 reserved[7]; 659*9d26e4fcSRobert Mustacchi __le32 addr_high; 660*9d26e4fcSRobert Mustacchi __le32 addr_low; 661*9d26e4fcSRobert Mustacchi }; 662*9d26e4fcSRobert Mustacchi 663*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 664*9d26e4fcSRobert Mustacchi 665*9d26e4fcSRobert Mustacchi /* expect an array of these structs in the response buffer */ 666*9d26e4fcSRobert Mustacchi struct i40e_aqc_switch_resource_alloc_element_resp { 667*9d26e4fcSRobert Mustacchi u8 resource_type; 668*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 669*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 670*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 671*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 672*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 673*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 674*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 675*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 676*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 677*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 678*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 679*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 680*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 681*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 682*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 683*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 684*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 685*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 686*9d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 687*9d26e4fcSRobert Mustacchi u8 reserved1; 688*9d26e4fcSRobert Mustacchi __le16 guaranteed; 689*9d26e4fcSRobert Mustacchi __le16 total; 690*9d26e4fcSRobert Mustacchi __le16 used; 691*9d26e4fcSRobert Mustacchi __le16 total_unalloced; 692*9d26e4fcSRobert Mustacchi u8 reserved2[6]; 693*9d26e4fcSRobert Mustacchi }; 694*9d26e4fcSRobert Mustacchi 695*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 696*9d26e4fcSRobert Mustacchi 697*9d26e4fcSRobert Mustacchi /* Add VSI (indirect 0x0210) 698*9d26e4fcSRobert Mustacchi * this indirect command uses struct i40e_aqc_vsi_properties_data 699*9d26e4fcSRobert Mustacchi * as the indirect buffer (128 bytes) 700*9d26e4fcSRobert Mustacchi * 701*9d26e4fcSRobert Mustacchi * Update VSI (indirect 0x211) 702*9d26e4fcSRobert Mustacchi * uses the same data structure as Add VSI 703*9d26e4fcSRobert Mustacchi * 704*9d26e4fcSRobert Mustacchi * Get VSI (indirect 0x0212) 705*9d26e4fcSRobert Mustacchi * uses the same completion and data structure as Add VSI 706*9d26e4fcSRobert Mustacchi */ 707*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi { 708*9d26e4fcSRobert Mustacchi __le16 uplink_seid; 709*9d26e4fcSRobert Mustacchi u8 connection_type; 710*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 711*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 712*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 713*9d26e4fcSRobert Mustacchi u8 reserved1; 714*9d26e4fcSRobert Mustacchi u8 vf_id; 715*9d26e4fcSRobert Mustacchi u8 reserved2; 716*9d26e4fcSRobert Mustacchi __le16 vsi_flags; 717*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_SHIFT 0x0 718*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 719*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VF 0x0 720*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 721*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_PF 0x2 722*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 723*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 724*9d26e4fcSRobert Mustacchi __le32 addr_high; 725*9d26e4fcSRobert Mustacchi __le32 addr_low; 726*9d26e4fcSRobert Mustacchi }; 727*9d26e4fcSRobert Mustacchi 728*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 729*9d26e4fcSRobert Mustacchi 730*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi_completion { 731*9d26e4fcSRobert Mustacchi __le16 seid; 732*9d26e4fcSRobert Mustacchi __le16 vsi_number; 733*9d26e4fcSRobert Mustacchi __le16 vsi_used; 734*9d26e4fcSRobert Mustacchi __le16 vsi_free; 735*9d26e4fcSRobert Mustacchi __le32 addr_high; 736*9d26e4fcSRobert Mustacchi __le32 addr_low; 737*9d26e4fcSRobert Mustacchi }; 738*9d26e4fcSRobert Mustacchi 739*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 740*9d26e4fcSRobert Mustacchi 741*9d26e4fcSRobert Mustacchi struct i40e_aqc_vsi_properties_data { 742*9d26e4fcSRobert Mustacchi /* first 96 byte are written by SW */ 743*9d26e4fcSRobert Mustacchi __le16 valid_sections; 744*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 745*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 746*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 747*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 748*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 749*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 750*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 751*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 752*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 753*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 754*9d26e4fcSRobert Mustacchi /* switch section */ 755*9d26e4fcSRobert Mustacchi __le16 switch_id; /* 12bit id combined with flags below */ 756*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 757*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 758*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 759*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 760*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 761*9d26e4fcSRobert Mustacchi u8 sw_reserved[2]; 762*9d26e4fcSRobert Mustacchi /* security section */ 763*9d26e4fcSRobert Mustacchi u8 sec_flags; 764*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 765*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 766*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 767*9d26e4fcSRobert Mustacchi u8 sec_reserved; 768*9d26e4fcSRobert Mustacchi /* VLAN section */ 769*9d26e4fcSRobert Mustacchi __le16 pvid; /* VLANS include priority bits */ 770*9d26e4fcSRobert Mustacchi __le16 fcoe_pvid; 771*9d26e4fcSRobert Mustacchi u8 port_vlan_flags; 772*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 773*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 774*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_MODE_SHIFT) 775*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 776*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 777*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 778*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 779*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 780*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 781*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 782*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 783*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 784*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 785*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 786*9d26e4fcSRobert Mustacchi u8 pvlan_reserved[3]; 787*9d26e4fcSRobert Mustacchi /* ingress egress up sections */ 788*9d26e4fcSRobert Mustacchi __le32 ingress_table; /* bitmap, 3 bits per up */ 789*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 790*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 791*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 792*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 793*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 794*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 795*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 796*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 797*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 798*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 799*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 800*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 801*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 802*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 803*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 804*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 805*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 806*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 807*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 808*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 809*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 810*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 811*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 812*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 813*9d26e4fcSRobert Mustacchi __le32 egress_table; /* same defines as for ingress table */ 814*9d26e4fcSRobert Mustacchi /* cascaded PV section */ 815*9d26e4fcSRobert Mustacchi __le16 cas_pv_tag; 816*9d26e4fcSRobert Mustacchi u8 cas_pv_flags; 817*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 818*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 819*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 820*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 821*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 822*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 823*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 824*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 825*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 826*9d26e4fcSRobert Mustacchi u8 cas_pv_reserved; 827*9d26e4fcSRobert Mustacchi /* queue mapping section */ 828*9d26e4fcSRobert Mustacchi __le16 mapping_flags; 829*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 830*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 831*9d26e4fcSRobert Mustacchi __le16 queue_mapping[16]; 832*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 833*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 834*9d26e4fcSRobert Mustacchi __le16 tc_mapping[8]; 835*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 836*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 837*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 838*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 839*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 840*9d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 841*9d26e4fcSRobert Mustacchi /* queueing option section */ 842*9d26e4fcSRobert Mustacchi u8 queueing_opt_flags; 843*9d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 844*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 845*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 846*9d26e4fcSRobert Mustacchi #endif 847*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 848*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 849*9d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 850*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 851*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 852*9d26e4fcSRobert Mustacchi #endif 853*9d26e4fcSRobert Mustacchi u8 queueing_opt_reserved[3]; 854*9d26e4fcSRobert Mustacchi /* scheduler section */ 855*9d26e4fcSRobert Mustacchi u8 up_enable_bits; 856*9d26e4fcSRobert Mustacchi u8 sched_reserved; 857*9d26e4fcSRobert Mustacchi /* outer up section */ 858*9d26e4fcSRobert Mustacchi __le32 outer_up_table; /* same structure and defines as ingress table */ 859*9d26e4fcSRobert Mustacchi u8 cmd_reserved[8]; 860*9d26e4fcSRobert Mustacchi /* last 32 bytes are written by FW */ 861*9d26e4fcSRobert Mustacchi __le16 qs_handle[8]; 862*9d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 863*9d26e4fcSRobert Mustacchi __le16 stat_counter_idx; 864*9d26e4fcSRobert Mustacchi __le16 sched_id; 865*9d26e4fcSRobert Mustacchi u8 resp_reserved[12]; 866*9d26e4fcSRobert Mustacchi }; 867*9d26e4fcSRobert Mustacchi 868*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 869*9d26e4fcSRobert Mustacchi 870*9d26e4fcSRobert Mustacchi /* Add Port Virtualizer (direct 0x0220) 871*9d26e4fcSRobert Mustacchi * also used for update PV (direct 0x0221) but only flags are used 872*9d26e4fcSRobert Mustacchi * (IS_CTRL_PORT only works on add PV) 873*9d26e4fcSRobert Mustacchi */ 874*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv { 875*9d26e4fcSRobert Mustacchi __le16 command_flags; 876*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 877*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 878*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 879*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 880*9d26e4fcSRobert Mustacchi __le16 uplink_seid; 881*9d26e4fcSRobert Mustacchi __le16 connected_seid; 882*9d26e4fcSRobert Mustacchi u8 reserved[10]; 883*9d26e4fcSRobert Mustacchi }; 884*9d26e4fcSRobert Mustacchi 885*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 886*9d26e4fcSRobert Mustacchi 887*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv_completion { 888*9d26e4fcSRobert Mustacchi /* reserved for update; for add also encodes error if rc == ENOSPC */ 889*9d26e4fcSRobert Mustacchi __le16 pv_seid; 890*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 891*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 892*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 893*9d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 894*9d26e4fcSRobert Mustacchi u8 reserved[14]; 895*9d26e4fcSRobert Mustacchi }; 896*9d26e4fcSRobert Mustacchi 897*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 898*9d26e4fcSRobert Mustacchi 899*9d26e4fcSRobert Mustacchi /* Get PV Params (direct 0x0222) 900*9d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 901*9d26e4fcSRobert Mustacchi */ 902*9d26e4fcSRobert Mustacchi 903*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_pv_params_completion { 904*9d26e4fcSRobert Mustacchi __le16 seid; 905*9d26e4fcSRobert Mustacchi __le16 default_stag; 906*9d26e4fcSRobert Mustacchi __le16 pv_flags; /* same flags as add_pv */ 907*9d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_PV_TYPE 0x1 908*9d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 909*9d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 910*9d26e4fcSRobert Mustacchi u8 reserved[8]; 911*9d26e4fcSRobert Mustacchi __le16 default_port_seid; 912*9d26e4fcSRobert Mustacchi }; 913*9d26e4fcSRobert Mustacchi 914*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 915*9d26e4fcSRobert Mustacchi 916*9d26e4fcSRobert Mustacchi /* Add VEB (direct 0x0230) */ 917*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb { 918*9d26e4fcSRobert Mustacchi __le16 uplink_seid; 919*9d26e4fcSRobert Mustacchi __le16 downlink_seid; 920*9d26e4fcSRobert Mustacchi __le16 veb_flags; 921*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_FLOATING 0x1 922*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 923*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 924*9d26e4fcSRobert Mustacchi I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 925*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 926*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 927*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 928*9d26e4fcSRobert Mustacchi u8 enable_tcs; 929*9d26e4fcSRobert Mustacchi u8 reserved[9]; 930*9d26e4fcSRobert Mustacchi }; 931*9d26e4fcSRobert Mustacchi 932*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 933*9d26e4fcSRobert Mustacchi 934*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb_completion { 935*9d26e4fcSRobert Mustacchi u8 reserved[6]; 936*9d26e4fcSRobert Mustacchi __le16 switch_seid; 937*9d26e4fcSRobert Mustacchi /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 938*9d26e4fcSRobert Mustacchi __le16 veb_seid; 939*9d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 940*9d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 941*9d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 942*9d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 943*9d26e4fcSRobert Mustacchi __le16 statistic_index; 944*9d26e4fcSRobert Mustacchi __le16 vebs_used; 945*9d26e4fcSRobert Mustacchi __le16 vebs_free; 946*9d26e4fcSRobert Mustacchi }; 947*9d26e4fcSRobert Mustacchi 948*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 949*9d26e4fcSRobert Mustacchi 950*9d26e4fcSRobert Mustacchi /* Get VEB Parameters (direct 0x0232) 951*9d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 952*9d26e4fcSRobert Mustacchi */ 953*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_veb_parameters_completion { 954*9d26e4fcSRobert Mustacchi __le16 seid; 955*9d26e4fcSRobert Mustacchi __le16 switch_id; 956*9d26e4fcSRobert Mustacchi __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 957*9d26e4fcSRobert Mustacchi __le16 statistic_index; 958*9d26e4fcSRobert Mustacchi __le16 vebs_used; 959*9d26e4fcSRobert Mustacchi __le16 vebs_free; 960*9d26e4fcSRobert Mustacchi u8 reserved[4]; 961*9d26e4fcSRobert Mustacchi }; 962*9d26e4fcSRobert Mustacchi 963*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 964*9d26e4fcSRobert Mustacchi 965*9d26e4fcSRobert Mustacchi /* Delete Element (direct 0x0243) 966*9d26e4fcSRobert Mustacchi * uses the generic i40e_aqc_switch_seid 967*9d26e4fcSRobert Mustacchi */ 968*9d26e4fcSRobert Mustacchi 969*9d26e4fcSRobert Mustacchi /* Add MAC-VLAN (indirect 0x0250) */ 970*9d26e4fcSRobert Mustacchi 971*9d26e4fcSRobert Mustacchi /* used for the command for most vlan commands */ 972*9d26e4fcSRobert Mustacchi struct i40e_aqc_macvlan { 973*9d26e4fcSRobert Mustacchi __le16 num_addresses; 974*9d26e4fcSRobert Mustacchi __le16 seid[3]; 975*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 976*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 977*9d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 978*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 979*9d26e4fcSRobert Mustacchi __le32 addr_high; 980*9d26e4fcSRobert Mustacchi __le32 addr_low; 981*9d26e4fcSRobert Mustacchi }; 982*9d26e4fcSRobert Mustacchi 983*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 984*9d26e4fcSRobert Mustacchi 985*9d26e4fcSRobert Mustacchi /* indirect data for command and response */ 986*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_macvlan_element_data { 987*9d26e4fcSRobert Mustacchi u8 mac_addr[6]; 988*9d26e4fcSRobert Mustacchi __le16 vlan_tag; 989*9d26e4fcSRobert Mustacchi __le16 flags; 990*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 991*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 992*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 993*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 994*9d26e4fcSRobert Mustacchi __le16 queue_number; 995*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 996*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 997*9d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 998*9d26e4fcSRobert Mustacchi /* response section */ 999*9d26e4fcSRobert Mustacchi u8 match_method; 1000*9d26e4fcSRobert Mustacchi #define I40E_AQC_MM_PERFECT_MATCH 0x01 1001*9d26e4fcSRobert Mustacchi #define I40E_AQC_MM_HASH_MATCH 0x02 1002*9d26e4fcSRobert Mustacchi #define I40E_AQC_MM_ERR_NO_RES 0xFF 1003*9d26e4fcSRobert Mustacchi u8 reserved1[3]; 1004*9d26e4fcSRobert Mustacchi }; 1005*9d26e4fcSRobert Mustacchi 1006*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_macvlan_completion { 1007*9d26e4fcSRobert Mustacchi __le16 perfect_mac_used; 1008*9d26e4fcSRobert Mustacchi __le16 perfect_mac_free; 1009*9d26e4fcSRobert Mustacchi __le16 unicast_hash_free; 1010*9d26e4fcSRobert Mustacchi __le16 multicast_hash_free; 1011*9d26e4fcSRobert Mustacchi __le32 addr_high; 1012*9d26e4fcSRobert Mustacchi __le32 addr_low; 1013*9d26e4fcSRobert Mustacchi }; 1014*9d26e4fcSRobert Mustacchi 1015*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1016*9d26e4fcSRobert Mustacchi 1017*9d26e4fcSRobert Mustacchi /* Remove MAC-VLAN (indirect 0x0251) 1018*9d26e4fcSRobert Mustacchi * uses i40e_aqc_macvlan for the descriptor 1019*9d26e4fcSRobert Mustacchi * data points to an array of num_addresses of elements 1020*9d26e4fcSRobert Mustacchi */ 1021*9d26e4fcSRobert Mustacchi 1022*9d26e4fcSRobert Mustacchi struct i40e_aqc_remove_macvlan_element_data { 1023*9d26e4fcSRobert Mustacchi u8 mac_addr[6]; 1024*9d26e4fcSRobert Mustacchi __le16 vlan_tag; 1025*9d26e4fcSRobert Mustacchi u8 flags; 1026*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1027*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1028*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1029*9d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1030*9d26e4fcSRobert Mustacchi u8 reserved[3]; 1031*9d26e4fcSRobert Mustacchi /* reply section */ 1032*9d26e4fcSRobert Mustacchi u8 error_code; 1033*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1034*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1035*9d26e4fcSRobert Mustacchi u8 reply_reserved[3]; 1036*9d26e4fcSRobert Mustacchi }; 1037*9d26e4fcSRobert Mustacchi 1038*9d26e4fcSRobert Mustacchi /* Add VLAN (indirect 0x0252) 1039*9d26e4fcSRobert Mustacchi * Remove VLAN (indirect 0x0253) 1040*9d26e4fcSRobert Mustacchi * use the generic i40e_aqc_macvlan for the command 1041*9d26e4fcSRobert Mustacchi */ 1042*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_element_data { 1043*9d26e4fcSRobert Mustacchi __le16 vlan_tag; 1044*9d26e4fcSRobert Mustacchi u8 vlan_flags; 1045*9d26e4fcSRobert Mustacchi /* flags for add VLAN */ 1046*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1047*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1048*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1049*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1050*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1051*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1052*9d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1053*9d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1054*9d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1055*9d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1056*9d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1057*9d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1058*9d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 1059*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1060*9d26e4fcSRobert Mustacchi u8 reserved; 1061*9d26e4fcSRobert Mustacchi u8 result; 1062*9d26e4fcSRobert Mustacchi /* flags for add VLAN */ 1063*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1064*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1065*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1066*9d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 1067*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1068*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1069*9d26e4fcSRobert Mustacchi u8 reserved1[3]; 1070*9d26e4fcSRobert Mustacchi }; 1071*9d26e4fcSRobert Mustacchi 1072*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_completion { 1073*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1074*9d26e4fcSRobert Mustacchi __le16 vlans_used; 1075*9d26e4fcSRobert Mustacchi __le16 vlans_free; 1076*9d26e4fcSRobert Mustacchi __le32 addr_high; 1077*9d26e4fcSRobert Mustacchi __le32 addr_low; 1078*9d26e4fcSRobert Mustacchi }; 1079*9d26e4fcSRobert Mustacchi 1080*9d26e4fcSRobert Mustacchi /* Set VSI Promiscuous Modes (direct 0x0254) */ 1081*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_vsi_promiscuous_modes { 1082*9d26e4fcSRobert Mustacchi __le16 promiscuous_flags; 1083*9d26e4fcSRobert Mustacchi __le16 valid_flags; 1084*9d26e4fcSRobert Mustacchi /* flags used for both fields above */ 1085*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1086*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1087*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1088*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_DEFAULT 0x08 1089*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1090*9d26e4fcSRobert Mustacchi __le16 seid; 1091*9d26e4fcSRobert Mustacchi #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1092*9d26e4fcSRobert Mustacchi __le16 vlan_tag; 1093*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1094*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1095*9d26e4fcSRobert Mustacchi u8 reserved[8]; 1096*9d26e4fcSRobert Mustacchi }; 1097*9d26e4fcSRobert Mustacchi 1098*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1099*9d26e4fcSRobert Mustacchi 1100*9d26e4fcSRobert Mustacchi /* Add S/E-tag command (direct 0x0255) 1101*9d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 1102*9d26e4fcSRobert Mustacchi */ 1103*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_tag { 1104*9d26e4fcSRobert Mustacchi __le16 flags; 1105*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1106*9d26e4fcSRobert Mustacchi __le16 seid; 1107*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1108*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1109*9d26e4fcSRobert Mustacchi I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1110*9d26e4fcSRobert Mustacchi __le16 tag; 1111*9d26e4fcSRobert Mustacchi __le16 queue_number; 1112*9d26e4fcSRobert Mustacchi u8 reserved[8]; 1113*9d26e4fcSRobert Mustacchi }; 1114*9d26e4fcSRobert Mustacchi 1115*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1116*9d26e4fcSRobert Mustacchi 1117*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_tag_completion { 1118*9d26e4fcSRobert Mustacchi u8 reserved[12]; 1119*9d26e4fcSRobert Mustacchi __le16 tags_used; 1120*9d26e4fcSRobert Mustacchi __le16 tags_free; 1121*9d26e4fcSRobert Mustacchi }; 1122*9d26e4fcSRobert Mustacchi 1123*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1124*9d26e4fcSRobert Mustacchi 1125*9d26e4fcSRobert Mustacchi /* Remove S/E-tag command (direct 0x0256) 1126*9d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 1127*9d26e4fcSRobert Mustacchi */ 1128*9d26e4fcSRobert Mustacchi struct i40e_aqc_remove_tag { 1129*9d26e4fcSRobert Mustacchi __le16 seid; 1130*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1131*9d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1132*9d26e4fcSRobert Mustacchi I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1133*9d26e4fcSRobert Mustacchi __le16 tag; 1134*9d26e4fcSRobert Mustacchi u8 reserved[12]; 1135*9d26e4fcSRobert Mustacchi }; 1136*9d26e4fcSRobert Mustacchi 1137*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1138*9d26e4fcSRobert Mustacchi 1139*9d26e4fcSRobert Mustacchi /* Add multicast E-Tag (direct 0x0257) 1140*9d26e4fcSRobert Mustacchi * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1141*9d26e4fcSRobert Mustacchi * and no external data 1142*9d26e4fcSRobert Mustacchi */ 1143*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag { 1144*9d26e4fcSRobert Mustacchi __le16 pv_seid; 1145*9d26e4fcSRobert Mustacchi __le16 etag; 1146*9d26e4fcSRobert Mustacchi u8 num_unicast_etags; 1147*9d26e4fcSRobert Mustacchi u8 reserved[3]; 1148*9d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte s-tags */ 1149*9d26e4fcSRobert Mustacchi __le32 addr_low; 1150*9d26e4fcSRobert Mustacchi }; 1151*9d26e4fcSRobert Mustacchi 1152*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1153*9d26e4fcSRobert Mustacchi 1154*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag_completion { 1155*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1156*9d26e4fcSRobert Mustacchi __le16 mcast_etags_used; 1157*9d26e4fcSRobert Mustacchi __le16 mcast_etags_free; 1158*9d26e4fcSRobert Mustacchi __le32 addr_high; 1159*9d26e4fcSRobert Mustacchi __le32 addr_low; 1160*9d26e4fcSRobert Mustacchi 1161*9d26e4fcSRobert Mustacchi }; 1162*9d26e4fcSRobert Mustacchi 1163*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1164*9d26e4fcSRobert Mustacchi 1165*9d26e4fcSRobert Mustacchi /* Update S/E-Tag (direct 0x0259) */ 1166*9d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag { 1167*9d26e4fcSRobert Mustacchi __le16 seid; 1168*9d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1169*9d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1170*9d26e4fcSRobert Mustacchi I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1171*9d26e4fcSRobert Mustacchi __le16 old_tag; 1172*9d26e4fcSRobert Mustacchi __le16 new_tag; 1173*9d26e4fcSRobert Mustacchi u8 reserved[10]; 1174*9d26e4fcSRobert Mustacchi }; 1175*9d26e4fcSRobert Mustacchi 1176*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1177*9d26e4fcSRobert Mustacchi 1178*9d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag_completion { 1179*9d26e4fcSRobert Mustacchi u8 reserved[12]; 1180*9d26e4fcSRobert Mustacchi __le16 tags_used; 1181*9d26e4fcSRobert Mustacchi __le16 tags_free; 1182*9d26e4fcSRobert Mustacchi }; 1183*9d26e4fcSRobert Mustacchi 1184*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1185*9d26e4fcSRobert Mustacchi 1186*9d26e4fcSRobert Mustacchi /* Add Control Packet filter (direct 0x025A) 1187*9d26e4fcSRobert Mustacchi * Remove Control Packet filter (direct 0x025B) 1188*9d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_oveb_cloud, 1189*9d26e4fcSRobert Mustacchi * and the generic direct completion structure 1190*9d26e4fcSRobert Mustacchi */ 1191*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter { 1192*9d26e4fcSRobert Mustacchi u8 mac[6]; 1193*9d26e4fcSRobert Mustacchi __le16 etype; 1194*9d26e4fcSRobert Mustacchi __le16 flags; 1195*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1196*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1197*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1198*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1199*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1200*9d26e4fcSRobert Mustacchi __le16 seid; 1201*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1202*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1203*9d26e4fcSRobert Mustacchi I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1204*9d26e4fcSRobert Mustacchi __le16 queue; 1205*9d26e4fcSRobert Mustacchi u8 reserved[2]; 1206*9d26e4fcSRobert Mustacchi }; 1207*9d26e4fcSRobert Mustacchi 1208*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1209*9d26e4fcSRobert Mustacchi 1210*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter_completion { 1211*9d26e4fcSRobert Mustacchi __le16 mac_etype_used; 1212*9d26e4fcSRobert Mustacchi __le16 etype_used; 1213*9d26e4fcSRobert Mustacchi __le16 mac_etype_free; 1214*9d26e4fcSRobert Mustacchi __le16 etype_free; 1215*9d26e4fcSRobert Mustacchi u8 reserved[8]; 1216*9d26e4fcSRobert Mustacchi }; 1217*9d26e4fcSRobert Mustacchi 1218*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1219*9d26e4fcSRobert Mustacchi 1220*9d26e4fcSRobert Mustacchi /* Add Cloud filters (indirect 0x025C) 1221*9d26e4fcSRobert Mustacchi * Remove Cloud filters (indirect 0x025D) 1222*9d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_remove_cloud_filters, 1223*9d26e4fcSRobert Mustacchi * and the generic indirect completion structure 1224*9d26e4fcSRobert Mustacchi */ 1225*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters { 1226*9d26e4fcSRobert Mustacchi u8 num_filters; 1227*9d26e4fcSRobert Mustacchi u8 reserved; 1228*9d26e4fcSRobert Mustacchi __le16 seid; 1229*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1230*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1231*9d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1232*9d26e4fcSRobert Mustacchi u8 reserved2[4]; 1233*9d26e4fcSRobert Mustacchi __le32 addr_high; 1234*9d26e4fcSRobert Mustacchi __le32 addr_low; 1235*9d26e4fcSRobert Mustacchi }; 1236*9d26e4fcSRobert Mustacchi 1237*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1238*9d26e4fcSRobert Mustacchi 1239*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters_element_data { 1240*9d26e4fcSRobert Mustacchi u8 outer_mac[6]; 1241*9d26e4fcSRobert Mustacchi u8 inner_mac[6]; 1242*9d26e4fcSRobert Mustacchi __le16 inner_vlan; 1243*9d26e4fcSRobert Mustacchi union { 1244*9d26e4fcSRobert Mustacchi struct { 1245*9d26e4fcSRobert Mustacchi u8 reserved[12]; 1246*9d26e4fcSRobert Mustacchi u8 data[4]; 1247*9d26e4fcSRobert Mustacchi } v4; 1248*9d26e4fcSRobert Mustacchi struct { 1249*9d26e4fcSRobert Mustacchi u8 data[16]; 1250*9d26e4fcSRobert Mustacchi } v6; 1251*9d26e4fcSRobert Mustacchi } ipaddr; 1252*9d26e4fcSRobert Mustacchi __le16 flags; 1253*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1254*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1255*9d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1256*9d26e4fcSRobert Mustacchi /* 0x0000 reserved */ 1257*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1258*9d26e4fcSRobert Mustacchi /* 0x0002 reserved */ 1259*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1260*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1261*9d26e4fcSRobert Mustacchi /* 0x0005 reserved */ 1262*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1263*9d26e4fcSRobert Mustacchi /* 0x0007 reserved */ 1264*9d26e4fcSRobert Mustacchi /* 0x0008 reserved */ 1265*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1266*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1267*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1268*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1269*9d26e4fcSRobert Mustacchi 1270*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1271*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1272*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1273*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1274*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1275*9d26e4fcSRobert Mustacchi 1276*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1277*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1278*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1279*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1280*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1281*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1282*9d26e4fcSRobert Mustacchi 1283*9d26e4fcSRobert Mustacchi __le32 tenant_id; 1284*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1285*9d26e4fcSRobert Mustacchi __le16 queue_number; 1286*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1287*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1288*9d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1289*9d26e4fcSRobert Mustacchi u8 reserved2[14]; 1290*9d26e4fcSRobert Mustacchi /* response section */ 1291*9d26e4fcSRobert Mustacchi u8 allocation_result; 1292*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1293*9d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1294*9d26e4fcSRobert Mustacchi u8 response_reserved[7]; 1295*9d26e4fcSRobert Mustacchi }; 1296*9d26e4fcSRobert Mustacchi 1297*9d26e4fcSRobert Mustacchi struct i40e_aqc_remove_cloud_filters_completion { 1298*9d26e4fcSRobert Mustacchi __le16 perfect_ovlan_used; 1299*9d26e4fcSRobert Mustacchi __le16 perfect_ovlan_free; 1300*9d26e4fcSRobert Mustacchi __le16 vlan_used; 1301*9d26e4fcSRobert Mustacchi __le16 vlan_free; 1302*9d26e4fcSRobert Mustacchi __le32 addr_high; 1303*9d26e4fcSRobert Mustacchi __le32 addr_low; 1304*9d26e4fcSRobert Mustacchi }; 1305*9d26e4fcSRobert Mustacchi 1306*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1307*9d26e4fcSRobert Mustacchi 1308*9d26e4fcSRobert Mustacchi /* Add Mirror Rule (indirect or direct 0x0260) 1309*9d26e4fcSRobert Mustacchi * Delete Mirror Rule (indirect or direct 0x0261) 1310*9d26e4fcSRobert Mustacchi * note: some rule types (4,5) do not use an external buffer. 1311*9d26e4fcSRobert Mustacchi * take care to set the flags correctly. 1312*9d26e4fcSRobert Mustacchi */ 1313*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule { 1314*9d26e4fcSRobert Mustacchi __le16 seid; 1315*9d26e4fcSRobert Mustacchi __le16 rule_type; 1316*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1317*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1318*9d26e4fcSRobert Mustacchi I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1319*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1320*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1321*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1322*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1323*9d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1324*9d26e4fcSRobert Mustacchi __le16 num_entries; 1325*9d26e4fcSRobert Mustacchi __le16 destination; /* VSI for add, rule id for delete */ 1326*9d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1327*9d26e4fcSRobert Mustacchi __le32 addr_low; 1328*9d26e4fcSRobert Mustacchi }; 1329*9d26e4fcSRobert Mustacchi 1330*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1331*9d26e4fcSRobert Mustacchi 1332*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule_completion { 1333*9d26e4fcSRobert Mustacchi u8 reserved[2]; 1334*9d26e4fcSRobert Mustacchi __le16 rule_id; /* only used on add */ 1335*9d26e4fcSRobert Mustacchi __le16 mirror_rules_used; 1336*9d26e4fcSRobert Mustacchi __le16 mirror_rules_free; 1337*9d26e4fcSRobert Mustacchi __le32 addr_high; 1338*9d26e4fcSRobert Mustacchi __le32 addr_low; 1339*9d26e4fcSRobert Mustacchi }; 1340*9d26e4fcSRobert Mustacchi 1341*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1342*9d26e4fcSRobert Mustacchi 1343*9d26e4fcSRobert Mustacchi /* DCB 0x03xx*/ 1344*9d26e4fcSRobert Mustacchi 1345*9d26e4fcSRobert Mustacchi /* PFC Ignore (direct 0x0301) 1346*9d26e4fcSRobert Mustacchi * the command and response use the same descriptor structure 1347*9d26e4fcSRobert Mustacchi */ 1348*9d26e4fcSRobert Mustacchi struct i40e_aqc_pfc_ignore { 1349*9d26e4fcSRobert Mustacchi u8 tc_bitmap; 1350*9d26e4fcSRobert Mustacchi u8 command_flags; /* unused on response */ 1351*9d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_SET 0x80 1352*9d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1353*9d26e4fcSRobert Mustacchi u8 reserved[14]; 1354*9d26e4fcSRobert Mustacchi }; 1355*9d26e4fcSRobert Mustacchi 1356*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1357*9d26e4fcSRobert Mustacchi 1358*9d26e4fcSRobert Mustacchi /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1359*9d26e4fcSRobert Mustacchi * with no parameters 1360*9d26e4fcSRobert Mustacchi */ 1361*9d26e4fcSRobert Mustacchi 1362*9d26e4fcSRobert Mustacchi /* TX scheduler 0x04xx */ 1363*9d26e4fcSRobert Mustacchi 1364*9d26e4fcSRobert Mustacchi /* Almost all the indirect commands use 1365*9d26e4fcSRobert Mustacchi * this generic struct to pass the SEID in param0 1366*9d26e4fcSRobert Mustacchi */ 1367*9d26e4fcSRobert Mustacchi struct i40e_aqc_tx_sched_ind { 1368*9d26e4fcSRobert Mustacchi __le16 vsi_seid; 1369*9d26e4fcSRobert Mustacchi u8 reserved[6]; 1370*9d26e4fcSRobert Mustacchi __le32 addr_high; 1371*9d26e4fcSRobert Mustacchi __le32 addr_low; 1372*9d26e4fcSRobert Mustacchi }; 1373*9d26e4fcSRobert Mustacchi 1374*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1375*9d26e4fcSRobert Mustacchi 1376*9d26e4fcSRobert Mustacchi /* Several commands respond with a set of queue set handles */ 1377*9d26e4fcSRobert Mustacchi struct i40e_aqc_qs_handles_resp { 1378*9d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 1379*9d26e4fcSRobert Mustacchi }; 1380*9d26e4fcSRobert Mustacchi 1381*9d26e4fcSRobert Mustacchi /* Configure VSI BW limits (direct 0x0400) */ 1382*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_bw_limit { 1383*9d26e4fcSRobert Mustacchi __le16 vsi_seid; 1384*9d26e4fcSRobert Mustacchi u8 reserved[2]; 1385*9d26e4fcSRobert Mustacchi __le16 credit; 1386*9d26e4fcSRobert Mustacchi u8 reserved1[2]; 1387*9d26e4fcSRobert Mustacchi u8 max_credit; /* 0-3, limit = 2^max */ 1388*9d26e4fcSRobert Mustacchi u8 reserved2[7]; 1389*9d26e4fcSRobert Mustacchi }; 1390*9d26e4fcSRobert Mustacchi 1391*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1392*9d26e4fcSRobert Mustacchi 1393*9d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1394*9d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 1395*9d26e4fcSRobert Mustacchi */ 1396*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1397*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1398*9d26e4fcSRobert Mustacchi u8 reserved[15]; 1399*9d26e4fcSRobert Mustacchi __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1400*9d26e4fcSRobert Mustacchi 1401*9d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1402*9d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 1403*9d26e4fcSRobert Mustacchi u8 reserved1[28]; 1404*9d26e4fcSRobert Mustacchi }; 1405*9d26e4fcSRobert Mustacchi 1406*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1407*9d26e4fcSRobert Mustacchi 1408*9d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1409*9d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 1410*9d26e4fcSRobert Mustacchi */ 1411*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_tc_bw_data { 1412*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1413*9d26e4fcSRobert Mustacchi u8 reserved[3]; 1414*9d26e4fcSRobert Mustacchi u8 tc_bw_credits[8]; 1415*9d26e4fcSRobert Mustacchi u8 reserved1[4]; 1416*9d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 1417*9d26e4fcSRobert Mustacchi }; 1418*9d26e4fcSRobert Mustacchi 1419*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1420*9d26e4fcSRobert Mustacchi 1421*9d26e4fcSRobert Mustacchi /* Query vsi bw configuration (indirect 0x0408) */ 1422*9d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_bw_config_resp { 1423*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1424*9d26e4fcSRobert Mustacchi u8 tc_suspended_bits; 1425*9d26e4fcSRobert Mustacchi u8 reserved[14]; 1426*9d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 1427*9d26e4fcSRobert Mustacchi u8 reserved1[4]; 1428*9d26e4fcSRobert Mustacchi __le16 port_bw_limit; 1429*9d26e4fcSRobert Mustacchi u8 reserved2[2]; 1430*9d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 1431*9d26e4fcSRobert Mustacchi u8 reserved3[23]; 1432*9d26e4fcSRobert Mustacchi }; 1433*9d26e4fcSRobert Mustacchi 1434*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1435*9d26e4fcSRobert Mustacchi 1436*9d26e4fcSRobert Mustacchi /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1437*9d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_ets_sla_config_resp { 1438*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1439*9d26e4fcSRobert Mustacchi u8 reserved[3]; 1440*9d26e4fcSRobert Mustacchi u8 share_credits[8]; 1441*9d26e4fcSRobert Mustacchi __le16 credits[8]; 1442*9d26e4fcSRobert Mustacchi 1443*9d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1444*9d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 1445*9d26e4fcSRobert Mustacchi }; 1446*9d26e4fcSRobert Mustacchi 1447*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1448*9d26e4fcSRobert Mustacchi 1449*9d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1450*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_limit { 1451*9d26e4fcSRobert Mustacchi __le16 seid; 1452*9d26e4fcSRobert Mustacchi u8 reserved[2]; 1453*9d26e4fcSRobert Mustacchi __le16 credit; 1454*9d26e4fcSRobert Mustacchi u8 reserved1[2]; 1455*9d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 1456*9d26e4fcSRobert Mustacchi u8 reserved2[7]; 1457*9d26e4fcSRobert Mustacchi }; 1458*9d26e4fcSRobert Mustacchi 1459*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1460*9d26e4fcSRobert Mustacchi 1461*9d26e4fcSRobert Mustacchi /* Enable Physical Port ETS (indirect 0x0413) 1462*9d26e4fcSRobert Mustacchi * Modify Physical Port ETS (indirect 0x0414) 1463*9d26e4fcSRobert Mustacchi * Disable Physical Port ETS (indirect 0x0415) 1464*9d26e4fcSRobert Mustacchi */ 1465*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_data { 1466*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1467*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1468*9d26e4fcSRobert Mustacchi u8 seepage; 1469*9d26e4fcSRobert Mustacchi #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1470*9d26e4fcSRobert Mustacchi u8 tc_strict_priority_flags; 1471*9d26e4fcSRobert Mustacchi u8 reserved1[17]; 1472*9d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 1473*9d26e4fcSRobert Mustacchi u8 reserved2[96]; 1474*9d26e4fcSRobert Mustacchi }; 1475*9d26e4fcSRobert Mustacchi 1476*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1477*9d26e4fcSRobert Mustacchi 1478*9d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1479*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1480*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1481*9d26e4fcSRobert Mustacchi u8 reserved[15]; 1482*9d26e4fcSRobert Mustacchi __le16 tc_bw_credit[8]; 1483*9d26e4fcSRobert Mustacchi 1484*9d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1485*9d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 1486*9d26e4fcSRobert Mustacchi u8 reserved1[28]; 1487*9d26e4fcSRobert Mustacchi }; 1488*9d26e4fcSRobert Mustacchi 1489*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1490*9d26e4fcSRobert Mustacchi 1491*9d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Allocation per Tc 1492*9d26e4fcSRobert Mustacchi * (indirect 0x0417) 1493*9d26e4fcSRobert Mustacchi */ 1494*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_config_data { 1495*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1496*9d26e4fcSRobert Mustacchi u8 reserved[2]; 1497*9d26e4fcSRobert Mustacchi u8 absolute_credits; /* bool */ 1498*9d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 1499*9d26e4fcSRobert Mustacchi u8 reserved1[20]; 1500*9d26e4fcSRobert Mustacchi }; 1501*9d26e4fcSRobert Mustacchi 1502*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1503*9d26e4fcSRobert Mustacchi 1504*9d26e4fcSRobert Mustacchi /* Query Switching Component Configuration (indirect 0x0418) */ 1505*9d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_ets_config_resp { 1506*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1507*9d26e4fcSRobert Mustacchi u8 reserved[35]; 1508*9d26e4fcSRobert Mustacchi __le16 port_bw_limit; 1509*9d26e4fcSRobert Mustacchi u8 reserved1[2]; 1510*9d26e4fcSRobert Mustacchi u8 tc_bw_max; /* 0-3, limit = 2^max */ 1511*9d26e4fcSRobert Mustacchi u8 reserved2[23]; 1512*9d26e4fcSRobert Mustacchi }; 1513*9d26e4fcSRobert Mustacchi 1514*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1515*9d26e4fcSRobert Mustacchi 1516*9d26e4fcSRobert Mustacchi /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1517*9d26e4fcSRobert Mustacchi struct i40e_aqc_query_port_ets_config_resp { 1518*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1519*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1520*9d26e4fcSRobert Mustacchi u8 reserved1; 1521*9d26e4fcSRobert Mustacchi u8 tc_strict_priority_bits; 1522*9d26e4fcSRobert Mustacchi u8 reserved2; 1523*9d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 1524*9d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 1525*9d26e4fcSRobert Mustacchi 1526*9d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1527*9d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 1528*9d26e4fcSRobert Mustacchi u8 reserved3[32]; 1529*9d26e4fcSRobert Mustacchi }; 1530*9d26e4fcSRobert Mustacchi 1531*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1532*9d26e4fcSRobert Mustacchi 1533*9d26e4fcSRobert Mustacchi /* Query Switching Component Bandwidth Allocation per Traffic Type 1534*9d26e4fcSRobert Mustacchi * (indirect 0x041A) 1535*9d26e4fcSRobert Mustacchi */ 1536*9d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_bw_config_resp { 1537*9d26e4fcSRobert Mustacchi u8 tc_valid_bits; 1538*9d26e4fcSRobert Mustacchi u8 reserved[2]; 1539*9d26e4fcSRobert Mustacchi u8 absolute_credits_enable; /* bool */ 1540*9d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 1541*9d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 1542*9d26e4fcSRobert Mustacchi 1543*9d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1544*9d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 1545*9d26e4fcSRobert Mustacchi }; 1546*9d26e4fcSRobert Mustacchi 1547*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1548*9d26e4fcSRobert Mustacchi 1549*9d26e4fcSRobert Mustacchi /* Suspend/resume port TX traffic 1550*9d26e4fcSRobert Mustacchi * (direct 0x041B and 0x041C) uses the generic SEID struct 1551*9d26e4fcSRobert Mustacchi */ 1552*9d26e4fcSRobert Mustacchi 1553*9d26e4fcSRobert Mustacchi /* Configure partition BW 1554*9d26e4fcSRobert Mustacchi * (indirect 0x041D) 1555*9d26e4fcSRobert Mustacchi */ 1556*9d26e4fcSRobert Mustacchi struct i40e_aqc_configure_partition_bw_data { 1557*9d26e4fcSRobert Mustacchi __le16 pf_valid_bits; 1558*9d26e4fcSRobert Mustacchi u8 min_bw[16]; /* guaranteed bandwidth */ 1559*9d26e4fcSRobert Mustacchi u8 max_bw[16]; /* bandwidth limit */ 1560*9d26e4fcSRobert Mustacchi }; 1561*9d26e4fcSRobert Mustacchi 1562*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1563*9d26e4fcSRobert Mustacchi 1564*9d26e4fcSRobert Mustacchi /* Get and set the active HMC resource profile and status. 1565*9d26e4fcSRobert Mustacchi * (direct 0x0500) and (direct 0x0501) 1566*9d26e4fcSRobert Mustacchi */ 1567*9d26e4fcSRobert Mustacchi struct i40e_aq_get_set_hmc_resource_profile { 1568*9d26e4fcSRobert Mustacchi u8 pm_profile; 1569*9d26e4fcSRobert Mustacchi u8 pe_vf_enabled; 1570*9d26e4fcSRobert Mustacchi u8 reserved[14]; 1571*9d26e4fcSRobert Mustacchi }; 1572*9d26e4fcSRobert Mustacchi 1573*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1574*9d26e4fcSRobert Mustacchi 1575*9d26e4fcSRobert Mustacchi enum i40e_aq_hmc_profile { 1576*9d26e4fcSRobert Mustacchi /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1577*9d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_DEFAULT = 1, 1578*9d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_FAVOR_VF = 2, 1579*9d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_EQUAL = 3, 1580*9d26e4fcSRobert Mustacchi }; 1581*9d26e4fcSRobert Mustacchi 1582*9d26e4fcSRobert Mustacchi #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1583*9d26e4fcSRobert Mustacchi #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1584*9d26e4fcSRobert Mustacchi 1585*9d26e4fcSRobert Mustacchi /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1586*9d26e4fcSRobert Mustacchi 1587*9d26e4fcSRobert Mustacchi /* set in param0 for get phy abilities to report qualified modules */ 1588*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1589*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1590*9d26e4fcSRobert Mustacchi 1591*9d26e4fcSRobert Mustacchi enum i40e_aq_phy_type { 1592*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SGMII = 0x0, 1593*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_KX = 0x1, 1594*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1595*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KR = 0x3, 1596*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1597*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XAUI = 0x5, 1598*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XFI = 0x6, 1599*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SFI = 0x7, 1600*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLAUI = 0x8, 1601*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLPPI = 0x9, 1602*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1603*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1604*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1605*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1606*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_100BASE_TX = 0x11, 1607*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T = 0x12, 1608*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_T = 0x13, 1609*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SR = 0x14, 1610*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_LR = 0x15, 1611*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1612*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1613*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1614*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1615*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1616*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1617*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1618*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1619*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1620*9d26e4fcSRobert Mustacchi I40E_PHY_TYPE_MAX 1621*9d26e4fcSRobert Mustacchi }; 1622*9d26e4fcSRobert Mustacchi 1623*9d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1624*9d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1625*9d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1626*9d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1627*9d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1628*9d26e4fcSRobert Mustacchi 1629*9d26e4fcSRobert Mustacchi enum i40e_aq_link_speed { 1630*9d26e4fcSRobert Mustacchi I40E_LINK_SPEED_UNKNOWN = 0, 1631*9d26e4fcSRobert Mustacchi I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1632*9d26e4fcSRobert Mustacchi I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1633*9d26e4fcSRobert Mustacchi I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1634*9d26e4fcSRobert Mustacchi I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1635*9d26e4fcSRobert Mustacchi I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1636*9d26e4fcSRobert Mustacchi }; 1637*9d26e4fcSRobert Mustacchi 1638*9d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc { 1639*9d26e4fcSRobert Mustacchi u8 oui[3]; 1640*9d26e4fcSRobert Mustacchi u8 reserved1; 1641*9d26e4fcSRobert Mustacchi u8 part_number[16]; 1642*9d26e4fcSRobert Mustacchi u8 revision[4]; 1643*9d26e4fcSRobert Mustacchi u8 reserved2[8]; 1644*9d26e4fcSRobert Mustacchi }; 1645*9d26e4fcSRobert Mustacchi 1646*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1647*9d26e4fcSRobert Mustacchi 1648*9d26e4fcSRobert Mustacchi struct i40e_aq_get_phy_abilities_resp { 1649*9d26e4fcSRobert Mustacchi __le32 phy_type; /* bitmap using the above enum for offsets */ 1650*9d26e4fcSRobert Mustacchi u8 link_speed; /* bitmap using the above enum bit patterns */ 1651*9d26e4fcSRobert Mustacchi u8 abilities; 1652*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1653*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1654*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1655*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLED 0x08 1656*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_AN_ENABLED 0x10 1657*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1658*9d26e4fcSRobert Mustacchi __le16 eee_capability; 1659*9d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_100BASE_TX 0x0002 1660*9d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_T 0x0004 1661*9d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_T 0x0008 1662*9d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_KX 0x0010 1663*9d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1664*9d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KR 0x0040 1665*9d26e4fcSRobert Mustacchi __le32 eeer_val; 1666*9d26e4fcSRobert Mustacchi u8 d3_lpan; 1667*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1668*9d26e4fcSRobert Mustacchi u8 reserved[3]; 1669*9d26e4fcSRobert Mustacchi u8 phy_id[4]; 1670*9d26e4fcSRobert Mustacchi u8 module_type[3]; 1671*9d26e4fcSRobert Mustacchi u8 qualified_module_count; 1672*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_MAX_QMS 16 1673*9d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1674*9d26e4fcSRobert Mustacchi }; 1675*9d26e4fcSRobert Mustacchi 1676*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1677*9d26e4fcSRobert Mustacchi 1678*9d26e4fcSRobert Mustacchi /* Set PHY Config (direct 0x0601) */ 1679*9d26e4fcSRobert Mustacchi struct i40e_aq_set_phy_config { /* same bits as above in all */ 1680*9d26e4fcSRobert Mustacchi __le32 phy_type; 1681*9d26e4fcSRobert Mustacchi u8 link_speed; 1682*9d26e4fcSRobert Mustacchi u8 abilities; 1683*9d26e4fcSRobert Mustacchi /* bits 0-2 use the values from get_phy_abilities_resp */ 1684*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_LINK 0x08 1685*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_AN 0x10 1686*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1687*9d26e4fcSRobert Mustacchi __le16 eee_capability; 1688*9d26e4fcSRobert Mustacchi __le32 eeer; 1689*9d26e4fcSRobert Mustacchi u8 low_power_ctrl; 1690*9d26e4fcSRobert Mustacchi u8 reserved[3]; 1691*9d26e4fcSRobert Mustacchi }; 1692*9d26e4fcSRobert Mustacchi 1693*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1694*9d26e4fcSRobert Mustacchi 1695*9d26e4fcSRobert Mustacchi /* Set MAC Config command data structure (direct 0x0603) */ 1696*9d26e4fcSRobert Mustacchi struct i40e_aq_set_mac_config { 1697*9d26e4fcSRobert Mustacchi __le16 max_frame_size; 1698*9d26e4fcSRobert Mustacchi u8 params; 1699*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1700*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1701*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1702*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1703*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1704*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1705*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1706*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1707*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1708*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1709*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1710*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1711*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1712*9d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1713*9d26e4fcSRobert Mustacchi u8 tx_timer_priority; /* bitmap */ 1714*9d26e4fcSRobert Mustacchi __le16 tx_timer_value; 1715*9d26e4fcSRobert Mustacchi __le16 fc_refresh_threshold; 1716*9d26e4fcSRobert Mustacchi u8 reserved[8]; 1717*9d26e4fcSRobert Mustacchi }; 1718*9d26e4fcSRobert Mustacchi 1719*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1720*9d26e4fcSRobert Mustacchi 1721*9d26e4fcSRobert Mustacchi /* Restart Auto-Negotiation (direct 0x605) */ 1722*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_link_restart_an { 1723*9d26e4fcSRobert Mustacchi u8 command; 1724*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_RESTART_AN 0x02 1725*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLE 0x04 1726*9d26e4fcSRobert Mustacchi u8 reserved[15]; 1727*9d26e4fcSRobert Mustacchi }; 1728*9d26e4fcSRobert Mustacchi 1729*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1730*9d26e4fcSRobert Mustacchi 1731*9d26e4fcSRobert Mustacchi /* Get Link Status cmd & response data structure (direct 0x0607) */ 1732*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_link_status { 1733*9d26e4fcSRobert Mustacchi __le16 command_flags; /* only field set on command */ 1734*9d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_MASK 0x3 1735*9d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_NOP 0x0 1736*9d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_DISABLE 0x2 1737*9d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_ENABLE 0x3 1738*9d26e4fcSRobert Mustacchi /* only response uses this flag */ 1739*9d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_IS_ENABLED 0x1 1740*9d26e4fcSRobert Mustacchi u8 phy_type; /* i40e_aq_phy_type */ 1741*9d26e4fcSRobert Mustacchi u8 link_speed; /* i40e_aq_link_speed */ 1742*9d26e4fcSRobert Mustacchi u8 link_info; 1743*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1744*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_FUNCTION 0x01 1745*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT 0x02 1746*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_TX 0x04 1747*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_RX 0x08 1748*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1749*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_PORT 0x20 1750*9d26e4fcSRobert Mustacchi #define I40E_AQ_MEDIA_AVAILABLE 0x40 1751*9d26e4fcSRobert Mustacchi #define I40E_AQ_SIGNAL_DETECT 0x80 1752*9d26e4fcSRobert Mustacchi u8 an_info; 1753*9d26e4fcSRobert Mustacchi #define I40E_AQ_AN_COMPLETED 0x01 1754*9d26e4fcSRobert Mustacchi #define I40E_AQ_LP_AN_ABILITY 0x02 1755*9d26e4fcSRobert Mustacchi #define I40E_AQ_PD_FAULT 0x04 1756*9d26e4fcSRobert Mustacchi #define I40E_AQ_FEC_EN 0x08 1757*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LOW_POWER 0x10 1758*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_TX 0x20 1759*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_RX 0x40 1760*9d26e4fcSRobert Mustacchi #define I40E_AQ_QUALIFIED_MODULE 0x80 1761*9d26e4fcSRobert Mustacchi u8 ext_info; 1762*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1763*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1764*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_SHIFT 0x02 1765*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1766*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_ACTIVE 0x00 1767*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_DRAINED 0x01 1768*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_FLUSHED 0x03 1769*9d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FORCED_40G 0x10 1770*9d26e4fcSRobert Mustacchi u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1771*9d26e4fcSRobert Mustacchi __le16 max_frame_size; 1772*9d26e4fcSRobert Mustacchi u8 config; 1773*9d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_CRC_ENA 0x04 1774*9d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_PACING_MASK 0x78 1775*9d26e4fcSRobert Mustacchi u8 reserved[5]; 1776*9d26e4fcSRobert Mustacchi }; 1777*9d26e4fcSRobert Mustacchi 1778*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1779*9d26e4fcSRobert Mustacchi 1780*9d26e4fcSRobert Mustacchi /* Set event mask command (direct 0x613) */ 1781*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_int_mask { 1782*9d26e4fcSRobert Mustacchi u8 reserved[8]; 1783*9d26e4fcSRobert Mustacchi __le16 event_mask; 1784*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1785*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1786*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1787*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1788*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1789*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1790*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1791*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1792*9d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1793*9d26e4fcSRobert Mustacchi u8 reserved1[6]; 1794*9d26e4fcSRobert Mustacchi }; 1795*9d26e4fcSRobert Mustacchi 1796*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1797*9d26e4fcSRobert Mustacchi 1798*9d26e4fcSRobert Mustacchi /* Get Local AN advt register (direct 0x0614) 1799*9d26e4fcSRobert Mustacchi * Set Local AN advt register (direct 0x0615) 1800*9d26e4fcSRobert Mustacchi * Get Link Partner AN advt register (direct 0x0616) 1801*9d26e4fcSRobert Mustacchi */ 1802*9d26e4fcSRobert Mustacchi struct i40e_aqc_an_advt_reg { 1803*9d26e4fcSRobert Mustacchi __le32 local_an_reg0; 1804*9d26e4fcSRobert Mustacchi __le16 local_an_reg1; 1805*9d26e4fcSRobert Mustacchi u8 reserved[10]; 1806*9d26e4fcSRobert Mustacchi }; 1807*9d26e4fcSRobert Mustacchi 1808*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1809*9d26e4fcSRobert Mustacchi 1810*9d26e4fcSRobert Mustacchi /* Set Loopback mode (0x0618) */ 1811*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_lb_mode { 1812*9d26e4fcSRobert Mustacchi __le16 lb_mode; 1813*9d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_LOCAL 0x01 1814*9d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_REMOTE 0x02 1815*9d26e4fcSRobert Mustacchi #define I40E_AQ_LB_MAC_LOCAL 0x04 1816*9d26e4fcSRobert Mustacchi u8 reserved[14]; 1817*9d26e4fcSRobert Mustacchi }; 1818*9d26e4fcSRobert Mustacchi 1819*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1820*9d26e4fcSRobert Mustacchi 1821*9d26e4fcSRobert Mustacchi /* Set PHY Debug command (0x0622) */ 1822*9d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_debug { 1823*9d26e4fcSRobert Mustacchi u8 command_flags; 1824*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1825*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1826*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1827*9d26e4fcSRobert Mustacchi I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1828*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1829*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1830*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1831*9d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1832*9d26e4fcSRobert Mustacchi u8 reserved[15]; 1833*9d26e4fcSRobert Mustacchi }; 1834*9d26e4fcSRobert Mustacchi 1835*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1836*9d26e4fcSRobert Mustacchi 1837*9d26e4fcSRobert Mustacchi enum i40e_aq_phy_reg_type { 1838*9d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_INTERNAL = 0x1, 1839*9d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1840*9d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1841*9d26e4fcSRobert Mustacchi }; 1842*9d26e4fcSRobert Mustacchi 1843*9d26e4fcSRobert Mustacchi /* NVM Read command (indirect 0x0701) 1844*9d26e4fcSRobert Mustacchi * NVM Erase commands (direct 0x0702) 1845*9d26e4fcSRobert Mustacchi * NVM Update commands (indirect 0x0703) 1846*9d26e4fcSRobert Mustacchi */ 1847*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_update { 1848*9d26e4fcSRobert Mustacchi u8 command_flags; 1849*9d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_LAST_CMD 0x01 1850*9d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_FLASH_ONLY 0x80 1851*9d26e4fcSRobert Mustacchi u8 module_pointer; 1852*9d26e4fcSRobert Mustacchi __le16 length; 1853*9d26e4fcSRobert Mustacchi __le32 offset; 1854*9d26e4fcSRobert Mustacchi __le32 addr_high; 1855*9d26e4fcSRobert Mustacchi __le32 addr_low; 1856*9d26e4fcSRobert Mustacchi }; 1857*9d26e4fcSRobert Mustacchi 1858*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1859*9d26e4fcSRobert Mustacchi 1860*9d26e4fcSRobert Mustacchi /* NVM Config Read (indirect 0x0704) */ 1861*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_read { 1862*9d26e4fcSRobert Mustacchi __le16 cmd_flags; 1863*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1864*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1865*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1866*9d26e4fcSRobert Mustacchi __le16 element_count; 1867*9d26e4fcSRobert Mustacchi __le16 element_id; /* Feature/field ID */ 1868*9d26e4fcSRobert Mustacchi __le16 element_id_msw; /* MSWord of field ID */ 1869*9d26e4fcSRobert Mustacchi __le32 address_high; 1870*9d26e4fcSRobert Mustacchi __le32 address_low; 1871*9d26e4fcSRobert Mustacchi }; 1872*9d26e4fcSRobert Mustacchi 1873*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1874*9d26e4fcSRobert Mustacchi 1875*9d26e4fcSRobert Mustacchi /* NVM Config Write (indirect 0x0705) */ 1876*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_write { 1877*9d26e4fcSRobert Mustacchi __le16 cmd_flags; 1878*9d26e4fcSRobert Mustacchi __le16 element_count; 1879*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1880*9d26e4fcSRobert Mustacchi __le32 address_high; 1881*9d26e4fcSRobert Mustacchi __le32 address_low; 1882*9d26e4fcSRobert Mustacchi }; 1883*9d26e4fcSRobert Mustacchi 1884*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1885*9d26e4fcSRobert Mustacchi 1886*9d26e4fcSRobert Mustacchi /* Used for 0x0704 as well as for 0x0705 commands */ 1887*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1888*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1889*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE 0 1890*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1891*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_feature { 1892*9d26e4fcSRobert Mustacchi __le16 feature_id; 1893*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1894*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1895*9d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1896*9d26e4fcSRobert Mustacchi __le16 feature_options; 1897*9d26e4fcSRobert Mustacchi __le16 feature_selection; 1898*9d26e4fcSRobert Mustacchi }; 1899*9d26e4fcSRobert Mustacchi 1900*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1901*9d26e4fcSRobert Mustacchi 1902*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_immediate_field { 1903*9d26e4fcSRobert Mustacchi __le32 field_id; 1904*9d26e4fcSRobert Mustacchi __le32 field_value; 1905*9d26e4fcSRobert Mustacchi __le16 field_options; 1906*9d26e4fcSRobert Mustacchi __le16 reserved; 1907*9d26e4fcSRobert Mustacchi }; 1908*9d26e4fcSRobert Mustacchi 1909*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1910*9d26e4fcSRobert Mustacchi 1911*9d26e4fcSRobert Mustacchi /* OEM Post Update (indirect 0x0720) 1912*9d26e4fcSRobert Mustacchi * no command data struct used 1913*9d26e4fcSRobert Mustacchi */ 1914*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_oem_post_update { 1915*9d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1916*9d26e4fcSRobert Mustacchi u8 sel_data; 1917*9d26e4fcSRobert Mustacchi u8 reserved[7]; 1918*9d26e4fcSRobert Mustacchi }; 1919*9d26e4fcSRobert Mustacchi 1920*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1921*9d26e4fcSRobert Mustacchi 1922*9d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_oem_post_update_buffer { 1923*9d26e4fcSRobert Mustacchi u8 str_len; 1924*9d26e4fcSRobert Mustacchi u8 dev_addr; 1925*9d26e4fcSRobert Mustacchi __le16 eeprom_addr; 1926*9d26e4fcSRobert Mustacchi u8 data[36]; 1927*9d26e4fcSRobert Mustacchi }; 1928*9d26e4fcSRobert Mustacchi 1929*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1930*9d26e4fcSRobert Mustacchi 1931*9d26e4fcSRobert Mustacchi /* Send to PF command (indirect 0x0801) id is only used by PF 1932*9d26e4fcSRobert Mustacchi * Send to VF command (indirect 0x0802) id is only used by PF 1933*9d26e4fcSRobert Mustacchi * Send to Peer PF command (indirect 0x0803) 1934*9d26e4fcSRobert Mustacchi */ 1935*9d26e4fcSRobert Mustacchi struct i40e_aqc_pf_vf_message { 1936*9d26e4fcSRobert Mustacchi __le32 id; 1937*9d26e4fcSRobert Mustacchi u8 reserved[4]; 1938*9d26e4fcSRobert Mustacchi __le32 addr_high; 1939*9d26e4fcSRobert Mustacchi __le32 addr_low; 1940*9d26e4fcSRobert Mustacchi }; 1941*9d26e4fcSRobert Mustacchi 1942*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1943*9d26e4fcSRobert Mustacchi 1944*9d26e4fcSRobert Mustacchi /* Alternate structure */ 1945*9d26e4fcSRobert Mustacchi 1946*9d26e4fcSRobert Mustacchi /* Direct write (direct 0x0900) 1947*9d26e4fcSRobert Mustacchi * Direct read (direct 0x0902) 1948*9d26e4fcSRobert Mustacchi */ 1949*9d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write { 1950*9d26e4fcSRobert Mustacchi __le32 address0; 1951*9d26e4fcSRobert Mustacchi __le32 data0; 1952*9d26e4fcSRobert Mustacchi __le32 address1; 1953*9d26e4fcSRobert Mustacchi __le32 data1; 1954*9d26e4fcSRobert Mustacchi }; 1955*9d26e4fcSRobert Mustacchi 1956*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1957*9d26e4fcSRobert Mustacchi 1958*9d26e4fcSRobert Mustacchi /* Indirect write (indirect 0x0901) 1959*9d26e4fcSRobert Mustacchi * Indirect read (indirect 0x0903) 1960*9d26e4fcSRobert Mustacchi */ 1961*9d26e4fcSRobert Mustacchi 1962*9d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_ind_write { 1963*9d26e4fcSRobert Mustacchi __le32 address; 1964*9d26e4fcSRobert Mustacchi __le32 length; 1965*9d26e4fcSRobert Mustacchi __le32 addr_high; 1966*9d26e4fcSRobert Mustacchi __le32 addr_low; 1967*9d26e4fcSRobert Mustacchi }; 1968*9d26e4fcSRobert Mustacchi 1969*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1970*9d26e4fcSRobert Mustacchi 1971*9d26e4fcSRobert Mustacchi /* Done alternate write (direct 0x0904) 1972*9d26e4fcSRobert Mustacchi * uses i40e_aq_desc 1973*9d26e4fcSRobert Mustacchi */ 1974*9d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write_done { 1975*9d26e4fcSRobert Mustacchi __le16 cmd_flags; 1976*9d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1977*9d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1978*9d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1979*9d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1980*9d26e4fcSRobert Mustacchi u8 reserved[14]; 1981*9d26e4fcSRobert Mustacchi }; 1982*9d26e4fcSRobert Mustacchi 1983*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1984*9d26e4fcSRobert Mustacchi 1985*9d26e4fcSRobert Mustacchi /* Set OEM mode (direct 0x0905) */ 1986*9d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_set_mode { 1987*9d26e4fcSRobert Mustacchi __le32 mode; 1988*9d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_NONE 0 1989*9d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_OEM 1 1990*9d26e4fcSRobert Mustacchi u8 reserved[12]; 1991*9d26e4fcSRobert Mustacchi }; 1992*9d26e4fcSRobert Mustacchi 1993*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1994*9d26e4fcSRobert Mustacchi 1995*9d26e4fcSRobert Mustacchi /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1996*9d26e4fcSRobert Mustacchi 1997*9d26e4fcSRobert Mustacchi /* async events 0x10xx */ 1998*9d26e4fcSRobert Mustacchi 1999*9d26e4fcSRobert Mustacchi /* Lan Queue Overflow Event (direct, 0x1001) */ 2000*9d26e4fcSRobert Mustacchi struct i40e_aqc_lan_overflow { 2001*9d26e4fcSRobert Mustacchi __le32 prtdcb_rupto; 2002*9d26e4fcSRobert Mustacchi __le32 otx_ctl; 2003*9d26e4fcSRobert Mustacchi u8 reserved[8]; 2004*9d26e4fcSRobert Mustacchi }; 2005*9d26e4fcSRobert Mustacchi 2006*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2007*9d26e4fcSRobert Mustacchi 2008*9d26e4fcSRobert Mustacchi /* Get LLDP MIB (indirect 0x0A00) */ 2009*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_get_mib { 2010*9d26e4fcSRobert Mustacchi u8 type; 2011*9d26e4fcSRobert Mustacchi u8 reserved1; 2012*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2013*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2014*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2015*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2016*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2017*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2018*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2019*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2020*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_SHIFT 0x4 2021*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2022*9d26e4fcSRobert Mustacchi /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2023*9d26e4fcSRobert Mustacchi __le16 local_len; 2024*9d26e4fcSRobert Mustacchi __le16 remote_len; 2025*9d26e4fcSRobert Mustacchi u8 reserved2[2]; 2026*9d26e4fcSRobert Mustacchi __le32 addr_high; 2027*9d26e4fcSRobert Mustacchi __le32 addr_low; 2028*9d26e4fcSRobert Mustacchi }; 2029*9d26e4fcSRobert Mustacchi 2030*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2031*9d26e4fcSRobert Mustacchi 2032*9d26e4fcSRobert Mustacchi /* Configure LLDP MIB Change Event (direct 0x0A01) 2033*9d26e4fcSRobert Mustacchi * also used for the event (with type in the command field) 2034*9d26e4fcSRobert Mustacchi */ 2035*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_mib { 2036*9d26e4fcSRobert Mustacchi u8 command; 2037*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2038*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2039*9d26e4fcSRobert Mustacchi u8 reserved[7]; 2040*9d26e4fcSRobert Mustacchi __le32 addr_high; 2041*9d26e4fcSRobert Mustacchi __le32 addr_low; 2042*9d26e4fcSRobert Mustacchi }; 2043*9d26e4fcSRobert Mustacchi 2044*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2045*9d26e4fcSRobert Mustacchi 2046*9d26e4fcSRobert Mustacchi /* Add LLDP TLV (indirect 0x0A02) 2047*9d26e4fcSRobert Mustacchi * Delete LLDP TLV (indirect 0x0A04) 2048*9d26e4fcSRobert Mustacchi */ 2049*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_add_tlv { 2050*9d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2051*9d26e4fcSRobert Mustacchi u8 reserved1[1]; 2052*9d26e4fcSRobert Mustacchi __le16 len; 2053*9d26e4fcSRobert Mustacchi u8 reserved2[4]; 2054*9d26e4fcSRobert Mustacchi __le32 addr_high; 2055*9d26e4fcSRobert Mustacchi __le32 addr_low; 2056*9d26e4fcSRobert Mustacchi }; 2057*9d26e4fcSRobert Mustacchi 2058*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2059*9d26e4fcSRobert Mustacchi 2060*9d26e4fcSRobert Mustacchi /* Update LLDP TLV (indirect 0x0A03) */ 2061*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_tlv { 2062*9d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2063*9d26e4fcSRobert Mustacchi u8 reserved; 2064*9d26e4fcSRobert Mustacchi __le16 old_len; 2065*9d26e4fcSRobert Mustacchi __le16 new_offset; 2066*9d26e4fcSRobert Mustacchi __le16 new_len; 2067*9d26e4fcSRobert Mustacchi __le32 addr_high; 2068*9d26e4fcSRobert Mustacchi __le32 addr_low; 2069*9d26e4fcSRobert Mustacchi }; 2070*9d26e4fcSRobert Mustacchi 2071*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2072*9d26e4fcSRobert Mustacchi 2073*9d26e4fcSRobert Mustacchi /* Stop LLDP (direct 0x0A05) */ 2074*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop { 2075*9d26e4fcSRobert Mustacchi u8 command; 2076*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_STOP 0x0 2077*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2078*9d26e4fcSRobert Mustacchi u8 reserved[15]; 2079*9d26e4fcSRobert Mustacchi }; 2080*9d26e4fcSRobert Mustacchi 2081*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2082*9d26e4fcSRobert Mustacchi 2083*9d26e4fcSRobert Mustacchi /* Start LLDP (direct 0x0A06) */ 2084*9d26e4fcSRobert Mustacchi 2085*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_start { 2086*9d26e4fcSRobert Mustacchi u8 command; 2087*9d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_START 0x1 2088*9d26e4fcSRobert Mustacchi u8 reserved[15]; 2089*9d26e4fcSRobert Mustacchi }; 2090*9d26e4fcSRobert Mustacchi 2091*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2092*9d26e4fcSRobert Mustacchi 2093*9d26e4fcSRobert Mustacchi /* Get CEE DCBX Oper Config (0x0A07) 2094*9d26e4fcSRobert Mustacchi * uses the generic descriptor struct 2095*9d26e4fcSRobert Mustacchi * returns below as indirect response 2096*9d26e4fcSRobert Mustacchi */ 2097*9d26e4fcSRobert Mustacchi 2098*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2099*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2100*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2101*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2102*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2103*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2104*9d26e4fcSRobert Mustacchi 2105*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2106*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2107*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2108*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2109*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2110*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2111*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2112*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2113*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2114*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2115*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2116*9d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2117*9d26e4fcSRobert Mustacchi 2118*9d26e4fcSRobert Mustacchi /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2119*9d26e4fcSRobert Mustacchi * word boundary layout issues, which the Linux compilers silently deal 2120*9d26e4fcSRobert Mustacchi * with by adding padding, making the actual struct larger than designed. 2121*9d26e4fcSRobert Mustacchi * However, the FW compiler for the NIC is less lenient and complains 2122*9d26e4fcSRobert Mustacchi * about the struct. Hence, the struct defined here has an extra byte in 2123*9d26e4fcSRobert Mustacchi * fields reserved3 and reserved4 to directly acknowledge that padding, 2124*9d26e4fcSRobert Mustacchi * and the new length is used in the length check macro. 2125*9d26e4fcSRobert Mustacchi */ 2126*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2127*9d26e4fcSRobert Mustacchi u8 reserved1; 2128*9d26e4fcSRobert Mustacchi u8 oper_num_tc; 2129*9d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 2130*9d26e4fcSRobert Mustacchi u8 reserved2; 2131*9d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 2132*9d26e4fcSRobert Mustacchi u8 oper_pfc_en; 2133*9d26e4fcSRobert Mustacchi u8 reserved3[2]; 2134*9d26e4fcSRobert Mustacchi __le16 oper_app_prio; 2135*9d26e4fcSRobert Mustacchi u8 reserved4[2]; 2136*9d26e4fcSRobert Mustacchi __le16 tlv_status; 2137*9d26e4fcSRobert Mustacchi }; 2138*9d26e4fcSRobert Mustacchi 2139*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2140*9d26e4fcSRobert Mustacchi 2141*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_resp { 2142*9d26e4fcSRobert Mustacchi u8 oper_num_tc; 2143*9d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 2144*9d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 2145*9d26e4fcSRobert Mustacchi u8 oper_pfc_en; 2146*9d26e4fcSRobert Mustacchi __le16 oper_app_prio; 2147*9d26e4fcSRobert Mustacchi __le32 tlv_status; 2148*9d26e4fcSRobert Mustacchi u8 reserved[12]; 2149*9d26e4fcSRobert Mustacchi }; 2150*9d26e4fcSRobert Mustacchi 2151*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2152*9d26e4fcSRobert Mustacchi 2153*9d26e4fcSRobert Mustacchi /* Set Local LLDP MIB (indirect 0x0A08) 2154*9d26e4fcSRobert Mustacchi * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2155*9d26e4fcSRobert Mustacchi */ 2156*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_set_local_mib { 2157*9d26e4fcSRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2158*9d26e4fcSRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2159*9d26e4fcSRobert Mustacchi u8 type; 2160*9d26e4fcSRobert Mustacchi u8 reserved0; 2161*9d26e4fcSRobert Mustacchi __le16 length; 2162*9d26e4fcSRobert Mustacchi u8 reserved1[4]; 2163*9d26e4fcSRobert Mustacchi __le32 address_high; 2164*9d26e4fcSRobert Mustacchi __le32 address_low; 2165*9d26e4fcSRobert Mustacchi }; 2166*9d26e4fcSRobert Mustacchi 2167*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2168*9d26e4fcSRobert Mustacchi 2169*9d26e4fcSRobert Mustacchi /* Stop/Start LLDP Agent (direct 0x0A09) 2170*9d26e4fcSRobert Mustacchi * Used for stopping/starting specific LLDP agent. e.g. DCBx 2171*9d26e4fcSRobert Mustacchi */ 2172*9d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop_start_specific_agent { 2173*9d26e4fcSRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2174*9d26e4fcSRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2175*9d26e4fcSRobert Mustacchi u8 command; 2176*9d26e4fcSRobert Mustacchi u8 reserved[15]; 2177*9d26e4fcSRobert Mustacchi }; 2178*9d26e4fcSRobert Mustacchi 2179*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2180*9d26e4fcSRobert Mustacchi 2181*9d26e4fcSRobert Mustacchi /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2182*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel { 2183*9d26e4fcSRobert Mustacchi __le16 udp_port; 2184*9d26e4fcSRobert Mustacchi u8 reserved0[3]; 2185*9d26e4fcSRobert Mustacchi u8 protocol_type; 2186*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2187*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2188*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2189*9d26e4fcSRobert Mustacchi u8 reserved1[10]; 2190*9d26e4fcSRobert Mustacchi }; 2191*9d26e4fcSRobert Mustacchi 2192*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2193*9d26e4fcSRobert Mustacchi 2194*9d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel_completion { 2195*9d26e4fcSRobert Mustacchi __le16 udp_port; 2196*9d26e4fcSRobert Mustacchi u8 filter_entry_index; 2197*9d26e4fcSRobert Mustacchi u8 multiple_pfs; 2198*9d26e4fcSRobert Mustacchi #define I40E_AQC_SINGLE_PF 0x0 2199*9d26e4fcSRobert Mustacchi #define I40E_AQC_MULTIPLE_PFS 0x1 2200*9d26e4fcSRobert Mustacchi u8 total_filters; 2201*9d26e4fcSRobert Mustacchi u8 reserved[11]; 2202*9d26e4fcSRobert Mustacchi }; 2203*9d26e4fcSRobert Mustacchi 2204*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2205*9d26e4fcSRobert Mustacchi 2206*9d26e4fcSRobert Mustacchi /* remove UDP Tunnel command (0x0B01) */ 2207*9d26e4fcSRobert Mustacchi struct i40e_aqc_remove_udp_tunnel { 2208*9d26e4fcSRobert Mustacchi u8 reserved[2]; 2209*9d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 2210*9d26e4fcSRobert Mustacchi u8 reserved2[13]; 2211*9d26e4fcSRobert Mustacchi }; 2212*9d26e4fcSRobert Mustacchi 2213*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2214*9d26e4fcSRobert Mustacchi 2215*9d26e4fcSRobert Mustacchi struct i40e_aqc_del_udp_tunnel_completion { 2216*9d26e4fcSRobert Mustacchi __le16 udp_port; 2217*9d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 2218*9d26e4fcSRobert Mustacchi u8 multiple_pfs; 2219*9d26e4fcSRobert Mustacchi u8 total_filters_used; 2220*9d26e4fcSRobert Mustacchi u8 reserved1[11]; 2221*9d26e4fcSRobert Mustacchi }; 2222*9d26e4fcSRobert Mustacchi 2223*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2224*9d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 2225*9d26e4fcSRobert Mustacchi 2226*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key { 2227*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2228*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2229*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2230*9d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2231*9d26e4fcSRobert Mustacchi __le16 vsi_id; 2232*9d26e4fcSRobert Mustacchi u8 reserved[6]; 2233*9d26e4fcSRobert Mustacchi __le32 addr_high; 2234*9d26e4fcSRobert Mustacchi __le32 addr_low; 2235*9d26e4fcSRobert Mustacchi }; 2236*9d26e4fcSRobert Mustacchi 2237*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2238*9d26e4fcSRobert Mustacchi 2239*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key_data { 2240*9d26e4fcSRobert Mustacchi u8 standard_rss_key[0x28]; 2241*9d26e4fcSRobert Mustacchi u8 extended_hash_key[0xc]; 2242*9d26e4fcSRobert Mustacchi }; 2243*9d26e4fcSRobert Mustacchi 2244*9d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2245*9d26e4fcSRobert Mustacchi 2246*9d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_lut { 2247*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2248*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2249*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2250*9d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2251*9d26e4fcSRobert Mustacchi __le16 vsi_id; 2252*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2253*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2254*9d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2255*9d26e4fcSRobert Mustacchi 2256*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2257*9d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2258*9d26e4fcSRobert Mustacchi __le16 flags; 2259*9d26e4fcSRobert Mustacchi u8 reserved[4]; 2260*9d26e4fcSRobert Mustacchi __le32 addr_high; 2261*9d26e4fcSRobert Mustacchi __le32 addr_low; 2262*9d26e4fcSRobert Mustacchi }; 2263*9d26e4fcSRobert Mustacchi 2264*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2265*9d26e4fcSRobert Mustacchi #endif 2266*9d26e4fcSRobert Mustacchi 2267*9d26e4fcSRobert Mustacchi /* tunnel key structure 0x0B10 */ 2268*9d26e4fcSRobert Mustacchi 2269*9d26e4fcSRobert Mustacchi struct i40e_aqc_tunnel_key_structure { 2270*9d26e4fcSRobert Mustacchi u8 key1_off; 2271*9d26e4fcSRobert Mustacchi u8 key2_off; 2272*9d26e4fcSRobert Mustacchi u8 key1_len; /* 0 to 15 */ 2273*9d26e4fcSRobert Mustacchi u8 key2_len; /* 0 to 15 */ 2274*9d26e4fcSRobert Mustacchi u8 flags; 2275*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2276*9d26e4fcSRobert Mustacchi /* response flags */ 2277*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2278*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2279*9d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2280*9d26e4fcSRobert Mustacchi u8 network_key_index; 2281*9d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2282*9d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2283*9d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2284*9d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2285*9d26e4fcSRobert Mustacchi u8 reserved[10]; 2286*9d26e4fcSRobert Mustacchi }; 2287*9d26e4fcSRobert Mustacchi 2288*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2289*9d26e4fcSRobert Mustacchi 2290*9d26e4fcSRobert Mustacchi /* OEM mode commands (direct 0xFE0x) */ 2291*9d26e4fcSRobert Mustacchi struct i40e_aqc_oem_param_change { 2292*9d26e4fcSRobert Mustacchi __le32 param_type; 2293*9d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2294*9d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2295*9d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_MAC 2 2296*9d26e4fcSRobert Mustacchi __le32 param_value1; 2297*9d26e4fcSRobert Mustacchi __le16 param_value2; 2298*9d26e4fcSRobert Mustacchi u8 reserved[6]; 2299*9d26e4fcSRobert Mustacchi }; 2300*9d26e4fcSRobert Mustacchi 2301*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2302*9d26e4fcSRobert Mustacchi 2303*9d26e4fcSRobert Mustacchi struct i40e_aqc_oem_state_change { 2304*9d26e4fcSRobert Mustacchi __le32 state; 2305*9d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2306*9d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2307*9d26e4fcSRobert Mustacchi u8 reserved[12]; 2308*9d26e4fcSRobert Mustacchi }; 2309*9d26e4fcSRobert Mustacchi 2310*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2311*9d26e4fcSRobert Mustacchi 2312*9d26e4fcSRobert Mustacchi /* Initialize OCSD (0xFE02, direct) */ 2313*9d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocsd_initialize { 2314*9d26e4fcSRobert Mustacchi u8 type_status; 2315*9d26e4fcSRobert Mustacchi u8 reserved1[3]; 2316*9d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_high; 2317*9d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_low; 2318*9d26e4fcSRobert Mustacchi __le32 requested_update_interval; 2319*9d26e4fcSRobert Mustacchi }; 2320*9d26e4fcSRobert Mustacchi 2321*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2322*9d26e4fcSRobert Mustacchi 2323*9d26e4fcSRobert Mustacchi /* Initialize OCBB (0xFE03, direct) */ 2324*9d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocbb_initialize { 2325*9d26e4fcSRobert Mustacchi u8 type_status; 2326*9d26e4fcSRobert Mustacchi u8 reserved1[3]; 2327*9d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_high; 2328*9d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_low; 2329*9d26e4fcSRobert Mustacchi u8 reserved2[4]; 2330*9d26e4fcSRobert Mustacchi }; 2331*9d26e4fcSRobert Mustacchi 2332*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2333*9d26e4fcSRobert Mustacchi 2334*9d26e4fcSRobert Mustacchi /* debug commands */ 2335*9d26e4fcSRobert Mustacchi 2336*9d26e4fcSRobert Mustacchi /* get device id (0xFF00) uses the generic structure */ 2337*9d26e4fcSRobert Mustacchi 2338*9d26e4fcSRobert Mustacchi /* set test more (0xFF01, internal) */ 2339*9d26e4fcSRobert Mustacchi 2340*9d26e4fcSRobert Mustacchi struct i40e_acq_set_test_mode { 2341*9d26e4fcSRobert Mustacchi u8 mode; 2342*9d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_PARTIAL 0 2343*9d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_FULL 1 2344*9d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_NVM 2 2345*9d26e4fcSRobert Mustacchi u8 reserved[3]; 2346*9d26e4fcSRobert Mustacchi u8 command; 2347*9d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_OPEN 0 2348*9d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_CLOSE 1 2349*9d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_INC 2 2350*9d26e4fcSRobert Mustacchi u8 reserved2[3]; 2351*9d26e4fcSRobert Mustacchi __le32 address_high; 2352*9d26e4fcSRobert Mustacchi __le32 address_low; 2353*9d26e4fcSRobert Mustacchi }; 2354*9d26e4fcSRobert Mustacchi 2355*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2356*9d26e4fcSRobert Mustacchi 2357*9d26e4fcSRobert Mustacchi /* Debug Read Register command (0xFF03) 2358*9d26e4fcSRobert Mustacchi * Debug Write Register command (0xFF04) 2359*9d26e4fcSRobert Mustacchi */ 2360*9d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_read_write { 2361*9d26e4fcSRobert Mustacchi __le32 reserved; 2362*9d26e4fcSRobert Mustacchi __le32 address; 2363*9d26e4fcSRobert Mustacchi __le32 value_high; 2364*9d26e4fcSRobert Mustacchi __le32 value_low; 2365*9d26e4fcSRobert Mustacchi }; 2366*9d26e4fcSRobert Mustacchi 2367*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2368*9d26e4fcSRobert Mustacchi 2369*9d26e4fcSRobert Mustacchi /* Scatter/gather Reg Read (indirect 0xFF05) 2370*9d26e4fcSRobert Mustacchi * Scatter/gather Reg Write (indirect 0xFF06) 2371*9d26e4fcSRobert Mustacchi */ 2372*9d26e4fcSRobert Mustacchi 2373*9d26e4fcSRobert Mustacchi /* i40e_aq_desc is used for the command */ 2374*9d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_sg_element_data { 2375*9d26e4fcSRobert Mustacchi __le32 address; 2376*9d26e4fcSRobert Mustacchi __le32 value; 2377*9d26e4fcSRobert Mustacchi }; 2378*9d26e4fcSRobert Mustacchi 2379*9d26e4fcSRobert Mustacchi /* Debug Modify register (direct 0xFF07) */ 2380*9d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_reg { 2381*9d26e4fcSRobert Mustacchi __le32 address; 2382*9d26e4fcSRobert Mustacchi __le32 value; 2383*9d26e4fcSRobert Mustacchi __le32 clear_mask; 2384*9d26e4fcSRobert Mustacchi __le32 set_mask; 2385*9d26e4fcSRobert Mustacchi }; 2386*9d26e4fcSRobert Mustacchi 2387*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2388*9d26e4fcSRobert Mustacchi 2389*9d26e4fcSRobert Mustacchi /* dump internal data (0xFF08, indirect) */ 2390*9d26e4fcSRobert Mustacchi 2391*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_AUX 0 2392*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2393*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2394*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_HMC 3 2395*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC0 4 2396*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC1 5 2397*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC2 6 2398*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC3 7 2399*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_DCB 8 2400*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2401*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2402*9d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2403*9d26e4fcSRobert Mustacchi 2404*9d26e4fcSRobert Mustacchi struct i40e_aqc_debug_dump_internals { 2405*9d26e4fcSRobert Mustacchi u8 cluster_id; 2406*9d26e4fcSRobert Mustacchi u8 table_id; 2407*9d26e4fcSRobert Mustacchi __le16 data_size; 2408*9d26e4fcSRobert Mustacchi __le32 idx; 2409*9d26e4fcSRobert Mustacchi __le32 address_high; 2410*9d26e4fcSRobert Mustacchi __le32 address_low; 2411*9d26e4fcSRobert Mustacchi }; 2412*9d26e4fcSRobert Mustacchi 2413*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2414*9d26e4fcSRobert Mustacchi 2415*9d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_internals { 2416*9d26e4fcSRobert Mustacchi u8 cluster_id; 2417*9d26e4fcSRobert Mustacchi u8 cluster_specific_params[7]; 2418*9d26e4fcSRobert Mustacchi __le32 address_high; 2419*9d26e4fcSRobert Mustacchi __le32 address_low; 2420*9d26e4fcSRobert Mustacchi }; 2421*9d26e4fcSRobert Mustacchi 2422*9d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2423*9d26e4fcSRobert Mustacchi 2424*9d26e4fcSRobert Mustacchi #endif 2425