19d26e4fcSRobert Mustacchi /****************************************************************************** 29d26e4fcSRobert Mustacchi 39d26e4fcSRobert Mustacchi Copyright (c) 2013-2015, Intel Corporation 49d26e4fcSRobert Mustacchi All rights reserved. 59d26e4fcSRobert Mustacchi 69d26e4fcSRobert Mustacchi Redistribution and use in source and binary forms, with or without 79d26e4fcSRobert Mustacchi modification, are permitted provided that the following conditions are met: 89d26e4fcSRobert Mustacchi 99d26e4fcSRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 109d26e4fcSRobert Mustacchi this list of conditions and the following disclaimer. 119d26e4fcSRobert Mustacchi 129d26e4fcSRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 139d26e4fcSRobert Mustacchi notice, this list of conditions and the following disclaimer in the 149d26e4fcSRobert Mustacchi documentation and/or other materials provided with the distribution. 159d26e4fcSRobert Mustacchi 169d26e4fcSRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 179d26e4fcSRobert Mustacchi contributors may be used to endorse or promote products derived from 189d26e4fcSRobert Mustacchi this software without specific prior written permission. 199d26e4fcSRobert Mustacchi 209d26e4fcSRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 219d26e4fcSRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 229d26e4fcSRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 239d26e4fcSRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 249d26e4fcSRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 259d26e4fcSRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 269d26e4fcSRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 279d26e4fcSRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 289d26e4fcSRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 299d26e4fcSRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 309d26e4fcSRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 319d26e4fcSRobert Mustacchi 329d26e4fcSRobert Mustacchi ******************************************************************************/ 33*3d75a287SRobert Mustacchi /*$FreeBSD$*/ 349d26e4fcSRobert Mustacchi 359d26e4fcSRobert Mustacchi #ifndef _I40E_ADMINQ_CMD_H_ 369d26e4fcSRobert Mustacchi #define _I40E_ADMINQ_CMD_H_ 379d26e4fcSRobert Mustacchi 389d26e4fcSRobert Mustacchi /* This header file defines the i40e Admin Queue commands and is shared between 399d26e4fcSRobert Mustacchi * i40e Firmware and Software. 409d26e4fcSRobert Mustacchi * 419d26e4fcSRobert Mustacchi * This file needs to comply with the Linux Kernel coding style. 429d26e4fcSRobert Mustacchi */ 439d26e4fcSRobert Mustacchi 449d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MAJOR 0x0001 45*3d75a287SRobert Mustacchi #define I40E_FW_API_VERSION_MINOR 0x0005 469d26e4fcSRobert Mustacchi 479d26e4fcSRobert Mustacchi struct i40e_aq_desc { 489d26e4fcSRobert Mustacchi __le16 flags; 499d26e4fcSRobert Mustacchi __le16 opcode; 509d26e4fcSRobert Mustacchi __le16 datalen; 519d26e4fcSRobert Mustacchi __le16 retval; 529d26e4fcSRobert Mustacchi __le32 cookie_high; 539d26e4fcSRobert Mustacchi __le32 cookie_low; 549d26e4fcSRobert Mustacchi union { 559d26e4fcSRobert Mustacchi struct { 569d26e4fcSRobert Mustacchi __le32 param0; 579d26e4fcSRobert Mustacchi __le32 param1; 589d26e4fcSRobert Mustacchi __le32 param2; 599d26e4fcSRobert Mustacchi __le32 param3; 609d26e4fcSRobert Mustacchi } internal; 619d26e4fcSRobert Mustacchi struct { 629d26e4fcSRobert Mustacchi __le32 param0; 639d26e4fcSRobert Mustacchi __le32 param1; 649d26e4fcSRobert Mustacchi __le32 addr_high; 659d26e4fcSRobert Mustacchi __le32 addr_low; 669d26e4fcSRobert Mustacchi } external; 679d26e4fcSRobert Mustacchi u8 raw[16]; 689d26e4fcSRobert Mustacchi } params; 699d26e4fcSRobert Mustacchi }; 709d26e4fcSRobert Mustacchi 719d26e4fcSRobert Mustacchi /* Flags sub-structure 729d26e4fcSRobert Mustacchi * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 739d26e4fcSRobert Mustacchi * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 749d26e4fcSRobert Mustacchi */ 759d26e4fcSRobert Mustacchi 769d26e4fcSRobert Mustacchi /* command flags and offsets*/ 779d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD_SHIFT 0 789d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP_SHIFT 1 799d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR_SHIFT 2 809d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE_SHIFT 3 819d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB_SHIFT 9 829d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD_SHIFT 10 839d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC_SHIFT 11 849d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF_SHIFT 12 859d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI_SHIFT 13 869d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI_SHIFT 14 879d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE_SHIFT 15 889d26e4fcSRobert Mustacchi 899d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 909d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 919d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 929d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 939d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 949d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 959d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 969d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 979d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 989d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 999d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 1009d26e4fcSRobert Mustacchi 1019d26e4fcSRobert Mustacchi /* error codes */ 1029d26e4fcSRobert Mustacchi enum i40e_admin_queue_err { 1039d26e4fcSRobert Mustacchi I40E_AQ_RC_OK = 0, /* success */ 1049d26e4fcSRobert Mustacchi I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 1059d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOENT = 2, /* No such element */ 1069d26e4fcSRobert Mustacchi I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 1079d26e4fcSRobert Mustacchi I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 1089d26e4fcSRobert Mustacchi I40E_AQ_RC_EIO = 5, /* I/O error */ 1099d26e4fcSRobert Mustacchi I40E_AQ_RC_ENXIO = 6, /* No such resource */ 1109d26e4fcSRobert Mustacchi I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 1119d26e4fcSRobert Mustacchi I40E_AQ_RC_EAGAIN = 8, /* Try again */ 1129d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 1139d26e4fcSRobert Mustacchi I40E_AQ_RC_EACCES = 10, /* Permission denied */ 1149d26e4fcSRobert Mustacchi I40E_AQ_RC_EFAULT = 11, /* Bad address */ 1159d26e4fcSRobert Mustacchi I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1169d26e4fcSRobert Mustacchi I40E_AQ_RC_EEXIST = 13, /* object already exists */ 1179d26e4fcSRobert Mustacchi I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 1189d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 1199d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 1209d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1219d26e4fcSRobert Mustacchi I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 1229d26e4fcSRobert Mustacchi I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 1239d26e4fcSRobert Mustacchi I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 1249d26e4fcSRobert Mustacchi I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1259d26e4fcSRobert Mustacchi I40E_AQ_RC_EFBIG = 22, /* File too large */ 1269d26e4fcSRobert Mustacchi }; 1279d26e4fcSRobert Mustacchi 1289d26e4fcSRobert Mustacchi /* Admin Queue command opcodes */ 1299d26e4fcSRobert Mustacchi enum i40e_admin_queue_opc { 1309d26e4fcSRobert Mustacchi /* aq commands */ 1319d26e4fcSRobert Mustacchi i40e_aqc_opc_get_version = 0x0001, 1329d26e4fcSRobert Mustacchi i40e_aqc_opc_driver_version = 0x0002, 1339d26e4fcSRobert Mustacchi i40e_aqc_opc_queue_shutdown = 0x0003, 1349d26e4fcSRobert Mustacchi i40e_aqc_opc_set_pf_context = 0x0004, 1359d26e4fcSRobert Mustacchi 1369d26e4fcSRobert Mustacchi /* resource ownership */ 1379d26e4fcSRobert Mustacchi i40e_aqc_opc_request_resource = 0x0008, 1389d26e4fcSRobert Mustacchi i40e_aqc_opc_release_resource = 0x0009, 1399d26e4fcSRobert Mustacchi 1409d26e4fcSRobert Mustacchi i40e_aqc_opc_list_func_capabilities = 0x000A, 1419d26e4fcSRobert Mustacchi i40e_aqc_opc_list_dev_capabilities = 0x000B, 1429d26e4fcSRobert Mustacchi 143*3d75a287SRobert Mustacchi /* Proxy commands */ 144*3d75a287SRobert Mustacchi i40e_aqc_opc_set_proxy_config = 0x0104, 145*3d75a287SRobert Mustacchi i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146*3d75a287SRobert Mustacchi 1479d26e4fcSRobert Mustacchi /* LAA */ 1489d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_read = 0x0107, 1499d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_write = 0x0108, 1509d26e4fcSRobert Mustacchi 1519d26e4fcSRobert Mustacchi /* PXE */ 1529d26e4fcSRobert Mustacchi i40e_aqc_opc_clear_pxe_mode = 0x0110, 1539d26e4fcSRobert Mustacchi 154*3d75a287SRobert Mustacchi /* WoL commands */ 155*3d75a287SRobert Mustacchi i40e_aqc_opc_set_wol_filter = 0x0120, 156*3d75a287SRobert Mustacchi i40e_aqc_opc_get_wake_reason = 0x0121, 157*3d75a287SRobert Mustacchi 1589d26e4fcSRobert Mustacchi /* internal switch commands */ 1599d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_config = 0x0200, 1609d26e4fcSRobert Mustacchi i40e_aqc_opc_add_statistics = 0x0201, 1619d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_statistics = 0x0202, 1629d26e4fcSRobert Mustacchi i40e_aqc_opc_set_port_parameters = 0x0203, 1639d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164*3d75a287SRobert Mustacchi i40e_aqc_opc_set_switch_config = 0x0205, 165396505afSPaul Winder i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 166396505afSPaul Winder i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 167396505afSPaul Winder 1689d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vsi = 0x0210, 1699d26e4fcSRobert Mustacchi i40e_aqc_opc_update_vsi_parameters = 0x0211, 1709d26e4fcSRobert Mustacchi i40e_aqc_opc_get_vsi_parameters = 0x0212, 1719d26e4fcSRobert Mustacchi 1729d26e4fcSRobert Mustacchi i40e_aqc_opc_add_pv = 0x0220, 1739d26e4fcSRobert Mustacchi i40e_aqc_opc_update_pv_parameters = 0x0221, 1749d26e4fcSRobert Mustacchi i40e_aqc_opc_get_pv_parameters = 0x0222, 1759d26e4fcSRobert Mustacchi 1769d26e4fcSRobert Mustacchi i40e_aqc_opc_add_veb = 0x0230, 1779d26e4fcSRobert Mustacchi i40e_aqc_opc_update_veb_parameters = 0x0231, 1789d26e4fcSRobert Mustacchi i40e_aqc_opc_get_veb_parameters = 0x0232, 1799d26e4fcSRobert Mustacchi 1809d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_element = 0x0243, 1819d26e4fcSRobert Mustacchi 1829d26e4fcSRobert Mustacchi i40e_aqc_opc_add_macvlan = 0x0250, 1839d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_macvlan = 0x0251, 1849d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vlan = 0x0252, 1859d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_vlan = 0x0253, 1869d26e4fcSRobert Mustacchi i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 1879d26e4fcSRobert Mustacchi i40e_aqc_opc_add_tag = 0x0255, 1889d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_tag = 0x0256, 1899d26e4fcSRobert Mustacchi i40e_aqc_opc_add_multicast_etag = 0x0257, 1909d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_multicast_etag = 0x0258, 1919d26e4fcSRobert Mustacchi i40e_aqc_opc_update_tag = 0x0259, 1929d26e4fcSRobert Mustacchi i40e_aqc_opc_add_control_packet_filter = 0x025A, 1939d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_control_packet_filter = 0x025B, 1949d26e4fcSRobert Mustacchi i40e_aqc_opc_add_cloud_filters = 0x025C, 1959d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_cloud_filters = 0x025D, 196*3d75a287SRobert Mustacchi i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 1979d26e4fcSRobert Mustacchi 1989d26e4fcSRobert Mustacchi i40e_aqc_opc_add_mirror_rule = 0x0260, 1999d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_mirror_rule = 0x0261, 2009d26e4fcSRobert Mustacchi 2019d26e4fcSRobert Mustacchi /* DCB commands */ 2029d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 2039d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_updated = 0x0302, 2049d26e4fcSRobert Mustacchi 2059d26e4fcSRobert Mustacchi /* TX scheduler */ 2069d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 2079d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 2089d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 2099d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_bw_config = 0x0408, 2109d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 2119d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 2129d26e4fcSRobert Mustacchi 2139d26e4fcSRobert Mustacchi i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 2149d26e4fcSRobert Mustacchi i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 2159d26e4fcSRobert Mustacchi i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 2169d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 2179d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 2189d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 2199d26e4fcSRobert Mustacchi i40e_aqc_opc_query_port_ets_config = 0x0419, 2209d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 2219d26e4fcSRobert Mustacchi i40e_aqc_opc_suspend_port_tx = 0x041B, 2229d26e4fcSRobert Mustacchi i40e_aqc_opc_resume_port_tx = 0x041C, 2239d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_partition_bw = 0x041D, 2249d26e4fcSRobert Mustacchi /* hmc */ 2259d26e4fcSRobert Mustacchi i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 2269d26e4fcSRobert Mustacchi i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 2279d26e4fcSRobert Mustacchi 228*3d75a287SRobert Mustacchi /* phy commands*/ 229*3d75a287SRobert Mustacchi 2309d26e4fcSRobert Mustacchi /* phy commands*/ 2319d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_abilities = 0x0600, 2329d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_config = 0x0601, 2339d26e4fcSRobert Mustacchi i40e_aqc_opc_set_mac_config = 0x0603, 2349d26e4fcSRobert Mustacchi i40e_aqc_opc_set_link_restart_an = 0x0605, 2359d26e4fcSRobert Mustacchi i40e_aqc_opc_get_link_status = 0x0607, 2369d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_int_mask = 0x0613, 2379d26e4fcSRobert Mustacchi i40e_aqc_opc_get_local_advt_reg = 0x0614, 2389d26e4fcSRobert Mustacchi i40e_aqc_opc_set_local_advt_reg = 0x0615, 2399d26e4fcSRobert Mustacchi i40e_aqc_opc_get_partner_advt = 0x0616, 2409d26e4fcSRobert Mustacchi i40e_aqc_opc_set_lb_modes = 0x0618, 2419d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_wol_caps = 0x0621, 2429d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_debug = 0x0622, 2439d26e4fcSRobert Mustacchi i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 244*3d75a287SRobert Mustacchi i40e_aqc_opc_run_phy_activity = 0x0626, 2459d26e4fcSRobert Mustacchi 2469d26e4fcSRobert Mustacchi /* NVM commands */ 2479d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_read = 0x0701, 2489d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_erase = 0x0702, 2499d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_update = 0x0703, 2509d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_read = 0x0704, 2519d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_write = 0x0705, 2529d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_post_update = 0x0720, 253*3d75a287SRobert Mustacchi i40e_aqc_opc_thermal_sensor = 0x0721, 2549d26e4fcSRobert Mustacchi 2559d26e4fcSRobert Mustacchi /* virtualization commands */ 2569d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_pf = 0x0801, 2579d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_vf = 0x0802, 2589d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_peer = 0x0803, 2599d26e4fcSRobert Mustacchi 2609d26e4fcSRobert Mustacchi /* alternate structure */ 2619d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write = 0x0900, 2629d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_indirect = 0x0901, 2639d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read = 0x0902, 2649d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read_indirect = 0x0903, 2659d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_done = 0x0904, 2669d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_set_mode = 0x0905, 2679d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_clear_port = 0x0906, 2689d26e4fcSRobert Mustacchi 2699d26e4fcSRobert Mustacchi /* LLDP commands */ 2709d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_get_mib = 0x0A00, 2719d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_mib = 0x0A01, 2729d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_add_tlv = 0x0A02, 2739d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_tlv = 0x0A03, 2749d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 2759d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop = 0x0A05, 2769d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_start = 0x0A06, 2779d26e4fcSRobert Mustacchi i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2789d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 2799d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 2809d26e4fcSRobert Mustacchi 2819d26e4fcSRobert Mustacchi /* Tunnel commands */ 2829d26e4fcSRobert Mustacchi i40e_aqc_opc_add_udp_tunnel = 0x0B00, 2839d26e4fcSRobert Mustacchi i40e_aqc_opc_del_udp_tunnel = 0x0B01, 2849d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_key = 0x0B02, 2859d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_lut = 0x0B03, 2869d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_key = 0x0B04, 2879d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_lut = 0x0B05, 2889d26e4fcSRobert Mustacchi 2899d26e4fcSRobert Mustacchi /* Async Events */ 2909d26e4fcSRobert Mustacchi i40e_aqc_opc_event_lan_overflow = 0x1001, 2919d26e4fcSRobert Mustacchi 2929d26e4fcSRobert Mustacchi /* OEM commands */ 2939d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_parameter_change = 0xFE00, 2949d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_device_status_change = 0xFE01, 2959d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 2969d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 2979d26e4fcSRobert Mustacchi 2989d26e4fcSRobert Mustacchi /* debug commands */ 2999d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_read_reg = 0xFF03, 3009d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_write_reg = 0xFF04, 3019d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_modify_reg = 0xFF07, 3029d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_dump_internals = 0xFF08, 3039d26e4fcSRobert Mustacchi }; 3049d26e4fcSRobert Mustacchi 3059d26e4fcSRobert Mustacchi /* command structures and indirect data structures */ 3069d26e4fcSRobert Mustacchi 3079d26e4fcSRobert Mustacchi /* Structure naming conventions: 3089d26e4fcSRobert Mustacchi * - no suffix for direct command descriptor structures 3099d26e4fcSRobert Mustacchi * - _data for indirect sent data 3109d26e4fcSRobert Mustacchi * - _resp for indirect return data (data which is both will use _data) 3119d26e4fcSRobert Mustacchi * - _completion for direct return data 3129d26e4fcSRobert Mustacchi * - _element_ for repeated elements (may also be _data or _resp) 3139d26e4fcSRobert Mustacchi * 3149d26e4fcSRobert Mustacchi * Command structures are expected to overlay the params.raw member of the basic 3159d26e4fcSRobert Mustacchi * descriptor, and as such cannot exceed 16 bytes in length. 3169d26e4fcSRobert Mustacchi */ 3179d26e4fcSRobert Mustacchi 3189d26e4fcSRobert Mustacchi /* This macro is used to generate a compilation error if a structure 3199d26e4fcSRobert Mustacchi * is not exactly the correct length. It gives a divide by zero error if the 3209d26e4fcSRobert Mustacchi * structure is not of the correct size, otherwise it creates an enum that is 3219d26e4fcSRobert Mustacchi * never used. 3229d26e4fcSRobert Mustacchi */ 3239d26e4fcSRobert Mustacchi #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 3249d26e4fcSRobert Mustacchi { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 3259d26e4fcSRobert Mustacchi 3269d26e4fcSRobert Mustacchi /* This macro is used extensively to ensure that command structures are 16 3279d26e4fcSRobert Mustacchi * bytes in length as they have to map to the raw array of that size. 3289d26e4fcSRobert Mustacchi */ 3299d26e4fcSRobert Mustacchi #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 3309d26e4fcSRobert Mustacchi 3319d26e4fcSRobert Mustacchi /* internal (0x00XX) commands */ 3329d26e4fcSRobert Mustacchi 3339d26e4fcSRobert Mustacchi /* Get version (direct 0x0001) */ 3349d26e4fcSRobert Mustacchi struct i40e_aqc_get_version { 3359d26e4fcSRobert Mustacchi __le32 rom_ver; 3369d26e4fcSRobert Mustacchi __le32 fw_build; 3379d26e4fcSRobert Mustacchi __le16 fw_major; 3389d26e4fcSRobert Mustacchi __le16 fw_minor; 3399d26e4fcSRobert Mustacchi __le16 api_major; 3409d26e4fcSRobert Mustacchi __le16 api_minor; 3419d26e4fcSRobert Mustacchi }; 3429d26e4fcSRobert Mustacchi 3439d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 3449d26e4fcSRobert Mustacchi 3459d26e4fcSRobert Mustacchi /* Send driver version (indirect 0x0002) */ 3469d26e4fcSRobert Mustacchi struct i40e_aqc_driver_version { 3479d26e4fcSRobert Mustacchi u8 driver_major_ver; 3489d26e4fcSRobert Mustacchi u8 driver_minor_ver; 3499d26e4fcSRobert Mustacchi u8 driver_build_ver; 3509d26e4fcSRobert Mustacchi u8 driver_subbuild_ver; 3519d26e4fcSRobert Mustacchi u8 reserved[4]; 3529d26e4fcSRobert Mustacchi __le32 address_high; 3539d26e4fcSRobert Mustacchi __le32 address_low; 3549d26e4fcSRobert Mustacchi }; 3559d26e4fcSRobert Mustacchi 3569d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 3579d26e4fcSRobert Mustacchi 3589d26e4fcSRobert Mustacchi /* Queue Shutdown (direct 0x0003) */ 3599d26e4fcSRobert Mustacchi struct i40e_aqc_queue_shutdown { 3609d26e4fcSRobert Mustacchi __le32 driver_unloading; 3619d26e4fcSRobert Mustacchi #define I40E_AQ_DRIVER_UNLOADING 0x1 3629d26e4fcSRobert Mustacchi u8 reserved[12]; 3639d26e4fcSRobert Mustacchi }; 3649d26e4fcSRobert Mustacchi 3659d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 3669d26e4fcSRobert Mustacchi 3679d26e4fcSRobert Mustacchi /* Set PF context (0x0004, direct) */ 3689d26e4fcSRobert Mustacchi struct i40e_aqc_set_pf_context { 3699d26e4fcSRobert Mustacchi u8 pf_id; 3709d26e4fcSRobert Mustacchi u8 reserved[15]; 3719d26e4fcSRobert Mustacchi }; 3729d26e4fcSRobert Mustacchi 3739d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 3749d26e4fcSRobert Mustacchi 3759d26e4fcSRobert Mustacchi /* Request resource ownership (direct 0x0008) 3769d26e4fcSRobert Mustacchi * Release resource ownership (direct 0x0009) 3779d26e4fcSRobert Mustacchi */ 3789d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM 1 3799d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_SDP 2 3809d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_READ 1 3819d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 3829d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 3839d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 3849d26e4fcSRobert Mustacchi 3859d26e4fcSRobert Mustacchi struct i40e_aqc_request_resource { 3869d26e4fcSRobert Mustacchi __le16 resource_id; 3879d26e4fcSRobert Mustacchi __le16 access_type; 3889d26e4fcSRobert Mustacchi __le32 timeout; 3899d26e4fcSRobert Mustacchi __le32 resource_number; 3909d26e4fcSRobert Mustacchi u8 reserved[4]; 3919d26e4fcSRobert Mustacchi }; 3929d26e4fcSRobert Mustacchi 3939d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 3949d26e4fcSRobert Mustacchi 3959d26e4fcSRobert Mustacchi /* Get function capabilities (indirect 0x000A) 3969d26e4fcSRobert Mustacchi * Get device capabilities (indirect 0x000B) 3979d26e4fcSRobert Mustacchi */ 3989d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilites { 3999d26e4fcSRobert Mustacchi u8 command_flags; 4009d26e4fcSRobert Mustacchi #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 4019d26e4fcSRobert Mustacchi u8 pf_index; 4029d26e4fcSRobert Mustacchi u8 reserved[2]; 4039d26e4fcSRobert Mustacchi __le32 count; 4049d26e4fcSRobert Mustacchi __le32 addr_high; 4059d26e4fcSRobert Mustacchi __le32 addr_low; 4069d26e4fcSRobert Mustacchi }; 4079d26e4fcSRobert Mustacchi 4089d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 4099d26e4fcSRobert Mustacchi 4109d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilities_element_resp { 4119d26e4fcSRobert Mustacchi __le16 id; 4129d26e4fcSRobert Mustacchi u8 major_rev; 4139d26e4fcSRobert Mustacchi u8 minor_rev; 4149d26e4fcSRobert Mustacchi __le32 number; 4159d26e4fcSRobert Mustacchi __le32 logical_id; 4169d26e4fcSRobert Mustacchi __le32 phys_id; 4179d26e4fcSRobert Mustacchi u8 reserved[16]; 4189d26e4fcSRobert Mustacchi }; 4199d26e4fcSRobert Mustacchi 4209d26e4fcSRobert Mustacchi /* list of caps */ 4219d26e4fcSRobert Mustacchi 4229d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 4239d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 4249d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 4259d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 4269d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 4279d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 428*3d75a287SRobert Mustacchi #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 4299d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SRIOV 0x0012 4309d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF 0x0013 4319d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VMDQ 0x0014 4329d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBG 0x0015 4339d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBR 0x0016 4349d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VSI 0x0017 4359d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_DCB 0x0018 4369d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FCOE 0x0021 4379d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ISCSI 0x0022 4389d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RSS 0x0040 4399d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RXQ 0x0041 4409d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_TXQ 0x0042 4419d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MSIX 0x0043 4429d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 4439d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 4449d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_1588 0x0046 4459d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_IWARP 0x0051 4469d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_LED 0x0061 4479d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SDP 0x0062 4489d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MDIO 0x0063 449*3d75a287SRobert Mustacchi #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 450*3d75a287SRobert Mustacchi #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 4519d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLEX10 0x00F1 4529d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_CEM 0x00F2 4539d26e4fcSRobert Mustacchi 4549d26e4fcSRobert Mustacchi /* Set CPPM Configuration (direct 0x0103) */ 4559d26e4fcSRobert Mustacchi struct i40e_aqc_cppm_configuration { 4569d26e4fcSRobert Mustacchi __le16 command_flags; 4579d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_LTRC 0x0800 4589d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTH 0x1000 4599d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 4609d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_HPTC 0x4000 4619d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMARC 0x8000 4629d26e4fcSRobert Mustacchi __le16 ttlx; 4639d26e4fcSRobert Mustacchi __le32 dmacr; 4649d26e4fcSRobert Mustacchi __le16 dmcth; 4659d26e4fcSRobert Mustacchi u8 hptc; 4669d26e4fcSRobert Mustacchi u8 reserved; 4679d26e4fcSRobert Mustacchi __le32 pfltrc; 4689d26e4fcSRobert Mustacchi }; 4699d26e4fcSRobert Mustacchi 4709d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 4719d26e4fcSRobert Mustacchi 4729d26e4fcSRobert Mustacchi /* Set ARP Proxy command / response (indirect 0x0104) */ 4739d26e4fcSRobert Mustacchi struct i40e_aqc_arp_proxy_data { 4749d26e4fcSRobert Mustacchi __le16 command_flags; 475*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_INIT_IPV4 0x0800 476*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_UNSUP_CTL 0x1000 477*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_ENA 0x2000 478*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_ADD_IPV4 0x4000 479*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_DEL_IPV4 0x8000 4809d26e4fcSRobert Mustacchi __le16 table_id; 481*3d75a287SRobert Mustacchi __le32 enabled_offloads; 482*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 483*3d75a287SRobert Mustacchi #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 4849d26e4fcSRobert Mustacchi __le32 ip_addr; 4859d26e4fcSRobert Mustacchi u8 mac_addr[6]; 4869d26e4fcSRobert Mustacchi u8 reserved[2]; 4879d26e4fcSRobert Mustacchi }; 4889d26e4fcSRobert Mustacchi 4899d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 4909d26e4fcSRobert Mustacchi 4919d26e4fcSRobert Mustacchi /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 4929d26e4fcSRobert Mustacchi struct i40e_aqc_ns_proxy_data { 4939d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_0; 4949d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_1; 4959d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_0; 4969d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_1; 4979d26e4fcSRobert Mustacchi __le16 control; 498*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_0 0x0001 499*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_0 0x0002 500*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_1 0x0004 501*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_1 0x0008 502*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 503*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 504*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 505*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 506*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 507*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 508*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 509*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 510*3d75a287SRobert Mustacchi #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 5119d26e4fcSRobert Mustacchi u8 mac_addr_0[6]; 5129d26e4fcSRobert Mustacchi u8 mac_addr_1[6]; 5139d26e4fcSRobert Mustacchi u8 local_mac_addr[6]; 5149d26e4fcSRobert Mustacchi u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 5159d26e4fcSRobert Mustacchi u8 ipv6_addr_1[16]; 5169d26e4fcSRobert Mustacchi }; 5179d26e4fcSRobert Mustacchi 5189d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 5199d26e4fcSRobert Mustacchi 5209d26e4fcSRobert Mustacchi /* Manage LAA Command (0x0106) - obsolete */ 5219d26e4fcSRobert Mustacchi struct i40e_aqc_mng_laa { 5229d26e4fcSRobert Mustacchi __le16 command_flags; 5239d26e4fcSRobert Mustacchi #define I40E_AQ_LAA_FLAG_WR 0x8000 5249d26e4fcSRobert Mustacchi u8 reserved[2]; 5259d26e4fcSRobert Mustacchi __le32 sal; 5269d26e4fcSRobert Mustacchi __le16 sah; 5279d26e4fcSRobert Mustacchi u8 reserved2[6]; 5289d26e4fcSRobert Mustacchi }; 5299d26e4fcSRobert Mustacchi 5309d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 5319d26e4fcSRobert Mustacchi 5329d26e4fcSRobert Mustacchi /* Manage MAC Address Read Command (indirect 0x0107) */ 5339d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read { 5349d26e4fcSRobert Mustacchi __le16 command_flags; 5359d26e4fcSRobert Mustacchi #define I40E_AQC_LAN_ADDR_VALID 0x10 5369d26e4fcSRobert Mustacchi #define I40E_AQC_SAN_ADDR_VALID 0x20 5379d26e4fcSRobert Mustacchi #define I40E_AQC_PORT_ADDR_VALID 0x40 5389d26e4fcSRobert Mustacchi #define I40E_AQC_WOL_ADDR_VALID 0x80 5399d26e4fcSRobert Mustacchi #define I40E_AQC_MC_MAG_EN_VALID 0x100 540*3d75a287SRobert Mustacchi #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 541*3d75a287SRobert Mustacchi #define I40E_AQC_ADDR_VALID_MASK 0x3F0 5429d26e4fcSRobert Mustacchi u8 reserved[6]; 5439d26e4fcSRobert Mustacchi __le32 addr_high; 5449d26e4fcSRobert Mustacchi __le32 addr_low; 5459d26e4fcSRobert Mustacchi }; 5469d26e4fcSRobert Mustacchi 5479d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 5489d26e4fcSRobert Mustacchi 5499d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read_data { 5509d26e4fcSRobert Mustacchi u8 pf_lan_mac[6]; 5519d26e4fcSRobert Mustacchi u8 pf_san_mac[6]; 5529d26e4fcSRobert Mustacchi u8 port_mac[6]; 5539d26e4fcSRobert Mustacchi u8 pf_wol_mac[6]; 5549d26e4fcSRobert Mustacchi }; 5559d26e4fcSRobert Mustacchi 5569d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 5579d26e4fcSRobert Mustacchi 5589d26e4fcSRobert Mustacchi /* Manage MAC Address Write Command (0x0108) */ 5599d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_write { 5609d26e4fcSRobert Mustacchi __le16 command_flags; 561*3d75a287SRobert Mustacchi #define I40E_AQC_MC_MAG_EN 0x0100 562*3d75a287SRobert Mustacchi #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 5639d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 5649d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 5659d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_PORT 0x8000 5669d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 5679d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_MASK 0xC000 5689d26e4fcSRobert Mustacchi 5699d26e4fcSRobert Mustacchi __le16 mac_sah; 5709d26e4fcSRobert Mustacchi __le32 mac_sal; 5719d26e4fcSRobert Mustacchi u8 reserved[8]; 5729d26e4fcSRobert Mustacchi }; 5739d26e4fcSRobert Mustacchi 5749d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 5759d26e4fcSRobert Mustacchi 5769d26e4fcSRobert Mustacchi /* PXE commands (0x011x) */ 5779d26e4fcSRobert Mustacchi 5789d26e4fcSRobert Mustacchi /* Clear PXE Command and response (direct 0x0110) */ 5799d26e4fcSRobert Mustacchi struct i40e_aqc_clear_pxe { 5809d26e4fcSRobert Mustacchi u8 rx_cnt; 5819d26e4fcSRobert Mustacchi u8 reserved[15]; 5829d26e4fcSRobert Mustacchi }; 5839d26e4fcSRobert Mustacchi 5849d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 5859d26e4fcSRobert Mustacchi 586*3d75a287SRobert Mustacchi /* Set WoL Filter (0x0120) */ 587*3d75a287SRobert Mustacchi 588*3d75a287SRobert Mustacchi struct i40e_aqc_set_wol_filter { 589*3d75a287SRobert Mustacchi __le16 filter_index; 590*3d75a287SRobert Mustacchi #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 591*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 592*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 593*3d75a287SRobert Mustacchi I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 594*3d75a287SRobert Mustacchi 595*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 596*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 597*3d75a287SRobert Mustacchi I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 598*3d75a287SRobert Mustacchi __le16 cmd_flags; 599*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER 0x8000 600*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 601*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 602*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 603*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 604*3d75a287SRobert Mustacchi __le16 valid_flags; 605*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 606*3d75a287SRobert Mustacchi #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 607*3d75a287SRobert Mustacchi u8 reserved[2]; 608*3d75a287SRobert Mustacchi __le32 address_high; 609*3d75a287SRobert Mustacchi __le32 address_low; 610*3d75a287SRobert Mustacchi }; 611*3d75a287SRobert Mustacchi 612*3d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 613*3d75a287SRobert Mustacchi 614*3d75a287SRobert Mustacchi struct i40e_aqc_set_wol_filter_data { 615*3d75a287SRobert Mustacchi u8 filter[128]; 616*3d75a287SRobert Mustacchi u8 mask[16]; 617*3d75a287SRobert Mustacchi }; 618*3d75a287SRobert Mustacchi 619*3d75a287SRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 620*3d75a287SRobert Mustacchi 621*3d75a287SRobert Mustacchi /* Get Wake Reason (0x0121) */ 622*3d75a287SRobert Mustacchi 623*3d75a287SRobert Mustacchi struct i40e_aqc_get_wake_reason_completion { 624*3d75a287SRobert Mustacchi u8 reserved_1[2]; 625*3d75a287SRobert Mustacchi __le16 wake_reason; 626*3d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 627*3d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 628*3d75a287SRobert Mustacchi I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 629*3d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 630*3d75a287SRobert Mustacchi #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 631*3d75a287SRobert Mustacchi I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 632*3d75a287SRobert Mustacchi u8 reserved_2[12]; 633*3d75a287SRobert Mustacchi }; 634*3d75a287SRobert Mustacchi 635*3d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 636*3d75a287SRobert Mustacchi 6379d26e4fcSRobert Mustacchi /* Switch configuration commands (0x02xx) */ 6389d26e4fcSRobert Mustacchi 6399d26e4fcSRobert Mustacchi /* Used by many indirect commands that only pass an seid and a buffer in the 6409d26e4fcSRobert Mustacchi * command 6419d26e4fcSRobert Mustacchi */ 6429d26e4fcSRobert Mustacchi struct i40e_aqc_switch_seid { 6439d26e4fcSRobert Mustacchi __le16 seid; 6449d26e4fcSRobert Mustacchi u8 reserved[6]; 6459d26e4fcSRobert Mustacchi __le32 addr_high; 6469d26e4fcSRobert Mustacchi __le32 addr_low; 6479d26e4fcSRobert Mustacchi }; 6489d26e4fcSRobert Mustacchi 6499d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 6509d26e4fcSRobert Mustacchi 6519d26e4fcSRobert Mustacchi /* Get Switch Configuration command (indirect 0x0200) 6529d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 6539d26e4fcSRobert Mustacchi */ 6549d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp { 6559d26e4fcSRobert Mustacchi __le16 num_reported; 6569d26e4fcSRobert Mustacchi __le16 num_total; 6579d26e4fcSRobert Mustacchi u8 reserved[12]; 6589d26e4fcSRobert Mustacchi }; 6599d26e4fcSRobert Mustacchi 6609d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 6619d26e4fcSRobert Mustacchi 6629d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp { 6639d26e4fcSRobert Mustacchi u8 element_type; 6649d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_MAC 1 6659d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PF 2 6669d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VF 3 6679d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_EMP 4 6689d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_BMC 5 6699d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PV 16 6709d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VEB 17 6719d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PA 18 6729d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VSI 19 6739d26e4fcSRobert Mustacchi u8 revision; 6749d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_REV_1 1 6759d26e4fcSRobert Mustacchi __le16 seid; 6769d26e4fcSRobert Mustacchi __le16 uplink_seid; 6779d26e4fcSRobert Mustacchi __le16 downlink_seid; 6789d26e4fcSRobert Mustacchi u8 reserved[3]; 6799d26e4fcSRobert Mustacchi u8 connection_type; 6809d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_REGULAR 0x1 6819d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 6829d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_CASCADED 0x3 6839d26e4fcSRobert Mustacchi __le16 scheduler_id; 6849d26e4fcSRobert Mustacchi __le16 element_info; 6859d26e4fcSRobert Mustacchi }; 6869d26e4fcSRobert Mustacchi 6879d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 6889d26e4fcSRobert Mustacchi 6899d26e4fcSRobert Mustacchi /* Get Switch Configuration (indirect 0x0200) 6909d26e4fcSRobert Mustacchi * an array of elements are returned in the response buffer 6919d26e4fcSRobert Mustacchi * the first in the array is the header, remainder are elements 6929d26e4fcSRobert Mustacchi */ 6939d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_resp { 6949d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp header; 6959d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp element[1]; 6969d26e4fcSRobert Mustacchi }; 6979d26e4fcSRobert Mustacchi 6989d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 6999d26e4fcSRobert Mustacchi 7009d26e4fcSRobert Mustacchi /* Add Statistics (direct 0x0201) 7019d26e4fcSRobert Mustacchi * Remove Statistics (direct 0x0202) 7029d26e4fcSRobert Mustacchi */ 7039d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_statistics { 7049d26e4fcSRobert Mustacchi __le16 seid; 7059d26e4fcSRobert Mustacchi __le16 vlan; 7069d26e4fcSRobert Mustacchi __le16 stat_index; 7079d26e4fcSRobert Mustacchi u8 reserved[10]; 7089d26e4fcSRobert Mustacchi }; 7099d26e4fcSRobert Mustacchi 7109d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 7119d26e4fcSRobert Mustacchi 7129d26e4fcSRobert Mustacchi /* Set Port Parameters command (direct 0x0203) */ 7139d26e4fcSRobert Mustacchi struct i40e_aqc_set_port_parameters { 7149d26e4fcSRobert Mustacchi __le16 command_flags; 7159d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 7169d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 7179d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 7189d26e4fcSRobert Mustacchi __le16 bad_frame_vsi; 719*3d75a287SRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 720*3d75a287SRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 7219d26e4fcSRobert Mustacchi __le16 default_seid; /* reserved for command */ 7229d26e4fcSRobert Mustacchi u8 reserved[10]; 7239d26e4fcSRobert Mustacchi }; 7249d26e4fcSRobert Mustacchi 7259d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 7269d26e4fcSRobert Mustacchi 7279d26e4fcSRobert Mustacchi /* Get Switch Resource Allocation (indirect 0x0204) */ 7289d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_resource_alloc { 7299d26e4fcSRobert Mustacchi u8 num_entries; /* reserved for command */ 7309d26e4fcSRobert Mustacchi u8 reserved[7]; 7319d26e4fcSRobert Mustacchi __le32 addr_high; 7329d26e4fcSRobert Mustacchi __le32 addr_low; 7339d26e4fcSRobert Mustacchi }; 7349d26e4fcSRobert Mustacchi 7359d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 7369d26e4fcSRobert Mustacchi 7379d26e4fcSRobert Mustacchi /* expect an array of these structs in the response buffer */ 7389d26e4fcSRobert Mustacchi struct i40e_aqc_switch_resource_alloc_element_resp { 7399d26e4fcSRobert Mustacchi u8 resource_type; 7409d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 7419d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 7429d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 7439d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 7449d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 7459d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 7469d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 7479d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 7489d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 7499d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 7509d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 7519d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 7529d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 7539d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 7549d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 7559d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 7569d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 7579d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 7589d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 7599d26e4fcSRobert Mustacchi u8 reserved1; 7609d26e4fcSRobert Mustacchi __le16 guaranteed; 7619d26e4fcSRobert Mustacchi __le16 total; 7629d26e4fcSRobert Mustacchi __le16 used; 7639d26e4fcSRobert Mustacchi __le16 total_unalloced; 7649d26e4fcSRobert Mustacchi u8 reserved2[6]; 7659d26e4fcSRobert Mustacchi }; 7669d26e4fcSRobert Mustacchi 7679d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 7689d26e4fcSRobert Mustacchi 769*3d75a287SRobert Mustacchi /* Set Switch Configuration (direct 0x0205) */ 770*3d75a287SRobert Mustacchi struct i40e_aqc_set_switch_config { 771*3d75a287SRobert Mustacchi __le16 flags; 772*3d75a287SRobert Mustacchi /* flags used for both fields below */ 773*3d75a287SRobert Mustacchi #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 774*3d75a287SRobert Mustacchi #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 775*3d75a287SRobert Mustacchi __le16 valid_flags; 776*3d75a287SRobert Mustacchi u8 reserved[12]; 777*3d75a287SRobert Mustacchi }; 778*3d75a287SRobert Mustacchi 779*3d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 780*3d75a287SRobert Mustacchi 781396505afSPaul Winder /* Read Receive control registers (direct 0x0206) 782396505afSPaul Winder * Write Receive control registers (direct 0x0207) 783396505afSPaul Winder * used for accessing Rx control registers that can be 784396505afSPaul Winder * slow and need special handling when under high Rx load 785396505afSPaul Winder */ 786396505afSPaul Winder struct i40e_aqc_rx_ctl_reg_read_write { 787396505afSPaul Winder __le32 reserved1; 788396505afSPaul Winder __le32 address; 789396505afSPaul Winder __le32 reserved2; 790396505afSPaul Winder __le32 value; 791396505afSPaul Winder }; 792396505afSPaul Winder 793396505afSPaul Winder I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 794396505afSPaul Winder 7959d26e4fcSRobert Mustacchi /* Add VSI (indirect 0x0210) 7969d26e4fcSRobert Mustacchi * this indirect command uses struct i40e_aqc_vsi_properties_data 7979d26e4fcSRobert Mustacchi * as the indirect buffer (128 bytes) 7989d26e4fcSRobert Mustacchi * 7999d26e4fcSRobert Mustacchi * Update VSI (indirect 0x211) 8009d26e4fcSRobert Mustacchi * uses the same data structure as Add VSI 8019d26e4fcSRobert Mustacchi * 8029d26e4fcSRobert Mustacchi * Get VSI (indirect 0x0212) 8039d26e4fcSRobert Mustacchi * uses the same completion and data structure as Add VSI 8049d26e4fcSRobert Mustacchi */ 8059d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi { 8069d26e4fcSRobert Mustacchi __le16 uplink_seid; 8079d26e4fcSRobert Mustacchi u8 connection_type; 8089d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 8099d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 8109d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 8119d26e4fcSRobert Mustacchi u8 reserved1; 8129d26e4fcSRobert Mustacchi u8 vf_id; 8139d26e4fcSRobert Mustacchi u8 reserved2; 8149d26e4fcSRobert Mustacchi __le16 vsi_flags; 8159d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_SHIFT 0x0 8169d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 8179d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VF 0x0 8189d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 8199d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_PF 0x2 8209d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 8219d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 8229d26e4fcSRobert Mustacchi __le32 addr_high; 8239d26e4fcSRobert Mustacchi __le32 addr_low; 8249d26e4fcSRobert Mustacchi }; 8259d26e4fcSRobert Mustacchi 8269d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 8279d26e4fcSRobert Mustacchi 8289d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi_completion { 8299d26e4fcSRobert Mustacchi __le16 seid; 8309d26e4fcSRobert Mustacchi __le16 vsi_number; 8319d26e4fcSRobert Mustacchi __le16 vsi_used; 8329d26e4fcSRobert Mustacchi __le16 vsi_free; 8339d26e4fcSRobert Mustacchi __le32 addr_high; 8349d26e4fcSRobert Mustacchi __le32 addr_low; 8359d26e4fcSRobert Mustacchi }; 8369d26e4fcSRobert Mustacchi 8379d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 8389d26e4fcSRobert Mustacchi 8399d26e4fcSRobert Mustacchi struct i40e_aqc_vsi_properties_data { 8409d26e4fcSRobert Mustacchi /* first 96 byte are written by SW */ 8419d26e4fcSRobert Mustacchi __le16 valid_sections; 8429d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 8439d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 8449d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 8459d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 8469d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 8479d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 8489d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 8499d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 8509d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 8519d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 8529d26e4fcSRobert Mustacchi /* switch section */ 8539d26e4fcSRobert Mustacchi __le16 switch_id; /* 12bit id combined with flags below */ 8549d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 8559d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 8569d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 8579d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 8589d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 8599d26e4fcSRobert Mustacchi u8 sw_reserved[2]; 8609d26e4fcSRobert Mustacchi /* security section */ 8619d26e4fcSRobert Mustacchi u8 sec_flags; 8629d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 8639d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 8649d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 8659d26e4fcSRobert Mustacchi u8 sec_reserved; 8669d26e4fcSRobert Mustacchi /* VLAN section */ 8679d26e4fcSRobert Mustacchi __le16 pvid; /* VLANS include priority bits */ 8689d26e4fcSRobert Mustacchi __le16 fcoe_pvid; 8699d26e4fcSRobert Mustacchi u8 port_vlan_flags; 8709d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 8719d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 8729d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_MODE_SHIFT) 8739d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 8749d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 8759d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 8769d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 8779d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 8789d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 8799d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 8809d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 8819d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 8829d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 8839d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 8849d26e4fcSRobert Mustacchi u8 pvlan_reserved[3]; 8859d26e4fcSRobert Mustacchi /* ingress egress up sections */ 8869d26e4fcSRobert Mustacchi __le32 ingress_table; /* bitmap, 3 bits per up */ 8879d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 8889d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 8899d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 8909d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 8919d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 8929d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 8939d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 8949d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 8959d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 8969d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 8979d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 8989d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 8999d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 9009d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 9019d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 9029d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 9039d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 9049d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 9059d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 9069d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 9079d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 9089d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 9099d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 9109d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 9119d26e4fcSRobert Mustacchi __le32 egress_table; /* same defines as for ingress table */ 9129d26e4fcSRobert Mustacchi /* cascaded PV section */ 9139d26e4fcSRobert Mustacchi __le16 cas_pv_tag; 9149d26e4fcSRobert Mustacchi u8 cas_pv_flags; 9159d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 9169d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 9179d26e4fcSRobert Mustacchi I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 9189d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 9199d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 9209d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 9219d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 9229d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 9239d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 9249d26e4fcSRobert Mustacchi u8 cas_pv_reserved; 9259d26e4fcSRobert Mustacchi /* queue mapping section */ 9269d26e4fcSRobert Mustacchi __le16 mapping_flags; 9279d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 9289d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 9299d26e4fcSRobert Mustacchi __le16 queue_mapping[16]; 9309d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 9319d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 9329d26e4fcSRobert Mustacchi __le16 tc_mapping[8]; 9339d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 9349d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 9359d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 9369d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 9379d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 9389d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 9399d26e4fcSRobert Mustacchi /* queueing option section */ 9409d26e4fcSRobert Mustacchi u8 queueing_opt_flags; 9419d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 9429d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 9439d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 9449d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 9459d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 9469d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 9479d26e4fcSRobert Mustacchi u8 queueing_opt_reserved[3]; 9489d26e4fcSRobert Mustacchi /* scheduler section */ 9499d26e4fcSRobert Mustacchi u8 up_enable_bits; 9509d26e4fcSRobert Mustacchi u8 sched_reserved; 9519d26e4fcSRobert Mustacchi /* outer up section */ 952*3d75a287SRobert Mustacchi __le32 outer_up_table; /* same structure and defines as ingress tbl */ 9539d26e4fcSRobert Mustacchi u8 cmd_reserved[8]; 9549d26e4fcSRobert Mustacchi /* last 32 bytes are written by FW */ 9559d26e4fcSRobert Mustacchi __le16 qs_handle[8]; 9569d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 9579d26e4fcSRobert Mustacchi __le16 stat_counter_idx; 9589d26e4fcSRobert Mustacchi __le16 sched_id; 9599d26e4fcSRobert Mustacchi u8 resp_reserved[12]; 9609d26e4fcSRobert Mustacchi }; 9619d26e4fcSRobert Mustacchi 9629d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 9639d26e4fcSRobert Mustacchi 9649d26e4fcSRobert Mustacchi /* Add Port Virtualizer (direct 0x0220) 9659d26e4fcSRobert Mustacchi * also used for update PV (direct 0x0221) but only flags are used 9669d26e4fcSRobert Mustacchi * (IS_CTRL_PORT only works on add PV) 9679d26e4fcSRobert Mustacchi */ 9689d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv { 9699d26e4fcSRobert Mustacchi __le16 command_flags; 9709d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 9719d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 9729d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 9739d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 9749d26e4fcSRobert Mustacchi __le16 uplink_seid; 9759d26e4fcSRobert Mustacchi __le16 connected_seid; 9769d26e4fcSRobert Mustacchi u8 reserved[10]; 9779d26e4fcSRobert Mustacchi }; 9789d26e4fcSRobert Mustacchi 9799d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 9809d26e4fcSRobert Mustacchi 9819d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv_completion { 9829d26e4fcSRobert Mustacchi /* reserved for update; for add also encodes error if rc == ENOSPC */ 9839d26e4fcSRobert Mustacchi __le16 pv_seid; 9849d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 9859d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 9869d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 9879d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 9889d26e4fcSRobert Mustacchi u8 reserved[14]; 9899d26e4fcSRobert Mustacchi }; 9909d26e4fcSRobert Mustacchi 9919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 9929d26e4fcSRobert Mustacchi 9939d26e4fcSRobert Mustacchi /* Get PV Params (direct 0x0222) 9949d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 9959d26e4fcSRobert Mustacchi */ 9969d26e4fcSRobert Mustacchi 9979d26e4fcSRobert Mustacchi struct i40e_aqc_get_pv_params_completion { 9989d26e4fcSRobert Mustacchi __le16 seid; 9999d26e4fcSRobert Mustacchi __le16 default_stag; 10009d26e4fcSRobert Mustacchi __le16 pv_flags; /* same flags as add_pv */ 10019d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_PV_TYPE 0x1 10029d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 10039d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 10049d26e4fcSRobert Mustacchi u8 reserved[8]; 10059d26e4fcSRobert Mustacchi __le16 default_port_seid; 10069d26e4fcSRobert Mustacchi }; 10079d26e4fcSRobert Mustacchi 10089d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 10099d26e4fcSRobert Mustacchi 10109d26e4fcSRobert Mustacchi /* Add VEB (direct 0x0230) */ 10119d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb { 10129d26e4fcSRobert Mustacchi __le16 uplink_seid; 10139d26e4fcSRobert Mustacchi __le16 downlink_seid; 10149d26e4fcSRobert Mustacchi __le16 veb_flags; 10159d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_FLOATING 0x1 10169d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 10179d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 10189d26e4fcSRobert Mustacchi I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 10199d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 10209d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1021*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1022*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 10239d26e4fcSRobert Mustacchi u8 enable_tcs; 10249d26e4fcSRobert Mustacchi u8 reserved[9]; 10259d26e4fcSRobert Mustacchi }; 10269d26e4fcSRobert Mustacchi 10279d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 10289d26e4fcSRobert Mustacchi 10299d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb_completion { 10309d26e4fcSRobert Mustacchi u8 reserved[6]; 10319d26e4fcSRobert Mustacchi __le16 switch_seid; 10329d26e4fcSRobert Mustacchi /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 10339d26e4fcSRobert Mustacchi __le16 veb_seid; 10349d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 10359d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 10369d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 10379d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 10389d26e4fcSRobert Mustacchi __le16 statistic_index; 10399d26e4fcSRobert Mustacchi __le16 vebs_used; 10409d26e4fcSRobert Mustacchi __le16 vebs_free; 10419d26e4fcSRobert Mustacchi }; 10429d26e4fcSRobert Mustacchi 10439d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 10449d26e4fcSRobert Mustacchi 10459d26e4fcSRobert Mustacchi /* Get VEB Parameters (direct 0x0232) 10469d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 10479d26e4fcSRobert Mustacchi */ 10489d26e4fcSRobert Mustacchi struct i40e_aqc_get_veb_parameters_completion { 10499d26e4fcSRobert Mustacchi __le16 seid; 10509d26e4fcSRobert Mustacchi __le16 switch_id; 10519d26e4fcSRobert Mustacchi __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 10529d26e4fcSRobert Mustacchi __le16 statistic_index; 10539d26e4fcSRobert Mustacchi __le16 vebs_used; 10549d26e4fcSRobert Mustacchi __le16 vebs_free; 10559d26e4fcSRobert Mustacchi u8 reserved[4]; 10569d26e4fcSRobert Mustacchi }; 10579d26e4fcSRobert Mustacchi 10589d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 10599d26e4fcSRobert Mustacchi 10609d26e4fcSRobert Mustacchi /* Delete Element (direct 0x0243) 10619d26e4fcSRobert Mustacchi * uses the generic i40e_aqc_switch_seid 10629d26e4fcSRobert Mustacchi */ 10639d26e4fcSRobert Mustacchi 10649d26e4fcSRobert Mustacchi /* Add MAC-VLAN (indirect 0x0250) */ 10659d26e4fcSRobert Mustacchi 10669d26e4fcSRobert Mustacchi /* used for the command for most vlan commands */ 10679d26e4fcSRobert Mustacchi struct i40e_aqc_macvlan { 10689d26e4fcSRobert Mustacchi __le16 num_addresses; 10699d26e4fcSRobert Mustacchi __le16 seid[3]; 10709d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 10719d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 10729d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 10739d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 10749d26e4fcSRobert Mustacchi __le32 addr_high; 10759d26e4fcSRobert Mustacchi __le32 addr_low; 10769d26e4fcSRobert Mustacchi }; 10779d26e4fcSRobert Mustacchi 10789d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 10799d26e4fcSRobert Mustacchi 10809d26e4fcSRobert Mustacchi /* indirect data for command and response */ 10819d26e4fcSRobert Mustacchi struct i40e_aqc_add_macvlan_element_data { 10829d26e4fcSRobert Mustacchi u8 mac_addr[6]; 10839d26e4fcSRobert Mustacchi __le16 vlan_tag; 10849d26e4fcSRobert Mustacchi __le16 flags; 10859d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 10869d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 10879d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 10889d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1089*3d75a287SRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 10909d26e4fcSRobert Mustacchi __le16 queue_number; 10919d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 10929d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 10939d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 10949d26e4fcSRobert Mustacchi /* response section */ 10959d26e4fcSRobert Mustacchi u8 match_method; 10969d26e4fcSRobert Mustacchi #define I40E_AQC_MM_PERFECT_MATCH 0x01 10979d26e4fcSRobert Mustacchi #define I40E_AQC_MM_HASH_MATCH 0x02 10989d26e4fcSRobert Mustacchi #define I40E_AQC_MM_ERR_NO_RES 0xFF 10999d26e4fcSRobert Mustacchi u8 reserved1[3]; 11009d26e4fcSRobert Mustacchi }; 11019d26e4fcSRobert Mustacchi 11029d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_macvlan_completion { 11039d26e4fcSRobert Mustacchi __le16 perfect_mac_used; 11049d26e4fcSRobert Mustacchi __le16 perfect_mac_free; 11059d26e4fcSRobert Mustacchi __le16 unicast_hash_free; 11069d26e4fcSRobert Mustacchi __le16 multicast_hash_free; 11079d26e4fcSRobert Mustacchi __le32 addr_high; 11089d26e4fcSRobert Mustacchi __le32 addr_low; 11099d26e4fcSRobert Mustacchi }; 11109d26e4fcSRobert Mustacchi 11119d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 11129d26e4fcSRobert Mustacchi 11139d26e4fcSRobert Mustacchi /* Remove MAC-VLAN (indirect 0x0251) 11149d26e4fcSRobert Mustacchi * uses i40e_aqc_macvlan for the descriptor 11159d26e4fcSRobert Mustacchi * data points to an array of num_addresses of elements 11169d26e4fcSRobert Mustacchi */ 11179d26e4fcSRobert Mustacchi 11189d26e4fcSRobert Mustacchi struct i40e_aqc_remove_macvlan_element_data { 11199d26e4fcSRobert Mustacchi u8 mac_addr[6]; 11209d26e4fcSRobert Mustacchi __le16 vlan_tag; 11219d26e4fcSRobert Mustacchi u8 flags; 11229d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 11239d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 11249d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 11259d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 11269d26e4fcSRobert Mustacchi u8 reserved[3]; 11279d26e4fcSRobert Mustacchi /* reply section */ 11289d26e4fcSRobert Mustacchi u8 error_code; 11299d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 11309d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 11319d26e4fcSRobert Mustacchi u8 reply_reserved[3]; 11329d26e4fcSRobert Mustacchi }; 11339d26e4fcSRobert Mustacchi 11349d26e4fcSRobert Mustacchi /* Add VLAN (indirect 0x0252) 11359d26e4fcSRobert Mustacchi * Remove VLAN (indirect 0x0253) 11369d26e4fcSRobert Mustacchi * use the generic i40e_aqc_macvlan for the command 11379d26e4fcSRobert Mustacchi */ 11389d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_element_data { 11399d26e4fcSRobert Mustacchi __le16 vlan_tag; 11409d26e4fcSRobert Mustacchi u8 vlan_flags; 11419d26e4fcSRobert Mustacchi /* flags for add VLAN */ 11429d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_LOCAL 0x1 11439d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 11449d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 11459d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 11469d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 11479d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 11489d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_SHIFT 3 11499d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 11509d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 11519d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 11529d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 11539d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 11549d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 11559d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_ALL 0x1 11569d26e4fcSRobert Mustacchi u8 reserved; 11579d26e4fcSRobert Mustacchi u8 result; 11589d26e4fcSRobert Mustacchi /* flags for add VLAN */ 11599d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 11609d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 11619d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 11629d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 11639d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 11649d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 11659d26e4fcSRobert Mustacchi u8 reserved1[3]; 11669d26e4fcSRobert Mustacchi }; 11679d26e4fcSRobert Mustacchi 11689d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_completion { 11699d26e4fcSRobert Mustacchi u8 reserved[4]; 11709d26e4fcSRobert Mustacchi __le16 vlans_used; 11719d26e4fcSRobert Mustacchi __le16 vlans_free; 11729d26e4fcSRobert Mustacchi __le32 addr_high; 11739d26e4fcSRobert Mustacchi __le32 addr_low; 11749d26e4fcSRobert Mustacchi }; 11759d26e4fcSRobert Mustacchi 11769d26e4fcSRobert Mustacchi /* Set VSI Promiscuous Modes (direct 0x0254) */ 11779d26e4fcSRobert Mustacchi struct i40e_aqc_set_vsi_promiscuous_modes { 11789d26e4fcSRobert Mustacchi __le16 promiscuous_flags; 11799d26e4fcSRobert Mustacchi __le16 valid_flags; 11809d26e4fcSRobert Mustacchi /* flags used for both fields above */ 11819d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 11829d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 11839d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 11849d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_DEFAULT 0x08 11859d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1186*3d75a287SRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 11879d26e4fcSRobert Mustacchi __le16 seid; 11889d26e4fcSRobert Mustacchi #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 11899d26e4fcSRobert Mustacchi __le16 vlan_tag; 11909d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 11919d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 11929d26e4fcSRobert Mustacchi u8 reserved[8]; 11939d26e4fcSRobert Mustacchi }; 11949d26e4fcSRobert Mustacchi 11959d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 11969d26e4fcSRobert Mustacchi 11979d26e4fcSRobert Mustacchi /* Add S/E-tag command (direct 0x0255) 11989d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 11999d26e4fcSRobert Mustacchi */ 12009d26e4fcSRobert Mustacchi struct i40e_aqc_add_tag { 12019d26e4fcSRobert Mustacchi __le16 flags; 12029d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 12039d26e4fcSRobert Mustacchi __le16 seid; 12049d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 12059d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 12069d26e4fcSRobert Mustacchi I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 12079d26e4fcSRobert Mustacchi __le16 tag; 12089d26e4fcSRobert Mustacchi __le16 queue_number; 12099d26e4fcSRobert Mustacchi u8 reserved[8]; 12109d26e4fcSRobert Mustacchi }; 12119d26e4fcSRobert Mustacchi 12129d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 12139d26e4fcSRobert Mustacchi 12149d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_tag_completion { 12159d26e4fcSRobert Mustacchi u8 reserved[12]; 12169d26e4fcSRobert Mustacchi __le16 tags_used; 12179d26e4fcSRobert Mustacchi __le16 tags_free; 12189d26e4fcSRobert Mustacchi }; 12199d26e4fcSRobert Mustacchi 12209d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 12219d26e4fcSRobert Mustacchi 12229d26e4fcSRobert Mustacchi /* Remove S/E-tag command (direct 0x0256) 12239d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 12249d26e4fcSRobert Mustacchi */ 12259d26e4fcSRobert Mustacchi struct i40e_aqc_remove_tag { 12269d26e4fcSRobert Mustacchi __le16 seid; 12279d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 12289d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 12299d26e4fcSRobert Mustacchi I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 12309d26e4fcSRobert Mustacchi __le16 tag; 12319d26e4fcSRobert Mustacchi u8 reserved[12]; 12329d26e4fcSRobert Mustacchi }; 12339d26e4fcSRobert Mustacchi 12349d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 12359d26e4fcSRobert Mustacchi 12369d26e4fcSRobert Mustacchi /* Add multicast E-Tag (direct 0x0257) 12379d26e4fcSRobert Mustacchi * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 12389d26e4fcSRobert Mustacchi * and no external data 12399d26e4fcSRobert Mustacchi */ 12409d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag { 12419d26e4fcSRobert Mustacchi __le16 pv_seid; 12429d26e4fcSRobert Mustacchi __le16 etag; 12439d26e4fcSRobert Mustacchi u8 num_unicast_etags; 12449d26e4fcSRobert Mustacchi u8 reserved[3]; 12459d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte s-tags */ 12469d26e4fcSRobert Mustacchi __le32 addr_low; 12479d26e4fcSRobert Mustacchi }; 12489d26e4fcSRobert Mustacchi 12499d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 12509d26e4fcSRobert Mustacchi 12519d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag_completion { 12529d26e4fcSRobert Mustacchi u8 reserved[4]; 12539d26e4fcSRobert Mustacchi __le16 mcast_etags_used; 12549d26e4fcSRobert Mustacchi __le16 mcast_etags_free; 12559d26e4fcSRobert Mustacchi __le32 addr_high; 12569d26e4fcSRobert Mustacchi __le32 addr_low; 12579d26e4fcSRobert Mustacchi 12589d26e4fcSRobert Mustacchi }; 12599d26e4fcSRobert Mustacchi 12609d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 12619d26e4fcSRobert Mustacchi 12629d26e4fcSRobert Mustacchi /* Update S/E-Tag (direct 0x0259) */ 12639d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag { 12649d26e4fcSRobert Mustacchi __le16 seid; 12659d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 12669d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 12679d26e4fcSRobert Mustacchi I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 12689d26e4fcSRobert Mustacchi __le16 old_tag; 12699d26e4fcSRobert Mustacchi __le16 new_tag; 12709d26e4fcSRobert Mustacchi u8 reserved[10]; 12719d26e4fcSRobert Mustacchi }; 12729d26e4fcSRobert Mustacchi 12739d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 12749d26e4fcSRobert Mustacchi 12759d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag_completion { 12769d26e4fcSRobert Mustacchi u8 reserved[12]; 12779d26e4fcSRobert Mustacchi __le16 tags_used; 12789d26e4fcSRobert Mustacchi __le16 tags_free; 12799d26e4fcSRobert Mustacchi }; 12809d26e4fcSRobert Mustacchi 12819d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 12829d26e4fcSRobert Mustacchi 12839d26e4fcSRobert Mustacchi /* Add Control Packet filter (direct 0x025A) 12849d26e4fcSRobert Mustacchi * Remove Control Packet filter (direct 0x025B) 12859d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_oveb_cloud, 12869d26e4fcSRobert Mustacchi * and the generic direct completion structure 12879d26e4fcSRobert Mustacchi */ 12889d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter { 12899d26e4fcSRobert Mustacchi u8 mac[6]; 12909d26e4fcSRobert Mustacchi __le16 etype; 12919d26e4fcSRobert Mustacchi __le16 flags; 12929d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 12939d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 12949d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 12959d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 12969d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 12979d26e4fcSRobert Mustacchi __le16 seid; 12989d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 12999d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 13009d26e4fcSRobert Mustacchi I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 13019d26e4fcSRobert Mustacchi __le16 queue; 13029d26e4fcSRobert Mustacchi u8 reserved[2]; 13039d26e4fcSRobert Mustacchi }; 13049d26e4fcSRobert Mustacchi 13059d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 13069d26e4fcSRobert Mustacchi 13079d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter_completion { 13089d26e4fcSRobert Mustacchi __le16 mac_etype_used; 13099d26e4fcSRobert Mustacchi __le16 etype_used; 13109d26e4fcSRobert Mustacchi __le16 mac_etype_free; 13119d26e4fcSRobert Mustacchi __le16 etype_free; 13129d26e4fcSRobert Mustacchi u8 reserved[8]; 13139d26e4fcSRobert Mustacchi }; 13149d26e4fcSRobert Mustacchi 13159d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 13169d26e4fcSRobert Mustacchi 13179d26e4fcSRobert Mustacchi /* Add Cloud filters (indirect 0x025C) 13189d26e4fcSRobert Mustacchi * Remove Cloud filters (indirect 0x025D) 13199d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_remove_cloud_filters, 13209d26e4fcSRobert Mustacchi * and the generic indirect completion structure 13219d26e4fcSRobert Mustacchi */ 13229d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters { 13239d26e4fcSRobert Mustacchi u8 num_filters; 13249d26e4fcSRobert Mustacchi u8 reserved; 13259d26e4fcSRobert Mustacchi __le16 seid; 13269d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 13279d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 13289d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 13299d26e4fcSRobert Mustacchi u8 reserved2[4]; 13309d26e4fcSRobert Mustacchi __le32 addr_high; 13319d26e4fcSRobert Mustacchi __le32 addr_low; 13329d26e4fcSRobert Mustacchi }; 13339d26e4fcSRobert Mustacchi 13349d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 13359d26e4fcSRobert Mustacchi 13369d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters_element_data { 13379d26e4fcSRobert Mustacchi u8 outer_mac[6]; 13389d26e4fcSRobert Mustacchi u8 inner_mac[6]; 13399d26e4fcSRobert Mustacchi __le16 inner_vlan; 13409d26e4fcSRobert Mustacchi union { 13419d26e4fcSRobert Mustacchi struct { 13429d26e4fcSRobert Mustacchi u8 reserved[12]; 13439d26e4fcSRobert Mustacchi u8 data[4]; 13449d26e4fcSRobert Mustacchi } v4; 13459d26e4fcSRobert Mustacchi struct { 13469d26e4fcSRobert Mustacchi u8 data[16]; 13479d26e4fcSRobert Mustacchi } v6; 13489d26e4fcSRobert Mustacchi } ipaddr; 13499d26e4fcSRobert Mustacchi __le16 flags; 13509d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 13519d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 13529d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 13539d26e4fcSRobert Mustacchi /* 0x0000 reserved */ 13549d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 13559d26e4fcSRobert Mustacchi /* 0x0002 reserved */ 13569d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 13579d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 13589d26e4fcSRobert Mustacchi /* 0x0005 reserved */ 13599d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 13609d26e4fcSRobert Mustacchi /* 0x0007 reserved */ 13619d26e4fcSRobert Mustacchi /* 0x0008 reserved */ 13629d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 13639d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 13649d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 13659d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 13669d26e4fcSRobert Mustacchi 13679d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 13689d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 13699d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 13709d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 13719d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 13729d26e4fcSRobert Mustacchi 13739d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 13749d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1375*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 13769d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1377*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 13789d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1379*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1380*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1381*3d75a287SRobert Mustacchi 1382*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1383*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1384*3d75a287SRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 13859d26e4fcSRobert Mustacchi 13869d26e4fcSRobert Mustacchi __le32 tenant_id; 13879d26e4fcSRobert Mustacchi u8 reserved[4]; 13889d26e4fcSRobert Mustacchi __le16 queue_number; 13899d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 13909d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 13919d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 13929d26e4fcSRobert Mustacchi u8 reserved2[14]; 13939d26e4fcSRobert Mustacchi /* response section */ 13949d26e4fcSRobert Mustacchi u8 allocation_result; 13959d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 13969d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 13979d26e4fcSRobert Mustacchi u8 response_reserved[7]; 13989d26e4fcSRobert Mustacchi }; 13999d26e4fcSRobert Mustacchi 14009d26e4fcSRobert Mustacchi struct i40e_aqc_remove_cloud_filters_completion { 14019d26e4fcSRobert Mustacchi __le16 perfect_ovlan_used; 14029d26e4fcSRobert Mustacchi __le16 perfect_ovlan_free; 14039d26e4fcSRobert Mustacchi __le16 vlan_used; 14049d26e4fcSRobert Mustacchi __le16 vlan_free; 14059d26e4fcSRobert Mustacchi __le32 addr_high; 14069d26e4fcSRobert Mustacchi __le32 addr_low; 14079d26e4fcSRobert Mustacchi }; 14089d26e4fcSRobert Mustacchi 14099d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 14109d26e4fcSRobert Mustacchi 14119d26e4fcSRobert Mustacchi /* Add Mirror Rule (indirect or direct 0x0260) 14129d26e4fcSRobert Mustacchi * Delete Mirror Rule (indirect or direct 0x0261) 14139d26e4fcSRobert Mustacchi * note: some rule types (4,5) do not use an external buffer. 14149d26e4fcSRobert Mustacchi * take care to set the flags correctly. 14159d26e4fcSRobert Mustacchi */ 14169d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule { 14179d26e4fcSRobert Mustacchi __le16 seid; 14189d26e4fcSRobert Mustacchi __le16 rule_type; 14199d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 14209d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 14219d26e4fcSRobert Mustacchi I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 14229d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 14239d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 14249d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 14259d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 14269d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 14279d26e4fcSRobert Mustacchi __le16 num_entries; 14289d26e4fcSRobert Mustacchi __le16 destination; /* VSI for add, rule id for delete */ 14299d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 14309d26e4fcSRobert Mustacchi __le32 addr_low; 14319d26e4fcSRobert Mustacchi }; 14329d26e4fcSRobert Mustacchi 14339d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 14349d26e4fcSRobert Mustacchi 14359d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule_completion { 14369d26e4fcSRobert Mustacchi u8 reserved[2]; 14379d26e4fcSRobert Mustacchi __le16 rule_id; /* only used on add */ 14389d26e4fcSRobert Mustacchi __le16 mirror_rules_used; 14399d26e4fcSRobert Mustacchi __le16 mirror_rules_free; 14409d26e4fcSRobert Mustacchi __le32 addr_high; 14419d26e4fcSRobert Mustacchi __le32 addr_low; 14429d26e4fcSRobert Mustacchi }; 14439d26e4fcSRobert Mustacchi 14449d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 14459d26e4fcSRobert Mustacchi 14469d26e4fcSRobert Mustacchi /* DCB 0x03xx*/ 14479d26e4fcSRobert Mustacchi 14489d26e4fcSRobert Mustacchi /* PFC Ignore (direct 0x0301) 14499d26e4fcSRobert Mustacchi * the command and response use the same descriptor structure 14509d26e4fcSRobert Mustacchi */ 14519d26e4fcSRobert Mustacchi struct i40e_aqc_pfc_ignore { 14529d26e4fcSRobert Mustacchi u8 tc_bitmap; 14539d26e4fcSRobert Mustacchi u8 command_flags; /* unused on response */ 14549d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_SET 0x80 14559d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 14569d26e4fcSRobert Mustacchi u8 reserved[14]; 14579d26e4fcSRobert Mustacchi }; 14589d26e4fcSRobert Mustacchi 14599d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 14609d26e4fcSRobert Mustacchi 14619d26e4fcSRobert Mustacchi /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 14629d26e4fcSRobert Mustacchi * with no parameters 14639d26e4fcSRobert Mustacchi */ 14649d26e4fcSRobert Mustacchi 14659d26e4fcSRobert Mustacchi /* TX scheduler 0x04xx */ 14669d26e4fcSRobert Mustacchi 14679d26e4fcSRobert Mustacchi /* Almost all the indirect commands use 14689d26e4fcSRobert Mustacchi * this generic struct to pass the SEID in param0 14699d26e4fcSRobert Mustacchi */ 14709d26e4fcSRobert Mustacchi struct i40e_aqc_tx_sched_ind { 14719d26e4fcSRobert Mustacchi __le16 vsi_seid; 14729d26e4fcSRobert Mustacchi u8 reserved[6]; 14739d26e4fcSRobert Mustacchi __le32 addr_high; 14749d26e4fcSRobert Mustacchi __le32 addr_low; 14759d26e4fcSRobert Mustacchi }; 14769d26e4fcSRobert Mustacchi 14779d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 14789d26e4fcSRobert Mustacchi 14799d26e4fcSRobert Mustacchi /* Several commands respond with a set of queue set handles */ 14809d26e4fcSRobert Mustacchi struct i40e_aqc_qs_handles_resp { 14819d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 14829d26e4fcSRobert Mustacchi }; 14839d26e4fcSRobert Mustacchi 14849d26e4fcSRobert Mustacchi /* Configure VSI BW limits (direct 0x0400) */ 14859d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_bw_limit { 14869d26e4fcSRobert Mustacchi __le16 vsi_seid; 14879d26e4fcSRobert Mustacchi u8 reserved[2]; 14889d26e4fcSRobert Mustacchi __le16 credit; 14899d26e4fcSRobert Mustacchi u8 reserved1[2]; 14909d26e4fcSRobert Mustacchi u8 max_credit; /* 0-3, limit = 2^max */ 14919d26e4fcSRobert Mustacchi u8 reserved2[7]; 14929d26e4fcSRobert Mustacchi }; 14939d26e4fcSRobert Mustacchi 14949d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 14959d26e4fcSRobert Mustacchi 14969d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 14979d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 14989d26e4fcSRobert Mustacchi */ 14999d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_ets_sla_bw_data { 15009d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15019d26e4fcSRobert Mustacchi u8 reserved[15]; 15029d26e4fcSRobert Mustacchi __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 15039d26e4fcSRobert Mustacchi 15049d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 15059d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 15069d26e4fcSRobert Mustacchi u8 reserved1[28]; 15079d26e4fcSRobert Mustacchi }; 15089d26e4fcSRobert Mustacchi 15099d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 15109d26e4fcSRobert Mustacchi 15119d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 15129d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 15139d26e4fcSRobert Mustacchi */ 15149d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_tc_bw_data { 15159d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15169d26e4fcSRobert Mustacchi u8 reserved[3]; 15179d26e4fcSRobert Mustacchi u8 tc_bw_credits[8]; 15189d26e4fcSRobert Mustacchi u8 reserved1[4]; 15199d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 15209d26e4fcSRobert Mustacchi }; 15219d26e4fcSRobert Mustacchi 15229d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 15239d26e4fcSRobert Mustacchi 15249d26e4fcSRobert Mustacchi /* Query vsi bw configuration (indirect 0x0408) */ 15259d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_bw_config_resp { 15269d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15279d26e4fcSRobert Mustacchi u8 tc_suspended_bits; 15289d26e4fcSRobert Mustacchi u8 reserved[14]; 15299d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 15309d26e4fcSRobert Mustacchi u8 reserved1[4]; 15319d26e4fcSRobert Mustacchi __le16 port_bw_limit; 15329d26e4fcSRobert Mustacchi u8 reserved2[2]; 15339d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 15349d26e4fcSRobert Mustacchi u8 reserved3[23]; 15359d26e4fcSRobert Mustacchi }; 15369d26e4fcSRobert Mustacchi 15379d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 15389d26e4fcSRobert Mustacchi 15399d26e4fcSRobert Mustacchi /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 15409d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_ets_sla_config_resp { 15419d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15429d26e4fcSRobert Mustacchi u8 reserved[3]; 15439d26e4fcSRobert Mustacchi u8 share_credits[8]; 15449d26e4fcSRobert Mustacchi __le16 credits[8]; 15459d26e4fcSRobert Mustacchi 15469d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 15479d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 15489d26e4fcSRobert Mustacchi }; 15499d26e4fcSRobert Mustacchi 15509d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 15519d26e4fcSRobert Mustacchi 15529d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 15539d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_limit { 15549d26e4fcSRobert Mustacchi __le16 seid; 15559d26e4fcSRobert Mustacchi u8 reserved[2]; 15569d26e4fcSRobert Mustacchi __le16 credit; 15579d26e4fcSRobert Mustacchi u8 reserved1[2]; 15589d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 15599d26e4fcSRobert Mustacchi u8 reserved2[7]; 15609d26e4fcSRobert Mustacchi }; 15619d26e4fcSRobert Mustacchi 15629d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 15639d26e4fcSRobert Mustacchi 15649d26e4fcSRobert Mustacchi /* Enable Physical Port ETS (indirect 0x0413) 15659d26e4fcSRobert Mustacchi * Modify Physical Port ETS (indirect 0x0414) 15669d26e4fcSRobert Mustacchi * Disable Physical Port ETS (indirect 0x0415) 15679d26e4fcSRobert Mustacchi */ 15689d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_data { 15699d26e4fcSRobert Mustacchi u8 reserved[4]; 15709d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15719d26e4fcSRobert Mustacchi u8 seepage; 15729d26e4fcSRobert Mustacchi #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 15739d26e4fcSRobert Mustacchi u8 tc_strict_priority_flags; 15749d26e4fcSRobert Mustacchi u8 reserved1[17]; 15759d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 15769d26e4fcSRobert Mustacchi u8 reserved2[96]; 15779d26e4fcSRobert Mustacchi }; 15789d26e4fcSRobert Mustacchi 15799d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 15809d26e4fcSRobert Mustacchi 15819d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 15829d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 15839d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15849d26e4fcSRobert Mustacchi u8 reserved[15]; 15859d26e4fcSRobert Mustacchi __le16 tc_bw_credit[8]; 15869d26e4fcSRobert Mustacchi 15879d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 15889d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 15899d26e4fcSRobert Mustacchi u8 reserved1[28]; 15909d26e4fcSRobert Mustacchi }; 15919d26e4fcSRobert Mustacchi 1592*3d75a287SRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, 1593*3d75a287SRobert Mustacchi i40e_aqc_configure_switching_comp_ets_bw_limit_data); 15949d26e4fcSRobert Mustacchi 15959d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Allocation per Tc 15969d26e4fcSRobert Mustacchi * (indirect 0x0417) 15979d26e4fcSRobert Mustacchi */ 15989d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_config_data { 15999d26e4fcSRobert Mustacchi u8 tc_valid_bits; 16009d26e4fcSRobert Mustacchi u8 reserved[2]; 16019d26e4fcSRobert Mustacchi u8 absolute_credits; /* bool */ 16029d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 16039d26e4fcSRobert Mustacchi u8 reserved1[20]; 16049d26e4fcSRobert Mustacchi }; 16059d26e4fcSRobert Mustacchi 16069d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 16079d26e4fcSRobert Mustacchi 16089d26e4fcSRobert Mustacchi /* Query Switching Component Configuration (indirect 0x0418) */ 16099d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_ets_config_resp { 16109d26e4fcSRobert Mustacchi u8 tc_valid_bits; 16119d26e4fcSRobert Mustacchi u8 reserved[35]; 16129d26e4fcSRobert Mustacchi __le16 port_bw_limit; 16139d26e4fcSRobert Mustacchi u8 reserved1[2]; 16149d26e4fcSRobert Mustacchi u8 tc_bw_max; /* 0-3, limit = 2^max */ 16159d26e4fcSRobert Mustacchi u8 reserved2[23]; 16169d26e4fcSRobert Mustacchi }; 16179d26e4fcSRobert Mustacchi 16189d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 16199d26e4fcSRobert Mustacchi 16209d26e4fcSRobert Mustacchi /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 16219d26e4fcSRobert Mustacchi struct i40e_aqc_query_port_ets_config_resp { 16229d26e4fcSRobert Mustacchi u8 reserved[4]; 16239d26e4fcSRobert Mustacchi u8 tc_valid_bits; 16249d26e4fcSRobert Mustacchi u8 reserved1; 16259d26e4fcSRobert Mustacchi u8 tc_strict_priority_bits; 16269d26e4fcSRobert Mustacchi u8 reserved2; 16279d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 16289d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 16299d26e4fcSRobert Mustacchi 16309d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 16319d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 16329d26e4fcSRobert Mustacchi u8 reserved3[32]; 16339d26e4fcSRobert Mustacchi }; 16349d26e4fcSRobert Mustacchi 16359d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 16369d26e4fcSRobert Mustacchi 16379d26e4fcSRobert Mustacchi /* Query Switching Component Bandwidth Allocation per Traffic Type 16389d26e4fcSRobert Mustacchi * (indirect 0x041A) 16399d26e4fcSRobert Mustacchi */ 16409d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_bw_config_resp { 16419d26e4fcSRobert Mustacchi u8 tc_valid_bits; 16429d26e4fcSRobert Mustacchi u8 reserved[2]; 16439d26e4fcSRobert Mustacchi u8 absolute_credits_enable; /* bool */ 16449d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 16459d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 16469d26e4fcSRobert Mustacchi 16479d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 16489d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 16499d26e4fcSRobert Mustacchi }; 16509d26e4fcSRobert Mustacchi 16519d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 16529d26e4fcSRobert Mustacchi 16539d26e4fcSRobert Mustacchi /* Suspend/resume port TX traffic 16549d26e4fcSRobert Mustacchi * (direct 0x041B and 0x041C) uses the generic SEID struct 16559d26e4fcSRobert Mustacchi */ 16569d26e4fcSRobert Mustacchi 16579d26e4fcSRobert Mustacchi /* Configure partition BW 16589d26e4fcSRobert Mustacchi * (indirect 0x041D) 16599d26e4fcSRobert Mustacchi */ 16609d26e4fcSRobert Mustacchi struct i40e_aqc_configure_partition_bw_data { 16619d26e4fcSRobert Mustacchi __le16 pf_valid_bits; 16629d26e4fcSRobert Mustacchi u8 min_bw[16]; /* guaranteed bandwidth */ 16639d26e4fcSRobert Mustacchi u8 max_bw[16]; /* bandwidth limit */ 16649d26e4fcSRobert Mustacchi }; 16659d26e4fcSRobert Mustacchi 16669d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 16679d26e4fcSRobert Mustacchi 16689d26e4fcSRobert Mustacchi /* Get and set the active HMC resource profile and status. 16699d26e4fcSRobert Mustacchi * (direct 0x0500) and (direct 0x0501) 16709d26e4fcSRobert Mustacchi */ 16719d26e4fcSRobert Mustacchi struct i40e_aq_get_set_hmc_resource_profile { 16729d26e4fcSRobert Mustacchi u8 pm_profile; 16739d26e4fcSRobert Mustacchi u8 pe_vf_enabled; 16749d26e4fcSRobert Mustacchi u8 reserved[14]; 16759d26e4fcSRobert Mustacchi }; 16769d26e4fcSRobert Mustacchi 16779d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 16789d26e4fcSRobert Mustacchi 16799d26e4fcSRobert Mustacchi enum i40e_aq_hmc_profile { 1680*3d75a287SRobert Mustacchi /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 16819d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_DEFAULT = 1, 16829d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_FAVOR_VF = 2, 16839d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_EQUAL = 3, 16849d26e4fcSRobert Mustacchi }; 16859d26e4fcSRobert Mustacchi 16869d26e4fcSRobert Mustacchi /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 16879d26e4fcSRobert Mustacchi 16889d26e4fcSRobert Mustacchi /* set in param0 for get phy abilities to report qualified modules */ 16899d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 16909d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 16919d26e4fcSRobert Mustacchi 16929d26e4fcSRobert Mustacchi enum i40e_aq_phy_type { 16939d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SGMII = 0x0, 16949d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_KX = 0x1, 16959d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 16969d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KR = 0x3, 16979d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 16989d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XAUI = 0x5, 16999d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XFI = 0x6, 17009d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SFI = 0x7, 17019d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLAUI = 0x8, 17029d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLPPI = 0x9, 17039d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 17049d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 17059d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_AOC = 0xC, 17069d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_AOC = 0xD, 17079d26e4fcSRobert Mustacchi I40E_PHY_TYPE_100BASE_TX = 0x11, 17089d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T = 0x12, 17099d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_T = 0x13, 17109d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SR = 0x14, 17119d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_LR = 0x15, 17129d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 17139d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 17149d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 17159d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 17169d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 17179d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_SX = 0x1B, 17189d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_LX = 0x1C, 17199d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 17209d26e4fcSRobert Mustacchi I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1721*3d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1722*3d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_CR = 0x20, 1723*3d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_SR = 0x21, 1724*3d75a287SRobert Mustacchi I40E_PHY_TYPE_25GBASE_LR = 0x22, 17259d26e4fcSRobert Mustacchi I40E_PHY_TYPE_MAX 17269d26e4fcSRobert Mustacchi }; 17279d26e4fcSRobert Mustacchi 17289d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_100MB_SHIFT 0x1 17299d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 17309d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_10GB_SHIFT 0x3 17319d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_40GB_SHIFT 0x4 17329d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1733*3d75a287SRobert Mustacchi #define I40E_LINK_SPEED_25GB_SHIFT 0x6 17349d26e4fcSRobert Mustacchi 17359d26e4fcSRobert Mustacchi enum i40e_aq_link_speed { 17369d26e4fcSRobert Mustacchi I40E_LINK_SPEED_UNKNOWN = 0, 17379d26e4fcSRobert Mustacchi I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 17389d26e4fcSRobert Mustacchi I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 17399d26e4fcSRobert Mustacchi I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 17409d26e4fcSRobert Mustacchi I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1741*3d75a287SRobert Mustacchi I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1742*3d75a287SRobert Mustacchi I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 17439d26e4fcSRobert Mustacchi }; 17449d26e4fcSRobert Mustacchi 17459d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc { 17469d26e4fcSRobert Mustacchi u8 oui[3]; 17479d26e4fcSRobert Mustacchi u8 reserved1; 17489d26e4fcSRobert Mustacchi u8 part_number[16]; 17499d26e4fcSRobert Mustacchi u8 revision[4]; 17509d26e4fcSRobert Mustacchi u8 reserved2[8]; 17519d26e4fcSRobert Mustacchi }; 17529d26e4fcSRobert Mustacchi 17539d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 17549d26e4fcSRobert Mustacchi 17559d26e4fcSRobert Mustacchi struct i40e_aq_get_phy_abilities_resp { 17569d26e4fcSRobert Mustacchi __le32 phy_type; /* bitmap using the above enum for offsets */ 17579d26e4fcSRobert Mustacchi u8 link_speed; /* bitmap using the above enum bit patterns */ 17589d26e4fcSRobert Mustacchi u8 abilities; 17599d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 17609d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 17619d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 17629d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLED 0x08 17639d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_AN_ENABLED 0x10 17649d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1765*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1766*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 17679d26e4fcSRobert Mustacchi __le16 eee_capability; 17689d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_100BASE_TX 0x0002 17699d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_T 0x0004 17709d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_T 0x0008 17719d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_KX 0x0010 17729d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KX4 0x0020 17739d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KR 0x0040 17749d26e4fcSRobert Mustacchi __le32 eeer_val; 17759d26e4fcSRobert Mustacchi u8 d3_lpan; 17769d26e4fcSRobert Mustacchi #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1777*3d75a287SRobert Mustacchi u8 phy_type_ext; 1778*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1779*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1780*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1781*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1782*3d75a287SRobert Mustacchi u8 mod_type_ext; 1783*3d75a287SRobert Mustacchi u8 ext_comp_code; 17849d26e4fcSRobert Mustacchi u8 phy_id[4]; 17859d26e4fcSRobert Mustacchi u8 module_type[3]; 17869d26e4fcSRobert Mustacchi u8 qualified_module_count; 17879d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_MAX_QMS 16 17889d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 17899d26e4fcSRobert Mustacchi }; 17909d26e4fcSRobert Mustacchi 17919d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 17929d26e4fcSRobert Mustacchi 17939d26e4fcSRobert Mustacchi /* Set PHY Config (direct 0x0601) */ 17949d26e4fcSRobert Mustacchi struct i40e_aq_set_phy_config { /* same bits as above in all */ 17959d26e4fcSRobert Mustacchi __le32 phy_type; 17969d26e4fcSRobert Mustacchi u8 link_speed; 17979d26e4fcSRobert Mustacchi u8 abilities; 17989d26e4fcSRobert Mustacchi /* bits 0-2 use the values from get_phy_abilities_resp */ 17999d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_LINK 0x08 18009d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_AN 0x10 18019d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 18029d26e4fcSRobert Mustacchi __le16 eee_capability; 18039d26e4fcSRobert Mustacchi __le32 eeer; 18049d26e4fcSRobert Mustacchi u8 low_power_ctrl; 1805*3d75a287SRobert Mustacchi u8 phy_type_ext; 1806*3d75a287SRobert Mustacchi u8 fec_config; 1807*3d75a287SRobert Mustacchi #define I40E_AQ_SET_FEC_ABILITY_KR (1 << 0) 1808*3d75a287SRobert Mustacchi #define I40E_AQ_SET_FEC_ABILITY_RS (1 << 1) 1809*3d75a287SRobert Mustacchi #define I40E_AQ_SET_FEC_REQUEST_KR (1 << 2) 1810*3d75a287SRobert Mustacchi #define I40E_AQ_SET_FEC_REQUEST_RS (1 << 3) 1811*3d75a287SRobert Mustacchi #define I40E_AQ_SET_FEC_AUTO (1 << 4) 1812*3d75a287SRobert Mustacchi u8 reserved; 18139d26e4fcSRobert Mustacchi }; 18149d26e4fcSRobert Mustacchi 18159d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 18169d26e4fcSRobert Mustacchi 18179d26e4fcSRobert Mustacchi /* Set MAC Config command data structure (direct 0x0603) */ 18189d26e4fcSRobert Mustacchi struct i40e_aq_set_mac_config { 18199d26e4fcSRobert Mustacchi __le16 max_frame_size; 18209d26e4fcSRobert Mustacchi u8 params; 18219d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 18229d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 18239d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 18249d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 18259d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 18269d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 18279d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 18289d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 18299d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 18309d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 18319d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 18329d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 18339d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 18349d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 18359d26e4fcSRobert Mustacchi u8 tx_timer_priority; /* bitmap */ 18369d26e4fcSRobert Mustacchi __le16 tx_timer_value; 18379d26e4fcSRobert Mustacchi __le16 fc_refresh_threshold; 18389d26e4fcSRobert Mustacchi u8 reserved[8]; 18399d26e4fcSRobert Mustacchi }; 18409d26e4fcSRobert Mustacchi 18419d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 18429d26e4fcSRobert Mustacchi 18439d26e4fcSRobert Mustacchi /* Restart Auto-Negotiation (direct 0x605) */ 18449d26e4fcSRobert Mustacchi struct i40e_aqc_set_link_restart_an { 18459d26e4fcSRobert Mustacchi u8 command; 18469d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_RESTART_AN 0x02 18479d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLE 0x04 18489d26e4fcSRobert Mustacchi u8 reserved[15]; 18499d26e4fcSRobert Mustacchi }; 18509d26e4fcSRobert Mustacchi 18519d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 18529d26e4fcSRobert Mustacchi 18539d26e4fcSRobert Mustacchi /* Get Link Status cmd & response data structure (direct 0x0607) */ 18549d26e4fcSRobert Mustacchi struct i40e_aqc_get_link_status { 18559d26e4fcSRobert Mustacchi __le16 command_flags; /* only field set on command */ 18569d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_MASK 0x3 18579d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_NOP 0x0 18589d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_DISABLE 0x2 18599d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_ENABLE 0x3 18609d26e4fcSRobert Mustacchi /* only response uses this flag */ 18619d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_IS_ENABLED 0x1 18629d26e4fcSRobert Mustacchi u8 phy_type; /* i40e_aq_phy_type */ 18639d26e4fcSRobert Mustacchi u8 link_speed; /* i40e_aq_link_speed */ 18649d26e4fcSRobert Mustacchi u8 link_info; 18659d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 18669d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_FUNCTION 0x01 18679d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT 0x02 18689d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_TX 0x04 18699d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_RX 0x08 18709d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_REMOTE 0x10 18719d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_PORT 0x20 18729d26e4fcSRobert Mustacchi #define I40E_AQ_MEDIA_AVAILABLE 0x40 18739d26e4fcSRobert Mustacchi #define I40E_AQ_SIGNAL_DETECT 0x80 18749d26e4fcSRobert Mustacchi u8 an_info; 18759d26e4fcSRobert Mustacchi #define I40E_AQ_AN_COMPLETED 0x01 18769d26e4fcSRobert Mustacchi #define I40E_AQ_LP_AN_ABILITY 0x02 18779d26e4fcSRobert Mustacchi #define I40E_AQ_PD_FAULT 0x04 18789d26e4fcSRobert Mustacchi #define I40E_AQ_FEC_EN 0x08 18799d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LOW_POWER 0x10 18809d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_TX 0x20 18819d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_RX 0x40 18829d26e4fcSRobert Mustacchi #define I40E_AQ_QUALIFIED_MODULE 0x80 18839d26e4fcSRobert Mustacchi u8 ext_info; 18849d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 18859d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 18869d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_SHIFT 0x02 18879d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 18889d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_ACTIVE 0x00 18899d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_DRAINED 0x01 18909d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_FLUSHED 0x03 18919d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FORCED_40G 0x10 1892*3d75a287SRobert Mustacchi /* 25G Error Codes */ 1893*3d75a287SRobert Mustacchi #define I40E_AQ_25G_NO_ERR 0X00 1894*3d75a287SRobert Mustacchi #define I40E_AQ_25G_NOT_PRESENT 0X01 1895*3d75a287SRobert Mustacchi #define I40E_AQ_25G_NVM_CRC_ERR 0X02 1896*3d75a287SRobert Mustacchi #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1897*3d75a287SRobert Mustacchi #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1898*3d75a287SRobert Mustacchi #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 18999d26e4fcSRobert Mustacchi u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 19009d26e4fcSRobert Mustacchi __le16 max_frame_size; 19019d26e4fcSRobert Mustacchi u8 config; 1902*3d75a287SRobert Mustacchi #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 1903*3d75a287SRobert Mustacchi #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 19049d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_CRC_ENA 0x04 19059d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_PACING_MASK 0x78 1906*3d75a287SRobert Mustacchi u8 power_desc; 1907*3d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1908*3d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1909*3d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1910*3d75a287SRobert Mustacchi #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1911*3d75a287SRobert Mustacchi #define I40E_AQ_PWR_CLASS_MASK 0x03 1912*3d75a287SRobert Mustacchi u8 reserved[4]; 19139d26e4fcSRobert Mustacchi }; 19149d26e4fcSRobert Mustacchi 19159d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 19169d26e4fcSRobert Mustacchi 19179d26e4fcSRobert Mustacchi /* Set event mask command (direct 0x613) */ 19189d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_int_mask { 19199d26e4fcSRobert Mustacchi u8 reserved[8]; 19209d26e4fcSRobert Mustacchi __le16 event_mask; 19219d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 19229d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MEDIA_NA 0x0004 19239d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_FAULT 0x0008 19249d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 19259d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 19269d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 19279d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 19289d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 19299d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 19309d26e4fcSRobert Mustacchi u8 reserved1[6]; 19319d26e4fcSRobert Mustacchi }; 19329d26e4fcSRobert Mustacchi 19339d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 19349d26e4fcSRobert Mustacchi 19359d26e4fcSRobert Mustacchi /* Get Local AN advt register (direct 0x0614) 19369d26e4fcSRobert Mustacchi * Set Local AN advt register (direct 0x0615) 19379d26e4fcSRobert Mustacchi * Get Link Partner AN advt register (direct 0x0616) 19389d26e4fcSRobert Mustacchi */ 19399d26e4fcSRobert Mustacchi struct i40e_aqc_an_advt_reg { 19409d26e4fcSRobert Mustacchi __le32 local_an_reg0; 19419d26e4fcSRobert Mustacchi __le16 local_an_reg1; 19429d26e4fcSRobert Mustacchi u8 reserved[10]; 19439d26e4fcSRobert Mustacchi }; 19449d26e4fcSRobert Mustacchi 19459d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 19469d26e4fcSRobert Mustacchi 19479d26e4fcSRobert Mustacchi /* Set Loopback mode (0x0618) */ 19489d26e4fcSRobert Mustacchi struct i40e_aqc_set_lb_mode { 19499d26e4fcSRobert Mustacchi __le16 lb_mode; 19509d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_LOCAL 0x01 19519d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_REMOTE 0x02 19529d26e4fcSRobert Mustacchi #define I40E_AQ_LB_MAC_LOCAL 0x04 19539d26e4fcSRobert Mustacchi u8 reserved[14]; 19549d26e4fcSRobert Mustacchi }; 19559d26e4fcSRobert Mustacchi 19569d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 19579d26e4fcSRobert Mustacchi 19589d26e4fcSRobert Mustacchi /* Set PHY Debug command (0x0622) */ 19599d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_debug { 19609d26e4fcSRobert Mustacchi u8 command_flags; 19619d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 19629d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 19639d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 19649d26e4fcSRobert Mustacchi I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 19659d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 19669d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 19679d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1968*3d75a287SRobert Mustacchi /* Disable link manageability on a single port */ 19699d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1970*3d75a287SRobert Mustacchi /* Disable link manageability on all ports needs both bits 4 and 5 */ 1971*3d75a287SRobert Mustacchi #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 19729d26e4fcSRobert Mustacchi u8 reserved[15]; 19739d26e4fcSRobert Mustacchi }; 19749d26e4fcSRobert Mustacchi 19759d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 19769d26e4fcSRobert Mustacchi 19779d26e4fcSRobert Mustacchi enum i40e_aq_phy_reg_type { 19789d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_INTERNAL = 0x1, 19799d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 19809d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 19819d26e4fcSRobert Mustacchi }; 19829d26e4fcSRobert Mustacchi 1983*3d75a287SRobert Mustacchi /* Run PHY Activity (0x0626) */ 1984*3d75a287SRobert Mustacchi struct i40e_aqc_run_phy_activity { 1985*3d75a287SRobert Mustacchi __le16 activity_id; 1986*3d75a287SRobert Mustacchi u8 flags; 1987*3d75a287SRobert Mustacchi u8 reserved1; 1988*3d75a287SRobert Mustacchi __le32 control; 1989*3d75a287SRobert Mustacchi __le32 data; 1990*3d75a287SRobert Mustacchi u8 reserved2[4]; 1991*3d75a287SRobert Mustacchi }; 1992*3d75a287SRobert Mustacchi 1993*3d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1994*3d75a287SRobert Mustacchi 19959d26e4fcSRobert Mustacchi /* NVM Read command (indirect 0x0701) 19969d26e4fcSRobert Mustacchi * NVM Erase commands (direct 0x0702) 19979d26e4fcSRobert Mustacchi * NVM Update commands (indirect 0x0703) 19989d26e4fcSRobert Mustacchi */ 19999d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_update { 20009d26e4fcSRobert Mustacchi u8 command_flags; 20019d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_LAST_CMD 0x01 20029d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_FLASH_ONLY 0x80 20039d26e4fcSRobert Mustacchi u8 module_pointer; 20049d26e4fcSRobert Mustacchi __le16 length; 20059d26e4fcSRobert Mustacchi __le32 offset; 20069d26e4fcSRobert Mustacchi __le32 addr_high; 20079d26e4fcSRobert Mustacchi __le32 addr_low; 20089d26e4fcSRobert Mustacchi }; 20099d26e4fcSRobert Mustacchi 20109d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 20119d26e4fcSRobert Mustacchi 20129d26e4fcSRobert Mustacchi /* NVM Config Read (indirect 0x0704) */ 20139d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_read { 20149d26e4fcSRobert Mustacchi __le16 cmd_flags; 20159d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 20169d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 20179d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 20189d26e4fcSRobert Mustacchi __le16 element_count; 2019*3d75a287SRobert Mustacchi __le16 element_id; /* Feature/field ID */ 20209d26e4fcSRobert Mustacchi __le16 element_id_msw; /* MSWord of field ID */ 20219d26e4fcSRobert Mustacchi __le32 address_high; 20229d26e4fcSRobert Mustacchi __le32 address_low; 20239d26e4fcSRobert Mustacchi }; 20249d26e4fcSRobert Mustacchi 20259d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 20269d26e4fcSRobert Mustacchi 20279d26e4fcSRobert Mustacchi /* NVM Config Write (indirect 0x0705) */ 20289d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_write { 20299d26e4fcSRobert Mustacchi __le16 cmd_flags; 20309d26e4fcSRobert Mustacchi __le16 element_count; 20319d26e4fcSRobert Mustacchi u8 reserved[4]; 20329d26e4fcSRobert Mustacchi __le32 address_high; 20339d26e4fcSRobert Mustacchi __le32 address_low; 20349d26e4fcSRobert Mustacchi }; 20359d26e4fcSRobert Mustacchi 20369d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 20379d26e4fcSRobert Mustacchi 20389d26e4fcSRobert Mustacchi /* Used for 0x0704 as well as for 0x0705 commands */ 20399d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2040*3d75a287SRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2041*3d75a287SRobert Mustacchi (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2042*3d75a287SRobert Mustacchi #define I40E_AQ_ANVM_FEATURE 0 2043*3d75a287SRobert Mustacchi #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 20449d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_feature { 20459d26e4fcSRobert Mustacchi __le16 feature_id; 20469d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 20479d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 20489d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 20499d26e4fcSRobert Mustacchi __le16 feature_options; 20509d26e4fcSRobert Mustacchi __le16 feature_selection; 20519d26e4fcSRobert Mustacchi }; 20529d26e4fcSRobert Mustacchi 20539d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 20549d26e4fcSRobert Mustacchi 20559d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_immediate_field { 20569d26e4fcSRobert Mustacchi __le32 field_id; 20579d26e4fcSRobert Mustacchi __le32 field_value; 20589d26e4fcSRobert Mustacchi __le16 field_options; 20599d26e4fcSRobert Mustacchi __le16 reserved; 20609d26e4fcSRobert Mustacchi }; 20619d26e4fcSRobert Mustacchi 20629d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 20639d26e4fcSRobert Mustacchi 20649d26e4fcSRobert Mustacchi /* OEM Post Update (indirect 0x0720) 20659d26e4fcSRobert Mustacchi * no command data struct used 20669d26e4fcSRobert Mustacchi */ 2067*3d75a287SRobert Mustacchi struct i40e_aqc_nvm_oem_post_update { 20689d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 20699d26e4fcSRobert Mustacchi u8 sel_data; 20709d26e4fcSRobert Mustacchi u8 reserved[7]; 20719d26e4fcSRobert Mustacchi }; 20729d26e4fcSRobert Mustacchi 20739d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 20749d26e4fcSRobert Mustacchi 20759d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_oem_post_update_buffer { 20769d26e4fcSRobert Mustacchi u8 str_len; 20779d26e4fcSRobert Mustacchi u8 dev_addr; 20789d26e4fcSRobert Mustacchi __le16 eeprom_addr; 20799d26e4fcSRobert Mustacchi u8 data[36]; 20809d26e4fcSRobert Mustacchi }; 20819d26e4fcSRobert Mustacchi 20829d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 20839d26e4fcSRobert Mustacchi 2084*3d75a287SRobert Mustacchi /* Thermal Sensor (indirect 0x0721) 2085*3d75a287SRobert Mustacchi * read or set thermal sensor configs and values 2086*3d75a287SRobert Mustacchi * takes a sensor and command specific data buffer, not detailed here 2087*3d75a287SRobert Mustacchi */ 2088*3d75a287SRobert Mustacchi struct i40e_aqc_thermal_sensor { 2089*3d75a287SRobert Mustacchi u8 sensor_action; 2090*3d75a287SRobert Mustacchi #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2091*3d75a287SRobert Mustacchi #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2092*3d75a287SRobert Mustacchi #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2093*3d75a287SRobert Mustacchi u8 reserved[7]; 2094*3d75a287SRobert Mustacchi __le32 addr_high; 2095*3d75a287SRobert Mustacchi __le32 addr_low; 2096*3d75a287SRobert Mustacchi }; 2097*3d75a287SRobert Mustacchi 2098*3d75a287SRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2099*3d75a287SRobert Mustacchi 21009d26e4fcSRobert Mustacchi /* Send to PF command (indirect 0x0801) id is only used by PF 21019d26e4fcSRobert Mustacchi * Send to VF command (indirect 0x0802) id is only used by PF 21029d26e4fcSRobert Mustacchi * Send to Peer PF command (indirect 0x0803) 21039d26e4fcSRobert Mustacchi */ 21049d26e4fcSRobert Mustacchi struct i40e_aqc_pf_vf_message { 21059d26e4fcSRobert Mustacchi __le32 id; 21069d26e4fcSRobert Mustacchi u8 reserved[4]; 21079d26e4fcSRobert Mustacchi __le32 addr_high; 21089d26e4fcSRobert Mustacchi __le32 addr_low; 21099d26e4fcSRobert Mustacchi }; 21109d26e4fcSRobert Mustacchi 21119d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 21129d26e4fcSRobert Mustacchi 21139d26e4fcSRobert Mustacchi /* Alternate structure */ 21149d26e4fcSRobert Mustacchi 21159d26e4fcSRobert Mustacchi /* Direct write (direct 0x0900) 21169d26e4fcSRobert Mustacchi * Direct read (direct 0x0902) 21179d26e4fcSRobert Mustacchi */ 21189d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write { 21199d26e4fcSRobert Mustacchi __le32 address0; 21209d26e4fcSRobert Mustacchi __le32 data0; 21219d26e4fcSRobert Mustacchi __le32 address1; 21229d26e4fcSRobert Mustacchi __le32 data1; 21239d26e4fcSRobert Mustacchi }; 21249d26e4fcSRobert Mustacchi 21259d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 21269d26e4fcSRobert Mustacchi 21279d26e4fcSRobert Mustacchi /* Indirect write (indirect 0x0901) 21289d26e4fcSRobert Mustacchi * Indirect read (indirect 0x0903) 21299d26e4fcSRobert Mustacchi */ 21309d26e4fcSRobert Mustacchi 21319d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_ind_write { 21329d26e4fcSRobert Mustacchi __le32 address; 21339d26e4fcSRobert Mustacchi __le32 length; 21349d26e4fcSRobert Mustacchi __le32 addr_high; 21359d26e4fcSRobert Mustacchi __le32 addr_low; 21369d26e4fcSRobert Mustacchi }; 21379d26e4fcSRobert Mustacchi 21389d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 21399d26e4fcSRobert Mustacchi 21409d26e4fcSRobert Mustacchi /* Done alternate write (direct 0x0904) 21419d26e4fcSRobert Mustacchi * uses i40e_aq_desc 21429d26e4fcSRobert Mustacchi */ 21439d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write_done { 21449d26e4fcSRobert Mustacchi __le16 cmd_flags; 21459d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 21469d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 21479d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 21489d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 21499d26e4fcSRobert Mustacchi u8 reserved[14]; 21509d26e4fcSRobert Mustacchi }; 21519d26e4fcSRobert Mustacchi 21529d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 21539d26e4fcSRobert Mustacchi 21549d26e4fcSRobert Mustacchi /* Set OEM mode (direct 0x0905) */ 21559d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_set_mode { 21569d26e4fcSRobert Mustacchi __le32 mode; 21579d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_NONE 0 21589d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_OEM 1 21599d26e4fcSRobert Mustacchi u8 reserved[12]; 21609d26e4fcSRobert Mustacchi }; 21619d26e4fcSRobert Mustacchi 21629d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 21639d26e4fcSRobert Mustacchi 21649d26e4fcSRobert Mustacchi /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 21659d26e4fcSRobert Mustacchi 21669d26e4fcSRobert Mustacchi /* async events 0x10xx */ 21679d26e4fcSRobert Mustacchi 21689d26e4fcSRobert Mustacchi /* Lan Queue Overflow Event (direct, 0x1001) */ 21699d26e4fcSRobert Mustacchi struct i40e_aqc_lan_overflow { 21709d26e4fcSRobert Mustacchi __le32 prtdcb_rupto; 21719d26e4fcSRobert Mustacchi __le32 otx_ctl; 21729d26e4fcSRobert Mustacchi u8 reserved[8]; 21739d26e4fcSRobert Mustacchi }; 21749d26e4fcSRobert Mustacchi 21759d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 21769d26e4fcSRobert Mustacchi 21779d26e4fcSRobert Mustacchi /* Get LLDP MIB (indirect 0x0A00) */ 21789d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_get_mib { 21799d26e4fcSRobert Mustacchi u8 type; 21809d26e4fcSRobert Mustacchi u8 reserved1; 21819d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 21829d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL 0x0 21839d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_REMOTE 0x1 21849d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 21859d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 21869d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 21879d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 21889d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 21899d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_SHIFT 0x4 21909d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 21919d26e4fcSRobert Mustacchi /* TX pause flags use I40E_AQ_LINK_TX_* above */ 21929d26e4fcSRobert Mustacchi __le16 local_len; 21939d26e4fcSRobert Mustacchi __le16 remote_len; 21949d26e4fcSRobert Mustacchi u8 reserved2[2]; 21959d26e4fcSRobert Mustacchi __le32 addr_high; 21969d26e4fcSRobert Mustacchi __le32 addr_low; 21979d26e4fcSRobert Mustacchi }; 21989d26e4fcSRobert Mustacchi 21999d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 22009d26e4fcSRobert Mustacchi 22019d26e4fcSRobert Mustacchi /* Configure LLDP MIB Change Event (direct 0x0A01) 22029d26e4fcSRobert Mustacchi * also used for the event (with type in the command field) 22039d26e4fcSRobert Mustacchi */ 22049d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_mib { 22059d26e4fcSRobert Mustacchi u8 command; 22069d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 22079d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 22089d26e4fcSRobert Mustacchi u8 reserved[7]; 22099d26e4fcSRobert Mustacchi __le32 addr_high; 22109d26e4fcSRobert Mustacchi __le32 addr_low; 22119d26e4fcSRobert Mustacchi }; 22129d26e4fcSRobert Mustacchi 22139d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 22149d26e4fcSRobert Mustacchi 22159d26e4fcSRobert Mustacchi /* Add LLDP TLV (indirect 0x0A02) 22169d26e4fcSRobert Mustacchi * Delete LLDP TLV (indirect 0x0A04) 22179d26e4fcSRobert Mustacchi */ 22189d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_add_tlv { 22199d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 22209d26e4fcSRobert Mustacchi u8 reserved1[1]; 22219d26e4fcSRobert Mustacchi __le16 len; 22229d26e4fcSRobert Mustacchi u8 reserved2[4]; 22239d26e4fcSRobert Mustacchi __le32 addr_high; 22249d26e4fcSRobert Mustacchi __le32 addr_low; 22259d26e4fcSRobert Mustacchi }; 22269d26e4fcSRobert Mustacchi 22279d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 22289d26e4fcSRobert Mustacchi 22299d26e4fcSRobert Mustacchi /* Update LLDP TLV (indirect 0x0A03) */ 22309d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_tlv { 22319d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 22329d26e4fcSRobert Mustacchi u8 reserved; 22339d26e4fcSRobert Mustacchi __le16 old_len; 22349d26e4fcSRobert Mustacchi __le16 new_offset; 22359d26e4fcSRobert Mustacchi __le16 new_len; 22369d26e4fcSRobert Mustacchi __le32 addr_high; 22379d26e4fcSRobert Mustacchi __le32 addr_low; 22389d26e4fcSRobert Mustacchi }; 22399d26e4fcSRobert Mustacchi 22409d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 22419d26e4fcSRobert Mustacchi 22429d26e4fcSRobert Mustacchi /* Stop LLDP (direct 0x0A05) */ 22439d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop { 22449d26e4fcSRobert Mustacchi u8 command; 22459d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_STOP 0x0 22469d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 22479d26e4fcSRobert Mustacchi u8 reserved[15]; 22489d26e4fcSRobert Mustacchi }; 22499d26e4fcSRobert Mustacchi 22509d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 22519d26e4fcSRobert Mustacchi 22529d26e4fcSRobert Mustacchi /* Start LLDP (direct 0x0A06) */ 22539d26e4fcSRobert Mustacchi 22549d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_start { 22559d26e4fcSRobert Mustacchi u8 command; 22569d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_START 0x1 22579d26e4fcSRobert Mustacchi u8 reserved[15]; 22589d26e4fcSRobert Mustacchi }; 22599d26e4fcSRobert Mustacchi 22609d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 22619d26e4fcSRobert Mustacchi 22629d26e4fcSRobert Mustacchi /* Get CEE DCBX Oper Config (0x0A07) 22639d26e4fcSRobert Mustacchi * uses the generic descriptor struct 22649d26e4fcSRobert Mustacchi * returns below as indirect response 22659d26e4fcSRobert Mustacchi */ 22669d26e4fcSRobert Mustacchi 22679d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 22689d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 22699d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 22709d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 22719d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 22729d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 22739d26e4fcSRobert Mustacchi 22749d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 22759d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 22769d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 22779d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 22789d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 22799d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 22809d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 22819d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 22829d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 22839d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 22849d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 22859d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 22869d26e4fcSRobert Mustacchi 22879d26e4fcSRobert Mustacchi /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 22889d26e4fcSRobert Mustacchi * word boundary layout issues, which the Linux compilers silently deal 22899d26e4fcSRobert Mustacchi * with by adding padding, making the actual struct larger than designed. 22909d26e4fcSRobert Mustacchi * However, the FW compiler for the NIC is less lenient and complains 22919d26e4fcSRobert Mustacchi * about the struct. Hence, the struct defined here has an extra byte in 22929d26e4fcSRobert Mustacchi * fields reserved3 and reserved4 to directly acknowledge that padding, 22939d26e4fcSRobert Mustacchi * and the new length is used in the length check macro. 22949d26e4fcSRobert Mustacchi */ 22959d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 22969d26e4fcSRobert Mustacchi u8 reserved1; 22979d26e4fcSRobert Mustacchi u8 oper_num_tc; 22989d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 22999d26e4fcSRobert Mustacchi u8 reserved2; 23009d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 23019d26e4fcSRobert Mustacchi u8 oper_pfc_en; 23029d26e4fcSRobert Mustacchi u8 reserved3[2]; 23039d26e4fcSRobert Mustacchi __le16 oper_app_prio; 23049d26e4fcSRobert Mustacchi u8 reserved4[2]; 23059d26e4fcSRobert Mustacchi __le16 tlv_status; 23069d26e4fcSRobert Mustacchi }; 23079d26e4fcSRobert Mustacchi 23089d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 23099d26e4fcSRobert Mustacchi 23109d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_resp { 23119d26e4fcSRobert Mustacchi u8 oper_num_tc; 23129d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 23139d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 23149d26e4fcSRobert Mustacchi u8 oper_pfc_en; 23159d26e4fcSRobert Mustacchi __le16 oper_app_prio; 23169d26e4fcSRobert Mustacchi __le32 tlv_status; 23179d26e4fcSRobert Mustacchi u8 reserved[12]; 23189d26e4fcSRobert Mustacchi }; 23199d26e4fcSRobert Mustacchi 23209d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 23219d26e4fcSRobert Mustacchi 23229d26e4fcSRobert Mustacchi /* Set Local LLDP MIB (indirect 0x0A08) 23239d26e4fcSRobert Mustacchi * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 23249d26e4fcSRobert Mustacchi */ 23259d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_set_local_mib { 23269d26e4fcSRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2327*3d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2328*3d75a287SRobert Mustacchi SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2329*3d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2330*3d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2331*3d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2332*3d75a287SRobert Mustacchi SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2333*3d75a287SRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 23349d26e4fcSRobert Mustacchi u8 type; 23359d26e4fcSRobert Mustacchi u8 reserved0; 23369d26e4fcSRobert Mustacchi __le16 length; 23379d26e4fcSRobert Mustacchi u8 reserved1[4]; 23389d26e4fcSRobert Mustacchi __le32 address_high; 23399d26e4fcSRobert Mustacchi __le32 address_low; 23409d26e4fcSRobert Mustacchi }; 23419d26e4fcSRobert Mustacchi 23429d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 23439d26e4fcSRobert Mustacchi 2344*3d75a287SRobert Mustacchi struct i40e_aqc_lldp_set_local_mib_resp { 2345*3d75a287SRobert Mustacchi #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2346*3d75a287SRobert Mustacchi u8 status; 2347*3d75a287SRobert Mustacchi u8 reserved[15]; 2348*3d75a287SRobert Mustacchi }; 2349*3d75a287SRobert Mustacchi 2350*3d75a287SRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2351*3d75a287SRobert Mustacchi 23529d26e4fcSRobert Mustacchi /* Stop/Start LLDP Agent (direct 0x0A09) 23539d26e4fcSRobert Mustacchi * Used for stopping/starting specific LLDP agent. e.g. DCBx 23549d26e4fcSRobert Mustacchi */ 23559d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop_start_specific_agent { 23569d26e4fcSRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2357*3d75a287SRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2358*3d75a287SRobert Mustacchi (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 23599d26e4fcSRobert Mustacchi u8 command; 23609d26e4fcSRobert Mustacchi u8 reserved[15]; 23619d26e4fcSRobert Mustacchi }; 23629d26e4fcSRobert Mustacchi 23639d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 23649d26e4fcSRobert Mustacchi 23659d26e4fcSRobert Mustacchi /* Add Udp Tunnel command and completion (direct 0x0B00) */ 23669d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel { 23679d26e4fcSRobert Mustacchi __le16 udp_port; 23689d26e4fcSRobert Mustacchi u8 reserved0[3]; 23699d26e4fcSRobert Mustacchi u8 protocol_type; 23709d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 23719d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 23729d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2373*3d75a287SRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 23749d26e4fcSRobert Mustacchi u8 reserved1[10]; 23759d26e4fcSRobert Mustacchi }; 23769d26e4fcSRobert Mustacchi 23779d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 23789d26e4fcSRobert Mustacchi 23799d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel_completion { 2380*3d75a287SRobert Mustacchi __le16 udp_port; 23819d26e4fcSRobert Mustacchi u8 filter_entry_index; 23829d26e4fcSRobert Mustacchi u8 multiple_pfs; 23839d26e4fcSRobert Mustacchi #define I40E_AQC_SINGLE_PF 0x0 23849d26e4fcSRobert Mustacchi #define I40E_AQC_MULTIPLE_PFS 0x1 23859d26e4fcSRobert Mustacchi u8 total_filters; 23869d26e4fcSRobert Mustacchi u8 reserved[11]; 23879d26e4fcSRobert Mustacchi }; 23889d26e4fcSRobert Mustacchi 23899d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 23909d26e4fcSRobert Mustacchi 23919d26e4fcSRobert Mustacchi /* remove UDP Tunnel command (0x0B01) */ 23929d26e4fcSRobert Mustacchi struct i40e_aqc_remove_udp_tunnel { 23939d26e4fcSRobert Mustacchi u8 reserved[2]; 23949d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 23959d26e4fcSRobert Mustacchi u8 reserved2[13]; 23969d26e4fcSRobert Mustacchi }; 23979d26e4fcSRobert Mustacchi 23989d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 23999d26e4fcSRobert Mustacchi 24009d26e4fcSRobert Mustacchi struct i40e_aqc_del_udp_tunnel_completion { 24019d26e4fcSRobert Mustacchi __le16 udp_port; 24029d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 24039d26e4fcSRobert Mustacchi u8 multiple_pfs; 24049d26e4fcSRobert Mustacchi u8 total_filters_used; 24059d26e4fcSRobert Mustacchi u8 reserved1[11]; 24069d26e4fcSRobert Mustacchi }; 24079d26e4fcSRobert Mustacchi 24089d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 24099d26e4fcSRobert Mustacchi 24109d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key { 24119d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 24129d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 24139d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 24149d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 24159d26e4fcSRobert Mustacchi __le16 vsi_id; 24169d26e4fcSRobert Mustacchi u8 reserved[6]; 24179d26e4fcSRobert Mustacchi __le32 addr_high; 24189d26e4fcSRobert Mustacchi __le32 addr_low; 24199d26e4fcSRobert Mustacchi }; 24209d26e4fcSRobert Mustacchi 24219d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 24229d26e4fcSRobert Mustacchi 24239d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key_data { 24249d26e4fcSRobert Mustacchi u8 standard_rss_key[0x28]; 24259d26e4fcSRobert Mustacchi u8 extended_hash_key[0xc]; 24269d26e4fcSRobert Mustacchi }; 24279d26e4fcSRobert Mustacchi 24289d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 24299d26e4fcSRobert Mustacchi 24309d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_lut { 24319d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 24329d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 24339d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 24349d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 24359d26e4fcSRobert Mustacchi __le16 vsi_id; 24369d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 24379d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 24389d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 24399d26e4fcSRobert Mustacchi 24409d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 24419d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 24429d26e4fcSRobert Mustacchi __le16 flags; 24439d26e4fcSRobert Mustacchi u8 reserved[4]; 24449d26e4fcSRobert Mustacchi __le32 addr_high; 24459d26e4fcSRobert Mustacchi __le32 addr_low; 24469d26e4fcSRobert Mustacchi }; 24479d26e4fcSRobert Mustacchi 24489d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 24499d26e4fcSRobert Mustacchi 24509d26e4fcSRobert Mustacchi /* tunnel key structure 0x0B10 */ 24519d26e4fcSRobert Mustacchi 24529d26e4fcSRobert Mustacchi struct i40e_aqc_tunnel_key_structure { 24539d26e4fcSRobert Mustacchi u8 key1_off; 24549d26e4fcSRobert Mustacchi u8 key2_off; 24559d26e4fcSRobert Mustacchi u8 key1_len; /* 0 to 15 */ 24569d26e4fcSRobert Mustacchi u8 key2_len; /* 0 to 15 */ 24579d26e4fcSRobert Mustacchi u8 flags; 24589d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 24599d26e4fcSRobert Mustacchi /* response flags */ 24609d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 24619d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 24629d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 24639d26e4fcSRobert Mustacchi u8 network_key_index; 24649d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 24659d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 24669d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 24679d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 24689d26e4fcSRobert Mustacchi u8 reserved[10]; 24699d26e4fcSRobert Mustacchi }; 24709d26e4fcSRobert Mustacchi 24719d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 24729d26e4fcSRobert Mustacchi 24739d26e4fcSRobert Mustacchi /* OEM mode commands (direct 0xFE0x) */ 24749d26e4fcSRobert Mustacchi struct i40e_aqc_oem_param_change { 24759d26e4fcSRobert Mustacchi __le32 param_type; 24769d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 24779d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 24789d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_MAC 2 24799d26e4fcSRobert Mustacchi __le32 param_value1; 24809d26e4fcSRobert Mustacchi __le16 param_value2; 24819d26e4fcSRobert Mustacchi u8 reserved[6]; 24829d26e4fcSRobert Mustacchi }; 24839d26e4fcSRobert Mustacchi 24849d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 24859d26e4fcSRobert Mustacchi 24869d26e4fcSRobert Mustacchi struct i40e_aqc_oem_state_change { 24879d26e4fcSRobert Mustacchi __le32 state; 24889d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 24899d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_UP 0x1 24909d26e4fcSRobert Mustacchi u8 reserved[12]; 24919d26e4fcSRobert Mustacchi }; 24929d26e4fcSRobert Mustacchi 24939d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 24949d26e4fcSRobert Mustacchi 24959d26e4fcSRobert Mustacchi /* Initialize OCSD (0xFE02, direct) */ 24969d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocsd_initialize { 24979d26e4fcSRobert Mustacchi u8 type_status; 24989d26e4fcSRobert Mustacchi u8 reserved1[3]; 24999d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_high; 25009d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_low; 25019d26e4fcSRobert Mustacchi __le32 requested_update_interval; 25029d26e4fcSRobert Mustacchi }; 25039d26e4fcSRobert Mustacchi 25049d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 25059d26e4fcSRobert Mustacchi 25069d26e4fcSRobert Mustacchi /* Initialize OCBB (0xFE03, direct) */ 25079d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocbb_initialize { 25089d26e4fcSRobert Mustacchi u8 type_status; 25099d26e4fcSRobert Mustacchi u8 reserved1[3]; 25109d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_high; 25119d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_low; 25129d26e4fcSRobert Mustacchi u8 reserved2[4]; 25139d26e4fcSRobert Mustacchi }; 25149d26e4fcSRobert Mustacchi 25159d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 25169d26e4fcSRobert Mustacchi 25179d26e4fcSRobert Mustacchi /* debug commands */ 25189d26e4fcSRobert Mustacchi 25199d26e4fcSRobert Mustacchi /* get device id (0xFF00) uses the generic structure */ 25209d26e4fcSRobert Mustacchi 25219d26e4fcSRobert Mustacchi /* set test more (0xFF01, internal) */ 25229d26e4fcSRobert Mustacchi 25239d26e4fcSRobert Mustacchi struct i40e_acq_set_test_mode { 25249d26e4fcSRobert Mustacchi u8 mode; 25259d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_PARTIAL 0 25269d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_FULL 1 25279d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_NVM 2 25289d26e4fcSRobert Mustacchi u8 reserved[3]; 25299d26e4fcSRobert Mustacchi u8 command; 25309d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_OPEN 0 25319d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_CLOSE 1 25329d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_INC 2 25339d26e4fcSRobert Mustacchi u8 reserved2[3]; 25349d26e4fcSRobert Mustacchi __le32 address_high; 25359d26e4fcSRobert Mustacchi __le32 address_low; 25369d26e4fcSRobert Mustacchi }; 25379d26e4fcSRobert Mustacchi 25389d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 25399d26e4fcSRobert Mustacchi 25409d26e4fcSRobert Mustacchi /* Debug Read Register command (0xFF03) 25419d26e4fcSRobert Mustacchi * Debug Write Register command (0xFF04) 25429d26e4fcSRobert Mustacchi */ 25439d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_read_write { 25449d26e4fcSRobert Mustacchi __le32 reserved; 25459d26e4fcSRobert Mustacchi __le32 address; 25469d26e4fcSRobert Mustacchi __le32 value_high; 25479d26e4fcSRobert Mustacchi __le32 value_low; 25489d26e4fcSRobert Mustacchi }; 25499d26e4fcSRobert Mustacchi 25509d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 25519d26e4fcSRobert Mustacchi 25529d26e4fcSRobert Mustacchi /* Scatter/gather Reg Read (indirect 0xFF05) 25539d26e4fcSRobert Mustacchi * Scatter/gather Reg Write (indirect 0xFF06) 25549d26e4fcSRobert Mustacchi */ 25559d26e4fcSRobert Mustacchi 25569d26e4fcSRobert Mustacchi /* i40e_aq_desc is used for the command */ 25579d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_sg_element_data { 25589d26e4fcSRobert Mustacchi __le32 address; 25599d26e4fcSRobert Mustacchi __le32 value; 25609d26e4fcSRobert Mustacchi }; 25619d26e4fcSRobert Mustacchi 25629d26e4fcSRobert Mustacchi /* Debug Modify register (direct 0xFF07) */ 25639d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_reg { 25649d26e4fcSRobert Mustacchi __le32 address; 25659d26e4fcSRobert Mustacchi __le32 value; 25669d26e4fcSRobert Mustacchi __le32 clear_mask; 25679d26e4fcSRobert Mustacchi __le32 set_mask; 25689d26e4fcSRobert Mustacchi }; 25699d26e4fcSRobert Mustacchi 25709d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 25719d26e4fcSRobert Mustacchi 25729d26e4fcSRobert Mustacchi /* dump internal data (0xFF08, indirect) */ 25739d26e4fcSRobert Mustacchi 25749d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_AUX 0 25759d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 25769d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_TXSCHED 2 25779d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_HMC 3 25789d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC0 4 25799d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC1 5 25809d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC2 6 25819d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC3 7 25829d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_DCB 8 25839d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 25849d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 25859d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_ALTRAM 11 25869d26e4fcSRobert Mustacchi 25879d26e4fcSRobert Mustacchi struct i40e_aqc_debug_dump_internals { 25889d26e4fcSRobert Mustacchi u8 cluster_id; 25899d26e4fcSRobert Mustacchi u8 table_id; 25909d26e4fcSRobert Mustacchi __le16 data_size; 25919d26e4fcSRobert Mustacchi __le32 idx; 25929d26e4fcSRobert Mustacchi __le32 address_high; 25939d26e4fcSRobert Mustacchi __le32 address_low; 25949d26e4fcSRobert Mustacchi }; 25959d26e4fcSRobert Mustacchi 25969d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 25979d26e4fcSRobert Mustacchi 25989d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_internals { 25999d26e4fcSRobert Mustacchi u8 cluster_id; 26009d26e4fcSRobert Mustacchi u8 cluster_specific_params[7]; 26019d26e4fcSRobert Mustacchi __le32 address_high; 26029d26e4fcSRobert Mustacchi __le32 address_low; 26039d26e4fcSRobert Mustacchi }; 26049d26e4fcSRobert Mustacchi 26059d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 26069d26e4fcSRobert Mustacchi 2607*3d75a287SRobert Mustacchi #endif /* _I40E_ADMINQ_CMD_H_ */ 2608