19d26e4fcSRobert Mustacchi /****************************************************************************** 29d26e4fcSRobert Mustacchi 39d26e4fcSRobert Mustacchi Copyright (c) 2013-2015, Intel Corporation 49d26e4fcSRobert Mustacchi All rights reserved. 59d26e4fcSRobert Mustacchi 69d26e4fcSRobert Mustacchi Redistribution and use in source and binary forms, with or without 79d26e4fcSRobert Mustacchi modification, are permitted provided that the following conditions are met: 89d26e4fcSRobert Mustacchi 99d26e4fcSRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 109d26e4fcSRobert Mustacchi this list of conditions and the following disclaimer. 119d26e4fcSRobert Mustacchi 129d26e4fcSRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 139d26e4fcSRobert Mustacchi notice, this list of conditions and the following disclaimer in the 149d26e4fcSRobert Mustacchi documentation and/or other materials provided with the distribution. 159d26e4fcSRobert Mustacchi 169d26e4fcSRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 179d26e4fcSRobert Mustacchi contributors may be used to endorse or promote products derived from 189d26e4fcSRobert Mustacchi this software without specific prior written permission. 199d26e4fcSRobert Mustacchi 209d26e4fcSRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 219d26e4fcSRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 229d26e4fcSRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 239d26e4fcSRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 249d26e4fcSRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 259d26e4fcSRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 269d26e4fcSRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 279d26e4fcSRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 289d26e4fcSRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 299d26e4fcSRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 309d26e4fcSRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 319d26e4fcSRobert Mustacchi 329d26e4fcSRobert Mustacchi ******************************************************************************/ 339d26e4fcSRobert Mustacchi /*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 284049 2015-06-05 22:52:42Z jfv $*/ 349d26e4fcSRobert Mustacchi 359d26e4fcSRobert Mustacchi #ifndef _I40E_ADMINQ_CMD_H_ 369d26e4fcSRobert Mustacchi #define _I40E_ADMINQ_CMD_H_ 379d26e4fcSRobert Mustacchi 389d26e4fcSRobert Mustacchi /* This header file defines the i40e Admin Queue commands and is shared between 399d26e4fcSRobert Mustacchi * i40e Firmware and Software. 409d26e4fcSRobert Mustacchi * 419d26e4fcSRobert Mustacchi * This file needs to comply with the Linux Kernel coding style. 429d26e4fcSRobert Mustacchi */ 439d26e4fcSRobert Mustacchi 449d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MAJOR 0x0001 459d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 469d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MINOR 0x0003 479d26e4fcSRobert Mustacchi #else 489d26e4fcSRobert Mustacchi #define I40E_FW_API_VERSION_MINOR 0x0004 499d26e4fcSRobert Mustacchi #endif 509d26e4fcSRobert Mustacchi 519d26e4fcSRobert Mustacchi struct i40e_aq_desc { 529d26e4fcSRobert Mustacchi __le16 flags; 539d26e4fcSRobert Mustacchi __le16 opcode; 549d26e4fcSRobert Mustacchi __le16 datalen; 559d26e4fcSRobert Mustacchi __le16 retval; 569d26e4fcSRobert Mustacchi __le32 cookie_high; 579d26e4fcSRobert Mustacchi __le32 cookie_low; 589d26e4fcSRobert Mustacchi union { 599d26e4fcSRobert Mustacchi struct { 609d26e4fcSRobert Mustacchi __le32 param0; 619d26e4fcSRobert Mustacchi __le32 param1; 629d26e4fcSRobert Mustacchi __le32 param2; 639d26e4fcSRobert Mustacchi __le32 param3; 649d26e4fcSRobert Mustacchi } internal; 659d26e4fcSRobert Mustacchi struct { 669d26e4fcSRobert Mustacchi __le32 param0; 679d26e4fcSRobert Mustacchi __le32 param1; 689d26e4fcSRobert Mustacchi __le32 addr_high; 699d26e4fcSRobert Mustacchi __le32 addr_low; 709d26e4fcSRobert Mustacchi } external; 719d26e4fcSRobert Mustacchi u8 raw[16]; 729d26e4fcSRobert Mustacchi } params; 739d26e4fcSRobert Mustacchi }; 749d26e4fcSRobert Mustacchi 759d26e4fcSRobert Mustacchi /* Flags sub-structure 769d26e4fcSRobert Mustacchi * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 779d26e4fcSRobert Mustacchi * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 789d26e4fcSRobert Mustacchi */ 799d26e4fcSRobert Mustacchi 809d26e4fcSRobert Mustacchi /* command flags and offsets*/ 819d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD_SHIFT 0 829d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP_SHIFT 1 839d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR_SHIFT 2 849d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE_SHIFT 3 859d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB_SHIFT 9 869d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD_SHIFT 10 879d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC_SHIFT 11 889d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF_SHIFT 12 899d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI_SHIFT 13 909d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI_SHIFT 14 919d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE_SHIFT 15 929d26e4fcSRobert Mustacchi 939d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 949d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 959d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 969d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 979d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 989d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 999d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 1009d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 1019d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 1029d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 1039d26e4fcSRobert Mustacchi #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 1049d26e4fcSRobert Mustacchi 1059d26e4fcSRobert Mustacchi /* error codes */ 1069d26e4fcSRobert Mustacchi enum i40e_admin_queue_err { 1079d26e4fcSRobert Mustacchi I40E_AQ_RC_OK = 0, /* success */ 1089d26e4fcSRobert Mustacchi I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 1099d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOENT = 2, /* No such element */ 1109d26e4fcSRobert Mustacchi I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 1119d26e4fcSRobert Mustacchi I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 1129d26e4fcSRobert Mustacchi I40E_AQ_RC_EIO = 5, /* I/O error */ 1139d26e4fcSRobert Mustacchi I40E_AQ_RC_ENXIO = 6, /* No such resource */ 1149d26e4fcSRobert Mustacchi I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 1159d26e4fcSRobert Mustacchi I40E_AQ_RC_EAGAIN = 8, /* Try again */ 1169d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 1179d26e4fcSRobert Mustacchi I40E_AQ_RC_EACCES = 10, /* Permission denied */ 1189d26e4fcSRobert Mustacchi I40E_AQ_RC_EFAULT = 11, /* Bad address */ 1199d26e4fcSRobert Mustacchi I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1209d26e4fcSRobert Mustacchi I40E_AQ_RC_EEXIST = 13, /* object already exists */ 1219d26e4fcSRobert Mustacchi I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 1229d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 1239d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 1249d26e4fcSRobert Mustacchi I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1259d26e4fcSRobert Mustacchi I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 1269d26e4fcSRobert Mustacchi I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 1279d26e4fcSRobert Mustacchi I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 1289d26e4fcSRobert Mustacchi I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1299d26e4fcSRobert Mustacchi I40E_AQ_RC_EFBIG = 22, /* File too large */ 1309d26e4fcSRobert Mustacchi }; 1319d26e4fcSRobert Mustacchi 1329d26e4fcSRobert Mustacchi /* Admin Queue command opcodes */ 1339d26e4fcSRobert Mustacchi enum i40e_admin_queue_opc { 1349d26e4fcSRobert Mustacchi /* aq commands */ 1359d26e4fcSRobert Mustacchi i40e_aqc_opc_get_version = 0x0001, 1369d26e4fcSRobert Mustacchi i40e_aqc_opc_driver_version = 0x0002, 1379d26e4fcSRobert Mustacchi i40e_aqc_opc_queue_shutdown = 0x0003, 1389d26e4fcSRobert Mustacchi i40e_aqc_opc_set_pf_context = 0x0004, 1399d26e4fcSRobert Mustacchi 1409d26e4fcSRobert Mustacchi /* resource ownership */ 1419d26e4fcSRobert Mustacchi i40e_aqc_opc_request_resource = 0x0008, 1429d26e4fcSRobert Mustacchi i40e_aqc_opc_release_resource = 0x0009, 1439d26e4fcSRobert Mustacchi 1449d26e4fcSRobert Mustacchi i40e_aqc_opc_list_func_capabilities = 0x000A, 1459d26e4fcSRobert Mustacchi i40e_aqc_opc_list_dev_capabilities = 0x000B, 1469d26e4fcSRobert Mustacchi 1479d26e4fcSRobert Mustacchi /* LAA */ 1489d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_read = 0x0107, 1499d26e4fcSRobert Mustacchi i40e_aqc_opc_mac_address_write = 0x0108, 1509d26e4fcSRobert Mustacchi 1519d26e4fcSRobert Mustacchi /* PXE */ 1529d26e4fcSRobert Mustacchi i40e_aqc_opc_clear_pxe_mode = 0x0110, 1539d26e4fcSRobert Mustacchi 1549d26e4fcSRobert Mustacchi /* internal switch commands */ 1559d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_config = 0x0200, 1569d26e4fcSRobert Mustacchi i40e_aqc_opc_add_statistics = 0x0201, 1579d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_statistics = 0x0202, 1589d26e4fcSRobert Mustacchi i40e_aqc_opc_set_port_parameters = 0x0203, 1599d26e4fcSRobert Mustacchi i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 1609d26e4fcSRobert Mustacchi 161*396505afSPaul Winder i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 162*396505afSPaul Winder i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 163*396505afSPaul Winder 1649d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vsi = 0x0210, 1659d26e4fcSRobert Mustacchi i40e_aqc_opc_update_vsi_parameters = 0x0211, 1669d26e4fcSRobert Mustacchi i40e_aqc_opc_get_vsi_parameters = 0x0212, 1679d26e4fcSRobert Mustacchi 1689d26e4fcSRobert Mustacchi i40e_aqc_opc_add_pv = 0x0220, 1699d26e4fcSRobert Mustacchi i40e_aqc_opc_update_pv_parameters = 0x0221, 1709d26e4fcSRobert Mustacchi i40e_aqc_opc_get_pv_parameters = 0x0222, 1719d26e4fcSRobert Mustacchi 1729d26e4fcSRobert Mustacchi i40e_aqc_opc_add_veb = 0x0230, 1739d26e4fcSRobert Mustacchi i40e_aqc_opc_update_veb_parameters = 0x0231, 1749d26e4fcSRobert Mustacchi i40e_aqc_opc_get_veb_parameters = 0x0232, 1759d26e4fcSRobert Mustacchi 1769d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_element = 0x0243, 1779d26e4fcSRobert Mustacchi 1789d26e4fcSRobert Mustacchi i40e_aqc_opc_add_macvlan = 0x0250, 1799d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_macvlan = 0x0251, 1809d26e4fcSRobert Mustacchi i40e_aqc_opc_add_vlan = 0x0252, 1819d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_vlan = 0x0253, 1829d26e4fcSRobert Mustacchi i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 1839d26e4fcSRobert Mustacchi i40e_aqc_opc_add_tag = 0x0255, 1849d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_tag = 0x0256, 1859d26e4fcSRobert Mustacchi i40e_aqc_opc_add_multicast_etag = 0x0257, 1869d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_multicast_etag = 0x0258, 1879d26e4fcSRobert Mustacchi i40e_aqc_opc_update_tag = 0x0259, 1889d26e4fcSRobert Mustacchi i40e_aqc_opc_add_control_packet_filter = 0x025A, 1899d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_control_packet_filter = 0x025B, 1909d26e4fcSRobert Mustacchi i40e_aqc_opc_add_cloud_filters = 0x025C, 1919d26e4fcSRobert Mustacchi i40e_aqc_opc_remove_cloud_filters = 0x025D, 1929d26e4fcSRobert Mustacchi 1939d26e4fcSRobert Mustacchi i40e_aqc_opc_add_mirror_rule = 0x0260, 1949d26e4fcSRobert Mustacchi i40e_aqc_opc_delete_mirror_rule = 0x0261, 1959d26e4fcSRobert Mustacchi 1969d26e4fcSRobert Mustacchi /* DCB commands */ 1979d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 1989d26e4fcSRobert Mustacchi i40e_aqc_opc_dcb_updated = 0x0302, 1999d26e4fcSRobert Mustacchi 2009d26e4fcSRobert Mustacchi /* TX scheduler */ 2019d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 2029d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 2039d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 2049d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_bw_config = 0x0408, 2059d26e4fcSRobert Mustacchi i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 2069d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 2079d26e4fcSRobert Mustacchi 2089d26e4fcSRobert Mustacchi i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 2099d26e4fcSRobert Mustacchi i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 2109d26e4fcSRobert Mustacchi i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 2119d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 2129d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 2139d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 2149d26e4fcSRobert Mustacchi i40e_aqc_opc_query_port_ets_config = 0x0419, 2159d26e4fcSRobert Mustacchi i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 2169d26e4fcSRobert Mustacchi i40e_aqc_opc_suspend_port_tx = 0x041B, 2179d26e4fcSRobert Mustacchi i40e_aqc_opc_resume_port_tx = 0x041C, 2189d26e4fcSRobert Mustacchi i40e_aqc_opc_configure_partition_bw = 0x041D, 2199d26e4fcSRobert Mustacchi 2209d26e4fcSRobert Mustacchi /* hmc */ 2219d26e4fcSRobert Mustacchi i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 2229d26e4fcSRobert Mustacchi i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 2239d26e4fcSRobert Mustacchi 2249d26e4fcSRobert Mustacchi /* phy commands*/ 2259d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_abilities = 0x0600, 2269d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_config = 0x0601, 2279d26e4fcSRobert Mustacchi i40e_aqc_opc_set_mac_config = 0x0603, 2289d26e4fcSRobert Mustacchi i40e_aqc_opc_set_link_restart_an = 0x0605, 2299d26e4fcSRobert Mustacchi i40e_aqc_opc_get_link_status = 0x0607, 2309d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_int_mask = 0x0613, 2319d26e4fcSRobert Mustacchi i40e_aqc_opc_get_local_advt_reg = 0x0614, 2329d26e4fcSRobert Mustacchi i40e_aqc_opc_set_local_advt_reg = 0x0615, 2339d26e4fcSRobert Mustacchi i40e_aqc_opc_get_partner_advt = 0x0616, 2349d26e4fcSRobert Mustacchi i40e_aqc_opc_set_lb_modes = 0x0618, 2359d26e4fcSRobert Mustacchi i40e_aqc_opc_get_phy_wol_caps = 0x0621, 2369d26e4fcSRobert Mustacchi i40e_aqc_opc_set_phy_debug = 0x0622, 2379d26e4fcSRobert Mustacchi i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 2389d26e4fcSRobert Mustacchi 2399d26e4fcSRobert Mustacchi /* NVM commands */ 2409d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_read = 0x0701, 2419d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_erase = 0x0702, 2429d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_update = 0x0703, 2439d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_read = 0x0704, 2449d26e4fcSRobert Mustacchi i40e_aqc_opc_nvm_config_write = 0x0705, 2459d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_post_update = 0x0720, 2469d26e4fcSRobert Mustacchi 2479d26e4fcSRobert Mustacchi /* virtualization commands */ 2489d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_pf = 0x0801, 2499d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_vf = 0x0802, 2509d26e4fcSRobert Mustacchi i40e_aqc_opc_send_msg_to_peer = 0x0803, 2519d26e4fcSRobert Mustacchi 2529d26e4fcSRobert Mustacchi /* alternate structure */ 2539d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write = 0x0900, 2549d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_indirect = 0x0901, 2559d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read = 0x0902, 2569d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_read_indirect = 0x0903, 2579d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_write_done = 0x0904, 2589d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_set_mode = 0x0905, 2599d26e4fcSRobert Mustacchi i40e_aqc_opc_alternate_clear_port = 0x0906, 2609d26e4fcSRobert Mustacchi 2619d26e4fcSRobert Mustacchi /* LLDP commands */ 2629d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_get_mib = 0x0A00, 2639d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_mib = 0x0A01, 2649d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_add_tlv = 0x0A02, 2659d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_update_tlv = 0x0A03, 2669d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 2679d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop = 0x0A05, 2689d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_start = 0x0A06, 2699d26e4fcSRobert Mustacchi i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2709d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 2719d26e4fcSRobert Mustacchi i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 2729d26e4fcSRobert Mustacchi 2739d26e4fcSRobert Mustacchi /* Tunnel commands */ 2749d26e4fcSRobert Mustacchi i40e_aqc_opc_add_udp_tunnel = 0x0B00, 2759d26e4fcSRobert Mustacchi i40e_aqc_opc_del_udp_tunnel = 0x0B01, 2769d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 2779d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_key = 0x0B02, 2789d26e4fcSRobert Mustacchi i40e_aqc_opc_set_rss_lut = 0x0B03, 2799d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_key = 0x0B04, 2809d26e4fcSRobert Mustacchi i40e_aqc_opc_get_rss_lut = 0x0B05, 2819d26e4fcSRobert Mustacchi #endif 2829d26e4fcSRobert Mustacchi 2839d26e4fcSRobert Mustacchi /* Async Events */ 2849d26e4fcSRobert Mustacchi i40e_aqc_opc_event_lan_overflow = 0x1001, 2859d26e4fcSRobert Mustacchi 2869d26e4fcSRobert Mustacchi /* OEM commands */ 2879d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_parameter_change = 0xFE00, 2889d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_device_status_change = 0xFE01, 2899d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 2909d26e4fcSRobert Mustacchi i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 2919d26e4fcSRobert Mustacchi 2929d26e4fcSRobert Mustacchi /* debug commands */ 2939d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_read_reg = 0xFF03, 2949d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_write_reg = 0xFF04, 2959d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_modify_reg = 0xFF07, 2969d26e4fcSRobert Mustacchi i40e_aqc_opc_debug_dump_internals = 0xFF08, 2979d26e4fcSRobert Mustacchi }; 2989d26e4fcSRobert Mustacchi 2999d26e4fcSRobert Mustacchi /* command structures and indirect data structures */ 3009d26e4fcSRobert Mustacchi 3019d26e4fcSRobert Mustacchi /* Structure naming conventions: 3029d26e4fcSRobert Mustacchi * - no suffix for direct command descriptor structures 3039d26e4fcSRobert Mustacchi * - _data for indirect sent data 3049d26e4fcSRobert Mustacchi * - _resp for indirect return data (data which is both will use _data) 3059d26e4fcSRobert Mustacchi * - _completion for direct return data 3069d26e4fcSRobert Mustacchi * - _element_ for repeated elements (may also be _data or _resp) 3079d26e4fcSRobert Mustacchi * 3089d26e4fcSRobert Mustacchi * Command structures are expected to overlay the params.raw member of the basic 3099d26e4fcSRobert Mustacchi * descriptor, and as such cannot exceed 16 bytes in length. 3109d26e4fcSRobert Mustacchi */ 3119d26e4fcSRobert Mustacchi 3129d26e4fcSRobert Mustacchi /* This macro is used to generate a compilation error if a structure 3139d26e4fcSRobert Mustacchi * is not exactly the correct length. It gives a divide by zero error if the 3149d26e4fcSRobert Mustacchi * structure is not of the correct size, otherwise it creates an enum that is 3159d26e4fcSRobert Mustacchi * never used. 3169d26e4fcSRobert Mustacchi */ 3179d26e4fcSRobert Mustacchi #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 3189d26e4fcSRobert Mustacchi { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 3199d26e4fcSRobert Mustacchi 3209d26e4fcSRobert Mustacchi /* This macro is used extensively to ensure that command structures are 16 3219d26e4fcSRobert Mustacchi * bytes in length as they have to map to the raw array of that size. 3229d26e4fcSRobert Mustacchi */ 3239d26e4fcSRobert Mustacchi #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 3249d26e4fcSRobert Mustacchi 3259d26e4fcSRobert Mustacchi /* internal (0x00XX) commands */ 3269d26e4fcSRobert Mustacchi 3279d26e4fcSRobert Mustacchi /* Get version (direct 0x0001) */ 3289d26e4fcSRobert Mustacchi struct i40e_aqc_get_version { 3299d26e4fcSRobert Mustacchi __le32 rom_ver; 3309d26e4fcSRobert Mustacchi __le32 fw_build; 3319d26e4fcSRobert Mustacchi __le16 fw_major; 3329d26e4fcSRobert Mustacchi __le16 fw_minor; 3339d26e4fcSRobert Mustacchi __le16 api_major; 3349d26e4fcSRobert Mustacchi __le16 api_minor; 3359d26e4fcSRobert Mustacchi }; 3369d26e4fcSRobert Mustacchi 3379d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 3389d26e4fcSRobert Mustacchi 3399d26e4fcSRobert Mustacchi /* Send driver version (indirect 0x0002) */ 3409d26e4fcSRobert Mustacchi struct i40e_aqc_driver_version { 3419d26e4fcSRobert Mustacchi u8 driver_major_ver; 3429d26e4fcSRobert Mustacchi u8 driver_minor_ver; 3439d26e4fcSRobert Mustacchi u8 driver_build_ver; 3449d26e4fcSRobert Mustacchi u8 driver_subbuild_ver; 3459d26e4fcSRobert Mustacchi u8 reserved[4]; 3469d26e4fcSRobert Mustacchi __le32 address_high; 3479d26e4fcSRobert Mustacchi __le32 address_low; 3489d26e4fcSRobert Mustacchi }; 3499d26e4fcSRobert Mustacchi 3509d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 3519d26e4fcSRobert Mustacchi 3529d26e4fcSRobert Mustacchi /* Queue Shutdown (direct 0x0003) */ 3539d26e4fcSRobert Mustacchi struct i40e_aqc_queue_shutdown { 3549d26e4fcSRobert Mustacchi __le32 driver_unloading; 3559d26e4fcSRobert Mustacchi #define I40E_AQ_DRIVER_UNLOADING 0x1 3569d26e4fcSRobert Mustacchi u8 reserved[12]; 3579d26e4fcSRobert Mustacchi }; 3589d26e4fcSRobert Mustacchi 3599d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 3609d26e4fcSRobert Mustacchi 3619d26e4fcSRobert Mustacchi /* Set PF context (0x0004, direct) */ 3629d26e4fcSRobert Mustacchi struct i40e_aqc_set_pf_context { 3639d26e4fcSRobert Mustacchi u8 pf_id; 3649d26e4fcSRobert Mustacchi u8 reserved[15]; 3659d26e4fcSRobert Mustacchi }; 3669d26e4fcSRobert Mustacchi 3679d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 3689d26e4fcSRobert Mustacchi 3699d26e4fcSRobert Mustacchi /* Request resource ownership (direct 0x0008) 3709d26e4fcSRobert Mustacchi * Release resource ownership (direct 0x0009) 3719d26e4fcSRobert Mustacchi */ 3729d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM 1 3739d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_SDP 2 3749d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_READ 1 3759d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 3769d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 3779d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 3789d26e4fcSRobert Mustacchi 3799d26e4fcSRobert Mustacchi struct i40e_aqc_request_resource { 3809d26e4fcSRobert Mustacchi __le16 resource_id; 3819d26e4fcSRobert Mustacchi __le16 access_type; 3829d26e4fcSRobert Mustacchi __le32 timeout; 3839d26e4fcSRobert Mustacchi __le32 resource_number; 3849d26e4fcSRobert Mustacchi u8 reserved[4]; 3859d26e4fcSRobert Mustacchi }; 3869d26e4fcSRobert Mustacchi 3879d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 3889d26e4fcSRobert Mustacchi 3899d26e4fcSRobert Mustacchi /* Get function capabilities (indirect 0x000A) 3909d26e4fcSRobert Mustacchi * Get device capabilities (indirect 0x000B) 3919d26e4fcSRobert Mustacchi */ 3929d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilites { 3939d26e4fcSRobert Mustacchi u8 command_flags; 3949d26e4fcSRobert Mustacchi #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 3959d26e4fcSRobert Mustacchi u8 pf_index; 3969d26e4fcSRobert Mustacchi u8 reserved[2]; 3979d26e4fcSRobert Mustacchi __le32 count; 3989d26e4fcSRobert Mustacchi __le32 addr_high; 3999d26e4fcSRobert Mustacchi __le32 addr_low; 4009d26e4fcSRobert Mustacchi }; 4019d26e4fcSRobert Mustacchi 4029d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 4039d26e4fcSRobert Mustacchi 4049d26e4fcSRobert Mustacchi struct i40e_aqc_list_capabilities_element_resp { 4059d26e4fcSRobert Mustacchi __le16 id; 4069d26e4fcSRobert Mustacchi u8 major_rev; 4079d26e4fcSRobert Mustacchi u8 minor_rev; 4089d26e4fcSRobert Mustacchi __le32 number; 4099d26e4fcSRobert Mustacchi __le32 logical_id; 4109d26e4fcSRobert Mustacchi __le32 phys_id; 4119d26e4fcSRobert Mustacchi u8 reserved[16]; 4129d26e4fcSRobert Mustacchi }; 4139d26e4fcSRobert Mustacchi 4149d26e4fcSRobert Mustacchi /* list of caps */ 4159d26e4fcSRobert Mustacchi 4169d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 4179d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 4189d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 4199d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 4209d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 4219d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 4229d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SRIOV 0x0012 4239d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF 0x0013 4249d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VMDQ 0x0014 4259d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBG 0x0015 4269d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_8021QBR 0x0016 4279d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VSI 0x0017 4289d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_DCB 0x0018 4299d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FCOE 0x0021 4309d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_ISCSI 0x0022 4319d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RSS 0x0040 4329d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_RXQ 0x0041 4339d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_TXQ 0x0042 4349d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MSIX 0x0043 4359d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 4369d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 4379d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_1588 0x0046 4389d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_IWARP 0x0051 4399d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_LED 0x0061 4409d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_SDP 0x0062 4419d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_MDIO 0x0063 4429d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_FLEX10 0x00F1 4439d26e4fcSRobert Mustacchi #define I40E_AQ_CAP_ID_CEM 0x00F2 4449d26e4fcSRobert Mustacchi 4459d26e4fcSRobert Mustacchi /* Set CPPM Configuration (direct 0x0103) */ 4469d26e4fcSRobert Mustacchi struct i40e_aqc_cppm_configuration { 4479d26e4fcSRobert Mustacchi __le16 command_flags; 4489d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_LTRC 0x0800 4499d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTH 0x1000 4509d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 4519d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_HPTC 0x4000 4529d26e4fcSRobert Mustacchi #define I40E_AQ_CPPM_EN_DMARC 0x8000 4539d26e4fcSRobert Mustacchi __le16 ttlx; 4549d26e4fcSRobert Mustacchi __le32 dmacr; 4559d26e4fcSRobert Mustacchi __le16 dmcth; 4569d26e4fcSRobert Mustacchi u8 hptc; 4579d26e4fcSRobert Mustacchi u8 reserved; 4589d26e4fcSRobert Mustacchi __le32 pfltrc; 4599d26e4fcSRobert Mustacchi }; 4609d26e4fcSRobert Mustacchi 4619d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 4629d26e4fcSRobert Mustacchi 4639d26e4fcSRobert Mustacchi /* Set ARP Proxy command / response (indirect 0x0104) */ 4649d26e4fcSRobert Mustacchi struct i40e_aqc_arp_proxy_data { 4659d26e4fcSRobert Mustacchi __le16 command_flags; 4669d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_INIT_IPV4 0x0008 4679d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_UNSUP_CTL 0x0010 4689d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_ENA 0x0020 4699d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_ADD_IPV4 0x0040 4709d26e4fcSRobert Mustacchi #define I40E_AQ_ARP_DEL_IPV4 0x0080 4719d26e4fcSRobert Mustacchi __le16 table_id; 4729d26e4fcSRobert Mustacchi __le32 pfpm_proxyfc; 4739d26e4fcSRobert Mustacchi __le32 ip_addr; 4749d26e4fcSRobert Mustacchi u8 mac_addr[6]; 4759d26e4fcSRobert Mustacchi u8 reserved[2]; 4769d26e4fcSRobert Mustacchi }; 4779d26e4fcSRobert Mustacchi 4789d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 4799d26e4fcSRobert Mustacchi 4809d26e4fcSRobert Mustacchi /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 4819d26e4fcSRobert Mustacchi struct i40e_aqc_ns_proxy_data { 4829d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_0; 4839d26e4fcSRobert Mustacchi __le16 table_idx_mac_addr_1; 4849d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_0; 4859d26e4fcSRobert Mustacchi __le16 table_idx_ipv6_1; 4869d26e4fcSRobert Mustacchi __le16 control; 4879d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_0 0x0100 4889d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_0 0x0200 4899d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_1 0x0400 4909d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_1 0x0800 4919d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 4929d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 4939d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 4949d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 4959d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 4969d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 4979d26e4fcSRobert Mustacchi #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 4989d26e4fcSRobert Mustacchi u8 mac_addr_0[6]; 4999d26e4fcSRobert Mustacchi u8 mac_addr_1[6]; 5009d26e4fcSRobert Mustacchi u8 local_mac_addr[6]; 5019d26e4fcSRobert Mustacchi u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 5029d26e4fcSRobert Mustacchi u8 ipv6_addr_1[16]; 5039d26e4fcSRobert Mustacchi }; 5049d26e4fcSRobert Mustacchi 5059d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 5069d26e4fcSRobert Mustacchi 5079d26e4fcSRobert Mustacchi /* Manage LAA Command (0x0106) - obsolete */ 5089d26e4fcSRobert Mustacchi struct i40e_aqc_mng_laa { 5099d26e4fcSRobert Mustacchi __le16 command_flags; 5109d26e4fcSRobert Mustacchi #define I40E_AQ_LAA_FLAG_WR 0x8000 5119d26e4fcSRobert Mustacchi u8 reserved[2]; 5129d26e4fcSRobert Mustacchi __le32 sal; 5139d26e4fcSRobert Mustacchi __le16 sah; 5149d26e4fcSRobert Mustacchi u8 reserved2[6]; 5159d26e4fcSRobert Mustacchi }; 5169d26e4fcSRobert Mustacchi 5179d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 5189d26e4fcSRobert Mustacchi 5199d26e4fcSRobert Mustacchi /* Manage MAC Address Read Command (indirect 0x0107) */ 5209d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read { 5219d26e4fcSRobert Mustacchi __le16 command_flags; 5229d26e4fcSRobert Mustacchi #define I40E_AQC_LAN_ADDR_VALID 0x10 5239d26e4fcSRobert Mustacchi #define I40E_AQC_SAN_ADDR_VALID 0x20 5249d26e4fcSRobert Mustacchi #define I40E_AQC_PORT_ADDR_VALID 0x40 5259d26e4fcSRobert Mustacchi #define I40E_AQC_WOL_ADDR_VALID 0x80 5269d26e4fcSRobert Mustacchi #define I40E_AQC_MC_MAG_EN_VALID 0x100 5279d26e4fcSRobert Mustacchi #define I40E_AQC_ADDR_VALID_MASK 0x1F0 5289d26e4fcSRobert Mustacchi u8 reserved[6]; 5299d26e4fcSRobert Mustacchi __le32 addr_high; 5309d26e4fcSRobert Mustacchi __le32 addr_low; 5319d26e4fcSRobert Mustacchi }; 5329d26e4fcSRobert Mustacchi 5339d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 5349d26e4fcSRobert Mustacchi 5359d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_read_data { 5369d26e4fcSRobert Mustacchi u8 pf_lan_mac[6]; 5379d26e4fcSRobert Mustacchi u8 pf_san_mac[6]; 5389d26e4fcSRobert Mustacchi u8 port_mac[6]; 5399d26e4fcSRobert Mustacchi u8 pf_wol_mac[6]; 5409d26e4fcSRobert Mustacchi }; 5419d26e4fcSRobert Mustacchi 5429d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 5439d26e4fcSRobert Mustacchi 5449d26e4fcSRobert Mustacchi /* Manage MAC Address Write Command (0x0108) */ 5459d26e4fcSRobert Mustacchi struct i40e_aqc_mac_address_write { 5469d26e4fcSRobert Mustacchi __le16 command_flags; 5479d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 5489d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 5499d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_PORT 0x8000 5509d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 5519d26e4fcSRobert Mustacchi #define I40E_AQC_WRITE_TYPE_MASK 0xC000 5529d26e4fcSRobert Mustacchi 5539d26e4fcSRobert Mustacchi __le16 mac_sah; 5549d26e4fcSRobert Mustacchi __le32 mac_sal; 5559d26e4fcSRobert Mustacchi u8 reserved[8]; 5569d26e4fcSRobert Mustacchi }; 5579d26e4fcSRobert Mustacchi 5589d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 5599d26e4fcSRobert Mustacchi 5609d26e4fcSRobert Mustacchi /* PXE commands (0x011x) */ 5619d26e4fcSRobert Mustacchi 5629d26e4fcSRobert Mustacchi /* Clear PXE Command and response (direct 0x0110) */ 5639d26e4fcSRobert Mustacchi struct i40e_aqc_clear_pxe { 5649d26e4fcSRobert Mustacchi u8 rx_cnt; 5659d26e4fcSRobert Mustacchi u8 reserved[15]; 5669d26e4fcSRobert Mustacchi }; 5679d26e4fcSRobert Mustacchi 5689d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 5699d26e4fcSRobert Mustacchi 5709d26e4fcSRobert Mustacchi /* Switch configuration commands (0x02xx) */ 5719d26e4fcSRobert Mustacchi 5729d26e4fcSRobert Mustacchi /* Used by many indirect commands that only pass an seid and a buffer in the 5739d26e4fcSRobert Mustacchi * command 5749d26e4fcSRobert Mustacchi */ 5759d26e4fcSRobert Mustacchi struct i40e_aqc_switch_seid { 5769d26e4fcSRobert Mustacchi __le16 seid; 5779d26e4fcSRobert Mustacchi u8 reserved[6]; 5789d26e4fcSRobert Mustacchi __le32 addr_high; 5799d26e4fcSRobert Mustacchi __le32 addr_low; 5809d26e4fcSRobert Mustacchi }; 5819d26e4fcSRobert Mustacchi 5829d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 5839d26e4fcSRobert Mustacchi 5849d26e4fcSRobert Mustacchi /* Get Switch Configuration command (indirect 0x0200) 5859d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 5869d26e4fcSRobert Mustacchi */ 5879d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp { 5889d26e4fcSRobert Mustacchi __le16 num_reported; 5899d26e4fcSRobert Mustacchi __le16 num_total; 5909d26e4fcSRobert Mustacchi u8 reserved[12]; 5919d26e4fcSRobert Mustacchi }; 5929d26e4fcSRobert Mustacchi 5939d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 5949d26e4fcSRobert Mustacchi 5959d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp { 5969d26e4fcSRobert Mustacchi u8 element_type; 5979d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_MAC 1 5989d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PF 2 5999d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VF 3 6009d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_EMP 4 6019d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_BMC 5 6029d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PV 16 6039d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VEB 17 6049d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_PA 18 6059d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_TYPE_VSI 19 6069d26e4fcSRobert Mustacchi u8 revision; 6079d26e4fcSRobert Mustacchi #define I40E_AQ_SW_ELEM_REV_1 1 6089d26e4fcSRobert Mustacchi __le16 seid; 6099d26e4fcSRobert Mustacchi __le16 uplink_seid; 6109d26e4fcSRobert Mustacchi __le16 downlink_seid; 6119d26e4fcSRobert Mustacchi u8 reserved[3]; 6129d26e4fcSRobert Mustacchi u8 connection_type; 6139d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_REGULAR 0x1 6149d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 6159d26e4fcSRobert Mustacchi #define I40E_AQ_CONN_TYPE_CASCADED 0x3 6169d26e4fcSRobert Mustacchi __le16 scheduler_id; 6179d26e4fcSRobert Mustacchi __le16 element_info; 6189d26e4fcSRobert Mustacchi }; 6199d26e4fcSRobert Mustacchi 6209d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 6219d26e4fcSRobert Mustacchi 6229d26e4fcSRobert Mustacchi /* Get Switch Configuration (indirect 0x0200) 6239d26e4fcSRobert Mustacchi * an array of elements are returned in the response buffer 6249d26e4fcSRobert Mustacchi * the first in the array is the header, remainder are elements 6259d26e4fcSRobert Mustacchi */ 6269d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_resp { 6279d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_config_header_resp header; 6289d26e4fcSRobert Mustacchi struct i40e_aqc_switch_config_element_resp element[1]; 6299d26e4fcSRobert Mustacchi }; 6309d26e4fcSRobert Mustacchi 6319d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 6329d26e4fcSRobert Mustacchi 6339d26e4fcSRobert Mustacchi /* Add Statistics (direct 0x0201) 6349d26e4fcSRobert Mustacchi * Remove Statistics (direct 0x0202) 6359d26e4fcSRobert Mustacchi */ 6369d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_statistics { 6379d26e4fcSRobert Mustacchi __le16 seid; 6389d26e4fcSRobert Mustacchi __le16 vlan; 6399d26e4fcSRobert Mustacchi __le16 stat_index; 6409d26e4fcSRobert Mustacchi u8 reserved[10]; 6419d26e4fcSRobert Mustacchi }; 6429d26e4fcSRobert Mustacchi 6439d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 6449d26e4fcSRobert Mustacchi 6459d26e4fcSRobert Mustacchi /* Set Port Parameters command (direct 0x0203) */ 6469d26e4fcSRobert Mustacchi struct i40e_aqc_set_port_parameters { 6479d26e4fcSRobert Mustacchi __le16 command_flags; 6489d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 6499d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 6509d26e4fcSRobert Mustacchi #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 6519d26e4fcSRobert Mustacchi __le16 bad_frame_vsi; 6529d26e4fcSRobert Mustacchi __le16 default_seid; /* reserved for command */ 6539d26e4fcSRobert Mustacchi u8 reserved[10]; 6549d26e4fcSRobert Mustacchi }; 6559d26e4fcSRobert Mustacchi 6569d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 6579d26e4fcSRobert Mustacchi 6589d26e4fcSRobert Mustacchi /* Get Switch Resource Allocation (indirect 0x0204) */ 6599d26e4fcSRobert Mustacchi struct i40e_aqc_get_switch_resource_alloc { 6609d26e4fcSRobert Mustacchi u8 num_entries; /* reserved for command */ 6619d26e4fcSRobert Mustacchi u8 reserved[7]; 6629d26e4fcSRobert Mustacchi __le32 addr_high; 6639d26e4fcSRobert Mustacchi __le32 addr_low; 6649d26e4fcSRobert Mustacchi }; 6659d26e4fcSRobert Mustacchi 6669d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 6679d26e4fcSRobert Mustacchi 6689d26e4fcSRobert Mustacchi /* expect an array of these structs in the response buffer */ 6699d26e4fcSRobert Mustacchi struct i40e_aqc_switch_resource_alloc_element_resp { 6709d26e4fcSRobert Mustacchi u8 resource_type; 6719d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 6729d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 6739d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 6749d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 6759d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 6769d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 6779d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 6789d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 6799d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 6809d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 6819d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 6829d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 6839d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 6849d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 6859d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 6869d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 6879d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 6889d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 6899d26e4fcSRobert Mustacchi #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 6909d26e4fcSRobert Mustacchi u8 reserved1; 6919d26e4fcSRobert Mustacchi __le16 guaranteed; 6929d26e4fcSRobert Mustacchi __le16 total; 6939d26e4fcSRobert Mustacchi __le16 used; 6949d26e4fcSRobert Mustacchi __le16 total_unalloced; 6959d26e4fcSRobert Mustacchi u8 reserved2[6]; 6969d26e4fcSRobert Mustacchi }; 6979d26e4fcSRobert Mustacchi 6989d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 6999d26e4fcSRobert Mustacchi 700*396505afSPaul Winder /* Read Receive control registers (direct 0x0206) 701*396505afSPaul Winder * Write Receive control registers (direct 0x0207) 702*396505afSPaul Winder * used for accessing Rx control registers that can be 703*396505afSPaul Winder * slow and need special handling when under high Rx load 704*396505afSPaul Winder */ 705*396505afSPaul Winder struct i40e_aqc_rx_ctl_reg_read_write { 706*396505afSPaul Winder __le32 reserved1; 707*396505afSPaul Winder __le32 address; 708*396505afSPaul Winder __le32 reserved2; 709*396505afSPaul Winder __le32 value; 710*396505afSPaul Winder }; 711*396505afSPaul Winder 712*396505afSPaul Winder I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 713*396505afSPaul Winder 7149d26e4fcSRobert Mustacchi /* Add VSI (indirect 0x0210) 7159d26e4fcSRobert Mustacchi * this indirect command uses struct i40e_aqc_vsi_properties_data 7169d26e4fcSRobert Mustacchi * as the indirect buffer (128 bytes) 7179d26e4fcSRobert Mustacchi * 7189d26e4fcSRobert Mustacchi * Update VSI (indirect 0x211) 7199d26e4fcSRobert Mustacchi * uses the same data structure as Add VSI 7209d26e4fcSRobert Mustacchi * 7219d26e4fcSRobert Mustacchi * Get VSI (indirect 0x0212) 7229d26e4fcSRobert Mustacchi * uses the same completion and data structure as Add VSI 7239d26e4fcSRobert Mustacchi */ 7249d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi { 7259d26e4fcSRobert Mustacchi __le16 uplink_seid; 7269d26e4fcSRobert Mustacchi u8 connection_type; 7279d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 7289d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 7299d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 7309d26e4fcSRobert Mustacchi u8 reserved1; 7319d26e4fcSRobert Mustacchi u8 vf_id; 7329d26e4fcSRobert Mustacchi u8 reserved2; 7339d26e4fcSRobert Mustacchi __le16 vsi_flags; 7349d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_SHIFT 0x0 7359d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 7369d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VF 0x0 7379d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 7389d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_PF 0x2 7399d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 7409d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 7419d26e4fcSRobert Mustacchi __le32 addr_high; 7429d26e4fcSRobert Mustacchi __le32 addr_low; 7439d26e4fcSRobert Mustacchi }; 7449d26e4fcSRobert Mustacchi 7459d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 7469d26e4fcSRobert Mustacchi 7479d26e4fcSRobert Mustacchi struct i40e_aqc_add_get_update_vsi_completion { 7489d26e4fcSRobert Mustacchi __le16 seid; 7499d26e4fcSRobert Mustacchi __le16 vsi_number; 7509d26e4fcSRobert Mustacchi __le16 vsi_used; 7519d26e4fcSRobert Mustacchi __le16 vsi_free; 7529d26e4fcSRobert Mustacchi __le32 addr_high; 7539d26e4fcSRobert Mustacchi __le32 addr_low; 7549d26e4fcSRobert Mustacchi }; 7559d26e4fcSRobert Mustacchi 7569d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 7579d26e4fcSRobert Mustacchi 7589d26e4fcSRobert Mustacchi struct i40e_aqc_vsi_properties_data { 7599d26e4fcSRobert Mustacchi /* first 96 byte are written by SW */ 7609d26e4fcSRobert Mustacchi __le16 valid_sections; 7619d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 7629d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 7639d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 7649d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 7659d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 7669d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 7679d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 7689d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 7699d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 7709d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 7719d26e4fcSRobert Mustacchi /* switch section */ 7729d26e4fcSRobert Mustacchi __le16 switch_id; /* 12bit id combined with flags below */ 7739d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 7749d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 7759d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 7769d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 7779d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 7789d26e4fcSRobert Mustacchi u8 sw_reserved[2]; 7799d26e4fcSRobert Mustacchi /* security section */ 7809d26e4fcSRobert Mustacchi u8 sec_flags; 7819d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 7829d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 7839d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 7849d26e4fcSRobert Mustacchi u8 sec_reserved; 7859d26e4fcSRobert Mustacchi /* VLAN section */ 7869d26e4fcSRobert Mustacchi __le16 pvid; /* VLANS include priority bits */ 7879d26e4fcSRobert Mustacchi __le16 fcoe_pvid; 7889d26e4fcSRobert Mustacchi u8 port_vlan_flags; 7899d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 7909d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 7919d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_MODE_SHIFT) 7929d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 7939d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 7949d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 7959d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 7969d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 7979d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 7989d26e4fcSRobert Mustacchi I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 7999d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 8009d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 8019d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 8029d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 8039d26e4fcSRobert Mustacchi u8 pvlan_reserved[3]; 8049d26e4fcSRobert Mustacchi /* ingress egress up sections */ 8059d26e4fcSRobert Mustacchi __le32 ingress_table; /* bitmap, 3 bits per up */ 8069d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 8079d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 8089d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 8099d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 8109d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 8119d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 8129d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 8139d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 8149d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 8159d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 8169d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 8179d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 8189d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 8199d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 8209d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 8219d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 8229d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 8239d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 8249d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 8259d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 8269d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 8279d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 8289d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 8299d26e4fcSRobert Mustacchi I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 8309d26e4fcSRobert Mustacchi __le32 egress_table; /* same defines as for ingress table */ 8319d26e4fcSRobert Mustacchi /* cascaded PV section */ 8329d26e4fcSRobert Mustacchi __le16 cas_pv_tag; 8339d26e4fcSRobert Mustacchi u8 cas_pv_flags; 8349d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 8359d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 8369d26e4fcSRobert Mustacchi I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 8379d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 8389d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 8399d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 8409d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 8419d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 8429d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 8439d26e4fcSRobert Mustacchi u8 cas_pv_reserved; 8449d26e4fcSRobert Mustacchi /* queue mapping section */ 8459d26e4fcSRobert Mustacchi __le16 mapping_flags; 8469d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 8479d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 8489d26e4fcSRobert Mustacchi __le16 queue_mapping[16]; 8499d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 8509d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 8519d26e4fcSRobert Mustacchi __le16 tc_mapping[8]; 8529d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 8539d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 8549d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 8559d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 8569d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 8579d26e4fcSRobert Mustacchi I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 858*396505afSPaul Winder #define I40E_AQ_VSI_TC_QUE_SIZE_MAX (1 << 0x6) 8599d26e4fcSRobert Mustacchi /* queueing option section */ 8609d26e4fcSRobert Mustacchi u8 queueing_opt_flags; 8619d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 8629d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 8639d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 8649d26e4fcSRobert Mustacchi #endif 8659d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 8669d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 8679d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 8689d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 8699d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 8709d26e4fcSRobert Mustacchi #endif 8719d26e4fcSRobert Mustacchi u8 queueing_opt_reserved[3]; 8729d26e4fcSRobert Mustacchi /* scheduler section */ 8739d26e4fcSRobert Mustacchi u8 up_enable_bits; 8749d26e4fcSRobert Mustacchi u8 sched_reserved; 8759d26e4fcSRobert Mustacchi /* outer up section */ 8769d26e4fcSRobert Mustacchi __le32 outer_up_table; /* same structure and defines as ingress table */ 8779d26e4fcSRobert Mustacchi u8 cmd_reserved[8]; 8789d26e4fcSRobert Mustacchi /* last 32 bytes are written by FW */ 8799d26e4fcSRobert Mustacchi __le16 qs_handle[8]; 8809d26e4fcSRobert Mustacchi #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 8819d26e4fcSRobert Mustacchi __le16 stat_counter_idx; 8829d26e4fcSRobert Mustacchi __le16 sched_id; 8839d26e4fcSRobert Mustacchi u8 resp_reserved[12]; 8849d26e4fcSRobert Mustacchi }; 8859d26e4fcSRobert Mustacchi 8869d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 8879d26e4fcSRobert Mustacchi 8889d26e4fcSRobert Mustacchi /* Add Port Virtualizer (direct 0x0220) 8899d26e4fcSRobert Mustacchi * also used for update PV (direct 0x0221) but only flags are used 8909d26e4fcSRobert Mustacchi * (IS_CTRL_PORT only works on add PV) 8919d26e4fcSRobert Mustacchi */ 8929d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv { 8939d26e4fcSRobert Mustacchi __le16 command_flags; 8949d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 8959d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 8969d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 8979d26e4fcSRobert Mustacchi #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 8989d26e4fcSRobert Mustacchi __le16 uplink_seid; 8999d26e4fcSRobert Mustacchi __le16 connected_seid; 9009d26e4fcSRobert Mustacchi u8 reserved[10]; 9019d26e4fcSRobert Mustacchi }; 9029d26e4fcSRobert Mustacchi 9039d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 9049d26e4fcSRobert Mustacchi 9059d26e4fcSRobert Mustacchi struct i40e_aqc_add_update_pv_completion { 9069d26e4fcSRobert Mustacchi /* reserved for update; for add also encodes error if rc == ENOSPC */ 9079d26e4fcSRobert Mustacchi __le16 pv_seid; 9089d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 9099d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 9109d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 9119d26e4fcSRobert Mustacchi #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 9129d26e4fcSRobert Mustacchi u8 reserved[14]; 9139d26e4fcSRobert Mustacchi }; 9149d26e4fcSRobert Mustacchi 9159d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 9169d26e4fcSRobert Mustacchi 9179d26e4fcSRobert Mustacchi /* Get PV Params (direct 0x0222) 9189d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 9199d26e4fcSRobert Mustacchi */ 9209d26e4fcSRobert Mustacchi 9219d26e4fcSRobert Mustacchi struct i40e_aqc_get_pv_params_completion { 9229d26e4fcSRobert Mustacchi __le16 seid; 9239d26e4fcSRobert Mustacchi __le16 default_stag; 9249d26e4fcSRobert Mustacchi __le16 pv_flags; /* same flags as add_pv */ 9259d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_PV_TYPE 0x1 9269d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 9279d26e4fcSRobert Mustacchi #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 9289d26e4fcSRobert Mustacchi u8 reserved[8]; 9299d26e4fcSRobert Mustacchi __le16 default_port_seid; 9309d26e4fcSRobert Mustacchi }; 9319d26e4fcSRobert Mustacchi 9329d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 9339d26e4fcSRobert Mustacchi 9349d26e4fcSRobert Mustacchi /* Add VEB (direct 0x0230) */ 9359d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb { 9369d26e4fcSRobert Mustacchi __le16 uplink_seid; 9379d26e4fcSRobert Mustacchi __le16 downlink_seid; 9389d26e4fcSRobert Mustacchi __le16 veb_flags; 9399d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_FLOATING 0x1 9409d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 9419d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 9429d26e4fcSRobert Mustacchi I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 9439d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 9449d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 9459d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 9469d26e4fcSRobert Mustacchi u8 enable_tcs; 9479d26e4fcSRobert Mustacchi u8 reserved[9]; 9489d26e4fcSRobert Mustacchi }; 9499d26e4fcSRobert Mustacchi 9509d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 9519d26e4fcSRobert Mustacchi 9529d26e4fcSRobert Mustacchi struct i40e_aqc_add_veb_completion { 9539d26e4fcSRobert Mustacchi u8 reserved[6]; 9549d26e4fcSRobert Mustacchi __le16 switch_seid; 9559d26e4fcSRobert Mustacchi /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 9569d26e4fcSRobert Mustacchi __le16 veb_seid; 9579d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 9589d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 9599d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 9609d26e4fcSRobert Mustacchi #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 9619d26e4fcSRobert Mustacchi __le16 statistic_index; 9629d26e4fcSRobert Mustacchi __le16 vebs_used; 9639d26e4fcSRobert Mustacchi __le16 vebs_free; 9649d26e4fcSRobert Mustacchi }; 9659d26e4fcSRobert Mustacchi 9669d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 9679d26e4fcSRobert Mustacchi 9689d26e4fcSRobert Mustacchi /* Get VEB Parameters (direct 0x0232) 9699d26e4fcSRobert Mustacchi * uses i40e_aqc_switch_seid for the descriptor 9709d26e4fcSRobert Mustacchi */ 9719d26e4fcSRobert Mustacchi struct i40e_aqc_get_veb_parameters_completion { 9729d26e4fcSRobert Mustacchi __le16 seid; 9739d26e4fcSRobert Mustacchi __le16 switch_id; 9749d26e4fcSRobert Mustacchi __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 9759d26e4fcSRobert Mustacchi __le16 statistic_index; 9769d26e4fcSRobert Mustacchi __le16 vebs_used; 9779d26e4fcSRobert Mustacchi __le16 vebs_free; 9789d26e4fcSRobert Mustacchi u8 reserved[4]; 9799d26e4fcSRobert Mustacchi }; 9809d26e4fcSRobert Mustacchi 9819d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 9829d26e4fcSRobert Mustacchi 9839d26e4fcSRobert Mustacchi /* Delete Element (direct 0x0243) 9849d26e4fcSRobert Mustacchi * uses the generic i40e_aqc_switch_seid 9859d26e4fcSRobert Mustacchi */ 9869d26e4fcSRobert Mustacchi 9879d26e4fcSRobert Mustacchi /* Add MAC-VLAN (indirect 0x0250) */ 9889d26e4fcSRobert Mustacchi 9899d26e4fcSRobert Mustacchi /* used for the command for most vlan commands */ 9909d26e4fcSRobert Mustacchi struct i40e_aqc_macvlan { 9919d26e4fcSRobert Mustacchi __le16 num_addresses; 9929d26e4fcSRobert Mustacchi __le16 seid[3]; 9939d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 9949d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 9959d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 9969d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 9979d26e4fcSRobert Mustacchi __le32 addr_high; 9989d26e4fcSRobert Mustacchi __le32 addr_low; 9999d26e4fcSRobert Mustacchi }; 10009d26e4fcSRobert Mustacchi 10019d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 10029d26e4fcSRobert Mustacchi 10039d26e4fcSRobert Mustacchi /* indirect data for command and response */ 10049d26e4fcSRobert Mustacchi struct i40e_aqc_add_macvlan_element_data { 10059d26e4fcSRobert Mustacchi u8 mac_addr[6]; 10069d26e4fcSRobert Mustacchi __le16 vlan_tag; 10079d26e4fcSRobert Mustacchi __le16 flags; 10089d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 10099d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 10109d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 10119d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 10129d26e4fcSRobert Mustacchi __le16 queue_number; 10139d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 10149d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 10159d26e4fcSRobert Mustacchi I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 10169d26e4fcSRobert Mustacchi /* response section */ 10179d26e4fcSRobert Mustacchi u8 match_method; 10189d26e4fcSRobert Mustacchi #define I40E_AQC_MM_PERFECT_MATCH 0x01 10199d26e4fcSRobert Mustacchi #define I40E_AQC_MM_HASH_MATCH 0x02 10209d26e4fcSRobert Mustacchi #define I40E_AQC_MM_ERR_NO_RES 0xFF 10219d26e4fcSRobert Mustacchi u8 reserved1[3]; 10229d26e4fcSRobert Mustacchi }; 10239d26e4fcSRobert Mustacchi 10249d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_macvlan_completion { 10259d26e4fcSRobert Mustacchi __le16 perfect_mac_used; 10269d26e4fcSRobert Mustacchi __le16 perfect_mac_free; 10279d26e4fcSRobert Mustacchi __le16 unicast_hash_free; 10289d26e4fcSRobert Mustacchi __le16 multicast_hash_free; 10299d26e4fcSRobert Mustacchi __le32 addr_high; 10309d26e4fcSRobert Mustacchi __le32 addr_low; 10319d26e4fcSRobert Mustacchi }; 10329d26e4fcSRobert Mustacchi 10339d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 10349d26e4fcSRobert Mustacchi 10359d26e4fcSRobert Mustacchi /* Remove MAC-VLAN (indirect 0x0251) 10369d26e4fcSRobert Mustacchi * uses i40e_aqc_macvlan for the descriptor 10379d26e4fcSRobert Mustacchi * data points to an array of num_addresses of elements 10389d26e4fcSRobert Mustacchi */ 10399d26e4fcSRobert Mustacchi 10409d26e4fcSRobert Mustacchi struct i40e_aqc_remove_macvlan_element_data { 10419d26e4fcSRobert Mustacchi u8 mac_addr[6]; 10429d26e4fcSRobert Mustacchi __le16 vlan_tag; 10439d26e4fcSRobert Mustacchi u8 flags; 10449d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 10459d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 10469d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 10479d26e4fcSRobert Mustacchi #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 10489d26e4fcSRobert Mustacchi u8 reserved[3]; 10499d26e4fcSRobert Mustacchi /* reply section */ 10509d26e4fcSRobert Mustacchi u8 error_code; 10519d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 10529d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 10539d26e4fcSRobert Mustacchi u8 reply_reserved[3]; 10549d26e4fcSRobert Mustacchi }; 10559d26e4fcSRobert Mustacchi 10569d26e4fcSRobert Mustacchi /* Add VLAN (indirect 0x0252) 10579d26e4fcSRobert Mustacchi * Remove VLAN (indirect 0x0253) 10589d26e4fcSRobert Mustacchi * use the generic i40e_aqc_macvlan for the command 10599d26e4fcSRobert Mustacchi */ 10609d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_element_data { 10619d26e4fcSRobert Mustacchi __le16 vlan_tag; 10629d26e4fcSRobert Mustacchi u8 vlan_flags; 10639d26e4fcSRobert Mustacchi /* flags for add VLAN */ 10649d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_LOCAL 0x1 10659d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 10669d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 10679d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 10689d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 10699d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 10709d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_SHIFT 3 10719d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 10729d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 10739d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 10749d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 10759d26e4fcSRobert Mustacchi #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 10769d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 10779d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_ALL 0x1 10789d26e4fcSRobert Mustacchi u8 reserved; 10799d26e4fcSRobert Mustacchi u8 result; 10809d26e4fcSRobert Mustacchi /* flags for add VLAN */ 10819d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 10829d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 10839d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 10849d26e4fcSRobert Mustacchi /* flags for remove VLAN */ 10859d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 10869d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 10879d26e4fcSRobert Mustacchi u8 reserved1[3]; 10889d26e4fcSRobert Mustacchi }; 10899d26e4fcSRobert Mustacchi 10909d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_vlan_completion { 10919d26e4fcSRobert Mustacchi u8 reserved[4]; 10929d26e4fcSRobert Mustacchi __le16 vlans_used; 10939d26e4fcSRobert Mustacchi __le16 vlans_free; 10949d26e4fcSRobert Mustacchi __le32 addr_high; 10959d26e4fcSRobert Mustacchi __le32 addr_low; 10969d26e4fcSRobert Mustacchi }; 10979d26e4fcSRobert Mustacchi 10989d26e4fcSRobert Mustacchi /* Set VSI Promiscuous Modes (direct 0x0254) */ 10999d26e4fcSRobert Mustacchi struct i40e_aqc_set_vsi_promiscuous_modes { 11009d26e4fcSRobert Mustacchi __le16 promiscuous_flags; 11019d26e4fcSRobert Mustacchi __le16 valid_flags; 11029d26e4fcSRobert Mustacchi /* flags used for both fields above */ 11039d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 11049d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 11059d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 11069d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_DEFAULT 0x08 11079d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 11089d26e4fcSRobert Mustacchi __le16 seid; 11099d26e4fcSRobert Mustacchi #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 11109d26e4fcSRobert Mustacchi __le16 vlan_tag; 11119d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 11129d26e4fcSRobert Mustacchi #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 11139d26e4fcSRobert Mustacchi u8 reserved[8]; 11149d26e4fcSRobert Mustacchi }; 11159d26e4fcSRobert Mustacchi 11169d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 11179d26e4fcSRobert Mustacchi 11189d26e4fcSRobert Mustacchi /* Add S/E-tag command (direct 0x0255) 11199d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 11209d26e4fcSRobert Mustacchi */ 11219d26e4fcSRobert Mustacchi struct i40e_aqc_add_tag { 11229d26e4fcSRobert Mustacchi __le16 flags; 11239d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 11249d26e4fcSRobert Mustacchi __le16 seid; 11259d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 11269d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 11279d26e4fcSRobert Mustacchi I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 11289d26e4fcSRobert Mustacchi __le16 tag; 11299d26e4fcSRobert Mustacchi __le16 queue_number; 11309d26e4fcSRobert Mustacchi u8 reserved[8]; 11319d26e4fcSRobert Mustacchi }; 11329d26e4fcSRobert Mustacchi 11339d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 11349d26e4fcSRobert Mustacchi 11359d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_tag_completion { 11369d26e4fcSRobert Mustacchi u8 reserved[12]; 11379d26e4fcSRobert Mustacchi __le16 tags_used; 11389d26e4fcSRobert Mustacchi __le16 tags_free; 11399d26e4fcSRobert Mustacchi }; 11409d26e4fcSRobert Mustacchi 11419d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 11429d26e4fcSRobert Mustacchi 11439d26e4fcSRobert Mustacchi /* Remove S/E-tag command (direct 0x0256) 11449d26e4fcSRobert Mustacchi * Uses generic i40e_aqc_add_remove_tag_completion for completion 11459d26e4fcSRobert Mustacchi */ 11469d26e4fcSRobert Mustacchi struct i40e_aqc_remove_tag { 11479d26e4fcSRobert Mustacchi __le16 seid; 11489d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 11499d26e4fcSRobert Mustacchi #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 11509d26e4fcSRobert Mustacchi I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 11519d26e4fcSRobert Mustacchi __le16 tag; 11529d26e4fcSRobert Mustacchi u8 reserved[12]; 11539d26e4fcSRobert Mustacchi }; 11549d26e4fcSRobert Mustacchi 11559d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 11569d26e4fcSRobert Mustacchi 11579d26e4fcSRobert Mustacchi /* Add multicast E-Tag (direct 0x0257) 11589d26e4fcSRobert Mustacchi * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 11599d26e4fcSRobert Mustacchi * and no external data 11609d26e4fcSRobert Mustacchi */ 11619d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag { 11629d26e4fcSRobert Mustacchi __le16 pv_seid; 11639d26e4fcSRobert Mustacchi __le16 etag; 11649d26e4fcSRobert Mustacchi u8 num_unicast_etags; 11659d26e4fcSRobert Mustacchi u8 reserved[3]; 11669d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte s-tags */ 11679d26e4fcSRobert Mustacchi __le32 addr_low; 11689d26e4fcSRobert Mustacchi }; 11699d26e4fcSRobert Mustacchi 11709d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 11719d26e4fcSRobert Mustacchi 11729d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_mcast_etag_completion { 11739d26e4fcSRobert Mustacchi u8 reserved[4]; 11749d26e4fcSRobert Mustacchi __le16 mcast_etags_used; 11759d26e4fcSRobert Mustacchi __le16 mcast_etags_free; 11769d26e4fcSRobert Mustacchi __le32 addr_high; 11779d26e4fcSRobert Mustacchi __le32 addr_low; 11789d26e4fcSRobert Mustacchi 11799d26e4fcSRobert Mustacchi }; 11809d26e4fcSRobert Mustacchi 11819d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 11829d26e4fcSRobert Mustacchi 11839d26e4fcSRobert Mustacchi /* Update S/E-Tag (direct 0x0259) */ 11849d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag { 11859d26e4fcSRobert Mustacchi __le16 seid; 11869d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 11879d26e4fcSRobert Mustacchi #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 11889d26e4fcSRobert Mustacchi I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 11899d26e4fcSRobert Mustacchi __le16 old_tag; 11909d26e4fcSRobert Mustacchi __le16 new_tag; 11919d26e4fcSRobert Mustacchi u8 reserved[10]; 11929d26e4fcSRobert Mustacchi }; 11939d26e4fcSRobert Mustacchi 11949d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 11959d26e4fcSRobert Mustacchi 11969d26e4fcSRobert Mustacchi struct i40e_aqc_update_tag_completion { 11979d26e4fcSRobert Mustacchi u8 reserved[12]; 11989d26e4fcSRobert Mustacchi __le16 tags_used; 11999d26e4fcSRobert Mustacchi __le16 tags_free; 12009d26e4fcSRobert Mustacchi }; 12019d26e4fcSRobert Mustacchi 12029d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 12039d26e4fcSRobert Mustacchi 12049d26e4fcSRobert Mustacchi /* Add Control Packet filter (direct 0x025A) 12059d26e4fcSRobert Mustacchi * Remove Control Packet filter (direct 0x025B) 12069d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_oveb_cloud, 12079d26e4fcSRobert Mustacchi * and the generic direct completion structure 12089d26e4fcSRobert Mustacchi */ 12099d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter { 12109d26e4fcSRobert Mustacchi u8 mac[6]; 12119d26e4fcSRobert Mustacchi __le16 etype; 12129d26e4fcSRobert Mustacchi __le16 flags; 12139d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 12149d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 12159d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 12169d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 12179d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 12189d26e4fcSRobert Mustacchi __le16 seid; 12199d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 12209d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 12219d26e4fcSRobert Mustacchi I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 12229d26e4fcSRobert Mustacchi __le16 queue; 12239d26e4fcSRobert Mustacchi u8 reserved[2]; 12249d26e4fcSRobert Mustacchi }; 12259d26e4fcSRobert Mustacchi 12269d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 12279d26e4fcSRobert Mustacchi 12289d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_control_packet_filter_completion { 12299d26e4fcSRobert Mustacchi __le16 mac_etype_used; 12309d26e4fcSRobert Mustacchi __le16 etype_used; 12319d26e4fcSRobert Mustacchi __le16 mac_etype_free; 12329d26e4fcSRobert Mustacchi __le16 etype_free; 12339d26e4fcSRobert Mustacchi u8 reserved[8]; 12349d26e4fcSRobert Mustacchi }; 12359d26e4fcSRobert Mustacchi 12369d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 12379d26e4fcSRobert Mustacchi 12389d26e4fcSRobert Mustacchi /* Add Cloud filters (indirect 0x025C) 12399d26e4fcSRobert Mustacchi * Remove Cloud filters (indirect 0x025D) 12409d26e4fcSRobert Mustacchi * uses the i40e_aqc_add_remove_cloud_filters, 12419d26e4fcSRobert Mustacchi * and the generic indirect completion structure 12429d26e4fcSRobert Mustacchi */ 12439d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters { 12449d26e4fcSRobert Mustacchi u8 num_filters; 12459d26e4fcSRobert Mustacchi u8 reserved; 12469d26e4fcSRobert Mustacchi __le16 seid; 12479d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 12489d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 12499d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 12509d26e4fcSRobert Mustacchi u8 reserved2[4]; 12519d26e4fcSRobert Mustacchi __le32 addr_high; 12529d26e4fcSRobert Mustacchi __le32 addr_low; 12539d26e4fcSRobert Mustacchi }; 12549d26e4fcSRobert Mustacchi 12559d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 12569d26e4fcSRobert Mustacchi 12579d26e4fcSRobert Mustacchi struct i40e_aqc_add_remove_cloud_filters_element_data { 12589d26e4fcSRobert Mustacchi u8 outer_mac[6]; 12599d26e4fcSRobert Mustacchi u8 inner_mac[6]; 12609d26e4fcSRobert Mustacchi __le16 inner_vlan; 12619d26e4fcSRobert Mustacchi union { 12629d26e4fcSRobert Mustacchi struct { 12639d26e4fcSRobert Mustacchi u8 reserved[12]; 12649d26e4fcSRobert Mustacchi u8 data[4]; 12659d26e4fcSRobert Mustacchi } v4; 12669d26e4fcSRobert Mustacchi struct { 12679d26e4fcSRobert Mustacchi u8 data[16]; 12689d26e4fcSRobert Mustacchi } v6; 12699d26e4fcSRobert Mustacchi } ipaddr; 12709d26e4fcSRobert Mustacchi __le16 flags; 12719d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 12729d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 12739d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 12749d26e4fcSRobert Mustacchi /* 0x0000 reserved */ 12759d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 12769d26e4fcSRobert Mustacchi /* 0x0002 reserved */ 12779d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 12789d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 12799d26e4fcSRobert Mustacchi /* 0x0005 reserved */ 12809d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 12819d26e4fcSRobert Mustacchi /* 0x0007 reserved */ 12829d26e4fcSRobert Mustacchi /* 0x0008 reserved */ 12839d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 12849d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 12859d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 12869d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 12879d26e4fcSRobert Mustacchi 12889d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 12899d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 12909d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 12919d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 12929d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 12939d26e4fcSRobert Mustacchi 12949d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 12959d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 12969d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 12979d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 12989d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 12999d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 13009d26e4fcSRobert Mustacchi 13019d26e4fcSRobert Mustacchi __le32 tenant_id; 13029d26e4fcSRobert Mustacchi u8 reserved[4]; 13039d26e4fcSRobert Mustacchi __le16 queue_number; 13049d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 13059d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 13069d26e4fcSRobert Mustacchi I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 13079d26e4fcSRobert Mustacchi u8 reserved2[14]; 13089d26e4fcSRobert Mustacchi /* response section */ 13099d26e4fcSRobert Mustacchi u8 allocation_result; 13109d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 13119d26e4fcSRobert Mustacchi #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 13129d26e4fcSRobert Mustacchi u8 response_reserved[7]; 13139d26e4fcSRobert Mustacchi }; 13149d26e4fcSRobert Mustacchi 13159d26e4fcSRobert Mustacchi struct i40e_aqc_remove_cloud_filters_completion { 13169d26e4fcSRobert Mustacchi __le16 perfect_ovlan_used; 13179d26e4fcSRobert Mustacchi __le16 perfect_ovlan_free; 13189d26e4fcSRobert Mustacchi __le16 vlan_used; 13199d26e4fcSRobert Mustacchi __le16 vlan_free; 13209d26e4fcSRobert Mustacchi __le32 addr_high; 13219d26e4fcSRobert Mustacchi __le32 addr_low; 13229d26e4fcSRobert Mustacchi }; 13239d26e4fcSRobert Mustacchi 13249d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 13259d26e4fcSRobert Mustacchi 13269d26e4fcSRobert Mustacchi /* Add Mirror Rule (indirect or direct 0x0260) 13279d26e4fcSRobert Mustacchi * Delete Mirror Rule (indirect or direct 0x0261) 13289d26e4fcSRobert Mustacchi * note: some rule types (4,5) do not use an external buffer. 13299d26e4fcSRobert Mustacchi * take care to set the flags correctly. 13309d26e4fcSRobert Mustacchi */ 13319d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule { 13329d26e4fcSRobert Mustacchi __le16 seid; 13339d26e4fcSRobert Mustacchi __le16 rule_type; 13349d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 13359d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 13369d26e4fcSRobert Mustacchi I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 13379d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 13389d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 13399d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 13409d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 13419d26e4fcSRobert Mustacchi #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 13429d26e4fcSRobert Mustacchi __le16 num_entries; 13439d26e4fcSRobert Mustacchi __le16 destination; /* VSI for add, rule id for delete */ 13449d26e4fcSRobert Mustacchi __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 13459d26e4fcSRobert Mustacchi __le32 addr_low; 13469d26e4fcSRobert Mustacchi }; 13479d26e4fcSRobert Mustacchi 13489d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 13499d26e4fcSRobert Mustacchi 13509d26e4fcSRobert Mustacchi struct i40e_aqc_add_delete_mirror_rule_completion { 13519d26e4fcSRobert Mustacchi u8 reserved[2]; 13529d26e4fcSRobert Mustacchi __le16 rule_id; /* only used on add */ 13539d26e4fcSRobert Mustacchi __le16 mirror_rules_used; 13549d26e4fcSRobert Mustacchi __le16 mirror_rules_free; 13559d26e4fcSRobert Mustacchi __le32 addr_high; 13569d26e4fcSRobert Mustacchi __le32 addr_low; 13579d26e4fcSRobert Mustacchi }; 13589d26e4fcSRobert Mustacchi 13599d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 13609d26e4fcSRobert Mustacchi 13619d26e4fcSRobert Mustacchi /* DCB 0x03xx*/ 13629d26e4fcSRobert Mustacchi 13639d26e4fcSRobert Mustacchi /* PFC Ignore (direct 0x0301) 13649d26e4fcSRobert Mustacchi * the command and response use the same descriptor structure 13659d26e4fcSRobert Mustacchi */ 13669d26e4fcSRobert Mustacchi struct i40e_aqc_pfc_ignore { 13679d26e4fcSRobert Mustacchi u8 tc_bitmap; 13689d26e4fcSRobert Mustacchi u8 command_flags; /* unused on response */ 13699d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_SET 0x80 13709d26e4fcSRobert Mustacchi #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 13719d26e4fcSRobert Mustacchi u8 reserved[14]; 13729d26e4fcSRobert Mustacchi }; 13739d26e4fcSRobert Mustacchi 13749d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 13759d26e4fcSRobert Mustacchi 13769d26e4fcSRobert Mustacchi /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 13779d26e4fcSRobert Mustacchi * with no parameters 13789d26e4fcSRobert Mustacchi */ 13799d26e4fcSRobert Mustacchi 13809d26e4fcSRobert Mustacchi /* TX scheduler 0x04xx */ 13819d26e4fcSRobert Mustacchi 13829d26e4fcSRobert Mustacchi /* Almost all the indirect commands use 13839d26e4fcSRobert Mustacchi * this generic struct to pass the SEID in param0 13849d26e4fcSRobert Mustacchi */ 13859d26e4fcSRobert Mustacchi struct i40e_aqc_tx_sched_ind { 13869d26e4fcSRobert Mustacchi __le16 vsi_seid; 13879d26e4fcSRobert Mustacchi u8 reserved[6]; 13889d26e4fcSRobert Mustacchi __le32 addr_high; 13899d26e4fcSRobert Mustacchi __le32 addr_low; 13909d26e4fcSRobert Mustacchi }; 13919d26e4fcSRobert Mustacchi 13929d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 13939d26e4fcSRobert Mustacchi 13949d26e4fcSRobert Mustacchi /* Several commands respond with a set of queue set handles */ 13959d26e4fcSRobert Mustacchi struct i40e_aqc_qs_handles_resp { 13969d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 13979d26e4fcSRobert Mustacchi }; 13989d26e4fcSRobert Mustacchi 13999d26e4fcSRobert Mustacchi /* Configure VSI BW limits (direct 0x0400) */ 14009d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_bw_limit { 14019d26e4fcSRobert Mustacchi __le16 vsi_seid; 14029d26e4fcSRobert Mustacchi u8 reserved[2]; 14039d26e4fcSRobert Mustacchi __le16 credit; 14049d26e4fcSRobert Mustacchi u8 reserved1[2]; 14059d26e4fcSRobert Mustacchi u8 max_credit; /* 0-3, limit = 2^max */ 14069d26e4fcSRobert Mustacchi u8 reserved2[7]; 14079d26e4fcSRobert Mustacchi }; 14089d26e4fcSRobert Mustacchi 14099d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 14109d26e4fcSRobert Mustacchi 14119d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 14129d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 14139d26e4fcSRobert Mustacchi */ 14149d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_ets_sla_bw_data { 14159d26e4fcSRobert Mustacchi u8 tc_valid_bits; 14169d26e4fcSRobert Mustacchi u8 reserved[15]; 14179d26e4fcSRobert Mustacchi __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 14189d26e4fcSRobert Mustacchi 14199d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 14209d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 14219d26e4fcSRobert Mustacchi u8 reserved1[28]; 14229d26e4fcSRobert Mustacchi }; 14239d26e4fcSRobert Mustacchi 14249d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 14259d26e4fcSRobert Mustacchi 14269d26e4fcSRobert Mustacchi /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 14279d26e4fcSRobert Mustacchi * responds with i40e_aqc_qs_handles_resp 14289d26e4fcSRobert Mustacchi */ 14299d26e4fcSRobert Mustacchi struct i40e_aqc_configure_vsi_tc_bw_data { 14309d26e4fcSRobert Mustacchi u8 tc_valid_bits; 14319d26e4fcSRobert Mustacchi u8 reserved[3]; 14329d26e4fcSRobert Mustacchi u8 tc_bw_credits[8]; 14339d26e4fcSRobert Mustacchi u8 reserved1[4]; 14349d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 14359d26e4fcSRobert Mustacchi }; 14369d26e4fcSRobert Mustacchi 14379d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 14389d26e4fcSRobert Mustacchi 14399d26e4fcSRobert Mustacchi /* Query vsi bw configuration (indirect 0x0408) */ 14409d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_bw_config_resp { 14419d26e4fcSRobert Mustacchi u8 tc_valid_bits; 14429d26e4fcSRobert Mustacchi u8 tc_suspended_bits; 14439d26e4fcSRobert Mustacchi u8 reserved[14]; 14449d26e4fcSRobert Mustacchi __le16 qs_handles[8]; 14459d26e4fcSRobert Mustacchi u8 reserved1[4]; 14469d26e4fcSRobert Mustacchi __le16 port_bw_limit; 14479d26e4fcSRobert Mustacchi u8 reserved2[2]; 14489d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 14499d26e4fcSRobert Mustacchi u8 reserved3[23]; 14509d26e4fcSRobert Mustacchi }; 14519d26e4fcSRobert Mustacchi 14529d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 14539d26e4fcSRobert Mustacchi 14549d26e4fcSRobert Mustacchi /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 14559d26e4fcSRobert Mustacchi struct i40e_aqc_query_vsi_ets_sla_config_resp { 14569d26e4fcSRobert Mustacchi u8 tc_valid_bits; 14579d26e4fcSRobert Mustacchi u8 reserved[3]; 14589d26e4fcSRobert Mustacchi u8 share_credits[8]; 14599d26e4fcSRobert Mustacchi __le16 credits[8]; 14609d26e4fcSRobert Mustacchi 14619d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 14629d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 14639d26e4fcSRobert Mustacchi }; 14649d26e4fcSRobert Mustacchi 14659d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 14669d26e4fcSRobert Mustacchi 14679d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 14689d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_limit { 14699d26e4fcSRobert Mustacchi __le16 seid; 14709d26e4fcSRobert Mustacchi u8 reserved[2]; 14719d26e4fcSRobert Mustacchi __le16 credit; 14729d26e4fcSRobert Mustacchi u8 reserved1[2]; 14739d26e4fcSRobert Mustacchi u8 max_bw; /* 0-3, limit = 2^max */ 14749d26e4fcSRobert Mustacchi u8 reserved2[7]; 14759d26e4fcSRobert Mustacchi }; 14769d26e4fcSRobert Mustacchi 14779d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 14789d26e4fcSRobert Mustacchi 14799d26e4fcSRobert Mustacchi /* Enable Physical Port ETS (indirect 0x0413) 14809d26e4fcSRobert Mustacchi * Modify Physical Port ETS (indirect 0x0414) 14819d26e4fcSRobert Mustacchi * Disable Physical Port ETS (indirect 0x0415) 14829d26e4fcSRobert Mustacchi */ 14839d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_data { 14849d26e4fcSRobert Mustacchi u8 reserved[4]; 14859d26e4fcSRobert Mustacchi u8 tc_valid_bits; 14869d26e4fcSRobert Mustacchi u8 seepage; 14879d26e4fcSRobert Mustacchi #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 14889d26e4fcSRobert Mustacchi u8 tc_strict_priority_flags; 14899d26e4fcSRobert Mustacchi u8 reserved1[17]; 14909d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 14919d26e4fcSRobert Mustacchi u8 reserved2[96]; 14929d26e4fcSRobert Mustacchi }; 14939d26e4fcSRobert Mustacchi 14949d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 14959d26e4fcSRobert Mustacchi 14969d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 14979d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 14989d26e4fcSRobert Mustacchi u8 tc_valid_bits; 14999d26e4fcSRobert Mustacchi u8 reserved[15]; 15009d26e4fcSRobert Mustacchi __le16 tc_bw_credit[8]; 15019d26e4fcSRobert Mustacchi 15029d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 15039d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 15049d26e4fcSRobert Mustacchi u8 reserved1[28]; 15059d26e4fcSRobert Mustacchi }; 15069d26e4fcSRobert Mustacchi 15079d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 15089d26e4fcSRobert Mustacchi 15099d26e4fcSRobert Mustacchi /* Configure Switching Component Bandwidth Allocation per Tc 15109d26e4fcSRobert Mustacchi * (indirect 0x0417) 15119d26e4fcSRobert Mustacchi */ 15129d26e4fcSRobert Mustacchi struct i40e_aqc_configure_switching_comp_bw_config_data { 15139d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15149d26e4fcSRobert Mustacchi u8 reserved[2]; 15159d26e4fcSRobert Mustacchi u8 absolute_credits; /* bool */ 15169d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 15179d26e4fcSRobert Mustacchi u8 reserved1[20]; 15189d26e4fcSRobert Mustacchi }; 15199d26e4fcSRobert Mustacchi 15209d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 15219d26e4fcSRobert Mustacchi 15229d26e4fcSRobert Mustacchi /* Query Switching Component Configuration (indirect 0x0418) */ 15239d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_ets_config_resp { 15249d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15259d26e4fcSRobert Mustacchi u8 reserved[35]; 15269d26e4fcSRobert Mustacchi __le16 port_bw_limit; 15279d26e4fcSRobert Mustacchi u8 reserved1[2]; 15289d26e4fcSRobert Mustacchi u8 tc_bw_max; /* 0-3, limit = 2^max */ 15299d26e4fcSRobert Mustacchi u8 reserved2[23]; 15309d26e4fcSRobert Mustacchi }; 15319d26e4fcSRobert Mustacchi 15329d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 15339d26e4fcSRobert Mustacchi 15349d26e4fcSRobert Mustacchi /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 15359d26e4fcSRobert Mustacchi struct i40e_aqc_query_port_ets_config_resp { 15369d26e4fcSRobert Mustacchi u8 reserved[4]; 15379d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15389d26e4fcSRobert Mustacchi u8 reserved1; 15399d26e4fcSRobert Mustacchi u8 tc_strict_priority_bits; 15409d26e4fcSRobert Mustacchi u8 reserved2; 15419d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 15429d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 15439d26e4fcSRobert Mustacchi 15449d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 15459d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 15469d26e4fcSRobert Mustacchi u8 reserved3[32]; 15479d26e4fcSRobert Mustacchi }; 15489d26e4fcSRobert Mustacchi 15499d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 15509d26e4fcSRobert Mustacchi 15519d26e4fcSRobert Mustacchi /* Query Switching Component Bandwidth Allocation per Traffic Type 15529d26e4fcSRobert Mustacchi * (indirect 0x041A) 15539d26e4fcSRobert Mustacchi */ 15549d26e4fcSRobert Mustacchi struct i40e_aqc_query_switching_comp_bw_config_resp { 15559d26e4fcSRobert Mustacchi u8 tc_valid_bits; 15569d26e4fcSRobert Mustacchi u8 reserved[2]; 15579d26e4fcSRobert Mustacchi u8 absolute_credits_enable; /* bool */ 15589d26e4fcSRobert Mustacchi u8 tc_bw_share_credits[8]; 15599d26e4fcSRobert Mustacchi __le16 tc_bw_limits[8]; 15609d26e4fcSRobert Mustacchi 15619d26e4fcSRobert Mustacchi /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 15629d26e4fcSRobert Mustacchi __le16 tc_bw_max[2]; 15639d26e4fcSRobert Mustacchi }; 15649d26e4fcSRobert Mustacchi 15659d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 15669d26e4fcSRobert Mustacchi 15679d26e4fcSRobert Mustacchi /* Suspend/resume port TX traffic 15689d26e4fcSRobert Mustacchi * (direct 0x041B and 0x041C) uses the generic SEID struct 15699d26e4fcSRobert Mustacchi */ 15709d26e4fcSRobert Mustacchi 15719d26e4fcSRobert Mustacchi /* Configure partition BW 15729d26e4fcSRobert Mustacchi * (indirect 0x041D) 15739d26e4fcSRobert Mustacchi */ 15749d26e4fcSRobert Mustacchi struct i40e_aqc_configure_partition_bw_data { 15759d26e4fcSRobert Mustacchi __le16 pf_valid_bits; 15769d26e4fcSRobert Mustacchi u8 min_bw[16]; /* guaranteed bandwidth */ 15779d26e4fcSRobert Mustacchi u8 max_bw[16]; /* bandwidth limit */ 15789d26e4fcSRobert Mustacchi }; 15799d26e4fcSRobert Mustacchi 15809d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 15819d26e4fcSRobert Mustacchi 15829d26e4fcSRobert Mustacchi /* Get and set the active HMC resource profile and status. 15839d26e4fcSRobert Mustacchi * (direct 0x0500) and (direct 0x0501) 15849d26e4fcSRobert Mustacchi */ 15859d26e4fcSRobert Mustacchi struct i40e_aq_get_set_hmc_resource_profile { 15869d26e4fcSRobert Mustacchi u8 pm_profile; 15879d26e4fcSRobert Mustacchi u8 pe_vf_enabled; 15889d26e4fcSRobert Mustacchi u8 reserved[14]; 15899d26e4fcSRobert Mustacchi }; 15909d26e4fcSRobert Mustacchi 15919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 15929d26e4fcSRobert Mustacchi 15939d26e4fcSRobert Mustacchi enum i40e_aq_hmc_profile { 15949d26e4fcSRobert Mustacchi /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 15959d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_DEFAULT = 1, 15969d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_FAVOR_VF = 2, 15979d26e4fcSRobert Mustacchi I40E_HMC_PROFILE_EQUAL = 3, 15989d26e4fcSRobert Mustacchi }; 15999d26e4fcSRobert Mustacchi 16009d26e4fcSRobert Mustacchi #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 16019d26e4fcSRobert Mustacchi #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 16029d26e4fcSRobert Mustacchi 16039d26e4fcSRobert Mustacchi /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 16049d26e4fcSRobert Mustacchi 16059d26e4fcSRobert Mustacchi /* set in param0 for get phy abilities to report qualified modules */ 16069d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 16079d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 16089d26e4fcSRobert Mustacchi 16099d26e4fcSRobert Mustacchi enum i40e_aq_phy_type { 16109d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SGMII = 0x0, 16119d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_KX = 0x1, 16129d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 16139d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_KR = 0x3, 16149d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 16159d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XAUI = 0x5, 16169d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XFI = 0x6, 16179d26e4fcSRobert Mustacchi I40E_PHY_TYPE_SFI = 0x7, 16189d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLAUI = 0x8, 16199d26e4fcSRobert Mustacchi I40E_PHY_TYPE_XLPPI = 0x9, 16209d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 16219d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 16229d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_AOC = 0xC, 16239d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_AOC = 0xD, 16249d26e4fcSRobert Mustacchi I40E_PHY_TYPE_100BASE_TX = 0x11, 16259d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T = 0x12, 16269d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_T = 0x13, 16279d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SR = 0x14, 16289d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_LR = 0x15, 16299d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 16309d26e4fcSRobert Mustacchi I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 16319d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 16329d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 16339d26e4fcSRobert Mustacchi I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 16349d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_SX = 0x1B, 16359d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_LX = 0x1C, 16369d26e4fcSRobert Mustacchi I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 16379d26e4fcSRobert Mustacchi I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 16389d26e4fcSRobert Mustacchi I40E_PHY_TYPE_MAX 16399d26e4fcSRobert Mustacchi }; 16409d26e4fcSRobert Mustacchi 16419d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_100MB_SHIFT 0x1 16429d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 16439d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_10GB_SHIFT 0x3 16449d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_40GB_SHIFT 0x4 16459d26e4fcSRobert Mustacchi #define I40E_LINK_SPEED_20GB_SHIFT 0x5 16469d26e4fcSRobert Mustacchi 16479d26e4fcSRobert Mustacchi enum i40e_aq_link_speed { 16489d26e4fcSRobert Mustacchi I40E_LINK_SPEED_UNKNOWN = 0, 16499d26e4fcSRobert Mustacchi I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 16509d26e4fcSRobert Mustacchi I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 16519d26e4fcSRobert Mustacchi I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 16529d26e4fcSRobert Mustacchi I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 16539d26e4fcSRobert Mustacchi I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 16549d26e4fcSRobert Mustacchi }; 16559d26e4fcSRobert Mustacchi 16569d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc { 16579d26e4fcSRobert Mustacchi u8 oui[3]; 16589d26e4fcSRobert Mustacchi u8 reserved1; 16599d26e4fcSRobert Mustacchi u8 part_number[16]; 16609d26e4fcSRobert Mustacchi u8 revision[4]; 16619d26e4fcSRobert Mustacchi u8 reserved2[8]; 16629d26e4fcSRobert Mustacchi }; 16639d26e4fcSRobert Mustacchi 16649d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 16659d26e4fcSRobert Mustacchi 16669d26e4fcSRobert Mustacchi struct i40e_aq_get_phy_abilities_resp { 16679d26e4fcSRobert Mustacchi __le32 phy_type; /* bitmap using the above enum for offsets */ 16689d26e4fcSRobert Mustacchi u8 link_speed; /* bitmap using the above enum bit patterns */ 16699d26e4fcSRobert Mustacchi u8 abilities; 16709d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 16719d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 16729d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 16739d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLED 0x08 16749d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_AN_ENABLED 0x10 16759d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 16769d26e4fcSRobert Mustacchi __le16 eee_capability; 16779d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_100BASE_TX 0x0002 16789d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_T 0x0004 16799d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_T 0x0008 16809d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_1000BASE_KX 0x0010 16819d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KX4 0x0020 16829d26e4fcSRobert Mustacchi #define I40E_AQ_EEE_10GBASE_KR 0x0040 16839d26e4fcSRobert Mustacchi __le32 eeer_val; 16849d26e4fcSRobert Mustacchi u8 d3_lpan; 16859d26e4fcSRobert Mustacchi #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 16869d26e4fcSRobert Mustacchi u8 reserved[3]; 16879d26e4fcSRobert Mustacchi u8 phy_id[4]; 16889d26e4fcSRobert Mustacchi u8 module_type[3]; 16899d26e4fcSRobert Mustacchi u8 qualified_module_count; 16909d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_MAX_QMS 16 16919d26e4fcSRobert Mustacchi struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 16929d26e4fcSRobert Mustacchi }; 16939d26e4fcSRobert Mustacchi 16949d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 16959d26e4fcSRobert Mustacchi 16969d26e4fcSRobert Mustacchi /* Set PHY Config (direct 0x0601) */ 16979d26e4fcSRobert Mustacchi struct i40e_aq_set_phy_config { /* same bits as above in all */ 16989d26e4fcSRobert Mustacchi __le32 phy_type; 16999d26e4fcSRobert Mustacchi u8 link_speed; 17009d26e4fcSRobert Mustacchi u8 abilities; 17019d26e4fcSRobert Mustacchi /* bits 0-2 use the values from get_phy_abilities_resp */ 17029d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_LINK 0x08 17039d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_AN 0x10 17049d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 17059d26e4fcSRobert Mustacchi __le16 eee_capability; 17069d26e4fcSRobert Mustacchi __le32 eeer; 17079d26e4fcSRobert Mustacchi u8 low_power_ctrl; 17089d26e4fcSRobert Mustacchi u8 reserved[3]; 17099d26e4fcSRobert Mustacchi }; 17109d26e4fcSRobert Mustacchi 17119d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 17129d26e4fcSRobert Mustacchi 17139d26e4fcSRobert Mustacchi /* Set MAC Config command data structure (direct 0x0603) */ 17149d26e4fcSRobert Mustacchi struct i40e_aq_set_mac_config { 17159d26e4fcSRobert Mustacchi __le16 max_frame_size; 17169d26e4fcSRobert Mustacchi u8 params; 17179d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 17189d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 17199d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 17209d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 17219d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 17229d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 17239d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 17249d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 17259d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 17269d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 17279d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 17289d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 17299d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 17309d26e4fcSRobert Mustacchi #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 17319d26e4fcSRobert Mustacchi u8 tx_timer_priority; /* bitmap */ 17329d26e4fcSRobert Mustacchi __le16 tx_timer_value; 17339d26e4fcSRobert Mustacchi __le16 fc_refresh_threshold; 17349d26e4fcSRobert Mustacchi u8 reserved[8]; 17359d26e4fcSRobert Mustacchi }; 17369d26e4fcSRobert Mustacchi 17379d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 17389d26e4fcSRobert Mustacchi 17399d26e4fcSRobert Mustacchi /* Restart Auto-Negotiation (direct 0x605) */ 17409d26e4fcSRobert Mustacchi struct i40e_aqc_set_link_restart_an { 17419d26e4fcSRobert Mustacchi u8 command; 17429d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_RESTART_AN 0x02 17439d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LINK_ENABLE 0x04 17449d26e4fcSRobert Mustacchi u8 reserved[15]; 17459d26e4fcSRobert Mustacchi }; 17469d26e4fcSRobert Mustacchi 17479d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 17489d26e4fcSRobert Mustacchi 17499d26e4fcSRobert Mustacchi /* Get Link Status cmd & response data structure (direct 0x0607) */ 17509d26e4fcSRobert Mustacchi struct i40e_aqc_get_link_status { 17519d26e4fcSRobert Mustacchi __le16 command_flags; /* only field set on command */ 17529d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_MASK 0x3 17539d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_NOP 0x0 17549d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_DISABLE 0x2 17559d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_ENABLE 0x3 17569d26e4fcSRobert Mustacchi /* only response uses this flag */ 17579d26e4fcSRobert Mustacchi #define I40E_AQ_LSE_IS_ENABLED 0x1 17589d26e4fcSRobert Mustacchi u8 phy_type; /* i40e_aq_phy_type */ 17599d26e4fcSRobert Mustacchi u8 link_speed; /* i40e_aq_link_speed */ 17609d26e4fcSRobert Mustacchi u8 link_info; 17619d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 17629d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_FUNCTION 0x01 17639d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT 0x02 17649d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_TX 0x04 17659d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_RX 0x08 17669d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FAULT_REMOTE 0x10 17679d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_UP_PORT 0x20 17689d26e4fcSRobert Mustacchi #define I40E_AQ_MEDIA_AVAILABLE 0x40 17699d26e4fcSRobert Mustacchi #define I40E_AQ_SIGNAL_DETECT 0x80 17709d26e4fcSRobert Mustacchi u8 an_info; 17719d26e4fcSRobert Mustacchi #define I40E_AQ_AN_COMPLETED 0x01 17729d26e4fcSRobert Mustacchi #define I40E_AQ_LP_AN_ABILITY 0x02 17739d26e4fcSRobert Mustacchi #define I40E_AQ_PD_FAULT 0x04 17749d26e4fcSRobert Mustacchi #define I40E_AQ_FEC_EN 0x08 17759d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_LOW_POWER 0x10 17769d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_TX 0x20 17779d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PAUSE_RX 0x40 17789d26e4fcSRobert Mustacchi #define I40E_AQ_QUALIFIED_MODULE 0x80 17799d26e4fcSRobert Mustacchi u8 ext_info; 17809d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 17819d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 17829d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_SHIFT 0x02 17839d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 17849d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_ACTIVE 0x00 17859d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_DRAINED 0x01 17869d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_TX_FLUSHED 0x03 17879d26e4fcSRobert Mustacchi #define I40E_AQ_LINK_FORCED_40G 0x10 17889d26e4fcSRobert Mustacchi u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 17899d26e4fcSRobert Mustacchi __le16 max_frame_size; 17909d26e4fcSRobert Mustacchi u8 config; 17919d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_CRC_ENA 0x04 17929d26e4fcSRobert Mustacchi #define I40E_AQ_CONFIG_PACING_MASK 0x78 17939d26e4fcSRobert Mustacchi u8 reserved[5]; 17949d26e4fcSRobert Mustacchi }; 17959d26e4fcSRobert Mustacchi 17969d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 17979d26e4fcSRobert Mustacchi 17989d26e4fcSRobert Mustacchi /* Set event mask command (direct 0x613) */ 17999d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_int_mask { 18009d26e4fcSRobert Mustacchi u8 reserved[8]; 18019d26e4fcSRobert Mustacchi __le16 event_mask; 18029d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 18039d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MEDIA_NA 0x0004 18049d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_LINK_FAULT 0x0008 18059d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 18069d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 18079d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 18089d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 18099d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 18109d26e4fcSRobert Mustacchi #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 18119d26e4fcSRobert Mustacchi u8 reserved1[6]; 18129d26e4fcSRobert Mustacchi }; 18139d26e4fcSRobert Mustacchi 18149d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 18159d26e4fcSRobert Mustacchi 18169d26e4fcSRobert Mustacchi /* Get Local AN advt register (direct 0x0614) 18179d26e4fcSRobert Mustacchi * Set Local AN advt register (direct 0x0615) 18189d26e4fcSRobert Mustacchi * Get Link Partner AN advt register (direct 0x0616) 18199d26e4fcSRobert Mustacchi */ 18209d26e4fcSRobert Mustacchi struct i40e_aqc_an_advt_reg { 18219d26e4fcSRobert Mustacchi __le32 local_an_reg0; 18229d26e4fcSRobert Mustacchi __le16 local_an_reg1; 18239d26e4fcSRobert Mustacchi u8 reserved[10]; 18249d26e4fcSRobert Mustacchi }; 18259d26e4fcSRobert Mustacchi 18269d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 18279d26e4fcSRobert Mustacchi 18289d26e4fcSRobert Mustacchi /* Set Loopback mode (0x0618) */ 18299d26e4fcSRobert Mustacchi struct i40e_aqc_set_lb_mode { 18309d26e4fcSRobert Mustacchi __le16 lb_mode; 18319d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_LOCAL 0x01 18329d26e4fcSRobert Mustacchi #define I40E_AQ_LB_PHY_REMOTE 0x02 18339d26e4fcSRobert Mustacchi #define I40E_AQ_LB_MAC_LOCAL 0x04 18349d26e4fcSRobert Mustacchi u8 reserved[14]; 18359d26e4fcSRobert Mustacchi }; 18369d26e4fcSRobert Mustacchi 18379d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 18389d26e4fcSRobert Mustacchi 18399d26e4fcSRobert Mustacchi /* Set PHY Debug command (0x0622) */ 18409d26e4fcSRobert Mustacchi struct i40e_aqc_set_phy_debug { 18419d26e4fcSRobert Mustacchi u8 command_flags; 18429d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 18439d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 18449d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 18459d26e4fcSRobert Mustacchi I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 18469d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 18479d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 18489d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 18499d26e4fcSRobert Mustacchi #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 18509d26e4fcSRobert Mustacchi u8 reserved[15]; 18519d26e4fcSRobert Mustacchi }; 18529d26e4fcSRobert Mustacchi 18539d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 18549d26e4fcSRobert Mustacchi 18559d26e4fcSRobert Mustacchi enum i40e_aq_phy_reg_type { 18569d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_INTERNAL = 0x1, 18579d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 18589d26e4fcSRobert Mustacchi I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 18599d26e4fcSRobert Mustacchi }; 18609d26e4fcSRobert Mustacchi 18619d26e4fcSRobert Mustacchi /* NVM Read command (indirect 0x0701) 18629d26e4fcSRobert Mustacchi * NVM Erase commands (direct 0x0702) 18639d26e4fcSRobert Mustacchi * NVM Update commands (indirect 0x0703) 18649d26e4fcSRobert Mustacchi */ 18659d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_update { 18669d26e4fcSRobert Mustacchi u8 command_flags; 18679d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_LAST_CMD 0x01 18689d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_FLASH_ONLY 0x80 18699d26e4fcSRobert Mustacchi u8 module_pointer; 18709d26e4fcSRobert Mustacchi __le16 length; 18719d26e4fcSRobert Mustacchi __le32 offset; 18729d26e4fcSRobert Mustacchi __le32 addr_high; 18739d26e4fcSRobert Mustacchi __le32 addr_low; 18749d26e4fcSRobert Mustacchi }; 18759d26e4fcSRobert Mustacchi 18769d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 18779d26e4fcSRobert Mustacchi 18789d26e4fcSRobert Mustacchi /* NVM Config Read (indirect 0x0704) */ 18799d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_read { 18809d26e4fcSRobert Mustacchi __le16 cmd_flags; 18819d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 18829d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 18839d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 18849d26e4fcSRobert Mustacchi __le16 element_count; 18859d26e4fcSRobert Mustacchi __le16 element_id; /* Feature/field ID */ 18869d26e4fcSRobert Mustacchi __le16 element_id_msw; /* MSWord of field ID */ 18879d26e4fcSRobert Mustacchi __le32 address_high; 18889d26e4fcSRobert Mustacchi __le32 address_low; 18899d26e4fcSRobert Mustacchi }; 18909d26e4fcSRobert Mustacchi 18919d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 18929d26e4fcSRobert Mustacchi 18939d26e4fcSRobert Mustacchi /* NVM Config Write (indirect 0x0705) */ 18949d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_write { 18959d26e4fcSRobert Mustacchi __le16 cmd_flags; 18969d26e4fcSRobert Mustacchi __le16 element_count; 18979d26e4fcSRobert Mustacchi u8 reserved[4]; 18989d26e4fcSRobert Mustacchi __le32 address_high; 18999d26e4fcSRobert Mustacchi __le32 address_low; 19009d26e4fcSRobert Mustacchi }; 19019d26e4fcSRobert Mustacchi 19029d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 19039d26e4fcSRobert Mustacchi 19049d26e4fcSRobert Mustacchi /* Used for 0x0704 as well as for 0x0705 commands */ 19059d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 19069d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 19079d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE 0 19089d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 19099d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_feature { 19109d26e4fcSRobert Mustacchi __le16 feature_id; 19119d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 19129d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 19139d26e4fcSRobert Mustacchi #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 19149d26e4fcSRobert Mustacchi __le16 feature_options; 19159d26e4fcSRobert Mustacchi __le16 feature_selection; 19169d26e4fcSRobert Mustacchi }; 19179d26e4fcSRobert Mustacchi 19189d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 19199d26e4fcSRobert Mustacchi 19209d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_config_data_immediate_field { 19219d26e4fcSRobert Mustacchi __le32 field_id; 19229d26e4fcSRobert Mustacchi __le32 field_value; 19239d26e4fcSRobert Mustacchi __le16 field_options; 19249d26e4fcSRobert Mustacchi __le16 reserved; 19259d26e4fcSRobert Mustacchi }; 19269d26e4fcSRobert Mustacchi 19279d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 19289d26e4fcSRobert Mustacchi 19299d26e4fcSRobert Mustacchi /* OEM Post Update (indirect 0x0720) 19309d26e4fcSRobert Mustacchi * no command data struct used 19319d26e4fcSRobert Mustacchi */ 19329d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_oem_post_update { 19339d26e4fcSRobert Mustacchi #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 19349d26e4fcSRobert Mustacchi u8 sel_data; 19359d26e4fcSRobert Mustacchi u8 reserved[7]; 19369d26e4fcSRobert Mustacchi }; 19379d26e4fcSRobert Mustacchi 19389d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 19399d26e4fcSRobert Mustacchi 19409d26e4fcSRobert Mustacchi struct i40e_aqc_nvm_oem_post_update_buffer { 19419d26e4fcSRobert Mustacchi u8 str_len; 19429d26e4fcSRobert Mustacchi u8 dev_addr; 19439d26e4fcSRobert Mustacchi __le16 eeprom_addr; 19449d26e4fcSRobert Mustacchi u8 data[36]; 19459d26e4fcSRobert Mustacchi }; 19469d26e4fcSRobert Mustacchi 19479d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 19489d26e4fcSRobert Mustacchi 19499d26e4fcSRobert Mustacchi /* Send to PF command (indirect 0x0801) id is only used by PF 19509d26e4fcSRobert Mustacchi * Send to VF command (indirect 0x0802) id is only used by PF 19519d26e4fcSRobert Mustacchi * Send to Peer PF command (indirect 0x0803) 19529d26e4fcSRobert Mustacchi */ 19539d26e4fcSRobert Mustacchi struct i40e_aqc_pf_vf_message { 19549d26e4fcSRobert Mustacchi __le32 id; 19559d26e4fcSRobert Mustacchi u8 reserved[4]; 19569d26e4fcSRobert Mustacchi __le32 addr_high; 19579d26e4fcSRobert Mustacchi __le32 addr_low; 19589d26e4fcSRobert Mustacchi }; 19599d26e4fcSRobert Mustacchi 19609d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 19619d26e4fcSRobert Mustacchi 19629d26e4fcSRobert Mustacchi /* Alternate structure */ 19639d26e4fcSRobert Mustacchi 19649d26e4fcSRobert Mustacchi /* Direct write (direct 0x0900) 19659d26e4fcSRobert Mustacchi * Direct read (direct 0x0902) 19669d26e4fcSRobert Mustacchi */ 19679d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write { 19689d26e4fcSRobert Mustacchi __le32 address0; 19699d26e4fcSRobert Mustacchi __le32 data0; 19709d26e4fcSRobert Mustacchi __le32 address1; 19719d26e4fcSRobert Mustacchi __le32 data1; 19729d26e4fcSRobert Mustacchi }; 19739d26e4fcSRobert Mustacchi 19749d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 19759d26e4fcSRobert Mustacchi 19769d26e4fcSRobert Mustacchi /* Indirect write (indirect 0x0901) 19779d26e4fcSRobert Mustacchi * Indirect read (indirect 0x0903) 19789d26e4fcSRobert Mustacchi */ 19799d26e4fcSRobert Mustacchi 19809d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_ind_write { 19819d26e4fcSRobert Mustacchi __le32 address; 19829d26e4fcSRobert Mustacchi __le32 length; 19839d26e4fcSRobert Mustacchi __le32 addr_high; 19849d26e4fcSRobert Mustacchi __le32 addr_low; 19859d26e4fcSRobert Mustacchi }; 19869d26e4fcSRobert Mustacchi 19879d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 19889d26e4fcSRobert Mustacchi 19899d26e4fcSRobert Mustacchi /* Done alternate write (direct 0x0904) 19909d26e4fcSRobert Mustacchi * uses i40e_aq_desc 19919d26e4fcSRobert Mustacchi */ 19929d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_write_done { 19939d26e4fcSRobert Mustacchi __le16 cmd_flags; 19949d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 19959d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 19969d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 19979d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 19989d26e4fcSRobert Mustacchi u8 reserved[14]; 19999d26e4fcSRobert Mustacchi }; 20009d26e4fcSRobert Mustacchi 20019d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 20029d26e4fcSRobert Mustacchi 20039d26e4fcSRobert Mustacchi /* Set OEM mode (direct 0x0905) */ 20049d26e4fcSRobert Mustacchi struct i40e_aqc_alternate_set_mode { 20059d26e4fcSRobert Mustacchi __le32 mode; 20069d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_NONE 0 20079d26e4fcSRobert Mustacchi #define I40E_AQ_ALTERNATE_MODE_OEM 1 20089d26e4fcSRobert Mustacchi u8 reserved[12]; 20099d26e4fcSRobert Mustacchi }; 20109d26e4fcSRobert Mustacchi 20119d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 20129d26e4fcSRobert Mustacchi 20139d26e4fcSRobert Mustacchi /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 20149d26e4fcSRobert Mustacchi 20159d26e4fcSRobert Mustacchi /* async events 0x10xx */ 20169d26e4fcSRobert Mustacchi 20179d26e4fcSRobert Mustacchi /* Lan Queue Overflow Event (direct, 0x1001) */ 20189d26e4fcSRobert Mustacchi struct i40e_aqc_lan_overflow { 20199d26e4fcSRobert Mustacchi __le32 prtdcb_rupto; 20209d26e4fcSRobert Mustacchi __le32 otx_ctl; 20219d26e4fcSRobert Mustacchi u8 reserved[8]; 20229d26e4fcSRobert Mustacchi }; 20239d26e4fcSRobert Mustacchi 20249d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 20259d26e4fcSRobert Mustacchi 20269d26e4fcSRobert Mustacchi /* Get LLDP MIB (indirect 0x0A00) */ 20279d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_get_mib { 20289d26e4fcSRobert Mustacchi u8 type; 20299d26e4fcSRobert Mustacchi u8 reserved1; 20309d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 20319d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL 0x0 20329d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_REMOTE 0x1 20339d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 20349d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 20359d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 20369d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 20379d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 20389d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_SHIFT 0x4 20399d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 20409d26e4fcSRobert Mustacchi /* TX pause flags use I40E_AQ_LINK_TX_* above */ 20419d26e4fcSRobert Mustacchi __le16 local_len; 20429d26e4fcSRobert Mustacchi __le16 remote_len; 20439d26e4fcSRobert Mustacchi u8 reserved2[2]; 20449d26e4fcSRobert Mustacchi __le32 addr_high; 20459d26e4fcSRobert Mustacchi __le32 addr_low; 20469d26e4fcSRobert Mustacchi }; 20479d26e4fcSRobert Mustacchi 20489d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 20499d26e4fcSRobert Mustacchi 20509d26e4fcSRobert Mustacchi /* Configure LLDP MIB Change Event (direct 0x0A01) 20519d26e4fcSRobert Mustacchi * also used for the event (with type in the command field) 20529d26e4fcSRobert Mustacchi */ 20539d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_mib { 20549d26e4fcSRobert Mustacchi u8 command; 20559d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 20569d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 20579d26e4fcSRobert Mustacchi u8 reserved[7]; 20589d26e4fcSRobert Mustacchi __le32 addr_high; 20599d26e4fcSRobert Mustacchi __le32 addr_low; 20609d26e4fcSRobert Mustacchi }; 20619d26e4fcSRobert Mustacchi 20629d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 20639d26e4fcSRobert Mustacchi 20649d26e4fcSRobert Mustacchi /* Add LLDP TLV (indirect 0x0A02) 20659d26e4fcSRobert Mustacchi * Delete LLDP TLV (indirect 0x0A04) 20669d26e4fcSRobert Mustacchi */ 20679d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_add_tlv { 20689d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 20699d26e4fcSRobert Mustacchi u8 reserved1[1]; 20709d26e4fcSRobert Mustacchi __le16 len; 20719d26e4fcSRobert Mustacchi u8 reserved2[4]; 20729d26e4fcSRobert Mustacchi __le32 addr_high; 20739d26e4fcSRobert Mustacchi __le32 addr_low; 20749d26e4fcSRobert Mustacchi }; 20759d26e4fcSRobert Mustacchi 20769d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 20779d26e4fcSRobert Mustacchi 20789d26e4fcSRobert Mustacchi /* Update LLDP TLV (indirect 0x0A03) */ 20799d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_update_tlv { 20809d26e4fcSRobert Mustacchi u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 20819d26e4fcSRobert Mustacchi u8 reserved; 20829d26e4fcSRobert Mustacchi __le16 old_len; 20839d26e4fcSRobert Mustacchi __le16 new_offset; 20849d26e4fcSRobert Mustacchi __le16 new_len; 20859d26e4fcSRobert Mustacchi __le32 addr_high; 20869d26e4fcSRobert Mustacchi __le32 addr_low; 20879d26e4fcSRobert Mustacchi }; 20889d26e4fcSRobert Mustacchi 20899d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 20909d26e4fcSRobert Mustacchi 20919d26e4fcSRobert Mustacchi /* Stop LLDP (direct 0x0A05) */ 20929d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop { 20939d26e4fcSRobert Mustacchi u8 command; 20949d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_STOP 0x0 20959d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 20969d26e4fcSRobert Mustacchi u8 reserved[15]; 20979d26e4fcSRobert Mustacchi }; 20989d26e4fcSRobert Mustacchi 20999d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 21009d26e4fcSRobert Mustacchi 21019d26e4fcSRobert Mustacchi /* Start LLDP (direct 0x0A06) */ 21029d26e4fcSRobert Mustacchi 21039d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_start { 21049d26e4fcSRobert Mustacchi u8 command; 21059d26e4fcSRobert Mustacchi #define I40E_AQ_LLDP_AGENT_START 0x1 21069d26e4fcSRobert Mustacchi u8 reserved[15]; 21079d26e4fcSRobert Mustacchi }; 21089d26e4fcSRobert Mustacchi 21099d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 21109d26e4fcSRobert Mustacchi 21119d26e4fcSRobert Mustacchi /* Get CEE DCBX Oper Config (0x0A07) 21129d26e4fcSRobert Mustacchi * uses the generic descriptor struct 21139d26e4fcSRobert Mustacchi * returns below as indirect response 21149d26e4fcSRobert Mustacchi */ 21159d26e4fcSRobert Mustacchi 21169d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 21179d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 21189d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 21199d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 21209d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 21219d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 21229d26e4fcSRobert Mustacchi 21239d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 21249d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 21259d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 21269d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 21279d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 21289d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 21299d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 21309d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 21319d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 21329d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 21339d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 21349d26e4fcSRobert Mustacchi #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 21359d26e4fcSRobert Mustacchi 21369d26e4fcSRobert Mustacchi /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 21379d26e4fcSRobert Mustacchi * word boundary layout issues, which the Linux compilers silently deal 21389d26e4fcSRobert Mustacchi * with by adding padding, making the actual struct larger than designed. 21399d26e4fcSRobert Mustacchi * However, the FW compiler for the NIC is less lenient and complains 21409d26e4fcSRobert Mustacchi * about the struct. Hence, the struct defined here has an extra byte in 21419d26e4fcSRobert Mustacchi * fields reserved3 and reserved4 to directly acknowledge that padding, 21429d26e4fcSRobert Mustacchi * and the new length is used in the length check macro. 21439d26e4fcSRobert Mustacchi */ 21449d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 21459d26e4fcSRobert Mustacchi u8 reserved1; 21469d26e4fcSRobert Mustacchi u8 oper_num_tc; 21479d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 21489d26e4fcSRobert Mustacchi u8 reserved2; 21499d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 21509d26e4fcSRobert Mustacchi u8 oper_pfc_en; 21519d26e4fcSRobert Mustacchi u8 reserved3[2]; 21529d26e4fcSRobert Mustacchi __le16 oper_app_prio; 21539d26e4fcSRobert Mustacchi u8 reserved4[2]; 21549d26e4fcSRobert Mustacchi __le16 tlv_status; 21559d26e4fcSRobert Mustacchi }; 21569d26e4fcSRobert Mustacchi 21579d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 21589d26e4fcSRobert Mustacchi 21599d26e4fcSRobert Mustacchi struct i40e_aqc_get_cee_dcb_cfg_resp { 21609d26e4fcSRobert Mustacchi u8 oper_num_tc; 21619d26e4fcSRobert Mustacchi u8 oper_prio_tc[4]; 21629d26e4fcSRobert Mustacchi u8 oper_tc_bw[8]; 21639d26e4fcSRobert Mustacchi u8 oper_pfc_en; 21649d26e4fcSRobert Mustacchi __le16 oper_app_prio; 21659d26e4fcSRobert Mustacchi __le32 tlv_status; 21669d26e4fcSRobert Mustacchi u8 reserved[12]; 21679d26e4fcSRobert Mustacchi }; 21689d26e4fcSRobert Mustacchi 21699d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 21709d26e4fcSRobert Mustacchi 21719d26e4fcSRobert Mustacchi /* Set Local LLDP MIB (indirect 0x0A08) 21729d26e4fcSRobert Mustacchi * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 21739d26e4fcSRobert Mustacchi */ 21749d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_set_local_mib { 21759d26e4fcSRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 21769d26e4fcSRobert Mustacchi #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 21779d26e4fcSRobert Mustacchi u8 type; 21789d26e4fcSRobert Mustacchi u8 reserved0; 21799d26e4fcSRobert Mustacchi __le16 length; 21809d26e4fcSRobert Mustacchi u8 reserved1[4]; 21819d26e4fcSRobert Mustacchi __le32 address_high; 21829d26e4fcSRobert Mustacchi __le32 address_low; 21839d26e4fcSRobert Mustacchi }; 21849d26e4fcSRobert Mustacchi 21859d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 21869d26e4fcSRobert Mustacchi 21879d26e4fcSRobert Mustacchi /* Stop/Start LLDP Agent (direct 0x0A09) 21889d26e4fcSRobert Mustacchi * Used for stopping/starting specific LLDP agent. e.g. DCBx 21899d26e4fcSRobert Mustacchi */ 21909d26e4fcSRobert Mustacchi struct i40e_aqc_lldp_stop_start_specific_agent { 21919d26e4fcSRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 21929d26e4fcSRobert Mustacchi #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 21939d26e4fcSRobert Mustacchi u8 command; 21949d26e4fcSRobert Mustacchi u8 reserved[15]; 21959d26e4fcSRobert Mustacchi }; 21969d26e4fcSRobert Mustacchi 21979d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 21989d26e4fcSRobert Mustacchi 21999d26e4fcSRobert Mustacchi /* Add Udp Tunnel command and completion (direct 0x0B00) */ 22009d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel { 22019d26e4fcSRobert Mustacchi __le16 udp_port; 22029d26e4fcSRobert Mustacchi u8 reserved0[3]; 22039d26e4fcSRobert Mustacchi u8 protocol_type; 22049d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 22059d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 22069d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 22079d26e4fcSRobert Mustacchi u8 reserved1[10]; 22089d26e4fcSRobert Mustacchi }; 22099d26e4fcSRobert Mustacchi 22109d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 22119d26e4fcSRobert Mustacchi 22129d26e4fcSRobert Mustacchi struct i40e_aqc_add_udp_tunnel_completion { 22139d26e4fcSRobert Mustacchi __le16 udp_port; 22149d26e4fcSRobert Mustacchi u8 filter_entry_index; 22159d26e4fcSRobert Mustacchi u8 multiple_pfs; 22169d26e4fcSRobert Mustacchi #define I40E_AQC_SINGLE_PF 0x0 22179d26e4fcSRobert Mustacchi #define I40E_AQC_MULTIPLE_PFS 0x1 22189d26e4fcSRobert Mustacchi u8 total_filters; 22199d26e4fcSRobert Mustacchi u8 reserved[11]; 22209d26e4fcSRobert Mustacchi }; 22219d26e4fcSRobert Mustacchi 22229d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 22239d26e4fcSRobert Mustacchi 22249d26e4fcSRobert Mustacchi /* remove UDP Tunnel command (0x0B01) */ 22259d26e4fcSRobert Mustacchi struct i40e_aqc_remove_udp_tunnel { 22269d26e4fcSRobert Mustacchi u8 reserved[2]; 22279d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 22289d26e4fcSRobert Mustacchi u8 reserved2[13]; 22299d26e4fcSRobert Mustacchi }; 22309d26e4fcSRobert Mustacchi 22319d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 22329d26e4fcSRobert Mustacchi 22339d26e4fcSRobert Mustacchi struct i40e_aqc_del_udp_tunnel_completion { 22349d26e4fcSRobert Mustacchi __le16 udp_port; 22359d26e4fcSRobert Mustacchi u8 index; /* 0 to 15 */ 22369d26e4fcSRobert Mustacchi u8 multiple_pfs; 22379d26e4fcSRobert Mustacchi u8 total_filters_used; 22389d26e4fcSRobert Mustacchi u8 reserved1[11]; 22399d26e4fcSRobert Mustacchi }; 22409d26e4fcSRobert Mustacchi 22419d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 22429d26e4fcSRobert Mustacchi #ifdef X722_SUPPORT 22439d26e4fcSRobert Mustacchi 22449d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key { 22459d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 22469d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 22479d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 22489d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 22499d26e4fcSRobert Mustacchi __le16 vsi_id; 22509d26e4fcSRobert Mustacchi u8 reserved[6]; 22519d26e4fcSRobert Mustacchi __le32 addr_high; 22529d26e4fcSRobert Mustacchi __le32 addr_low; 22539d26e4fcSRobert Mustacchi }; 22549d26e4fcSRobert Mustacchi 22559d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 22569d26e4fcSRobert Mustacchi 22579d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_key_data { 22589d26e4fcSRobert Mustacchi u8 standard_rss_key[0x28]; 22599d26e4fcSRobert Mustacchi u8 extended_hash_key[0xc]; 22609d26e4fcSRobert Mustacchi }; 22619d26e4fcSRobert Mustacchi 22629d26e4fcSRobert Mustacchi I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 22639d26e4fcSRobert Mustacchi 22649d26e4fcSRobert Mustacchi struct i40e_aqc_get_set_rss_lut { 22659d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 22669d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 22679d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 22689d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 22699d26e4fcSRobert Mustacchi __le16 vsi_id; 22709d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 22719d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 22729d26e4fcSRobert Mustacchi I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 22739d26e4fcSRobert Mustacchi 22749d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 22759d26e4fcSRobert Mustacchi #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 22769d26e4fcSRobert Mustacchi __le16 flags; 22779d26e4fcSRobert Mustacchi u8 reserved[4]; 22789d26e4fcSRobert Mustacchi __le32 addr_high; 22799d26e4fcSRobert Mustacchi __le32 addr_low; 22809d26e4fcSRobert Mustacchi }; 22819d26e4fcSRobert Mustacchi 22829d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 22839d26e4fcSRobert Mustacchi #endif 22849d26e4fcSRobert Mustacchi 22859d26e4fcSRobert Mustacchi /* tunnel key structure 0x0B10 */ 22869d26e4fcSRobert Mustacchi 22879d26e4fcSRobert Mustacchi struct i40e_aqc_tunnel_key_structure { 22889d26e4fcSRobert Mustacchi u8 key1_off; 22899d26e4fcSRobert Mustacchi u8 key2_off; 22909d26e4fcSRobert Mustacchi u8 key1_len; /* 0 to 15 */ 22919d26e4fcSRobert Mustacchi u8 key2_len; /* 0 to 15 */ 22929d26e4fcSRobert Mustacchi u8 flags; 22939d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 22949d26e4fcSRobert Mustacchi /* response flags */ 22959d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 22969d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 22979d26e4fcSRobert Mustacchi #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 22989d26e4fcSRobert Mustacchi u8 network_key_index; 22999d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 23009d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 23019d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 23029d26e4fcSRobert Mustacchi #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 23039d26e4fcSRobert Mustacchi u8 reserved[10]; 23049d26e4fcSRobert Mustacchi }; 23059d26e4fcSRobert Mustacchi 23069d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 23079d26e4fcSRobert Mustacchi 23089d26e4fcSRobert Mustacchi /* OEM mode commands (direct 0xFE0x) */ 23099d26e4fcSRobert Mustacchi struct i40e_aqc_oem_param_change { 23109d26e4fcSRobert Mustacchi __le32 param_type; 23119d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 23129d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 23139d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_PARAM_MAC 2 23149d26e4fcSRobert Mustacchi __le32 param_value1; 23159d26e4fcSRobert Mustacchi __le16 param_value2; 23169d26e4fcSRobert Mustacchi u8 reserved[6]; 23179d26e4fcSRobert Mustacchi }; 23189d26e4fcSRobert Mustacchi 23199d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 23209d26e4fcSRobert Mustacchi 23219d26e4fcSRobert Mustacchi struct i40e_aqc_oem_state_change { 23229d26e4fcSRobert Mustacchi __le32 state; 23239d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 23249d26e4fcSRobert Mustacchi #define I40E_AQ_OEM_STATE_LINK_UP 0x1 23259d26e4fcSRobert Mustacchi u8 reserved[12]; 23269d26e4fcSRobert Mustacchi }; 23279d26e4fcSRobert Mustacchi 23289d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 23299d26e4fcSRobert Mustacchi 23309d26e4fcSRobert Mustacchi /* Initialize OCSD (0xFE02, direct) */ 23319d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocsd_initialize { 23329d26e4fcSRobert Mustacchi u8 type_status; 23339d26e4fcSRobert Mustacchi u8 reserved1[3]; 23349d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_high; 23359d26e4fcSRobert Mustacchi __le32 ocsd_memory_block_addr_low; 23369d26e4fcSRobert Mustacchi __le32 requested_update_interval; 23379d26e4fcSRobert Mustacchi }; 23389d26e4fcSRobert Mustacchi 23399d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 23409d26e4fcSRobert Mustacchi 23419d26e4fcSRobert Mustacchi /* Initialize OCBB (0xFE03, direct) */ 23429d26e4fcSRobert Mustacchi struct i40e_aqc_opc_oem_ocbb_initialize { 23439d26e4fcSRobert Mustacchi u8 type_status; 23449d26e4fcSRobert Mustacchi u8 reserved1[3]; 23459d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_high; 23469d26e4fcSRobert Mustacchi __le32 ocbb_memory_block_addr_low; 23479d26e4fcSRobert Mustacchi u8 reserved2[4]; 23489d26e4fcSRobert Mustacchi }; 23499d26e4fcSRobert Mustacchi 23509d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 23519d26e4fcSRobert Mustacchi 23529d26e4fcSRobert Mustacchi /* debug commands */ 23539d26e4fcSRobert Mustacchi 23549d26e4fcSRobert Mustacchi /* get device id (0xFF00) uses the generic structure */ 23559d26e4fcSRobert Mustacchi 23569d26e4fcSRobert Mustacchi /* set test more (0xFF01, internal) */ 23579d26e4fcSRobert Mustacchi 23589d26e4fcSRobert Mustacchi struct i40e_acq_set_test_mode { 23599d26e4fcSRobert Mustacchi u8 mode; 23609d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_PARTIAL 0 23619d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_FULL 1 23629d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_NVM 2 23639d26e4fcSRobert Mustacchi u8 reserved[3]; 23649d26e4fcSRobert Mustacchi u8 command; 23659d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_OPEN 0 23669d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_CLOSE 1 23679d26e4fcSRobert Mustacchi #define I40E_AQ_TEST_INC 2 23689d26e4fcSRobert Mustacchi u8 reserved2[3]; 23699d26e4fcSRobert Mustacchi __le32 address_high; 23709d26e4fcSRobert Mustacchi __le32 address_low; 23719d26e4fcSRobert Mustacchi }; 23729d26e4fcSRobert Mustacchi 23739d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 23749d26e4fcSRobert Mustacchi 23759d26e4fcSRobert Mustacchi /* Debug Read Register command (0xFF03) 23769d26e4fcSRobert Mustacchi * Debug Write Register command (0xFF04) 23779d26e4fcSRobert Mustacchi */ 23789d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_read_write { 23799d26e4fcSRobert Mustacchi __le32 reserved; 23809d26e4fcSRobert Mustacchi __le32 address; 23819d26e4fcSRobert Mustacchi __le32 value_high; 23829d26e4fcSRobert Mustacchi __le32 value_low; 23839d26e4fcSRobert Mustacchi }; 23849d26e4fcSRobert Mustacchi 23859d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 23869d26e4fcSRobert Mustacchi 23879d26e4fcSRobert Mustacchi /* Scatter/gather Reg Read (indirect 0xFF05) 23889d26e4fcSRobert Mustacchi * Scatter/gather Reg Write (indirect 0xFF06) 23899d26e4fcSRobert Mustacchi */ 23909d26e4fcSRobert Mustacchi 23919d26e4fcSRobert Mustacchi /* i40e_aq_desc is used for the command */ 23929d26e4fcSRobert Mustacchi struct i40e_aqc_debug_reg_sg_element_data { 23939d26e4fcSRobert Mustacchi __le32 address; 23949d26e4fcSRobert Mustacchi __le32 value; 23959d26e4fcSRobert Mustacchi }; 23969d26e4fcSRobert Mustacchi 23979d26e4fcSRobert Mustacchi /* Debug Modify register (direct 0xFF07) */ 23989d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_reg { 23999d26e4fcSRobert Mustacchi __le32 address; 24009d26e4fcSRobert Mustacchi __le32 value; 24019d26e4fcSRobert Mustacchi __le32 clear_mask; 24029d26e4fcSRobert Mustacchi __le32 set_mask; 24039d26e4fcSRobert Mustacchi }; 24049d26e4fcSRobert Mustacchi 24059d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 24069d26e4fcSRobert Mustacchi 24079d26e4fcSRobert Mustacchi /* dump internal data (0xFF08, indirect) */ 24089d26e4fcSRobert Mustacchi 24099d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_AUX 0 24109d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 24119d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_TXSCHED 2 24129d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_HMC 3 24139d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC0 4 24149d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC1 5 24159d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC2 6 24169d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_MAC3 7 24179d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_DCB 8 24189d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 24199d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 24209d26e4fcSRobert Mustacchi #define I40E_AQ_CLUSTER_ID_ALTRAM 11 24219d26e4fcSRobert Mustacchi 24229d26e4fcSRobert Mustacchi struct i40e_aqc_debug_dump_internals { 24239d26e4fcSRobert Mustacchi u8 cluster_id; 24249d26e4fcSRobert Mustacchi u8 table_id; 24259d26e4fcSRobert Mustacchi __le16 data_size; 24269d26e4fcSRobert Mustacchi __le32 idx; 24279d26e4fcSRobert Mustacchi __le32 address_high; 24289d26e4fcSRobert Mustacchi __le32 address_low; 24299d26e4fcSRobert Mustacchi }; 24309d26e4fcSRobert Mustacchi 24319d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 24329d26e4fcSRobert Mustacchi 24339d26e4fcSRobert Mustacchi struct i40e_aqc_debug_modify_internals { 24349d26e4fcSRobert Mustacchi u8 cluster_id; 24359d26e4fcSRobert Mustacchi u8 cluster_specific_params[7]; 24369d26e4fcSRobert Mustacchi __le32 address_high; 24379d26e4fcSRobert Mustacchi __le32 address_low; 24389d26e4fcSRobert Mustacchi }; 24399d26e4fcSRobert Mustacchi 24409d26e4fcSRobert Mustacchi I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 24419d26e4fcSRobert Mustacchi 24429d26e4fcSRobert Mustacchi #endif 2443