13dec9fcdSqs /*
23dec9fcdSqs  * CDDL HEADER START
33dec9fcdSqs  *
43dec9fcdSqs  * The contents of this file are subject to the terms of the
53dec9fcdSqs  * Common Development and Distribution License (the "License").
63dec9fcdSqs  * You may not use this file except in compliance with the License.
73dec9fcdSqs  *
83dec9fcdSqs  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
93dec9fcdSqs  * or http://www.opensolaris.org/os/licensing.
103dec9fcdSqs  * See the License for the specific language governing permissions
113dec9fcdSqs  * and limitations under the License.
123dec9fcdSqs  *
133dec9fcdSqs  * When distributing Covered Code, include this CDDL HEADER in each
143dec9fcdSqs  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
153dec9fcdSqs  * If applicable, add the following below this CDDL HEADER, with the
163dec9fcdSqs  * fields enclosed by brackets "[]" replaced with your own identifying
173dec9fcdSqs  * information: Portions Copyright [yyyy] [name of copyright owner]
183dec9fcdSqs  *
193dec9fcdSqs  * CDDL HEADER END
203dec9fcdSqs  */
213dec9fcdSqs /*
2241307000SQiyan Sun - Sun Microsystems - San Diego United States  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
233dec9fcdSqs  * Use is subject to license terms.
243dec9fcdSqs  */
263dec9fcdSqs #ifndef	_SYS_HXGE_HXGE_RXDMA_H
273dec9fcdSqs #define	_SYS_HXGE_HXGE_RXDMA_H
293dec9fcdSqs #ifdef	__cplusplus
303dec9fcdSqs extern "C" {
313dec9fcdSqs #endif
333dec9fcdSqs #include <hxge_rdc_hw.h>
343dec9fcdSqs #include <hpi_rxdma.h>
3641307000SQiyan Sun - Sun Microsystems - San Diego United States #define	RXDMA_CK_DIV_DEFAULT		25000	/* 84 usec */
37676f0400SMichael Speer #define	RXDMA_RCR_PTHRES_DEFAULT	0x1
38e5d97391SQiyan Sun - Sun Microsystems - San Diego United States #define	RXDMA_RCR_TO_DEFAULT		0x1
393dec9fcdSqs #define	RXDMA_HDR_SIZE_DEFAULT		2
403dec9fcdSqs #define	RXDMA_HDR_SIZE_FULL		6	/* entire header of 6B */
423dec9fcdSqs /*
433dec9fcdSqs  * Receive Completion Ring (RCR)
443dec9fcdSqs  */
453dec9fcdSqs #define	RCR_PKT_BUF_ADDR_SHIFT		0			/* bit 37:0 */
463dec9fcdSqs #define	RCR_PKT_BUF_ADDR_SHIFT_FULL	6	/* fulll buffer address */
473dec9fcdSqs #define	RCR_PKT_BUF_ADDR_MASK		0x0000003FFFFFFFFFULL
483dec9fcdSqs #define	RCR_PKTBUFSZ_SHIFT		38			/* bit 39:38 */
493dec9fcdSqs #define	RCR_PKTBUFSZ_MASK		0x000000C000000000ULL
503dec9fcdSqs #define	RCR_L2_LEN_SHIFT		40			/* bit 53:40 */
513dec9fcdSqs #define	RCR_L2_LEN_MASK			0x003fff0000000000ULL
523dec9fcdSqs #define	RCR_ERROR_SHIFT			54			/* bit 57:54 */
533dec9fcdSqs #define	RCR_ERROR_MASK			0x03C0000000000000ULL
543dec9fcdSqs #define	RCR_PKT_TYPE_SHIFT		61			/* bit 62:61 */
553dec9fcdSqs #define	RCR_PKT_TYPE_MASK		0x6000000000000000ULL
563dec9fcdSqs #define	RCR_MULTI_SHIFT			63			/* bit 63 */
573dec9fcdSqs #define	RCR_MULTI_MASK			0x8000000000000000ULL
593dec9fcdSqs #define	RCR_PKTBUFSZ_0			0x00
603dec9fcdSqs #define	RCR_PKTBUFSZ_1			0x01
613dec9fcdSqs #define	RCR_PKTBUFSZ_2			0x02
623dec9fcdSqs #define	RCR_SINGLE_BLOCK		0x03
63*f043ebedSMichael Speer #define	N_PKTSIZE_TYPES			0x04
653dec9fcdSqs #define	RCR_NO_ERROR			0x0
663dec9fcdSqs #define	RCR_CTRL_FIFO_DED		0x1
673dec9fcdSqs #define	RCR_DATA_FIFO_DED		0x2
683dec9fcdSqs #define	RCR_ERROR_RESERVE		0x4
703dec9fcdSqs #define	RCR_PKT_IS_TCP			0x2000000000000000ULL
713dec9fcdSqs #define	RCR_PKT_IS_UDP			0x4000000000000000ULL
723dec9fcdSqs #define	RCR_PKT_IS_SCTP			0x6000000000000000ULL
743dec9fcdSqs #define	RDC_INT_MASK_RBRFULL_SHIFT	34
753dec9fcdSqs #define	RDC_INT_MASK_RBRFULL_MASK	0x0000000400000000ULL
763dec9fcdSqs #define	RDC_INT_MASK_RBREMPTY_SHIFT	35
773dec9fcdSqs #define	RDC_INT_MASK_RBREMPTY_MASK	0x0000000800000000ULL
783dec9fcdSqs #define	RDC_INT_MASK_RCRFULL_SHIFT	36
793dec9fcdSqs #define	RDC_INT_MASK_RCRFULL_MASK	0x0000001000000000ULL
803dec9fcdSqs #define	RDC_INT_MASK_RCRSH_FULL_SHIFT	39
813dec9fcdSqs #define	RDC_INT_MASK_RCRSH_FULL_MASK	0x0000008000000000ULL
823dec9fcdSqs #define	RDC_INT_MASK_RBR_PRE_EMPTY_SHIFT	40
833dec9fcdSqs #define	RDC_INT_MASK_RBR_PRE_EMPTY_MASK	0x0000010000000000ULL
843dec9fcdSqs #define	RDC_INT_MASK_RBR_PRE_PAR_SHIFT	43
853dec9fcdSqs #define	RDC_INT_MASK_RBR_PRE_PAR_MASK	0x0000080000000000ULL
863dec9fcdSqs #define	RDC_INT_MASK_RCR_SHA_PAR_SHIFT	44
873dec9fcdSqs #define	RDC_INT_MASK_RCR_SHA_PAR_MASK	0x0000100000000000ULL
883dec9fcdSqs #define	RDC_INT_MASK_RCRTO_SHIFT	45
893dec9fcdSqs #define	RDC_INT_MASK_RCRTO_MASK		0x0000200000000000ULL
903dec9fcdSqs #define	RDC_INT_MASK_THRES_SHIFT	46
913dec9fcdSqs #define	RDC_INT_MASK_THRES_MASK		0x0000400000000000ULL
923dec9fcdSqs #define	RDC_INT_MASK_PEU_ERR_SHIFT	52
933dec9fcdSqs #define	RDC_INT_MASK_PEU_ERR_MASK	0x0010000000000000ULL
943dec9fcdSqs #define	RDC_INT_MASK_RBR_CPL_SHIFT	53
953dec9fcdSqs #define	RDC_INT_MASK_RBR_CPL_MASK	0x0020000000000000ULL
963dec9fcdSqs #define	RDC_INT_MASK_ALL	(RDC_INT_MASK_RBRFULL_MASK |		\
973dec9fcdSqs 				RDC_INT_MASK_RBREMPTY_MASK |		\
983dec9fcdSqs 				RDC_INT_MASK_RCRFULL_MASK |		\
993dec9fcdSqs 				RDC_INT_MASK_RCRSH_FULL_MASK |		\
1003dec9fcdSqs 				RDC_INT_MASK_RBR_PRE_EMPTY_MASK |	\
1013dec9fcdSqs 				RDC_INT_MASK_RBR_PRE_PAR_MASK |		\
1023dec9fcdSqs 				RDC_INT_MASK_RCR_SHA_PAR_MASK |		\
1033dec9fcdSqs 				RDC_INT_MASK_RCRTO_MASK |		\
1043dec9fcdSqs 				RDC_INT_MASK_THRES_MASK |		\
1053dec9fcdSqs 				RDC_INT_MASK_PEU_ERR_MASK |		\
1063dec9fcdSqs 				RDC_INT_MASK_RBR_CPL_MASK)
1083dec9fcdSqs #define	RDC_STAT_PKTREAD_SHIFT			0	/* WO, bit 15:0 */
1093dec9fcdSqs #define	RDC_STAT_PKTREAD_MASK			0x000000000000ffffULL
1103dec9fcdSqs #define	RDC_STAT_PTRREAD_SHIFT			16	/* WO, bit 31:16 */
1113dec9fcdSqs #define	RDC_STAT_PTRREAD_MASK			0x00000000FFFF0000ULL
1133dec9fcdSqs #define	RDC_STAT_RBRFULL_SHIFT			34	/* RO, bit 34 */
1143dec9fcdSqs #define	RDC_STAT_RBRFULL			0x0000000400000000ULL
1153dec9fcdSqs #define	RDC_STAT_RBRFULL_MASK			0x0000000400000000ULL
1163dec9fcdSqs #define	RDC_STAT_RBREMPTY_SHIFT			35	/* RW1C, bit 35 */
1173dec9fcdSqs #define	RDC_STAT_RBREMPTY			0x0000000800000000ULL
1183dec9fcdSqs #define	RDC_STAT_RBREMPTY_MASK			0x0000000800000000ULL
1193dec9fcdSqs #define	RDC_STAT_RCR_FULL_SHIFT			36	/* RW1C, bit 36 */
1203dec9fcdSqs #define	RDC_STAT_RCR_FULL			0x0000001000000000ULL
1213dec9fcdSqs #define	RDC_STAT_RCR_FULL_MASK			0x0000001000000000ULL
1233dec9fcdSqs #define	RDC_STAT_RCR_SHDW_FULL_SHIFT 		39	/* RW1C, bit 39 */
1243dec9fcdSqs #define	RDC_STAT_RCR_SHDW_FULL 			0x0000008000000000ULL
1253dec9fcdSqs #define	RDC_STAT_RCR_SHDW_FULL_MASK 		0x0000008000000000ULL
1263dec9fcdSqs #define	RDC_STAT_RBR_PRE_EMPTY_SHIFT 		40	/* RO, bit 40 */
1273dec9fcdSqs #define	RDC_STAT_RBR_PRE_EMPTY 			0x0000010000000000ULL
1283dec9fcdSqs #define	RDC_STAT_RBR_PRE_EMPTY_MASK  		0x0000010000000000ULL
1303dec9fcdSqs #define	RDC_STAT_RBR_PRE_PAR_SHIFT 		43	/* RO, bit 43 */
1313dec9fcdSqs #define	RDC_STAT_RBR_PRE_PAR 			0x0000080000000000ULL
1323dec9fcdSqs #define	RDC_STAT_RBR_PRE_PAR_MASK  		0x0000080000000000ULL
1333dec9fcdSqs #define	RDC_STAT_RCR_SHA_PAR_SHIFT 		44	/* RO, bit 44 */
1343dec9fcdSqs #define	RDC_STAT_RCR_SHA_PAR 			0x0000100000000000ULL
1353dec9fcdSqs #define	RDC_STAT_RCR_SHA_PAR_MASK  		0x0000100000000000ULL
1373dec9fcdSqs #define	RDC_STAT_RCR_TO_SHIFT			45	/* RW1C, bit 45 */
1383dec9fcdSqs #define	RDC_STAT_RCR_TO				0x0000200000000000ULL
1393dec9fcdSqs #define	RDC_STAT_RCR_TO_MASK			0x0000200000000000ULL
1403dec9fcdSqs #define	RDC_STAT_RCR_THRES_SHIFT		46	/* RO, bit 46 */
1413dec9fcdSqs #define	RDC_STAT_RCR_THRES			0x0000400000000000ULL
1423dec9fcdSqs #define	RDC_STAT_RCR_THRES_MASK			0x0000400000000000ULL
1433dec9fcdSqs #define	RDC_STAT_RCR_MEX_SHIFT			47	/* RW, bit 47 */
1443dec9fcdSqs #define	RDC_STAT_RCR_MEX			0x0000800000000000ULL
1453dec9fcdSqs #define	RDC_STAT_RCR_MEX_MASK			0x0000800000000000ULL
1473dec9fcdSqs #define	RDC_STAT_PEU_ERR_SHIFT			52	/* RO, bit 52 */
1483dec9fcdSqs #define	RDC_STAT_PEU_ERR			0x0010000000000000ULL
1493dec9fcdSqs #define	RDC_STAT_PEU_ERR_MASK			0x0010000000000000ULL
1513dec9fcdSqs #define	RDC_STAT_RBR_CPL_SHIFT			53	/* RO, bit 53 */
1523dec9fcdSqs #define	RDC_STAT_RBR_CPL			0x0020000000000000ULL
1533dec9fcdSqs #define	RDC_STAT_RBR_CPL_MASK			0x0020000000000000ULL
1553dec9fcdSqs #define	RDC_STAT_ERROR 				RDC_INT_MASK_ALL
1573dec9fcdSqs /* the following are write 1 to clear bits */
1583dec9fcdSqs #define	RDC_STAT_WR1C		(RDC_STAT_RBREMPTY | 		\
1593dec9fcdSqs 				RDC_STAT_RCR_SHDW_FULL | 	\
1603dec9fcdSqs 				RDC_STAT_RBR_PRE_EMPTY | 	\
1613dec9fcdSqs 				RDC_STAT_RBR_PRE_PAR |		\
1623dec9fcdSqs 				RDC_STAT_RCR_SHA_PAR |		\
1633dec9fcdSqs 				RDC_STAT_RBR_CPL |		\
1643dec9fcdSqs 				RDC_STAT_PEU_ERR)
1663dec9fcdSqs typedef union _rcr_entry_t {
1673dec9fcdSqs 	uint64_t value;
1683dec9fcdSqs 	struct {
1693dec9fcdSqs #if defined(_BIG_ENDIAN)
170fe930412Sqs 		uint32_t multi:1;
171fe930412Sqs 		uint32_t pkt_type:2;
172fe930412Sqs 		uint32_t reserved:3;
173fe930412Sqs 		uint32_t error:4;
174fe930412Sqs 		uint32_t l2_len:14;
175fe930412Sqs 		uint32_t pktbufsz:2;
176fe930412Sqs 		uint32_t pkt_buf_addr:6;
177fe930412Sqs 		uint32_t pkt_buf_addr_l:32;
1783dec9fcdSqs #else
179fe930412Sqs 		uint32_t pkt_buf_addr_l:32;
180fe930412Sqs 		uint32_t pkt_buf_addr:6;
181fe930412Sqs 		uint32_t pktbufsz:2;
182fe930412Sqs 		uint32_t l2_len:14;
183fe930412Sqs 		uint32_t error:4;
184fe930412Sqs 		uint32_t reserved:3;
185fe930412Sqs 		uint32_t pkt_type:2;
186fe930412Sqs 		uint32_t multi:1;
1873dec9fcdSqs #endif
1883dec9fcdSqs 	} bits;
1893dec9fcdSqs } rcr_entry_t, *p_rcr_entry_t;
1913dec9fcdSqs #define	RX_DMA_MAILBOX_BYTE_LENGTH	64
1933dec9fcdSqs typedef struct _rxdma_mailbox_t {
1943dec9fcdSqs 	rdc_stat_t		rxdma_ctl_stat;		/* 8 bytes */
1953dec9fcdSqs 	rdc_rbr_qlen_t		rbr_stat;		/* 8 bytes */
1963dec9fcdSqs 	rdc_rbr_head_t		rbr_hdh;		/* 8 bytes */
197dc10a9c2SMichael Speer 	uint64_t		resv_1;
1983dec9fcdSqs 	rdc_rcr_tail_t		rcrstat_c;		/* 8 bytes */
199dc10a9c2SMichael Speer 	uint64_t		resv_2;
2003dec9fcdSqs 	rdc_rcr_qlen_t		rcrstat_a;		/* 8 bytes */
201dc10a9c2SMichael Speer 	uint64_t		resv_3;
2023dec9fcdSqs } rxdma_mailbox_t, *p_rxdma_mailbox_t;
2043dec9fcdSqs /*
2053dec9fcdSqs  * hardware workarounds: kick 16 (was 8 before)
2063dec9fcdSqs  */
2073dec9fcdSqs #define	HXGE_RXDMA_POST_BATCH		16
2093dec9fcdSqs #define	RXBUF_START_ADDR(a, index, bsize)	((a & (index * bsize))
2103dec9fcdSqs #define	RXBUF_OFFSET_FROM_START(a, start)	(start - a)
2113dec9fcdSqs #define	RXBUF_64B_ALIGNED		64
2133dec9fcdSqs #define	HXGE_RXBUF_EXTRA		34
2153dec9fcdSqs /*
2163dec9fcdSqs  * Receive buffer thresholds and buffer types
2173dec9fcdSqs  */
2183dec9fcdSqs #define	HXGE_RX_BCOPY_SCALE	8	/* use 1/8 as lowest granularity */
2203dec9fcdSqs typedef enum  {
2213dec9fcdSqs 	HXGE_RX_COPY_ALL = 0,		/* do bcopy on every packet	 */
2223dec9fcdSqs 	HXGE_RX_COPY_1,			/* bcopy on 1/8 of buffer posted */
2233dec9fcdSqs 	HXGE_RX_COPY_2,			/* bcopy on 2/8 of buffer posted */
2243dec9fcdSqs 	HXGE_RX_COPY_3,			/* bcopy on 3/8 of buffer posted */
2253dec9fcdSqs 	HXGE_RX_COPY_4,			/* bcopy on 4/8 of buffer posted */
2263dec9fcdSqs 	HXGE_RX_COPY_5,			/* bcopy on 5/8 of buffer posted */
2273dec9fcdSqs 	HXGE_RX_COPY_6,			/* bcopy on 6/8 of buffer posted */
2283dec9fcdSqs 	HXGE_RX_COPY_7,			/* bcopy on 7/8 of buffer posted */
2293dec9fcdSqs 	HXGE_RX_COPY_NONE		/* don't do bcopy at all	 */
2303dec9fcdSqs } hxge_rxbuf_threshold_t;
2323dec9fcdSqs typedef enum  {
2333dec9fcdSqs 	HXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0,  /* bcopy buffer size 0 (small) */
2343dec9fcdSqs 	HXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1,  /* bcopy buffer size 1 (medium) */
2353dec9fcdSqs 	HXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2	  /* bcopy buffer size 2 (large) */
2363dec9fcdSqs } hxge_rxbuf_type_t;
2383dec9fcdSqs typedef	struct _rdc_errlog {
2393dec9fcdSqs 	rdc_pref_par_log_t	pre_par;
2403dec9fcdSqs 	rdc_pref_par_log_t	sha_par;
2413dec9fcdSqs 	uint8_t			compl_err_type;
2423dec9fcdSqs } rdc_errlog_t;
2443dec9fcdSqs /*
2453dec9fcdSqs  * Receive  Statistics.
2463dec9fcdSqs  */
2473dec9fcdSqs typedef struct _hxge_rx_ring_stats_t {
2483dec9fcdSqs 	uint64_t	ipackets;
2493dec9fcdSqs 	uint64_t	ibytes;
2503dec9fcdSqs 	uint32_t	ierrors;
2513dec9fcdSqs 	uint32_t	jumbo_pkts;
2533dec9fcdSqs 	/*
2543dec9fcdSqs 	 * Error event stats.
2553dec9fcdSqs 	 */
2563dec9fcdSqs 	uint32_t	rcr_unknown_err;
2573dec9fcdSqs 	uint32_t	ctrl_fifo_ecc_err;
2583dec9fcdSqs 	uint32_t	data_fifo_ecc_err;
2593dec9fcdSqs 	uint32_t	rbr_tmout;		/* rbr_cpl_to */
2603dec9fcdSqs 	uint32_t 	peu_resp_err;		/* peu_resp_err */
2613dec9fcdSqs 	uint32_t 	rcr_sha_par;		/* rcr_shadow_par_err */
2623dec9fcdSqs 	uint32_t 	rbr_pre_par;		/* rbr_prefetch_par_err */
2633dec9fcdSqs 	uint32_t 	rbr_pre_empty;		/* rbr_pre_empty */
2643dec9fcdSqs 	uint32_t 	rcr_shadow_full;	/* rcr_shadow_full */
2653dec9fcdSqs 	uint32_t 	rcrfull;		/* rcr_full */
2663dec9fcdSqs 	uint32_t 	rbr_empty;		/* rbr_empty */
267b83cd2c3SMichael Speer 	uint32_t 	rbr_empty_fail;		/* rbr_empty_fail */
2681c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States 	uint32_t 	rbr_empty_restore;	/* rbr_empty_restore */
2693dec9fcdSqs 	uint32_t 	rbrfull;		/* rbr_full */
2708ad8db65SMichael Speer 	/*
2718ad8db65SMichael Speer 	 * RCR invalids: when processing RCR entries, can
2728ad8db65SMichael Speer 	 * run into invalid RCR entries.  This counter provides
2738ad8db65SMichael Speer 	 * a means to account for invalid RCR entries.
2748ad8db65SMichael Speer 	 */
2758ad8db65SMichael Speer 	uint32_t 	rcr_invalids;		/* rcr invalids */
2763dec9fcdSqs 	uint32_t 	rcr_to;			/* rcr_to */
2773dec9fcdSqs 	uint32_t 	rcr_thres;		/* rcr_thres */
278fd9489ceSQiyan Sun - Sun Microsystems - San Diego United States 	/* Packets dropped in order to prevent rbr_empty condition */
279fd9489ceSQiyan Sun - Sun Microsystems - San Diego United States 	uint32_t 	pkt_drop;
2803dec9fcdSqs 	rdc_errlog_t	errlog;
2813dec9fcdSqs } hxge_rx_ring_stats_t, *p_hxge_rx_ring_stats_t;
2833dec9fcdSqs typedef struct _hxge_rdc_sys_stats {
2843dec9fcdSqs 	uint32_t	ctrl_fifo_sec;
2853dec9fcdSqs 	uint32_t	ctrl_fifo_ded;
2863dec9fcdSqs 	uint32_t	data_fifo_sec;
2873dec9fcdSqs 	uint32_t	data_fifo_ded;
2883dec9fcdSqs } hxge_rdc_sys_stats_t, *p_hxge_rdc_sys_stats_t;
2903dec9fcdSqs typedef struct _rx_msg_t {
2913dec9fcdSqs 	hxge_os_dma_common_t	buf_dma;
2923dec9fcdSqs 	hxge_os_mutex_t 	lock;
2933dec9fcdSqs 	struct _hxge_t		*hxgep;
2943dec9fcdSqs 	struct _rx_rbr_ring_t	*rx_rbr_p;
2953dec9fcdSqs 	boolean_t 		free;
2963dec9fcdSqs 	uint32_t 		ref_cnt;
2973dec9fcdSqs 	hxge_os_frtn_t 		freeb;
2983dec9fcdSqs 	size_t 			block_size;
2993dec9fcdSqs 	uint32_t		block_index;
3003dec9fcdSqs 	uint32_t 		pkt_buf_size;
3013dec9fcdSqs 	uint32_t 		pkt_buf_size_code;
3023dec9fcdSqs 	uint32_t		cur_usage_cnt;
3033dec9fcdSqs 	uint32_t		max_usage_cnt;
3043dec9fcdSqs 	uchar_t			*buffer;
3053dec9fcdSqs 	uint32_t 		pri;
3063dec9fcdSqs 	uint32_t 		shifted_addr;
3073dec9fcdSqs 	boolean_t		use_buf_pool;
3083dec9fcdSqs 	p_mblk_t 		rx_mblk_p;
3093dec9fcdSqs 	boolean_t		rx_use_bcopy;
3103dec9fcdSqs } rx_msg_t, *p_rx_msg_t;
3123dec9fcdSqs /* Receive Completion Ring */
3133dec9fcdSqs typedef struct _rx_rcr_ring_t {
3143dec9fcdSqs 	hxge_os_dma_common_t	rcr_desc;
3153dec9fcdSqs 	struct _hxge_t		*hxgep;
3161ed83081SMichael Speer 	mac_ring_handle_t   	rcr_mac_handle;
3171ed83081SMichael Speer 	uint64_t		rcr_gen_num;
3181ed83081SMichael Speer 	boolean_t		poll_flag;
3191ed83081SMichael Speer 	p_hxge_ldv_t		ldvp;
3201ed83081SMichael Speer 	p_hxge_ldg_t		ldgp;
3223dec9fcdSqs 	p_hxge_rx_ring_stats_t	rdc_stats;	/* pointer to real kstats */
3243dec9fcdSqs 	rdc_rcr_cfg_a_t		rcr_cfga;
3253dec9fcdSqs 	rdc_rcr_cfg_b_t		rcr_cfgb;
3273dec9fcdSqs 	hxge_os_mutex_t 	lock;
3283dec9fcdSqs 	uint16_t		index;
3293dec9fcdSqs 	uint16_t		rdc;
3303dec9fcdSqs 	boolean_t		full_hdr_flag;	 /* 1: 18 bytes header */
3313dec9fcdSqs 	uint16_t		sw_priv_hdr_len; /* 0 - 192 bytes (SW) */
3323dec9fcdSqs 	uint32_t 		comp_size;	 /* # of RCR entries */
3333dec9fcdSqs 	uint64_t		rcr_addr;
3343dec9fcdSqs 	uint_t 			comp_wrap_mask;
3353dec9fcdSqs 	uint_t 			comp_rd_index;
3363dec9fcdSqs 	uint_t 			comp_wt_index;
3383dec9fcdSqs 	p_rcr_entry_t		rcr_desc_first_p;
3393dec9fcdSqs 	p_rcr_entry_t		rcr_desc_first_pp;
3403dec9fcdSqs 	p_rcr_entry_t		rcr_desc_last_p;
3413dec9fcdSqs 	p_rcr_entry_t		rcr_desc_last_pp;
3433dec9fcdSqs 	p_rcr_entry_t		rcr_desc_rd_head_p;	/* software next read */
3443dec9fcdSqs 	p_rcr_entry_t		rcr_desc_rd_head_pp;
345a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	uint64_t		rcr_tail_begin;
3473dec9fcdSqs 	struct _rx_rbr_ring_t	*rx_rbr_p;
3483dec9fcdSqs 	uint32_t		intr_timeout;
3493dec9fcdSqs 	uint32_t		intr_threshold;
3503dec9fcdSqs 	uint32_t		rcvd_pkt_bytes; /* Received bytes of a packet */
3513dec9fcdSqs } rx_rcr_ring_t, *p_rx_rcr_ring_t;
3543dec9fcdSqs /* Buffer index information */
3553dec9fcdSqs typedef struct _rxbuf_index_info_t {
3563dec9fcdSqs 	uint32_t		buf_index;
3573dec9fcdSqs 	uint32_t		start_index;
3583dec9fcdSqs 	uint32_t		buf_size;
3593dec9fcdSqs 	uint64_t		dvma_addr;
3603dec9fcdSqs 	uint64_t		kaddr;
3613dec9fcdSqs } rxbuf_index_info_t, *p_rxbuf_index_info_t;
3633dec9fcdSqs /* Buffer index information */
3653dec9fcdSqs typedef struct _rxring_info_t {
366*f043ebedSMichael Speer 	uint32_t		hint[N_PKTSIZE_TYPES];
3673dec9fcdSqs 	uint32_t		block_size_mask;
3683dec9fcdSqs 	uint16_t		max_iterations;
3693dec9fcdSqs 	rxbuf_index_info_t	buffer[HXGE_DMA_BLOCK];
3703dec9fcdSqs } rxring_info_t, *p_rxring_info_t;
3733dec9fcdSqs typedef enum {
3743dec9fcdSqs 	RBR_POSTING = 1,	/* We may post rx buffers. */
3753dec9fcdSqs 	RBR_UNMAPPING,		/* We are in the process of unmapping. */
3763dec9fcdSqs 	RBR_UNMAPPED		/* The ring is unmapped. */
3773dec9fcdSqs } rbr_state_t;
3803dec9fcdSqs /* Receive Buffer Block Ring */
3813dec9fcdSqs typedef struct _rx_rbr_ring_t {
3823dec9fcdSqs 	hxge_os_dma_common_t	rbr_desc;
3833dec9fcdSqs 	p_rx_msg_t 		*rx_msg_ring;
3843dec9fcdSqs 	p_hxge_dma_common_t 	*dma_bufp;
3853dec9fcdSqs 	rdc_rbr_cfg_a_t		rbr_cfga;
3863dec9fcdSqs 	rdc_rbr_cfg_b_t		rbr_cfgb;
3873dec9fcdSqs 	rdc_rbr_kick_t		rbr_kick;
3883dec9fcdSqs 	rdc_page_handle_t	page_hdl;
3903dec9fcdSqs 	hxge_os_mutex_t		lock;
3913dec9fcdSqs 	hxge_os_mutex_t		post_lock;
392b83cd2c3SMichael Speer 	boolean_t		rbr_is_empty;
39357c5371aSQiyan Sun - Sun Microsystems - San Diego United States 	uint32_t		rbr_used;
3943dec9fcdSqs 	uint16_t		index;
3953dec9fcdSqs 	struct _hxge_t		*hxgep;
3963dec9fcdSqs 	uint16_t		rdc;
3973dec9fcdSqs 	uint_t 			rbr_max_size;
3983dec9fcdSqs 	uint64_t		rbr_addr;
3993dec9fcdSqs 	uint_t 			rbr_wrap_mask;
4003dec9fcdSqs 	uint_t 			rbb_max;
4013dec9fcdSqs 	uint_t			block_size;
4023dec9fcdSqs 	uint_t			num_blocks;
4033dec9fcdSqs 	uint_t			tnblocks;
4043dec9fcdSqs 	uint_t			pkt_buf_size0;
4053dec9fcdSqs 	uint_t			pkt_buf_size0_bytes;
4063dec9fcdSqs 	uint_t			hpi_pkt_buf_size0;
4073dec9fcdSqs 	uint_t			pkt_buf_size1;
4083dec9fcdSqs 	uint_t			pkt_buf_size1_bytes;
4093dec9fcdSqs 	uint_t			hpi_pkt_buf_size1;
4103dec9fcdSqs 	uint_t			pkt_buf_size2;
4113dec9fcdSqs 	uint_t			pkt_buf_size2_bytes;
4123dec9fcdSqs 	uint_t			hpi_pkt_buf_size2;
4143dec9fcdSqs 	uint64_t		rbr_head_pp;
4153dec9fcdSqs 	uint64_t		rbr_tail_pp;
4163dec9fcdSqs 	uint32_t		*rbr_desc_vp;
4183dec9fcdSqs 	p_rx_rcr_ring_t		rx_rcr_p;
4203dec9fcdSqs 	rdc_rbr_head_t		rbr_head;
4213dec9fcdSqs 	uint_t 			rbr_wr_index;
4223dec9fcdSqs 	uint_t 			rbr_rd_index;
4233dec9fcdSqs 	uint_t 			rbr_hw_head_index;
4243dec9fcdSqs 	uint64_t 		rbr_hw_head_ptr;
4263dec9fcdSqs 	rxring_info_t		*ring_info;
4273dec9fcdSqs 	uint_t 			rbr_consumed;
4283dec9fcdSqs 	uint_t 			rbr_threshold_hi;
4293dec9fcdSqs 	uint_t 			rbr_threshold_lo;
4303dec9fcdSqs 	hxge_rxbuf_type_t	rbr_bufsize_type;
4313dec9fcdSqs 	boolean_t		rbr_use_bcopy;
4333dec9fcdSqs 	/*
4343dec9fcdSqs 	 * <rbr_ref_cnt> is a count of those receive buffers which
4353dec9fcdSqs 	 * have been loaned to the kernel.  We will not free this
4363dec9fcdSqs 	 * ring until the reference count reaches zero (0).
4373dec9fcdSqs 	 */
4383dec9fcdSqs 	uint32_t		rbr_ref_cnt;
4393dec9fcdSqs 	rbr_state_t		rbr_state;	/* POSTING, etc */
4403dec9fcdSqs } rx_rbr_ring_t, *p_rx_rbr_ring_t;
4423dec9fcdSqs /* Receive Mailbox */
4433dec9fcdSqs typedef struct _rx_mbox_t {
4443dec9fcdSqs 	hxge_os_dma_common_t	rx_mbox;
4453dec9fcdSqs 	rdc_rx_cfg1_t		rx_cfg1;
4463dec9fcdSqs 	rdc_rx_cfg2_t		rx_cfg2;
4473dec9fcdSqs 	uint64_t		mbox_addr;
4483dec9fcdSqs 	boolean_t		cfg_set;
4503dec9fcdSqs 	hxge_os_mutex_t 	lock;
4513dec9fcdSqs 	uint16_t		index;
4523dec9fcdSqs 	struct _hxge_t		*hxgep;
4533dec9fcdSqs 	uint16_t		rdc;
4543dec9fcdSqs } rx_mbox_t, *p_rx_mbox_t;
4563dec9fcdSqs typedef struct _rx_rbr_rings_t {
4573dec9fcdSqs 	p_rx_rbr_ring_t 	*rbr_rings;
4583dec9fcdSqs 	uint32_t		ndmas;
4593dec9fcdSqs 	boolean_t		rxbuf_allocated;
4603dec9fcdSqs } rx_rbr_rings_t, *p_rx_rbr_rings_t;
4623dec9fcdSqs typedef struct _rx_rcr_rings_t {
4633dec9fcdSqs 	p_rx_rcr_ring_t 	*rcr_rings;
4643dec9fcdSqs 	uint32_t		ndmas;
4653dec9fcdSqs 	boolean_t		cntl_buf_allocated;
4663dec9fcdSqs } rx_rcr_rings_t, *p_rx_rcr_rings_t;
4683dec9fcdSqs typedef struct _rx_mbox_areas_t {
4693dec9fcdSqs 	p_rx_mbox_t 		*rxmbox_areas;
4703dec9fcdSqs 	uint32_t		ndmas;
4713dec9fcdSqs 	boolean_t		mbox_allocated;
4723dec9fcdSqs } rx_mbox_areas_t, *p_rx_mbox_areas_t;
4743dec9fcdSqs /*
4753dec9fcdSqs  * Receive DMA Prototypes.
4763dec9fcdSqs  */
4773dec9fcdSqs hxge_status_t hxge_init_rxdma_channels(p_hxge_t hxgep);
4783dec9fcdSqs void hxge_uninit_rxdma_channels(p_hxge_t hxgep);
4793dec9fcdSqs hxge_status_t hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep,
4803dec9fcdSqs 	uint16_t channel, rdc_stat_t *cs_p);
4813dec9fcdSqs hxge_status_t hxge_enable_rxdma_channel(p_hxge_t hxgep,
4823dec9fcdSqs 	uint16_t channel, p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p,
483fd9489ceSQiyan Sun - Sun Microsystems - San Diego United States 	p_rx_mbox_t mbox_p, int n_init_kick);
4843dec9fcdSqs hxge_status_t hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable);
4853dec9fcdSqs int hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel);
4863dec9fcdSqs hxge_status_t hxge_rxdma_handle_sys_errors(p_hxge_t hxgep);
4881ed83081SMichael Speer extern int hxge_enable_poll(void *arg);
4891ed83081SMichael Speer extern int hxge_disable_poll(void *arg);
4901ed83081SMichael Speer extern mblk_t *hxge_rx_poll(void *arg, int bytes_to_read);
4911ed83081SMichael Speer 
4933dec9fcdSqs #ifdef	__cplusplus
4943dec9fcdSqs }
4953dec9fcdSqs #endif
4973dec9fcdSqs #endif	/* _SYS_HXGE_HXGE_RXDMA_H */