13dec9fcdSqs /* 23dec9fcdSqs * CDDL HEADER START 33dec9fcdSqs * 43dec9fcdSqs * The contents of this file are subject to the terms of the 53dec9fcdSqs * Common Development and Distribution License (the "License"). 63dec9fcdSqs * You may not use this file except in compliance with the License. 73dec9fcdSqs * 83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs * See the License for the specific language governing permissions 113dec9fcdSqs * and limitations under the License. 123dec9fcdSqs * 133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs * 193dec9fcdSqs * CDDL HEADER END 203dec9fcdSqs */ 213dec9fcdSqs /* 223dec9fcdSqs * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs * Use is subject to license terms. 243dec9fcdSqs */ 253dec9fcdSqs 263dec9fcdSqs #ifndef _SYS_HXGE_HXGE_RXDMA_H 273dec9fcdSqs #define _SYS_HXGE_HXGE_RXDMA_H 283dec9fcdSqs 293dec9fcdSqs #pragma ident "%Z%%M% %I% %E% SMI" 303dec9fcdSqs 313dec9fcdSqs #ifdef __cplusplus 323dec9fcdSqs extern "C" { 333dec9fcdSqs #endif 343dec9fcdSqs 353dec9fcdSqs #include <hxge_rdc_hw.h> 363dec9fcdSqs #include <hpi_rxdma.h> 373dec9fcdSqs 383dec9fcdSqs #define RXDMA_CK_DIV_DEFAULT 7500 /* 25 usec */ 393dec9fcdSqs #define RXDMA_RCR_PTHRES_DEFAULT 0x20 403dec9fcdSqs #define RXDMA_RCR_TO_DEFAULT 0x8 413dec9fcdSqs #define RXDMA_HDR_SIZE_DEFAULT 2 423dec9fcdSqs #define RXDMA_HDR_SIZE_FULL 6 /* entire header of 6B */ 433dec9fcdSqs 443dec9fcdSqs /* 453dec9fcdSqs * Receive Completion Ring (RCR) 463dec9fcdSqs */ 473dec9fcdSqs #define RCR_PKT_BUF_ADDR_SHIFT 0 /* bit 37:0 */ 483dec9fcdSqs #define RCR_PKT_BUF_ADDR_SHIFT_FULL 6 /* fulll buffer address */ 493dec9fcdSqs #define RCR_PKT_BUF_ADDR_MASK 0x0000003FFFFFFFFFULL 503dec9fcdSqs #define RCR_PKTBUFSZ_SHIFT 38 /* bit 39:38 */ 513dec9fcdSqs #define RCR_PKTBUFSZ_MASK 0x000000C000000000ULL 523dec9fcdSqs #define RCR_L2_LEN_SHIFT 40 /* bit 53:40 */ 533dec9fcdSqs #define RCR_L2_LEN_MASK 0x003fff0000000000ULL 543dec9fcdSqs #define RCR_ERROR_SHIFT 54 /* bit 57:54 */ 553dec9fcdSqs #define RCR_ERROR_MASK 0x03C0000000000000ULL 563dec9fcdSqs #define RCR_PKT_TYPE_SHIFT 61 /* bit 62:61 */ 573dec9fcdSqs #define RCR_PKT_TYPE_MASK 0x6000000000000000ULL 583dec9fcdSqs #define RCR_MULTI_SHIFT 63 /* bit 63 */ 593dec9fcdSqs #define RCR_MULTI_MASK 0x8000000000000000ULL 603dec9fcdSqs 613dec9fcdSqs #define RCR_PKTBUFSZ_0 0x00 623dec9fcdSqs #define RCR_PKTBUFSZ_1 0x01 633dec9fcdSqs #define RCR_PKTBUFSZ_2 0x02 643dec9fcdSqs #define RCR_SINGLE_BLOCK 0x03 653dec9fcdSqs 663dec9fcdSqs #define RCR_NO_ERROR 0x0 673dec9fcdSqs #define RCR_CTRL_FIFO_DED 0x1 683dec9fcdSqs #define RCR_DATA_FIFO_DED 0x2 693dec9fcdSqs #define RCR_ERROR_RESERVE 0x4 703dec9fcdSqs 713dec9fcdSqs #define RCR_PKT_IS_TCP 0x2000000000000000ULL 723dec9fcdSqs #define RCR_PKT_IS_UDP 0x4000000000000000ULL 733dec9fcdSqs #define RCR_PKT_IS_SCTP 0x6000000000000000ULL 743dec9fcdSqs 753dec9fcdSqs #define RDC_INT_MASK_RBRFULL_SHIFT 34 763dec9fcdSqs #define RDC_INT_MASK_RBRFULL_MASK 0x0000000400000000ULL 773dec9fcdSqs #define RDC_INT_MASK_RBREMPTY_SHIFT 35 783dec9fcdSqs #define RDC_INT_MASK_RBREMPTY_MASK 0x0000000800000000ULL 793dec9fcdSqs #define RDC_INT_MASK_RCRFULL_SHIFT 36 803dec9fcdSqs #define RDC_INT_MASK_RCRFULL_MASK 0x0000001000000000ULL 813dec9fcdSqs #define RDC_INT_MASK_RCRSH_FULL_SHIFT 39 823dec9fcdSqs #define RDC_INT_MASK_RCRSH_FULL_MASK 0x0000008000000000ULL 833dec9fcdSqs #define RDC_INT_MASK_RBR_PRE_EMPTY_SHIFT 40 843dec9fcdSqs #define RDC_INT_MASK_RBR_PRE_EMPTY_MASK 0x0000010000000000ULL 853dec9fcdSqs #define RDC_INT_MASK_RBR_PRE_PAR_SHIFT 43 863dec9fcdSqs #define RDC_INT_MASK_RBR_PRE_PAR_MASK 0x0000080000000000ULL 873dec9fcdSqs #define RDC_INT_MASK_RCR_SHA_PAR_SHIFT 44 883dec9fcdSqs #define RDC_INT_MASK_RCR_SHA_PAR_MASK 0x0000100000000000ULL 893dec9fcdSqs #define RDC_INT_MASK_RCRTO_SHIFT 45 903dec9fcdSqs #define RDC_INT_MASK_RCRTO_MASK 0x0000200000000000ULL 913dec9fcdSqs #define RDC_INT_MASK_THRES_SHIFT 46 923dec9fcdSqs #define RDC_INT_MASK_THRES_MASK 0x0000400000000000ULL 933dec9fcdSqs #define RDC_INT_MASK_PEU_ERR_SHIFT 52 943dec9fcdSqs #define RDC_INT_MASK_PEU_ERR_MASK 0x0010000000000000ULL 953dec9fcdSqs #define RDC_INT_MASK_RBR_CPL_SHIFT 53 963dec9fcdSqs #define RDC_INT_MASK_RBR_CPL_MASK 0x0020000000000000ULL 973dec9fcdSqs #define RDC_INT_MASK_ALL (RDC_INT_MASK_RBRFULL_MASK | \ 983dec9fcdSqs RDC_INT_MASK_RBREMPTY_MASK | \ 993dec9fcdSqs RDC_INT_MASK_RCRFULL_MASK | \ 1003dec9fcdSqs RDC_INT_MASK_RCRSH_FULL_MASK | \ 1013dec9fcdSqs RDC_INT_MASK_RBR_PRE_EMPTY_MASK | \ 1023dec9fcdSqs RDC_INT_MASK_RBR_PRE_PAR_MASK | \ 1033dec9fcdSqs RDC_INT_MASK_RCR_SHA_PAR_MASK | \ 1043dec9fcdSqs RDC_INT_MASK_RCRTO_MASK | \ 1053dec9fcdSqs RDC_INT_MASK_THRES_MASK | \ 1063dec9fcdSqs RDC_INT_MASK_PEU_ERR_MASK | \ 1073dec9fcdSqs RDC_INT_MASK_RBR_CPL_MASK) 1083dec9fcdSqs 1093dec9fcdSqs #define RDC_STAT_PKTREAD_SHIFT 0 /* WO, bit 15:0 */ 1103dec9fcdSqs #define RDC_STAT_PKTREAD_MASK 0x000000000000ffffULL 1113dec9fcdSqs #define RDC_STAT_PTRREAD_SHIFT 16 /* WO, bit 31:16 */ 1123dec9fcdSqs #define RDC_STAT_PTRREAD_MASK 0x00000000FFFF0000ULL 1133dec9fcdSqs 1143dec9fcdSqs #define RDC_STAT_RBRFULL_SHIFT 34 /* RO, bit 34 */ 1153dec9fcdSqs #define RDC_STAT_RBRFULL 0x0000000400000000ULL 1163dec9fcdSqs #define RDC_STAT_RBRFULL_MASK 0x0000000400000000ULL 1173dec9fcdSqs #define RDC_STAT_RBREMPTY_SHIFT 35 /* RW1C, bit 35 */ 1183dec9fcdSqs #define RDC_STAT_RBREMPTY 0x0000000800000000ULL 1193dec9fcdSqs #define RDC_STAT_RBREMPTY_MASK 0x0000000800000000ULL 1203dec9fcdSqs #define RDC_STAT_RCR_FULL_SHIFT 36 /* RW1C, bit 36 */ 1213dec9fcdSqs #define RDC_STAT_RCR_FULL 0x0000001000000000ULL 1223dec9fcdSqs #define RDC_STAT_RCR_FULL_MASK 0x0000001000000000ULL 1233dec9fcdSqs 1243dec9fcdSqs #define RDC_STAT_RCR_SHDW_FULL_SHIFT 39 /* RW1C, bit 39 */ 1253dec9fcdSqs #define RDC_STAT_RCR_SHDW_FULL 0x0000008000000000ULL 1263dec9fcdSqs #define RDC_STAT_RCR_SHDW_FULL_MASK 0x0000008000000000ULL 1273dec9fcdSqs #define RDC_STAT_RBR_PRE_EMPTY_SHIFT 40 /* RO, bit 40 */ 1283dec9fcdSqs #define RDC_STAT_RBR_PRE_EMPTY 0x0000010000000000ULL 1293dec9fcdSqs #define RDC_STAT_RBR_PRE_EMPTY_MASK 0x0000010000000000ULL 1303dec9fcdSqs 1313dec9fcdSqs #define RDC_STAT_RBR_PRE_PAR_SHIFT 43 /* RO, bit 43 */ 1323dec9fcdSqs #define RDC_STAT_RBR_PRE_PAR 0x0000080000000000ULL 1333dec9fcdSqs #define RDC_STAT_RBR_PRE_PAR_MASK 0x0000080000000000ULL 1343dec9fcdSqs #define RDC_STAT_RCR_SHA_PAR_SHIFT 44 /* RO, bit 44 */ 1353dec9fcdSqs #define RDC_STAT_RCR_SHA_PAR 0x0000100000000000ULL 1363dec9fcdSqs #define RDC_STAT_RCR_SHA_PAR_MASK 0x0000100000000000ULL 1373dec9fcdSqs 1383dec9fcdSqs #define RDC_STAT_RCR_TO_SHIFT 45 /* RW1C, bit 45 */ 1393dec9fcdSqs #define RDC_STAT_RCR_TO 0x0000200000000000ULL 1403dec9fcdSqs #define RDC_STAT_RCR_TO_MASK 0x0000200000000000ULL 1413dec9fcdSqs #define RDC_STAT_RCR_THRES_SHIFT 46 /* RO, bit 46 */ 1423dec9fcdSqs #define RDC_STAT_RCR_THRES 0x0000400000000000ULL 1433dec9fcdSqs #define RDC_STAT_RCR_THRES_MASK 0x0000400000000000ULL 1443dec9fcdSqs #define RDC_STAT_RCR_MEX_SHIFT 47 /* RW, bit 47 */ 1453dec9fcdSqs #define RDC_STAT_RCR_MEX 0x0000800000000000ULL 1463dec9fcdSqs #define RDC_STAT_RCR_MEX_MASK 0x0000800000000000ULL 1473dec9fcdSqs 1483dec9fcdSqs #define RDC_STAT_PEU_ERR_SHIFT 52 /* RO, bit 52 */ 1493dec9fcdSqs #define RDC_STAT_PEU_ERR 0x0010000000000000ULL 1503dec9fcdSqs #define RDC_STAT_PEU_ERR_MASK 0x0010000000000000ULL 1513dec9fcdSqs 1523dec9fcdSqs #define RDC_STAT_RBR_CPL_SHIFT 53 /* RO, bit 53 */ 1533dec9fcdSqs #define RDC_STAT_RBR_CPL 0x0020000000000000ULL 1543dec9fcdSqs #define RDC_STAT_RBR_CPL_MASK 0x0020000000000000ULL 1553dec9fcdSqs 1563dec9fcdSqs #define RDC_STAT_ERROR RDC_INT_MASK_ALL 1573dec9fcdSqs 1583dec9fcdSqs /* the following are write 1 to clear bits */ 1593dec9fcdSqs #define RDC_STAT_WR1C (RDC_STAT_RBREMPTY | \ 1603dec9fcdSqs RDC_STAT_RCR_SHDW_FULL | \ 1613dec9fcdSqs RDC_STAT_RBR_PRE_EMPTY | \ 1623dec9fcdSqs RDC_STAT_RBR_PRE_PAR | \ 1633dec9fcdSqs RDC_STAT_RCR_SHA_PAR | \ 1643dec9fcdSqs RDC_STAT_RCR_TO | \ 1653dec9fcdSqs RDC_STAT_RCR_THRES | \ 1663dec9fcdSqs RDC_STAT_RBR_CPL | \ 1673dec9fcdSqs RDC_STAT_PEU_ERR) 1683dec9fcdSqs 1693dec9fcdSqs typedef union _rcr_entry_t { 1703dec9fcdSqs uint64_t value; 1713dec9fcdSqs struct { 1723dec9fcdSqs #if defined(_BIG_ENDIAN) 173*fe930412Sqs uint32_t multi:1; 174*fe930412Sqs uint32_t pkt_type:2; 175*fe930412Sqs uint32_t reserved:3; 176*fe930412Sqs uint32_t error:4; 177*fe930412Sqs uint32_t l2_len:14; 178*fe930412Sqs uint32_t pktbufsz:2; 179*fe930412Sqs uint32_t pkt_buf_addr:6; 180*fe930412Sqs uint32_t pkt_buf_addr_l:32; 1813dec9fcdSqs #else 182*fe930412Sqs uint32_t pkt_buf_addr_l:32; 183*fe930412Sqs uint32_t pkt_buf_addr:6; 184*fe930412Sqs uint32_t pktbufsz:2; 185*fe930412Sqs uint32_t l2_len:14; 186*fe930412Sqs uint32_t error:4; 187*fe930412Sqs uint32_t reserved:3; 188*fe930412Sqs uint32_t pkt_type:2; 189*fe930412Sqs uint32_t multi:1; 1903dec9fcdSqs #endif 1913dec9fcdSqs } bits; 1923dec9fcdSqs } rcr_entry_t, *p_rcr_entry_t; 1933dec9fcdSqs 1943dec9fcdSqs #define RX_DMA_MAILBOX_BYTE_LENGTH 64 1953dec9fcdSqs #define RX_DMA_MBOX_UNUSED_1 8 1963dec9fcdSqs #define RX_DMA_MBOX_UNUSED_2 16 1973dec9fcdSqs 1983dec9fcdSqs typedef struct _rxdma_mailbox_t { 1993dec9fcdSqs rdc_stat_t rxdma_ctl_stat; /* 8 bytes */ 2003dec9fcdSqs rdc_rbr_qlen_t rbr_stat; /* 8 bytes */ 2013dec9fcdSqs rdc_rbr_head_t rbr_hdh; /* 8 bytes */ 2023dec9fcdSqs uint8_t resv_1[RX_DMA_MBOX_UNUSED_1]; 2033dec9fcdSqs rdc_rcr_tail_t rcrstat_c; /* 8 bytes */ 2043dec9fcdSqs uint8_t resv_2[RX_DMA_MBOX_UNUSED_1]; 2053dec9fcdSqs rdc_rcr_qlen_t rcrstat_a; /* 8 bytes */ 2063dec9fcdSqs uint8_t resv_3[RX_DMA_MBOX_UNUSED_1]; 2073dec9fcdSqs } rxdma_mailbox_t, *p_rxdma_mailbox_t; 2083dec9fcdSqs 2093dec9fcdSqs /* 2103dec9fcdSqs * hardware workarounds: kick 16 (was 8 before) 2113dec9fcdSqs */ 2123dec9fcdSqs #define HXGE_RXDMA_POST_BATCH 16 2133dec9fcdSqs 2143dec9fcdSqs #define RXBUF_START_ADDR(a, index, bsize) ((a & (index * bsize)) 2153dec9fcdSqs #define RXBUF_OFFSET_FROM_START(a, start) (start - a) 2163dec9fcdSqs #define RXBUF_64B_ALIGNED 64 2173dec9fcdSqs 2183dec9fcdSqs #define HXGE_RXBUF_EXTRA 34 2193dec9fcdSqs 2203dec9fcdSqs /* 2213dec9fcdSqs * Receive buffer thresholds and buffer types 2223dec9fcdSqs */ 2233dec9fcdSqs #define HXGE_RX_BCOPY_SCALE 8 /* use 1/8 as lowest granularity */ 2243dec9fcdSqs 2253dec9fcdSqs typedef enum { 2263dec9fcdSqs HXGE_RX_COPY_ALL = 0, /* do bcopy on every packet */ 2273dec9fcdSqs HXGE_RX_COPY_1, /* bcopy on 1/8 of buffer posted */ 2283dec9fcdSqs HXGE_RX_COPY_2, /* bcopy on 2/8 of buffer posted */ 2293dec9fcdSqs HXGE_RX_COPY_3, /* bcopy on 3/8 of buffer posted */ 2303dec9fcdSqs HXGE_RX_COPY_4, /* bcopy on 4/8 of buffer posted */ 2313dec9fcdSqs HXGE_RX_COPY_5, /* bcopy on 5/8 of buffer posted */ 2323dec9fcdSqs HXGE_RX_COPY_6, /* bcopy on 6/8 of buffer posted */ 2333dec9fcdSqs HXGE_RX_COPY_7, /* bcopy on 7/8 of buffer posted */ 2343dec9fcdSqs HXGE_RX_COPY_NONE /* don't do bcopy at all */ 2353dec9fcdSqs } hxge_rxbuf_threshold_t; 2363dec9fcdSqs 2373dec9fcdSqs typedef enum { 2383dec9fcdSqs HXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0, /* bcopy buffer size 0 (small) */ 2393dec9fcdSqs HXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1, /* bcopy buffer size 1 (medium) */ 2403dec9fcdSqs HXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2 /* bcopy buffer size 2 (large) */ 2413dec9fcdSqs } hxge_rxbuf_type_t; 2423dec9fcdSqs 2433dec9fcdSqs typedef struct _rdc_errlog { 2443dec9fcdSqs rdc_pref_par_log_t pre_par; 2453dec9fcdSqs rdc_pref_par_log_t sha_par; 2463dec9fcdSqs uint8_t compl_err_type; 2473dec9fcdSqs } rdc_errlog_t; 2483dec9fcdSqs 2493dec9fcdSqs /* 2503dec9fcdSqs * Receive Statistics. 2513dec9fcdSqs */ 2523dec9fcdSqs typedef struct _hxge_rx_ring_stats_t { 2533dec9fcdSqs uint64_t ipackets; 2543dec9fcdSqs uint64_t ibytes; 2553dec9fcdSqs uint32_t ierrors; 2563dec9fcdSqs uint32_t jumbo_pkts; 2573dec9fcdSqs 2583dec9fcdSqs /* 2593dec9fcdSqs * Error event stats. 2603dec9fcdSqs */ 2613dec9fcdSqs uint32_t rcr_unknown_err; 2623dec9fcdSqs uint32_t ctrl_fifo_ecc_err; 2633dec9fcdSqs uint32_t data_fifo_ecc_err; 2643dec9fcdSqs uint32_t rbr_tmout; /* rbr_cpl_to */ 2653dec9fcdSqs uint32_t peu_resp_err; /* peu_resp_err */ 2663dec9fcdSqs uint32_t rcr_sha_par; /* rcr_shadow_par_err */ 2673dec9fcdSqs uint32_t rbr_pre_par; /* rbr_prefetch_par_err */ 2683dec9fcdSqs uint32_t rbr_pre_empty; /* rbr_pre_empty */ 2693dec9fcdSqs uint32_t rcr_shadow_full; /* rcr_shadow_full */ 2703dec9fcdSqs uint32_t rcrfull; /* rcr_full */ 2713dec9fcdSqs uint32_t rbr_empty; /* rbr_empty */ 2723dec9fcdSqs uint32_t rbrfull; /* rbr_full */ 2733dec9fcdSqs uint32_t rcr_to; /* rcr_to */ 2743dec9fcdSqs uint32_t rcr_thres; /* rcr_thres */ 2753dec9fcdSqs rdc_errlog_t errlog; 2763dec9fcdSqs } hxge_rx_ring_stats_t, *p_hxge_rx_ring_stats_t; 2773dec9fcdSqs 2783dec9fcdSqs typedef struct _hxge_rdc_sys_stats { 2793dec9fcdSqs uint32_t ctrl_fifo_sec; 2803dec9fcdSqs uint32_t ctrl_fifo_ded; 2813dec9fcdSqs uint32_t data_fifo_sec; 2823dec9fcdSqs uint32_t data_fifo_ded; 2833dec9fcdSqs } hxge_rdc_sys_stats_t, *p_hxge_rdc_sys_stats_t; 2843dec9fcdSqs 2853dec9fcdSqs typedef struct _rx_msg_t { 2863dec9fcdSqs hxge_os_dma_common_t buf_dma; 2873dec9fcdSqs hxge_os_mutex_t lock; 2883dec9fcdSqs struct _hxge_t *hxgep; 2893dec9fcdSqs struct _rx_rbr_ring_t *rx_rbr_p; 2903dec9fcdSqs boolean_t free; 2913dec9fcdSqs uint32_t ref_cnt; 2923dec9fcdSqs hxge_os_frtn_t freeb; 2933dec9fcdSqs size_t block_size; 2943dec9fcdSqs uint32_t block_index; 2953dec9fcdSqs uint32_t pkt_buf_size; 2963dec9fcdSqs uint32_t pkt_buf_size_code; 2973dec9fcdSqs uint32_t cur_usage_cnt; 2983dec9fcdSqs uint32_t max_usage_cnt; 2993dec9fcdSqs uchar_t *buffer; 3003dec9fcdSqs uint32_t pri; 3013dec9fcdSqs uint32_t shifted_addr; 3023dec9fcdSqs boolean_t use_buf_pool; 3033dec9fcdSqs p_mblk_t rx_mblk_p; 3043dec9fcdSqs boolean_t rx_use_bcopy; 3053dec9fcdSqs } rx_msg_t, *p_rx_msg_t; 3063dec9fcdSqs 3073dec9fcdSqs /* Receive Completion Ring */ 3083dec9fcdSqs typedef struct _rx_rcr_ring_t { 3093dec9fcdSqs hxge_os_dma_common_t rcr_desc; 3103dec9fcdSqs struct _hxge_t *hxgep; 3113dec9fcdSqs 3123dec9fcdSqs p_hxge_rx_ring_stats_t rdc_stats; /* pointer to real kstats */ 3133dec9fcdSqs 3143dec9fcdSqs rdc_rcr_cfg_a_t rcr_cfga; 3153dec9fcdSqs rdc_rcr_cfg_b_t rcr_cfgb; 3163dec9fcdSqs 3173dec9fcdSqs hxge_os_mutex_t lock; 3183dec9fcdSqs uint16_t index; 3193dec9fcdSqs uint16_t rdc; 3203dec9fcdSqs boolean_t full_hdr_flag; /* 1: 18 bytes header */ 3213dec9fcdSqs uint16_t sw_priv_hdr_len; /* 0 - 192 bytes (SW) */ 3223dec9fcdSqs uint32_t comp_size; /* # of RCR entries */ 3233dec9fcdSqs uint64_t rcr_addr; 3243dec9fcdSqs uint_t comp_wrap_mask; 3253dec9fcdSqs uint_t comp_rd_index; 3263dec9fcdSqs uint_t comp_wt_index; 3273dec9fcdSqs 3283dec9fcdSqs p_rcr_entry_t rcr_desc_first_p; 3293dec9fcdSqs p_rcr_entry_t rcr_desc_first_pp; 3303dec9fcdSqs p_rcr_entry_t rcr_desc_last_p; 3313dec9fcdSqs p_rcr_entry_t rcr_desc_last_pp; 3323dec9fcdSqs 3333dec9fcdSqs p_rcr_entry_t rcr_desc_rd_head_p; /* software next read */ 3343dec9fcdSqs p_rcr_entry_t rcr_desc_rd_head_pp; 3353dec9fcdSqs 3363dec9fcdSqs struct _rx_rbr_ring_t *rx_rbr_p; 3373dec9fcdSqs uint32_t intr_timeout; 3383dec9fcdSqs uint32_t intr_threshold; 3393dec9fcdSqs uint64_t max_receive_pkts; 3403dec9fcdSqs mac_resource_handle_t rcr_mac_handle; 3413dec9fcdSqs uint32_t rcvd_pkt_bytes; /* Received bytes of a packet */ 3423dec9fcdSqs } rx_rcr_ring_t, *p_rx_rcr_ring_t; 3433dec9fcdSqs 3443dec9fcdSqs 3453dec9fcdSqs /* Buffer index information */ 3463dec9fcdSqs typedef struct _rxbuf_index_info_t { 3473dec9fcdSqs uint32_t buf_index; 3483dec9fcdSqs uint32_t start_index; 3493dec9fcdSqs uint32_t buf_size; 3503dec9fcdSqs uint64_t dvma_addr; 3513dec9fcdSqs uint64_t kaddr; 3523dec9fcdSqs } rxbuf_index_info_t, *p_rxbuf_index_info_t; 3533dec9fcdSqs 3543dec9fcdSqs /* Buffer index information */ 3553dec9fcdSqs 3563dec9fcdSqs typedef struct _rxring_info_t { 3573dec9fcdSqs uint32_t hint[3]; 3583dec9fcdSqs uint32_t block_size_mask; 3593dec9fcdSqs uint16_t max_iterations; 3603dec9fcdSqs rxbuf_index_info_t buffer[HXGE_DMA_BLOCK]; 3613dec9fcdSqs } rxring_info_t, *p_rxring_info_t; 3623dec9fcdSqs 3633dec9fcdSqs 3643dec9fcdSqs typedef enum { 3653dec9fcdSqs RBR_POSTING = 1, /* We may post rx buffers. */ 3663dec9fcdSqs RBR_UNMAPPING, /* We are in the process of unmapping. */ 3673dec9fcdSqs RBR_UNMAPPED /* The ring is unmapped. */ 3683dec9fcdSqs } rbr_state_t; 3693dec9fcdSqs 3703dec9fcdSqs 3713dec9fcdSqs /* Receive Buffer Block Ring */ 3723dec9fcdSqs typedef struct _rx_rbr_ring_t { 3733dec9fcdSqs hxge_os_dma_common_t rbr_desc; 3743dec9fcdSqs p_rx_msg_t *rx_msg_ring; 3753dec9fcdSqs p_hxge_dma_common_t *dma_bufp; 3763dec9fcdSqs rdc_rbr_cfg_a_t rbr_cfga; 3773dec9fcdSqs rdc_rbr_cfg_b_t rbr_cfgb; 3783dec9fcdSqs rdc_rbr_kick_t rbr_kick; 3793dec9fcdSqs rdc_page_handle_t page_hdl; 3803dec9fcdSqs 3813dec9fcdSqs hxge_os_mutex_t lock; 3823dec9fcdSqs hxge_os_mutex_t post_lock; 3833dec9fcdSqs uint16_t index; 3843dec9fcdSqs struct _hxge_t *hxgep; 3853dec9fcdSqs uint16_t rdc; 3863dec9fcdSqs uint_t rbr_max_size; 3873dec9fcdSqs uint64_t rbr_addr; 3883dec9fcdSqs uint_t rbr_wrap_mask; 3893dec9fcdSqs uint_t rbb_max; 3903dec9fcdSqs uint_t block_size; 3913dec9fcdSqs uint_t num_blocks; 3923dec9fcdSqs uint_t tnblocks; 3933dec9fcdSqs uint_t pkt_buf_size0; 3943dec9fcdSqs uint_t pkt_buf_size0_bytes; 3953dec9fcdSqs uint_t hpi_pkt_buf_size0; 3963dec9fcdSqs uint_t pkt_buf_size1; 3973dec9fcdSqs uint_t pkt_buf_size1_bytes; 3983dec9fcdSqs uint_t hpi_pkt_buf_size1; 3993dec9fcdSqs uint_t pkt_buf_size2; 4003dec9fcdSqs uint_t pkt_buf_size2_bytes; 4013dec9fcdSqs uint_t hpi_pkt_buf_size2; 4023dec9fcdSqs 4033dec9fcdSqs uint64_t rbr_head_pp; 4043dec9fcdSqs uint64_t rbr_tail_pp; 4053dec9fcdSqs uint32_t *rbr_desc_vp; 4063dec9fcdSqs 4073dec9fcdSqs p_rx_rcr_ring_t rx_rcr_p; 4083dec9fcdSqs 4093dec9fcdSqs rdc_rbr_head_t rbr_head; 4103dec9fcdSqs uint_t rbr_wr_index; 4113dec9fcdSqs uint_t rbr_rd_index; 4123dec9fcdSqs uint_t rbr_hw_head_index; 4133dec9fcdSqs uint64_t rbr_hw_head_ptr; 4143dec9fcdSqs 4153dec9fcdSqs rxring_info_t *ring_info; 4163dec9fcdSqs uint_t rbr_consumed; 4173dec9fcdSqs uint_t rbr_threshold_hi; 4183dec9fcdSqs uint_t rbr_threshold_lo; 4193dec9fcdSqs hxge_rxbuf_type_t rbr_bufsize_type; 4203dec9fcdSqs boolean_t rbr_use_bcopy; 4213dec9fcdSqs 4223dec9fcdSqs /* 4233dec9fcdSqs * <rbr_ref_cnt> is a count of those receive buffers which 4243dec9fcdSqs * have been loaned to the kernel. We will not free this 4253dec9fcdSqs * ring until the reference count reaches zero (0). 4263dec9fcdSqs */ 4273dec9fcdSqs uint32_t rbr_ref_cnt; 4283dec9fcdSqs rbr_state_t rbr_state; /* POSTING, etc */ 4293dec9fcdSqs 4303dec9fcdSqs int pages_to_post; 4313dec9fcdSqs int pages_to_post_threshold; 4323dec9fcdSqs int pages_to_skip; 4333dec9fcdSqs } rx_rbr_ring_t, *p_rx_rbr_ring_t; 4343dec9fcdSqs 4353dec9fcdSqs /* Receive Mailbox */ 4363dec9fcdSqs typedef struct _rx_mbox_t { 4373dec9fcdSqs hxge_os_dma_common_t rx_mbox; 4383dec9fcdSqs rdc_rx_cfg1_t rx_cfg1; 4393dec9fcdSqs rdc_rx_cfg2_t rx_cfg2; 4403dec9fcdSqs uint64_t mbox_addr; 4413dec9fcdSqs boolean_t cfg_set; 4423dec9fcdSqs 4433dec9fcdSqs hxge_os_mutex_t lock; 4443dec9fcdSqs uint16_t index; 4453dec9fcdSqs struct _hxge_t *hxgep; 4463dec9fcdSqs uint16_t rdc; 4473dec9fcdSqs } rx_mbox_t, *p_rx_mbox_t; 4483dec9fcdSqs 4493dec9fcdSqs typedef struct _rx_rbr_rings_t { 4503dec9fcdSqs p_rx_rbr_ring_t *rbr_rings; 4513dec9fcdSqs uint32_t ndmas; 4523dec9fcdSqs boolean_t rxbuf_allocated; 4533dec9fcdSqs } rx_rbr_rings_t, *p_rx_rbr_rings_t; 4543dec9fcdSqs 4553dec9fcdSqs typedef struct _rx_rcr_rings_t { 4563dec9fcdSqs p_rx_rcr_ring_t *rcr_rings; 4573dec9fcdSqs uint32_t ndmas; 4583dec9fcdSqs boolean_t cntl_buf_allocated; 4593dec9fcdSqs } rx_rcr_rings_t, *p_rx_rcr_rings_t; 4603dec9fcdSqs 4613dec9fcdSqs typedef struct _rx_mbox_areas_t { 4623dec9fcdSqs p_rx_mbox_t *rxmbox_areas; 4633dec9fcdSqs uint32_t ndmas; 4643dec9fcdSqs boolean_t mbox_allocated; 4653dec9fcdSqs } rx_mbox_areas_t, *p_rx_mbox_areas_t; 4663dec9fcdSqs 4673dec9fcdSqs /* 4683dec9fcdSqs * Receive DMA Prototypes. 4693dec9fcdSqs */ 4703dec9fcdSqs hxge_status_t hxge_init_rxdma_channels(p_hxge_t hxgep); 4713dec9fcdSqs void hxge_uninit_rxdma_channels(p_hxge_t hxgep); 4723dec9fcdSqs hxge_status_t hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, 4733dec9fcdSqs uint16_t channel, rdc_stat_t *cs_p); 4743dec9fcdSqs hxge_status_t hxge_enable_rxdma_channel(p_hxge_t hxgep, 4753dec9fcdSqs uint16_t channel, p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, 4763dec9fcdSqs p_rx_mbox_t mbox_p); 4773dec9fcdSqs hxge_status_t hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable); 4783dec9fcdSqs int hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel); 4793dec9fcdSqs hxge_status_t hxge_rxdma_handle_sys_errors(p_hxge_t hxgep); 4803dec9fcdSqs 4813dec9fcdSqs 4823dec9fcdSqs #ifdef __cplusplus 4833dec9fcdSqs } 4843dec9fcdSqs #endif 4853dec9fcdSqs 4863dec9fcdSqs #endif /* _SYS_HXGE_HXGE_RXDMA_H */ 487