13dec9fcdSqs /* 23dec9fcdSqs * CDDL HEADER START 33dec9fcdSqs * 43dec9fcdSqs * The contents of this file are subject to the terms of the 53dec9fcdSqs * Common Development and Distribution License (the "License"). 63dec9fcdSqs * You may not use this file except in compliance with the License. 73dec9fcdSqs * 83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs * See the License for the specific language governing permissions 113dec9fcdSqs * and limitations under the License. 123dec9fcdSqs * 133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs * 193dec9fcdSqs * CDDL HEADER END 203dec9fcdSqs */ 213dec9fcdSqs /* 223dec9fcdSqs * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs * Use is subject to license terms. 243dec9fcdSqs */ 253dec9fcdSqs 263dec9fcdSqs #ifndef _HXGE_RDC_HW_H 273dec9fcdSqs #define _HXGE_RDC_HW_H 283dec9fcdSqs 293dec9fcdSqs #ifdef __cplusplus 303dec9fcdSqs extern "C" { 313dec9fcdSqs #endif 323dec9fcdSqs 333dec9fcdSqs #define RDC_BASE_ADDR 0X00300000 343dec9fcdSqs 353dec9fcdSqs #define RDC_PAGE_HANDLE (RDC_BASE_ADDR + 0x8) 363dec9fcdSqs #define RDC_RX_CFG1 (RDC_BASE_ADDR + 0x20) 373dec9fcdSqs #define RDC_RX_CFG2 (RDC_BASE_ADDR + 0x28) 383dec9fcdSqs #define RDC_RBR_CFG_A (RDC_BASE_ADDR + 0x40) 393dec9fcdSqs #define RDC_RBR_CFG_B (RDC_BASE_ADDR + 0x48) 403dec9fcdSqs #define RDC_RBR_KICK (RDC_BASE_ADDR + 0x50) 413dec9fcdSqs #define RDC_RBR_QLEN (RDC_BASE_ADDR + 0x58) 423dec9fcdSqs #define RDC_RBR_HEAD (RDC_BASE_ADDR + 0x68) 433dec9fcdSqs #define RDC_RCR_CFG_A (RDC_BASE_ADDR + 0x80) 443dec9fcdSqs #define RDC_RCR_CFG_B (RDC_BASE_ADDR + 0x88) 453dec9fcdSqs #define RDC_RCR_QLEN (RDC_BASE_ADDR + 0x90) 463dec9fcdSqs #define RDC_RCR_TAIL (RDC_BASE_ADDR + 0xA0) 473dec9fcdSqs #define RDC_RCR_FLUSH (RDC_BASE_ADDR + 0xA8) 483dec9fcdSqs #define RDC_CLOCK_DIV (RDC_BASE_ADDR + 0xB0) 493dec9fcdSqs #define RDC_INT_MASK (RDC_BASE_ADDR + 0xB8) 503dec9fcdSqs #define RDC_STAT (RDC_BASE_ADDR + 0xC0) 513dec9fcdSqs #define RDC_PKT_COUNT (RDC_BASE_ADDR + 0xD0) 523dec9fcdSqs #define RDC_DROP_COUNT (RDC_BASE_ADDR + 0xD8) 533dec9fcdSqs #define RDC_BYTE_COUNT (RDC_BASE_ADDR + 0xE0) 543dec9fcdSqs #define RDC_PREF_CMD (RDC_BASE_ADDR + 0x100) 553dec9fcdSqs #define RDC_PREF_DATA (RDC_BASE_ADDR + 0x108) 563dec9fcdSqs #define RDC_SHADOW_CMD (RDC_BASE_ADDR + 0x110) 573dec9fcdSqs #define RDC_SHADOW_DATA (RDC_BASE_ADDR + 0x118) 583dec9fcdSqs #define RDC_SHADOW_PAR_DATA (RDC_BASE_ADDR + 0x120) 593dec9fcdSqs #define RDC_CTRL_FIFO_CMD (RDC_BASE_ADDR + 0x128) 603dec9fcdSqs #define RDC_CTRL_FIFO_DATA_LO (RDC_BASE_ADDR + 0x130) 613dec9fcdSqs #define RDC_CTRL_FIFO_DATA_HI (RDC_BASE_ADDR + 0x138) 623dec9fcdSqs #define RDC_CTRL_FIFO_DATA_ECC (RDC_BASE_ADDR + 0x140) 633dec9fcdSqs #define RDC_DATA_FIFO_CMD (RDC_BASE_ADDR + 0x148) 643dec9fcdSqs #define RDC_DATA_FIFO_DATA_LO (RDC_BASE_ADDR + 0x150) 653dec9fcdSqs #define RDC_DATA_FIFO_DATA_HI (RDC_BASE_ADDR + 0x158) 663dec9fcdSqs #define RDC_DATA_FIFO_DATA_ECC (RDC_BASE_ADDR + 0x160) 673dec9fcdSqs #define RDC_STAT_INT_DBG (RDC_BASE_ADDR + 0x200) 683dec9fcdSqs #define RDC_PREF_PAR_LOG (RDC_BASE_ADDR + 0x210) 693dec9fcdSqs #define RDC_SHADOW_PAR_LOG (RDC_BASE_ADDR + 0x218) 703dec9fcdSqs #define RDC_CTRL_FIFO_ECC_LOG (RDC_BASE_ADDR + 0x220) 713dec9fcdSqs #define RDC_DATA_FIFO_ECC_LOG (RDC_BASE_ADDR + 0x228) 723dec9fcdSqs #define RDC_FIFO_ERR_INT_MASK (RDC_BASE_ADDR + 0x230) 733dec9fcdSqs #define RDC_FIFO_ERR_STAT (RDC_BASE_ADDR + 0x238) 743dec9fcdSqs #define RDC_FIFO_ERR_INT_DBG (RDC_BASE_ADDR + 0x240) 753dec9fcdSqs #define RDC_PEU_TXN_LOG (RDC_BASE_ADDR + 0x250) 763dec9fcdSqs #define RDC_DBG_TRAINING_VEC (RDC_BASE_ADDR + 0x300) 773dec9fcdSqs #define RDC_DBG_GRP_SEL (RDC_BASE_ADDR + 0x308) 783dec9fcdSqs 793dec9fcdSqs 803dec9fcdSqs /* 813dec9fcdSqs * Register: RdcPageHandle 823dec9fcdSqs * Logical Page Handle 833dec9fcdSqs * Description: Logical page handle specifying upper bits of 64-bit 843dec9fcdSqs * PCIE addresses. Fields in this register are part of the dma 853dec9fcdSqs * configuration and cannot be changed once the dma is enabled. 863dec9fcdSqs * Fields: 873dec9fcdSqs * Bits [63:44] of a 64-bit address, used to concatenate to a 883dec9fcdSqs * 44-bit address when generating 64-bit addresses on the PCIE 893dec9fcdSqs * bus. 903dec9fcdSqs */ 913dec9fcdSqs typedef union { 923dec9fcdSqs uint64_t value; 933dec9fcdSqs struct { 943dec9fcdSqs #if defined(_BIG_ENDIAN) 95*fe930412Sqs uint32_t rsrvd:32; 96*fe930412Sqs uint32_t rsrvd_l:12; 97*fe930412Sqs uint32_t handle:20; 983dec9fcdSqs #else 99*fe930412Sqs uint32_t handle:20; 100*fe930412Sqs uint32_t rsrvd_l:12; 101*fe930412Sqs uint32_t rsrvd:32; 1023dec9fcdSqs #endif 1033dec9fcdSqs } bits; 1043dec9fcdSqs } rdc_page_handle_t; 1053dec9fcdSqs 1063dec9fcdSqs 1073dec9fcdSqs /* 1083dec9fcdSqs * Register: RdcRxCfg1 1093dec9fcdSqs * DMA Configuration 1 1103dec9fcdSqs * Description: Configuration parameters for receive DMA block. 1113dec9fcdSqs * Fields in this register are part of the dma configuration and 1123dec9fcdSqs * cannot be changed once the dma is enabled. 1133dec9fcdSqs * The usage of enable, reset, and qst is as follows. Software 1143dec9fcdSqs * should use the following sequence to reset a DMA channel. First, 1153dec9fcdSqs * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to 1163dec9fcdSqs * 1. After DMA.reset is cleared by hardware and the DMA.qst is set 1173dec9fcdSqs * to 1, software may then start configuring the DMA channel. The 1183dec9fcdSqs * DMA.enable can be set or cleared while the DMA is in operation. 1193dec9fcdSqs * The state machines of the DMA may not have returned to its initial 1203dec9fcdSqs * states yet after the DMA.enable bit is cleared. This condition is 1213dec9fcdSqs * indicated by the value of the DMA.qst. An example of DMA.enable 1223dec9fcdSqs * being cleared during operation is when a fatal error occurs. 1233dec9fcdSqs * Fields: 1243dec9fcdSqs * Set to 1 to enable the Receive DMA. If set to 0, packets 1253dec9fcdSqs * selecting this DMA will be discarded. On fatal errors, this 1263dec9fcdSqs * bit will be cleared by hardware. This bit cannot be set if sw 1273dec9fcdSqs * has not resolved any pending fatal error condition: i.e. any 1283dec9fcdSqs * RdcStat ldf1 error bits remain set. 1293dec9fcdSqs * Set to 1 to reset the DMA. Hardware will clear this bit after 1303dec9fcdSqs * reset is completed. A reset will bring the sepecific DMA back 1313dec9fcdSqs * to the power on state (including the DMA.en in this register). 1323dec9fcdSqs * When set to 1, it indicates all state associated with the DMA 1333dec9fcdSqs * are in its initial state following either dma reset or 1343dec9fcdSqs * disable. Thus, once this is set to 1, sw could start to 1353dec9fcdSqs * configure the DMA if needed. 1363dec9fcdSqs * Bits [43:32] of the Mailbox address. 1373dec9fcdSqs */ 1383dec9fcdSqs typedef union { 1393dec9fcdSqs uint64_t value; 1403dec9fcdSqs struct { 1413dec9fcdSqs #if defined(_BIG_ENDIAN) 142*fe930412Sqs uint32_t rsrvd:32; 143*fe930412Sqs uint32_t enable:1; 144*fe930412Sqs uint32_t reset:1; 145*fe930412Sqs uint32_t qst:1; 146*fe930412Sqs uint32_t rsrvd1:17; 147*fe930412Sqs uint32_t mbaddr_h:12; 1483dec9fcdSqs #else 149*fe930412Sqs uint32_t mbaddr_h:12; 150*fe930412Sqs uint32_t rsrvd1:17; 151*fe930412Sqs uint32_t qst:1; 152*fe930412Sqs uint32_t reset:1; 153*fe930412Sqs uint32_t enable:1; 154*fe930412Sqs uint32_t rsrvd:32; 1553dec9fcdSqs #endif 1563dec9fcdSqs } bits; 1573dec9fcdSqs } rdc_rx_cfg1_t; 1583dec9fcdSqs 1593dec9fcdSqs 1603dec9fcdSqs /* 1613dec9fcdSqs * Register: RdcRxCfg2 1623dec9fcdSqs * DMA Configuration 2 1633dec9fcdSqs * Description: Configuration parameters for receive DMA block. 1643dec9fcdSqs * Fields in this register are part of the dma configuration and 1653dec9fcdSqs * cannot be changed once the dma is enabled. 1663dec9fcdSqs * Fields: 1673dec9fcdSqs * Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to 1683dec9fcdSqs * be zero, or 64B aligned. 1693dec9fcdSqs * Multiple of 64Bs, 0 means no offset, b01 means 64B, b10 means 1703dec9fcdSqs * 128B. b11 is invalid, hardware behavior not specified. 1713dec9fcdSqs * Set to 1 to select the entire header of 6B. 1723dec9fcdSqs */ 1733dec9fcdSqs typedef union { 1743dec9fcdSqs uint64_t value; 1753dec9fcdSqs struct { 1763dec9fcdSqs #if defined(_BIG_ENDIAN) 177*fe930412Sqs uint32_t rsrvd:32; 178*fe930412Sqs uint32_t mbaddr_l:26; 179*fe930412Sqs uint32_t rsrvd1:3; 180*fe930412Sqs uint32_t offset:2; 181*fe930412Sqs uint32_t full_hdr:1; 1823dec9fcdSqs #else 183*fe930412Sqs uint32_t full_hdr:1; 184*fe930412Sqs uint32_t offset:2; 185*fe930412Sqs uint32_t rsrvd1:3; 186*fe930412Sqs uint32_t mbaddr_l:26; 187*fe930412Sqs uint32_t rsrvd:32; 1883dec9fcdSqs #endif 1893dec9fcdSqs } bits; 1903dec9fcdSqs } rdc_rx_cfg2_t; 1913dec9fcdSqs 1923dec9fcdSqs 1933dec9fcdSqs /* 1943dec9fcdSqs * Register: RdcRbrCfgA 1953dec9fcdSqs * RBR Configuration A 1963dec9fcdSqs * Description: The following registers are used to configure and 1973dec9fcdSqs * manage the RBR. Note that the entire RBR must stay within the 1983dec9fcdSqs * 'page' defined by staddrBase. The behavior of the hardware is 1993dec9fcdSqs * undefined if the last entry is outside of the page (if bits 43:18 2003dec9fcdSqs * of the address of the last entry are different from bits 43:18 of 2013dec9fcdSqs * the base address). Hardware will support wrapping around at the 2023dec9fcdSqs * end of the ring buffer defined by LEN. LEN must be a multiple of 2033dec9fcdSqs * 64. Fields in this register are part of the dma configuration and 2043dec9fcdSqs * cannot be changed once the dma is enabled. 2053dec9fcdSqs * HW does not check for all configuration errors across different 2063dec9fcdSqs * fields. 2073dec9fcdSqs * 2083dec9fcdSqs * Fields: 2093dec9fcdSqs * Bits 15:6 of the maximum number of RBBs in the buffer ring. 2103dec9fcdSqs * Bits 5:0 are hardcoded to zero. The maximum is (2^16 - 64) and 2113dec9fcdSqs * is limited by the staddr value. (len + staddr) should not 2123dec9fcdSqs * exceed (2^16 - 64). 2133dec9fcdSqs * Bits [43:18] of the address for the RBR. This value remains 2143dec9fcdSqs * fixed, and is used as the base address of the ring. All 2153dec9fcdSqs * entries in the ring have this as their upper address bits. 2163dec9fcdSqs * Bits [17:6] of the address of the RBR. staddrBase concatinated 2173dec9fcdSqs * with staddr is the starting address of the RBR. (len + staddr) 2183dec9fcdSqs * should not exceed (2^16 - 64). 2193dec9fcdSqs */ 2203dec9fcdSqs typedef union { 2213dec9fcdSqs uint64_t value; 2223dec9fcdSqs struct { 2233dec9fcdSqs #if defined(_BIG_ENDIAN) 224*fe930412Sqs uint32_t len:10; 225*fe930412Sqs uint32_t len_lo:6; 226*fe930412Sqs uint32_t rsrvd:4; 227*fe930412Sqs uint32_t staddr_base:12; 228*fe930412Sqs uint32_t staddr_base_l:14; 229*fe930412Sqs uint32_t staddr:12; 230*fe930412Sqs uint32_t rsrvd1:6; 2313dec9fcdSqs #else 232*fe930412Sqs uint32_t rsrvd1:6; 233*fe930412Sqs uint32_t staddr:12; 234*fe930412Sqs uint32_t staddr_base_l:14; 235*fe930412Sqs uint32_t staddr_base:12; 236*fe930412Sqs uint32_t rsrvd:4; 237*fe930412Sqs uint32_t len_lo:6; 238*fe930412Sqs uint32_t len:10; 2393dec9fcdSqs #endif 2403dec9fcdSqs } bits; 2413dec9fcdSqs } rdc_rbr_cfg_a_t; 2423dec9fcdSqs 2433dec9fcdSqs 2443dec9fcdSqs /* 2453dec9fcdSqs * Register: RdcRbrCfgB 2463dec9fcdSqs * RBR Configuration B 2473dec9fcdSqs * Description: This register configures the block size, and the 2483dec9fcdSqs * individual packet buffer sizes. The VLD bits of the three block 2493dec9fcdSqs * sizes have to be set to 1 in normal operations. These bits may be 2503dec9fcdSqs * turned off for debug purpose only. Fields in this register are 2513dec9fcdSqs * part of the dma configuration and cannot be changed once the dma 2523dec9fcdSqs * is enabled. 2533dec9fcdSqs * Fields: 2543dec9fcdSqs * Buffer Block Size. b0 - 4K; b1 - 8K. 2553dec9fcdSqs * Set to 1 to indicate SIZE2 is valid, and enable hardware to 2563dec9fcdSqs * allocate buffers of size 2. Always set to 1 in normal 2573dec9fcdSqs * operation. 2583dec9fcdSqs * Size 2 of packet buffer. b0 - 2K; b1 - 4K. 2593dec9fcdSqs * Set to 1 to indicate SIZE1 is valid, and enable hardware to 2603dec9fcdSqs * allocate buffers of size 1. Always set to 1 in normal 2613dec9fcdSqs * operation. 2623dec9fcdSqs * Size 1 of packet buffer. b0 - 1K; b1 - 2K. 2633dec9fcdSqs * Set to 1 to indicate SIZE0 is valid, and enable hardware to 2643dec9fcdSqs * allocate buffers of size 0. Always set to 1 in normal 2653dec9fcdSqs * operation. 2663dec9fcdSqs * Size 0 of packet buffer. b00 - 256; b01 - 512; b10 - 1K; b11 - 2673dec9fcdSqs * reserved. 2683dec9fcdSqs */ 2693dec9fcdSqs typedef union { 2703dec9fcdSqs uint64_t value; 2713dec9fcdSqs struct { 2723dec9fcdSqs #if defined(_BIG_ENDIAN) 273*fe930412Sqs uint32_t rsrvd:32; 274*fe930412Sqs uint32_t rsrvd_l:7; 275*fe930412Sqs uint32_t bksize:1; 276*fe930412Sqs uint32_t vld2:1; 277*fe930412Sqs uint32_t rsrvd1:6; 278*fe930412Sqs uint32_t bufsz2:1; 279*fe930412Sqs uint32_t vld1:1; 280*fe930412Sqs uint32_t rsrvd2:6; 281*fe930412Sqs uint32_t bufsz1:1; 282*fe930412Sqs uint32_t vld0:1; 283*fe930412Sqs uint32_t rsrvd3:5; 284*fe930412Sqs uint32_t bufsz0:2; 2853dec9fcdSqs #else 286*fe930412Sqs uint32_t bufsz0:2; 287*fe930412Sqs uint32_t rsrvd3:5; 288*fe930412Sqs uint32_t vld0:1; 289*fe930412Sqs uint32_t bufsz1:1; 290*fe930412Sqs uint32_t rsrvd2:6; 291*fe930412Sqs uint32_t vld1:1; 292*fe930412Sqs uint32_t bufsz2:1; 293*fe930412Sqs uint32_t rsrvd1:6; 294*fe930412Sqs uint32_t vld2:1; 295*fe930412Sqs uint32_t bksize:1; 296*fe930412Sqs uint32_t rsrvd_l:7; 297*fe930412Sqs uint32_t rsrvd:32; 2983dec9fcdSqs #endif 2993dec9fcdSqs } bits; 3003dec9fcdSqs } rdc_rbr_cfg_b_t; 3013dec9fcdSqs 3023dec9fcdSqs 3033dec9fcdSqs /* 3043dec9fcdSqs * Register: RdcRbrKick 3053dec9fcdSqs * RBR Kick 3063dec9fcdSqs * Description: Block buffer addresses are added to the ring buffer 3073dec9fcdSqs * by software. When software writes to the Kick register, indicating 3083dec9fcdSqs * the number of descriptors added, hardware will update the internal 3093dec9fcdSqs * state of the corresponding buffer pool. 3103dec9fcdSqs * HW does not check for all configuration errors across different 3113dec9fcdSqs * fields. 3123dec9fcdSqs * 3133dec9fcdSqs * Fields: 3143dec9fcdSqs * Number of Block Buffers added by software. Hardware effect 3153dec9fcdSqs * will be triggered when the register is written to. 3163dec9fcdSqs */ 3173dec9fcdSqs typedef union { 3183dec9fcdSqs uint64_t value; 3193dec9fcdSqs struct { 3203dec9fcdSqs #if defined(_BIG_ENDIAN) 321*fe930412Sqs uint32_t rsrvd:32; 322*fe930412Sqs uint32_t rsrvd_l:16; 323*fe930412Sqs uint32_t bkadd:16; 3243dec9fcdSqs #else 325*fe930412Sqs uint32_t bkadd:16; 326*fe930412Sqs uint32_t rsrvd_l:16; 327*fe930412Sqs uint32_t rsrvd:32; 3283dec9fcdSqs #endif 3293dec9fcdSqs } bits; 3303dec9fcdSqs } rdc_rbr_kick_t; 3313dec9fcdSqs 3323dec9fcdSqs 3333dec9fcdSqs /* 3343dec9fcdSqs * Register: RdcRbrQlen 3353dec9fcdSqs * RBR Queue Length 3363dec9fcdSqs * Description: The current number of entries in the RBR. 3373dec9fcdSqs * Fields: 3383dec9fcdSqs * Number of block addresses in the ring buffer. 3393dec9fcdSqs */ 3403dec9fcdSqs typedef union { 3413dec9fcdSqs uint64_t value; 3423dec9fcdSqs struct { 3433dec9fcdSqs #if defined(_BIG_ENDIAN) 344*fe930412Sqs uint32_t rsrvd:32; 345*fe930412Sqs uint32_t rsrvd_l:16; 346*fe930412Sqs uint32_t qlen:16; 3473dec9fcdSqs #else 348*fe930412Sqs uint32_t qlen:16; 349*fe930412Sqs uint32_t rsrvd_l:16; 350*fe930412Sqs uint32_t rsrvd:32; 3513dec9fcdSqs #endif 3523dec9fcdSqs } bits; 3533dec9fcdSqs } rdc_rbr_qlen_t; 3543dec9fcdSqs 3553dec9fcdSqs 3563dec9fcdSqs /* 3573dec9fcdSqs * Register: RdcRbrHead 3583dec9fcdSqs * RBR Head 3593dec9fcdSqs * Description: Lower bits of the RBR head pointer. Software programs 3603dec9fcdSqs * the upper bits, specified in rdcRbrConfigA.staddrBase. 3613dec9fcdSqs * Fields: 3623dec9fcdSqs * Bits [17:2] of the software posted address, 4B aligned. This 3633dec9fcdSqs * pointer is updated by hardware after each block buffer is 3643dec9fcdSqs * consumed. 3653dec9fcdSqs */ 3663dec9fcdSqs typedef union { 3673dec9fcdSqs uint64_t value; 3683dec9fcdSqs struct { 3693dec9fcdSqs #if defined(_BIG_ENDIAN) 370*fe930412Sqs uint32_t rsrvd:32; 371*fe930412Sqs uint32_t rsrvd_l:14; 372*fe930412Sqs uint32_t head:16; 373*fe930412Sqs uint32_t rsrvd1:2; 3743dec9fcdSqs #else 375*fe930412Sqs uint32_t rsrvd1:2; 376*fe930412Sqs uint32_t head:16; 377*fe930412Sqs uint32_t rsrvd_l:14; 378*fe930412Sqs uint32_t rsrvd:32; 3793dec9fcdSqs #endif 3803dec9fcdSqs } bits; 3813dec9fcdSqs } rdc_rbr_head_t; 3823dec9fcdSqs 3833dec9fcdSqs 3843dec9fcdSqs /* 3853dec9fcdSqs * Register: RdcRcrCfgA 3863dec9fcdSqs * RCR Configuration A 3873dec9fcdSqs * Description: The RCR should be within the 'page' defined by the 3883dec9fcdSqs * staddrBase, i.e. staddrBase concatenate with STADDR plus 8 x LEN 3893dec9fcdSqs * should be within the last address of the 'page' defined by 3903dec9fcdSqs * staddrBase. The length must be a multiple of 32. Fields in this 3913dec9fcdSqs * register are part of the dma configuration and cannot be changed 3923dec9fcdSqs * once the dma is enabled. 3933dec9fcdSqs * HW does not check for all configuration errors across different 3943dec9fcdSqs * fields. 3953dec9fcdSqs * 3963dec9fcdSqs * Fields: 3973dec9fcdSqs * Bits 15:5 of the maximum number of 8B entries in RCR. Bits 4:0 3983dec9fcdSqs * are hard-coded to zero. The maximum size is (2^16 - 32) and is 3993dec9fcdSqs * limited by staddr value. (len + staddr) should not exceed 4003dec9fcdSqs * (2^16 - 32). 4013dec9fcdSqs * Bits [43:19] of the Start address for the RCR. 4023dec9fcdSqs * Bits [18:6] of start address for the RCR. (len + staddr) 4033dec9fcdSqs * should not exceed (2^16 - 32). 4043dec9fcdSqs */ 4053dec9fcdSqs typedef union { 4063dec9fcdSqs uint64_t value; 4073dec9fcdSqs struct { 4083dec9fcdSqs #if defined(_BIG_ENDIAN) 409*fe930412Sqs uint32_t len:11; 410*fe930412Sqs uint32_t len_lo:5; 411*fe930412Sqs uint32_t rsrvd:4; 412*fe930412Sqs uint32_t staddr_base:12; 413*fe930412Sqs uint32_t staddr_base_l:13; 414*fe930412Sqs uint32_t staddr:13; 415*fe930412Sqs uint32_t rsrvd1:6; 4163dec9fcdSqs #else 417*fe930412Sqs uint32_t rsrvd1:6; 418*fe930412Sqs uint32_t staddr:13; 419*fe930412Sqs uint32_t staddr_base_l:13; 420*fe930412Sqs uint32_t staddr_base:12; 421*fe930412Sqs uint32_t rsrvd:4; 422*fe930412Sqs uint32_t len_lo:5; 423*fe930412Sqs uint32_t len:11; 4243dec9fcdSqs #endif 4253dec9fcdSqs } bits; 4263dec9fcdSqs } rdc_rcr_cfg_a_t; 4273dec9fcdSqs 4283dec9fcdSqs 4293dec9fcdSqs /* 4303dec9fcdSqs * Register: RdcRcrCfgB 4313dec9fcdSqs * RCR Configuration B 4323dec9fcdSqs * Description: RCR configuration settings. 4333dec9fcdSqs * Fields: 4343dec9fcdSqs * Packet Threshold; when the number of packets enqueued in RCR 4353dec9fcdSqs * is strictly larger than PTHRES, the DMA MAY issue an interrupt 4363dec9fcdSqs * if enabled. 4373dec9fcdSqs * Enable timeout. If set to one, enable the timeout. A timeout 4383dec9fcdSqs * will initiate an update of the software visible states. If 4393dec9fcdSqs * interrupt is armed, in addition to the update, an interrupt to 4403dec9fcdSqs * CPU will be generated, and the interrupt disarmed. 4413dec9fcdSqs * Time out value. The system clock is divided down by the value 4423dec9fcdSqs * programmed in the Receive DMA Clock Divider register. 4433dec9fcdSqs */ 4443dec9fcdSqs typedef union { 4453dec9fcdSqs uint64_t value; 4463dec9fcdSqs struct { 4473dec9fcdSqs #if defined(_BIG_ENDIAN) 448*fe930412Sqs uint32_t rsrvd:32; 449*fe930412Sqs uint32_t pthres:16; 450*fe930412Sqs uint32_t entout:1; 451*fe930412Sqs uint32_t rsrvd1:9; 452*fe930412Sqs uint32_t timeout:6; 4533dec9fcdSqs #else 454*fe930412Sqs uint32_t timeout:6; 455*fe930412Sqs uint32_t rsrvd1:9; 456*fe930412Sqs uint32_t entout:1; 457*fe930412Sqs uint32_t pthres:16; 458*fe930412Sqs uint32_t rsrvd:32; 4593dec9fcdSqs #endif 4603dec9fcdSqs } bits; 4613dec9fcdSqs } rdc_rcr_cfg_b_t; 4623dec9fcdSqs 4633dec9fcdSqs 4643dec9fcdSqs /* 4653dec9fcdSqs * Register: RdcRcrQlen 4663dec9fcdSqs * RCR Queue Length 4673dec9fcdSqs * Description: The number of entries in the RCR. 4683dec9fcdSqs * Fields: 4693dec9fcdSqs * Number of packets queued. Initialize to zero after the RCR 4703dec9fcdSqs * Configuration A register is written to. 4713dec9fcdSqs */ 4723dec9fcdSqs typedef union { 4733dec9fcdSqs uint64_t value; 4743dec9fcdSqs struct { 4753dec9fcdSqs #if defined(_BIG_ENDIAN) 476*fe930412Sqs uint32_t rsrvd:32; 477*fe930412Sqs uint32_t rsrvd_l:16; 478*fe930412Sqs uint32_t qlen:16; 4793dec9fcdSqs #else 480*fe930412Sqs uint32_t qlen:16; 481*fe930412Sqs uint32_t rsrvd_l:16; 482*fe930412Sqs uint32_t rsrvd:32; 4833dec9fcdSqs #endif 4843dec9fcdSqs } bits; 4853dec9fcdSqs } rdc_rcr_qlen_t; 4863dec9fcdSqs 4873dec9fcdSqs 4883dec9fcdSqs /* 4893dec9fcdSqs * Register: RdcRcrTail 4903dec9fcdSqs * RCR Tail 4913dec9fcdSqs * Description: Lower bits of the RCR tail pointer. Software programs 4923dec9fcdSqs * the upper bits, specified in rdcRcrConfigA.staddrBase. 4933dec9fcdSqs * Fields: 4943dec9fcdSqs * Address of the RCR Tail Pointer [18:3] (points to the next 4953dec9fcdSqs * available location.) Initialized after the RCR Configuration A 4963dec9fcdSqs * register is written to. 4973dec9fcdSqs */ 4983dec9fcdSqs typedef union { 4993dec9fcdSqs uint64_t value; 5003dec9fcdSqs struct { 5013dec9fcdSqs #if defined(_BIG_ENDIAN) 502*fe930412Sqs uint32_t rsrvd:32; 503*fe930412Sqs uint32_t rsrvd_l:13; 504*fe930412Sqs uint32_t tail:16; 505*fe930412Sqs uint32_t rsrvd1:3; 5063dec9fcdSqs #else 507*fe930412Sqs uint32_t rsrvd1:3; 508*fe930412Sqs uint32_t tail:16; 509*fe930412Sqs uint32_t rsrvd_l:13; 510*fe930412Sqs uint32_t rsrvd:32; 5113dec9fcdSqs #endif 5123dec9fcdSqs } bits; 5133dec9fcdSqs } rdc_rcr_tail_t; 5143dec9fcdSqs 5153dec9fcdSqs 5163dec9fcdSqs /* 5173dec9fcdSqs * Register: RdcRcrFlush 5183dec9fcdSqs * RCR Flush 5193dec9fcdSqs * Description: This register will force an update to the RCR in 5203dec9fcdSqs * system memory. 5213dec9fcdSqs * Fields: 5223dec9fcdSqs * Set to 1 to force the hardware to store the shadow tail block 5233dec9fcdSqs * to DRAM if the hardware state (queue length and pointers) is 5243dec9fcdSqs * different from the software visible state. Reset to 0 by 5253dec9fcdSqs * hardware when done. 5263dec9fcdSqs */ 5273dec9fcdSqs typedef union { 5283dec9fcdSqs uint64_t value; 5293dec9fcdSqs struct { 5303dec9fcdSqs #if defined(_BIG_ENDIAN) 531*fe930412Sqs uint32_t rsrvd:32; 532*fe930412Sqs uint32_t rsrvd_l:31; 533*fe930412Sqs uint32_t flush:1; 5343dec9fcdSqs #else 535*fe930412Sqs uint32_t flush:1; 536*fe930412Sqs uint32_t rsrvd_l:31; 537*fe930412Sqs uint32_t rsrvd:32; 5383dec9fcdSqs #endif 5393dec9fcdSqs } bits; 5403dec9fcdSqs } rdc_rcr_flush_t; 5413dec9fcdSqs 5423dec9fcdSqs 5433dec9fcdSqs /* 5443dec9fcdSqs * Register: RdcClockDiv 5453dec9fcdSqs * Receive DMA Clock Divider 5463dec9fcdSqs * Description: The granularity of the DMA timers is determined by 5473dec9fcdSqs * the following counter. This is used to drive the DMA timeout 5483dec9fcdSqs * counters. For a 250MHz system clock, a value of 25000 (decimal) 5493dec9fcdSqs * will yield a granularity of 100 usec. 5503dec9fcdSqs * Fields: 5513dec9fcdSqs * System clock divider, determines the granularity of the DMA 5523dec9fcdSqs * timeout count-down. The hardware count down is count+1. 5533dec9fcdSqs */ 5543dec9fcdSqs typedef union { 5553dec9fcdSqs uint64_t value; 5563dec9fcdSqs struct { 5573dec9fcdSqs #if defined(_BIG_ENDIAN) 558*fe930412Sqs uint32_t rsrvd:32; 559*fe930412Sqs uint32_t rsrvd_l:16; 560*fe930412Sqs uint32_t count:16; 5613dec9fcdSqs #else 562*fe930412Sqs uint32_t count:16; 563*fe930412Sqs uint32_t rsrvd_l:16; 564*fe930412Sqs uint32_t rsrvd:32; 5653dec9fcdSqs #endif 5663dec9fcdSqs } bits; 5673dec9fcdSqs } rdc_clock_div_t; 5683dec9fcdSqs 5693dec9fcdSqs 5703dec9fcdSqs /* 5713dec9fcdSqs * Register: RdcIntMask 5723dec9fcdSqs * RDC Interrupt Mask 5733dec9fcdSqs * Description: RDC interrupt status register. RCRTHRES and RCRTO 5743dec9fcdSqs * bits are used to keep track of normal DMA operations, while the 5753dec9fcdSqs * remaining bits are primarily used to detect error conditions. 5763dec9fcdSqs * Fields: 5773dec9fcdSqs * Set to 0 to enable flagging when rdc receives a response 5783dec9fcdSqs * completion timeout from peu. Part of LDF 1. 5793dec9fcdSqs * Set to 1 to enable flagging when rdc receives a poisoned 5803dec9fcdSqs * completion or non-zero (unsuccessful) completion status 5813dec9fcdSqs * received from PEU. Part of LDF 1. 5823dec9fcdSqs * Set to 0 to enable flagging when RCR threshold crossed. Part 5833dec9fcdSqs * of LDF 0. 5843dec9fcdSqs * Set to 0 to enable flagging when RCR timeout. Part of LDF 0. 5853dec9fcdSqs * Set to 0 to enable flagging when read from rcr shadow ram 5863dec9fcdSqs * generates a parity error Part of LDF 1. 5873dec9fcdSqs * Set to 0 to enable flagging when read from rbr prefetch ram 5883dec9fcdSqs * generates a parity error Part of LDF 1. 5893dec9fcdSqs * Set to 0 to enable flagging when Receive Block Ring prefetch 5903dec9fcdSqs * is empty (not enough buffer blocks available depending on 5913dec9fcdSqs * incoming pkt size) when hardware tries to queue a packet. 5923dec9fcdSqs * Incoming packets will be discarded. Non-fatal error. Part of 5933dec9fcdSqs * LDF 1. 5943dec9fcdSqs * Set to 0 to enable flagging when packet discard because of RCR 5953dec9fcdSqs * shadow full. 5963dec9fcdSqs * Set to 0 to enable flagging when Receive Completion Ring full 5973dec9fcdSqs * when hardware tries to enqueue the completion status of a 5983dec9fcdSqs * packet. Part of LDF 1. 5993dec9fcdSqs * Set to 0 to enable flagging when RBR empty when hardware 6003dec9fcdSqs * attempts to prefetch. Part of LDF 1. 6013dec9fcdSqs * Set to 0 to enable flagging when Receive Block Ring full when 6023dec9fcdSqs * software tries to post more blocks. Part of LDF 1. 6033dec9fcdSqs */ 6043dec9fcdSqs typedef union { 6053dec9fcdSqs uint64_t value; 6063dec9fcdSqs struct { 6073dec9fcdSqs #if defined(_BIG_ENDIAN) 608*fe930412Sqs uint32_t rsrvd:10; 609*fe930412Sqs uint32_t rbr_cpl_to:1; 610*fe930412Sqs uint32_t peu_resp_err:1; 611*fe930412Sqs uint32_t rsrvd1:5; 612*fe930412Sqs uint32_t rcr_thres:1; 613*fe930412Sqs uint32_t rcr_to:1; 614*fe930412Sqs uint32_t rcr_shadow_par_err:1; 615*fe930412Sqs uint32_t rbr_prefetch_par_err:1; 616*fe930412Sqs uint32_t rsrvd2:2; 617*fe930412Sqs uint32_t rbr_pre_empty:1; 618*fe930412Sqs uint32_t rcr_shadow_full:1; 619*fe930412Sqs uint32_t rsrvd3:2; 620*fe930412Sqs uint32_t rcr_full:1; 621*fe930412Sqs uint32_t rbr_empty:1; 622*fe930412Sqs uint32_t rbr_full:1; 623*fe930412Sqs uint32_t rsrvd4:2; 624*fe930412Sqs uint32_t rsrvd5:32; 6253dec9fcdSqs #else 626*fe930412Sqs uint32_t rsrvd5:32; 627*fe930412Sqs uint32_t rsrvd4:2; 628*fe930412Sqs uint32_t rbr_full:1; 629*fe930412Sqs uint32_t rbr_empty:1; 630*fe930412Sqs uint32_t rcr_full:1; 631*fe930412Sqs uint32_t rsrvd3:2; 632*fe930412Sqs uint32_t rcr_shadow_full:1; 633*fe930412Sqs uint32_t rbr_pre_empty:1; 634*fe930412Sqs uint32_t rsrvd2:2; 635*fe930412Sqs uint32_t rbr_prefetch_par_err:1; 636*fe930412Sqs uint32_t rcr_shadow_par_err:1; 637*fe930412Sqs uint32_t rcr_to:1; 638*fe930412Sqs uint32_t rcr_thres:1; 639*fe930412Sqs uint32_t rsrvd1:5; 640*fe930412Sqs uint32_t peu_resp_err:1; 641*fe930412Sqs uint32_t rbr_cpl_to:1; 642*fe930412Sqs uint32_t rsrvd:10; 6433dec9fcdSqs #endif 6443dec9fcdSqs } bits; 6453dec9fcdSqs } rdc_int_mask_t; 6463dec9fcdSqs 6473dec9fcdSqs 6483dec9fcdSqs /* 6493dec9fcdSqs * Register: RdcStat 6503dec9fcdSqs * RDC Control And Status 6513dec9fcdSqs * Description: The DMA channels are controlled using this register. 6523dec9fcdSqs * Fields: 6533dec9fcdSqs * Set to 1 to indicate rdc received a response completion 6543dec9fcdSqs * timeout from peu. Fatal error. Part of LDF 1. 6553dec9fcdSqs * Set to 1 to indicate poisoned completion or non-zero 6563dec9fcdSqs * (unsuccessful) completion status received from PEU. Part of 6573dec9fcdSqs * LDF 1. 6583dec9fcdSqs * Set to 1 to enable mailbox update. Hardware will reset to 0 6593dec9fcdSqs * after one update. Software needs to set to 1 for each update. 6603dec9fcdSqs * Write 0 has no effect. Note that once set by software, only 6613dec9fcdSqs * hardware can reset the value. This bit is also used to keep 6623dec9fcdSqs * track of the exclusivity between threshold triggered or 6633dec9fcdSqs * timeout triggered interrupt. If this bit is not set, there 6643dec9fcdSqs * will be no timer based interrupt, and threshold based 6653dec9fcdSqs * interrupt will not issue a mailbox update. It is recommended 6663dec9fcdSqs * that software should set this bit to one when arming the 6673dec9fcdSqs * device for interrupt. 6683dec9fcdSqs * Set to 1 to indicate RCR threshold crossed. This is a level 6693dec9fcdSqs * event. Part of LDF 0. 6703dec9fcdSqs * Set to 1 to indicate RCR time-outed if MEX bit is set and the 6713dec9fcdSqs * queue length is non-zero when timeout occurs. When software 6723dec9fcdSqs * writes 1 to this bit, RCRTO will be reset to 0. Part of LDF 0. 6733dec9fcdSqs * Set to 1 to indicate read from rcr shadow ram generates a 6743dec9fcdSqs * parity error Writing a 1 to this register also clears the 6753dec9fcdSqs * rdcshadowParLog register Fatal error. Part of LDF 1. 6763dec9fcdSqs * Set to 1 to indicate read from rbr prefetch ram generates 6773dec9fcdSqs * parity error Writing a 1 to this register also clears the 6783dec9fcdSqs * rdcPrefParLog register Fatal error. Part of LDF 1. 6793dec9fcdSqs * Set to 1 to indicate Receive Block Ring prefetch is empty (not 6803dec9fcdSqs * enough buffer blocks available depending on incoming pkt size) 6813dec9fcdSqs * when hardware tries to queue a packet. Incoming packets will 6823dec9fcdSqs * be discarded. Non-fatal error. Part of LDF 1. 6833dec9fcdSqs * Set to 1 to indicate packet discard because of RCR shadow 6843dec9fcdSqs * full. RCR Shadow full cannot be set to 1 in a normal 6853dec9fcdSqs * operation. When set to 1, it indicates a fatal error. Part of 6863dec9fcdSqs * LDF 1. 6873dec9fcdSqs * Set to 1 to indicate Receive Completion Ring full when 6883dec9fcdSqs * hardware tries to enqueue the completion status of a packet. 6893dec9fcdSqs * Incoming packets will be discarded. No buffer consumed. Fatal 6903dec9fcdSqs * error. Part of LDF 1. 6913dec9fcdSqs * Set to 1 to indicate RBR empty when hardware attempts to 6923dec9fcdSqs * prefetch. Part of LDF 1. 6933dec9fcdSqs * Set to 1 to indicate Receive Buffer Ring full when software 6943dec9fcdSqs * writes the kick register with a value greater than the length 6953dec9fcdSqs * of the RBR length. Incoming packets will be discarded. Fatal 6963dec9fcdSqs * error. Part of LDF 1. 6973dec9fcdSqs * Number of buffer pointers read. Used to advance the RCR head 6983dec9fcdSqs * pointer. 6993dec9fcdSqs * Number of packets read; when written to, decrement the QLEN 7003dec9fcdSqs * counter by PKTREAD. QLEN is lower bounded to zero. 7013dec9fcdSqs */ 7023dec9fcdSqs typedef union { 7033dec9fcdSqs uint64_t value; 7043dec9fcdSqs struct { 7053dec9fcdSqs #if defined(_BIG_ENDIAN) 706*fe930412Sqs uint32_t rsrvd:10; 707*fe930412Sqs uint32_t rbr_cpl_to:1; 708*fe930412Sqs uint32_t peu_resp_err:1; 709*fe930412Sqs uint32_t rsrvd1:4; 710*fe930412Sqs uint32_t mex:1; 711*fe930412Sqs uint32_t rcr_thres:1; 712*fe930412Sqs uint32_t rcr_to:1; 713*fe930412Sqs uint32_t rcr_shadow_par_err:1; 714*fe930412Sqs uint32_t rbr_prefetch_par_err:1; 715*fe930412Sqs uint32_t rsrvd2:2; 716*fe930412Sqs uint32_t rbr_pre_empty:1; 717*fe930412Sqs uint32_t rcr_shadow_full:1; 718*fe930412Sqs uint32_t rsrvd3:2; 719*fe930412Sqs uint32_t rcr_full:1; 720*fe930412Sqs uint32_t rbr_empty:1; 721*fe930412Sqs uint32_t rbr_full:1; 722*fe930412Sqs uint32_t rsrvd4:2; 723*fe930412Sqs uint32_t ptrread:16; 724*fe930412Sqs uint32_t pktread:16; 7253dec9fcdSqs #else 726*fe930412Sqs uint32_t pktread:16; 727*fe930412Sqs uint32_t ptrread:16; 728*fe930412Sqs uint32_t rsrvd4:2; 729*fe930412Sqs uint32_t rbr_full:1; 730*fe930412Sqs uint32_t rbr_empty:1; 731*fe930412Sqs uint32_t rcr_full:1; 732*fe930412Sqs uint32_t rsrvd3:2; 733*fe930412Sqs uint32_t rcr_shadow_full:1; 734*fe930412Sqs uint32_t rbr_pre_empty:1; 735*fe930412Sqs uint32_t rsrvd2:2; 736*fe930412Sqs uint32_t rbr_prefetch_par_err:1; 737*fe930412Sqs uint32_t rcr_shadow_par_err:1; 738*fe930412Sqs uint32_t rcr_to:1; 739*fe930412Sqs uint32_t rcr_thres:1; 740*fe930412Sqs uint32_t mex:1; 741*fe930412Sqs uint32_t rsrvd1:4; 742*fe930412Sqs uint32_t peu_resp_err:1; 743*fe930412Sqs uint32_t rbr_cpl_to:1; 744*fe930412Sqs uint32_t rsrvd:10; 7453dec9fcdSqs #endif 7463dec9fcdSqs } bits; 7473dec9fcdSqs } rdc_stat_t; 7483dec9fcdSqs 7493dec9fcdSqs 7503dec9fcdSqs /* 7513dec9fcdSqs * Register: RdcPktCount 7523dec9fcdSqs * Rx DMA Packet Counter 7533dec9fcdSqs * Description: Counts the number of packets received from the Rx 7543dec9fcdSqs * Virtual MAC for this DMA channel. 7553dec9fcdSqs * Fields: 7563dec9fcdSqs * Count of SYN packets received from RVM. This counter 7573dec9fcdSqs * saturates. 7583dec9fcdSqs * Count of packets received from RVM. This counter saturates. 7593dec9fcdSqs */ 7603dec9fcdSqs typedef union { 7613dec9fcdSqs uint64_t value; 7623dec9fcdSqs struct { 7633dec9fcdSqs #if defined(_BIG_ENDIAN) 764*fe930412Sqs uint32_t syn_pkt_count:32; 765*fe930412Sqs uint32_t pkt_count:32; 7663dec9fcdSqs #else 767*fe930412Sqs uint32_t pkt_count:32; 768*fe930412Sqs uint32_t syn_pkt_count:32; 7693dec9fcdSqs #endif 7703dec9fcdSqs } bits; 7713dec9fcdSqs } rdc_pkt_count_t; 7723dec9fcdSqs 7733dec9fcdSqs 7743dec9fcdSqs /* 7753dec9fcdSqs * Register: RdcDropCount 7763dec9fcdSqs * Rx DMA Dropped Packet Counters 7773dec9fcdSqs * Description: Counts the number of packets dropped due to different 7783dec9fcdSqs * types of errors. 7793dec9fcdSqs * Fields: 7803dec9fcdSqs * Count of packets dropped because they were longer than the 7813dec9fcdSqs * maximum length. This counter saturates. 7823dec9fcdSqs * Count of packets dropped because there was no block available 7833dec9fcdSqs * in the RBR Prefetch Buffer. This counter saturates. 7843dec9fcdSqs * Count of packets dropped because the RVM marked the packet as 7853dec9fcdSqs * errored. This counter saturates. 7863dec9fcdSqs * Count of packets dropped because there was a framing error 7873dec9fcdSqs * from the RVM. This counter saturates. 7883dec9fcdSqs * Count of packets dropped because the packet did not fit in the 7893dec9fcdSqs * rx ram. This counter saturates. 7903dec9fcdSqs */ 7913dec9fcdSqs typedef union { 7923dec9fcdSqs uint64_t value; 7933dec9fcdSqs struct { 7943dec9fcdSqs #if defined(_BIG_ENDIAN) 795*fe930412Sqs uint32_t rsrvd:16; 796*fe930412Sqs uint32_t too_long:8; 797*fe930412Sqs uint32_t no_rbr_avail:8; 798*fe930412Sqs uint32_t rvm_error:8; 799*fe930412Sqs uint32_t frame_error:8; 800*fe930412Sqs uint32_t rxram_error:8; 801*fe930412Sqs uint32_t rsrvd1:8; 8023dec9fcdSqs #else 803*fe930412Sqs uint32_t rsrvd1:8; 804*fe930412Sqs uint32_t rxram_error:8; 805*fe930412Sqs uint32_t frame_error:8; 806*fe930412Sqs uint32_t rvm_error:8; 807*fe930412Sqs uint32_t no_rbr_avail:8; 808*fe930412Sqs uint32_t too_long:8; 809*fe930412Sqs uint32_t rsrvd:16; 8103dec9fcdSqs #endif 8113dec9fcdSqs } bits; 8123dec9fcdSqs } rdc_drop_count_t; 8133dec9fcdSqs 8143dec9fcdSqs 8153dec9fcdSqs /* 8163dec9fcdSqs * Register: RdcByteCount 8173dec9fcdSqs * Rx DMA Byte Counter 8183dec9fcdSqs * Description: Counts the number of bytes transferred by dma for all 8193dec9fcdSqs * channels. 8203dec9fcdSqs * Fields: 8213dec9fcdSqs * Count of bytes transferred by dma. This counter saturates. 8223dec9fcdSqs */ 8233dec9fcdSqs typedef union { 8243dec9fcdSqs uint64_t value; 8253dec9fcdSqs struct { 8263dec9fcdSqs #if defined(_BIG_ENDIAN) 827*fe930412Sqs uint32_t rsrvd:32; 828*fe930412Sqs uint32_t count:32; 8293dec9fcdSqs #else 830*fe930412Sqs uint32_t count:32; 831*fe930412Sqs uint32_t rsrvd:32; 8323dec9fcdSqs #endif 8333dec9fcdSqs } bits; 8343dec9fcdSqs } rdc_byte_count_t; 8353dec9fcdSqs 8363dec9fcdSqs 8373dec9fcdSqs /* 8383dec9fcdSqs * Register: RdcPrefCmd 8393dec9fcdSqs * Rx DMA Prefetch Buffer Command 8403dec9fcdSqs * Description: Allows debug access to the entire prefetch buffer, 8413dec9fcdSqs * along with the rdcPrefData register. Writing the rdcPrefCmd 8423dec9fcdSqs * triggers the access. For writes, software writes the 32 bits of 8433dec9fcdSqs * data to the rdcPrefData register before writing the write command 8443dec9fcdSqs * to this register. For reads, software first writes the the read 8453dec9fcdSqs * command to this register, then reads the 32-bit value from the 8463dec9fcdSqs * rdcPrefData register. The status field should be polled by 8473dec9fcdSqs * software until it goes low, indicating the read or write has 8483dec9fcdSqs * completed. 8493dec9fcdSqs * Fields: 8503dec9fcdSqs * status of indirect access 0=busy 1=done 8513dec9fcdSqs * Command type. 1 indicates a read command, 0 a write command. 8523dec9fcdSqs * enable writing of parity bits 1=enabled, 0=disabled 8533dec9fcdSqs * DMA channel of entry to read or write 8543dec9fcdSqs * Entry in the prefetch buffer to read or write 8553dec9fcdSqs */ 8563dec9fcdSqs typedef union { 8573dec9fcdSqs uint64_t value; 8583dec9fcdSqs struct { 8593dec9fcdSqs #if defined(_BIG_ENDIAN) 860*fe930412Sqs uint32_t rsrvd:32; 861*fe930412Sqs uint32_t status:1; 862*fe930412Sqs uint32_t cmd:1; 863*fe930412Sqs uint32_t par_en:1; 864*fe930412Sqs uint32_t rsrvd1:22; 865*fe930412Sqs uint32_t dmc:2; 866*fe930412Sqs uint32_t entry:5; 8673dec9fcdSqs #else 868*fe930412Sqs uint32_t entry:5; 869*fe930412Sqs uint32_t dmc:2; 870*fe930412Sqs uint32_t rsrvd1:22; 871*fe930412Sqs uint32_t par_en:1; 872*fe930412Sqs uint32_t cmd:1; 873*fe930412Sqs uint32_t status:1; 874*fe930412Sqs uint32_t rsrvd:32; 8753dec9fcdSqs #endif 8763dec9fcdSqs } bits; 8773dec9fcdSqs } rdc_pref_cmd_t; 8783dec9fcdSqs 8793dec9fcdSqs 8803dec9fcdSqs /* 8813dec9fcdSqs * Register: RdcPrefData 8823dec9fcdSqs * Rx DMA Prefetch Buffer Data 8833dec9fcdSqs * Description: See rdcPrefCmd register. 8843dec9fcdSqs * Fields: 8853dec9fcdSqs * For writes, parity bits is written into prefetch buffer. For 8863dec9fcdSqs * reads, parity bits read from the prefetch buffer. 8873dec9fcdSqs * For writes, data which is written into prefetch buffer. For 8883dec9fcdSqs * reads, data read from the prefetch buffer. 8893dec9fcdSqs */ 8903dec9fcdSqs typedef union { 8913dec9fcdSqs uint64_t value; 8923dec9fcdSqs struct { 8933dec9fcdSqs #if defined(_BIG_ENDIAN) 894*fe930412Sqs uint32_t rsrvd:28; 895*fe930412Sqs uint32_t par:4; 896*fe930412Sqs uint32_t data:32; 8973dec9fcdSqs #else 898*fe930412Sqs uint32_t data:32; 899*fe930412Sqs uint32_t par:4; 900*fe930412Sqs uint32_t rsrvd:28; 9013dec9fcdSqs #endif 9023dec9fcdSqs } bits; 9033dec9fcdSqs } rdc_pref_data_t; 9043dec9fcdSqs 9053dec9fcdSqs 9063dec9fcdSqs /* 9073dec9fcdSqs * Register: RdcShadowCmd 9083dec9fcdSqs * Rx DMA Shadow Tail Command 9093dec9fcdSqs * Description: Allows debug access to the entire shadow tail, along 9103dec9fcdSqs * with the rdcShadowData register. Writing the rdcShadowCmd triggers 9113dec9fcdSqs * the access. For writes, software writes the 64 bits of data to the 9123dec9fcdSqs * rdcShadowData register before writing the write command to this 9133dec9fcdSqs * register. For reads, software first writes the the read command to 9143dec9fcdSqs * this register, then reads the 64-bit value from the rdcShadowData 9153dec9fcdSqs * register. The valid field should be polled by software until it 9163dec9fcdSqs * goes low, indicating the read or write has completed. 9173dec9fcdSqs * Fields: 9183dec9fcdSqs * status of indirect access 0=busy 1=done 9193dec9fcdSqs * Command type. 1 indicates a read command, 0 a write command. 9203dec9fcdSqs * enable writing of parity bits 1=enabled, 0=disabled 9213dec9fcdSqs * DMA channel of entry to read or write 9223dec9fcdSqs * Entry in the shadow tail to read or write 9233dec9fcdSqs */ 9243dec9fcdSqs typedef union { 9253dec9fcdSqs uint64_t value; 9263dec9fcdSqs struct { 9273dec9fcdSqs #if defined(_BIG_ENDIAN) 928*fe930412Sqs uint32_t rsrvd:32; 929*fe930412Sqs uint32_t status:1; 930*fe930412Sqs uint32_t cmd:1; 931*fe930412Sqs uint32_t par_en:1; 932*fe930412Sqs uint32_t rsrvd1:23; 933*fe930412Sqs uint32_t dmc:2; 934*fe930412Sqs uint32_t entry:4; 9353dec9fcdSqs #else 936*fe930412Sqs uint32_t entry:4; 937*fe930412Sqs uint32_t dmc:2; 938*fe930412Sqs uint32_t rsrvd1:23; 939*fe930412Sqs uint32_t par_en:1; 940*fe930412Sqs uint32_t cmd:1; 941*fe930412Sqs uint32_t status:1; 942*fe930412Sqs uint32_t rsrvd:32; 9433dec9fcdSqs #endif 9443dec9fcdSqs } bits; 9453dec9fcdSqs } rdc_shadow_cmd_t; 9463dec9fcdSqs 9473dec9fcdSqs 9483dec9fcdSqs /* 9493dec9fcdSqs * Register: RdcShadowData 9503dec9fcdSqs * Rx DMA Shadow Tail Data 9513dec9fcdSqs * Description: See rdcShadowCmd register. 9523dec9fcdSqs * Fields: 9533dec9fcdSqs * For writes, data which is written into shadow tail. For reads, 9543dec9fcdSqs * data read from the shadow tail. 9553dec9fcdSqs */ 9563dec9fcdSqs typedef union { 9573dec9fcdSqs uint64_t value; 9583dec9fcdSqs struct { 9593dec9fcdSqs #if defined(_BIG_ENDIAN) 960*fe930412Sqs uint32_t data:32; 961*fe930412Sqs uint32_t data_l:32; 9623dec9fcdSqs #else 963*fe930412Sqs uint32_t data_l:32; 964*fe930412Sqs uint32_t data:32; 9653dec9fcdSqs #endif 9663dec9fcdSqs } bits; 9673dec9fcdSqs } rdc_shadow_data_t; 9683dec9fcdSqs 9693dec9fcdSqs 9703dec9fcdSqs /* 9713dec9fcdSqs * Register: RdcShadowParData 9723dec9fcdSqs * Rx DMA Shadow Tail Parity Data 9733dec9fcdSqs * Description: See rdcShadowCmd register. 9743dec9fcdSqs * Fields: 9753dec9fcdSqs * For writes, parity data is written into shadow tail. For 9763dec9fcdSqs * reads, parity data read from the shadow tail. 9773dec9fcdSqs */ 9783dec9fcdSqs typedef union { 9793dec9fcdSqs uint64_t value; 9803dec9fcdSqs struct { 9813dec9fcdSqs #if defined(_BIG_ENDIAN) 982*fe930412Sqs uint32_t rsrvd:32; 983*fe930412Sqs uint32_t rsrvd1:24; 984*fe930412Sqs uint32_t parity_data:8; 9853dec9fcdSqs #else 986*fe930412Sqs uint32_t parity_data:8; 987*fe930412Sqs uint32_t rsrvd1:24; 988*fe930412Sqs uint32_t rsrvd:32; 9893dec9fcdSqs #endif 9903dec9fcdSqs } bits; 9913dec9fcdSqs } rdc_shadow_par_data_t; 9923dec9fcdSqs 9933dec9fcdSqs 9943dec9fcdSqs /* 9953dec9fcdSqs * Register: RdcCtrlFifoCmd 9963dec9fcdSqs * Rx DMA Control Fifo Command 9973dec9fcdSqs * Description: Allows debug access to the entire Rx Ctl FIFO, along 9983dec9fcdSqs * with the rdcCtrlFifoData register. Writing the rdcCtrlFifoCmd 9993dec9fcdSqs * triggers the access. For writes, software writes the 128 bits of 10003dec9fcdSqs * data to the rdcCtrlFifoData registers before writing the write 10013dec9fcdSqs * command to this register. For reads, software first writes the the 10023dec9fcdSqs * read command to this register, then reads the 128-bit value from 10033dec9fcdSqs * the rdcCtrlFifoData registers. The valid field should be polled by 10043dec9fcdSqs * software until it goes low, indicating the read or write has 10053dec9fcdSqs * completed. 10063dec9fcdSqs * Fields: 10073dec9fcdSqs * status of indirect access 0=busy 1=done 10083dec9fcdSqs * Command type. 1 indicates a read command, 0 a write command. 10093dec9fcdSqs * enable writing of ECC bits 1=enabled, 0=disabled 10103dec9fcdSqs * Entry in the rx control ram to read or write 10113dec9fcdSqs */ 10123dec9fcdSqs typedef union { 10133dec9fcdSqs uint64_t value; 10143dec9fcdSqs struct { 10153dec9fcdSqs #if defined(_BIG_ENDIAN) 1016*fe930412Sqs uint32_t rsrvd:32; 1017*fe930412Sqs uint32_t status:1; 1018*fe930412Sqs uint32_t cmd:1; 1019*fe930412Sqs uint32_t ecc_en:1; 1020*fe930412Sqs uint32_t rsrvd1:20; 1021*fe930412Sqs uint32_t entry:9; 10223dec9fcdSqs #else 1023*fe930412Sqs uint32_t entry:9; 1024*fe930412Sqs uint32_t rsrvd1:20; 1025*fe930412Sqs uint32_t ecc_en:1; 1026*fe930412Sqs uint32_t cmd:1; 1027*fe930412Sqs uint32_t status:1; 1028*fe930412Sqs uint32_t rsrvd:32; 10293dec9fcdSqs #endif 10303dec9fcdSqs } bits; 10313dec9fcdSqs } rdc_ctrl_fifo_cmd_t; 10323dec9fcdSqs 10333dec9fcdSqs 10343dec9fcdSqs /* 10353dec9fcdSqs * Register: RdcCtrlFifoDataLo 10363dec9fcdSqs * Rx DMA Control Fifo Data Lo 10373dec9fcdSqs * Description: Lower 64 bits read or written to the Rx Ctl FIFO. See 10383dec9fcdSqs * rdcCtrlFifoCmd register. 10393dec9fcdSqs * Fields: 10403dec9fcdSqs * For writes, data which is written into rx control ram. For 10413dec9fcdSqs * reads, data read from the rx control ram. 10423dec9fcdSqs */ 10433dec9fcdSqs typedef union { 10443dec9fcdSqs uint64_t value; 10453dec9fcdSqs struct { 10463dec9fcdSqs #if defined(_BIG_ENDIAN) 1047*fe930412Sqs uint32_t data:32; 1048*fe930412Sqs uint32_t data_l:32; 10493dec9fcdSqs #else 1050*fe930412Sqs uint32_t data_l:32; 1051*fe930412Sqs uint32_t data:32; 10523dec9fcdSqs #endif 10533dec9fcdSqs } bits; 10543dec9fcdSqs } rdc_ctrl_fifo_data_lo_t; 10553dec9fcdSqs 10563dec9fcdSqs 10573dec9fcdSqs /* 10583dec9fcdSqs * Register: RdcCtrlFifoDataHi 10593dec9fcdSqs * Rx DMA Control Fifo Data Hi 10603dec9fcdSqs * Description: Upper 64 bits read or written to the Rx Ctl FIFO. See 10613dec9fcdSqs * rdcCtrlFifoCmd register. 10623dec9fcdSqs * Fields: 10633dec9fcdSqs * For writes, data which is written into rx control ram. For 10643dec9fcdSqs * reads, data read from the rx control ram. 10653dec9fcdSqs */ 10663dec9fcdSqs typedef union { 10673dec9fcdSqs uint64_t value; 10683dec9fcdSqs struct { 10693dec9fcdSqs #if defined(_BIG_ENDIAN) 1070*fe930412Sqs uint32_t data:32; 1071*fe930412Sqs uint32_t data_l:32; 10723dec9fcdSqs #else 1073*fe930412Sqs uint32_t data_l:32; 1074*fe930412Sqs uint32_t data:32; 10753dec9fcdSqs #endif 10763dec9fcdSqs } bits; 10773dec9fcdSqs } rdc_ctrl_fifo_data_hi_t; 10783dec9fcdSqs 10793dec9fcdSqs 10803dec9fcdSqs /* 10813dec9fcdSqs * Register: RdcCtrlFifoDataEcc 10823dec9fcdSqs * Rx DMA Control Fifo Data ECC 10833dec9fcdSqs * Description: 16 bits ECC data read or written to the Rx Ctl FIFO. 10843dec9fcdSqs * See rdcCtrlFifoCmd register. 10853dec9fcdSqs * Fields: 10863dec9fcdSqs * For writes, data which is written into rx control ram. For 10873dec9fcdSqs * reads, data read from the rx control ram. 10883dec9fcdSqs * For writes, data which is written into rx control ram. For 10893dec9fcdSqs * reads, data read from the rx control ram. 10903dec9fcdSqs */ 10913dec9fcdSqs typedef union { 10923dec9fcdSqs uint64_t value; 10933dec9fcdSqs struct { 10943dec9fcdSqs #if defined(_BIG_ENDIAN) 1095*fe930412Sqs uint32_t rsrvd:32; 1096*fe930412Sqs uint32_t rsrvd1:16; 1097*fe930412Sqs uint32_t ecc_data_hi:8; 1098*fe930412Sqs uint32_t ecc_data_lo:8; 10993dec9fcdSqs #else 1100*fe930412Sqs uint32_t ecc_data_lo:8; 1101*fe930412Sqs uint32_t ecc_data_hi:8; 1102*fe930412Sqs uint32_t rsrvd1:16; 1103*fe930412Sqs uint32_t rsrvd:32; 11043dec9fcdSqs #endif 11053dec9fcdSqs } bits; 11063dec9fcdSqs } rdc_ctrl_fifo_data_ecc_t; 11073dec9fcdSqs 11083dec9fcdSqs 11093dec9fcdSqs /* 11103dec9fcdSqs * Register: RdcDataFifoCmd 11113dec9fcdSqs * Rx DMA Data Fifo Command 11123dec9fcdSqs * Description: Allows debug access to the entire Rx Data FIFO, along 11133dec9fcdSqs * with the rdcDataFifoData register. Writing the rdcCtrlFifoCmd 11143dec9fcdSqs * triggers the access. For writes, software writes the 128 bits of 11153dec9fcdSqs * data to the rdcDataFifoData registers before writing the write 11163dec9fcdSqs * command to this register. For reads, software first writes the the 11173dec9fcdSqs * read command to this register, then reads the 128-bit value from 11183dec9fcdSqs * the rdcDataFifoData registers. The valid field should be polled by 11193dec9fcdSqs * software until it goes low, indicating the read or write has 11203dec9fcdSqs * completed. 11213dec9fcdSqs * Fields: 11223dec9fcdSqs * status of indirect access 0=busy 1=done 11233dec9fcdSqs * Command type. 1 indicates a read command, 0 a write command. 11243dec9fcdSqs * enable writing of ECC bits 1=enabled, 0=disabled 11253dec9fcdSqs * Entry in the rx data ram to read or write 11263dec9fcdSqs */ 11273dec9fcdSqs typedef union { 11283dec9fcdSqs uint64_t value; 11293dec9fcdSqs struct { 11303dec9fcdSqs #if defined(_BIG_ENDIAN) 1131*fe930412Sqs uint32_t rsrvd:32; 1132*fe930412Sqs uint32_t status:1; 1133*fe930412Sqs uint32_t cmd:1; 1134*fe930412Sqs uint32_t ecc_en:1; 1135*fe930412Sqs uint32_t rsrvd1:18; 1136*fe930412Sqs uint32_t entry:11; 11373dec9fcdSqs #else 1138*fe930412Sqs uint32_t entry:11; 1139*fe930412Sqs uint32_t rsrvd1:18; 1140*fe930412Sqs uint32_t ecc_en:1; 1141*fe930412Sqs uint32_t cmd:1; 1142*fe930412Sqs uint32_t status:1; 1143*fe930412Sqs uint32_t rsrvd:32; 11443dec9fcdSqs #endif 11453dec9fcdSqs } bits; 11463dec9fcdSqs } rdc_data_fifo_cmd_t; 11473dec9fcdSqs 11483dec9fcdSqs 11493dec9fcdSqs /* 11503dec9fcdSqs * Register: RdcDataFifoDataLo 11513dec9fcdSqs * Rx DMA Data Fifo Data Lo 11523dec9fcdSqs * Description: Lower 64 bits read or written to the Rx Data FIFO. 11533dec9fcdSqs * See rdcDataFifoCmd register. 11543dec9fcdSqs * Fields: 11553dec9fcdSqs * For writes, data which is written into rx data ram. For reads, 11563dec9fcdSqs * data read from the rx data ram. 11573dec9fcdSqs */ 11583dec9fcdSqs typedef union { 11593dec9fcdSqs uint64_t value; 11603dec9fcdSqs struct { 11613dec9fcdSqs #if defined(_BIG_ENDIAN) 1162*fe930412Sqs uint32_t data:32; 1163*fe930412Sqs uint32_t data_l:32; 11643dec9fcdSqs #else 1165*fe930412Sqs uint32_t data_l:32; 1166*fe930412Sqs uint32_t data:32; 11673dec9fcdSqs #endif 11683dec9fcdSqs } bits; 11693dec9fcdSqs } rdc_data_fifo_data_lo_t; 11703dec9fcdSqs 11713dec9fcdSqs 11723dec9fcdSqs /* 11733dec9fcdSqs * Register: RdcDataFifoDataHi 11743dec9fcdSqs * Rx DMA Data Fifo Data Hi 11753dec9fcdSqs * Description: Upper 64 bits read or written to the Rx Data FIFO. 11763dec9fcdSqs * See rdcDataFifoCmd register. 11773dec9fcdSqs * Fields: 11783dec9fcdSqs * For writes, data which is written into rx data ram. For reads, 11793dec9fcdSqs * data read from the rx data ram. 11803dec9fcdSqs */ 11813dec9fcdSqs typedef union { 11823dec9fcdSqs uint64_t value; 11833dec9fcdSqs struct { 11843dec9fcdSqs #if defined(_BIG_ENDIAN) 1185*fe930412Sqs uint32_t data:32; 1186*fe930412Sqs uint32_t data_l:32; 11873dec9fcdSqs #else 1188*fe930412Sqs uint32_t data_l:32; 1189*fe930412Sqs uint32_t data:32; 11903dec9fcdSqs #endif 11913dec9fcdSqs } bits; 11923dec9fcdSqs } rdc_data_fifo_data_hi_t; 11933dec9fcdSqs 11943dec9fcdSqs 11953dec9fcdSqs /* 11963dec9fcdSqs * Register: RdcDataFifoDataEcc 11973dec9fcdSqs * Rx DMA Data Fifo ECC Data 11983dec9fcdSqs * Description: 16 bits ECC data read or written to the Rx Data FIFO. 11993dec9fcdSqs * See rdcDataFifoCmd register. 12003dec9fcdSqs * Fields: 12013dec9fcdSqs * For writes, data which is written into rx data ram. For reads, 12023dec9fcdSqs * data read from the rx data ram. 12033dec9fcdSqs * For writes, data which is written into rx data ram. For reads, 12043dec9fcdSqs * data read from the rx data ram. 12053dec9fcdSqs */ 12063dec9fcdSqs typedef union { 12073dec9fcdSqs uint64_t value; 12083dec9fcdSqs struct { 12093dec9fcdSqs #if defined(_BIG_ENDIAN) 1210*fe930412Sqs uint32_t rsrvd:32; 1211*fe930412Sqs uint32_t rsrvd1:16; 1212*fe930412Sqs uint32_t ecc_data_hi:8; 1213*fe930412Sqs uint32_t ecc_data_lo:8; 12143dec9fcdSqs #else 1215*fe930412Sqs uint32_t ecc_data_lo:8; 1216*fe930412Sqs uint32_t ecc_data_hi:8; 1217*fe930412Sqs uint32_t rsrvd1:16; 1218*fe930412Sqs uint32_t rsrvd:32; 12193dec9fcdSqs #endif 12203dec9fcdSqs } bits; 12213dec9fcdSqs } rdc_data_fifo_data_ecc_t; 12223dec9fcdSqs 12233dec9fcdSqs 12243dec9fcdSqs /* 12253dec9fcdSqs * Register: RdcStatIntDbg 12263dec9fcdSqs * RDC Debug Control and Status Interrupt 12273dec9fcdSqs * Description: RDC debug control and status interrupt register. 12283dec9fcdSqs * Debug RDC control and status register bits to check if interrupt 12293dec9fcdSqs * is asserted used to detect error conditions. 12303dec9fcdSqs * Fields: 12313dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12323dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12333dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 0. 12343dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 0. 12353dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12363dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12373dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12383dec9fcdSqs * Set to 1 to enable interrupt 12393dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12403dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12413dec9fcdSqs * Set to 1 to enable interrupt Part of LDF 1. 12423dec9fcdSqs */ 12433dec9fcdSqs typedef union { 12443dec9fcdSqs uint64_t value; 12453dec9fcdSqs struct { 12463dec9fcdSqs #if defined(_BIG_ENDIAN) 1247*fe930412Sqs uint32_t rsrvd:10; 1248*fe930412Sqs uint32_t rbr_cpl_to:1; 1249*fe930412Sqs uint32_t peu_resp_err:1; 1250*fe930412Sqs uint32_t rsrvd1:5; 1251*fe930412Sqs uint32_t rcr_thres:1; 1252*fe930412Sqs uint32_t rcr_to:1; 1253*fe930412Sqs uint32_t rcr_shadow_par_err:1; 1254*fe930412Sqs uint32_t rbr_prefetch_par_err:1; 1255*fe930412Sqs uint32_t rsrvd2:2; 1256*fe930412Sqs uint32_t rbr_pre_empty:1; 1257*fe930412Sqs uint32_t rcr_shadow_full:1; 1258*fe930412Sqs uint32_t rsrvd3:2; 1259*fe930412Sqs uint32_t rcr_full:1; 1260*fe930412Sqs uint32_t rbr_empty:1; 1261*fe930412Sqs uint32_t rbr_full:1; 1262*fe930412Sqs uint32_t rsrvd4:2; 1263*fe930412Sqs uint32_t rsrvd5:32; 12643dec9fcdSqs #else 1265*fe930412Sqs uint32_t rsrvd5:32; 1266*fe930412Sqs uint32_t rsrvd4:2; 1267*fe930412Sqs uint32_t rbr_full:1; 1268*fe930412Sqs uint32_t rbr_empty:1; 1269*fe930412Sqs uint32_t rcr_full:1; 1270*fe930412Sqs uint32_t rsrvd3:2; 1271*fe930412Sqs uint32_t rcr_shadow_full:1; 1272*fe930412Sqs uint32_t rbr_pre_empty:1; 1273*fe930412Sqs uint32_t rsrvd2:2; 1274*fe930412Sqs uint32_t rbr_prefetch_par_err:1; 1275*fe930412Sqs uint32_t rcr_shadow_par_err:1; 1276*fe930412Sqs uint32_t rcr_to:1; 1277*fe930412Sqs uint32_t rcr_thres:1; 1278*fe930412Sqs uint32_t rsrvd1:5; 1279*fe930412Sqs uint32_t peu_resp_err:1; 1280*fe930412Sqs uint32_t rbr_cpl_to:1; 1281*fe930412Sqs uint32_t rsrvd:10; 12823dec9fcdSqs #endif 12833dec9fcdSqs } bits; 12843dec9fcdSqs } rdc_stat_int_dbg_t; 12853dec9fcdSqs 12863dec9fcdSqs 12873dec9fcdSqs /* 12883dec9fcdSqs * Register: RdcPrefParLog 12893dec9fcdSqs * Rx DMA Prefetch Buffer Parity Log 12903dec9fcdSqs * Description: RDC DMA Prefetch Buffer parity log register This 12913dec9fcdSqs * register logs the first parity error that is encountered. Writing 12923dec9fcdSqs * a 1 to RdcStat::rbrPrefetchParErr clears this register 12933dec9fcdSqs * Fields: 12943dec9fcdSqs * Address of parity error 12953dec9fcdSqs */ 12963dec9fcdSqs typedef union { 12973dec9fcdSqs uint64_t value; 12983dec9fcdSqs struct { 12993dec9fcdSqs #if defined(_BIG_ENDIAN) 1300*fe930412Sqs uint32_t rsrvd:32; 1301*fe930412Sqs uint32_t rsrvd_l:25; 1302*fe930412Sqs uint32_t address:7; 13033dec9fcdSqs #else 1304*fe930412Sqs uint32_t address:7; 1305*fe930412Sqs uint32_t rsrvd_l:25; 1306*fe930412Sqs uint32_t rsrvd:32; 13073dec9fcdSqs #endif 13083dec9fcdSqs } bits; 13093dec9fcdSqs } rdc_pref_par_log_t; 13103dec9fcdSqs 13113dec9fcdSqs 13123dec9fcdSqs /* 13133dec9fcdSqs * Register: RdcShadowParLog 13143dec9fcdSqs * Rx DMA Shadow Tail Parity Log 13153dec9fcdSqs * Description: RDC DMA Shadow Tail parity log register This register 13163dec9fcdSqs * logs the first parity error that is encountered. Writing a 1 to 13173dec9fcdSqs * RdcStat::rcrShadowParErr clears this register 13183dec9fcdSqs * Fields: 13193dec9fcdSqs * Address of parity error 13203dec9fcdSqs */ 13213dec9fcdSqs typedef union { 13223dec9fcdSqs uint64_t value; 13233dec9fcdSqs struct { 13243dec9fcdSqs #if defined(_BIG_ENDIAN) 1325*fe930412Sqs uint32_t rsrvd:32; 1326*fe930412Sqs uint32_t rsrvd1:26; 1327*fe930412Sqs uint32_t address:6; 13283dec9fcdSqs #else 1329*fe930412Sqs uint32_t address:6; 1330*fe930412Sqs uint32_t rsrvd1:26; 1331*fe930412Sqs uint32_t rsrvd:32; 13323dec9fcdSqs #endif 13333dec9fcdSqs } bits; 13343dec9fcdSqs } rdc_shadow_par_log_t; 13353dec9fcdSqs 13363dec9fcdSqs 13373dec9fcdSqs /* 13383dec9fcdSqs * Register: RdcCtrlFifoEccLog 13393dec9fcdSqs * Rx DMA Control Fifo ECC Log 13403dec9fcdSqs * Description: RDC DMA Control FIFO ECC log register This register 13413dec9fcdSqs * logs the first ECC error that is encountered. A double-bit ecc 13423dec9fcdSqs * error over writes any single-bit ecc error previously logged 13433dec9fcdSqs * Fields: 13443dec9fcdSqs * Address of ECC error for upper 64 bits Writing a 1 to 13453dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoDed[1] or 13463dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoSec[1] clears this register 13473dec9fcdSqs * Address of ECC error for lower 64 bits Writing a 1 to 13483dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoDed[0] or 13493dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoSec[0] clears this register 13503dec9fcdSqs * ECC syndrome for upper 64 bits Writing a 1 to 13513dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoDed[1] or 13523dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoSec[1] clears this register 13533dec9fcdSqs * ECC syndrome for lower 64 bits Writing a 1 to 13543dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoDed[0] or 13553dec9fcdSqs * RdcFifoErrStat::rxCtrlFifoSec[0] clears this register 13563dec9fcdSqs */ 13573dec9fcdSqs typedef union { 13583dec9fcdSqs uint64_t value; 13593dec9fcdSqs struct { 13603dec9fcdSqs #if defined(_BIG_ENDIAN) 1361*fe930412Sqs uint32_t rsrvd:7; 1362*fe930412Sqs uint32_t address_hi:9; 1363*fe930412Sqs uint32_t rsrvd1:7; 1364*fe930412Sqs uint32_t address_lo:9; 1365*fe930412Sqs uint32_t rsrvd2:8; 1366*fe930412Sqs uint32_t syndrome_hi:8; 1367*fe930412Sqs uint32_t rsrvd3:8; 1368*fe930412Sqs uint32_t syndrome_lo:8; 13693dec9fcdSqs #else 1370*fe930412Sqs uint32_t syndrome_lo:8; 1371*fe930412Sqs uint32_t rsrvd3:8; 1372*fe930412Sqs uint32_t syndrome_hi:8; 1373*fe930412Sqs uint32_t rsrvd2:8; 1374*fe930412Sqs uint32_t address_lo:9; 1375*fe930412Sqs uint32_t rsrvd1:7; 1376*fe930412Sqs uint32_t address_hi:9; 1377*fe930412Sqs uint32_t rsrvd:7; 13783dec9fcdSqs #endif 13793dec9fcdSqs } bits; 13803dec9fcdSqs } rdc_ctrl_fifo_ecc_log_t; 13813dec9fcdSqs 13823dec9fcdSqs 13833dec9fcdSqs /* 13843dec9fcdSqs * Register: RdcDataFifoEccLog 13853dec9fcdSqs * Rx DMA Data Fifo ECC Log 13863dec9fcdSqs * Description: RDC DMA data FIFO ECC log register This register logs 13873dec9fcdSqs * the first ECC error that is encountered. A double-bit ecc error 13883dec9fcdSqs * over writes any single-bit ecc error previously logged 13893dec9fcdSqs * Fields: 13903dec9fcdSqs * Address of ECC error for upper 64 bits Writing a 1 to 13913dec9fcdSqs * RdcFifoErrStat::rxDataFifoDed[1] or 13923dec9fcdSqs * RdcFifoErrStat::rxDataFifoSec[1] clears this register 13933dec9fcdSqs * Address of ECC error for lower 64 bits Writing a 1 to 13943dec9fcdSqs * RdcFifoErrStat::rxDataFifoDed[0] or 13953dec9fcdSqs * RdcFifoErrStat::rxDataFifoSec[0] clears this register 13963dec9fcdSqs * ECC syndrome for upper 64 bits Writing a 1 to 13973dec9fcdSqs * RdcFifoErrStat::rxDataFifoDed[1] or 13983dec9fcdSqs * RdcFifoErrStat::rxDataFifoSec[1] clears this register 13993dec9fcdSqs * ECC syndrome for lower 64 bits Writing a 1 to 14003dec9fcdSqs * RdcFifoErrStat::rxDataFifoDed[0] or 14013dec9fcdSqs * RdcFifoErrStat::rxDataFifoSec[0] clears this register 14023dec9fcdSqs */ 14033dec9fcdSqs typedef union { 14043dec9fcdSqs uint64_t value; 14053dec9fcdSqs struct { 14063dec9fcdSqs #if defined(_BIG_ENDIAN) 1407*fe930412Sqs uint32_t rsrvd:5; 1408*fe930412Sqs uint32_t address_hi:11; 1409*fe930412Sqs uint32_t rsrvd1:5; 1410*fe930412Sqs uint32_t address_lo:11; 1411*fe930412Sqs uint32_t rsrvd2:8; 1412*fe930412Sqs uint32_t syndrome_hi:8; 1413*fe930412Sqs uint32_t rsrvd3:8; 1414*fe930412Sqs uint32_t syndrome_lo:8; 14153dec9fcdSqs #else 1416*fe930412Sqs uint32_t syndrome_lo:8; 1417*fe930412Sqs uint32_t rsrvd3:8; 1418*fe930412Sqs uint32_t syndrome_hi:8; 1419*fe930412Sqs uint32_t rsrvd2:8; 1420*fe930412Sqs uint32_t address_lo:11; 1421*fe930412Sqs uint32_t rsrvd1:5; 1422*fe930412Sqs uint32_t address_hi:11; 1423*fe930412Sqs uint32_t rsrvd:5; 14243dec9fcdSqs #endif 14253dec9fcdSqs } bits; 14263dec9fcdSqs } rdc_data_fifo_ecc_log_t; 14273dec9fcdSqs 14283dec9fcdSqs 14293dec9fcdSqs /* 14303dec9fcdSqs * Register: RdcFifoErrIntMask 14313dec9fcdSqs * FIFO Error Interrupt Mask 14323dec9fcdSqs * Description: FIFO Error interrupt mask register. Control the 14333dec9fcdSqs * interrupt assertion of FIFO Errors. see FIFO Error Status register 14343dec9fcdSqs * for more description 14353dec9fcdSqs * Fields: 14363dec9fcdSqs * Set to 0 to enable flagging when rx ctrl ram logs ecc single 14373dec9fcdSqs * bit error Part of Device Error 0. 14383dec9fcdSqs * Set to 0 to enable flagging when rx ctrl ram logs ecc double 14393dec9fcdSqs * bit error Part of Device Error 1. 14403dec9fcdSqs * Set to 0 to enable flagging when rx data ram logs ecc single 14413dec9fcdSqs * bit error Part of Device Error 0. 14423dec9fcdSqs * Set to 0 to enable flagging when rx data ram logs ecc double 14433dec9fcdSqs * bit error Part of Device Error 1. 14443dec9fcdSqs */ 14453dec9fcdSqs typedef union { 14463dec9fcdSqs uint64_t value; 14473dec9fcdSqs struct { 14483dec9fcdSqs #if defined(_BIG_ENDIAN) 1449*fe930412Sqs uint32_t rsrvd:32; 1450*fe930412Sqs uint32_t rsrvd1:24; 1451*fe930412Sqs uint32_t rx_ctrl_fifo_sec:2; 1452*fe930412Sqs uint32_t rx_ctrl_fifo_ded:2; 1453*fe930412Sqs uint32_t rx_data_fifo_sec:2; 1454*fe930412Sqs uint32_t rx_data_fifo_ded:2; 14553dec9fcdSqs #else 1456*fe930412Sqs uint32_t rx_data_fifo_ded:2; 1457*fe930412Sqs uint32_t rx_data_fifo_sec:2; 1458*fe930412Sqs uint32_t rx_ctrl_fifo_ded:2; 1459*fe930412Sqs uint32_t rx_ctrl_fifo_sec:2; 1460*fe930412Sqs uint32_t rsrvd1:24; 1461*fe930412Sqs uint32_t rsrvd:32; 14623dec9fcdSqs #endif 14633dec9fcdSqs } bits; 14643dec9fcdSqs } rdc_fifo_err_int_mask_t; 14653dec9fcdSqs 14663dec9fcdSqs 14673dec9fcdSqs /* 14683dec9fcdSqs * Register: RdcFifoErrStat 14693dec9fcdSqs * FIFO Error Status 14703dec9fcdSqs * Description: FIFO Error Status register. Log status of FIFO 14713dec9fcdSqs * Errors. Rx Data buffer is physically two seperate memory, each of 14723dec9fcdSqs * the two error bits point to one of the memory. Each entry in the 14733dec9fcdSqs * rx ctrl point to 2 buffer locations and they are read seperatly. 14743dec9fcdSqs * The two error bits point to each half of the entry. 14753dec9fcdSqs * Fields: 14763dec9fcdSqs * Set to 1 by HW to indicate rx control ram received a ecc 14773dec9fcdSqs * single bit error Writing a 1 to either bit clears the 14783dec9fcdSqs * RdcCtrlFifoEccLog register Non-Fatal error. Part of Device 14793dec9fcdSqs * Error 0 14803dec9fcdSqs * Set to 1 by HW to indicate rx control ram received a ecc 14813dec9fcdSqs * double bit error Writing a 1 to either bit clears the 14823dec9fcdSqs * RdcCtrlFifoEccLog register Fatal error. Part of Device Error 1 14833dec9fcdSqs * Set to 1 by HW to indicate rx data ram received a ecc single 14843dec9fcdSqs * bit error Writing a 1 to either bit clears the 14853dec9fcdSqs * RdcDataFifoEccLog register Non-Fatal error. Part of Device 14863dec9fcdSqs * Error 0 14873dec9fcdSqs * Set to 1 by HW to indicate rx data ram received a ecc double 14883dec9fcdSqs * bit error Writing a 1 to either bit clears the 14893dec9fcdSqs * RdcDataFifoEccLog register Fatal error. Part of Device Error 1 14903dec9fcdSqs */ 14913dec9fcdSqs typedef union { 14923dec9fcdSqs uint64_t value; 14933dec9fcdSqs struct { 14943dec9fcdSqs #if defined(_BIG_ENDIAN) 1495*fe930412Sqs uint32_t rsrvd:32; 1496*fe930412Sqs uint32_t rsrvd_l:24; 1497*fe930412Sqs uint32_t rx_ctrl_fifo_sec:2; 1498*fe930412Sqs uint32_t rx_ctrl_fifo_ded:2; 1499*fe930412Sqs uint32_t rx_data_fifo_sec:2; 1500*fe930412Sqs uint32_t rx_data_fifo_ded:2; 15013dec9fcdSqs #else 1502*fe930412Sqs uint32_t rx_data_fifo_ded:2; 1503*fe930412Sqs uint32_t rx_data_fifo_sec:2; 1504*fe930412Sqs uint32_t rx_ctrl_fifo_ded:2; 1505*fe930412Sqs uint32_t rx_ctrl_fifo_sec:2; 1506*fe930412Sqs uint32_t rsrvd_l:24; 1507*fe930412Sqs uint32_t rsrvd:32; 15083dec9fcdSqs #endif 15093dec9fcdSqs } bits; 15103dec9fcdSqs } rdc_fifo_err_stat_t; 15113dec9fcdSqs 15123dec9fcdSqs 15133dec9fcdSqs /* 15143dec9fcdSqs * Register: RdcFifoErrIntDbg 15153dec9fcdSqs * FIFO Error Interrupt Debug 15163dec9fcdSqs * Description: FIFO Error interrupt Debug register. Debug Control 15173dec9fcdSqs * the interrupt assertion of FIFO Errors. 15183dec9fcdSqs * Fields: 15193dec9fcdSqs * Set to 1 to enable interrupt Part of Device Error 0. 15203dec9fcdSqs * Set to 1 to enable interrupt Part of Device Error 1. 15213dec9fcdSqs * Set to 1 to enable interrupt Part of Device Error 0. 15223dec9fcdSqs * Set to 1 to enable interrupt Part of Device Error 1. 15233dec9fcdSqs */ 15243dec9fcdSqs typedef union { 15253dec9fcdSqs uint64_t value; 15263dec9fcdSqs struct { 15273dec9fcdSqs #if defined(_BIG_ENDIAN) 1528*fe930412Sqs uint32_t rsrvd:32; 1529*fe930412Sqs uint32_t rsrvd1:24; 1530*fe930412Sqs uint32_t rx_ctrl_fifo_sec:2; 1531*fe930412Sqs uint32_t rx_ctrl_fifo_ded:2; 1532*fe930412Sqs uint32_t rx_data_fifo_sec:2; 1533*fe930412Sqs uint32_t rx_data_fifo_ded:2; 15343dec9fcdSqs #else 1535*fe930412Sqs uint32_t rx_data_fifo_ded:2; 1536*fe930412Sqs uint32_t rx_data_fifo_sec:2; 1537*fe930412Sqs uint32_t rx_ctrl_fifo_ded:2; 1538*fe930412Sqs uint32_t rx_ctrl_fifo_sec:2; 1539*fe930412Sqs uint32_t rsrvd1:24; 1540*fe930412Sqs uint32_t rsrvd:32; 15413dec9fcdSqs #endif 15423dec9fcdSqs } bits; 15433dec9fcdSqs } rdc_fifo_err_int_dbg_t; 15443dec9fcdSqs 15453dec9fcdSqs 15463dec9fcdSqs /* 15473dec9fcdSqs * Register: RdcPeuTxnLog 15483dec9fcdSqs * PEU Transaction Log 15493dec9fcdSqs * Description: PEU Transaction Log register. Counts the memory read 15503dec9fcdSqs * and write requests sent to peu block. For debug only. 15513dec9fcdSqs * Fields: 15523dec9fcdSqs * Counts the memory write transactions sent to peu block. This 15533dec9fcdSqs * counter saturates. This counter increments when vnmDbg is on 15543dec9fcdSqs * Counts the memory read transactions sent to peu block. This 15553dec9fcdSqs * counter saturates. This counter increments when vnmDbg is on 15563dec9fcdSqs */ 15573dec9fcdSqs typedef union { 15583dec9fcdSqs uint64_t value; 15593dec9fcdSqs struct { 15603dec9fcdSqs #if defined(_BIG_ENDIAN) 1561*fe930412Sqs uint32_t rsrvd:32; 1562*fe930412Sqs uint32_t rsrvd1:16; 1563*fe930412Sqs uint32_t peu_mem_wr_count:8; 1564*fe930412Sqs uint32_t peu_mem_rd_count:8; 15653dec9fcdSqs #else 1566*fe930412Sqs uint32_t peu_mem_rd_count:8; 1567*fe930412Sqs uint32_t peu_mem_wr_count:8; 1568*fe930412Sqs uint32_t rsrvd1:16; 1569*fe930412Sqs uint32_t rsrvd:32; 15703dec9fcdSqs #endif 15713dec9fcdSqs } bits; 15723dec9fcdSqs } rdc_peu_txn_log_t; 15733dec9fcdSqs 15743dec9fcdSqs 15753dec9fcdSqs /* 15763dec9fcdSqs * Register: RdcDbgTrainingVec 15773dec9fcdSqs * Debug Training Vector 15783dec9fcdSqs * Description: Debug Training Vector register Debug Training Vector 15793dec9fcdSqs * for the coreClk domain. For the pcieClk domain, the dbgxMsb and 15803dec9fcdSqs * dbgyMsb values are flipped on the debug bus. 15813dec9fcdSqs * Fields: 15823dec9fcdSqs * Blade Number, the value read depends on the blade this block 15833dec9fcdSqs * resides 15843dec9fcdSqs * debug training vector the sub-group select value of 0 selects 15853dec9fcdSqs * this vector 15863dec9fcdSqs * Blade Number, the value read depends on the blade this block 15873dec9fcdSqs * resides 15883dec9fcdSqs * debug training vector the sub-group select value of 0 selects 15893dec9fcdSqs * this vector 15903dec9fcdSqs */ 15913dec9fcdSqs typedef union { 15923dec9fcdSqs uint64_t value; 15933dec9fcdSqs struct { 15943dec9fcdSqs #if defined(_BIG_ENDIAN) 1595*fe930412Sqs uint32_t rsrvd:32; 1596*fe930412Sqs uint32_t dbgx_msb:1; 1597*fe930412Sqs uint32_t dbgx_bld_num:3; 1598*fe930412Sqs uint32_t dbgx_training_vec:12; 1599*fe930412Sqs uint32_t dbgy_msb:1; 1600*fe930412Sqs uint32_t dbgy_bld_num:3; 1601*fe930412Sqs uint32_t dbgy_training_vec:12; 16023dec9fcdSqs #else 1603*fe930412Sqs uint32_t dbgy_training_vec:12; 1604*fe930412Sqs uint32_t dbgy_bld_num:3; 1605*fe930412Sqs uint32_t dbgy_msb:1; 1606*fe930412Sqs uint32_t dbgx_training_vec:12; 1607*fe930412Sqs uint32_t dbgx_bld_num:3; 1608*fe930412Sqs uint32_t dbgx_msb:1; 1609*fe930412Sqs uint32_t rsrvd:32; 16103dec9fcdSqs #endif 16113dec9fcdSqs } bits; 16123dec9fcdSqs } rdc_dbg_training_vec_t; 16133dec9fcdSqs 16143dec9fcdSqs 16153dec9fcdSqs /* 16163dec9fcdSqs * Register: RdcDbgGrpSel 16173dec9fcdSqs * Debug Group Select 16183dec9fcdSqs * Description: Debug Group Select register. Debug Group Select 16193dec9fcdSqs * register selects the group of signals brought out on the debug 16203dec9fcdSqs * port 16213dec9fcdSqs * Fields: 16223dec9fcdSqs * high 32b sub-group select 16233dec9fcdSqs * low 32b sub-group select 16243dec9fcdSqs */ 16253dec9fcdSqs typedef union { 16263dec9fcdSqs uint64_t value; 16273dec9fcdSqs struct { 16283dec9fcdSqs #if defined(_BIG_ENDIAN) 1629*fe930412Sqs uint32_t rsrvd:32; 1630*fe930412Sqs uint32_t rsrvd_l:16; 1631*fe930412Sqs uint32_t dbg_h32_sub_sel:8; 1632*fe930412Sqs uint32_t dbg_l32_sub_sel:8; 16333dec9fcdSqs #else 1634*fe930412Sqs uint32_t dbg_l32_sub_sel:8; 1635*fe930412Sqs uint32_t dbg_h32_sub_sel:8; 1636*fe930412Sqs uint32_t rsrvd_l:16; 1637*fe930412Sqs uint32_t rsrvd:32; 16383dec9fcdSqs #endif 16393dec9fcdSqs } bits; 16403dec9fcdSqs } rdc_dbg_grp_sel_t; 16413dec9fcdSqs 16423dec9fcdSqs 16433dec9fcdSqs #ifdef __cplusplus 16443dec9fcdSqs } 16453dec9fcdSqs #endif 16463dec9fcdSqs 16473dec9fcdSqs #endif /* _HXGE_RDC_HW_H */ 1648