1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_HXGE_PEU_HW_H
27 #define	_HXGE_PEU_HW_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #define	PIO_LDSV_BASE_ADDR			0X800000
36 #define	PIO_BASE_ADDR				0X000000
37 #define	PIO_LDMASK_BASE_ADDR			0XA00000
38 
39 #define	DEVICE_VENDOR_ID			(PIO_BASE_ADDR + 0x0)
40 #define	STATUS_COMMAND				(PIO_BASE_ADDR + 0x4)
41 #define	CLASSCODE_REV_ID			(PIO_BASE_ADDR + 0x8)
42 #define	BIST_HDRTYP_LATTMR_CASHLSZ		(PIO_BASE_ADDR + 0xC)
43 #define	PIO_BAR0				(PIO_BASE_ADDR + 0x10)
44 #define	PIO_BAR1				(PIO_BASE_ADDR + 0x14)
45 #define	MSIX_BAR0				(PIO_BASE_ADDR + 0x18)
46 #define	MSIX_BAR1				(PIO_BASE_ADDR + 0x1C)
47 #define	VIRT_BAR0				(PIO_BASE_ADDR + 0x20)
48 #define	VIRT_BAR1				(PIO_BASE_ADDR + 0x24)
49 #define	CIS_PTR					(PIO_BASE_ADDR + 0x28)
50 #define	SUB_VENDOR_ID				(PIO_BASE_ADDR + 0x2C)
51 #define	EXP_ROM_BAR				(PIO_BASE_ADDR + 0x30)
52 #define	CAP_PTR					(PIO_BASE_ADDR + 0x34)
53 #define	INT_LINE				(PIO_BASE_ADDR + 0x3C)
54 #define	PM_CAP					(PIO_BASE_ADDR + 0x40)
55 #define	PM_CTRL_STAT				(PIO_BASE_ADDR + 0x44)
56 #define	MSI_CAP					(PIO_BASE_ADDR + 0x50)
57 #define	MSI_LO_ADDR				(PIO_BASE_ADDR + 0x54)
58 #define	MSI_HI_ADDR				(PIO_BASE_ADDR + 0x58)
59 #define	MSI_DATA				(PIO_BASE_ADDR + 0x5C)
60 #define	MSI_MASK				(PIO_BASE_ADDR + 0x60)
61 #define	MSI_PEND				(PIO_BASE_ADDR + 0x64)
62 #define	MSIX_CAP				(PIO_BASE_ADDR + 0x70)
63 #define	MSIX_TAB_OFF				(PIO_BASE_ADDR + 0x74)
64 #define	MSIX_PBA_OFF				(PIO_BASE_ADDR + 0x78)
65 #define	PCIE_CAP				(PIO_BASE_ADDR + 0x80)
66 #define	DEV_CAP					(PIO_BASE_ADDR + 0x84)
67 #define	DEV_STAT_CTRL				(PIO_BASE_ADDR + 0x88)
68 #define	LNK_CAP					(PIO_BASE_ADDR + 0x8C)
69 #define	LNK_STAT_CTRL				(PIO_BASE_ADDR + 0x90)
70 #define	VEN_CAP_HDR				(PIO_BASE_ADDR + 0x94)
71 #define	VEN_CTRL				(PIO_BASE_ADDR + 0x98)
72 #define	VEN_PRT_HDR				(PIO_BASE_ADDR + 0x9C)
73 #define	ACKLAT_REPLAY				(PIO_BASE_ADDR + 0xA0)
74 #define	OTH_MSG					(PIO_BASE_ADDR + 0xA4)
75 #define	FORCE_LINK				(PIO_BASE_ADDR + 0xA8)
76 #define	ACK_FREQ				(PIO_BASE_ADDR + 0xAC)
77 #define	LINK_CTRL				(PIO_BASE_ADDR + 0xB0)
78 #define	LANE_SKEW				(PIO_BASE_ADDR + 0xB4)
79 #define	SYMBOL_NUM				(PIO_BASE_ADDR + 0xB8)
80 #define	SYMB_TIM_RADM_FLT1			(PIO_BASE_ADDR + 0xBC)
81 #define	RADM_FLT2				(PIO_BASE_ADDR + 0xC0)
82 #define	CASCADE_DEB_REG0			(PIO_BASE_ADDR + 0xC8)
83 #define	CASCADE_DEB_REG1			(PIO_BASE_ADDR + 0xCC)
84 #define	TXP_FC_CREDIT_STAT			(PIO_BASE_ADDR + 0xD0)
85 #define	TXNP_FC_CREDIT_STAT			(PIO_BASE_ADDR + 0xD4)
86 #define	TXCPL_FC_CREDIT_STAT			(PIO_BASE_ADDR + 0xD8)
87 #define	QUEUE_STAT				(PIO_BASE_ADDR + 0xDC)
88 #define	GBT_DEBUG0				(PIO_BASE_ADDR + 0xE0)
89 #define	GBT_DEBUG1				(PIO_BASE_ADDR + 0xE4)
90 #define	GBT_DEBUG2				(PIO_BASE_ADDR + 0xE8)
91 #define	GBT_DEBUG3				(PIO_BASE_ADDR + 0xEC)
92 #define	PIPE_DEBUG0				(PIO_BASE_ADDR + 0xF0)
93 #define	PIPE_DEBUG1				(PIO_BASE_ADDR + 0xF4)
94 #define	PIPE_DEBUG2				(PIO_BASE_ADDR + 0xF8)
95 #define	PIPE_DEBUG3				(PIO_BASE_ADDR + 0xFC)
96 #define	PCIE_ENH_CAP_HDR			(PIO_BASE_ADDR + 0x100)
97 #define	UNC_ERR_STAT				(PIO_BASE_ADDR + 0x104)
98 #define	UNC_ERR_MASK				(PIO_BASE_ADDR + 0x108)
99 #define	UNC_ERR_SVRTY				(PIO_BASE_ADDR + 0x10C)
100 #define	CORR_ERR_STAT				(PIO_BASE_ADDR + 0x110)
101 #define	CORR_ERR_MASK				(PIO_BASE_ADDR + 0x114)
102 #define	ADV_CAP_CTRL				(PIO_BASE_ADDR + 0x118)
103 #define	HDR_LOG0				(PIO_BASE_ADDR + 0x11C)
104 #define	HDR_LOG1				(PIO_BASE_ADDR + 0x120)
105 #define	HDR_LOG2				(PIO_BASE_ADDR + 0x124)
106 #define	HDR_LOG3				(PIO_BASE_ADDR + 0x128)
107 #define	PIPE_RX_TX_CONTROL			(PIO_BASE_ADDR + 0x1000)
108 #define	PIPE_RX_TX_STATUS			(PIO_BASE_ADDR + 0x1004)
109 #define	PIPE_RX_TX_PWR_CNTL			(PIO_BASE_ADDR + 0x1008)
110 #define	PIPE_RX_TX_PARAM			(PIO_BASE_ADDR + 0x1010)
111 #define	PIPE_RX_TX_CLOCK			(PIO_BASE_ADDR + 0x1014)
112 #define	PIPE_GLUE_CNTL0				(PIO_BASE_ADDR + 0x1018)
113 #define	PIPE_GLUE_CNTL1				(PIO_BASE_ADDR + 0x101C)
114 #define	HCR_REG					(PIO_BASE_ADDR + 0x2000)
115 #define	BLOCK_RESET				(PIO_BASE_ADDR + 0x8000)
116 #define	TIMEOUT_CFG				(PIO_BASE_ADDR + 0x8004)
117 #define	HEART_CFG				(PIO_BASE_ADDR + 0x8008)
118 #define	HEART_TIMER				(PIO_BASE_ADDR + 0x800C)
119 #define	CIP_GP_CTRL				(PIO_BASE_ADDR + 0x8010)
120 #define	CIP_STATUS				(PIO_BASE_ADDR + 0x8014)
121 #define	CIP_LINK_STAT				(PIO_BASE_ADDR + 0x801C)
122 #define	EPC_STAT				(PIO_BASE_ADDR + 0x8020)
123 #define	EPC_DATA				(PIO_BASE_ADDR + 0x8024)
124 #define	SPC_STAT				(PIO_BASE_ADDR + 0x8030)
125 #define	HOST2SPI_INDACC_ADDR			(PIO_BASE_ADDR + 0x8050)
126 #define	HOST2SPI_INDACC_CTRL			(PIO_BASE_ADDR + 0x8054)
127 #define	HOST2SPI_INDACC_DATA			(PIO_BASE_ADDR + 0x8058)
128 #define	BT_CTRL0				(PIO_BASE_ADDR + 0x8080)
129 #define	BT_DATA0				(PIO_BASE_ADDR + 0x8084)
130 #define	BT_INTMASK0				(PIO_BASE_ADDR + 0x8088)
131 #define	BT_CTRL1				(PIO_BASE_ADDR + 0x8090)
132 #define	BT_DATA1				(PIO_BASE_ADDR + 0x8094)
133 #define	BT_INTMASK1				(PIO_BASE_ADDR + 0x8098)
134 #define	BT_CTRL2				(PIO_BASE_ADDR + 0x80A0)
135 #define	BT_DATA2				(PIO_BASE_ADDR + 0x80A4)
136 #define	BT_INTMASK2				(PIO_BASE_ADDR + 0x80A8)
137 #define	BT_CTRL3				(PIO_BASE_ADDR + 0x80B0)
138 #define	BT_DATA3				(PIO_BASE_ADDR + 0x80B4)
139 #define	BT_INTMASK3				(PIO_BASE_ADDR + 0x80B8)
140 #define	DEBUG_SEL				(PIO_BASE_ADDR + 0x80C0)
141 #define	INDACC_MEM0_CTRL			(PIO_BASE_ADDR + 0x80C4)
142 #define	INDACC_MEM0_DATA0			(PIO_BASE_ADDR + 0x80C8)
143 #define	INDACC_MEM0_DATA1			(PIO_BASE_ADDR + 0x80CC)
144 #define	INDACC_MEM0_DATA2			(PIO_BASE_ADDR + 0x80D0)
145 #define	INDACC_MEM0_DATA3			(PIO_BASE_ADDR + 0x80D4)
146 #define	INDACC_MEM0_PRTY			(PIO_BASE_ADDR + 0x80D8)
147 #define	INDACC_MEM1_CTRL			(PIO_BASE_ADDR + 0x80DC)
148 #define	INDACC_MEM1_DATA0			(PIO_BASE_ADDR + 0x80E0)
149 #define	INDACC_MEM1_DATA1			(PIO_BASE_ADDR + 0x80E4)
150 #define	INDACC_MEM1_DATA2			(PIO_BASE_ADDR + 0x80E8)
151 #define	INDACC_MEM1_DATA3			(PIO_BASE_ADDR + 0x80EC)
152 #define	INDACC_MEM1_PRTY			(PIO_BASE_ADDR + 0x80F0)
153 #define	PHY_DEBUG_TRAINING_VEC			(PIO_BASE_ADDR + 0x80F4)
154 #define	PEU_DEBUG_TRAINING_VEC			(PIO_BASE_ADDR + 0x80F8)
155 #define	PIPE_CFG0				(PIO_BASE_ADDR + 0x8120)
156 #define	PIPE_CFG1				(PIO_BASE_ADDR + 0x8124)
157 #define	CIP_BAR_MASK_CFG			(PIO_BASE_ADDR + 0x8134)
158 #define	CIP_BAR_MASK				(PIO_BASE_ADDR + 0x8138)
159 #define	CIP_LDSV0_STAT				(PIO_BASE_ADDR + 0x8140)
160 #define	CIP_LDSV1_STAT				(PIO_BASE_ADDR + 0x8144)
161 #define	PEU_INTR_STAT				(PIO_BASE_ADDR + 0x8148)
162 #define	PEU_INTR_MASK				(PIO_BASE_ADDR + 0x814C)
163 #define	PEU_INTR_STAT_MIRROR			(PIO_BASE_ADDR + 0x8150)
164 #define	CPL_HDRQ_PERR_LOC			(PIO_BASE_ADDR + 0x8154)
165 #define	CPL_DATAQ_PERR_LOC			(PIO_BASE_ADDR + 0x8158)
166 #define	RETR_PERR_LOC				(PIO_BASE_ADDR + 0x815C)
167 #define	RETR_SOT_PERR_LOC			(PIO_BASE_ADDR + 0x8160)
168 #define	P_HDRQ_PERR_LOC				(PIO_BASE_ADDR + 0x8164)
169 #define	P_DATAQ_PERR_LOC			(PIO_BASE_ADDR + 0x8168)
170 #define	NP_HDRQ_PERR_LOC			(PIO_BASE_ADDR + 0x816C)
171 #define	NP_DATAQ_PERR_LOC			(PIO_BASE_ADDR + 0x8170)
172 #define	MSIX_PERR_LOC				(PIO_BASE_ADDR + 0x8174)
173 #define	HCR_PERR_LOC				(PIO_BASE_ADDR + 0x8178)
174 #define	TDC_PIOACC_ERR_LOG			(PIO_BASE_ADDR + 0x8180)
175 #define	RDC_PIOACC_ERR_LOG			(PIO_BASE_ADDR + 0x8184)
176 #define	PFC_PIOACC_ERR_LOG			(PIO_BASE_ADDR + 0x8188)
177 #define	VMAC_PIOACC_ERR_LOG			(PIO_BASE_ADDR + 0x818C)
178 #define	LD_GRP_CTRL				(PIO_BASE_ADDR + 0x8300)
179 #define	DEV_ERR_STAT				(PIO_BASE_ADDR + 0x8380)
180 #define	DEV_ERR_MASK				(PIO_BASE_ADDR + 0x8384)
181 #define	LD_INTR_TIM_RES				(PIO_BASE_ADDR + 0x8390)
182 #define	LDSV0					(PIO_LDSV_BASE_ADDR + 0x0)
183 #define	LDSV1					(PIO_LDSV_BASE_ADDR + 0x4)
184 #define	LD_INTR_MASK				(PIO_LDMASK_BASE_ADDR + 0x0)
185 #define	LD_INTR_MGMT				(PIO_LDMASK_BASE_ADDR + 0x4)
186 #define	SID					(PIO_LDMASK_BASE_ADDR + 0x8)
187 
188 
189 /*
190  * Register: DeviceVendorId
191  * Device ID and Vendor ID
192  * Description: Device ID/Vendor ID
193  * Fields:
194  *     Device ID Register: dbi writeable
195  *     Vendor ID Register (Sun Microsystem): dbi writeable
196  */
197 typedef union {
198 	uint32_t value;
199 	struct {
200 #if defined(_BIG_ENDIAN)
201 		uint32_t	device_id:16;
202 		uint32_t	vendor_id:16;
203 #else
204 		uint32_t	vendor_id:16;
205 		uint32_t	device_id:16;
206 #endif
207 	} bits;
208 } device_vendor_id_t;
209 
210 
211 /*
212  * Register: StatusCommand
213  * Status and Command
214  * Description: Status/Command
215  * Fields:
216  *     The device detected a parity error. The device detects
217  *     Poisoned TLP received regardless of Command Register Parity
218  *     Error Enable/Response bit.
219  *     The device signaled a system error with SERR#. The device
220  *     detects a UE, is about to send a F/NF error message; and if
221  *     the Command Register SERR# enable is set.
222  *     A transaction initiated by this device was terminated due to a
223  *     Master Abort (i.e. Unsupported Request Completion Status was
224  *     received).
225  *     A transaction initiated by this device was terminated due to a
226  *     Target Abort (i.e. Completer Abort Completion Status was
227  *     received).
228  *     Set when Completer Abort Completion Status is sent back to the
229  *     RC. The request violated hydra's programming rules.
230  *     The slowest DEVSEL# timing for this target device (N/A in
231  *     PCIE)
232  *     Master Data Parity Error - set if all the following conditions
233  *     are true: received a poisoned TLP header or sending a poisoned
234  *     write request; and the parity error response bit in the
235  *     command register is set.
236  *     Fast Back-to-Back Capable (N/A in PCIE)
237  *     66 MHz Capable (N/A in PCIE)
238  *     Capabilities List - presence of extended capability item.
239  *     INTx Status
240  *     INTx Assertion Disable
241  *     Fast Back-to-Back Enable (N/A in PCIE)
242  *     This device can drive the SERR# line.
243  *     IDSEL Stepping/Wait Cycle Control (N/A in PCIE)
244  *     This device can drive the PERR# line.
245  *     VGA Palette Snoop (N/A in PCIE)
246  *     The device can issue Memory Write-and-Invalidate commands (N/A
247  *     in PCIE)
248  *     This device monitors for PCI Special Cycles (N/A in PCIE)
249  *     This device's bus master capability is enabled.
250  *     This device responds to PCI memory accesses.
251  *     This device responds to PCI IO accesses (No I/O space used in
252  *     Hydra)
253  */
254 typedef union {
255 	uint32_t value;
256 	struct {
257 #if defined(_BIG_ENDIAN)
258 		uint32_t	det_par_err:1;
259 		uint32_t	sig_serr:1;
260 		uint32_t	rcv_mstr_abrt:1;
261 		uint32_t	rcv_tgt_abrt:1;
262 		uint32_t	sig_tgt_abrt:1;
263 		uint32_t	devsel_timing:2;
264 		uint32_t	mstr_dpe:1;
265 		uint32_t	fast_b2b_cap:1;
266 		uint32_t	rsrvd:1;
267 		uint32_t	mhz_cap:1;
268 		uint32_t	cap_list:1;
269 		uint32_t	intx_stat:1;
270 		uint32_t	rsrvd1:3;
271 		uint32_t	rsrvd2:5;
272 		uint32_t	intx_dis:1;
273 		uint32_t	fast_b2b_en:1;
274 		uint32_t	serr_en:1;
275 		uint32_t	idsel_step:1;
276 		uint32_t	par_err_en:1;
277 		uint32_t	vga_snoop:1;
278 		uint32_t	mwi_en:1;
279 		uint32_t	special_cycle:1;
280 		uint32_t	bm_en:1;
281 		uint32_t	mem_sp_en:1;
282 		uint32_t	io_sp_en:1;
283 #else
284 		uint32_t	io_sp_en:1;
285 		uint32_t	mem_sp_en:1;
286 		uint32_t	bm_en:1;
287 		uint32_t	special_cycle:1;
288 		uint32_t	mwi_en:1;
289 		uint32_t	vga_snoop:1;
290 		uint32_t	par_err_en:1;
291 		uint32_t	idsel_step:1;
292 		uint32_t	serr_en:1;
293 		uint32_t	fast_b2b_en:1;
294 		uint32_t	intx_dis:1;
295 		uint32_t	rsrvd2:5;
296 		uint32_t	rsrvd1:3;
297 		uint32_t	intx_stat:1;
298 		uint32_t	cap_list:1;
299 		uint32_t	mhz_cap:1;
300 		uint32_t	rsrvd:1;
301 		uint32_t	fast_b2b_cap:1;
302 		uint32_t	mstr_dpe:1;
303 		uint32_t	devsel_timing:2;
304 		uint32_t	sig_tgt_abrt:1;
305 		uint32_t	rcv_tgt_abrt:1;
306 		uint32_t	rcv_mstr_abrt:1;
307 		uint32_t	sig_serr:1;
308 		uint32_t	det_par_err:1;
309 #endif
310 	} bits;
311 } status_command_t;
312 
313 
314 /*
315  * Register: ClasscodeRevId
316  * Class Code, and Revision ID
317  * Description: Class Code/Revision ID
318  * Fields:
319  *     Base Class (Network Controller): dbi writeable
320  *     Sub Class (Ethernet Controller): dbi writeable
321  *     Programming Interface: dbi writeable
322  *     Revision ID: dbi writeable
323  */
324 typedef union {
325 	uint32_t value;
326 	struct {
327 #if defined(_BIG_ENDIAN)
328 		uint32_t	base_class:8;
329 		uint32_t	sub_class:8;
330 		uint32_t	prog_if:8;
331 		uint32_t	rev_id:8;
332 #else
333 		uint32_t	rev_id:8;
334 		uint32_t	prog_if:8;
335 		uint32_t	sub_class:8;
336 		uint32_t	base_class:8;
337 #endif
338 	} bits;
339 } classcode_rev_id_t;
340 
341 
342 /*
343  * Register: BistHdrtypLattmrCashlsz
344  * BIST, Header Type, Latency Timer, and Cache Line Size
345  * Description: BIST, Latency Timer etc
346  * Fields:
347  *     BIST is not supported. Header Type Fields
348  *     Multi-Function Device: dbi writeable
349  *     Configuration Header Format. 0 = Type 0.
350  *     Master Latency Timer. (N/A in PCIE)
351  *     Cache line size for legacy compatibility (N/A in PCIE)
352  */
353 typedef union {
354 	uint32_t value;
355 	struct {
356 #if defined(_BIG_ENDIAN)
357 		uint32_t	value:8;
358 		uint32_t	mult_func_dev:1;
359 		uint32_t	cfg_hdr_fmt:7;
360 		uint32_t	timer:8;
361 		uint32_t	cache_line_sz:8;
362 #else
363 		uint32_t	cache_line_sz:8;
364 		uint32_t	timer:8;
365 		uint32_t	cfg_hdr_fmt:7;
366 		uint32_t	mult_func_dev:1;
367 		uint32_t	value:8;
368 #endif
369 	} bits;
370 } bist_hdrtyp_lattmr_cashlsz_t;
371 
372 
373 /*
374  * Register: PioBar0
375  * PIO BAR0
376  * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0
377  * are together configured as a 64b BAR register (Synopsys core
378  * implementation dependent) where PIO BAR1 handles the upper address
379  * bits and PIO BAR0 handles the lower address bits.
380  * Fields:
381  *     Base Address Relocation : indirect dbi writeable via bar0Mask
382  *     register in EP core
383  *     Base Address for PIO (16MB space) : indirect dbi writeable via
384  *     bar0Mask register in EP core
385  *     Prefetchable if memory BAR (PIOs not prefetchable): dbi
386  *     writeable
387  *     If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64
388  *     bit): dbi writeable
389  *     I/O or Memory space indicator (0 = memory BAR): dbi writeable
390  */
391 typedef union {
392 	uint32_t value;
393 	struct {
394 #if defined(_BIG_ENDIAN)
395 		uint32_t	base_addr_rel_lo:8;
396 		uint32_t	base_addr:20;
397 		uint32_t	pftch:1;
398 		uint32_t	type:2;
399 		uint32_t	mem_sp_ind:1;
400 #else
401 		uint32_t	mem_sp_ind:1;
402 		uint32_t	type:2;
403 		uint32_t	pftch:1;
404 		uint32_t	base_addr:20;
405 		uint32_t	base_addr_rel_lo:8;
406 #endif
407 	} bits;
408 } pio_bar0_t;
409 
410 
411 /*
412  * Register: PioBar1
413  * PIO BAR1
414  * Description: PIO BAR1
415  * Fields:
416  *     Base Address Relocation : indirect dbi writeable via bar0Mask
417  *     register in EP core
418  */
419 typedef union {
420 	uint32_t value;
421 	struct {
422 #if defined(_BIG_ENDIAN)
423 		uint32_t	base_addr_rel_hi:32;
424 #else
425 		uint32_t	base_addr_rel_hi:32;
426 #endif
427 	} bits;
428 } pio_bar1_t;
429 
430 
431 /*
432  * Register: MsixBar0
433  * MSIX BAR0
434  * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX
435  * BAR0 are together configured as a 64b BAR register (Synopsys core
436  * implementation dependent) where MSIX BAR1 handles the upper
437  * address bits and MSIX BAR0 handles the lower address bits.
438  * Fields:
439  *     Base Address Relocation : indirect dbi writeable via bar2Mask
440  *     register in EP core
441  *     Base Address for MSIX (16KB space) : indirect dbi writeable
442  *     via bar2Mask register in EP core
443  *     Prefetchable if memory BAR (Not prefetchable) : dbi writeable
444  *     If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64
445  *     bit): dbi writeable
446  *     I/O or Memory space indicator (0 = memory BAR) : dbi writeable
447  */
448 typedef union {
449 	uint32_t value;
450 	struct {
451 #if defined(_BIG_ENDIAN)
452 		uint32_t	base_addr_rel_lo:18;
453 		uint32_t	base_addr:10;
454 		uint32_t	pftch:1;
455 		uint32_t	type:2;
456 		uint32_t	mem_sp_ind:1;
457 #else
458 		uint32_t	mem_sp_ind:1;
459 		uint32_t	type:2;
460 		uint32_t	pftch:1;
461 		uint32_t	base_addr:10;
462 		uint32_t	base_addr_rel_lo:18;
463 #endif
464 	} bits;
465 } msix_bar0_t;
466 
467 
468 /*
469  * Register: MsixBar1
470  * MSIX BAR1
471  * Description: MSIX BAR1
472  * Fields:
473  *     Base Address Relocation : indirect dbi writeable via bar2Mask
474  *     register in EP core
475  */
476 typedef union {
477 	uint32_t value;
478 	struct {
479 #if defined(_BIG_ENDIAN)
480 		uint32_t	base_addr_rel_hi:32;
481 #else
482 		uint32_t	base_addr_rel_hi:32;
483 #endif
484 	} bits;
485 } msix_bar1_t;
486 
487 
488 /*
489  * Register: VirtBar0
490  * Virtualization BAR0
491  * Description: Virtualization BAR0 - Previously for Hydra
492  * Virtualization space This bar is no longer enabled and is not dbi
493  * writeable. VIRT BAR1 & VIRT BAR0 could be configured as a 64b BAR
494  * register (Synopsys core implementation dependent), but this is not
495  * used in hydra.
496  * Fields:
497  *     Base Address Relocation
498  *     Base Address for Virtualization (64KB space)
499  *     Prefetchable if memory BAR (Not prefetchable)
500  *     If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64
501  *     bit)
502  *     I/O or Memory space indicator (0 = memory BAR)
503  */
504 typedef union {
505 	uint32_t value;
506 	struct {
507 #if defined(_BIG_ENDIAN)
508 		uint32_t	base_addr_rel_lo:17;
509 		uint32_t	base_addr:11;
510 		uint32_t	pftch:1;
511 		uint32_t	type:2;
512 		uint32_t	mem_sp_ind:1;
513 #else
514 		uint32_t	mem_sp_ind:1;
515 		uint32_t	type:2;
516 		uint32_t	pftch:1;
517 		uint32_t	base_addr:11;
518 		uint32_t	base_addr_rel_lo:17;
519 #endif
520 	} bits;
521 } virt_bar0_t;
522 
523 
524 /*
525  * Register: VirtBar1
526  * Virtualization BAR1
527  * Description: Previously for Virtualization BAR1 This bar is no
528  * longer enabled and is not dbi writeable.
529  * Fields:
530  *     Base Address Relocation
531  */
532 typedef union {
533 	uint32_t value;
534 	struct {
535 #if defined(_BIG_ENDIAN)
536 		uint32_t	base_addr_rel_hi:32;
537 #else
538 		uint32_t	base_addr_rel_hi:32;
539 #endif
540 	} bits;
541 } virt_bar1_t;
542 
543 
544 /*
545  * Register: CisPtr
546  * CardBus CIS Pointer
547  * Description: CardBus CIS Pointer
548  * Fields:
549  *     CardBus CIS Pointer: dbi writeable
550  */
551 typedef union {
552 	uint32_t value;
553 	struct {
554 #if defined(_BIG_ENDIAN)
555 		uint32_t	cis_ptr:32;
556 #else
557 		uint32_t	cis_ptr:32;
558 #endif
559 	} bits;
560 } cis_ptr_t;
561 
562 
563 /*
564  * Register: SubVendorId
565  * Subsystem ID and Vendor ID
566  * Description: Subsystem ID and Vendor ID
567  * Fields:
568  *     Subsystem ID as assigned by PCI-SIG : dbi writeable
569  *     Subsystem Vendor ID as assigned by PCI-SIG : dbi writeable
570  */
571 typedef union {
572 	uint32_t value;
573 	struct {
574 #if defined(_BIG_ENDIAN)
575 		uint32_t	dev_id:16;
576 		uint32_t	vendor_id:16;
577 #else
578 		uint32_t	vendor_id:16;
579 		uint32_t	dev_id:16;
580 #endif
581 	} bits;
582 } sub_vendor_id_t;
583 
584 
585 /*
586  * Register: ExpRomBar
587  * Expansion ROM BAR
588  * Description: Expansion ROM BAR - For Hydra EEPROM space
589  * Fields:
590  *     Base Address Relocatable : indirect dbi writeable via
591  *     romBarMask register in EP core
592  *     Base Address for ROM (2MB) : indirect dbi writeable via
593  *     romBarMask register in EP core
594  *     ROM Enable: dbi writeable
595  */
596 typedef union {
597 	uint32_t value;
598 	struct {
599 #if defined(_BIG_ENDIAN)
600 		uint32_t	base_addr_rel:11;
601 		uint32_t	base_addr:10;
602 		uint32_t	rsrvd:10;
603 		uint32_t	rom_en:1;
604 #else
605 		uint32_t	rom_en:1;
606 		uint32_t	rsrvd:10;
607 		uint32_t	base_addr:10;
608 		uint32_t	base_addr_rel:11;
609 #endif
610 	} bits;
611 } exp_rom_bar_t;
612 
613 
614 /*
615  * Register: CapPtr
616  * Capabilities Pointer
617  * Description: Capabilities Pointer
618  * Fields:
619  *     Pointer to PM Capability structure : dbi writeable
620  */
621 typedef union {
622 	uint32_t value;
623 	struct {
624 #if defined(_BIG_ENDIAN)
625 		uint32_t	rsrvd:24;
626 		uint32_t	pm_ptr:8;
627 #else
628 		uint32_t	pm_ptr:8;
629 		uint32_t	rsrvd:24;
630 #endif
631 	} bits;
632 } cap_ptr_t;
633 
634 
635 /*
636  * Register: IntLine
637  * Interrupt Line
638  * Description: Interrupt Line
639  * Fields:
640  *     Max Latency (N/A in PCIE)
641  *     Minimum Grant (N/A in PCIE)
642  *     Interrupt pin: dbi writeable
643  *     Interrupt Line
644  */
645 typedef union {
646 	uint32_t value;
647 	struct {
648 #if defined(_BIG_ENDIAN)
649 		uint32_t	max_lat:8;
650 		uint32_t	min_gnt:8;
651 		uint32_t	int_pin:8;
652 		uint32_t	int_line:8;
653 #else
654 		uint32_t	int_line:8;
655 		uint32_t	int_pin:8;
656 		uint32_t	min_gnt:8;
657 		uint32_t	max_lat:8;
658 #endif
659 	} bits;
660 } int_line_t;
661 
662 
663 /*
664  * Register: PmCap
665  * Power Management Capability
666  * Description: Power Management Capability
667  * Fields:
668  *     PME Support (N/A in Hydra): dbi writeable
669  *     D2 Support (N/A in Hydra): dbi writeable
670  *     D1 Support (N/A in Hydra): dbi writeable
671  *     Aux Current (N/A in Hydra): dbi writeable
672  *     Device Specific Initialization: dbi writeable
673  *     PME Clock (N/A in PCIE)
674  *     PM Spec Version: dbi writeable
675  *     Next Capability Pointer: dbi writeable
676  *     Power Management Capability ID: dbi writeable
677  */
678 typedef union {
679 	uint32_t value;
680 	struct {
681 #if defined(_BIG_ENDIAN)
682 		uint32_t	pme_supt:5;
683 		uint32_t	d2_supt:1;
684 		uint32_t	d1_supt:1;
685 		uint32_t	aux_curr:3;
686 		uint32_t	dev_spec_init:1;
687 		uint32_t	rsrvd:1;
688 		uint32_t	pme_clk:1;
689 		uint32_t	pm_ver:3;
690 		uint32_t	nxt_cap_ptr:8;
691 		uint32_t	pm_id:8;
692 #else
693 		uint32_t	pm_id:8;
694 		uint32_t	nxt_cap_ptr:8;
695 		uint32_t	pm_ver:3;
696 		uint32_t	pme_clk:1;
697 		uint32_t	rsrvd:1;
698 		uint32_t	dev_spec_init:1;
699 		uint32_t	aux_curr:3;
700 		uint32_t	d1_supt:1;
701 		uint32_t	d2_supt:1;
702 		uint32_t	pme_supt:5;
703 #endif
704 	} bits;
705 } pm_cap_t;
706 
707 
708 /*
709  * Register: PmCtrlStat
710  * Power Management Control and Status
711  * Description: Power Management Control and Status
712  * Fields:
713  *     Data for additional info (N/A)
714  *     Bus Power and Clock Control Enable (N/A in PCIE)
715  *     B2/B3 Support (N/A in PCIE)
716  *     Indicates if PME event occured
717  *     Data Scale (N/A)
718  *     Data Select (N/A)
719  *     PME Enable (Sticky)
720  *     Power State
721  */
722 typedef union {
723 	uint32_t value;
724 	struct {
725 #if defined(_BIG_ENDIAN)
726 		uint32_t	pwr_data:8;
727 		uint32_t	pwr_clk_en:1;
728 		uint32_t	b2_b3_supt:1;
729 		uint32_t	rsrvd:6;
730 		uint32_t	pme_stat:1;
731 		uint32_t	data_scale:2;
732 		uint32_t	data_sel:4;
733 		uint32_t	pme_en:1;
734 		uint32_t	rsrvd1:6;
735 		uint32_t	pwr_st:2;
736 #else
737 		uint32_t	pwr_st:2;
738 		uint32_t	rsrvd1:6;
739 		uint32_t	pme_en:1;
740 		uint32_t	data_sel:4;
741 		uint32_t	data_scale:2;
742 		uint32_t	pme_stat:1;
743 		uint32_t	rsrvd:6;
744 		uint32_t	b2_b3_supt:1;
745 		uint32_t	pwr_clk_en:1;
746 		uint32_t	pwr_data:8;
747 #endif
748 	} bits;
749 } pm_ctrl_stat_t;
750 
751 
752 /*
753  * Register: MsiCap
754  * MSI Capability
755  * Description: MSI Capability
756  * Fields:
757  *     Mask and Pending bits available
758  *     64-bit Address Capable
759  *     Multiple Messages Enabled
760  *     Multiple Message Capable (32 messages = 0x5)
761  *     MSI Enabled (if enabled, INTx must be diabled)
762  *     Next Capability Pointer: dbi writeable
763  *     MSI Capability ID
764  */
765 typedef union {
766 	uint32_t value;
767 	struct {
768 #if defined(_BIG_ENDIAN)
769 		uint32_t	rsrvd:7;
770 		uint32_t	vect_mask:1;
771 		uint32_t	msi64_en:1;
772 		uint32_t	mult_msg_en:3;
773 		uint32_t	mult_msg_cap:3;
774 		uint32_t	msi_en:1;
775 		uint32_t	nxt_cap_ptr:8;
776 		uint32_t	msi_cap_id:8;
777 #else
778 		uint32_t	msi_cap_id:8;
779 		uint32_t	nxt_cap_ptr:8;
780 		uint32_t	msi_en:1;
781 		uint32_t	mult_msg_cap:3;
782 		uint32_t	mult_msg_en:3;
783 		uint32_t	msi64_en:1;
784 		uint32_t	vect_mask:1;
785 		uint32_t	rsrvd:7;
786 #endif
787 	} bits;
788 } msi_cap_t;
789 
790 
791 /*
792  * Register: MsiLoAddr
793  * MSI Low Address
794  * Description: MSI Low Address
795  * Fields:
796  *     Lower 32 bit Address
797  */
798 typedef union {
799 	uint32_t value;
800 	struct {
801 #if defined(_BIG_ENDIAN)
802 		uint32_t	lo_addr:30;
803 		uint32_t	rsrvd:2;
804 #else
805 		uint32_t	rsrvd:2;
806 		uint32_t	lo_addr:30;
807 #endif
808 	} bits;
809 } msi_lo_addr_t;
810 
811 
812 /*
813  * Register: MsiHiAddr
814  * MSI High Address
815  * Description: MSI High Address
816  * Fields:
817  *     Upper 32 bit Address (only if msi64En = 1)
818  */
819 typedef union {
820 	uint32_t value;
821 	struct {
822 #if defined(_BIG_ENDIAN)
823 		uint32_t	hi_addr:32;
824 #else
825 		uint32_t	hi_addr:32;
826 #endif
827 	} bits;
828 } msi_hi_addr_t;
829 
830 
831 /*
832  * Register: MsiData
833  * MSI Data
834  * Description: MSI Data
835  * Fields:
836  *     MSI Data. Depending on the value for multMsgEn in the MSI
837  *     Capability Register which determines the number of allocated
838  *     vectors, bits [4:0] may be replaced with msiVector[4:0] bits
839  *     to generate up to 32 MSI messages. # allocated vectors Actual
840  *     messageData[4:0] ------------------- ------------------------
841  *     1 DATA[4:0] (no replacement) 2 {DATA[4:1], msiVector[0]} 4
842  *     {DATA[4:2], msiVector[1:0]} 8 {DATA[4:3], msiVector[2:0]} 16
843  *     {DATA[4], msiVector[3:0]} 32 msiVector[4:0] (full replacement)
844  */
845 typedef union {
846 	uint32_t value;
847 	struct {
848 #if defined(_BIG_ENDIAN)
849 		uint32_t	rsrvd:16;
850 		uint32_t	data:16;
851 #else
852 		uint32_t	data:16;
853 		uint32_t	rsrvd:16;
854 #endif
855 	} bits;
856 } msi_data_t;
857 
858 
859 /*
860  * Register: MsiMask
861  * MSI Mask
862  * Description: MSI Mask
863  * Fields:
864  *     per vector MSI Mask bits
865  */
866 typedef union {
867 	uint32_t value;
868 	struct {
869 #if defined(_BIG_ENDIAN)
870 		uint32_t	mask:32;
871 #else
872 		uint32_t	mask:32;
873 #endif
874 	} bits;
875 } msi_mask_t;
876 
877 
878 /*
879  * Register: MsiPend
880  * MSI Pending
881  * Description: MSI Pending
882  * Fields:
883  *     per vector MSI Pending bits
884  */
885 typedef union {
886 	uint32_t value;
887 	struct {
888 #if defined(_BIG_ENDIAN)
889 		uint32_t	pend:32;
890 #else
891 		uint32_t	pend:32;
892 #endif
893 	} bits;
894 } msi_pend_t;
895 
896 
897 /*
898  * Register: MsixCap
899  * MSIX Capability
900  * Description: MSIX Capability
901  * Fields:
902  *     MSIX Enable (if enabled, MSI and INTx must be disabled)
903  *     Function Mask (1 = all vectors masked regardless of per vector
904  *     mask, 0 = each vector's mask
905  *     Table Size (0x1F = 32 entries): dbi writeable
906  *     Next Capability Pointer: dbi writeable
907  *     MSIX Capability ID
908  */
909 typedef union {
910 	uint32_t value;
911 	struct {
912 #if defined(_BIG_ENDIAN)
913 		uint32_t	msix_en:1;
914 		uint32_t	func_mask:1;
915 		uint32_t	rsrvd:3;
916 		uint32_t	tab_sz:11;
917 		uint32_t	nxt_cap_ptr:8;
918 		uint32_t	msix_cap_id:8;
919 #else
920 		uint32_t	msix_cap_id:8;
921 		uint32_t	nxt_cap_ptr:8;
922 		uint32_t	tab_sz:11;
923 		uint32_t	rsrvd:3;
924 		uint32_t	func_mask:1;
925 		uint32_t	msix_en:1;
926 #endif
927 	} bits;
928 } msix_cap_t;
929 
930 
931 /*
932  * Register: MsixTabOff
933  * MSIX Table Offset
934  * Description: MSIX Table Offset
935  * Fields:
936  *     Table Offset (Base address of MSIX Table = msixTabBir.BAR +
937  *     msixTabOff) : dbi writeable
938  *     Table BAR Indicator (0x2 = BAR2 at loc 0x18) : dbi writeable
939  */
940 typedef union {
941 	uint32_t value;
942 	struct {
943 #if defined(_BIG_ENDIAN)
944 		uint32_t	msix_tab_off:29;
945 		uint32_t	msix_tab_bir:3;
946 #else
947 		uint32_t	msix_tab_bir:3;
948 		uint32_t	msix_tab_off:29;
949 #endif
950 	} bits;
951 } msix_tab_off_t;
952 
953 
954 /*
955  * Register: MsixPbaOff
956  * MSIX PBA Offset
957  * Description: MSIX PBA Offset
958  * Fields:
959  *     Pending Bit Array (PBA) Offset (Base address of MSIX Table =
960  *     msixTabBir.BAR + msixPbaOff); msixPbaOff is quad-aligned, i.e.
961  *     starts at 0x2000 (half-way in MSI-X bar space. : dbi writeable
962  *     Pending Bit Array (PBA) BAR Indicator (0x2 = BAR2 at loc 0x18)
963  *     : dbi writeable
964  */
965 typedef union {
966 	uint32_t value;
967 	struct {
968 #if defined(_BIG_ENDIAN)
969 		uint32_t	msix_pba_off:29;
970 		uint32_t	msix_pba_bir:3;
971 #else
972 		uint32_t	msix_pba_bir:3;
973 		uint32_t	msix_pba_off:29;
974 #endif
975 	} bits;
976 } msix_pba_off_t;
977 
978 
979 /*
980  * Register: PcieCap
981  * PCIE Capability
982  * Description: PCIE Capability
983  * Fields:
984  *     Interrupt Message Number (updated by HW)
985  *     Slot Implemented (Endpoint must be 0)
986  *     PCIE Express Device Port Type (Endpoint)
987  *     PCIE Express Capability Version
988  *     Next Capability Pointer: dbi writeable
989  *     PCI Express Capability ID
990  */
991 typedef union {
992 	uint32_t value;
993 	struct {
994 #if defined(_BIG_ENDIAN)
995 		uint32_t	rsrvd:2;
996 		uint32_t	int_msg_num:5;
997 		uint32_t	pcie_slt_imp:1;
998 		uint32_t	pcie_dev_type:4;
999 		uint32_t	pcie_cap_ver:4;
1000 		uint32_t	nxt_cap_ptr:8;
1001 		uint32_t	pcie_cap_id:8;
1002 #else
1003 		uint32_t	pcie_cap_id:8;
1004 		uint32_t	nxt_cap_ptr:8;
1005 		uint32_t	pcie_cap_ver:4;
1006 		uint32_t	pcie_dev_type:4;
1007 		uint32_t	pcie_slt_imp:1;
1008 		uint32_t	int_msg_num:5;
1009 		uint32_t	rsrvd:2;
1010 #endif
1011 	} bits;
1012 } pcie_cap_t;
1013 
1014 
1015 /*
1016  * Register: DevCap
1017  * Device Capability
1018  * Description: Device Capability
1019  * Fields:
1020  *     Slot Power Limit Scale (Msg from RC) Hydra can capture
1021  *     Received setSlotPowerLimit message; values in this field are
1022  *     ignored as no power scaling is possible.
1023  *     Slot Power Limit Value (Msg from RC) Hydra can capture
1024  *     Received setSlotPowerLimit message; values in this field are
1025  *     ignored as no power scaling is possible.
1026  *     Introduced in PCIe 1.1 specification. : dbi writeable
1027  *     L1 Acceptable Latency (4 - 8 us) : dbi writeable
1028  *     LOs Acceptable Latency (2 - 4 us) : dbi writeable
1029  *     Extended Tag Field Support (N/A) : dbi writeable
1030  *     Phantom Function Supported (N/A) : dbi writeable
1031  *     Maximum Payload Size supported (Hydra = 1KB) : dbi writeable
1032  */
1033 typedef union {
1034 	uint32_t value;
1035 	struct {
1036 #if defined(_BIG_ENDIAN)
1037 		uint32_t	rsrvd:4;
1038 		uint32_t	slt_pwr_lmt_scle:2;
1039 		uint32_t	slt_pwr_lmt_val:8;
1040 		uint32_t	rsrvd1:2;
1041 		uint32_t	role_based_err:1;
1042 		uint32_t	rsrvd2:3;
1043 		uint32_t	l1_lat:3;
1044 		uint32_t	los_lat:3;
1045 		uint32_t	ext_tag:1;
1046 		uint32_t	phant_func:2;
1047 		uint32_t	max_mtu:3;
1048 #else
1049 		uint32_t	max_mtu:3;
1050 		uint32_t	phant_func:2;
1051 		uint32_t	ext_tag:1;
1052 		uint32_t	los_lat:3;
1053 		uint32_t	l1_lat:3;
1054 		uint32_t	rsrvd2:3;
1055 		uint32_t	role_based_err:1;
1056 		uint32_t	rsrvd1:2;
1057 		uint32_t	slt_pwr_lmt_val:8;
1058 		uint32_t	slt_pwr_lmt_scle:2;
1059 		uint32_t	rsrvd:4;
1060 #endif
1061 	} bits;
1062 } dev_cap_t;
1063 
1064 
1065 /*
1066  * Register: DevStatCtrl
1067  * Device Status and Control
1068  * Description: Device Control
1069  * Fields:
1070  *     Transaction Pending (1 if NP request not completed)
1071  *     Auxilliary Power Detected (1 if detected)
1072  *     Unsupported Request Detect
1073  *     Fatal Error Detected
1074  *     Non-Fatal Error Detected
1075  *     Correctable Error Detected ----- Control Fields
1076  *     Introduced in PCIe 1.1 specification.
1077  *     Maximum Read Request Size (default = 512B) for the device as a
1078  *     requester. 3'b000: 128 Bytes 3'b001: 256 Bytes 3'b010: 512
1079  *     Bytes 3'b011: 1K Bytes 3'b100: 2K Bytes 3'b101: 4K Bytes
1080  *     3'b110: Reserved 3'b111: Reserved
1081  *     No Snoop Enable This bit indicates the device "could", not
1082  *     that it does. Both this bit and the hydra specific peuCip
1083  *     register bit must be set for the value of this bit to impact
1084  *     the TLP header no snoop attribute. When both are set, hydra
1085  *     sets the no snoop attribute on all initiated TLPs. Software
1086  *     must guarantee the No Snoop attribute is used in the system
1087  *     correctly.
1088  *     Auxilliary Power PM Enable
1089  *     Phantom Function enable
1090  *     Extended Tag Field Enable
1091  *     Maximum Payload Size. 3-bit value has the same encodings as
1092  *     the maxRdSz field.
1093  *     Relaxed Ordering Enable This bit indicates the device "could",
1094  *     not that it does. Both this bit and the hydra specific peuCip
1095  *     register bit must be set for the value of this bit to impact
1096  *     the TLP header relaxed ordering attribute. When both are set,
1097  *     packet operations set the relaxed ordering attribute. Mailbox
1098  *     updates always set the relaxed ordering attribute to 0,
1099  *     regardless of this bit. When this bit is 0, the default
1100  *     Sun4u/Sun4v ordering model is used.
1101  *     Unsupported Request Report Enable
1102  *     Fatal Error Report Enable
1103  *     Non-Fatal Error Report Enable
1104  *     Correctable Error Report Enable
1105  */
1106 typedef union {
1107 	uint32_t value;
1108 	struct {
1109 #if defined(_BIG_ENDIAN)
1110 		uint32_t	rsrvd:10;
1111 		uint32_t	trans_pend:1;
1112 		uint32_t	aux_pwr_det:1;
1113 		uint32_t	unsup_req_det:1;
1114 		uint32_t	fat_err_det:1;
1115 		uint32_t	nf_err_det:1;
1116 		uint32_t	corr_err_det:1;
1117 		uint32_t	pcie2pcix_brdg:1;
1118 		uint32_t	max_rd_sz:3;
1119 		uint32_t	no_snoop_en:1;
1120 		uint32_t	aux_pwr_pm_en:1;
1121 		uint32_t	phant_func_en:1;
1122 		uint32_t	ext_tag_en:1;
1123 		uint32_t	max_pld_sz:3;
1124 		uint32_t	rlx_ord_en:1;
1125 		uint32_t	unsup_req_en:1;
1126 		uint32_t	fat_err_en:1;
1127 		uint32_t	nf_err_en:1;
1128 		uint32_t	corr_err_en:1;
1129 #else
1130 		uint32_t	corr_err_en:1;
1131 		uint32_t	nf_err_en:1;
1132 		uint32_t	fat_err_en:1;
1133 		uint32_t	unsup_req_en:1;
1134 		uint32_t	rlx_ord_en:1;
1135 		uint32_t	max_pld_sz:3;
1136 		uint32_t	ext_tag_en:1;
1137 		uint32_t	phant_func_en:1;
1138 		uint32_t	aux_pwr_pm_en:1;
1139 		uint32_t	no_snoop_en:1;
1140 		uint32_t	max_rd_sz:3;
1141 		uint32_t	pcie2pcix_brdg:1;
1142 		uint32_t	corr_err_det:1;
1143 		uint32_t	nf_err_det:1;
1144 		uint32_t	fat_err_det:1;
1145 		uint32_t	unsup_req_det:1;
1146 		uint32_t	aux_pwr_det:1;
1147 		uint32_t	trans_pend:1;
1148 		uint32_t	rsrvd:10;
1149 #endif
1150 	} bits;
1151 } dev_stat_ctrl_t;
1152 
1153 
1154 /*
1155  * Register: LnkCap
1156  * Link Capability
1157  * Description: Link Capability
1158  * Fields:
1159  *     Port Number : dbi writeable
1160  *     Introduced in PCIe 1.1 specification.
1161  *     Introduced in PCIe 1.1 specification.
1162  *     Default Clock Power Management (N/A) Introduced in PCIe 1.1
1163  *     specification. : dbi writeable
1164  *     Default L1 Exit Latency (32us to 64us => 0x6) : dbi writeable
1165  *     Default L0s Exit Latency (1us to 2us => 0x5) : dbi writeable
1166  *     Active Link PM Support (only L0s = 1) : dbi writeable
1167  *     Maximum Link Width (x8) : dbi writeable
1168  *     Maximum Link Speed (2.5 Gbps = 1) : dbi writeable
1169  */
1170 typedef union {
1171 	uint32_t value;
1172 	struct {
1173 #if defined(_BIG_ENDIAN)
1174 		uint32_t	prt_num:8;
1175 		uint32_t	rsrvd:3;
1176 		uint32_t	def_dll_act_rptg:1;
1177 		uint32_t	def_surpise_down:1;
1178 		uint32_t	def_clk_pm_cap:1;
1179 		uint32_t	def_l1_lat:3;
1180 		uint32_t	def_l0s_lat:3;
1181 		uint32_t	as_lnk_pm_supt:2;
1182 		uint32_t	max_lnk_wid:6;
1183 		uint32_t	max_lnk_spd:4;
1184 #else
1185 		uint32_t	max_lnk_spd:4;
1186 		uint32_t	max_lnk_wid:6;
1187 		uint32_t	as_lnk_pm_supt:2;
1188 		uint32_t	def_l0s_lat:3;
1189 		uint32_t	def_l1_lat:3;
1190 		uint32_t	def_clk_pm_cap:1;
1191 		uint32_t	def_surpise_down:1;
1192 		uint32_t	def_dll_act_rptg:1;
1193 		uint32_t	rsrvd:3;
1194 		uint32_t	prt_num:8;
1195 #endif
1196 	} bits;
1197 } lnk_cap_t;
1198 
1199 
1200 /*
1201  * Register: LnkStatCtrl
1202  * Link Status and Control
1203  * Description: Link Control
1204  * Fields:
1205  *     Slot Clock Configuration (0 = using independent clock; pg 266
1206  *     PCIe 1.1) : dbi writeable
1207  *     Link Training (N/A for EP)
1208  *     Training Error (N/A for EP)
1209  *     Negotiated Link Width (Max negotiated: x8)
1210  *     Negotiated Link Speed (Max negotiated: 1 = 2.5 Gbps) -----
1211  *     Control Fields
1212  *     Introduced in PCIe 1.1.
1213  *     Extended Synch
1214  *     Common Clock Configuration
1215  *     Retrain Link (N/A for EP)
1216  *     Link Disable (N/A for EP)
1217  *     Read Completion Boundary (128B)
1218  *     Active State Link PM Control
1219  */
1220 typedef union {
1221 	uint32_t value;
1222 	struct {
1223 #if defined(_BIG_ENDIAN)
1224 		uint32_t	rsrvd:2;
1225 		uint32_t	dll_active:1;
1226 		uint32_t	slt_clk_cfg:1;
1227 		uint32_t	lnk_train:1;
1228 		uint32_t	train_err:1;
1229 		uint32_t	lnk_wid:6;
1230 		uint32_t	lnk_spd:4;
1231 		uint32_t	rsrvd1:7;
1232 		uint32_t	en_clkpwr_mg:1;
1233 		uint32_t	ext_sync:1;
1234 		uint32_t	com_clk_cfg:1;
1235 		uint32_t	retrain_lnk:1;
1236 		uint32_t	lnk_dis:1;
1237 		uint32_t	rd_cmpl_bndy:1;
1238 		uint32_t	rsrvd2:1;
1239 		uint32_t	aspm_ctrl:2;
1240 #else
1241 		uint32_t	aspm_ctrl:2;
1242 		uint32_t	rsrvd2:1;
1243 		uint32_t	rd_cmpl_bndy:1;
1244 		uint32_t	lnk_dis:1;
1245 		uint32_t	retrain_lnk:1;
1246 		uint32_t	com_clk_cfg:1;
1247 		uint32_t	ext_sync:1;
1248 		uint32_t	en_clkpwr_mg:1;
1249 		uint32_t	rsrvd1:7;
1250 		uint32_t	lnk_spd:4;
1251 		uint32_t	lnk_wid:6;
1252 		uint32_t	train_err:1;
1253 		uint32_t	lnk_train:1;
1254 		uint32_t	slt_clk_cfg:1;
1255 		uint32_t	dll_active:1;
1256 		uint32_t	rsrvd:2;
1257 #endif
1258 	} bits;
1259 } lnk_stat_ctrl_t;
1260 
1261 
1262 /*
1263  * Register: VenCapHdr
1264  * Vendor Specific Capability Header
1265  * Description: Vendor Specific Capability Header
1266  * Fields:
1267  *     Length
1268  *     Next Capbility Pointer
1269  *     Vendor Specific Capbility ID
1270  */
1271 typedef union {
1272 	uint32_t value;
1273 	struct {
1274 #if defined(_BIG_ENDIAN)
1275 		uint32_t	rsrvd:8;
1276 		uint32_t	len:8;
1277 		uint32_t	nxt_cap_ptr:8;
1278 		uint32_t	ven_cap_id:8;
1279 #else
1280 		uint32_t	ven_cap_id:8;
1281 		uint32_t	nxt_cap_ptr:8;
1282 		uint32_t	len:8;
1283 		uint32_t	rsrvd:8;
1284 #endif
1285 	} bits;
1286 } ven_cap_hdr_t;
1287 
1288 
1289 /*
1290  * Register: VenCtrl
1291  * Vendor Specific Control
1292  * Description: Vendor Specific Control
1293  * Fields:
1294  *     PCIe spec absolute minimum is 50usec - (likely ~10ms). PCIe
1295  *     spec absolute max is 50msec. Default set for 22.2 msec via
1296  *     adding time as follows: Bit 23: 3.21 secs <---POR 0 Bit 22:
1297  *     201.3 msec <---POR 0 Bit 21: 100.8 msec <---POR 0 Bit 20: 25.2
1298  *     msec <---POR 0 Bit 19: 12.6 msec <---POR 1 Bit 18: 6.3 msec
1299  *     <---POR 1 Bit 17: 3.3 msec <---POR 1 Bit 16: if 0:
1300  *     Baseline0=50usec; else Baseline1(use for
1301  *     simulation-only)=804nsec
1302  *     Interrupt Control Mode (00 = Reserved, 01 = INTx emulation, 10
1303  *     = Reserved [Neptune INTx pins], 11 = Reserved [Neptune INTx
1304  *     emulation + pins]
1305  */
1306 typedef union {
1307 	uint32_t value;
1308 	struct {
1309 #if defined(_BIG_ENDIAN)
1310 		uint32_t	rsrvd:8;
1311 		uint32_t	eic_xtd_cpl_timout:8;
1312 		uint32_t	rsrvd1:14;
1313 		uint32_t	legacy_int_ctrl:2;
1314 #else
1315 		uint32_t	legacy_int_ctrl:2;
1316 		uint32_t	rsrvd1:14;
1317 		uint32_t	eic_xtd_cpl_timout:8;
1318 		uint32_t	rsrvd:8;
1319 #endif
1320 	} bits;
1321 } ven_ctrl_t;
1322 
1323 
1324 /*
1325  * Register: VenPrtHdr
1326  * Vendor Specific Port Logic Header
1327  * Description: Vendor Specific Port Logic Header
1328  * Fields:
1329  *     Length
1330  *     Next Capbility Pointer (END, no more)
1331  *     Vendor Specific Capbility ID
1332  */
1333 typedef union {
1334 	uint32_t value;
1335 	struct {
1336 #if defined(_BIG_ENDIAN)
1337 		uint32_t	rsrvd:8;
1338 		uint32_t	len:8;
1339 		uint32_t	nxt_cap_ptr:8;
1340 		uint32_t	ven_cap_id:8;
1341 #else
1342 		uint32_t	ven_cap_id:8;
1343 		uint32_t	nxt_cap_ptr:8;
1344 		uint32_t	len:8;
1345 		uint32_t	rsrvd:8;
1346 #endif
1347 	} bits;
1348 } ven_prt_hdr_t;
1349 
1350 
1351 /*
1352  * Register: AcklatReplay
1353  * Ack Latency and Replay Timer register
1354  * Description: Ack Latency/Replay Timer
1355  * Fields:
1356  *     Replay Time limit = 16'd12429/`cxNb where cxNb=1.
1357  *     Round Trip Latency Time limit = 9d'4143/`cxNb where cxNb=1.
1358  */
1359 typedef union {
1360 	uint32_t value;
1361 	struct {
1362 #if defined(_BIG_ENDIAN)
1363 		uint32_t	rep_tim:16;
1364 		uint32_t	ack_tim:16;
1365 #else
1366 		uint32_t	ack_tim:16;
1367 		uint32_t	rep_tim:16;
1368 #endif
1369 	} bits;
1370 } acklat_replay_t;
1371 
1372 
1373 /*
1374  * Register: OthMsg
1375  * Other Message Register
1376  * Description: Other Message Register
1377  * Fields:
1378  *     Message to send/Data to corrupt LCRC
1379  */
1380 typedef union {
1381 	uint32_t value;
1382 	struct {
1383 #if defined(_BIG_ENDIAN)
1384 		uint32_t	oth_msg:32;
1385 #else
1386 		uint32_t	oth_msg:32;
1387 #endif
1388 	} bits;
1389 } oth_msg_t;
1390 
1391 
1392 /*
1393  * Register: ForceLink
1394  * Port Force Link
1395  * Description: Other Message Register
1396  * Fields:
1397  *     LinkState that the EP core will be forced to when ForceLink
1398  *     (bit[15]) is set
1399  *     Forces Link to the specified LinkState field below. Write this
1400  *     bit to generate a pulse to the ltssm. It clears itself once
1401  *     the pulse is generated. Read will always return 0.
1402  *     Link Number - N/A for Endpoint
1403  */
1404 typedef union {
1405 	uint32_t value;
1406 	struct {
1407 #if defined(_BIG_ENDIAN)
1408 		uint32_t	rsrvd:10;
1409 		uint32_t	link_state:6;
1410 		uint32_t	force_link:1;
1411 		uint32_t	rsrvd1:7;
1412 		uint32_t	link_num:8;
1413 #else
1414 		uint32_t	link_num:8;
1415 		uint32_t	rsrvd1:7;
1416 		uint32_t	force_link:1;
1417 		uint32_t	link_state:6;
1418 		uint32_t	rsrvd:10;
1419 #endif
1420 	} bits;
1421 } force_link_t;
1422 
1423 
1424 /*
1425  * Register: AckFreq
1426  * ACK Frequency Register
1427  * Description: ACK Frequency Register
1428  * Fields:
1429  *     NFTS = 115.
1430  *     NFTS = 115.
1431  */
1432 typedef union {
1433 	uint32_t value;
1434 	struct {
1435 #if defined(_BIG_ENDIAN)
1436 		uint32_t	rsrvd:2;
1437 		uint32_t	l1_entr_latency:3;
1438 		uint32_t	los_entr_latency:3;
1439 		uint32_t	cx_comm_nfts:8;
1440 		uint32_t	nfts:8;
1441 		uint32_t	def_ack_freq:8;
1442 #else
1443 		uint32_t	def_ack_freq:8;
1444 		uint32_t	nfts:8;
1445 		uint32_t	cx_comm_nfts:8;
1446 		uint32_t	los_entr_latency:3;
1447 		uint32_t	l1_entr_latency:3;
1448 		uint32_t	rsrvd:2;
1449 #endif
1450 	} bits;
1451 } ack_freq_t;
1452 
1453 
1454 /*
1455  * Register: LinkCtrl
1456  * Port Link Control
1457  * Description: Port Link Control
1458  * Fields:
1459  *     8 lanes
1460  *     When set, this bit is only set for 1 cycle. A write of 0 has
1461  *     no effect.
1462  */
1463 typedef union {
1464 	uint32_t value;
1465 	struct {
1466 #if defined(_BIG_ENDIAN)
1467 		uint32_t	rsrvd:4;
1468 		uint32_t	rsrvd1:2;
1469 		uint32_t	corrupt_lcrc:1;
1470 		uint32_t	rsrvd2:1;
1471 		uint32_t	rsrvd3:2;
1472 		uint32_t	link_mode_en:6;
1473 		uint32_t	rsrvd4:4;
1474 		uint32_t	rsrvd5:4;
1475 		uint32_t	fast_link_mode:1;
1476 		uint32_t	rsrvd6:1;
1477 		uint32_t	dll_link_en:1;
1478 		uint32_t	rsrvd7:1;
1479 		uint32_t	reset_assert:1;
1480 		uint32_t	lpbk_en:1;
1481 		uint32_t	scram_dis:1;
1482 		uint32_t	oth_msg_req:1;
1483 #else
1484 		uint32_t	oth_msg_req:1;
1485 		uint32_t	scram_dis:1;
1486 		uint32_t	lpbk_en:1;
1487 		uint32_t	reset_assert:1;
1488 		uint32_t	rsrvd7:1;
1489 		uint32_t	dll_link_en:1;
1490 		uint32_t	rsrvd6:1;
1491 		uint32_t	fast_link_mode:1;
1492 		uint32_t	rsrvd5:4;
1493 		uint32_t	rsrvd4:4;
1494 		uint32_t	link_mode_en:6;
1495 		uint32_t	rsrvd3:2;
1496 		uint32_t	rsrvd2:1;
1497 		uint32_t	corrupt_lcrc:1;
1498 		uint32_t	rsrvd1:2;
1499 		uint32_t	rsrvd:4;
1500 #endif
1501 	} bits;
1502 } link_ctrl_t;
1503 
1504 
1505 /*
1506  * Register: LaneSkew
1507  * Lane Skew Register
1508  * Description: Lane Skew Register
1509  * Fields:
1510  *     prevents EP core from sending Ack/Nack DLLPs
1511  *     prevents EP core from sending FC DLLPs
1512  */
1513 typedef union {
1514 	uint32_t value;
1515 	struct {
1516 #if defined(_BIG_ENDIAN)
1517 		uint32_t	dis_lane_to_lane_deskew:1;
1518 		uint32_t	rsrvd:5;
1519 		uint32_t	ack_nack_dis:1;
1520 		uint32_t	flow_control_dis:1;
1521 		uint32_t	tx_lane_skew:24;
1522 #else
1523 		uint32_t	tx_lane_skew:24;
1524 		uint32_t	flow_control_dis:1;
1525 		uint32_t	ack_nack_dis:1;
1526 		uint32_t	rsrvd:5;
1527 		uint32_t	dis_lane_to_lane_deskew:1;
1528 #endif
1529 	} bits;
1530 } lane_skew_t;
1531 
1532 
1533 /*
1534  * Register: SymbolNum
1535  * Symbol Number Register
1536  * Description: Symbol Number Register
1537  * Fields:
1538  *     Timer modifier for Flow control Watch Dog timer
1539  *     Timer modifier for Ack/Nack latency timer
1540  *     Timer modifier for Replay timer
1541  *     Note: rtl uses defaultNSkipSymbols
1542  *     Note: rtl initialized using defaultNTs1Symbols
1543  */
1544 typedef union {
1545 	uint32_t value;
1546 	struct {
1547 #if defined(_BIG_ENDIAN)
1548 		uint32_t	rsrvd:3;
1549 		uint32_t	fc_wdog_tim_mod:5;
1550 		uint32_t	ack_nack_tim_mod:5;
1551 		uint32_t	rep_tim_mod:5;
1552 		uint32_t	rsrvd1:3;
1553 		uint32_t	num_skip_symb:3;
1554 		uint32_t	rsrvd2:4;
1555 		uint32_t	num_ts_symb:4;
1556 #else
1557 		uint32_t	num_ts_symb:4;
1558 		uint32_t	rsrvd2:4;
1559 		uint32_t	num_skip_symb:3;
1560 		uint32_t	rsrvd1:3;
1561 		uint32_t	rep_tim_mod:5;
1562 		uint32_t	ack_nack_tim_mod:5;
1563 		uint32_t	fc_wdog_tim_mod:5;
1564 		uint32_t	rsrvd:3;
1565 #endif
1566 	} bits;
1567 } symbol_num_t;
1568 
1569 
1570 /*
1571  * Register: SymbTimRadmFlt1
1572  * Symbol Timer Register / RADM Filter Mask Register 1
1573  * Description: Symbol Timer / RADM Filter Mask 1
1574  * Fields:
1575  *     No masking errors while filtering
1576  */
1577 typedef union {
1578 	uint32_t value;
1579 	struct {
1580 #if defined(_BIG_ENDIAN)
1581 		uint32_t	mask_radm_flt:16;
1582 		uint32_t	dis_fc_wdog:1;
1583 		uint32_t	rsrvd:4;
1584 		uint32_t	skip_interval:11;
1585 #else
1586 		uint32_t	skip_interval:11;
1587 		uint32_t	rsrvd:4;
1588 		uint32_t	dis_fc_wdog:1;
1589 		uint32_t	mask_radm_flt:16;
1590 #endif
1591 	} bits;
1592 } symb_tim_radm_flt1_t;
1593 
1594 
1595 /*
1596  * Register: RadmFlt2
1597  * RADM Filter Mask Register 2
1598  * Description: RADM Filter Mask Register 2
1599  * Fields:
1600  *     [31:2] = Reserved [1]=0=Vendor MSG Type0 dropped & treated as
1601  *     UR, [0]=0=Vendor MSG Type1 silently dropped.
1602  */
1603 typedef union {
1604 	uint32_t value;
1605 	struct {
1606 #if defined(_BIG_ENDIAN)
1607 		uint32_t	mask_radm_flt:32;
1608 #else
1609 		uint32_t	mask_radm_flt:32;
1610 #endif
1611 	} bits;
1612 } radm_flt2_t;
1613 
1614 
1615 /*
1616  * Register: CascadeDebReg0
1617  * Cascade core (EP) Debug Register 0
1618  * Description: Debug Register 0 EP Core SII Interface bus :
1619  * cxplDebugInfo[31:0]
1620  * Fields:
1621  */
1622 typedef union {
1623 	uint32_t value;
1624 	struct {
1625 #if defined(_BIG_ENDIAN)
1626 		uint32_t	rmlh_ts_link_ctrl:4;
1627 		uint32_t	rmlh_ts_lane_num_is_k237:1;
1628 		uint32_t	rmlh_ts_link_num_is_k237:1;
1629 		uint32_t	rmlh_rcvd_idle_bit0:1;
1630 		uint32_t	rmlh_rcvd_idle_bit1:1;
1631 		uint32_t	mac_phy_txdata:16;
1632 		uint32_t	mac_phy_txdatak:2;
1633 		uint32_t	rsrvd:1;
1634 		uint32_t	xmlh_ltssm_state:5;
1635 #else
1636 		uint32_t	xmlh_ltssm_state:5;
1637 		uint32_t	rsrvd:1;
1638 		uint32_t	mac_phy_txdatak:2;
1639 		uint32_t	mac_phy_txdata:16;
1640 		uint32_t	rmlh_rcvd_idle_bit1:1;
1641 		uint32_t	rmlh_rcvd_idle_bit0:1;
1642 		uint32_t	rmlh_ts_link_num_is_k237:1;
1643 		uint32_t	rmlh_ts_lane_num_is_k237:1;
1644 		uint32_t	rmlh_ts_link_ctrl:4;
1645 #endif
1646 	} bits;
1647 } cascade_deb_reg0_t;
1648 
1649 
1650 /*
1651  * Register: CascadeDebReg1
1652  * Cascade Core (EP) Debug Register 1
1653  * Description: Debug Register 1 EP Core SII Interface bus :
1654  * cxplDebugInfo[63:32]
1655  * Fields:
1656  *     PCIe Link status. 0=down, 1=up
1657  */
1658 typedef union {
1659 	uint32_t value;
1660 	struct {
1661 #if defined(_BIG_ENDIAN)
1662 		uint32_t	xmlh_scrambler_disable:1;
1663 		uint32_t	xmlh_link_disable:1;
1664 		uint32_t	xmlh_link_in_training:1;
1665 		uint32_t	xmlh_rcvr_revrs_pol_en:1;
1666 		uint32_t	xmlh_training_rst_n:1;
1667 		uint32_t	rsrvd:4;
1668 		uint32_t	mac_phy_txdetectrx_loopback:1;
1669 		uint32_t	mac_phy_txelecidle_bit0:1;
1670 		uint32_t	mac_phy_txcompliance_bit0:1;
1671 		uint32_t	app_init_rst:1;
1672 		uint32_t	rsrvd1:3;
1673 		uint32_t	rmlh_rs_link_num:8;
1674 		uint32_t	rmlh_link_mode:3;
1675 		uint32_t	xmlh_link_up:1;
1676 		uint32_t	rmlh_inskip_rcv:1;
1677 		uint32_t	rmlh_ts1_rcvd:1;
1678 		uint32_t	rmlh_ts2_rcvd:1;
1679 		uint32_t	rmlh_rcvd_lane_rev:1;
1680 #else
1681 		uint32_t	rmlh_rcvd_lane_rev:1;
1682 		uint32_t	rmlh_ts2_rcvd:1;
1683 		uint32_t	rmlh_ts1_rcvd:1;
1684 		uint32_t	rmlh_inskip_rcv:1;
1685 		uint32_t	xmlh_link_up:1;
1686 		uint32_t	rmlh_link_mode:3;
1687 		uint32_t	rmlh_rs_link_num:8;
1688 		uint32_t	rsrvd1:3;
1689 		uint32_t	app_init_rst:1;
1690 		uint32_t	mac_phy_txcompliance_bit0:1;
1691 		uint32_t	mac_phy_txelecidle_bit0:1;
1692 		uint32_t	mac_phy_txdetectrx_loopback:1;
1693 		uint32_t	rsrvd:4;
1694 		uint32_t	xmlh_training_rst_n:1;
1695 		uint32_t	xmlh_rcvr_revrs_pol_en:1;
1696 		uint32_t	xmlh_link_in_training:1;
1697 		uint32_t	xmlh_link_disable:1;
1698 		uint32_t	xmlh_scrambler_disable:1;
1699 #endif
1700 	} bits;
1701 } cascade_deb_reg1_t;
1702 
1703 
1704 /*
1705  * Register: TxpFcCreditStat
1706  * Transmit Posted FC Credit Status
1707  * Description: Transmit Posted FC Credit Status
1708  * Fields:
1709  */
1710 typedef union {
1711 	uint32_t value;
1712 	struct {
1713 #if defined(_BIG_ENDIAN)
1714 		uint32_t	rsrvd:12;
1715 		uint32_t	txp_fc_hdr_credit_stat:8;
1716 		uint32_t	txp_fc_data_credit_stat:12;
1717 #else
1718 		uint32_t	txp_fc_data_credit_stat:12;
1719 		uint32_t	txp_fc_hdr_credit_stat:8;
1720 		uint32_t	rsrvd:12;
1721 #endif
1722 	} bits;
1723 } txp_fc_credit_stat_t;
1724 
1725 
1726 /*
1727  * Register: TxnpFcCreditStat
1728  * Transmit Non-Posted FC Credit Status
1729  * Description: Transmit Non-Posted FC Credit Status
1730  * Fields:
1731  */
1732 typedef union {
1733 	uint32_t value;
1734 	struct {
1735 #if defined(_BIG_ENDIAN)
1736 		uint32_t	rsrvd:12;
1737 		uint32_t	txnp_fc_hdr_credit_stat:8;
1738 		uint32_t	txnp_fc_data_credit_stat:12;
1739 #else
1740 		uint32_t	txnp_fc_data_credit_stat:12;
1741 		uint32_t	txnp_fc_hdr_credit_stat:8;
1742 		uint32_t	rsrvd:12;
1743 #endif
1744 	} bits;
1745 } txnp_fc_credit_stat_t;
1746 
1747 
1748 /*
1749  * Register: TxcplFcCreditStat
1750  * Transmit Completion FC Credit Status
1751  * Description: Transmit Completion FC Credit Status
1752  * Fields:
1753  */
1754 typedef union {
1755 	uint32_t value;
1756 	struct {
1757 #if defined(_BIG_ENDIAN)
1758 		uint32_t	rsrvd:12;
1759 		uint32_t	txcpl_fc_hdr_credit_stat:8;
1760 		uint32_t	txcpl_fc_data_credit_stat:12;
1761 #else
1762 		uint32_t	txcpl_fc_data_credit_stat:12;
1763 		uint32_t	txcpl_fc_hdr_credit_stat:8;
1764 		uint32_t	rsrvd:12;
1765 #endif
1766 	} bits;
1767 } txcpl_fc_credit_stat_t;
1768 
1769 
1770 /*
1771  * Register: QueueStat
1772  * Queue Status
1773  * Description: Queue Status
1774  * Fields:
1775  */
1776 typedef union {
1777 	uint32_t value;
1778 	struct {
1779 #if defined(_BIG_ENDIAN)
1780 		uint32_t	rsrvd:29;
1781 		uint32_t	rx_queue_not_empty:1;
1782 		uint32_t	tx_rbuf_not_empty:1;
1783 		uint32_t	tx_fc_credit_not_ret:1;
1784 #else
1785 		uint32_t	tx_fc_credit_not_ret:1;
1786 		uint32_t	tx_rbuf_not_empty:1;
1787 		uint32_t	rx_queue_not_empty:1;
1788 		uint32_t	rsrvd:29;
1789 #endif
1790 	} bits;
1791 } queue_stat_t;
1792 
1793 
1794 /*
1795  * Register: GbtDebug0
1796  * GBT Debug, Status register
1797  * Description: This register returns bits [31:0] of the PIPE core's
1798  * gbtDebug bus
1799  * Fields:
1800  *     [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
1801  *     tbcout10O will always read 1'b0
1802  * The value specified here is the Power On Reset value as given
1803  *     in spec. except for the clock bits which are hardwired to
1804  *     1'b0.
1805  * The gbtDebug[0:15] bus is provided for each lane as an output
1806  *     from the pcieGbtopWrapper.v module. These signals are not
1807  *     required for manufacturing test and may be left unconnected.
1808  *     The cw00041130PipeParam.vh bus width is the number of lanes
1809  *     multiplied by 16. lane0 is bits[15:0], lane1 is bits[31:16],
1810  *     lane2 is bits[47:32], lane3 is bits[63:48], lane4 is
1811  *     bits[79:64], lane5 is bits[95:80], lane6 is bits[111:96],
1812  *     lane7 is bits[127:112].
1813  * Refer to section 4.2.2.4, Gigablaze Debug Signals section.
1814  *     (pgs 4.27 - 4.28) in the following document :
1815  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
1816  *     cw000411TechMan.pdf
1817  *     lane0 is bits[15:0], which is gbtDebug0[15:0] lane1 is
1818  *     bits[31:16], which is gbtDebug0[31:16]
1819  *
1820  *     -------------------------------------------------------------------------
1821  *     Signal Bit Reset Description
1822  *     -------------------------------------------------------------------------
1823  *     gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
1824  *     gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
1825  *     gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
1826  *     [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
1827  *     [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
1828  *     10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
1829  *     [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
1830  *     [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
1831  *     loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
1832  *     active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
1833  *     0 reserved
1834  *     -------------------------------------------------------------------------
1835  */
1836 typedef union {
1837 	uint32_t value;
1838 	struct {
1839 #if defined(_BIG_ENDIAN)
1840 		uint32_t	data:32;
1841 #else
1842 		uint32_t	data:32;
1843 #endif
1844 	} bits;
1845 } gbt_debug0_t;
1846 
1847 
1848 /*
1849  * Register: GbtDebug1
1850  * GBT Debug, Status register
1851  * Description: This register returns bits [63:32] of the PIPE core's
1852  * gbtDebug bus
1853  * Fields:
1854  *     [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
1855  *     tbcout10O will always read 1'b0
1856  * The value specified here is the Power On Reset value as given
1857  *     in spec. except for the clock bits which are hardwired to
1858  *     1'b0.
1859  * The gbtDebug[0:15] bus is provided for each lane as an output
1860  *     from the pcieGbtopWrapper.v module. These signals are not
1861  *     required for manufacturing test and may be left unconnected.
1862  *     The cw00041130PipeParam.vh bus width is the number of lanes
1863  *     multiplied by 16.
1864  * Refer to section 4.2.2.4, Gigablaze Debug Signals section.
1865  *     (pgs 4.27 - 4.28) in the following document :
1866  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
1867  *     cw000411TechMan.pdf
1868  *     lane2 is bits[47:32], which is gbtDebug1[15:0] lane3 is
1869  *     bits[63:48], which is gbtDebug1[31:16]
1870  *
1871  *     -------------------------------------------------------------------------
1872  *     Signal Bit Reset Description
1873  *     -------------------------------------------------------------------------
1874  *     gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
1875  *     gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
1876  *     gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
1877  *     [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
1878  *     [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
1879  *     10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
1880  *     [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
1881  *     [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
1882  *     loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
1883  *     active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
1884  *     0 reserved
1885  *     -------------------------------------------------------------------------
1886  */
1887 typedef union {
1888 	uint32_t value;
1889 	struct {
1890 #if defined(_BIG_ENDIAN)
1891 		uint32_t	data:32;
1892 #else
1893 		uint32_t	data:32;
1894 #endif
1895 	} bits;
1896 } gbt_debug1_t;
1897 
1898 
1899 /*
1900  * Register: GbtDebug2
1901  * GBT Debug, Status register
1902  * Description: This register returns bits [95:64] of the PIPE core's
1903  * gbtDebug bus
1904  * Fields:
1905  *     [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
1906  *     tbcout10O will always read 1'b0
1907  * The value specified here is the Power On Reset value as given
1908  *     in spec. except for the clock bits which are hardwired to
1909  *     1'b0.
1910  * The gbtDebug[0:15] bus is provided for each lane as an output
1911  *     from the pcieGbtopWrapper.v module. These signals are not
1912  *     required for manufacturing test and may be left unconnected.
1913  *     The cw00041130PipeParam.vh bus width is the number of lanes
1914  *     multiplied by 16.
1915  * Refer to section 4.2.2.4, Gigablaze Debug Signals section.
1916  *     (pgs 4.27 - 4.28) in the following document :
1917  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
1918  *     cw000411TechMan.pdf
1919  *     lane4 is bits[79:64], which is gbtDebug2[15:0] lane5 is
1920  *     bits[95:80], which is gbtDebug2[31:16]
1921  *
1922  *     -------------------------------------------------------------------------
1923  *     Signal Bit Reset Description
1924  *     -------------------------------------------------------------------------
1925  *     gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
1926  *     gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
1927  *     gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
1928  *     [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
1929  *     [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
1930  *     10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
1931  *     [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
1932  *     [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
1933  *     loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
1934  *     active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
1935  *     0 reserved
1936  *     -------------------------------------------------------------------------
1937  */
1938 typedef union {
1939 	uint32_t value;
1940 	struct {
1941 #if defined(_BIG_ENDIAN)
1942 		uint32_t	data:32;
1943 #else
1944 		uint32_t	data:32;
1945 #endif
1946 	} bits;
1947 } gbt_debug2_t;
1948 
1949 
1950 /*
1951  * Register: GbtDebug3
1952  * GBT Debug, Status register
1953  * Description: This register returns bits [127:96] of the PIPE
1954  * core's gbtDebug bus
1955  * Fields:
1956  *     [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
1957  *     tbcout10O will always read 1'b0
1958  * The value specified here is the Power On Reset value as given
1959  *     in spec. except for the clock bits which are hardwired to
1960  *     1'b0.
1961  * The gbtDebug[0:15] bus is provided for each lane as an output
1962  *     from the pcieGbtopWrapper.v module. These signals are not
1963  *     required for manufacturing test and may be left unconnected.
1964  *     The cw00041130PipeParam.vh bus width is the number of lanes
1965  *     multiplied by 16.
1966  * Refer to section 4.2.2.4, Gigablaze Debug Signals section.
1967  *     (pgs 4.27 - 4.28) in the following document :
1968  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
1969  *     cw000411TechMan.pdf
1970  *     lane6 is bits[111:96], which is gbtDebug3[15:0] lane7 is
1971  *     bits[127:112], which is gbtDebug3[31:16]
1972  *
1973  *     -------------------------------------------------------------------------
1974  *     Signal Bit Reset Description
1975  *     -------------------------------------------------------------------------
1976  *     gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
1977  *     gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
1978  *     gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
1979  *     [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
1980  *     [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
1981  *     10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
1982  *     [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
1983  *     [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
1984  *     loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
1985  *     active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
1986  *     0 reserved
1987  *     -------------------------------------------------------------------------
1988  */
1989 typedef union {
1990 	uint32_t value;
1991 	struct {
1992 #if defined(_BIG_ENDIAN)
1993 		uint32_t	data:32;
1994 #else
1995 		uint32_t	data:32;
1996 #endif
1997 	} bits;
1998 } gbt_debug3_t;
1999 
2000 
2001 /*
2002  * Register: PipeDebug0
2003  * PIPE Debug, status register
2004  * Description: This register returns bits [31:0] of the PIPE core's
2005  * gbtDebug bus
2006  * Fields:
2007  *     The value specified here is the Power On Reset value as given
2008  *     in spec.
2009  * This 16-bit debug bus reports operating conditions for the
2010  *     PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2011  *     is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2012  *     lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2013  *     bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2014  * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
2015  *     the following document :
2016  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
2017  *     cw000411TechMan.pdf
2018  *     lane0 is bit[15:0], which is pipeDebug0[15:0] lane1 is
2019  *     bit[31:16], which is pipeDebug0[31:16]
2020  *
2021  *     -------------------------------------------------------------------------
2022  *     pipeDebug Signal or Condition Description Reset
2023  *     -------------------------------------------------------------------------
2024  *     [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
2025  *     underflow occurred
2026  * [14] skipInsert or EFIFO skip inserted or 0 skipDelete
2027  *     deleted 0
2028  * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
2029  *     Used with skipcharflag to verify EFIFO depth.
2030  * [12] skipcharflag Skip flag written by EFIFO 0
2031  * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
2032  * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
2033  *     output
2034  * [6] efifoBytesync EFIFO output byte 0 synchronization
2035  * [5] rxinvalid 8b/10b error or 0 or code violation
2036  * [4] rxinitdone Receiver bit-init done. 0 Synchronous with
2037  *     pipeClk.
2038  * [3] txinitdone Transmitter-bit init done. 0 Synchronous with
2039  *     pipeClk.
2040  * [2] filteredrxlos Filtered loss of signal used 1 to generate
2041  *     p2lRxelectidle. Synchronous with pipeClk.
2042  * [1] rxdetectInt Receiver detected 0
2043  * [0] pipeMasterDoneOut Receiver detection valid 0
2044  *
2045  */
2046 typedef union {
2047 	uint32_t value;
2048 	struct {
2049 #if defined(_BIG_ENDIAN)
2050 		uint32_t	data:32;
2051 #else
2052 		uint32_t	data:32;
2053 #endif
2054 	} bits;
2055 } pipe_debug0_t;
2056 
2057 
2058 /*
2059  * Register: PipeDebug1
2060  * PIPE Debug, status register
2061  * Description: This register returns bits [63:32] of the PIPE core's
2062  * gbtDebug bus
2063  * Fields:
2064  *     The value specified here is the Power On Reset value as given
2065  *     in spec.
2066  * This 16-bit debug bus reports operating conditions for the
2067  *     PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2068  *     is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2069  *     lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2070  *     bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2071  * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
2072  *     the following document :
2073  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
2074  *     cw000411TechMan.pdf
2075  * lane2 is bits[47:32], which is pipeDebug1[15:0] lane3 is
2076  *     bits[63:48], which is pipeDebug1[31:16]
2077  *
2078  *     -------------------------------------------------------------------------
2079  *     pipeDebug Signal or Condition Description Reset
2080  *     -------------------------------------------------------------------------
2081  *     [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
2082  *     underflow occurred
2083  * [14] skipInsert or EFIFO skip inserted or 0 skipDelete
2084  *     deleted 0
2085  * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
2086  *     Used with skipcharflag to verify EFIFO depth.
2087  * [12] skipcharflag Skip flag written by EFIFO 0
2088  * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
2089  * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
2090  *     output
2091  * [6] efifoBytesync EFIFO output byte 0 synchronization
2092  * [5] rxinvalid 8b/10b error or 0 or code violation
2093  * [4] rxinitdone Receiver bit-init done. 0 Synchronous with
2094  *     pipeClk.
2095  * [3] txinitdone Transmitter-bit init done. 0 Synchronous with
2096  *     pipeClk.
2097  * [2] filteredrxlos Filtered loss of signal used 1 to generate
2098  *     p2lRxelectidle. Synchronous with pipeClk.
2099  * [1] rxdetectInt Receiver detected 0
2100  * [0] pipeMasterDoneOut Receiver detection valid 0
2101  *
2102  */
2103 typedef union {
2104 	uint32_t value;
2105 	struct {
2106 #if defined(_BIG_ENDIAN)
2107 		uint32_t	data:32;
2108 #else
2109 		uint32_t	data:32;
2110 #endif
2111 	} bits;
2112 } pipe_debug1_t;
2113 
2114 
2115 /*
2116  * Register: PipeDebug2
2117  * PIPE Debug, status register
2118  *     The value specified here is the Power On Reset value as given
2119  *     in spec.
2120  * This 16-bit debug bus reports operating conditions for the
2121  *     PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2122  *     is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2123  *     lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2124  *     bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2125  * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
2126  *     the following document :
2127  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
2128  *     cw000411TechMan.pdf
2129  * lane4 is bits[79:64], which is pipeDebug2[15:0] lane5 is
2130  *     bits[95:80], which is pipeDebug2[31:16]
2131  *
2132  *     -------------------------------------------------------------------------
2133  *     pipeDebug Signal or Condition Description Reset
2134  *     -------------------------------------------------------------------------
2135  *     [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
2136  *     underflow occurred
2137  * [14] skipInsert or EFIFO skip inserted or 0 skipDelete
2138  *     deleted 0
2139  * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
2140  *     Used with skipcharflag to verify EFIFO depth.
2141  * [12] skipcharflag Skip flag written by EFIFO 0
2142  * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
2143  * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
2144  *     output
2145  * [6] efifoBytesync EFIFO output byte 0 synchronization
2146  * [5] rxinvalid 8b/10b error or 0 or code violation
2147  * [4] rxinitdone Receiver bit-init done. 0 Synchronous with
2148  *     pipeClk.
2149  * [3] txinitdone Transmitter-bit init done. 0 Synchronous with
2150  *     pipeClk.
2151  * [2] filteredrxlos Filtered loss of signal used 1 to generate
2152  *     p2lRxelectidle. Synchronous with pipeClk.
2153  * [1] rxdetectInt Receiver detected 0
2154  * [0] pipeMasterDoneOut Receiver detection valid 0
2155  *
2156  */
2157 typedef union {
2158 	uint32_t value;
2159 	struct {
2160 #if defined(_BIG_ENDIAN)
2161 		uint32_t	data:32;
2162 #else
2163 		uint32_t	data:32;
2164 #endif
2165 	} bits;
2166 } pipe_debug2_t;
2167 
2168 
2169 /*
2170  * Register: PipeDebug3
2171  * PIPE Debug, status register
2172  * Description: This register returns bits [127:96] of the PIPE
2173  * core's gbtDebug bus
2174  * Fields:
2175  *     The value specified here is the Power On Reset value as given
2176  *     in spec.
2177  * This 16-bit debug bus reports operating conditions for the
2178  *     PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2179  *     is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2180  *     lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2181  *     bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2182  * Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
2183  *     the following document :
2184  *     /home/cadtools/cores/lsi/cw000411/cw00041131/prod/docs/manuals/
2185  *     cw000411TechMan.pdf
2186  * lane6 is bits[111:96], which is pipeDebug3[15:0] lane7 is
2187  *     bits[127:112], which is pipeDebug3[31:16]
2188  *
2189  *     -------------------------------------------------------------------------
2190  *     pipeDebug Signal or Condition Description Reset
2191  *     -------------------------------------------------------------------------
2192  *     [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
2193  *     underflow occurred
2194  * [14] skipInsert or EFIFO skip inserted or 0 skipDelete
2195  *     deleted 0
2196  * [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
2197  *     Used with skipcharflag to verify EFIFO depth.
2198  * [12] skipcharflag Skip flag written by EFIFO 0
2199  * [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
2200  * [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
2201  *     output
2202  * [6] efifoBytesync EFIFO output byte 0 synchronization
2203  * [5] rxinvalid 8b/10b error or 0 or code violation
2204  * [4] rxinitdone Receiver bit-init done. 0 Synchronous with
2205  *     pipeClk.
2206  * [3] txinitdone Transmitter-bit init done. 0 Synchronous with
2207  *     pipeClk.
2208  * [2] filteredrxlos Filtered loss of signal used 1 to generate
2209  *     p2lRxelectidle. Synchronous with pipeClk.
2210  * [1] rxdetectInt Receiver detected 0
2211  * [0] pipeMasterDoneOut Receiver detection valid 0
2212  *
2213  */
2214 typedef union {
2215 	uint32_t value;
2216 	struct {
2217 #if defined(_BIG_ENDIAN)
2218 		uint32_t	data:32;
2219 #else
2220 		uint32_t	data:32;
2221 #endif
2222 	} bits;
2223 } pipe_debug3_t;
2224 
2225 
2226 /*
2227  * Register: PcieEnhCapHdr
2228  * PCIE Enhanced Capability Header
2229  * Description: PCIE Enhanced Capability Header
2230  * Fields:
2231  *     Next Capability Offset (END, no more)
2232  *     Capability Version
2233  *     PCI Express Enhanced Capability ID (0x1 = Advanced Error
2234  *     Reporting)
2235  */
2236 typedef union {
2237 	uint32_t value;
2238 	struct {
2239 #if defined(_BIG_ENDIAN)
2240 		uint32_t	nxt_cap_offset:12;
2241 		uint32_t	cap_ver:4;
2242 		uint32_t	pcie_enh_cap_id:16;
2243 #else
2244 		uint32_t	pcie_enh_cap_id:16;
2245 		uint32_t	cap_ver:4;
2246 		uint32_t	nxt_cap_offset:12;
2247 #endif
2248 	} bits;
2249 } pcie_enh_cap_hdr_t;
2250 
2251 
2252 /*
2253  * Register: UncErrStat
2254  * Uncorrectable Error Status
2255  * Description: Uncorrectable Error Status
2256  * Fields:
2257  *     Unsupported Request Error
2258  *     ECRC Error
2259  *     Malformed TLP
2260  *     Reciever Overflow
2261  *     Unexpected Completion
2262  *     Completion Abort
2263  *     Completion Timeout
2264  *     Flow Control Protocol Error
2265  *     Poisoned TLP
2266  *     Introduced in PCIe 1.1 specification.
2267  *     Data Link Protocol Error
2268  */
2269 typedef union {
2270 	uint32_t value;
2271 	struct {
2272 #if defined(_BIG_ENDIAN)
2273 		uint32_t	rsrvd:11;
2274 		uint32_t	unsup_req_err:1;
2275 		uint32_t	ecrc_err:1;
2276 		uint32_t	bad_tlp:1;
2277 		uint32_t	rcv_ovfl:1;
2278 		uint32_t	unexp_cpl:1;
2279 		uint32_t	cpl_abrt:1;
2280 		uint32_t	cpl_tmout:1;
2281 		uint32_t	fc_err:1;
2282 		uint32_t	psn_tlp:1;
2283 		uint32_t	rsrvd1:6;
2284 		uint32_t	surprise_down_err:1;
2285 		uint32_t	dlp_err:1;
2286 		uint32_t	rsrvd2:4;
2287 #else
2288 		uint32_t	rsrvd2:4;
2289 		uint32_t	dlp_err:1;
2290 		uint32_t	surprise_down_err:1;
2291 		uint32_t	rsrvd1:6;
2292 		uint32_t	psn_tlp:1;
2293 		uint32_t	fc_err:1;
2294 		uint32_t	cpl_tmout:1;
2295 		uint32_t	cpl_abrt:1;
2296 		uint32_t	unexp_cpl:1;
2297 		uint32_t	rcv_ovfl:1;
2298 		uint32_t	bad_tlp:1;
2299 		uint32_t	ecrc_err:1;
2300 		uint32_t	unsup_req_err:1;
2301 		uint32_t	rsrvd:11;
2302 #endif
2303 	} bits;
2304 } unc_err_stat_t;
2305 
2306 
2307 /*
2308  * Register: UncErrMask
2309  * Uncorrectable Error Mask
2310  * Description: Uncorrectable Error Mask
2311  * Fields:
2312  *     Unsupported Request Error
2313  *     ECRC Error
2314  *     Malformed TLP
2315  *     Reciever Overflow
2316  *     Unexpected Completion
2317  *     Completion Abort
2318  *     Completion Timeout
2319  *     Flow Control Protocol Error
2320  *     Poisoned TLP
2321  *     Introduced in PCIe 1.1
2322  *     Data Link Protocol Error
2323  */
2324 typedef union {
2325 	uint32_t value;
2326 	struct {
2327 #if defined(_BIG_ENDIAN)
2328 		uint32_t	rsrvd:11;
2329 		uint32_t	unsup_req_err:1;
2330 		uint32_t	ecrc_err:1;
2331 		uint32_t	bad_tlp:1;
2332 		uint32_t	rcv_ovfl:1;
2333 		uint32_t	unexp_cpl:1;
2334 		uint32_t	cpl_abrt:1;
2335 		uint32_t	cpl_tmout:1;
2336 		uint32_t	fc_err:1;
2337 		uint32_t	psn_tlp:1;
2338 		uint32_t	rsrvd1:6;
2339 		uint32_t	surprise_down_err:1;
2340 		uint32_t	dlp_err:1;
2341 		uint32_t	rsrvd2:4;
2342 #else
2343 		uint32_t	rsrvd2:4;
2344 		uint32_t	dlp_err:1;
2345 		uint32_t	surprise_down_err:1;
2346 		uint32_t	rsrvd1:6;
2347 		uint32_t	psn_tlp:1;
2348 		uint32_t	fc_err:1;
2349 		uint32_t	cpl_tmout:1;
2350 		uint32_t	cpl_abrt:1;
2351 		uint32_t	unexp_cpl:1;
2352 		uint32_t	rcv_ovfl:1;
2353 		uint32_t	bad_tlp:1;
2354 		uint32_t	ecrc_err:1;
2355 		uint32_t	unsup_req_err:1;
2356 		uint32_t	rsrvd:11;
2357 #endif
2358 	} bits;
2359 } unc_err_mask_t;
2360 
2361 
2362 /*
2363  * Register: UncErrSvrty
2364  * Uncorrectable Error Severity
2365  * Description: Uncorrectable Error Severity
2366  * Fields:
2367  *     Unsupported Request Error
2368  *     ECRC Error
2369  *     Malformed TLP
2370  *     Reciever Overflow
2371  *     Unexpected Completion
2372  *     Completion Abort
2373  *     Completion Timeout
2374  *     Flow Control Protocol Error
2375  *     Poisoned TLP
2376  *     Introduced in PCIe 1.1 specification. Not supported; use PCIe
2377  *     default.
2378  *     Data Link Protocol Error
2379  */
2380 typedef union {
2381 	uint32_t value;
2382 	struct {
2383 #if defined(_BIG_ENDIAN)
2384 		uint32_t	rsrvd:11;
2385 		uint32_t	unsup_req_err:1;
2386 		uint32_t	ecrc_err:1;
2387 		uint32_t	bad_tlp:1;
2388 		uint32_t	rcv_ovfl:1;
2389 		uint32_t	unexp_cpl:1;
2390 		uint32_t	cpl_abrt:1;
2391 		uint32_t	cpl_tmout:1;
2392 		uint32_t	fc_err:1;
2393 		uint32_t	psn_tlp:1;
2394 		uint32_t	rsrvd1:6;
2395 		uint32_t	surprise_down_err:1;
2396 		uint32_t	dlp_err:1;
2397 		uint32_t	rsrvd2:4;
2398 #else
2399 		uint32_t	rsrvd2:4;
2400 		uint32_t	dlp_err:1;
2401 		uint32_t	surprise_down_err:1;
2402 		uint32_t	rsrvd1:6;
2403 		uint32_t	psn_tlp:1;
2404 		uint32_t	fc_err:1;
2405 		uint32_t	cpl_tmout:1;
2406 		uint32_t	cpl_abrt:1;
2407 		uint32_t	unexp_cpl:1;
2408 		uint32_t	rcv_ovfl:1;
2409 		uint32_t	bad_tlp:1;
2410 		uint32_t	ecrc_err:1;
2411 		uint32_t	unsup_req_err:1;
2412 		uint32_t	rsrvd:11;
2413 #endif
2414 	} bits;
2415 } unc_err_svrty_t;
2416 
2417 
2418 /*
2419  * Register: CorrErrStat
2420  * Correctable Error Status
2421  * Description: Correctable Error Status
2422  * Fields:
2423  *     Advisory Non-Fatal Error Introduced in PCIe 1.1 specification.
2424  *     Reply Timer Timeout
2425  *     Replay Number Rollover
2426  *     Bad DLLP
2427  *     Bad TLP
2428  *     Receive Error
2429  */
2430 typedef union {
2431 	uint32_t value;
2432 	struct {
2433 #if defined(_BIG_ENDIAN)
2434 		uint32_t	rsrvd:18;
2435 		uint32_t	adv_nf_err:1;
2436 		uint32_t	rply_tmr_tmout:1;
2437 		uint32_t	rsrvd1:3;
2438 		uint32_t	rply_rlovr:1;
2439 		uint32_t	bad_dllp:1;
2440 		uint32_t	bad_tlp:1;
2441 		uint32_t	rsrvd2:5;
2442 		uint32_t	rcv_err:1;
2443 #else
2444 		uint32_t	rcv_err:1;
2445 		uint32_t	rsrvd2:5;
2446 		uint32_t	bad_tlp:1;
2447 		uint32_t	bad_dllp:1;
2448 		uint32_t	rply_rlovr:1;
2449 		uint32_t	rsrvd1:3;
2450 		uint32_t	rply_tmr_tmout:1;
2451 		uint32_t	adv_nf_err:1;
2452 		uint32_t	rsrvd:18;
2453 #endif
2454 	} bits;
2455 } corr_err_stat_t;
2456 
2457 
2458 /*
2459  * Register: CorrErrMask
2460  * Correctable Error Mask
2461  * Description: Correctable Error Mask
2462  * Fields:
2463  *     Advisory Non Fatal Error Mask
2464  *     Reply Timer Timeout
2465  *     Replay Number Rollover
2466  *     Bad DLLP
2467  *     Bad TLP
2468  *     Receive Error
2469  */
2470 typedef union {
2471 	uint32_t value;
2472 	struct {
2473 #if defined(_BIG_ENDIAN)
2474 		uint32_t	rsrvd:18;
2475 		uint32_t	adv_nf_err_mask:1;
2476 		uint32_t	rply_tmr_tmout:1;
2477 		uint32_t	rsrvd1:3;
2478 		uint32_t	rply_rlovr:1;
2479 		uint32_t	bad_dllp:1;
2480 		uint32_t	bad_tlp:1;
2481 		uint32_t	rsrvd2:5;
2482 		uint32_t	rcv_err:1;
2483 #else
2484 		uint32_t	rcv_err:1;
2485 		uint32_t	rsrvd2:5;
2486 		uint32_t	bad_tlp:1;
2487 		uint32_t	bad_dllp:1;
2488 		uint32_t	rply_rlovr:1;
2489 		uint32_t	rsrvd1:3;
2490 		uint32_t	rply_tmr_tmout:1;
2491 		uint32_t	adv_nf_err_mask:1;
2492 		uint32_t	rsrvd:18;
2493 #endif
2494 	} bits;
2495 } corr_err_mask_t;
2496 
2497 
2498 /*
2499  * Register: AdvCapCtrl
2500  * Advanced Capability and Control
2501  * Description: Advanced Capability and Control
2502  * Fields:
2503  *     ECRC Check Enable
2504  *     ECRC Check Capable
2505  *     ECRC Generation Enable
2506  *     ECRC Generation Capability
2507  *     First Error Pointer
2508  */
2509 typedef union {
2510 	uint32_t value;
2511 	struct {
2512 #if defined(_BIG_ENDIAN)
2513 		uint32_t	rsrvd:23;
2514 		uint32_t	ecrc_chk_en:1;
2515 		uint32_t	ecrc_chk_cap:1;
2516 		uint32_t	ecrc_gen_en:1;
2517 		uint32_t	ecrc_gen_cap:1;
2518 		uint32_t	st_err_ptr:5;
2519 #else
2520 		uint32_t	st_err_ptr:5;
2521 		uint32_t	ecrc_gen_cap:1;
2522 		uint32_t	ecrc_gen_en:1;
2523 		uint32_t	ecrc_chk_cap:1;
2524 		uint32_t	ecrc_chk_en:1;
2525 		uint32_t	rsrvd:23;
2526 #endif
2527 	} bits;
2528 } adv_cap_ctrl_t;
2529 
2530 
2531 /*
2532  * Register: HdrLog0
2533  * Header Log0
2534  * Description: Header Log0
2535  * Fields:
2536  *     First DW of TLP header with error
2537  */
2538 typedef union {
2539 	uint32_t value;
2540 	struct {
2541 #if defined(_BIG_ENDIAN)
2542 		uint32_t	data:32;
2543 #else
2544 		uint32_t	data:32;
2545 #endif
2546 	} bits;
2547 } hdr_log0_t;
2548 
2549 
2550 /*
2551  * Register: HdrLog1
2552  * Header Log1
2553  * Description: Header Log1
2554  * Fields:
2555  *     Second DW of TLP header with error
2556  */
2557 typedef union {
2558 	uint32_t value;
2559 	struct {
2560 #if defined(_BIG_ENDIAN)
2561 		uint32_t	data:32;
2562 #else
2563 		uint32_t	data:32;
2564 #endif
2565 	} bits;
2566 } hdr_log1_t;
2567 
2568 
2569 /*
2570  * Register: HdrLog2
2571  * Header Log2
2572  * Description: Header Log2
2573  * Fields:
2574  *     Third DW of TLP header with error
2575  */
2576 typedef union {
2577 	uint32_t value;
2578 	struct {
2579 #if defined(_BIG_ENDIAN)
2580 		uint32_t	data:32;
2581 #else
2582 		uint32_t	data:32;
2583 #endif
2584 	} bits;
2585 } hdr_log2_t;
2586 
2587 
2588 /*
2589  * Register: HdrLog3
2590  * Header Log3
2591  * Description: Header Log3
2592  * Fields:
2593  *     Fourth DW of TLP header with error
2594  */
2595 typedef union {
2596 	uint32_t value;
2597 	struct {
2598 #if defined(_BIG_ENDIAN)
2599 		uint32_t	data:32;
2600 #else
2601 		uint32_t	data:32;
2602 #endif
2603 	} bits;
2604 } hdr_log3_t;
2605 
2606 
2607 /*
2608  * Register: PipeRxTxControl
2609  * Pipe Rx/Tx Control
2610  *     00 : ewrap : Enable wrapback test mode 01 : padLoopback :
2611  *     Enable Pad Serial Loopback test mode 10 : revLoopback : Enable
2612  *     Reverse Loopback test mode 11 : efifoLoopback : Enable PCI
2613  *     Express Slave loop back
2614  *     100 : Clock generator test x10 : Vil/Vih test x01 : Vih/Vil
2615  *     test x11 : No-error test. A full test of the transceiver 111 :
2616  *     Forced-error test. A full test of the transceiver with forced
2617  *     errors
2618  *     1 : selects 20-bit mode 0 : selects 10-bit mode
2619  *     1 : selects Tx 20-bit fifo mode
2620  *     00 : 52 us (470 cycles) 01 : 53 us (720 cycles) 10 : 54 us
2621  *     (970 cycles) 11 : 55 us (1220 cycles)
2622  *     1 : selects 20-bit mode 0 : selects 10-bit mode
2623  *     1 : Enable receiver reference clocks
2624  */
2625 typedef union {
2626 	uint32_t value;
2627 	struct {
2628 #if defined(_BIG_ENDIAN)
2629 		uint32_t	rsrvd:1;
2630 		uint32_t	loopback:1;
2631 		uint32_t	loopback_mode_sel:2;
2632 		uint32_t	rsrvd1:1;
2633 		uint32_t	en_bist:3;
2634 		uint32_t	tdws20:1;
2635 		uint32_t	tdenfifo:1;
2636 		uint32_t	rxpreswin:2;
2637 		uint32_t	rdws20:1;
2638 		uint32_t	enstretch:1;
2639 		uint32_t	rsrvd2:18;
2640 #else
2641 		uint32_t	rsrvd2:18;
2642 		uint32_t	enstretch:1;
2643 		uint32_t	rdws20:1;
2644 		uint32_t	rxpreswin:2;
2645 		uint32_t	tdenfifo:1;
2646 		uint32_t	tdws20:1;
2647 		uint32_t	en_bist:3;
2648 		uint32_t	rsrvd1:1;
2649 		uint32_t	loopback_mode_sel:2;
2650 		uint32_t	loopback:1;
2651 		uint32_t	rsrvd:1;
2652 #endif
2653 	} bits;
2654 } pipe_rx_tx_control_t;
2655 
2656 
2657 /*
2658  * Register: PipeRxTxStatus
2659  * Pipe Rx/Tx Status
2660  */
2661 typedef union {
2662 	uint32_t value;
2663 	struct {
2664 #if defined(_BIG_ENDIAN)
2665 		uint32_t	rsrvd:32;
2666 #else
2667 		uint32_t	rsrvd:32;
2668 #endif
2669 	} bits;
2670 } pipe_rx_tx_status_t;
2671 
2672 
2673 /*
2674  * Register: PipeRxTxPwrCntl
2675  * Pipe Rx/Tx Power Control
2676  *     1 : power down termination trimming circuit 0 : normal
2677  *     operation
2678  *     Power down PECL Clock buffer 1 : when a bit is 1, power down
2679  *     associated clock buffer cell 0 : normal operation
2680  *     Power down Transmit PLL 1 : when a bit is 1, power down
2681  *     associated Tx PLL circuit 0 : normal operation
2682  *     Power down Differential O/P Clock buffer 1 : when a bit is 1,
2683  *     power down associated differntial clock buffer that drives
2684  *     gbtClkoutN/p 0 : normal operation
2685  *     Power down Transmitter Analog section 1 : when a bit is 1,
2686  *     power down analog section of the associated Transmitter and
2687  *     the Tx buffer 0 : normal operation
2688  *     Power down RxLOS 1 : when a bit is 1, it powers down the Rx
2689  *     LOS circuitry for the associated serdes lanes 0 : normal
2690  *     operation
2691  *     Power down Receiver Analog section 1 : when a bit is 1, power
2692  *     down analog section of the associated Receiver and the Tx
2693  *     buffer 0 : normal operation
2694  */
2695 typedef union {
2696 	uint32_t value;
2697 	struct {
2698 #if defined(_BIG_ENDIAN)
2699 		uint32_t	rsrvd:1;
2700 		uint32_t	pdrtrim:1;
2701 		uint32_t	pdownpecl:2;
2702 		uint32_t	pdownpll:2;
2703 		uint32_t	pdclkout:2;
2704 		uint32_t	pdownt:8;
2705 		uint32_t	pdrxlos:8;
2706 		uint32_t	pdownr:8;
2707 #else
2708 		uint32_t	pdownr:8;
2709 		uint32_t	pdrxlos:8;
2710 		uint32_t	pdownt:8;
2711 		uint32_t	pdclkout:2;
2712 		uint32_t	pdownpll:2;
2713 		uint32_t	pdownpecl:2;
2714 		uint32_t	pdrtrim:1;
2715 		uint32_t	rsrvd:1;
2716 #endif
2717 	} bits;
2718 } pipe_rx_tx_pwr_cntl_t;
2719 
2720 
2721 /*
2722  * Register: PipeRxTxParam
2723  * Pipe Rx/Tx Parameter
2724  *     Tx Driver Emphasis
2725  *     Serial output Slew Rate Control
2726  *     Tx Voltage Mux control
2727  *     Tx Voltage Pulse control
2728  *     Output Swing setting
2729  *     Transmitter Clock generator pole adjust
2730  *     Transmitter Clock generator zero adjust
2731  *     Receiver Clock generator pole adjust
2732  *     Receiver Clock generator zero adjust
2733  *     Bias Control for factory testing and debugging
2734  *     Receiver LOS Threshold adjustment. This value is determined by
2735  *     LSI.
2736  *     Receiver Input Equalizer control
2737  */
2738 typedef union {
2739 	uint32_t value;
2740 	struct {
2741 #if defined(_BIG_ENDIAN)
2742 		uint32_t	rsrvd:1;
2743 		uint32_t	emph:3;
2744 		uint32_t	rsrvd1:1;
2745 		uint32_t	risefall:3;
2746 		uint32_t	vmuxlo:2;
2747 		uint32_t	vpulselo:2;
2748 		uint32_t	vtxlo:4;
2749 		uint32_t	tp:2;
2750 		uint32_t	tz:2;
2751 		uint32_t	rp:2;
2752 		uint32_t	rz:2;
2753 		uint32_t	biascntl:1;
2754 		uint32_t	losadj:3;
2755 		uint32_t	rxeq:4;
2756 #else
2757 		uint32_t	rxeq:4;
2758 		uint32_t	losadj:3;
2759 		uint32_t	biascntl:1;
2760 		uint32_t	rz:2;
2761 		uint32_t	rp:2;
2762 		uint32_t	tz:2;
2763 		uint32_t	tp:2;
2764 		uint32_t	vtxlo:4;
2765 		uint32_t	vpulselo:2;
2766 		uint32_t	vmuxlo:2;
2767 		uint32_t	risefall:3;
2768 		uint32_t	rsrvd1:1;
2769 		uint32_t	emph:3;
2770 		uint32_t	rsrvd:1;
2771 #endif
2772 	} bits;
2773 } pipe_rx_tx_param_t;
2774 
2775 
2776 /*
2777  * Register: PipeRxTxClock
2778  * Pipe Rx/Tx Clock
2779  *     Reverse Loopback clock select 00 : gbtRbcAO 01 : gbtRbcBO 10 :
2780  *     gbtRbcCO 11 : gbtRbcDO
2781  *     Select Master Clock 100 : All lanes 000 : Lane A 001 : Lane B
2782  *     010 : Lane C 011 : Lane D
2783  *     Transmit PLL Divider control
2784  *     Transmit Data rate control
2785  *     Receiver PLL Frequency control
2786  *     Bit rate control to enable bit doubling feature
2787  *     Reset Transmitter lane
2788  *     Reset Receiver lane
2789  */
2790 typedef union {
2791 	uint32_t value;
2792 	struct {
2793 #if defined(_BIG_ENDIAN)
2794 		uint32_t	rsrvd:2;
2795 		uint32_t	revlbrefsel:2;
2796 		uint32_t	rsrvd1:1;
2797 		uint32_t	tdmaster:3;
2798 		uint32_t	fbdivt:3;
2799 		uint32_t	half_ratet:1;
2800 		uint32_t	fbdivr:3;
2801 		uint32_t	half_rater:1;
2802 		uint32_t	txreset:8;
2803 		uint32_t	rxreset:8;
2804 #else
2805 		uint32_t	rxreset:8;
2806 		uint32_t	txreset:8;
2807 		uint32_t	half_rater:1;
2808 		uint32_t	fbdivr:3;
2809 		uint32_t	half_ratet:1;
2810 		uint32_t	fbdivt:3;
2811 		uint32_t	tdmaster:3;
2812 		uint32_t	rsrvd1:1;
2813 		uint32_t	revlbrefsel:2;
2814 		uint32_t	rsrvd:2;
2815 #endif
2816 	} bits;
2817 } pipe_rx_tx_clock_t;
2818 
2819 
2820 /*
2821  * Register: PipeGlueCntl0
2822  * Pipe Glue Control 0
2823  *     Lock to Bitstream Initialization Time
2824  *     RXLOS Test bit
2825  *     Electrical Idle Ordered set enable
2826  *     Enable RxLOS
2827  *     Enable Fast resync
2828  *     RxLOS Sample Interval
2829  *     RxLOS threshold
2830  */
2831 typedef union {
2832 	uint32_t value;
2833 	struct {
2834 #if defined(_BIG_ENDIAN)
2835 		uint32_t	bitlocktime:16;
2836 		uint32_t	rxlos_test:1;
2837 		uint32_t	eiosenable:1;
2838 		uint32_t	rxlosenable:1;
2839 		uint32_t	fastresync:1;
2840 		uint32_t	samplerate:4;
2841 		uint32_t	thresholdcount:8;
2842 #else
2843 		uint32_t	thresholdcount:8;
2844 		uint32_t	samplerate:4;
2845 		uint32_t	fastresync:1;
2846 		uint32_t	rxlosenable:1;
2847 		uint32_t	eiosenable:1;
2848 		uint32_t	rxlos_test:1;
2849 		uint32_t	bitlocktime:16;
2850 #endif
2851 	} bits;
2852 } pipe_glue_cntl0_t;
2853 
2854 
2855 /*
2856  * Register: PipeGlueCntl1
2857  * Pipe Glue Control 1
2858  *     Receiver Trim Resistance Configuration
2859  *     Transmitter Trim Resistance Configuration
2860  *     Auto Trim Enable
2861  *     50 Ohm Termination Enable
2862  *     Customer select for reference clock frequency
2863  *     EFIFO Same clock select
2864  *     EFIFO start depth
2865  *     Lock to refclk initialization time
2866  */
2867 typedef union {
2868 	uint32_t value;
2869 	struct {
2870 #if defined(_BIG_ENDIAN)
2871 		uint32_t	termrcfg:2;
2872 		uint32_t	termtcfg:2;
2873 		uint32_t	rtrimen:1;
2874 		uint32_t	ref50:1;
2875 		uint32_t	freq_sel:1;
2876 		uint32_t	same_sel:1;
2877 		uint32_t	rsrvd:1;
2878 		uint32_t	start_efifo:3;
2879 		uint32_t	rsrvd1:2;
2880 		uint32_t	inittime:18;
2881 #else
2882 		uint32_t	inittime:18;
2883 		uint32_t	rsrvd1:2;
2884 		uint32_t	start_efifo:3;
2885 		uint32_t	rsrvd:1;
2886 		uint32_t	same_sel:1;
2887 		uint32_t	freq_sel:1;
2888 		uint32_t	ref50:1;
2889 		uint32_t	rtrimen:1;
2890 		uint32_t	termtcfg:2;
2891 		uint32_t	termrcfg:2;
2892 #endif
2893 	} bits;
2894 } pipe_glue_cntl1_t;
2895 
2896 
2897 /*
2898  * Register: HcrReg
2899  * HCR Registers
2900  * Description: Hydra Specific Configuration Registers for use by
2901  * software. These registers are loaded with the SPROM contents at
2902  * power on. A maximum of 128 DWords has been assigned for s/w to
2903  * use. This space generally stores the following informations : MAC
2904  * Address Number of MAC addresses MAC Phy Type Other data fields are
2905  * upto the software to use.
2906  *
2907  * Fields:
2908  *     Hydra specific configuration controlled by software
2909  */
2910 typedef union {
2911 	uint32_t value;
2912 	struct {
2913 #if defined(_BIG_ENDIAN)
2914 		uint32_t	hcr_val:32;
2915 #else
2916 		uint32_t	hcr_val:32;
2917 #endif
2918 	} bits;
2919 } hcr_reg_t;
2920 
2921 
2922 /*
2923  * Register: BlockReset
2924  * Block Reset
2925  * Description: Soft resets to modules. Blade domain modules are
2926  * reset by setting the corresponding block reset to 1. Shared domain
2927  * resets are sent to SPI for processing and corresponding action by
2928  * SPI. Shared domains are reset only if all the blades have
2929  * requested a reset for that block. Below is an example scenario :
2930  * s/w initiates the reset by writing '1' to the dpmRst bit dpmRst
2931  * bit remains '1' until dpmRstStat is detected to be 1. Once
2932  * dpmRstStat is detected to be 1, even if s/w writes 1 to this bit
2933  * again no new reset will be initiated to the shared domain, ie,
2934  * DPM. dpmRstStat is driven by external i/f (shared domain status
2935  * provided by SPI) dpmRstStat bit will show '1' as long as the input
2936  * stays at 1 or until s/w reads the status and is cleared only after
2937  * s/w reads it and if dpmRstStat is 0 by then.
2938  * If Host wants to reset entire Hydra it should do so through the
2939  * mailbox. In this case, the message interprettation is upto the
2940  * software. Writing a '1' to any of these bits generates a single
2941  * pulse to the SP module which then controls the reset of the
2942  * respective block.
2943  *
2944  * Fields:
2945  *     1 : indicates that an active reset has been applied to the SP
2946  *     based on the request from all of the blades. Clears on Read
2947  *     provided the reset to SP has been deasserted by then by SPI.
2948  *     Setting to 1 allows this blade to request Service Processor
2949  *     (Shared) reset. However, SP reset can only occur if all blades
2950  *     agree. The success of reset request is indicated by spRstStat
2951  *     = 1 which is wired-AND of request from all the blades. Current
2952  *     request can be removed by writing a '0' to this bit. This bit
2953  *     clears automatically on detecting spRstStat = 1.
2954  *     Enable blade to service processor (Shared) reset voter
2955  *     registration = 1, disabled = 0
2956  *     Issue power reset to the EP Core Clears to 0, writing 0 has no
2957  *     effect.
2958  *     Issue core reset to the EP Core Clears to 0, writing 0 has no
2959  *     effect.
2960  *     Issue system reset (sysPor) to the PIPE Core This issues reset
2961  *     to the EP core, PCIe domains of Tdc, Rdc, and CIP. This shuts
2962  *     down the PCIe clock until Pipe core comes out of reset. The
2963  *     status of the Pipe core can be read by reading out the
2964  *     cipLinkStat register's pipe core status and pcie reset status
2965  *     bits. Clears to 0, writing 0 has no effect.
2966  *     1 : indicates that an active reset has been applied to the
2967  *     NMAC based on the request from all of the blades. Clears on
2968  *     Read provided the reset to NMAC has been deasserted by then by
2969  *     SPI.
2970  *     1 : indicates that an active reset has been applied to the TDP
2971  *     based on the request from all of the blades. Clears on Read
2972  *     provided the reset to TDP has been deasserted by then by SPI.
2973  *     1 : indicates that an active reset has been applied to the DPM
2974  *     based on the request from all of the blades. Clears on Read
2975  *     provided the reset to DPM has been deasserted by then by SPI.
2976  *     This bit is effective only if sharedVoterEn (bit 24 of this
2977  *     reg) has been enabled. Writing '1' sends a request to SP to
2978  *     reset NMAC if sharedVoterEn=1. Intended for backdoor access.
2979  *     The success of reset request is indicated by nmacRstStat = 1
2980  *     which is wired-AND of request from all the blades. This also
2981  *     means that the reset request is successful only if all the
2982  *     blades requested for reset of this block. Current request can
2983  *     be removed by writing a '0' to this bit. This bit clears
2984  *     automatically on detecting nmacRstStat = 1.
2985  *     This bit is effective only if sharedVoterEn (bit 24 of this
2986  *     reg) has been enabled. Writing '1' sends a request to SP to
2987  *     reset TDP if sharedVoterEn=1. Intended for backdoor access.
2988  *     Intended for backdoor access. The success of reset request is
2989  *     indicated by tdpRstStat = 1 which is wired-AND of request from
2990  *     all the blades. This also means that the reset request is
2991  *     successful only if all the blades requested for reset of this
2992  *     block. Current request can be removed by writing a '0' to this
2993  *     bit. This bit clears automatically on detecting tdpRstStat =
2994  *     1.
2995  *     This bit is effective only if sharedVoterEn (bit 24 of this
2996  *     reg) has been enabled. Writing '1' sends a request to SP to
2997  *     reset DPM if sharedVoterEn=1. Intended for backdoor access.
2998  *     Intended for backdoor access. The success of reset request is
2999  *     indicated by dpmRstStat = 1 which is wired-AND of request from
3000  *     all the blades. This also means that the reset request is
3001  *     successful only if all the blades requested for reset of this
3002  *     block. Current request can be removed by writing a '0' to this
3003  *     bit. This bit clears automatically on detecting dpmRstStat =
3004  *     1.
3005  *     Setting to 1 generates tdcCoreReset and tdcPcieReset to the
3006  *     TDC block. The reset will stay asserted for atleast 4 clock
3007  *     cycles. Clears to 0, writing 0 has no effect.
3008  *     Setting to 1 generates rdcCoreReset and rdcPcieReset to the
3009  *     RDC block. The reset will stay asserted for atleast 4 clock
3010  *     cycles. Clears to 0, writing 0 has no effect.
3011  *     Setting to 1 generates reset to the PFC block. The reset will
3012  *     stay asserted for atleast 4 clock cycles. Clears to 0, writing
3013  *     0 has no effect.
3014  *     Setting to 1 generates reset to the VMAC block. The reset will
3015  *     stay asserted for atleast 4 clock cycles. Clears to 0, writing
3016  *     0 has no effect.
3017  */
3018 typedef union {
3019 	uint32_t value;
3020 	struct {
3021 #if defined(_BIG_ENDIAN)
3022 		uint32_t	rsrvd:13;
3023 		uint32_t	sp_rst_stat:1;
3024 		uint32_t	sp_rst:1;
3025 		uint32_t	shared_voter_en:1;
3026 		uint32_t	epcore_pwr_rst:1;
3027 		uint32_t	epcore_core_rst:1;
3028 		uint32_t	pipe_sys_rst:1;
3029 		uint32_t	nmac_rst_stat:1;
3030 		uint32_t	tdp_rst_stat:1;
3031 		uint32_t	dpm_rst_stat:1;
3032 		uint32_t	rsrvd1:1;
3033 		uint32_t	nmac_rst:1;
3034 		uint32_t	tdp_rst:1;
3035 		uint32_t	dpm_rst:1;
3036 		uint32_t	rsrvd2:1;
3037 		uint32_t	tdc_rst:1;
3038 		uint32_t	rdc_rst:1;
3039 		uint32_t	pfc_rst:1;
3040 		uint32_t	vmac_rst:1;
3041 		uint32_t	rsrvd3:1;
3042 #else
3043 		uint32_t	rsrvd3:1;
3044 		uint32_t	vmac_rst:1;
3045 		uint32_t	pfc_rst:1;
3046 		uint32_t	rdc_rst:1;
3047 		uint32_t	tdc_rst:1;
3048 		uint32_t	rsrvd2:1;
3049 		uint32_t	dpm_rst:1;
3050 		uint32_t	tdp_rst:1;
3051 		uint32_t	nmac_rst:1;
3052 		uint32_t	rsrvd1:1;
3053 		uint32_t	dpm_rst_stat:1;
3054 		uint32_t	tdp_rst_stat:1;
3055 		uint32_t	nmac_rst_stat:1;
3056 		uint32_t	pipe_sys_rst:1;
3057 		uint32_t	epcore_core_rst:1;
3058 		uint32_t	epcore_pwr_rst:1;
3059 		uint32_t	shared_voter_en:1;
3060 		uint32_t	sp_rst:1;
3061 		uint32_t	sp_rst_stat:1;
3062 		uint32_t	rsrvd:13;
3063 #endif
3064 	} bits;
3065 } block_reset_t;
3066 
3067 
3068 /*
3069  * Register: TimeoutCfg
3070  * PIO Timeout Configuration
3071  * Description: PIO Timeout Configuration register to control wait
3072  * time for a PIO access to complete. The timer resolution is in 250
3073  * MHz clock.
3074  * Fields:
3075  *     Programmable timeout counter value for PIO clients who did not
3076  *     ack a transaction in time. Minimum value should be 64.
3077  *     Timeout enable for PIO access to clients. 1 = enable.
3078  */
3079 typedef union {
3080 	uint32_t value;
3081 	struct {
3082 #if defined(_BIG_ENDIAN)
3083 		uint32_t	rsrvd:21;
3084 		uint32_t	tmout_cnt:10;
3085 		uint32_t	tmout_en:1;
3086 #else
3087 		uint32_t	tmout_en:1;
3088 		uint32_t	tmout_cnt:10;
3089 		uint32_t	rsrvd:21;
3090 #endif
3091 	} bits;
3092 } timeout_cfg_t;
3093 
3094 
3095 /*
3096  * Register: HeartCfg
3097  * PIO Heartbeat Config
3098  * Description: PIO Blade presence indication : Heartbeat
3099  * configuration The timer resolution is in 250 MHz clock.
3100  * Fields:
3101  *     Heartbeat countdown 250Mhz clock divider which serves as
3102  *     resolution for the heartTimer.
3103  *     Heartbeat countdown enable
3104  */
3105 typedef union {
3106 	uint32_t value;
3107 	struct {
3108 #if defined(_BIG_ENDIAN)
3109 		uint32_t	divider:28;
3110 		uint32_t	rsrvd:3;
3111 		uint32_t	en:1;
3112 #else
3113 		uint32_t	en:1;
3114 		uint32_t	rsrvd:3;
3115 		uint32_t	divider:28;
3116 #endif
3117 	} bits;
3118 } heart_cfg_t;
3119 
3120 
3121 /*
3122  * Register: HeartTimer
3123  * PIO Heartbeat Timer
3124  * Description: PIO Blade presence indication : Heartbeat timer The
3125  * timer resolution is in 250 MHz clock.
3126  * Fields:
3127  *     Number of heartCfg.divider ticks of the 250Mhz clock before
3128  *     blade presence expires. This register decrements for every
3129  *     heartCfg.divider number of 250MHz clock cycles. It expires to
3130  *     0 and so must be written periodically to reset the timer back
3131  *     to the required value. This counter does not have any effect
3132  *     on CIP functionality.
3133  */
3134 typedef union {
3135 	uint32_t value;
3136 	struct {
3137 #if defined(_BIG_ENDIAN)
3138 		uint32_t	timer:32;
3139 #else
3140 		uint32_t	timer:32;
3141 #endif
3142 	} bits;
3143 } heart_timer_t;
3144 
3145 
3146 /*
3147  * Register: CipGpCtrl
3148  * CIP General Purpose Control Register
3149  */
3150 typedef union {
3151 	uint32_t value;
3152 	struct {
3153 #if defined(_BIG_ENDIAN)
3154 		uint32_t	rsrvd:30;
3155 		uint32_t	dma_override_relaxord:1;
3156 		uint32_t	dma_override_nosnoop:1;
3157 #else
3158 		uint32_t	dma_override_nosnoop:1;
3159 		uint32_t	dma_override_relaxord:1;
3160 		uint32_t	rsrvd:30;
3161 #endif
3162 	} bits;
3163 } cip_gp_ctrl_t;
3164 
3165 
3166 /*
3167  * Register: CipStatus
3168  * CIP Status
3169  * Description: This register returns CIP block's current logic
3170  * status
3171  * Fields:
3172  *     Current state of the cipEpc state machine 00 : epIdle ( wait
3173  *     for EEPROM request from SP or Host ) 01 : waitAck0 ( wait for
3174  *     ack from EEPROM for the first 16 bit read of the DW access )
3175  *     11 : waitAck1 ( wait for ack from EEPROM for the second 16 bit
3176  *     read of the DW access ) 10 : UNDEFINED ( Undefined/Unused
3177  *     state; EPC is never expected to be in this state )
3178  *     Current state of the cipSpc state machine 000 : spReset ( wait
3179  *     for Power-On SPROM download to start) 001 : getAddr ( Get
3180  *     CfgReg Address ) 010 : getData ( Get CfgReg Data ) 011 :
3181  *     ignoreData ( Address phase had an error, so ignore the Data
3182  *     coming in ) 100 : idleCyc ( Idle cycle following an AHB
3183  *     Address phase ) 101 : waitAck0 ( Wait for ack from EP Core
3184  *     during SPROM Download ) 110 : waitAck1 ( Wait for ack from EP
3185  *     Core during register read/write ) 111 : NORMAL ( SPROM
3186  *     Download/Register read/write access completed and wait for
3187  *     SP/Host initiated PCI/AHB/HCR read/write )
3188  *     PCI Bus Number as reported by EP core
3189  *     PCI Bus Device Number as reported by EP core
3190  *     1: current csr access in progress is Local CIP csr access
3191  *     1: current csr access in progress is Blade Domain csr access
3192  *     1: a 64 bit blade domain access is in progress as two 32 bit
3193  *     accesses
3194  *     1: indicates config values were downloaded from SPROM
3195  *     1: indicates non-zero number of HCR config values downloaded
3196  *     from SPROM
3197  *     1: indicates non-zero number of PCI config values downloaded
3198  *     from SPROM
3199  *     1: indicates non-zero number of Pipe config values downloaded
3200  *     from SPROM
3201  */
3202 typedef union {
3203 	uint32_t value;
3204 	struct {
3205 #if defined(_BIG_ENDIAN)
3206 		uint32_t	rsrvd:7;
3207 		uint32_t	cip_epc_sm:2;
3208 		uint32_t	cip_spc_sm:3;
3209 		uint32_t	pbus_num:8;
3210 		uint32_t	pbus_dev_num:5;
3211 		uint32_t	loc_csr_access:1;
3212 		uint32_t	bd_csr_access:1;
3213 		uint32_t	d64_in_progress:1;
3214 		uint32_t	spc_dnld_done:1;
3215 		uint32_t	hcr_nz_cfg:1;
3216 		uint32_t	pci_nz_cfg:1;
3217 		uint32_t	pipe_nz_cfg:1;
3218 #else
3219 		uint32_t	pipe_nz_cfg:1;
3220 		uint32_t	pci_nz_cfg:1;
3221 		uint32_t	hcr_nz_cfg:1;
3222 		uint32_t	spc_dnld_done:1;
3223 		uint32_t	d64_in_progress:1;
3224 		uint32_t	bd_csr_access:1;
3225 		uint32_t	loc_csr_access:1;
3226 		uint32_t	pbus_dev_num:5;
3227 		uint32_t	pbus_num:8;
3228 		uint32_t	cip_spc_sm:3;
3229 		uint32_t	cip_epc_sm:2;
3230 		uint32_t	rsrvd:7;
3231 #endif
3232 	} bits;
3233 } cip_status_t;
3234 
3235 
3236 /*
3237  * Register: CipLinkStat
3238  * Link Status Register
3239  * Description: This register returns the Link status
3240  * Fields:
3241  *     NMAC XPCS-2 Link Status
3242  *     NMAC XPCS-1 Link Status
3243  *     NMAC XPCS-0 Link Status
3244  *     '1' indicates that pipe core went down suddenly when its reset
3245  *     sources are at deactivated level. When this happens, the PCIe
3246  *     domain logics are reset including the EP core, TDC/RDC PCIe
3247  *     domains. All these logics, EP Core, and the pipe core are held
3248  *     at reset until s/w writes 1 to this bit to clear status which
3249  *     will also bring the PCIe domain out of reset
3250  *     pipe core clock & reset status 1: core is up & running, ie,
3251  *     PIPE core is out of reset and clock is ON
3252  *     PCIe domain reset status 1: PCIe domain logics including EP
3253  *     core are out of reset; This also implies that PCIe clock is up
3254  *     and running
3255  *     EP Core XDM Link State
3256  *     EP Core RDM Link State
3257  *     EP Core LTSSM State
3258  */
3259 typedef union {
3260 	uint32_t value;
3261 	struct {
3262 #if defined(_BIG_ENDIAN)
3263 		uint32_t	rsrvd:13;
3264 		uint32_t	xpcs2_link_up:1;
3265 		uint32_t	xpcs1_link_up:1;
3266 		uint32_t	xpcs0_link_up:1;
3267 		uint32_t	rsrvd1:6;
3268 		uint32_t	surprise_pipedn:1;
3269 		uint32_t	pipe_core_stable:1;
3270 		uint32_t	pcie_domain_stable:1;
3271 		uint32_t	xmlh_link_up:1;
3272 		uint32_t	rdlh_link_up:1;
3273 		uint32_t	xmlh_ltssm_state:5;
3274 #else
3275 		uint32_t	xmlh_ltssm_state:5;
3276 		uint32_t	rdlh_link_up:1;
3277 		uint32_t	xmlh_link_up:1;
3278 		uint32_t	pcie_domain_stable:1;
3279 		uint32_t	pipe_core_stable:1;
3280 		uint32_t	surprise_pipedn:1;
3281 		uint32_t	rsrvd1:6;
3282 		uint32_t	xpcs0_link_up:1;
3283 		uint32_t	xpcs1_link_up:1;
3284 		uint32_t	xpcs2_link_up:1;
3285 		uint32_t	rsrvd:13;
3286 #endif
3287 	} bits;
3288 } cip_link_stat_t;
3289 
3290 
3291 /*
3292  * Register: EpcStat
3293  * EEPROM PIO Status
3294  * Description: EEPROM PIO Status The Host may initiate access to the
3295  * EEPROM either thru this register or directly by TRGT1 interfaces
3296  * using ROM BAR access. Note that since the EEPROM can be accessed
3297  * by either Host or SP, access must be granted to the PEU using the
3298  * SPI PROM Control Register eepromPeuEn bit for proper operation.
3299  * All EEPROM accesses initiated from either the Host or SP are
3300  * always acknowledged. If a Host access is not acknowledged, then
3301  * check the SPI PROM Control Register eepromPeuEn bit to make sure
3302  * the PEU to EEPROM access has been enabled. Meanwhile, Host read
3303  * and write accesses through the TRGT1 interface may be held up
3304  * waiting for the acknowledgement. Thus, in order to recover from
3305  * any faulty/stuck condition due to the blocked EEPROM accesses, the
3306  * SP should configure the epcGotoNormal bit in the epcStat register.
3307  * When Host accesses are stuck, only the SP can write into this bit
3308  * to recover from this condition.
3309  * The EEPROM is 1M x 16 bits or 2M bytes. The read address in bits
3310  * [22:2] is byte address. The EEPROM access can only be DW access.
3311  * While accessing through these registers, the lower 2 bits of the
3312  * specified address is ignored resulting in a DW access to the
3313  * EEPROM controller. While accessing through the ROM BAR range, only
3314  * DW accesses are accepted and all other accesses will result in
3315  * error status returned to the host.
3316  * The read will initiate two reads to the EPC and the accumulated
3317  * 32 bit data is returned to the Host either via the Client2 bus or
3318  * in the epcData register depending on the cause of the transaction.
3319  * This means, a read addr=0,1,2,3 will return data from EPC
3320  * locations 0 & 1 which are 16 bits each, and a read to addr=4,5,6,7
3321  * will return data from EPC locations 2,3 which are 16 bits each.
3322  * Some examples for the address translation : 1) when Host gives
3323  * address 0x0000, it means to get bytes 0,1,2, and 3 from the
3324  * EEPROM. These bytes are stored at locations 0x0000 (bytes 0,1) and
3325  * 0x0001 (bytes 2,3) in EEPROM. Hence PEU will present address
3326  * 0x0000 followed by 0x0001 to the EEPROM.
3327  * 2) when Host gives address 0x0004, it means to get bytes 4,5,6,
3328  * and 7 from the EEPROM. These bytes are stored at locations 0x0002
3329  * (bytes 4,5) and 0x0003 (bytes 6,7) in EEPROM. Hence PEU will
3330  * present address 0x0002 followed by 0x0003 to the EEPROM.
3331  * etc ..
3332  *
3333  * Fields:
3334  *     Force the EPC state machine to go to epIdle state. This bit is
3335  *     used to force the EPC to skip the reading of the EEPROM and
3336  *     goto the epIdle state which is normal state for EPC. The bit
3337  *     is auto-cleared after switching to the epIdle state. Both SP
3338  *     and HOST can write into this bit. However care must be taken
3339  *     writing '1' into this bit since setting this bit will flush
3340  *     out any pending EEPROM access request from Host. Hence, this
3341  *     bit should be used only if the EPC State machine (cipEpcSm
3342  *     bits in cipStatus register) is stuck at a non-zero state.
3343  *     EEPROM Byte Address for read operation This field can be
3344  *     updated only if there is no pending EEPROM read access.
3345  *     Software should poll bit 0 of this register (epcRdInit) to
3346  *     make sure that it is '0' before writing into this. If polled
3347  *     epcRdInit value is '1', then write to epcAddr field is
3348  *     ignored. This is to safe-guard the epcAddr value which is
3349  *     being read out the EEPROM.
3350  *     Read access completion status; set to '0' for successful
3351  *     completion by EPC set to '1' to indicate read access error
3352  *     from EPC
3353  * Note: Currently, the EEPROM controller in Hydra does not
3354  *     return any error condition, ie, epcPeuErr = 1'b0 always. And
3355  *     so, for the PIO read access by the Host, the epcStat register
3356  *     in PEU will always show that the access was successful. For
3357  *     EEPROM read initiated through the ROM BAR by the Host, CIP
3358  *     will always return Successful Completion status to the Host.
3359  *     Any error situation is reported only in the Status Register
3360  *     within the EEPROM device. For access information about this
3361  *     register, please refer to the EEPROM/SPI PRMs.
3362  *
3363  *     Read Initiate. SW writes 1 to this bit to initiate a EEPROM
3364  *     read. Clears to 0 on updating the epcData reg. Writing 0 has
3365  *     no effect.
3366  */
3367 typedef union {
3368 	uint32_t value;
3369 	struct {
3370 #if defined(_BIG_ENDIAN)
3371 		uint32_t	epc_goto_normal:1;
3372 		uint32_t	rsrvd:8;
3373 		uint32_t	epc_addr:21;
3374 		uint32_t	epc_cpl_stat:1;
3375 		uint32_t	epc_rd_init:1;
3376 #else
3377 		uint32_t	epc_rd_init:1;
3378 		uint32_t	epc_cpl_stat:1;
3379 		uint32_t	epc_addr:21;
3380 		uint32_t	rsrvd:8;
3381 		uint32_t	epc_goto_normal:1;
3382 #endif
3383 	} bits;
3384 } epc_stat_t;
3385 
3386 
3387 /*
3388  * Register: EpcData
3389  * EEPROM PIO Data
3390  * Description: EEPROM PIO Data The data returned from EEPROM
3391  * controller for the EEPROM access initiated by the EEPROM PIO
3392  * Status register is returned in this register.
3393  * Fields:
3394  *     EEPROM Read Data; valid when rdInit transitioned from 1 to 0.
3395  */
3396 typedef union {
3397 	uint32_t value;
3398 	struct {
3399 #if defined(_BIG_ENDIAN)
3400 		uint32_t	eeprom_data:32;
3401 #else
3402 		uint32_t	eeprom_data:32;
3403 #endif
3404 	} bits;
3405 } epc_data_t;
3406 
3407 
3408 /*
3409  * Register: SpcStat
3410  * SPROM PIO Status
3411  * Description: SPROM PIO Status
3412  * Fields:
3413  *     Force the SPC state machine to go to NORMAL state. This bit is
3414  *     used to force the SPC to skip the downloading of the SPROM
3415  *     contents into the EP/Pipe/Hcr registers. Setting this bit will
3416  *     make CIP to drop any pending requests to the DBI/AHB buses.
3417  *     The bit is auto-cleared after switching to the Normal state.
3418  *     This bit can not be used to terminate a pio access to
3419  *     PCI/PIPE/HCR registers. If a pio access to these registers is
3420  *     not responded to, by the respective block, then the pio access
3421  *     will automatically timeout. The timeout value is specified by
3422  *     the timeoutCfg:tmoutCnt value
3423  */
3424 typedef union {
3425 	uint32_t value;
3426 	struct {
3427 #if defined(_BIG_ENDIAN)
3428 		uint32_t	rsrvd:29;
3429 		uint32_t	spc_goto_normal:1;
3430 		uint32_t	rsrvd1:2;
3431 #else
3432 		uint32_t	rsrvd1:2;
3433 		uint32_t	spc_goto_normal:1;
3434 		uint32_t	rsrvd:29;
3435 #endif
3436 	} bits;
3437 } spc_stat_t;
3438 
3439 
3440 /*
3441  * Register: Host2spiIndaccAddr
3442  * HOST -> SPI Shared Domain Read Address
3443  * Description: Read address set by Host for indirect access to
3444  * shared domain address space The decoding of the address is as
3445  * follows: [23:20] - block select [19:0] - register offset from base
3446  * address of block
3447  * Fields:
3448  *     Address in Shared domain
3449  */
3450 typedef union {
3451 	uint32_t value;
3452 	struct {
3453 #if defined(_BIG_ENDIAN)
3454 		uint32_t	rsrvd:8;
3455 		uint32_t	addr:24;
3456 #else
3457 		uint32_t	addr:24;
3458 		uint32_t	rsrvd:8;
3459 #endif
3460 	} bits;
3461 } host2spi_indacc_addr_t;
3462 
3463 
3464 /*
3465  * Register: Host2spiIndaccCtrl
3466  * HOST -> SPI Shared Domain Read Control
3467  * Description: Control word set by Host for indirect access to the
3468  * shared domain address space Writing to this register initiates the
3469  * indirect access to the shared domain.
3470  * The Host may read or write to a shared domain region data as
3471  * below : Host updates the host2spiIndaccAddr register with address
3472  * of the shared domain reg. For writes, Host updates the
3473  * host2spiIndaccData register with write data Host then writes to
3474  * bit 0 of host2spiIndaccCtrl register to '1' or '0' to initiate the
3475  * read or write access; 1 : write command, 0 : read command Host
3476  * should then poll bit 1 of host2spiIndaccCtrl register for the
3477  * access status. 1 : access is done, 0 : access is in progress
3478  * (busy) Host should then check bit 2 of host2spiIndaccCtrl register
3479  * to know if the command was successful; 1 : access error, 0 :
3480  * access successful For reads, Host then reads the
3481  * host2spiIndaccData register for the read data.
3482  * This register can be written into only when there is no pending
3483  * access, ie, indaccCtrl.cplStat=1. Writes when indaccCtrl.cplStat=0
3484  * is ignored.
3485  *
3486  * Fields:
3487  *     command completion status; 0 : successful completion of
3488  *     command by SPI 1 : access error from SPI
3489  *     command progress status; 0 : access is in progress (busy) 1 :
3490  *     access is done
3491  *     1 : Initiate a write access 0 : Initiate a read access
3492  */
3493 typedef union {
3494 	uint32_t value;
3495 	struct {
3496 #if defined(_BIG_ENDIAN)
3497 		uint32_t	rsrvd:29;
3498 		uint32_t	err_stat:1;
3499 		uint32_t	cpl_stat:1;
3500 		uint32_t	rd_wr_cmd:1;
3501 #else
3502 		uint32_t	rd_wr_cmd:1;
3503 		uint32_t	cpl_stat:1;
3504 		uint32_t	err_stat:1;
3505 		uint32_t	rsrvd:29;
3506 #endif
3507 	} bits;
3508 } host2spi_indacc_ctrl_t;
3509 
3510 
3511 /*
3512  * Register: Host2spiIndaccData
3513  * HOST -> SPI Shared Domain Read/Write Data
3514  * Description: For indirect read access by the Host, this register
3515  * returns the data returned from the Shared Domain For indirect
3516  * write access by the Host, the host should update this register
3517  * with the writeData for the Shared Domain, before writing to the
3518  * host2spiIndaccCtrl register to initiate the access.
3519  * This register can be written into only when there is no pending
3520  * access, ie, indaccCtrl.cplStat=1. Writes when indaccCtrl.cplStat=0
3521  * is ignored.
3522  *
3523  * Fields:
3524  *     Shared domain read/write data
3525  */
3526 typedef union {
3527 	uint32_t value;
3528 	struct {
3529 #if defined(_BIG_ENDIAN)
3530 		uint32_t	data:32;
3531 #else
3532 		uint32_t	data:32;
3533 #endif
3534 	} bits;
3535 } host2spi_indacc_data_t;
3536 
3537 
3538 /*
3539  * Register: BtCtrl0
3540  * Mailbox Control & Access status 0
3541  * Description: Host (blade) <-> SP Block Transfer mailbox control
3542  * and access status register 0.
3543  * Host is allowed 8 bits read/write access to this register ; To do
3544  * the same, it should provide the btCtrl0 address, data on
3545  * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
3546  * read/write access to this register ; To do the same, it should
3547  * provide the btCtrl0 address, data on spiDataBus[7:0], and no need
3548  * of spiBen
3549  *
3550  * Fields:
3551  *     The SP sets/clears this bit to indicate if it is busy and can
3552  *     not accept any other request; write 1 to toggle the bit; Read
3553  *     Only by Host.
3554  *     The Host sets/clears this bit to indicate if it is busy and
3555  *     can not accept any other request; Read Only by SP.
3556  *     Reserved for definition by platform. Typical usage could be
3557  *     "heartbeat" mechanism from/to the host. The host sets OEM0 to
3558  *     interrupt the SP and then polls it to be cleared by SP
3559  *     The SP sets this bit when it has detected and queued an SMS
3560  *     message in the SP2HOST buffer that must be reported to the
3561  *     HOST. The Host clears this bit by writing a 1 to it. This bit
3562  *     may generate an intrpt to Host depending on the sp2hostIntEn
3563  *     bit. Writing 0 has no effect
3564  *     The SP writes 1 to this bit after it has finished writing a
3565  *     message into the SP2HOST buffer. The Host clears this bit by
3566  *     writing 1 to it after it has set the hostBusy bit This bit may
3567  *     generate an intrpt to Host depending on the sp2hostIntEn bit.
3568  *     Writing 0 has no effect
3569  *     The Host writes 1 to this bit to generate an interrupt to SP
3570  *     after it has finished writing a message into the HOST2SP
3571  *     buffer. The SP clears this bit by writing 1 to it after it has
3572  *     set the spBusy bit. Writing 0 has no effect
3573  *     The host writes 1 to clear the read pointer to the BT SP2HOST
3574  *     buffer; the SP writes 1 to clear the read pointer to the BT
3575  *     HOST2SP buffer. This bit is always read back as 0; writing 0
3576  *     has no effect.
3577  *     The host writes 1 to clear the write pointer to the BT HOST2SP
3578  *     buffer; the SP writes 1 to clear the write pointer to the BT
3579  *     SP2HOST buffer. This bit is always read back as 0; writing 0
3580  *     has no effect.
3581  */
3582 typedef union {
3583 	uint32_t value;
3584 	struct {
3585 #if defined(_BIG_ENDIAN)
3586 		uint32_t	rsrvd:24;
3587 		uint32_t	sp_busy:1;
3588 		uint32_t	host_busy:1;
3589 		uint32_t	oem0:1;
3590 		uint32_t	sms_atn:1;
3591 		uint32_t	sp2host_atn:1;
3592 		uint32_t	host2sp_atn:1;
3593 		uint32_t	clr_rd_ptr:1;
3594 		uint32_t	clr_wr_ptr:1;
3595 #else
3596 		uint32_t	clr_wr_ptr:1;
3597 		uint32_t	clr_rd_ptr:1;
3598 		uint32_t	host2sp_atn:1;
3599 		uint32_t	sp2host_atn:1;
3600 		uint32_t	sms_atn:1;
3601 		uint32_t	oem0:1;
3602 		uint32_t	host_busy:1;
3603 		uint32_t	sp_busy:1;
3604 		uint32_t	rsrvd:24;
3605 #endif
3606 	} bits;
3607 } bt_ctrl0_t;
3608 
3609 
3610 /*
3611  * Register: BtData0
3612  * Mailbox Data 0
3613  * Description: Host (blade) <-> SP mailbox data register 0.
3614  * Host is allowed a 32 bits read/write access to this register ; To
3615  * do the same, it should provide the btData0 address, data on
3616  * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
3617  * bits read/write access to this register ; To do the same, it
3618  * should provide the btData0 address, data on spiDataBus[7:0], and
3619  * no need of spiBen
3620  * All references to the mail box control bits in this register
3621  * refer to btCtrl0. When spBusy=0 && host2spAtn=0, data is written
3622  * by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0,
3623  * data is written by the SP and read by the Host.
3624  *
3625  * Fields:
3626  *     Bits 7:0 of message data to send to SP/HOST
3627  */
3628 typedef union {
3629 	uint32_t value;
3630 	struct {
3631 #if defined(_BIG_ENDIAN)
3632 		uint32_t	rsrvd:24;
3633 		uint32_t	data:8;
3634 #else
3635 		uint32_t	data:8;
3636 		uint32_t	rsrvd:24;
3637 #endif
3638 	} bits;
3639 } bt_data0_t;
3640 
3641 
3642 /*
3643  * Register: BtIntmask0
3644  * Mailbox Interrupt Mask & Status 0
3645  * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
3646  * Status register 0
3647  * Host is allowed 8 bits read/write access to this register ; To do
3648  * the same, it should provide the btIntmask0 address, data on
3649  * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
3650  * read only access to this register ; To do the same, it should
3651  * provide the btIntmask0 address and no need of spiBen
3652  * All references to the mail box control bits in this register
3653  * refer to btCtrl0
3654  * Fields:
3655  *     The host writes 1 to reset the entire mailbox 0 accesses for
3656  *     error recovery; resets both SP and HOST write and read
3657  *     pointers. Writing 0 has no effect. This is non-sticky. Always
3658  *     read back as 0.
3659  *     Reserved for definition by platform manufacturer for BIOS/SMI
3660  *     Handler use. Generic IPMI software must write this bit as 0
3661  *     and ignore the value on read
3662  *     Reserved for definition by platform manufacturer for BIOS/SMI
3663  *     Handler use. Generic IPMI software must write this bit as 0
3664  *     and ignore the value on read
3665  *     Reserved for definition by platform manufacturer for BIOS/SMI
3666  *     Handler use. Generic IPMI software must write this bit as 0
3667  *     and ignore the value on read
3668  *     SP to HOST Interrupt status This bit reflects the state of the
3669  *     intrpt line to the Host. O/S driver should write 1 to clear.
3670  *     SP to HOST Interrupt Enable The interrupt is generated if
3671  *     sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
3672  */
3673 typedef union {
3674 	uint32_t value;
3675 	struct {
3676 #if defined(_BIG_ENDIAN)
3677 		uint32_t	rsrvd:24;
3678 		uint32_t	mb_master_reset:1;
3679 		uint32_t	rsrvd1:2;
3680 		uint32_t	oem3:1;
3681 		uint32_t	oem2:1;
3682 		uint32_t	oem1:1;
3683 		uint32_t	sp2h_irq:1;
3684 		uint32_t	sp2h_irq_en:1;
3685 #else
3686 		uint32_t	sp2h_irq_en:1;
3687 		uint32_t	sp2h_irq:1;
3688 		uint32_t	oem1:1;
3689 		uint32_t	oem2:1;
3690 		uint32_t	oem3:1;
3691 		uint32_t	rsrvd1:2;
3692 		uint32_t	mb_master_reset:1;
3693 		uint32_t	rsrvd:24;
3694 #endif
3695 	} bits;
3696 } bt_intmask0_t;
3697 
3698 
3699 /*
3700  * Register: BtCtrl1
3701  * Mailbox Control & Access status 1
3702  * Description: Host (blade) <-> SP Block Transfer mailbox control
3703  * and access status register 1.
3704  * Host is allowed 8 bits read/write access to this register ; To do
3705  * the same, it should provide the btCtrl1 address, data on
3706  * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
3707  * read/write access to this register ; To do the same, it should
3708  * provide the btCtrl1 address, data on spiDataBus[7:0], and no need
3709  * of spiBen
3710  *
3711  * Fields:
3712  *     The SP sets/clears this bit to indicate that it is busy and
3713  *     can not accept any other request; write 1 to toggle the bit;
3714  *     Read only by Host.
3715  *     The Host sets/clears this bit to indicate that it is busy and
3716  *     can not accept any other request; Read only by SP.
3717  *     Reserved for definition by platform. Typical usage could be
3718  *     "heartbeat" mechanism from/to the host. The host sets OEM0 to
3719  *     interrupt the SP and then polls it to be cleared by SP
3720  *     The SP sets this bit when it has detected and queued an SMS
3721  *     message in the SP2HOST buffer that must be reported to the
3722  *     HOST. The Host clears this bit by writing a 1 to it. This bit
3723  *     may generate an intrpt to Host depending on the sp2hostIntEn
3724  *     bit. Writing 0 has no effect
3725  *     The SP writes 1 to this bit after it has finished writing a
3726  *     message into the SP2HOST buffer. The Host clears this bit by
3727  *     writing 1 to it after it has set the hostBusy bit This bit may
3728  *     generate an intrpt to Host depending on the sp2hostIntEn bit.
3729  *     Writing 0 has no effect
3730  *     The Host writes 1 to this bit to generate an interrupt to SP
3731  *     after it has finished writing a message into the HOST2SP
3732  *     buffer. The SP clears this bit by writing 1 to it after it has
3733  *     set the spBusy bit. Writing 0 has no effect
3734  *     The host writes 1 to clear the read pointer to the BT SP2HOST
3735  *     buffer; the SP writes 1 to clear the read pointer to the BT
3736  *     HOST2SP buffer. This bit is always read back as 0; writing 0
3737  *     has no effect.
3738  *     The host writes 1 to clear the write pointer to the BT HOST2SP
3739  *     buffer; the SP writes 1 to clear the write pointer to the BT
3740  *     SP2HOST buffer. This bit is always read back as 0; writing 0
3741  *     has no effect.
3742  */
3743 typedef union {
3744 	uint32_t value;
3745 	struct {
3746 #if defined(_BIG_ENDIAN)
3747 		uint32_t	rsrvd:24;
3748 		uint32_t	sp_busy:1;
3749 		uint32_t	host_busy:1;
3750 		uint32_t	oem0:1;
3751 		uint32_t	sms_atn:1;
3752 		uint32_t	sp2host_atn:1;
3753 		uint32_t	host2sp_atn:1;
3754 		uint32_t	clr_rd_ptr:1;
3755 		uint32_t	clr_wr_ptr:1;
3756 #else
3757 		uint32_t	clr_wr_ptr:1;
3758 		uint32_t	clr_rd_ptr:1;
3759 		uint32_t	host2sp_atn:1;
3760 		uint32_t	sp2host_atn:1;
3761 		uint32_t	sms_atn:1;
3762 		uint32_t	oem0:1;
3763 		uint32_t	host_busy:1;
3764 		uint32_t	sp_busy:1;
3765 		uint32_t	rsrvd:24;
3766 #endif
3767 	} bits;
3768 } bt_ctrl1_t;
3769 
3770 
3771 /*
3772  * Register: BtData1
3773  * Mailbox Data 1
3774  * Description: Host (blade) <-> SP mailbox data register 1.
3775  * Host is allowed a 32 bits read/write access to this register ; To
3776  * do the same, it should provide the btData1 address, data on
3777  * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
3778  * bits read/write access to this register ; To do the same, it
3779  * should provide the btData1 address, data on spiDataBus[7:0], and
3780  * no need of spiBen
3781  * All references to the mail box control bits in this register
3782  * refer to btCtrl1. When spBusy=0 && host2spAtn=0, data is written
3783  * by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0,
3784  * data is written by the SP and read by the Host.
3785  * Fields:
3786  *     Bits 31:0 of message data to send to SP/HOST
3787  */
3788 typedef union {
3789 	uint32_t value;
3790 	struct {
3791 #if defined(_BIG_ENDIAN)
3792 		uint32_t	rsrvd:24;
3793 		uint32_t	data:8;
3794 #else
3795 		uint32_t	data:8;
3796 		uint32_t	rsrvd:24;
3797 #endif
3798 	} bits;
3799 } bt_data1_t;
3800 
3801 
3802 /*
3803  * Register: BtIntmask1
3804  * Mailbox Interrupt Mask & Status 1
3805  * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
3806  * Status register 1
3807  * Host is allowed 8 bits read/write access to this register ; To do
3808  * the same, it should provide the btIntmask1 address, data on
3809  * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
3810  * read only access to this register ; To do the same, it should
3811  * provide the btIntmask1 address and no need of spiBen
3812  * All references to the mail box control bits in this register
3813  * refer to btCtrl1
3814  * Fields:
3815  *     The host writes 1 to reset the entire mailbox 1 accesses for
3816  *     error recovery; resets both SP and HOST write and read
3817  *     pointers. Writing 0 has no effect. This is non-sticky. Always
3818  *     read back as 0.
3819  *     Reserved for definition by platform manufacturer for BIOS/SMI
3820  *     Handler use. Generic IPMI software must write this bit as 0
3821  *     and ignore the value on read
3822  *     Reserved for definition by platform manufacturer for BIOS/SMI
3823  *     Handler use. Generic IPMI software must write this bit as 0
3824  *     and ignore the value on read
3825  *     Reserved for definition by platform manufacturer for BIOS/SMI
3826  *     Handler use. Generic IPMI software must write this bit as 0
3827  *     and ignore the value on read
3828  *     SP to HOST Interrupt status This bit reflects the state of the
3829  *     intrpt line to the Host. O/S driver should write 1 to clear.
3830  *     SP to HOST Interrupt Enable The interrupt is generated if
3831  *     sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
3832  */
3833 typedef union {
3834 	uint32_t value;
3835 	struct {
3836 #if defined(_BIG_ENDIAN)
3837 		uint32_t	rsrvd:24;
3838 		uint32_t	mb_master_reset:1;
3839 		uint32_t	rsrvd1:2;
3840 		uint32_t	oem3:1;
3841 		uint32_t	oem2:1;
3842 		uint32_t	oem1:1;
3843 		uint32_t	sp2h_irq:1;
3844 		uint32_t	sp2h_irq_en:1;
3845 #else
3846 		uint32_t	sp2h_irq_en:1;
3847 		uint32_t	sp2h_irq:1;
3848 		uint32_t	oem1:1;
3849 		uint32_t	oem2:1;
3850 		uint32_t	oem3:1;
3851 		uint32_t	rsrvd1:2;
3852 		uint32_t	mb_master_reset:1;
3853 		uint32_t	rsrvd:24;
3854 #endif
3855 	} bits;
3856 } bt_intmask1_t;
3857 
3858 
3859 /*
3860  * Register: BtCtrl2
3861  * Mailbox Control & Access status 2
3862  * Description: Host (blade) <-> SP Block Transfer mailbox control
3863  * and access status register 2.
3864  * Host is allowed 8 bits read/write access to this register ; To do
3865  * the same, it should provide the btCtrl2 address, data on
3866  * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
3867  * read/write access to this register ; To do the same, it should
3868  * provide the btCtrl2 address, data on spiDataBus[7:0], and no need
3869  * of spiBen
3870  *
3871  * Fields:
3872  *     The SP sets/clears this bit to indicate that it is busy and
3873  *     can not accept any other request; write 1 to toggle the bit;
3874  *     Read only by Host.
3875  *     The Host sets/clears this bit to indicate that it is busy and
3876  *     can not accept any other request; Read only by SP.
3877  *     Reserved for definition by platform. Typical usage could be
3878  *     "heartbeat" mechanism from/to the host. The host sets OEM0 to
3879  *     interrupt the SP and then polls it to be cleared by SP
3880  *     The SP sets this bit when it has detected and queued an SMS
3881  *     message in the SP2HOST buffer that must be reported to the
3882  *     HOST. The Host clears this bit by writing a 1 to it. This bit
3883  *     may generate an intrpt to Host depending on the sp2hostIntEn
3884  *     bit. Writing 0 has no effect
3885  *     The SP writes 1 to this bit after it has finished writing a
3886  *     message into the SP2HOST buffer. The Host clears this bit by
3887  *     writing 1 to it after it has set the hostBusy bit This bit may
3888  *     generate an intrpt to Host depending on the sp2hostIntEn bit.
3889  *     Writing 0 has no effect
3890  *     The Host writes 1 to this bit to generate an interrupt to SP
3891  *     after it has finished writing a message into the HOST2SP
3892  *     buffer. The SP clears this bit by writing 1 to it after it has
3893  *     set the spBusy bit. Writing 0 has no effect
3894  *     The host writes 1 to clear the read pointer to the BT SP2HOST
3895  *     buffer; the SP writes 1 to clear the read pointer to the BT
3896  *     HOST2SP buffer. This bit is always read back as 0; writing 0
3897  *     has no effect.
3898  *     The host writes 1 to clear the write pointer to the BT HOST2SP
3899  *     buffer; the SP writes 1 to clear the write pointer to the BT
3900  *     SP2HOST buffer. This bit is always read back as 0; writing 0
3901  *     has no effect.
3902  */
3903 typedef union {
3904 	uint32_t value;
3905 	struct {
3906 #if defined(_BIG_ENDIAN)
3907 		uint32_t	rsrvd:24;
3908 		uint32_t	sp_busy:1;
3909 		uint32_t	host_busy:1;
3910 		uint32_t	oem0:1;
3911 		uint32_t	sms_atn:1;
3912 		uint32_t	sp2host_atn:1;
3913 		uint32_t	host2sp_atn:1;
3914 		uint32_t	clr_rd_ptr:1;
3915 		uint32_t	clr_wr_ptr:1;
3916 #else
3917 		uint32_t	clr_wr_ptr:1;
3918 		uint32_t	clr_rd_ptr:1;
3919 		uint32_t	host2sp_atn:1;
3920 		uint32_t	sp2host_atn:1;
3921 		uint32_t	sms_atn:1;
3922 		uint32_t	oem0:1;
3923 		uint32_t	host_busy:1;
3924 		uint32_t	sp_busy:1;
3925 		uint32_t	rsrvd:24;
3926 #endif
3927 	} bits;
3928 } bt_ctrl2_t;
3929 
3930 
3931 /*
3932  * Register: BtData2
3933  * Mailbox Data 2
3934  * Description: Host (blade) <-> SP mailbox data register 2. All
3935  * references to the mail box control bits in this register refer to
3936  * btCtrl2.
3937  * Host is allowed a 32 bits read/write access to this register ; To
3938  * do the same, it should provide the btData2 address, data on
3939  * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
3940  * bits read/write access to this register ; To do the same, it
3941  * should provide the btData2 address, data on spiDataBus[7:0], and
3942  * no need of spiBen
3943  * When spBusy=0 && host2spAtn=0, data is written by the host and
3944  * read by the SP. When hostBusy=0 && sp2hostAtn=0, data is written
3945  * by the SP and read by the Host.
3946  * Fields:
3947  *     Bits 31:0 of message data to send to SP/HOST
3948  */
3949 typedef union {
3950 	uint32_t value;
3951 	struct {
3952 #if defined(_BIG_ENDIAN)
3953 		uint32_t	rsrvd:24;
3954 		uint32_t	data:8;
3955 #else
3956 		uint32_t	data:8;
3957 		uint32_t	rsrvd:24;
3958 #endif
3959 	} bits;
3960 } bt_data2_t;
3961 
3962 
3963 /*
3964  * Register: BtIntmask2
3965  * Mailbox Interrupt Mask & Status 2
3966  * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
3967  * Status register 2
3968  * Host is allowed 8 bits read/write access to this register ; To do
3969  * the same, it should provide the btIntmask2 address, data on
3970  * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
3971  * read only access to this register ; To do the same, it should
3972  * provide the btIntmask2 address and no need of spiBen
3973  * All references to the mail box control bits in this register
3974  * refer to btCtrl2
3975  * Fields:
3976  *     The host writes 1 to reset the entire mailbox 2 accesses for
3977  *     error recovery; resets both SP and HOST write and read
3978  *     pointers. Writing 0 has no effect. This is non-sticky. Always
3979  *     read back as 0.
3980  *     Reserved for definition by platform manufacturer for BIOS/SMI
3981  *     Handler use. Generic IPMI software must write this bit as 0
3982  *     and ignore the value on read
3983  *     Reserved for definition by platform manufacturer for BIOS/SMI
3984  *     Handler use. Generic IPMI software must write this bit as 0
3985  *     and ignore the value on read
3986  *     Reserved for definition by platform manufacturer for BIOS/SMI
3987  *     Handler use. Generic IPMI software must write this bit as 0
3988  *     and ignore the value on read
3989  *     SP to HOST Interrupt status This bit reflects the state of the
3990  *     intrpt line to the Host. O/S driver should write 1 to clear.
3991  *     SP to HOST Interrupt Enable The interrupt is generated if
3992  *     sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
3993  */
3994 typedef union {
3995 	uint32_t value;
3996 	struct {
3997 #if defined(_BIG_ENDIAN)
3998 		uint32_t	rsrvd:24;
3999 		uint32_t	mb_master_reset:1;
4000 		uint32_t	rsrvd1:2;
4001 		uint32_t	oem3:1;
4002 		uint32_t	oem2:1;
4003 		uint32_t	oem1:1;
4004 		uint32_t	sp2h_irq:1;
4005 		uint32_t	sp2h_irq_en:1;
4006 #else
4007 		uint32_t	sp2h_irq_en:1;
4008 		uint32_t	sp2h_irq:1;
4009 		uint32_t	oem1:1;
4010 		uint32_t	oem2:1;
4011 		uint32_t	oem3:1;
4012 		uint32_t	rsrvd1:2;
4013 		uint32_t	mb_master_reset:1;
4014 		uint32_t	rsrvd:24;
4015 #endif
4016 	} bits;
4017 } bt_intmask2_t;
4018 
4019 
4020 /*
4021  * Register: BtCtrl3
4022  * Mailbox Control & Access status 3
4023  * Description: Host (blade) <-> SP Block Transfer mailbox control
4024  * and access status register 3.
4025  * Host is allowed 8 bits read/write access to this register ; To do
4026  * the same, it should provide the btCtrl3 address, data on
4027  * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
4028  * read/write access to this register ; To do the same, it should
4029  * provide the btCtrl3 address, data on spiDataBus[7:0], and no need
4030  * of spiBen
4031  *
4032  * Fields:
4033  *     The SP sets/clears this bit to indicate that it is busy and
4034  *     can not accept any other request; write 1 to toggle the bit;
4035  *     Read only by Host.
4036  *     The Host sets/clears this bit to indicate that it is busy and
4037  *     can not accept any other request; Read only by SP.
4038  *     Reserved for definition by platform. Typical usage could be
4039  *     "heartbeat" mechanism from/to the host. The host sets OEM0 to
4040  *     interrupt the SP and then polls it to be cleared by SP
4041  *     The SP sets this bit when it has detected and queued an SMS
4042  *     message in the SP2HOST buffer that must be reported to the
4043  *     HOST. The Host clears this bit by writing a 1 to it. This bit
4044  *     may generate an intrpt to Host depending on the sp2hostIntEn
4045  *     bit. Writing 0 has no effect
4046  *     The SP writes 1 to this bit after it has finished writing a
4047  *     message into the SP2HOST buffer. The Host clears this bit by
4048  *     writing 1 to it after it has set the hostBusy bit This bit may
4049  *     generate an intrpt to Host depending on the sp2hostIntEn bit.
4050  *     Writing 0 has no effect
4051  *     The Host writes 1 to this bit to generate an interrupt to SP
4052  *     after it has finished writing a message into the HOST2SP
4053  *     buffer. The SP clears this bit by writing 1 to it after it has
4054  *     set the spBusy bit. Writing 0 has no effect
4055  *     The host writes 1 to clear the read pointer to the BT SP2HOST
4056  *     buffer; the SP writes 1 to clear the read pointer to the BT
4057  *     HOST2SP buffer. This bit is always read back as 0; writing 0
4058  *     has no effect.
4059  *     The host writes 1 to clear the write pointer to the BT HOST2SP
4060  *     buffer; the SP writes 1 to clear the write pointer to the BT
4061  *     SP2HOST buffer. This bit is always read back as 0; writing 0
4062  *     has no effect.
4063  */
4064 typedef union {
4065 	uint32_t value;
4066 	struct {
4067 #if defined(_BIG_ENDIAN)
4068 		uint32_t	rsrvd:24;
4069 		uint32_t	sp_busy:1;
4070 		uint32_t	host_busy:1;
4071 		uint32_t	oem0:1;
4072 		uint32_t	sms_atn:1;
4073 		uint32_t	sp2host_atn:1;
4074 		uint32_t	host2sp_atn:1;
4075 		uint32_t	clr_rd_ptr:1;
4076 		uint32_t	clr_wr_ptr:1;
4077 #else
4078 		uint32_t	clr_wr_ptr:1;
4079 		uint32_t	clr_rd_ptr:1;
4080 		uint32_t	host2sp_atn:1;
4081 		uint32_t	sp2host_atn:1;
4082 		uint32_t	sms_atn:1;
4083 		uint32_t	oem0:1;
4084 		uint32_t	host_busy:1;
4085 		uint32_t	sp_busy:1;
4086 		uint32_t	rsrvd:24;
4087 #endif
4088 	} bits;
4089 } bt_ctrl3_t;
4090 
4091 
4092 /*
4093  * Register: BtData3
4094  * Mailbox Data 3
4095  * Description: Host (blade) <-> SP mailbox data register 3.
4096  * Host is allowed a 32 bits read/write access to this register ; To
4097  * do the same, it should provide the btData3 address, data on
4098  * hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
4099  * bits read/write access to this register ; To do the same, it
4100  * should provide the btData3 address, data on spiDataBus[7:0], and
4101  * no need of spiBen
4102  * All references to the mail box control bits in this register
4103  * refer to btCtrl3. When spBusy=0 && host2spAtn=0, data is written
4104  * by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0,
4105  * data is written by the SP and read by the Host.
4106  * Fields:
4107  *     Bits 31:0 of message data to send to SP/HOST
4108  */
4109 typedef union {
4110 	uint32_t value;
4111 	struct {
4112 #if defined(_BIG_ENDIAN)
4113 		uint32_t	rsrvd:24;
4114 		uint32_t	data:8;
4115 #else
4116 		uint32_t	data:8;
4117 		uint32_t	rsrvd:24;
4118 #endif
4119 	} bits;
4120 } bt_data3_t;
4121 
4122 
4123 /*
4124  * Register: BtIntmask3
4125  * Mailbox Interrupt Mask & Status 3
4126  * Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
4127  * Status register 3
4128  * Host is allowed 8 bits read/write access to this register ; To do
4129  * the same, it should provide the btIntmask3 address, data on
4130  * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
4131  * read only access to this register ; To do the same, it should
4132  * provide the btIntmask3 address and no need of spiBen
4133  * All references to the mail box control bits in this register
4134  * refer to btCtrl3
4135  * Fields:
4136  *     The host writes 1 to reset the entire mailbox 3 accesses for
4137  *     error recovery; resets both SP and HOST write and read
4138  *     pointers. Writing 0 has no effect. This is non-sticky. Always
4139  *     read back as 0.
4140  *     Reserved for definition by platform manufacturer for BIOS/SMI
4141  *     Handler use. Generic IPMI software must write this bit as 0
4142  *     and ignore the value on read
4143  *     Reserved for definition by platform manufacturer for BIOS/SMI
4144  *     Handler use. Generic IPMI software must write this bit as 0
4145  *     and ignore the value on read
4146  *     Reserved for definition by platform manufacturer for BIOS/SMI
4147  *     Handler use. Generic IPMI software must write this bit as 0
4148  *     and ignore the value on read
4149  *     SP to HOST Interrupt status This bit reflects the state of the
4150  *     intrpt line to the Host. O/S driver should write 1 to clear.
4151  *     SP to HOST Interrupt Enable The interrupt is generated if
4152  *     sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
4153  */
4154 typedef union {
4155 	uint32_t value;
4156 	struct {
4157 #if defined(_BIG_ENDIAN)
4158 		uint32_t	rsrvd:24;
4159 		uint32_t	mb_master_reset:1;
4160 		uint32_t	rsrvd1:2;
4161 		uint32_t	oem3:1;
4162 		uint32_t	oem2:1;
4163 		uint32_t	oem1:1;
4164 		uint32_t	sp2h_irq:1;
4165 		uint32_t	sp2h_irq_en:1;
4166 #else
4167 		uint32_t	sp2h_irq_en:1;
4168 		uint32_t	sp2h_irq:1;
4169 		uint32_t	oem1:1;
4170 		uint32_t	oem2:1;
4171 		uint32_t	oem3:1;
4172 		uint32_t	rsrvd1:2;
4173 		uint32_t	mb_master_reset:1;
4174 		uint32_t	rsrvd:24;
4175 #endif
4176 	} bits;
4177 } bt_intmask3_t;
4178 
4179 
4180 /*
4181  * Register: DebugSel
4182  * CIP Debug Data Select
4183  * Description: Selects the debug data signals from the CIP blocks
4184  * Fields:
4185  *     Selects up to 16 groups of gbtDebug/pipeDebug on
4186  *     peuPhyVdbgDebugPort[31:0]
4187  *     Selects the high DW of the debug data - default is PCIe link
4188  *     status
4189  *     Selects the low DW of the debug data
4190  */
4191 typedef union {
4192 	uint32_t value;
4193 	struct {
4194 #if defined(_BIG_ENDIAN)
4195 		uint32_t	rsrvd:12;
4196 		uint32_t	phy_dbug_sel:4;
4197 		uint32_t	rsrvd1:3;
4198 		uint32_t	cip_hdbug_sel:5;
4199 		uint32_t	rsrvd2:3;
4200 		uint32_t	cip_ldbug_sel:5;
4201 #else
4202 		uint32_t	cip_ldbug_sel:5;
4203 		uint32_t	rsrvd2:3;
4204 		uint32_t	cip_hdbug_sel:5;
4205 		uint32_t	rsrvd1:3;
4206 		uint32_t	phy_dbug_sel:4;
4207 		uint32_t	rsrvd:12;
4208 #endif
4209 	} bits;
4210 } debug_sel_t;
4211 
4212 
4213 /*
4214  * Register: IndaccMem0Ctrl
4215  * CIP Mem0 Debug ctrl
4216  * Description: Debug data signals from the CIP blocks
4217  * Fields:
4218  *     1: rd/wr access is done 0: rd/wr access is in progress
4219  *     1: pkt injection is done 0: pkt injection is in progress
4220  *     Ingress pkt injection enable: write to 1 for single pkt
4221  *     injection. Must be 0 when enabling diagnostic rd/wr access to
4222  *     memories.
4223  *     1: Diagnostic rd/wr access to memories enabled 0: Diagnostic
4224  *     rd/wr access to memories disabled Must be 0 when enabling pkt
4225  *     injection.
4226  *     1: read, 0: write
4227  *     This bit is read/writable only if mem0Diagen=1 or if
4228  *     mem0Diagen bit is also written with '1' along with enabling
4229  *     this bit. Else, the write will not have any effect. 1: Apply
4230  *     the parity mask provided in the Prty register 0: Do not apply
4231  *     the parity mask provided in the Prty register
4232  *     0 : select npdataq memory 1 : select nphdrq memory 2 : select
4233  *     pdataq memory 3 : select phdrq memory 4 : select cpldataq
4234  *     memory 5 : select cplhdrq memory
4235  */
4236 typedef union {
4237 	uint32_t value;
4238 	struct {
4239 #if defined(_BIG_ENDIAN)
4240 		uint32_t	mem0_access_status:1;
4241 		uint32_t	rsrvd:5;
4242 		uint32_t	mem0_pktinj_stat:1;
4243 		uint32_t	mem0_pktinj_en:1;
4244 		uint32_t	rsrvd1:1;
4245 		uint32_t	mem0_diagen:1;
4246 		uint32_t	mem0_command:1;
4247 		uint32_t	mem0_prty_wen:1;
4248 		uint32_t	rsrvd2:1;
4249 		uint32_t	mem0_sel:3;
4250 		uint32_t	mem0_addr:16;
4251 #else
4252 		uint32_t	mem0_addr:16;
4253 		uint32_t	mem0_sel:3;
4254 		uint32_t	rsrvd2:1;
4255 		uint32_t	mem0_prty_wen:1;
4256 		uint32_t	mem0_command:1;
4257 		uint32_t	mem0_diagen:1;
4258 		uint32_t	rsrvd1:1;
4259 		uint32_t	mem0_pktinj_en:1;
4260 		uint32_t	mem0_pktinj_stat:1;
4261 		uint32_t	rsrvd:5;
4262 		uint32_t	mem0_access_status:1;
4263 #endif
4264 	} bits;
4265 } indacc_mem0_ctrl_t;
4266 
4267 
4268 /*
4269  * Register: IndaccMem0Data0
4270  * CIP Mem0 Debug Data0
4271  * Description: Debug data signals from the CIP blocks
4272  * Fields:
4273  *     When pktInjectionEnable is 0: Data[31:0] from/for the memory
4274  *     selected by mem0Sel bits from mem0Ctrl This data is written to
4275  *     the memory when indaccMem0Ctrl register is written with the
4276  *     write command When indaccMem0Ctrl register is written with the
4277  *     read command, this register will hold the Data[31:0] returned
4278  *     from the memory When pktInjectionEnable is 1:
4279  *     debugData0Reg[31:0] is used in the following ways: [17:16] =
4280  *     radmTrgt1Fmt[1:0]: 2'b00 3DW MRd 2'b01 4DW MRd 2'b10 3DW MWr
4281  *     2'b11 4DW MWr [13:12] = radmTrgt1DwLen[1:0]: 2'b01 1DW 2'b10
4282  *     2DW [11:8] = radmTrgt1LastBe[3:0]: 4'b0000 1DW 4'b1111 2DW [7]
4283  *     = radmTrgt1RomInRange 1'b0 PIO Access 1'b1 EEPROM Access [6:4]
4284  *     = radmTrgt1InMembarRange[2:0] 3'b000 PIO Access 3'b010 MSIX
4285  *     Ram/PBA Table Access [1:0] = radmTrgt1Dwen[1:0] 2'b01
4286  *     1DW->last DW is at radmTrgt1Data[31:0] 2'b11 2DW->last DW is
4287  *     at radmTrgt1Data[63:32]
4288  */
4289 typedef union {
4290 	uint32_t value;
4291 	struct {
4292 #if defined(_BIG_ENDIAN)
4293 		uint32_t	mem0_data0:32;
4294 #else
4295 		uint32_t	mem0_data0:32;
4296 #endif
4297 	} bits;
4298 } indacc_mem0_data0_t;
4299 
4300 
4301 /*
4302  * Register: IndaccMem0Data1
4303  * CIP Mem0 Debug Data1
4304  * Description: Debug data signals from the CIP blocks
4305  * Fields:
4306  *     When pktInjectionEnable is 0: Data[63:32] from/for the memory
4307  *     selected by mem0Sel bits from mem0Ctrl This data is written to
4308  *     the memory when indaccMem0Ctrl register is written with the
4309  *     write command When indaccMem0Ctrl register is written with the
4310  *     read command, this register will hold the Data[63:32] returned
4311  *     from the memory When pktInjectionEnable is 1:
4312  *     debugData1Reg[31:0] is used as radmTrgt1Addr[31:0].
4313  */
4314 typedef union {
4315 	uint32_t value;
4316 	struct {
4317 #if defined(_BIG_ENDIAN)
4318 		uint32_t	mem0_data1:32;
4319 #else
4320 		uint32_t	mem0_data1:32;
4321 #endif
4322 	} bits;
4323 } indacc_mem0_data1_t;
4324 
4325 
4326 /*
4327  * Register: IndaccMem0Data2
4328  * CIP Mem0 Debug Data2
4329  * Description: Debug data signals from the CIP blocks
4330  * Fields:
4331  *     When pktInjectionEnable is 0: Data[95:64] from/for the memory
4332  *     selected by mem0Sel bits from mem0Ctrl This data is written to
4333  *     the memory when indaccMem0Ctrl register is written with the
4334  *     write command When indaccMem0Ctrl register is written with the
4335  *     read command, this register will hold the Data[95:64] returned
4336  *     from the memory When pktInjectionEnable is 1:
4337  *     debugData2Reg[31:0] is used as radmTrgt1Data[63:32]. Allows up
4338  *     to QW=2DW access.
4339  */
4340 typedef union {
4341 	uint32_t value;
4342 	struct {
4343 #if defined(_BIG_ENDIAN)
4344 		uint32_t	mem0_data2:32;
4345 #else
4346 		uint32_t	mem0_data2:32;
4347 #endif
4348 	} bits;
4349 } indacc_mem0_data2_t;
4350 
4351 
4352 /*
4353  * Register: IndaccMem0Data3
4354  * CIP Mem0 Debug Data3
4355  * Description: Debug data signals from the CIP blocks
4356  * Fields:
4357  *     When pktInjectionEnable is 0: Data[127:96] from/for the memory
4358  *     selected by mem0Sel bits from mem0Ctrl This data is written to
4359  *     the memory when indaccMem0Ctrl register is written with the
4360  *     write command When indaccMem0Ctrl register is written with the
4361  *     read command, this register will hold the Data[127:96]
4362  *     returned from the memory When pktInjectionEnable is 1:
4363  *     debugData3Reg[31:0] is used as radmTrgt1Data[31:0].
4364  */
4365 typedef union {
4366 	uint32_t value;
4367 	struct {
4368 #if defined(_BIG_ENDIAN)
4369 		uint32_t	mem0_data3:32;
4370 #else
4371 		uint32_t	mem0_data3:32;
4372 #endif
4373 	} bits;
4374 } indacc_mem0_data3_t;
4375 
4376 
4377 /*
4378  * Register: IndaccMem0Prty
4379  * CIP Mem0 Debug Parity
4380  * Description: Debug data signals from the CIP blocks
4381  * Fields:
4382  *     parity mask bits for the memory selected by mem0Sel bits from
4383  *     mem0Ctrl to inject parity error These bits serve two purposes
4384  *     regarding memory parity : - During indirect write access to
4385  *     the memories, the value in this register is applied as mask to
4386  *     the actual parity if prtyWen bit of the indaccCtrl register
4387  *     has been enabled. The masked parity and data are written into
4388  *     the specified memory location. - During indirect read access
4389  *     to the memories, the value in this register is overwritten
4390  *     with the parity value read from the memory location. If the
4391  *     parity mask had been set and enabled to be written into this
4392  *     location it will generate parity error for that memory
4393  *     location
4394  */
4395 typedef union {
4396 	uint32_t value;
4397 	struct {
4398 #if defined(_BIG_ENDIAN)
4399 		uint32_t	rsrvd:18;
4400 		uint32_t	mem0_parity:14;
4401 #else
4402 		uint32_t	mem0_parity:14;
4403 		uint32_t	rsrvd:18;
4404 #endif
4405 	} bits;
4406 } indacc_mem0_prty_t;
4407 
4408 
4409 /*
4410  * Register: IndaccMem1Ctrl
4411  * CIP Mem1 Debug ctrl
4412  * Description: Debug data signals from the CIP blocks
4413  * Fields:
4414  *     1: rd/wr access is done 0: rd/wr access is in progress
4415  *     1: client pkt injection is done 0: client pkt injection is in
4416  *     progress
4417  *     1: client1 pkt injection 0: client0 pkt injection
4418  *     Mutually exclusive: Either client0 or client1 egress pkt
4419  *     injection enable: write to 1 for single pkt injection. Must be
4420  *     0 when enabling diagnostic rd/wr access to memories.
4421  *     1: Diagnostic rd/wr access enabled 0: Diagnostic rd/wr access
4422  *     disabled Must be 0 when enabling pkt injection.
4423  *     1: read, 0: write
4424  *     This bit is read/writable only if mem1Diagen=1 or if
4425  *     mem1Diagen bit is also written with '1' along with enabling
4426  *     this bit. Else, the write will not have any effect. 1: Apply
4427  *     the parity mask provided in the Prty register 0: Do not apply
4428  *     the parity mask provided in the Prty register
4429  *     0 : select retry sot memory 1 : select retry buffer memory 2 :
4430  *     select msix memory 3 : select hcr cfg memory
4431  */
4432 typedef union {
4433 	uint32_t value;
4434 	struct {
4435 #if defined(_BIG_ENDIAN)
4436 		uint32_t	mem1_access_status:1;
4437 		uint32_t	rsrvd:4;
4438 		uint32_t	mem1_pktinj_stat:1;
4439 		uint32_t	mem1_pktinj_client:1;
4440 		uint32_t	mem1_pktinj_en:1;
4441 		uint32_t	rsrvd1:1;
4442 		uint32_t	mem1_diagen:1;
4443 		uint32_t	mem1_command:1;
4444 		uint32_t	mem1_prty_wen:1;
4445 		uint32_t	rsrvd2:2;
4446 		uint32_t	mem1_sel:2;
4447 		uint32_t	mem1_addr:16;
4448 #else
4449 		uint32_t	mem1_addr:16;
4450 		uint32_t	mem1_sel:2;
4451 		uint32_t	rsrvd2:2;
4452 		uint32_t	mem1_prty_wen:1;
4453 		uint32_t	mem1_command:1;
4454 		uint32_t	mem1_diagen:1;
4455 		uint32_t	rsrvd1:1;
4456 		uint32_t	mem1_pktinj_en:1;
4457 		uint32_t	mem1_pktinj_client:1;
4458 		uint32_t	mem1_pktinj_stat:1;
4459 		uint32_t	rsrvd:4;
4460 		uint32_t	mem1_access_status:1;
4461 #endif
4462 	} bits;
4463 } indacc_mem1_ctrl_t;
4464 
4465 
4466 /*
4467  * Register: IndaccMem1Data0
4468  * CIP Mem1 Debug Data0
4469  * Description: Debug data signals from the CIP blocks
4470  * Fields:
4471  *     When pktInjectionEnable is 0: Data[31:0] from/for the memory
4472  *     selected by mem1Sel bits from mem1Ctrl This data is written to
4473  *     the memory when indaccMem1Ctrl register is written with the
4474  *     write command When indaccMem1Ctrl register is written with the
4475  *     read command, this register will hold the Data[31:0] returned
4476  *     from the memory
4477  * When pktInjectionEnable is 1: debugData0Reg[31:0] is used in
4478  *     the following ways: [27:26] = tdcPeuTlp0[or
4479  *     rdcPeuTlp1]_fmt[1:0]: 2'b00 3DW MRd 2'b01 4DW MRd 2'b10 3DW
4480  *     MWr 2'b11 4DW MWr [25:13] = tdcPeuTlp0[or
4481  *     rdcPeuTlp1]_byteLen[12:0]: Note MWr must be limited to 4B =
4482  *     13'b0000000000001. [12:8] = tdcPeuTlp0[or
4483  *     rdcPeuTlp1]_tid[4:0]: 5 lsb of tid (TAG ID) [7:0] =
4484  *     tdcPeuTlp0[or rdcPeuTlp1]_byteEn[7:0]: [7:4] = last DW byte
4485  *     enables [3:0] = first DW byte enables
4486  */
4487 typedef union {
4488 	uint32_t value;
4489 	struct {
4490 #if defined(_BIG_ENDIAN)
4491 		uint32_t	mem1_data0:32;
4492 #else
4493 		uint32_t	mem1_data0:32;
4494 #endif
4495 	} bits;
4496 } indacc_mem1_data0_t;
4497 
4498 
4499 /*
4500  * Register: IndaccMem1Data1
4501  * CIP Mem1 Debug Data1
4502  * Description: Debug data signals from the CIP blocks
4503  * Fields:
4504  *     When pktInjectionEnable is 0: Data[63:32] from/for the memory
4505  *     selected by mem1Sel bits from mem1Ctrl This data is written to
4506  *     the memory when indaccMem1Ctrl register is written with the
4507  *     write command When indaccMem1Ctrl register is written with the
4508  *     read command, this register will hold the Data[63:32] returned
4509  *     from the memory
4510  * When pktInjectionEnable is 1: debugData1Reg[31:0] is used as
4511  *     tdcPeuTlp0[or rdcPeuTlp1]_addr[63:32] high address bits.
4512  */
4513 typedef union {
4514 	uint32_t value;
4515 	struct {
4516 #if defined(_BIG_ENDIAN)
4517 		uint32_t	mem1_data1:32;
4518 #else
4519 		uint32_t	mem1_data1:32;
4520 #endif
4521 	} bits;
4522 } indacc_mem1_data1_t;
4523 
4524 
4525 /*
4526  * Register: IndaccMem1Data2
4527  * CIP Mem1 Debug Data2
4528  * Description: Debug data signals from the CIP blocks
4529  * Fields:
4530  *     When pktInjectionEnable is 0: Data[95:64] from/for the memory
4531  *     selected by mem1Sel bits from mem1Ctrl This data is written to
4532  *     the memory when indaccMem1Ctrl register is written with the
4533  *     write command When indaccMem1Ctrl register is written with the
4534  *     read command, this register will hold the Data[95:64] returned
4535  *     from the memory
4536  * When pktInjectionEnable is 1: debugData2Reg[31:0] is used as
4537  *     tdcPeuTlp0[or rdcPeuTlp1]_addr[31:0] low address bits.
4538  */
4539 typedef union {
4540 	uint32_t value;
4541 	struct {
4542 #if defined(_BIG_ENDIAN)
4543 		uint32_t	mem1_data2:32;
4544 #else
4545 		uint32_t	mem1_data2:32;
4546 #endif
4547 	} bits;
4548 }