13dec9fcdSqs /* 23dec9fcdSqs * CDDL HEADER START 33dec9fcdSqs * 43dec9fcdSqs * The contents of this file are subject to the terms of the 53dec9fcdSqs * Common Development and Distribution License (the "License"). 63dec9fcdSqs * You may not use this file except in compliance with the License. 73dec9fcdSqs * 83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs * See the License for the specific language governing permissions 113dec9fcdSqs * and limitations under the License. 123dec9fcdSqs * 133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs * 193dec9fcdSqs * CDDL HEADER END 203dec9fcdSqs */ 213dec9fcdSqs /* 22*0dc2366fSVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs * Use is subject to license terms. 243dec9fcdSqs */ 253dec9fcdSqs 263dec9fcdSqs #ifndef _SYS_HXGE_HXGE_IMPL_H 273dec9fcdSqs #define _SYS_HXGE_HXGE_IMPL_H 283dec9fcdSqs 293dec9fcdSqs #ifdef __cplusplus 303dec9fcdSqs extern "C" { 313dec9fcdSqs #endif 323dec9fcdSqs 333dec9fcdSqs #ifndef _ASM 343dec9fcdSqs #include <sys/types.h> 353dec9fcdSqs #include <sys/byteorder.h> 363dec9fcdSqs #include <sys/debug.h> 373dec9fcdSqs #include <sys/stropts.h> 383dec9fcdSqs #include <sys/stream.h> 393dec9fcdSqs #include <sys/strlog.h> 403dec9fcdSqs #include <sys/strsubr.h> 413dec9fcdSqs #include <sys/cmn_err.h> 423dec9fcdSqs #include <sys/vtrace.h> 433dec9fcdSqs #include <sys/kmem.h> 443dec9fcdSqs #include <sys/ddi.h> 453dec9fcdSqs #include <sys/sunddi.h> 463dec9fcdSqs #include <sys/strsun.h> 473dec9fcdSqs #include <sys/stat.h> 483dec9fcdSqs #include <sys/cpu.h> 493dec9fcdSqs #include <sys/kstat.h> 503dec9fcdSqs #include <inet/common.h> 513dec9fcdSqs #include <inet/ip.h> 523dec9fcdSqs #include <inet/ip6.h> 533dec9fcdSqs #include <sys/dlpi.h> 543dec9fcdSqs #include <inet/nd.h> 553dec9fcdSqs #include <netinet/in.h> 563dec9fcdSqs #include <sys/ethernet.h> 573dec9fcdSqs #include <sys/vlan.h> 583dec9fcdSqs #include <sys/pci.h> 593dec9fcdSqs #include <sys/taskq.h> 603dec9fcdSqs #include <sys/atomic.h> 613dec9fcdSqs 623dec9fcdSqs #include <hxge_defs.h> 633dec9fcdSqs #include <hxge_peu.h> 643dec9fcdSqs #include <hxge_pfc.h> 653dec9fcdSqs #include <hxge_pfc_hw.h> 663dec9fcdSqs #include <hxge_vmac.h> 673dec9fcdSqs #include <hxge_fm.h> 683dec9fcdSqs #include <sys/netlb.h> 693dec9fcdSqs #include <sys/ddi_intr.h> 703dec9fcdSqs 71da14cebeSEric Cheng #include <sys/mac_provider.h> 723dec9fcdSqs #include <sys/mac_ether.h> 73*0dc2366fSVenugopal Iyer #include <sys/note.h> 743dec9fcdSqs 753dec9fcdSqs /* 763dec9fcdSqs * Handy macros (taken from bge driver) 773dec9fcdSqs */ 783dec9fcdSqs #define RBR_SIZE 4 793dec9fcdSqs #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 803dec9fcdSqs #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 813dec9fcdSqs #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 823dec9fcdSqs #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 833dec9fcdSqs #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 843dec9fcdSqs (area).offset, (area).alength, \ 853dec9fcdSqs (flag))) 863dec9fcdSqs #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 873dec9fcdSqs ((void) ddi_dma_sync((area).dma_handle,\ 883dec9fcdSqs (area.offset + bufoffset), len, \ 893dec9fcdSqs (flag))) 903dec9fcdSqs 913dec9fcdSqs #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 923dec9fcdSqs #define NEXT_ENTRY_PTR(ptr, first, last) \ 933dec9fcdSqs ((ptr == last) ? first : (ptr + 1)) 943dec9fcdSqs 953dec9fcdSqs /* 963dec9fcdSqs * HPI related macros 973dec9fcdSqs */ 983dec9fcdSqs #define HXGE_DEV_HPI_HANDLE(hxgep) (hxgep->hpi_handle) 993dec9fcdSqs 1003dec9fcdSqs #define HPI_PCI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_pci_handle.regh = ah) 1013dec9fcdSqs #define HPI_PCI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_pci_handle.regp = ap) 1023dec9fcdSqs 1033dec9fcdSqs #define HPI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_handle.regh = ah) 1043dec9fcdSqs #define HPI_ADD_HANDLE_SET(hxgep, ap) \ 1053dec9fcdSqs hxgep->hpi_handle.is_vraddr = B_FALSE; \ 1063dec9fcdSqs hxgep->hpi_handle.function.instance = hxgep->instance; \ 1073dec9fcdSqs hxgep->hpi_handle.function.function = 0; \ 1083dec9fcdSqs hxgep->hpi_handle.hxgep = (void *) hxgep; \ 1093dec9fcdSqs hxgep->hpi_handle.regp = ap; 1103dec9fcdSqs 1113dec9fcdSqs #define HPI_REG_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_reg_handle.regh = ah) 1123dec9fcdSqs #define HPI_REG_ADD_HANDLE_SET(hxgep, ap) \ 1133dec9fcdSqs hxgep->hpi_reg_handle.is_vraddr = B_FALSE; \ 1143dec9fcdSqs hxgep->hpi_handle.function.instance = hxgep->instance; \ 1153dec9fcdSqs hxgep->hpi_handle.function.function = 0; \ 1163dec9fcdSqs hxgep->hpi_reg_handle.hxgep = (void *) hxgep; \ 1173dec9fcdSqs hxgep->hpi_reg_handle.regp = ap; 1183dec9fcdSqs 1193dec9fcdSqs #define HPI_MSI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_msi_handle.regh = ah) 12023b519b2SMichael Speer #define HPI_MSI_ADD_HANDLE_SET(hxgep, ap) \ 12123b519b2SMichael Speer hxgep->hpi_msi_handle.is_vraddr = B_FALSE; \ 12223b519b2SMichael Speer hxgep->hpi_msi_handle.function.instance = hxgep->instance; \ 12323b519b2SMichael Speer hxgep->hpi_msi_handle.function.function = 0; \ 12423b519b2SMichael Speer hxgep->hpi_msi_handle.hxgep = (void *) hxgep; \ 12523b519b2SMichael Speer hxgep->hpi_msi_handle.regp = ap; 1263dec9fcdSqs 1273dec9fcdSqs #define HPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->hpi_handle.regh = ah) 1283dec9fcdSqs #define HPI_DMA_ACC_HANDLE_GET(dmap) (dmap->hpi_handle.regh) 1293dec9fcdSqs 1303dec9fcdSqs #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 1313dec9fcdSqs 1323dec9fcdSqs typedef uint32_t hxge_status_t; 1333dec9fcdSqs 1343dec9fcdSqs typedef enum { 1353dec9fcdSqs DVMA, 1363dec9fcdSqs DMA, 1373dec9fcdSqs SDMA 1383dec9fcdSqs } dma_method_t; 1393dec9fcdSqs 1403dec9fcdSqs typedef enum { 1413dec9fcdSqs BKSIZE_4K, 1423dec9fcdSqs BKSIZE_8K, 1433dec9fcdSqs BKSIZE_16K, 1443dec9fcdSqs BKSIZE_32K 1453dec9fcdSqs } hxge_rx_block_size_t; 1463dec9fcdSqs 1473dec9fcdSqs #ifdef TX_ONE_BUF 1481ed83081SMichael Speer #define TX_BCOPY_MAX 512 1493dec9fcdSqs #else 1501ed83081SMichael Speer #define TX_BCOPY_MAX 512 1511ed83081SMichael Speer #define TX_BCOPY_SIZE 512 1523dec9fcdSqs #endif 1533dec9fcdSqs 1543dec9fcdSqs #define TX_STREAM_MIN 512 1553dec9fcdSqs #define TX_FASTDVMA_MIN 1024 1563dec9fcdSqs 1573dec9fcdSqs #define HXGE_RDC_RCR_THRESHOLD_MAX 256 1583dec9fcdSqs #define HXGE_RDC_RCR_TIMEOUT_MAX 64 1593dec9fcdSqs #define HXGE_RDC_RCR_THRESHOLD_MIN 1 1603dec9fcdSqs #define HXGE_RDC_RCR_TIMEOUT_MIN 1 1613dec9fcdSqs 1623dec9fcdSqs #define HXGE_IS_VLAN_PACKET(ptr) \ 1633dec9fcdSqs ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 1643dec9fcdSqs htons(VLAN_ETHERTYPE)) 1653dec9fcdSqs 1663dec9fcdSqs typedef enum { 1673dec9fcdSqs USE_NONE, 1683dec9fcdSqs USE_BCOPY, 1693dec9fcdSqs USE_DVMA, 1703dec9fcdSqs USE_DMA, 1713dec9fcdSqs USE_SDMA 1723dec9fcdSqs } dma_type_t; 1733dec9fcdSqs 1743dec9fcdSqs struct _hxge_block_mv_t { 1753dec9fcdSqs uint32_t msg_type; 1763dec9fcdSqs dma_type_t dma_type; 1773dec9fcdSqs }; 1783dec9fcdSqs 1793dec9fcdSqs typedef struct _hxge_block_mv_t hxge_block_mv_t, *p_hxge_block_mv_t; 1803dec9fcdSqs 1813dec9fcdSqs typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 1823dec9fcdSqs typedef struct ether_header ether_header_t, *p_ether_header_t; 1833dec9fcdSqs typedef queue_t *p_queue_t; 1843dec9fcdSqs typedef mblk_t *p_mblk_t; 1853dec9fcdSqs 1863dec9fcdSqs /* 1873dec9fcdSqs * Common DMA data elements. 1883dec9fcdSqs */ 1893dec9fcdSqs struct _hxge_dma_common_t { 1903dec9fcdSqs uint16_t dma_channel; 1913dec9fcdSqs void *kaddrp; 1923dec9fcdSqs void *ioaddr_pp; 1933dec9fcdSqs ddi_dma_cookie_t dma_cookie; 1943dec9fcdSqs uint32_t ncookies; 1953dec9fcdSqs 1963dec9fcdSqs ddi_dma_handle_t dma_handle; 1973dec9fcdSqs hxge_os_acc_handle_t acc_handle; 1983dec9fcdSqs hpi_handle_t hpi_handle; 1993dec9fcdSqs 2003dec9fcdSqs size_t block_size; 2013dec9fcdSqs uint32_t nblocks; 2023dec9fcdSqs size_t alength; 2033dec9fcdSqs uint_t offset; 2043dec9fcdSqs uint_t dma_chunk_index; 2053dec9fcdSqs void *orig_ioaddr_pp; 2063dec9fcdSqs uint64_t orig_vatopa; 2073dec9fcdSqs void *orig_kaddrp; 2083dec9fcdSqs size_t orig_alength; 2093dec9fcdSqs boolean_t contig_alloc_type; 2103dec9fcdSqs }; 2113dec9fcdSqs 2123dec9fcdSqs typedef struct _hxge_t hxge_t, *p_hxge_t; 2133dec9fcdSqs typedef struct _hxge_dma_common_t hxge_dma_common_t, *p_hxge_dma_common_t; 2143dec9fcdSqs 2153dec9fcdSqs typedef struct _hxge_dma_pool_t { 2163dec9fcdSqs p_hxge_dma_common_t *dma_buf_pool_p; 2173dec9fcdSqs uint32_t ndmas; 2183dec9fcdSqs uint32_t *num_chunks; 2193dec9fcdSqs boolean_t buf_allocated; 2203dec9fcdSqs } hxge_dma_pool_t, *p_hxge_dma_pool_t; 2213dec9fcdSqs 2223dec9fcdSqs /* 2233dec9fcdSqs * Each logical device (69): 2243dec9fcdSqs * - LDG # 2253dec9fcdSqs * - flag bits 2263dec9fcdSqs * - masks. 2273dec9fcdSqs * - interrupt handler function. 2283dec9fcdSqs * 2293dec9fcdSqs * Generic system interrupt handler with two arguments: 2303dec9fcdSqs * (hxge_sys_intr_t) 2313dec9fcdSqs * Per device instance data structure 2323dec9fcdSqs * Logical group data structure. 2333dec9fcdSqs * 2343dec9fcdSqs * Logical device interrupt handler with two arguments: 2353dec9fcdSqs * (hxge_ldv_intr_t) 2363dec9fcdSqs * Per device instance data structure 2373dec9fcdSqs * Logical device number 2383dec9fcdSqs */ 2393dec9fcdSqs typedef struct _hxge_ldg_t hxge_ldg_t, *p_hxge_ldg_t; 2403dec9fcdSqs typedef struct _hxge_ldv_t hxge_ldv_t, *p_hxge_ldv_t; 2413dec9fcdSqs typedef uint_t (*hxge_sys_intr_t)(caddr_t arg1, caddr_t arg2); 2423dec9fcdSqs typedef uint_t (*hxge_ldv_intr_t)(caddr_t arg1, caddr_t arg2); 2433dec9fcdSqs 2443dec9fcdSqs /* 2453dec9fcdSqs * Each logical device Group (64) needs to have the following 2463dec9fcdSqs * configurations: 2473dec9fcdSqs * - timer counter (6 bits) 2483dec9fcdSqs * - timer resolution (20 bits, number of system clocks) 2493dec9fcdSqs * - system data (7 bits) 2503dec9fcdSqs */ 2513dec9fcdSqs struct _hxge_ldg_t { 2523dec9fcdSqs uint8_t ldg; /* logical group number */ 2533dec9fcdSqs uint8_t vldg_index; 2543dec9fcdSqs boolean_t arm; 2553dec9fcdSqs boolean_t interrupted; 2563dec9fcdSqs uint16_t ldg_timer; /* counter */ 2573dec9fcdSqs uint8_t vector; 2583dec9fcdSqs uint8_t nldvs; 2593dec9fcdSqs p_hxge_ldv_t ldvp; 2603dec9fcdSqs hxge_sys_intr_t sys_intr_handler; 2613dec9fcdSqs p_hxge_t hxgep; 262*0dc2366fSVenugopal Iyer uint32_t htable_idx; 2633dec9fcdSqs }; 2643dec9fcdSqs 2653dec9fcdSqs struct _hxge_ldv_t { 2663dec9fcdSqs uint8_t ldg_assigned; 2673dec9fcdSqs uint8_t ldv; 2683dec9fcdSqs boolean_t is_rxdma; 2693dec9fcdSqs boolean_t is_txdma; 2703dec9fcdSqs boolean_t is_vmac; 2713dec9fcdSqs boolean_t is_syserr; 2723dec9fcdSqs boolean_t is_pfc; 2733dec9fcdSqs boolean_t use_timer; 2743dec9fcdSqs uint8_t channel; 2753dec9fcdSqs uint8_t vdma_index; 2763dec9fcdSqs p_hxge_ldg_t ldgp; 2773dec9fcdSqs uint8_t ldv_ldf_masks; 2783dec9fcdSqs hxge_ldv_intr_t ldv_intr_handler; 2793dec9fcdSqs p_hxge_t hxgep; 2803dec9fcdSqs }; 2813dec9fcdSqs 2823dec9fcdSqs typedef struct _pci_cfg_t { 2833dec9fcdSqs uint16_t vendorid; 2843dec9fcdSqs uint16_t devid; 2853dec9fcdSqs uint16_t command; 2863dec9fcdSqs uint16_t status; 2873dec9fcdSqs uint8_t revid; 2883dec9fcdSqs uint8_t res0; 2893dec9fcdSqs uint16_t junk1; 2903dec9fcdSqs uint8_t cache_line; 2913dec9fcdSqs uint8_t latency; 2923dec9fcdSqs uint8_t header; 2933dec9fcdSqs uint8_t bist; 2943dec9fcdSqs uint32_t base; 2953dec9fcdSqs uint32_t base14; 2963dec9fcdSqs uint32_t base18; 2973dec9fcdSqs uint32_t base1c; 2983dec9fcdSqs uint32_t base20; 2993dec9fcdSqs uint32_t base24; 3003dec9fcdSqs uint32_t base28; 3013dec9fcdSqs uint32_t base2c; 3023dec9fcdSqs uint32_t base30; 3033dec9fcdSqs uint32_t res1[2]; 3043dec9fcdSqs uint8_t int_line; 3053dec9fcdSqs uint8_t int_pin; 3063dec9fcdSqs uint8_t min_gnt; 3073dec9fcdSqs uint8_t max_lat; 3083dec9fcdSqs } pci_cfg_t, *p_pci_cfg_t; 3093dec9fcdSqs 3103dec9fcdSqs typedef struct _dev_regs_t { 3113dec9fcdSqs hxge_os_acc_handle_t hxge_pciregh; /* PCI config DDI IO handle */ 3123dec9fcdSqs p_pci_cfg_t hxge_pciregp; /* mapped PCI registers */ 3133dec9fcdSqs 3143dec9fcdSqs hxge_os_acc_handle_t hxge_regh; /* device DDI IO (BAR 0) */ 3153dec9fcdSqs void *hxge_regp; /* mapped device registers */ 3163dec9fcdSqs 3173dec9fcdSqs hxge_os_acc_handle_t hxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 3183dec9fcdSqs void *hxge_msix_regp; /* MSI/X register */ 3193dec9fcdSqs 3203dec9fcdSqs hxge_os_acc_handle_t hxge_romh; /* fcode rom handle */ 3213dec9fcdSqs unsigned char *hxge_romp; /* fcode pointer */ 3223dec9fcdSqs } dev_regs_t, *p_dev_regs_t; 3233dec9fcdSqs 3243dec9fcdSqs #include <hxge_common_impl.h> 3253dec9fcdSqs #include <hxge_common.h> 3263dec9fcdSqs #include <hxge_rxdma.h> 3273dec9fcdSqs #include <hxge_txdma.h> 3283dec9fcdSqs #include <hxge_fzc.h> 3293dec9fcdSqs #include <hxge_flow.h> 3303dec9fcdSqs #include <hxge_virtual.h> 3313dec9fcdSqs #include <hxge.h> 3323dec9fcdSqs #include <sys/modctl.h> 3333dec9fcdSqs #include <sys/pattr.h> 3343dec9fcdSqs #include <hpi_vir.h> 3353dec9fcdSqs 3363dec9fcdSqs /* 3373dec9fcdSqs * Reconfiguring the network devices requires the net_config privilege 3383dec9fcdSqs * in Solaris 10+. Prior to this, root privilege is required. In order 3393dec9fcdSqs * that the driver binary can run on both S10+ and earlier versions, we 3403dec9fcdSqs * make the decisiion as to which to use at runtime. These declarations 3413dec9fcdSqs * allow for either (or both) to exist ... 3423dec9fcdSqs */ 3433dec9fcdSqs extern int secpolicy_net_config(const cred_t *, boolean_t); 3443dec9fcdSqs extern void hxge_fm_report_error(p_hxge_t hxgep, 3453dec9fcdSqs uint8_t err_chan, hxge_fm_ereport_id_t fm_ereport_id); 3463dec9fcdSqs extern int fm_check_acc_handle(ddi_acc_handle_t); 3473dec9fcdSqs extern int fm_check_dma_handle(ddi_dma_handle_t); 3483dec9fcdSqs 3493dec9fcdSqs #pragma weak secpolicy_net_config 3503dec9fcdSqs 3513dec9fcdSqs hxge_status_t hxge_classify_init(p_hxge_t hxgep); 3523dec9fcdSqs hxge_status_t hxge_classify_uninit(p_hxge_t hxgep); 3533dec9fcdSqs void hxge_put_tcam(p_hxge_t hxgep, p_mblk_t mp); 3543dec9fcdSqs void hxge_get_tcam(p_hxge_t hxgep, p_mblk_t mp); 3553dec9fcdSqs 3563dec9fcdSqs hxge_status_t hxge_classify_init_hw(p_hxge_t hxgep); 3573dec9fcdSqs hxge_status_t hxge_classify_init_sw(p_hxge_t hxgep); 3583dec9fcdSqs hxge_status_t hxge_classify_exit_sw(p_hxge_t hxgep); 3593dec9fcdSqs hxge_status_t hxge_pfc_ip_class_config_all(p_hxge_t hxgep); 3603dec9fcdSqs hxge_status_t hxge_pfc_ip_class_config(p_hxge_t hxgep, tcam_class_t l3_class, 3613dec9fcdSqs uint32_t class_config); 3623dec9fcdSqs hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t hxgep, 3633dec9fcdSqs tcam_class_t l3_class, uint32_t *class_config); 3643dec9fcdSqs 3653dec9fcdSqs hxge_status_t hxge_pfc_set_hash(p_hxge_t, uint32_t); 3663dec9fcdSqs hxge_status_t hxge_pfc_config_tcam_enable(p_hxge_t); 3673dec9fcdSqs hxge_status_t hxge_pfc_config_tcam_disable(p_hxge_t); 3683dec9fcdSqs hxge_status_t hxge_pfc_ip_class_config(p_hxge_t, tcam_class_t, uint32_t); 3693dec9fcdSqs hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t, tcam_class_t, uint32_t *); 3703dec9fcdSqs hxge_status_t hxge_pfc_mac_addrs_get(p_hxge_t hxgep); 3713dec9fcdSqs 3723dec9fcdSqs 3733dec9fcdSqs hxge_status_t hxge_pfc_hw_reset(p_hxge_t hxgep); 3743dec9fcdSqs hxge_status_t hxge_pfc_handle_sys_errors(p_hxge_t hxgep); 3753dec9fcdSqs 3763dec9fcdSqs /* hxge_kstats.c */ 3773dec9fcdSqs void hxge_init_statsp(p_hxge_t); 3783dec9fcdSqs void hxge_setup_kstats(p_hxge_t); 3793dec9fcdSqs void hxge_destroy_kstats(p_hxge_t); 3803dec9fcdSqs int hxge_port_kstat_update(kstat_t *, int); 3813dec9fcdSqs 3823dec9fcdSqs int hxge_m_stat(void *arg, uint_t stat, uint64_t *val); 383*0dc2366fSVenugopal Iyer int hxge_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 384*0dc2366fSVenugopal Iyer int hxge_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 3853dec9fcdSqs 3863dec9fcdSqs /* hxge_hw.c */ 3873dec9fcdSqs void 3883dec9fcdSqs hxge_hw_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 3893dec9fcdSqs void hxge_loopback_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 3903dec9fcdSqs void hxge_global_reset(p_hxge_t); 3913dec9fcdSqs uint_t hxge_intr(caddr_t arg1, caddr_t arg2); 3923dec9fcdSqs void hxge_intr_enable(p_hxge_t hxgep); 3933dec9fcdSqs void hxge_intr_disable(p_hxge_t hxgep); 3943dec9fcdSqs void hxge_hw_id_init(p_hxge_t hxgep); 3953dec9fcdSqs void hxge_hw_init_niu_common(p_hxge_t hxgep); 3963dec9fcdSqs void hxge_intr_hw_enable(p_hxge_t hxgep); 3973dec9fcdSqs void hxge_intr_hw_disable(p_hxge_t hxgep); 3983dec9fcdSqs void hxge_hw_stop(p_hxge_t hxgep); 3993dec9fcdSqs void hxge_global_reset(p_hxge_t hxgep); 4003dec9fcdSqs void hxge_check_hw_state(p_hxge_t hxgep); 4013dec9fcdSqs 4023dec9fcdSqs /* hxge_send.c. */ 4033dec9fcdSqs uint_t hxge_reschedule(caddr_t arg); 4043dec9fcdSqs 4053dec9fcdSqs /* hxge_ndd.c */ 4063dec9fcdSqs void hxge_get_param_soft_properties(p_hxge_t); 4073dec9fcdSqs void hxge_setup_param(p_hxge_t); 4083dec9fcdSqs void hxge_init_param(p_hxge_t); 4093dec9fcdSqs void hxge_destroy_param(p_hxge_t); 4103dec9fcdSqs boolean_t hxge_check_rxdma_port_member(p_hxge_t, uint8_t); 4113dec9fcdSqs boolean_t hxge_check_txdma_port_member(p_hxge_t, uint8_t); 4123dec9fcdSqs int hxge_param_get_generic(p_hxge_t, queue_t *, mblk_t *, caddr_t); 4133dec9fcdSqs int hxge_param_set_generic(p_hxge_t, queue_t *, mblk_t *, char *, caddr_t); 4143dec9fcdSqs int hxge_get_default(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 4153dec9fcdSqs int hxge_set_default(p_hxge_t, queue_t *, p_mblk_t, char *, caddr_t); 4163dec9fcdSqs int hxge_nd_get_names(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 4173dec9fcdSqs int hxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size); 4183dec9fcdSqs void hxge_param_ioctl(p_hxge_t hxgep, queue_t *, mblk_t *, struct iocblk *); 4193dec9fcdSqs boolean_t hxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 4203dec9fcdSqs void hxge_nd_free(caddr_t *); 4213dec9fcdSqs int hxge_nd_getset(p_hxge_t, queue_t *, caddr_t, p_mblk_t); 4223dec9fcdSqs boolean_t hxge_set_lb(p_hxge_t, queue_t *wq, p_mblk_t mp); 423a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int hxge_param_rx_intr_pkts(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 424a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States caddr_t); 425a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int hxge_param_rx_intr_time(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 426a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States caddr_t); 427a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int hxge_param_set_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, char *, caddr_t); 428a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int hxge_param_get_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, caddr_t); 4293dec9fcdSqs 4303dec9fcdSqs /* hxge_virtual.c */ 4313dec9fcdSqs hxge_status_t hxge_get_config_properties(p_hxge_t); 4323dec9fcdSqs hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, 4333dec9fcdSqs p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p); 4343dec9fcdSqs hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 4353dec9fcdSqs p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 4363dec9fcdSqs hxge_status_t hxge_init_fzc_rx_common(p_hxge_t hxgep); 4373dec9fcdSqs hxge_status_t hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep, 4383dec9fcdSqs uint16_t channel, p_rx_rbr_ring_t rbr_p); 4393dec9fcdSqs hxge_status_t hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, 4403dec9fcdSqs uint16_t channel, p_tx_ring_t tx_ring_p); 4413dec9fcdSqs hxge_status_t hxge_intr_mask_mgmt_set(p_hxge_t hxgep, boolean_t on); 4423dec9fcdSqs 4433dec9fcdSqs /* MAC functions */ 4443dec9fcdSqs hxge_status_t hxge_vmac_init(p_hxge_t hxgep); 4453dec9fcdSqs hxge_status_t hxge_link_init(p_hxge_t hxgep); 4463dec9fcdSqs hxge_status_t hxge_tx_vmac_init(p_hxge_t hxgep); 4473dec9fcdSqs hxge_status_t hxge_rx_vmac_init(p_hxge_t hxgep); 4483dec9fcdSqs hxge_status_t hxge_tx_vmac_enable(p_hxge_t hxgep); 4493dec9fcdSqs hxge_status_t hxge_tx_vmac_disable(p_hxge_t hxgep); 4503dec9fcdSqs hxge_status_t hxge_rx_vmac_enable(p_hxge_t hxgep); 4513dec9fcdSqs hxge_status_t hxge_rx_vmac_disable(p_hxge_t hxgep); 4523dec9fcdSqs hxge_status_t hxge_tx_vmac_reset(p_hxge_t hxgep); 4533dec9fcdSqs hxge_status_t hxge_rx_vmac_reset(p_hxge_t hxgep); 4543dec9fcdSqs hxge_status_t hxge_add_mcast_addr(p_hxge_t, struct ether_addr *); 4553dec9fcdSqs hxge_status_t hxge_del_mcast_addr(p_hxge_t, struct ether_addr *); 4561ed83081SMichael Speer hxge_status_t hxge_pfc_set_mac_address(p_hxge_t hxgep, uint32_t slot, 4571ed83081SMichael Speer struct ether_addr *addrp); 4581ed83081SMichael Speer hxge_status_t hxge_pfc_num_macs_get(p_hxge_t hxgep, uint8_t *nmacs); 4591ed83081SMichael Speer hxge_status_t hxge_pfc_clear_mac_address(p_hxge_t, uint32_t slot); 4603dec9fcdSqs hxge_status_t hxge_set_promisc(p_hxge_t hxgep, boolean_t on); 4613dec9fcdSqs void hxge_save_cntrs(p_hxge_t hxgep); 462a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int hxge_vmac_set_framesize(p_hxge_t hxgep); 4633dec9fcdSqs 4643dec9fcdSqs void hxge_debug_msg(p_hxge_t, uint64_t, char *, ...); 4653dec9fcdSqs 4663dec9fcdSqs #ifdef HXGE_DEBUG 4673dec9fcdSqs char *hxge_dump_packet(char *addr, int size); 4683dec9fcdSqs #endif 4693dec9fcdSqs 4703dec9fcdSqs #endif /* !_ASM */ 4713dec9fcdSqs 4723dec9fcdSqs #ifdef __cplusplus 4733dec9fcdSqs } 4743dec9fcdSqs #endif 4753dec9fcdSqs 4763dec9fcdSqs #endif /* _SYS_HXGE_HXGE_IMPL_H */ 477