1*3dec9fcdSqs /*
2*3dec9fcdSqs * CDDL HEADER START
3*3dec9fcdSqs *
4*3dec9fcdSqs * The contents of this file are subject to the terms of the
5*3dec9fcdSqs * Common Development and Distribution License (the "License").
6*3dec9fcdSqs * You may not use this file except in compliance with the License.
7*3dec9fcdSqs *
8*3dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*3dec9fcdSqs * or http://www.opensolaris.org/os/licensing.
10*3dec9fcdSqs * See the License for the specific language governing permissions
11*3dec9fcdSqs * and limitations under the License.
12*3dec9fcdSqs *
13*3dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each
14*3dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*3dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the
16*3dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying
17*3dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner]
18*3dec9fcdSqs *
19*3dec9fcdSqs * CDDL HEADER END
20*3dec9fcdSqs */
21*3dec9fcdSqs /*
22*3dec9fcdSqs * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23*3dec9fcdSqs * Use is subject to license terms.
24*3dec9fcdSqs */
25*3dec9fcdSqs
26*3dec9fcdSqs #include <hxge_impl.h>
27*3dec9fcdSqs #include <hpi_vmac.h>
28*3dec9fcdSqs #include <hpi_rxdma.h>
29*3dec9fcdSqs
30*3dec9fcdSqs /*
31*3dec9fcdSqs * System interrupt registers that are under function zero management.
32*3dec9fcdSqs */
33*3dec9fcdSqs hxge_status_t
hxge_fzc_intr_init(p_hxge_t hxgep)34*3dec9fcdSqs hxge_fzc_intr_init(p_hxge_t hxgep)
35*3dec9fcdSqs {
36*3dec9fcdSqs hxge_status_t status = HXGE_OK;
37*3dec9fcdSqs
38*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_init"));
39*3dec9fcdSqs
40*3dec9fcdSqs /* Configure the initial timer resolution */
41*3dec9fcdSqs if ((status = hxge_fzc_intr_tmres_set(hxgep)) != HXGE_OK) {
42*3dec9fcdSqs return (status);
43*3dec9fcdSqs }
44*3dec9fcdSqs
45*3dec9fcdSqs /*
46*3dec9fcdSqs * Set up the logical device group's logical devices that
47*3dec9fcdSqs * the group owns.
48*3dec9fcdSqs */
49*3dec9fcdSqs if ((status = hxge_fzc_intr_ldg_num_set(hxgep)) != HXGE_OK) {
50*3dec9fcdSqs return (status);
51*3dec9fcdSqs }
52*3dec9fcdSqs
53*3dec9fcdSqs /* Configure the system interrupt data */
54*3dec9fcdSqs if ((status = hxge_fzc_intr_sid_set(hxgep)) != HXGE_OK) {
55*3dec9fcdSqs return (status);
56*3dec9fcdSqs }
57*3dec9fcdSqs
58*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_init"));
59*3dec9fcdSqs
60*3dec9fcdSqs return (status);
61*3dec9fcdSqs }
62*3dec9fcdSqs
63*3dec9fcdSqs hxge_status_t
hxge_fzc_intr_ldg_num_set(p_hxge_t hxgep)64*3dec9fcdSqs hxge_fzc_intr_ldg_num_set(p_hxge_t hxgep)
65*3dec9fcdSqs {
66*3dec9fcdSqs p_hxge_ldg_t ldgp;
67*3dec9fcdSqs p_hxge_ldv_t ldvp;
68*3dec9fcdSqs hpi_handle_t handle;
69*3dec9fcdSqs int i, j;
70*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
71*3dec9fcdSqs
72*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_ldg_num_set"));
73*3dec9fcdSqs
74*3dec9fcdSqs if (hxgep->ldgvp == NULL) {
75*3dec9fcdSqs return (HXGE_ERROR);
76*3dec9fcdSqs }
77*3dec9fcdSqs
78*3dec9fcdSqs ldgp = hxgep->ldgvp->ldgp;
79*3dec9fcdSqs ldvp = hxgep->ldgvp->ldvp;
80*3dec9fcdSqs if (ldgp == NULL || ldvp == NULL) {
81*3dec9fcdSqs return (HXGE_ERROR);
82*3dec9fcdSqs }
83*3dec9fcdSqs
84*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
85*3dec9fcdSqs
86*3dec9fcdSqs for (i = 0; i < hxgep->ldgvp->ldg_intrs; i++, ldgp++) {
87*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_ldg_num_set "
88*3dec9fcdSqs "<== hxge_f(Hydra): # ldv %d in group %d", ldgp->nldvs,
89*3dec9fcdSqs ldgp->ldg));
90*3dec9fcdSqs
91*3dec9fcdSqs for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
92*3dec9fcdSqs rs = hpi_fzc_ldg_num_set(handle, ldvp->ldv,
93*3dec9fcdSqs ldvp->ldg_assigned);
94*3dec9fcdSqs if (rs != HPI_SUCCESS) {
95*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
96*3dec9fcdSqs "<== hxge_fzc_intr_ldg_num_set failed "
97*3dec9fcdSqs " rs 0x%x ldv %d ldg %d",
98*3dec9fcdSqs rs, ldvp->ldv, ldvp->ldg_assigned));
99*3dec9fcdSqs return (HXGE_ERROR | rs);
100*3dec9fcdSqs }
101*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
102*3dec9fcdSqs "<== hxge_fzc_intr_ldg_num_set OK ldv %d ldg %d",
103*3dec9fcdSqs ldvp->ldv, ldvp->ldg_assigned));
104*3dec9fcdSqs }
105*3dec9fcdSqs }
106*3dec9fcdSqs
107*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_ldg_num_set"));
108*3dec9fcdSqs return (HXGE_OK);
109*3dec9fcdSqs }
110*3dec9fcdSqs
111*3dec9fcdSqs hxge_status_t
hxge_fzc_intr_tmres_set(p_hxge_t hxgep)112*3dec9fcdSqs hxge_fzc_intr_tmres_set(p_hxge_t hxgep)
113*3dec9fcdSqs {
114*3dec9fcdSqs hpi_handle_t handle;
115*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
116*3dec9fcdSqs
117*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_tmrese_set"));
118*3dec9fcdSqs if (hxgep->ldgvp == NULL) {
119*3dec9fcdSqs return (HXGE_ERROR);
120*3dec9fcdSqs }
121*3dec9fcdSqs
122*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
123*3dec9fcdSqs if ((rs = hpi_fzc_ldg_timer_res_set(handle, hxgep->ldgvp->tmres))) {
124*3dec9fcdSqs return (HXGE_ERROR | rs);
125*3dec9fcdSqs }
126*3dec9fcdSqs
127*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_tmrese_set"));
128*3dec9fcdSqs return (HXGE_OK);
129*3dec9fcdSqs }
130*3dec9fcdSqs
131*3dec9fcdSqs hxge_status_t
hxge_fzc_intr_sid_set(p_hxge_t hxgep)132*3dec9fcdSqs hxge_fzc_intr_sid_set(p_hxge_t hxgep)
133*3dec9fcdSqs {
134*3dec9fcdSqs hpi_handle_t handle;
135*3dec9fcdSqs p_hxge_ldg_t ldgp;
136*3dec9fcdSqs fzc_sid_t sid;
137*3dec9fcdSqs int i;
138*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
139*3dec9fcdSqs
140*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_sid_set"));
141*3dec9fcdSqs if (hxgep->ldgvp == NULL) {
142*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
143*3dec9fcdSqs "<== hxge_fzc_intr_sid_set: no ldg"));
144*3dec9fcdSqs return (HXGE_ERROR);
145*3dec9fcdSqs }
146*3dec9fcdSqs
147*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
148*3dec9fcdSqs ldgp = hxgep->ldgvp->ldgp;
149*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
150*3dec9fcdSqs "==> hxge_fzc_intr_sid_set: #int %d", hxgep->ldgvp->ldg_intrs));
151*3dec9fcdSqs for (i = 0; i < hxgep->ldgvp->ldg_intrs; i++, ldgp++) {
152*3dec9fcdSqs sid.ldg = ldgp->ldg;
153*3dec9fcdSqs sid.vector = ldgp->vector;
154*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
155*3dec9fcdSqs "==> hxge_fzc_intr_sid_set(%d): group %d vector %d",
156*3dec9fcdSqs i, sid.ldg, sid.vector));
157*3dec9fcdSqs rs = hpi_fzc_sid_set(handle, sid);
158*3dec9fcdSqs if (rs != HPI_SUCCESS) {
159*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
160*3dec9fcdSqs "<== hxge_fzc_intr_sid_set:failed 0x%x", rs));
161*3dec9fcdSqs return (HXGE_ERROR | rs);
162*3dec9fcdSqs }
163*3dec9fcdSqs }
164*3dec9fcdSqs
165*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_sid_set"));
166*3dec9fcdSqs return (HXGE_OK);
167*3dec9fcdSqs }
168*3dec9fcdSqs
169*3dec9fcdSqs /*
170*3dec9fcdSqs * Receive DMA registers that are under function zero management.
171*3dec9fcdSqs */
172*3dec9fcdSqs /*ARGSUSED*/
173*3dec9fcdSqs hxge_status_t
hxge_init_fzc_rxdma_channel(p_hxge_t hxgep,uint16_t channel,p_rx_rbr_ring_t rbr_p,p_rx_rcr_ring_t rcr_p,p_rx_mbox_t mbox_p)174*3dec9fcdSqs hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
175*3dec9fcdSqs p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p)
176*3dec9fcdSqs {
177*3dec9fcdSqs hxge_status_t status = HXGE_OK;
178*3dec9fcdSqs
179*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_init_fzc_rxdma_channel"));
180*3dec9fcdSqs
181*3dec9fcdSqs /* Initialize the RXDMA logical pages */
182*3dec9fcdSqs status = hxge_init_fzc_rxdma_channel_pages(hxgep, channel, rbr_p);
183*3dec9fcdSqs if (status != HXGE_OK)
184*3dec9fcdSqs return (status);
185*3dec9fcdSqs
186*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_init_fzc_rxdma_channel"));
187*3dec9fcdSqs return (status);
188*3dec9fcdSqs }
189*3dec9fcdSqs
190*3dec9fcdSqs /*ARGSUSED*/
191*3dec9fcdSqs hxge_status_t
hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep,uint16_t channel,p_rx_rbr_ring_t rbrp)192*3dec9fcdSqs hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep,
193*3dec9fcdSqs uint16_t channel, p_rx_rbr_ring_t rbrp)
194*3dec9fcdSqs {
195*3dec9fcdSqs hpi_handle_t handle;
196*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
197*3dec9fcdSqs
198*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
199*3dec9fcdSqs "==> hxge_init_fzc_rxdma_channel_pages"));
200*3dec9fcdSqs
201*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
202*3dec9fcdSqs
203*3dec9fcdSqs /* Initialize the page handle */
204*3dec9fcdSqs rs = hpi_rxdma_cfg_logical_page_handle(handle, channel,
205*3dec9fcdSqs rbrp->page_hdl.bits.handle);
206*3dec9fcdSqs if (rs != HPI_SUCCESS)
207*3dec9fcdSqs return (HXGE_ERROR | rs);
208*3dec9fcdSqs
209*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
210*3dec9fcdSqs "<== hxge_init_fzc_rxdma_channel_pages"));
211*3dec9fcdSqs return (HXGE_OK);
212*3dec9fcdSqs }
213*3dec9fcdSqs
214*3dec9fcdSqs /*ARGSUSED*/
215*3dec9fcdSqs hxge_status_t
hxge_init_fzc_txdma_channel(p_hxge_t hxgep,uint16_t channel,p_tx_ring_t tx_ring_p,p_tx_mbox_t mbox_p)216*3dec9fcdSqs hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel,
217*3dec9fcdSqs p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p)
218*3dec9fcdSqs {
219*3dec9fcdSqs hxge_status_t status = HXGE_OK;
220*3dec9fcdSqs
221*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_init_fzc_txdma_channel"));
222*3dec9fcdSqs
223*3dec9fcdSqs /* Initialize the TXDMA logical pages */
224*3dec9fcdSqs (void) hxge_init_fzc_txdma_channel_pages(hxgep, channel, tx_ring_p);
225*3dec9fcdSqs
226*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_init_fzc_txdma_channel"));
227*3dec9fcdSqs return (status);
228*3dec9fcdSqs }
229*3dec9fcdSqs
230*3dec9fcdSqs hxge_status_t
hxge_init_fzc_rx_common(p_hxge_t hxgep)231*3dec9fcdSqs hxge_init_fzc_rx_common(p_hxge_t hxgep)
232*3dec9fcdSqs {
233*3dec9fcdSqs hpi_handle_t handle;
234*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
235*3dec9fcdSqs hxge_status_t status = HXGE_OK;
236*3dec9fcdSqs
237*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_init_fzc_rx_common"));
238*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
239*3dec9fcdSqs
240*3dec9fcdSqs /*
241*3dec9fcdSqs * Configure the rxdma clock divider
242*3dec9fcdSqs * This is the granularity counter based on
243*3dec9fcdSqs * the hardware system clock (i.e. 300 Mhz) and
244*3dec9fcdSqs * it is running around 3 nanoseconds.
245*3dec9fcdSqs * So, set the clock divider counter to 1000 to get
246*3dec9fcdSqs * microsecond granularity.
247*3dec9fcdSqs * For example, for a 3 microsecond timeout, the timeout
248*3dec9fcdSqs * will be set to 1.
249*3dec9fcdSqs */
250*3dec9fcdSqs rs = hpi_rxdma_cfg_clock_div_set(handle, RXDMA_CK_DIV_DEFAULT);
251*3dec9fcdSqs if (rs != HPI_SUCCESS)
252*3dec9fcdSqs return (HXGE_ERROR | rs);
253*3dec9fcdSqs
254*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
255*3dec9fcdSqs "<== hxge_init_fzc_rx_common:status 0x%08x", status));
256*3dec9fcdSqs return (status);
257*3dec9fcdSqs }
258*3dec9fcdSqs
259*3dec9fcdSqs hxge_status_t
hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep,uint16_t channel,p_tx_ring_t tx_ring_p)260*3dec9fcdSqs hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, uint16_t channel,
261*3dec9fcdSqs p_tx_ring_t tx_ring_p)
262*3dec9fcdSqs {
263*3dec9fcdSqs hpi_handle_t handle;
264*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
265*3dec9fcdSqs
266*3dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
267*3dec9fcdSqs "==> hxge_init_fzc_txdma_channel_pages"));
268*3dec9fcdSqs
269*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
270*3dec9fcdSqs
271*3dec9fcdSqs /* Initialize the page handle */
272*3dec9fcdSqs rs = hpi_txdma_log_page_handle_set(handle, channel,
273*3dec9fcdSqs &tx_ring_p->page_hdl);
274*3dec9fcdSqs
275*3dec9fcdSqs if (rs == HPI_SUCCESS)
276*3dec9fcdSqs return (HXGE_OK);
277*3dec9fcdSqs else
278*3dec9fcdSqs return (HXGE_ERROR | rs);
279*3dec9fcdSqs }
280*3dec9fcdSqs
281*3dec9fcdSqs hxge_status_t
hxge_fzc_sys_err_mask_set(p_hxge_t hxgep,boolean_t mask)282*3dec9fcdSqs hxge_fzc_sys_err_mask_set(p_hxge_t hxgep, boolean_t mask)
283*3dec9fcdSqs {
284*3dec9fcdSqs hpi_status_t rs = HPI_SUCCESS;
285*3dec9fcdSqs hpi_handle_t handle;
286*3dec9fcdSqs
287*3dec9fcdSqs handle = HXGE_DEV_HPI_HANDLE(hxgep);
288*3dec9fcdSqs rs = hpi_fzc_sys_err_mask_set(handle, mask);
289*3dec9fcdSqs if (rs == HPI_SUCCESS)
290*3dec9fcdSqs return (HXGE_OK);
291*3dec9fcdSqs else
292*3dec9fcdSqs return (HXGE_ERROR | rs);
293*3dec9fcdSqs }
294