13dec9fcdSqs /* 23dec9fcdSqs * CDDL HEADER START 33dec9fcdSqs * 43dec9fcdSqs * The contents of this file are subject to the terms of the 53dec9fcdSqs * Common Development and Distribution License (the "License"). 63dec9fcdSqs * You may not use this file except in compliance with the License. 73dec9fcdSqs * 83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs * See the License for the specific language governing permissions 113dec9fcdSqs * and limitations under the License. 123dec9fcdSqs * 133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs * 193dec9fcdSqs * CDDL HEADER END 203dec9fcdSqs */ 213dec9fcdSqs /* 223dec9fcdSqs * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs * Use is subject to license terms. 243dec9fcdSqs */ 253dec9fcdSqs 263dec9fcdSqs #ifndef _SYS_HXGE_HXGE_DEFS_H 273dec9fcdSqs #define _SYS_HXGE_HXGE_DEFS_H 283dec9fcdSqs 293dec9fcdSqs #ifdef __cplusplus 303dec9fcdSqs extern "C" { 313dec9fcdSqs #endif 323dec9fcdSqs 333dec9fcdSqs #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \ 343dec9fcdSqs !defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) 353dec9fcdSqs #error Host endianness not defined 363dec9fcdSqs #endif 373dec9fcdSqs 383dec9fcdSqs #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \ 393dec9fcdSqs !defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH) 403dec9fcdSqs #error Bit ordering not defined 413dec9fcdSqs #endif 423dec9fcdSqs 433dec9fcdSqs /* RDC/TDC CSR size */ 443dec9fcdSqs #define DMA_CSR_SIZE 2048 453dec9fcdSqs 463dec9fcdSqs /* 473dec9fcdSqs * Define the Default RBR, RCR 483dec9fcdSqs */ 493dec9fcdSqs #define RBR_DEFAULT_MAX_BLKS 4096 /* each entry (16 blockaddr/64B) */ 503dec9fcdSqs #define RBR_NBLK_PER_LINE 16 /* 16 block addresses per 64 B line */ 513dec9fcdSqs #define RBR_DEFAULT_MAX_LEN 65472 /* 2^16 - 64 */ 523dec9fcdSqs #define RBR_DEFAULT_MIN_LEN 64 /* multiple of 64 */ 533dec9fcdSqs 543dec9fcdSqs #define SW_OFFSET_NO_OFFSET 0 553dec9fcdSqs #define SW_OFFSET_64 1 /* 64 bytes */ 563dec9fcdSqs #define SW_OFFSET_128 2 /* 128 bytes */ 573dec9fcdSqs #define SW_OFFSET_INVALID 3 583dec9fcdSqs 593dec9fcdSqs /* 603dec9fcdSqs * RBR block descriptor is 32 bits (bits [43:12] 613dec9fcdSqs */ 623dec9fcdSqs #define RBR_BKADDR_SHIFT 12 633dec9fcdSqs #define RCR_DEFAULT_MAX_BLKS 4096 /* each entry (8 blockaddr/64B) */ 643dec9fcdSqs #define RCR_NBLK_PER_LINE 8 /* 8 block addresses per 64 B line */ 653dec9fcdSqs #define RCR_DEFAULT_MAX_LEN (RCR_DEFAULT_MAX_BLKS) 663dec9fcdSqs #define RCR_DEFAULT_MIN_LEN 32 673dec9fcdSqs 683dec9fcdSqs /* DMA Channels. */ 693dec9fcdSqs #define HXGE_MAX_DMCS (HXGE_MAX_RDCS + HXGE_MAX_TDCS) 703dec9fcdSqs #define HXGE_MAX_RDCS 4 713dec9fcdSqs #define HXGE_MAX_TDCS 4 723dec9fcdSqs 733dec9fcdSqs #define VLAN_ETHERTYPE (0x8100) 743dec9fcdSqs 753dec9fcdSqs /* 256 total, each blade gets 42 */ 763dec9fcdSqs #define TCAM_HXGE_TCAM_MAX_ENTRY 42 773dec9fcdSqs 783dec9fcdSqs /* 793dec9fcdSqs * Locate the DMA channel start offset (PIO_VADDR) 803dec9fcdSqs * (DMA virtual address space of the PIO block) 813dec9fcdSqs */ 823dec9fcdSqs /* TX_RNG_CFIG is not used since we are not using VADDR. */ 833dec9fcdSqs #define TX_RNG_CFIG 0x1000000 843dec9fcdSqs #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) 853dec9fcdSqs #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) 863dec9fcdSqs 873dec9fcdSqs /* 883dec9fcdSqs * PIO access using the DMC block directly (DMC) 893dec9fcdSqs */ 903dec9fcdSqs #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) 913dec9fcdSqs #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) 923dec9fcdSqs 933dec9fcdSqs #ifdef SOLARIS 943dec9fcdSqs #ifndef i386 953dec9fcdSqs #define _BIT_FIELDS_BIG_ENDIAN _BIT_FIELDS_HTOL 963dec9fcdSqs #else 973dec9fcdSqs #define _BIT_FIELDS_LITTLE_ENDIAN _BIT_FIELDS_LTOH 983dec9fcdSqs #endif 993dec9fcdSqs #else 1003dec9fcdSqs #define _BIT_FIELDS_LITTLE_ENDIAN _LITTLE_ENDIAN_BITFIELD 1013dec9fcdSqs #endif 1023dec9fcdSqs 1033dec9fcdSqs /* 1043dec9fcdSqs * The following macros expect unsigned input values. 1053dec9fcdSqs */ 1063dec9fcdSqs #define TXDMA_CHANNEL_VALID(cn) (cn < HXGE_MAX_TDCS) 1073dec9fcdSqs 1083dec9fcdSqs /* 1093dec9fcdSqs * Logical device definitions. 1103dec9fcdSqs */ 1113dec9fcdSqs #define HXGE_INT_MAX_LD 32 1123dec9fcdSqs #define HXGE_INT_MAX_LDG 32 1133dec9fcdSqs 1143dec9fcdSqs #define HXGE_RDMA_LD_START 0 /* 0 - 3 with 4 - 7 reserved */ 1153dec9fcdSqs #define HXGE_TDMA_LD_START 8 /* 8 - 11 with 12 - 15 reserved */ 1163dec9fcdSqs #define HXGE_VMAC_LD 16 1173dec9fcdSqs #define HXGE_PFC_LD 17 1183dec9fcdSqs #define HXGE_NMAC_LD 18 1193dec9fcdSqs #define HXGE_MBOX_LD_START 20 /* 20 - 23 for SW Mbox */ 1203dec9fcdSqs #define HXGE_SYS_ERROR_LD 31 1213dec9fcdSqs 1223dec9fcdSqs #define LDG_VALID(n) (n < HXGE_INT_MAX_LDG) 1233dec9fcdSqs #define LD_VALID(n) (n < HXGE_INT_MAX_LD) 1243dec9fcdSqs #define LD_RXDMA_LD_VALID(n) (n < HXGE_MAX_RDCS) 1253dec9fcdSqs #define LD_TXDMA_LD_VALID(n) (n >= HXGE_MAX_RDCS && \ 1263dec9fcdSqs ((n - HXGE_MAX_RDCS) < HXGE_MAX_TDCS))) 1273dec9fcdSqs 1283dec9fcdSqs #define LD_TIMER_MAX 0x3f 1293dec9fcdSqs #define LD_INTTIMER_VALID(n) (n <= LD_TIMER_MAX) 1303dec9fcdSqs 1313dec9fcdSqs /* System Interrupt Data */ 1323dec9fcdSqs #define SID_VECTOR_MAX 0x1f 1333dec9fcdSqs #define SID_VECTOR_VALID(n) (n <= SID_VECTOR_MAX) 1343dec9fcdSqs 1353dec9fcdSqs #define LD_IM_MASK 0x00000003ULL 1363dec9fcdSqs #define LDGTITMRES_RES_MASK 0x000FFFFFULL 1373dec9fcdSqs 138*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define MIN_FRAME_SIZE 106 /* 68 byte min MTU + 38 byte header */ 139*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define MAX_FRAME_SIZE 9216 140*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define STD_FRAME_SIZE 1522 /* 1518 + 4 = 5EE + 4 */ 141*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_DEFAULT_MTU 1500 142*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* 143*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * sizeof (struct ether_header) + ETHERFCSL + 4 + TX_PKT_HEADER_SIZE 144*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * 12 + 6 + 4 + 16 145*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */ 146*a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define MTU_TO_FRAME_SIZE 38 1473dec9fcdSqs 1483dec9fcdSqs #ifdef __cplusplus 1493dec9fcdSqs } 1503dec9fcdSqs #endif 1513dec9fcdSqs 1523dec9fcdSqs #endif /* _SYS_HXGE_HXGE_DEFS_H */ 153