13dec9fcdSqs /* 23dec9fcdSqs * CDDL HEADER START 33dec9fcdSqs * 43dec9fcdSqs * The contents of this file are subject to the terms of the 53dec9fcdSqs * Common Development and Distribution License (the "License"). 63dec9fcdSqs * You may not use this file except in compliance with the License. 73dec9fcdSqs * 83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs * See the License for the specific language governing permissions 113dec9fcdSqs * and limitations under the License. 123dec9fcdSqs * 133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs * 193dec9fcdSqs * CDDL HEADER END 203dec9fcdSqs */ 213dec9fcdSqs /* 22*1ed83081SMichael Speer * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs * Use is subject to license terms. 243dec9fcdSqs */ 253dec9fcdSqs 263dec9fcdSqs #ifndef _SYS_HXGE_HXGE_H 273dec9fcdSqs #define _SYS_HXGE_HXGE_H 283dec9fcdSqs 293dec9fcdSqs #ifdef __cplusplus 303dec9fcdSqs extern "C" { 313dec9fcdSqs #endif 323dec9fcdSqs 333dec9fcdSqs #include <hxge_vmac.h> 343dec9fcdSqs #include <hxge_pfc.h> 353dec9fcdSqs #include <hxge_classify.h> 363dec9fcdSqs 373dec9fcdSqs /* 383dec9fcdSqs * HXGE diagnostics IOCTLS. 393dec9fcdSqs */ 403dec9fcdSqs #define HXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 413dec9fcdSqs 42*1ed83081SMichael Speer #define HXGE_GET_TX_RING_SZ (HXGE_IOC|1) 43*1ed83081SMichael Speer #define HXGE_GET_TX_DESC (HXGE_IOC|2) 44*1ed83081SMichael Speer #define HXGE_GLOBAL_RESET (HXGE_IOC|3) 45*1ed83081SMichael Speer #define HXGE_TX_SIDE_RESET (HXGE_IOC|4) 46*1ed83081SMichael Speer #define HXGE_RX_SIDE_RESET (HXGE_IOC|5) 47*1ed83081SMichael Speer #define HXGE_RESET_MAC (HXGE_IOC|6) 48*1ed83081SMichael Speer #define HXGE_RTRACE (HXGE_IOC|7) 49*1ed83081SMichael Speer #define HXGE_GET_TCAM (HXGE_IOC|8) 50*1ed83081SMichael Speer #define HXGE_PUT_TCAM (HXGE_IOC|9) 513dec9fcdSqs 523dec9fcdSqs #define HXGE_OK 0 533dec9fcdSqs #define HXGE_ERROR 0x40000000 543dec9fcdSqs #define HXGE_DDI_FAILED 0x20000000 553dec9fcdSqs 563dec9fcdSqs /* 573dec9fcdSqs * Definitions for module_info. 583dec9fcdSqs */ 593dec9fcdSqs #define HXGE_DRIVER_NAME "hxge" /* module name */ 603dec9fcdSqs #define HXGE_CHECK_TIMER (5000) 613dec9fcdSqs 623dec9fcdSqs typedef enum { 633dec9fcdSqs param_instance, 643dec9fcdSqs 653dec9fcdSqs param_accept_jumbo, 663dec9fcdSqs param_rxdma_rbr_size, 673dec9fcdSqs param_rxdma_rcr_size, 683dec9fcdSqs param_rxdma_intr_time, 693dec9fcdSqs param_rxdma_intr_pkts, 703dec9fcdSqs param_vlan_ids, 713dec9fcdSqs param_implicit_vlan_id, 723dec9fcdSqs param_tcam_enable, 733dec9fcdSqs 743dec9fcdSqs param_hash_init_value, 753dec9fcdSqs param_class_cfg_ether_usr1, 763dec9fcdSqs param_class_cfg_ether_usr2, 773dec9fcdSqs param_class_opt_ipv4_tcp, 783dec9fcdSqs param_class_opt_ipv4_udp, 793dec9fcdSqs param_class_opt_ipv4_ah, 803dec9fcdSqs param_class_opt_ipv4_sctp, 813dec9fcdSqs param_class_opt_ipv6_tcp, 823dec9fcdSqs param_class_opt_ipv6_udp, 833dec9fcdSqs param_class_opt_ipv6_ah, 843dec9fcdSqs param_class_opt_ipv6_sctp, 853dec9fcdSqs param_hxge_debug_flag, 863dec9fcdSqs param_hpi_debug_flag, 873dec9fcdSqs param_dump_ptrs, 883dec9fcdSqs param_end 893dec9fcdSqs } hxge_param_index_t; 903dec9fcdSqs 913dec9fcdSqs 923dec9fcdSqs #define HXGE_PARAM_READ 0x00000001ULL 933dec9fcdSqs #define HXGE_PARAM_WRITE 0x00000002ULL 943dec9fcdSqs #define HXGE_PARAM_SHARED 0x00000004ULL 953dec9fcdSqs #define HXGE_PARAM_PRIV 0x00000008ULL 963dec9fcdSqs #define HXGE_PARAM_RW HXGE_PARAM_READ | HXGE_PARAM_WRITE 973dec9fcdSqs #define HXGE_PARAM_RWS HXGE_PARAM_RW | HXGE_PARAM_SHARED 983dec9fcdSqs #define HXGE_PARAM_RWP HXGE_PARAM_RW | HXGE_PARAM_PRIV 993dec9fcdSqs 1003dec9fcdSqs #define HXGE_PARAM_RXDMA 0x00000010ULL 1013dec9fcdSqs #define HXGE_PARAM_TXDMA 0x00000020ULL 1023dec9fcdSqs #define HXGE_PARAM_MAC 0x00000040ULL 1033dec9fcdSqs 1043dec9fcdSqs #define HXGE_PARAM_CMPLX 0x00010000ULL 1053dec9fcdSqs #define HXGE_PARAM_NDD_WR_OK 0x00020000ULL 1063dec9fcdSqs #define HXGE_PARAM_INIT_ONLY 0x00040000ULL 1073dec9fcdSqs #define HXGE_PARAM_INIT_CONFIG 0x00080000ULL 1083dec9fcdSqs 1093dec9fcdSqs #define HXGE_PARAM_READ_PROP 0x00100000ULL 1103dec9fcdSqs #define HXGE_PARAM_PROP_ARR32 0x00200000ULL 1113dec9fcdSqs #define HXGE_PARAM_PROP_ARR64 0x00400000ULL 1123dec9fcdSqs #define HXGE_PARAM_PROP_STR 0x00800000ULL 1133dec9fcdSqs 1143dec9fcdSqs #define HXGE_PARAM_DONT_SHOW 0x80000000ULL 1153dec9fcdSqs 1163dec9fcdSqs #define HXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 1173dec9fcdSqs #define HXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 1183dec9fcdSqs #define HXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 1193dec9fcdSqs #define HXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 1203dec9fcdSqs 1213dec9fcdSqs typedef struct _hxge_param_t { 1223dec9fcdSqs int (*getf)(); 1233dec9fcdSqs int (*setf)(); /* null for read only */ 1243dec9fcdSqs uint64_t type; /* R/W/ Common/Port/ .... */ 1253dec9fcdSqs uint64_t minimum; 1263dec9fcdSqs uint64_t maximum; 1273dec9fcdSqs uint64_t value; /* for array params, pointer to value array */ 1283dec9fcdSqs uint64_t old_value; /* for array params, pointer to old_value array */ 1293dec9fcdSqs char *fcode_name; 1303dec9fcdSqs char *name; 1313dec9fcdSqs } hxge_param_t, *p_hxge_param_t; 1323dec9fcdSqs 1333dec9fcdSqs 1343dec9fcdSqs typedef enum { 1353dec9fcdSqs hxge_lb_normal, 1363dec9fcdSqs hxge_lb_mac10g 1373dec9fcdSqs } hxge_lb_t; 1383dec9fcdSqs 1393dec9fcdSqs enum hxge_mac_state { 1403dec9fcdSqs HXGE_MAC_STOPPED = 0, 1413dec9fcdSqs HXGE_MAC_STARTED 1423dec9fcdSqs }; 1433dec9fcdSqs 1443dec9fcdSqs typedef struct _filter_t { 1453dec9fcdSqs uint32_t all_phys_cnt; 1463dec9fcdSqs uint32_t all_multicast_cnt; 1473dec9fcdSqs uint32_t all_sap_cnt; 1483dec9fcdSqs } filter_t, *p_filter_t; 1493dec9fcdSqs 1503dec9fcdSqs typedef struct _hxge_port_stats_t { 1513dec9fcdSqs hxge_lb_t lb_mode; 1523dec9fcdSqs uint32_t poll_mode; 1533dec9fcdSqs } hxge_port_stats_t, *p_hxge_port_stats_t; 1543dec9fcdSqs 1553dec9fcdSqs 1563dec9fcdSqs typedef struct _hxge_peu_sys_stats { 1573dec9fcdSqs uint32_t spc_acc_err; 1583dec9fcdSqs uint32_t tdc_pioacc_err; 1593dec9fcdSqs uint32_t rdc_pioacc_err; 1603dec9fcdSqs uint32_t pfc_pioacc_err; 1613dec9fcdSqs uint32_t vmac_pioacc_err; 1623dec9fcdSqs uint32_t cpl_hdrq_parerr; 1633dec9fcdSqs uint32_t cpl_dataq_parerr; 1643dec9fcdSqs uint32_t retryram_xdlh_parerr; 1653dec9fcdSqs uint32_t retrysotram_xdlh_parerr; 1663dec9fcdSqs uint32_t p_hdrq_parerr; 1673dec9fcdSqs uint32_t p_dataq_parerr; 1683dec9fcdSqs uint32_t np_hdrq_parerr; 1693dec9fcdSqs uint32_t np_dataq_parerr; 1703dec9fcdSqs uint32_t eic_msix_parerr; 1713dec9fcdSqs uint32_t hcr_parerr; 1723dec9fcdSqs } hxge_peu_sys_stats_t, *p_hxge_peu_sys_stats_t; 1733dec9fcdSqs 1743dec9fcdSqs 1753dec9fcdSqs typedef struct _hxge_stats_t { 1763dec9fcdSqs /* 1773dec9fcdSqs * Overall structure size 1783dec9fcdSqs */ 1793dec9fcdSqs size_t stats_size; 1803dec9fcdSqs 1813dec9fcdSqs kstat_t *ksp; 1823dec9fcdSqs kstat_t *rdc_ksp[HXGE_MAX_RDCS]; 1833dec9fcdSqs kstat_t *tdc_ksp[HXGE_MAX_TDCS]; 1843dec9fcdSqs kstat_t *rdc_sys_ksp; 1853dec9fcdSqs kstat_t *tdc_sys_ksp; 1863dec9fcdSqs kstat_t *pfc_ksp; 1873dec9fcdSqs kstat_t *vmac_ksp; 1883dec9fcdSqs kstat_t *port_ksp; 1893dec9fcdSqs kstat_t *mmac_ksp; 1903dec9fcdSqs kstat_t *peu_sys_ksp; 1913dec9fcdSqs 1923dec9fcdSqs hxge_mac_stats_t mac_stats; 1933dec9fcdSqs hxge_vmac_stats_t vmac_stats; /* VMAC Statistics */ 1943dec9fcdSqs 1953dec9fcdSqs hxge_rx_ring_stats_t rdc_stats[HXGE_MAX_RDCS]; /* per rdc stats */ 1963dec9fcdSqs hxge_rdc_sys_stats_t rdc_sys_stats; /* RDC system stats */ 1973dec9fcdSqs 1983dec9fcdSqs hxge_tx_ring_stats_t tdc_stats[HXGE_MAX_TDCS]; /* per tdc stats */ 1993dec9fcdSqs hxge_tdc_sys_stats_t tdc_sys_stats; /* TDC system stats */ 2003dec9fcdSqs 2013dec9fcdSqs hxge_pfc_stats_t pfc_stats; /* pfc stats */ 2023dec9fcdSqs hxge_port_stats_t port_stats; /* port stats */ 2033dec9fcdSqs 2043dec9fcdSqs hxge_peu_sys_stats_t peu_sys_stats; /* PEU system stats */ 2053dec9fcdSqs } hxge_stats_t, *p_hxge_stats_t; 2063dec9fcdSqs 2073dec9fcdSqs typedef struct _hxge_intr_t { 2083dec9fcdSqs boolean_t intr_registered; /* interrupts are registered */ 2093dec9fcdSqs boolean_t intr_enabled; /* interrupts are enabled */ 2103dec9fcdSqs boolean_t niu_msi_enable; /* debug or configurable? */ 2113dec9fcdSqs uint8_t nldevs; /* # of logical devices */ 2123dec9fcdSqs int intr_types; /* interrupt types supported */ 2133dec9fcdSqs int intr_type; /* interrupt type to add */ 2143dec9fcdSqs int msi_intx_cnt; /* # msi/intx ints returned */ 2153dec9fcdSqs int intr_added; /* # ints actually needed */ 2163dec9fcdSqs int intr_cap; /* interrupt capabilities */ 2173dec9fcdSqs size_t intr_size; /* size of array to allocate */ 2183dec9fcdSqs ddi_intr_handle_t *htable; /* For array of interrupts */ 2193dec9fcdSqs /* Add interrupt number for each interrupt vector */ 2203dec9fcdSqs int pri; 2213dec9fcdSqs } hxge_intr_t, *p_hxge_intr_t; 2223dec9fcdSqs 2233dec9fcdSqs typedef struct _hxge_ldgv_t { 2243dec9fcdSqs uint8_t ndma_ldvs; 2253dec9fcdSqs uint8_t nldvs; 2263dec9fcdSqs uint8_t start_ldg; 2273dec9fcdSqs uint8_t maxldgs; 2283dec9fcdSqs uint8_t maxldvs; 2293dec9fcdSqs uint8_t ldg_intrs; 2303dec9fcdSqs uint32_t tmres; 2313dec9fcdSqs p_hxge_ldg_t ldgp; 2323dec9fcdSqs p_hxge_ldv_t ldvp; 2333dec9fcdSqs p_hxge_ldv_t ldvp_syserr; 2343dec9fcdSqs } hxge_ldgv_t, *p_hxge_ldgv_t; 2353dec9fcdSqs 236a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States typedef struct _hxge_timeout { 237a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States timeout_id_t id; 238a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States clock_t ticks; 239a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States kmutex_t lock; 240a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint32_t link_status; 241e5d97391SQiyan Sun - Sun Microsystems - San Diego United States boolean_t report_link_status; 242a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } hxge_timeout; 243a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 244*1ed83081SMichael Speer typedef struct _hxge_addr { 245*1ed83081SMichael Speer boolean_t set; 246*1ed83081SMichael Speer boolean_t primary; 247*1ed83081SMichael Speer uint8_t addr[ETHERADDRL]; 248*1ed83081SMichael Speer } hxge_addr_t; 249*1ed83081SMichael Speer 250*1ed83081SMichael Speer #define HXGE_MAX_MAC_ADDRS 16 251*1ed83081SMichael Speer 252*1ed83081SMichael Speer typedef struct _hxge_mmac { 253*1ed83081SMichael Speer uint8_t total; 254*1ed83081SMichael Speer uint8_t available; 255*1ed83081SMichael Speer hxge_addr_t addrs[HXGE_MAX_MAC_ADDRS]; 256*1ed83081SMichael Speer } hxge_mmac_t; 257*1ed83081SMichael Speer 258*1ed83081SMichael Speer /* 259*1ed83081SMichael Speer * Ring Group Strucuture. 260*1ed83081SMichael Speer */ 261*1ed83081SMichael Speer #define HXGE_MAX_RX_GROUPS 1 262*1ed83081SMichael Speer 263*1ed83081SMichael Speer typedef struct _hxge_rx_ring_group_t { 264*1ed83081SMichael Speer mac_ring_type_t type; 265*1ed83081SMichael Speer mac_group_handle_t ghandle; 266*1ed83081SMichael Speer struct _hxge_t *hxgep; 267*1ed83081SMichael Speer int index; 268*1ed83081SMichael Speer boolean_t started; 269*1ed83081SMichael Speer } hxge_ring_group_t; 270*1ed83081SMichael Speer 271*1ed83081SMichael Speer /* 272*1ed83081SMichael Speer * Ring Handle 273*1ed83081SMichael Speer */ 274*1ed83081SMichael Speer typedef struct _hxge_ring_handle_t { 275*1ed83081SMichael Speer struct _hxge_t *hxgep; 276*1ed83081SMichael Speer int index; /* port-wise */ 277*1ed83081SMichael Speer mac_ring_handle_t ring_handle; 278*1ed83081SMichael Speer boolean_t started; 279*1ed83081SMichael Speer } hxge_ring_handle_t; 280*1ed83081SMichael Speer 281*1ed83081SMichael Speer typedef hxge_ring_handle_t *p_hxge_ring_handle_t; 282*1ed83081SMichael Speer 2833dec9fcdSqs /* 2843dec9fcdSqs * Hydra Device instance state information. 2853dec9fcdSqs * Each instance is dynamically allocated on first attach. 2863dec9fcdSqs */ 2873dec9fcdSqs struct _hxge_t { 2883dec9fcdSqs dev_info_t *dip; /* device instance */ 2893dec9fcdSqs dev_info_t *p_dip; /* Parent's device instance */ 2903dec9fcdSqs int instance; /* instance number */ 2913dec9fcdSqs uint32_t drv_state; /* driver state bit flags */ 2923dec9fcdSqs uint64_t hxge_debug_level; /* driver state bit flags */ 2933dec9fcdSqs kmutex_t genlock[1]; 2943dec9fcdSqs enum hxge_mac_state hxge_mac_state; 2953dec9fcdSqs 2963dec9fcdSqs p_dev_regs_t dev_regs; 2973dec9fcdSqs hpi_handle_t hpi_handle; 2983dec9fcdSqs hpi_handle_t hpi_pci_handle; 2993dec9fcdSqs hpi_handle_t hpi_reg_handle; 3003dec9fcdSqs hpi_handle_t hpi_msi_handle; 3013dec9fcdSqs 3023dec9fcdSqs hxge_vmac_t vmac; 3033dec9fcdSqs hxge_classify_t classifier; 3043dec9fcdSqs 3053dec9fcdSqs mac_handle_t mach; /* mac module handle */ 3063dec9fcdSqs 3073dec9fcdSqs p_hxge_stats_t statsp; 3083dec9fcdSqs uint32_t param_count; 3093dec9fcdSqs p_hxge_param_t param_arr; 3103dec9fcdSqs hxge_hw_list_t *hxge_hw_p; /* pointer to per Hydra */ 3113dec9fcdSqs uint8_t nrdc; 3123dec9fcdSqs uint8_t rdc[HXGE_MAX_RDCS]; 313676f0400SMichael Speer boolean_t rdc_first_intr[HXGE_MAX_RDCS]; 3143dec9fcdSqs uint8_t ntdc; 3153dec9fcdSqs uint8_t tdc[HXGE_MAX_TDCS]; 3163dec9fcdSqs 317*1ed83081SMichael Speer hxge_ring_handle_t tx_ring_handles[HXGE_MAX_TDCS]; 318*1ed83081SMichael Speer hxge_ring_handle_t rx_ring_handles[HXGE_MAX_RDCS]; 319*1ed83081SMichael Speer hxge_ring_group_t rx_groups[HXGE_MAX_RX_GROUPS]; 320*1ed83081SMichael Speer 3213dec9fcdSqs hxge_intr_t hxge_intr_type; 3223dec9fcdSqs hxge_dma_pt_cfg_t pt_config; 3233dec9fcdSqs hxge_class_pt_cfg_t class_config; 3243dec9fcdSqs 3253dec9fcdSqs /* Logical device and group data structures. */ 3263dec9fcdSqs p_hxge_ldgv_t ldgvp; 3273dec9fcdSqs 3283dec9fcdSqs caddr_t param_list; /* Parameter list */ 3293dec9fcdSqs 3303dec9fcdSqs ether_addr_st factaddr; /* factory mac address */ 3313dec9fcdSqs ether_addr_st ouraddr; /* individual address */ 3323dec9fcdSqs kmutex_t ouraddr_lock; /* lock to protect to uradd */ 333*1ed83081SMichael Speer hxge_mmac_t mmac; 3343dec9fcdSqs 3353dec9fcdSqs ddi_iblock_cookie_t interrupt_cookie; 3363dec9fcdSqs 3373dec9fcdSqs /* 3383dec9fcdSqs * Blocks of memory may be pre-allocated by the 3393dec9fcdSqs * partition manager or the driver. They may include 3403dec9fcdSqs * blocks for configuration and buffers. The idea is 3413dec9fcdSqs * to preallocate big blocks of contiguous areas in 3423dec9fcdSqs * system memory (i.e. with IOMMU). These blocks then 3433dec9fcdSqs * will be broken up to a fixed number of blocks with 3443dec9fcdSqs * each block having the same block size (4K, 8K, 16K or 3453dec9fcdSqs * 32K) in the case of buffer blocks. For systems that 3463dec9fcdSqs * do not support DVMA, more than one big block will be 3473dec9fcdSqs * allocated. 3483dec9fcdSqs */ 3493dec9fcdSqs uint32_t rx_default_block_size; 3503dec9fcdSqs hxge_rx_block_size_t rx_bksize_code; 3513dec9fcdSqs 3523dec9fcdSqs p_hxge_dma_pool_t rx_buf_pool_p; 3538ad8db65SMichael Speer p_hxge_dma_pool_t rx_rbr_cntl_pool_p; 3548ad8db65SMichael Speer p_hxge_dma_pool_t rx_rcr_cntl_pool_p; 3558ad8db65SMichael Speer p_hxge_dma_pool_t rx_mbox_cntl_pool_p; 3563dec9fcdSqs 3573dec9fcdSqs p_hxge_dma_pool_t tx_buf_pool_p; 3583dec9fcdSqs p_hxge_dma_pool_t tx_cntl_pool_p; 3593dec9fcdSqs 3603dec9fcdSqs /* Receive buffer block ring and completion ring. */ 3613dec9fcdSqs p_rx_rbr_rings_t rx_rbr_rings; 3623dec9fcdSqs p_rx_rcr_rings_t rx_rcr_rings; 3633dec9fcdSqs p_rx_mbox_areas_t rx_mbox_areas_p; 3643dec9fcdSqs 3653dec9fcdSqs uint32_t start_rdc; 3663dec9fcdSqs uint32_t max_rdcs; 3673dec9fcdSqs 3683dec9fcdSqs /* Transmit descriptors rings */ 3693dec9fcdSqs p_tx_rings_t tx_rings; 3703dec9fcdSqs p_tx_mbox_areas_t tx_mbox_areas_p; 3713dec9fcdSqs 3723dec9fcdSqs uint32_t start_tdc; 3733dec9fcdSqs uint32_t max_tdcs; 3743dec9fcdSqs uint32_t tdc_mask; 3753dec9fcdSqs 3763dec9fcdSqs ddi_dma_handle_t dmasparehandle; 3773dec9fcdSqs 3783dec9fcdSqs ulong_t sys_page_sz; 3793dec9fcdSqs ulong_t sys_page_mask; 3803dec9fcdSqs int suspended; 3813dec9fcdSqs 3823dec9fcdSqs filter_t filter; /* Current instance filter */ 3833dec9fcdSqs p_hash_filter_t hash_filter; /* Multicast hash filter. */ 3843dec9fcdSqs krwlock_t filter_lock; /* Lock to protect filters. */ 3853dec9fcdSqs 3863dec9fcdSqs ulong_t sys_burst_sz; 3873dec9fcdSqs timeout_id_t hxge_timerid; 3883dec9fcdSqs uint8_t msg_min; 3893dec9fcdSqs 3903dec9fcdSqs uint16_t intr_timeout; 3913dec9fcdSqs uint16_t intr_threshold; 3923dec9fcdSqs 3933dec9fcdSqs rtrace_t rtrace; 3943dec9fcdSqs int fm_capabilities; /* FMA capabilities */ 3953dec9fcdSqs 3963dec9fcdSqs uint32_t hxge_port_rbr_size; 3973dec9fcdSqs uint32_t hxge_port_rcr_size; 3983dec9fcdSqs uint32_t hxge_port_tx_ring_size; 399fe930412Sqs 400fe930412Sqs kmutex_t pio_lock; 401a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_timeout timeout; 4021c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States 4031c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States int msix_count; 40457c5371aSQiyan Sun - Sun Microsystems - San Diego United States int msix_index; 40557c5371aSQiyan Sun - Sun Microsystems - San Diego United States uint32_t msix_table[32][3]; 40657c5371aSQiyan Sun - Sun Microsystems - San Diego United States uint32_t msix_table_check[1][3]; 4073dec9fcdSqs }; 4083dec9fcdSqs 4093dec9fcdSqs /* 4103dec9fcdSqs * Driver state flags. 4113dec9fcdSqs */ 4123dec9fcdSqs #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 4133dec9fcdSqs #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 4143dec9fcdSqs #define STATE_NODE_CREATED 0x000000004 /* device node created */ 4153dec9fcdSqs #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 4163dec9fcdSqs #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 4173dec9fcdSqs 4183dec9fcdSqs typedef struct _hxge_port_kstat_t { 4193dec9fcdSqs /* 4203dec9fcdSqs * Transciever state informations. 4213dec9fcdSqs */ 4223dec9fcdSqs kstat_named_t cap_autoneg; 4233dec9fcdSqs kstat_named_t cap_10gfdx; 4243dec9fcdSqs 4253dec9fcdSqs /* 4263dec9fcdSqs * Link partner capabilities. 4273dec9fcdSqs */ 4283dec9fcdSqs kstat_named_t lp_cap_autoneg; 4293dec9fcdSqs kstat_named_t lp_cap_10gfdx; 4303dec9fcdSqs 4313dec9fcdSqs /* 4323dec9fcdSqs * Shared link setup. 4333dec9fcdSqs */ 4343dec9fcdSqs kstat_named_t link_speed; 4353dec9fcdSqs kstat_named_t link_duplex; 4363dec9fcdSqs kstat_named_t link_up; 4373dec9fcdSqs 4383dec9fcdSqs /* 4393dec9fcdSqs * Lets the user know the MTU currently in use by 4403dec9fcdSqs * the physical MAC port. 4413dec9fcdSqs */ 4423dec9fcdSqs kstat_named_t lb_mode; 4433dec9fcdSqs 4443dec9fcdSqs kstat_named_t tx_max_pend; 4453dec9fcdSqs kstat_named_t rx_jumbo_pkts; 4463dec9fcdSqs 4473dec9fcdSqs /* 4483dec9fcdSqs * Misc MAC statistics. 4493dec9fcdSqs */ 4503dec9fcdSqs kstat_named_t ifspeed; 4513dec9fcdSqs kstat_named_t promisc; 4523dec9fcdSqs } hxge_port_kstat_t, *p_hxge_port_kstat_t; 4533dec9fcdSqs 4543dec9fcdSqs typedef struct _hxge_rdc_kstat { 4553dec9fcdSqs /* 4563dec9fcdSqs * Receive DMA channel statistics. 4573dec9fcdSqs * This structure needs to be consistent with hxge_rdc_stat_index_t 4583dec9fcdSqs * in hxge_kstat.c 4593dec9fcdSqs */ 4603dec9fcdSqs kstat_named_t ipackets; 4613dec9fcdSqs kstat_named_t rbytes; 4623dec9fcdSqs kstat_named_t errors; 4633dec9fcdSqs kstat_named_t jumbo_pkts; 4643dec9fcdSqs 4653dec9fcdSqs kstat_named_t rcr_unknown_err; 4663dec9fcdSqs kstat_named_t rcr_sha_par_err; 4673dec9fcdSqs kstat_named_t rbr_pre_par_err; 4683dec9fcdSqs kstat_named_t rbr_pre_emty; 4693dec9fcdSqs 4703dec9fcdSqs kstat_named_t rcr_shadow_full; 4713dec9fcdSqs kstat_named_t rbr_tmout; 4723dec9fcdSqs kstat_named_t peu_resp_err; 4733dec9fcdSqs 4743dec9fcdSqs kstat_named_t ctrl_fifo_ecc_err; 4753dec9fcdSqs kstat_named_t data_fifo_ecc_err; 4763dec9fcdSqs 4773dec9fcdSqs kstat_named_t rcrfull; 4783dec9fcdSqs kstat_named_t rbr_empty; 479b83cd2c3SMichael Speer kstat_named_t rbr_empty_fail; 4801c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States kstat_named_t rbr_empty_restore; 4813dec9fcdSqs kstat_named_t rbrfull; 4828ad8db65SMichael Speer kstat_named_t rcr_invalids; /* Account for invalid RCR entries. */ 4833dec9fcdSqs 4843dec9fcdSqs kstat_named_t rcr_to; 4853dec9fcdSqs kstat_named_t rcr_thresh; 486fd9489ceSQiyan Sun - Sun Microsystems - San Diego United States kstat_named_t pkt_drop; 4873dec9fcdSqs } hxge_rdc_kstat_t, *p_hxge_rdc_kstat_t; 4883dec9fcdSqs 4893dec9fcdSqs typedef struct _hxge_rdc_sys_kstat { 4903dec9fcdSqs /* 4913dec9fcdSqs * Receive DMA system statistics. 4923dec9fcdSqs * This structure needs to be consistent with hxge_rdc_sys_stat_idx_t 4933dec9fcdSqs * in hxge_kstat.c 4943dec9fcdSqs */ 4953dec9fcdSqs kstat_named_t ctrl_fifo_sec; 4963dec9fcdSqs kstat_named_t ctrl_fifo_ded; 4973dec9fcdSqs kstat_named_t data_fifo_sec; 4983dec9fcdSqs kstat_named_t data_fifo_ded; 4993dec9fcdSqs } hxge_rdc_sys_kstat_t, *p_hxge_rdc_sys_kstat_t; 5003dec9fcdSqs 5013dec9fcdSqs typedef struct _hxge_tdc_kstat { 5023dec9fcdSqs /* 5033dec9fcdSqs * Transmit DMA channel statistics. 5043dec9fcdSqs * This structure needs to be consistent with hxge_tdc_stats_index_t 5053dec9fcdSqs * in hxge_kstat.c 5063dec9fcdSqs */ 5073dec9fcdSqs kstat_named_t opackets; 5083dec9fcdSqs kstat_named_t obytes; 5093dec9fcdSqs kstat_named_t obytes_with_pad; 5103dec9fcdSqs kstat_named_t oerrors; 5113dec9fcdSqs kstat_named_t tx_inits; 5123dec9fcdSqs kstat_named_t tx_no_buf; 5133dec9fcdSqs 5143dec9fcdSqs kstat_named_t peu_resp_err; 5153dec9fcdSqs kstat_named_t pkt_size_err; 5163dec9fcdSqs kstat_named_t tx_rng_oflow; 5173dec9fcdSqs kstat_named_t pkt_size_hdr_err; 5183dec9fcdSqs kstat_named_t runt_pkt_drop_err; 5193dec9fcdSqs kstat_named_t pref_par_err; 5203dec9fcdSqs kstat_named_t tdr_pref_cpl_to; 5213dec9fcdSqs kstat_named_t pkt_cpl_to; 5223dec9fcdSqs kstat_named_t invalid_sop; 5233dec9fcdSqs kstat_named_t unexpected_sop; 5243dec9fcdSqs 5253dec9fcdSqs kstat_named_t count_hdr_size_err; 5263dec9fcdSqs kstat_named_t count_runt; 5273dec9fcdSqs kstat_named_t count_abort; 5283dec9fcdSqs 5293dec9fcdSqs kstat_named_t tx_starts; 5303dec9fcdSqs kstat_named_t tx_no_desc; 5313dec9fcdSqs kstat_named_t tx_dma_bind_fail; 5323dec9fcdSqs kstat_named_t tx_hdr_pkts; 5333dec9fcdSqs kstat_named_t tx_ddi_pkts; 5343dec9fcdSqs kstat_named_t tx_jumbo_pkts; 5353dec9fcdSqs kstat_named_t tx_max_pend; 5363dec9fcdSqs kstat_named_t tx_marks; 5373dec9fcdSqs } hxge_tdc_kstat_t, *p_hxge_tdc_kstat_t; 5383dec9fcdSqs 5393dec9fcdSqs typedef struct _hxge_tdc_sys_kstat { 5403dec9fcdSqs /* 5413dec9fcdSqs * Transmit DMA system statistics. 5423dec9fcdSqs * This structure needs to be consistent with hxge_tdc_sys_stat_idx_t 5433dec9fcdSqs * in hxge_kstat.c 5443dec9fcdSqs */ 5453dec9fcdSqs kstat_named_t reord_tbl_par_err; 5463dec9fcdSqs kstat_named_t reord_buf_ded_err; 5473dec9fcdSqs kstat_named_t reord_buf_sec_err; 5483dec9fcdSqs } hxge_tdc_sys_kstat_t, *p_hxge_tdc_sys_kstat_t; 5493dec9fcdSqs 5503dec9fcdSqs typedef struct _hxge_vmac_kstat { 5513dec9fcdSqs /* 5523dec9fcdSqs * VMAC statistics. 5533dec9fcdSqs * This structure needs to be consistent with hxge_vmac_stat_index_t 5543dec9fcdSqs * in hxge_kstat.c 5553dec9fcdSqs */ 5563dec9fcdSqs kstat_named_t tx_frame_cnt; 5573dec9fcdSqs kstat_named_t tx_byte_cnt; 5583dec9fcdSqs 5593dec9fcdSqs kstat_named_t rx_frame_cnt; 5603dec9fcdSqs kstat_named_t rx_byte_cnt; 5613dec9fcdSqs kstat_named_t rx_drop_frame_cnt; 5623dec9fcdSqs kstat_named_t rx_drop_byte_cnt; 5633dec9fcdSqs kstat_named_t rx_crc_cnt; 5643dec9fcdSqs kstat_named_t rx_pause_cnt; 5653dec9fcdSqs kstat_named_t rx_bcast_fr_cnt; 5663dec9fcdSqs kstat_named_t rx_mcast_fr_cnt; 5673dec9fcdSqs } hxge_vmac_kstat_t, *p_hxge_vmac_kstat_t; 5683dec9fcdSqs 5693dec9fcdSqs typedef struct _hxge_pfc_kstat { 5703dec9fcdSqs /* 5713dec9fcdSqs * This structure needs to be consistent with hxge_pfc_stat_index_t 5723dec9fcdSqs * in hxge_kstat.c 5733dec9fcdSqs */ 5743dec9fcdSqs kstat_named_t pfc_pkt_drop; 5753dec9fcdSqs kstat_named_t pfc_tcam_parity_err; 5763dec9fcdSqs kstat_named_t pfc_vlan_parity_err; 5773dec9fcdSqs kstat_named_t pfc_bad_cs_count; 5783dec9fcdSqs kstat_named_t pfc_drop_count; 5793dec9fcdSqs kstat_named_t pfc_tcp_ctrl_drop; 5803dec9fcdSqs kstat_named_t pfc_l2_addr_drop; 5813dec9fcdSqs kstat_named_t pfc_class_code_drop; 5823dec9fcdSqs kstat_named_t pfc_tcam_drop; 5833dec9fcdSqs kstat_named_t pfc_vlan_drop; 5843dec9fcdSqs } hxge_pfc_kstat_t, *p_hxge_pfc_kstat_t; 5853dec9fcdSqs 5863dec9fcdSqs typedef struct _hxge_mmac_kstat { 5873dec9fcdSqs /* 5883dec9fcdSqs * This structure needs to be consistent with hxge_mmac_stat_index_t 5893dec9fcdSqs * in hxge_kstat.c 5903dec9fcdSqs */ 5913dec9fcdSqs kstat_named_t mmac_max_addr_cnt; 5923dec9fcdSqs kstat_named_t mmac_avail_addr_cnt; 5933dec9fcdSqs kstat_named_t mmac_addr1; 5943dec9fcdSqs kstat_named_t mmac_addr2; 5953dec9fcdSqs kstat_named_t mmac_addr3; 5963dec9fcdSqs kstat_named_t mmac_addr4; 5973dec9fcdSqs kstat_named_t mmac_addr5; 5983dec9fcdSqs kstat_named_t mmac_addr6; 5993dec9fcdSqs kstat_named_t mmac_addr7; 6003dec9fcdSqs kstat_named_t mmac_addr8; 6013dec9fcdSqs kstat_named_t mmac_addr9; 6023dec9fcdSqs kstat_named_t mmac_addr10; 6033dec9fcdSqs kstat_named_t mmac_addr11; 6043dec9fcdSqs kstat_named_t mmac_addr12; 6053dec9fcdSqs kstat_named_t mmac_addr13; 6063dec9fcdSqs kstat_named_t mmac_addr14; 6073dec9fcdSqs kstat_named_t mmac_addr15; 6083dec9fcdSqs kstat_named_t mmac_addr16; 6093dec9fcdSqs } hxge_mmac_kstat_t, *p_hxge_mmac_kstat_t; 6103dec9fcdSqs 6113dec9fcdSqs typedef struct _hxge_peu_sys_kstat { 6123dec9fcdSqs /* 6133dec9fcdSqs * This structure needs to be consistent with hxge_peu_sys_stat_idx_t 6143dec9fcdSqs * in hxge_kstat.c 6153dec9fcdSqs */ 6163dec9fcdSqs kstat_named_t spc_acc_err; 6173dec9fcdSqs kstat_named_t tdc_pioacc_err; 6183dec9fcdSqs kstat_named_t rdc_pioacc_err; 6193dec9fcdSqs kstat_named_t pfc_pioacc_err; 6203dec9fcdSqs kstat_named_t vmac_pioacc_err; 6213dec9fcdSqs kstat_named_t cpl_hdrq_parerr; 6223dec9fcdSqs kstat_named_t cpl_dataq_parerr; 6233dec9fcdSqs kstat_named_t retryram_xdlh_parerr; 6243dec9fcdSqs kstat_named_t retrysotram_xdlh_parerr; 6253dec9fcdSqs kstat_named_t p_hdrq_parerr; 6263dec9fcdSqs kstat_named_t p_dataq_parerr; 6273dec9fcdSqs kstat_named_t np_hdrq_parerr; 6283dec9fcdSqs kstat_named_t np_dataq_parerr; 6293dec9fcdSqs kstat_named_t eic_msix_parerr; 6303dec9fcdSqs kstat_named_t hcr_parerr; 6313dec9fcdSqs } hxge_peu_sys_kstat_t, *p_hxge_peu_sys_kstat_t; 6323dec9fcdSqs 6333dec9fcdSqs /* 6343dec9fcdSqs * Prototype definitions. 6353dec9fcdSqs */ 6363dec9fcdSqs hxge_status_t hxge_init(p_hxge_t); 6373dec9fcdSqs void hxge_uninit(p_hxge_t); 6383dec9fcdSqs 6393dec9fcdSqs typedef void (*fptrv_t)(); 6403dec9fcdSqs timeout_id_t hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec); 6413dec9fcdSqs void hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid); 6423dec9fcdSqs 6433dec9fcdSqs #ifdef __cplusplus 6443dec9fcdSqs } 6453dec9fcdSqs #endif 6463dec9fcdSqs 6473dec9fcdSqs #endif /* _SYS_HXGE_HXGE_H */ 648