13dec9fcdSqs /* 23dec9fcdSqs * CDDL HEADER START 33dec9fcdSqs * 43dec9fcdSqs * The contents of this file are subject to the terms of the 53dec9fcdSqs * Common Development and Distribution License (the "License"). 63dec9fcdSqs * You may not use this file except in compliance with the License. 73dec9fcdSqs * 83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 103dec9fcdSqs * See the License for the specific language governing permissions 113dec9fcdSqs * and limitations under the License. 123dec9fcdSqs * 133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 183dec9fcdSqs * 193dec9fcdSqs * CDDL HEADER END 203dec9fcdSqs */ 213dec9fcdSqs /* 223dec9fcdSqs * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 233dec9fcdSqs * Use is subject to license terms. 243dec9fcdSqs */ 253dec9fcdSqs 263dec9fcdSqs #ifndef _HPI_TXDMA_H 273dec9fcdSqs #define _HPI_TXDMA_H 283dec9fcdSqs 293dec9fcdSqs #ifdef __cplusplus 303dec9fcdSqs extern "C" { 313dec9fcdSqs #endif 323dec9fcdSqs 333dec9fcdSqs #include <hpi.h> 343dec9fcdSqs #include <hxge_txdma_hw.h> 353dec9fcdSqs #include <hxge_tdc_hw.h> 363dec9fcdSqs 373dec9fcdSqs typedef enum _txdma_cs_cntl_e { 383dec9fcdSqs TXDMA_INIT_RESET = 0x1, 393dec9fcdSqs TXDMA_INIT_START = 0x2, 403dec9fcdSqs TXDMA_START = 0x3, 413dec9fcdSqs TXDMA_RESET = 0x4, 423dec9fcdSqs TXDMA_STOP = 0x5, 433dec9fcdSqs TXDMA_MBOX_ENABLE = 0x6 443dec9fcdSqs } txdma_cs_cntl_t; 453dec9fcdSqs 463dec9fcdSqs #define HXGE_TXDMA_OFFSET(x, v, channel) (x + \ 473dec9fcdSqs (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel))) 483dec9fcdSqs /* 493dec9fcdSqs * PIO macros to read and write the transmit registers. 503dec9fcdSqs */ 513dec9fcdSqs #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ 523dec9fcdSqs HXGE_REG_RD64(handle, \ 533dec9fcdSqs (HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p) 543dec9fcdSqs 553dec9fcdSqs #define TXDMA_REG_WRITE64(handle, reg, channel, data) \ 563dec9fcdSqs HXGE_REG_WR64(handle, \ 573dec9fcdSqs HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data) 583dec9fcdSqs 593dec9fcdSqs #define HPI_TXDMA_GATHER_INDEX(index) \ 603dec9fcdSqs ((index <= TX_MAX_GATHER_POINTERS)) ? HPI_SUCCESS : \ 613dec9fcdSqs (HPI_TXDMA_GATHER_INVALID) 623dec9fcdSqs 633dec9fcdSqs /* 643dec9fcdSqs * Transmit HPI error codes 653dec9fcdSqs */ 663dec9fcdSqs #define TXDMA_ER_ST (TXDMA_BLK_ID << HPI_BLOCK_ID_SHIFT) 673dec9fcdSqs #define TXDMA_ID_SHIFT(n) (n << HPI_PORT_CHAN_SHIFT) 683dec9fcdSqs 693dec9fcdSqs #define TXDMA_HW_STOP_FAILED (HPI_BK_HW_ER_START | 0x1) 703dec9fcdSqs #define TXDMA_HW_RESUME_FAILED (HPI_BK_HW_ER_START | 0x2) 713dec9fcdSqs 723dec9fcdSqs #define TXDMA_GATHER_INVALID (HPI_BK_ERROR_START | 0x1) 733dec9fcdSqs #define TXDMA_XFER_LEN_INVALID (HPI_BK_ERROR_START | 0x2) 743dec9fcdSqs 753dec9fcdSqs #define HPI_TXDMA_OPCODE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 763dec9fcdSqs TXDMA_ER_ST | OPCODE_INVALID) 773dec9fcdSqs 783dec9fcdSqs #define HPI_TXDMA_FUNC_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 793dec9fcdSqs TXDMA_ER_ST | PORT_INVALID) 803dec9fcdSqs #define HPI_TXDMA_CHANNEL_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 813dec9fcdSqs TXDMA_ER_ST | CHANNEL_INVALID) 823dec9fcdSqs 833dec9fcdSqs #define HPI_TXDMA_PAGE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 843dec9fcdSqs TXDMA_ER_ST | LOGICAL_PAGE_INVALID) 853dec9fcdSqs 863dec9fcdSqs #define HPI_TXDMA_REGISTER_INVALID (TXDMA_ER_ST | REGISTER_INVALID) 873dec9fcdSqs #define HPI_TXDMA_COUNTER_INVALID (TXDMA_ER_ST | COUNTER_INVALID) 883dec9fcdSqs #define HPI_TXDMA_CONFIG_INVALID (TXDMA_ER_ST | CONFIG_INVALID) 893dec9fcdSqs 903dec9fcdSqs 913dec9fcdSqs #define HPI_TXDMA_GATHER_INVALID (TXDMA_ER_ST | TXDMA_GATHER_INVALID) 923dec9fcdSqs #define HPI_TXDMA_XFER_LEN_INVALID (TXDMA_ER_ST | TXDMA_XFER_LEN_INVALID) 933dec9fcdSqs 943dec9fcdSqs #define HPI_TXDMA_RESET_FAILED (TXDMA_ER_ST | RESET_FAILED) 953dec9fcdSqs #define HPI_TXDMA_STOP_FAILED (TXDMA_ER_ST | TXDMA_HW_STOP_FAILED) 963dec9fcdSqs #define HPI_TXDMA_RESUME_FAILED (TXDMA_ER_ST | TXDMA_HW_RESUME_FAILED) 973dec9fcdSqs 983dec9fcdSqs /* 993dec9fcdSqs * Transmit DMA Channel HPI Prototypes. 1003dec9fcdSqs */ 1013dec9fcdSqs hpi_status_t hpi_txdma_log_page_handle_set(hpi_handle_t handle, 1023dec9fcdSqs uint8_t channel, tdc_page_handle_t *hdl_p); 1033dec9fcdSqs hpi_status_t hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel); 1043dec9fcdSqs hpi_status_t hpi_txdma_channel_init_enable(hpi_handle_t handle, 1053dec9fcdSqs uint8_t channel); 1063dec9fcdSqs hpi_status_t hpi_txdma_channel_enable(hpi_handle_t handle, uint8_t channel); 1073dec9fcdSqs hpi_status_t hpi_txdma_channel_disable(hpi_handle_t handle, uint8_t channel); 1083dec9fcdSqs hpi_status_t hpi_txdma_channel_mbox_enable(hpi_handle_t handle, 1093dec9fcdSqs uint8_t channel); 1103dec9fcdSqs hpi_status_t hpi_txdma_channel_control(hpi_handle_t handle, 1113dec9fcdSqs txdma_cs_cntl_t control, uint8_t channel); 1123dec9fcdSqs hpi_status_t hpi_txdma_control_status(hpi_handle_t handle, io_op_t op_mode, 1133dec9fcdSqs uint8_t channel, tdc_stat_t *cs_p); 1143dec9fcdSqs 1153dec9fcdSqs hpi_status_t hpi_txdma_event_mask(hpi_handle_t handle, io_op_t op_mode, 1163dec9fcdSqs uint8_t channel, tdc_int_mask_t *mask_p); 1173dec9fcdSqs 1183dec9fcdSqs hpi_status_t hpi_txdma_ring_config(hpi_handle_t handle, io_op_t op_mode, 1193dec9fcdSqs uint8_t channel, uint64_t *reg_data); 1203dec9fcdSqs hpi_status_t hpi_txdma_mbox_config(hpi_handle_t handle, io_op_t op_mode, 1213dec9fcdSqs uint8_t channel, uint64_t *mbox_addr); 1223dec9fcdSqs hpi_status_t hpi_txdma_desc_gather_set(hpi_handle_t handle, 1233dec9fcdSqs p_tx_desc_t desc_p, uint8_t gather_index, 1243dec9fcdSqs boolean_t mark, uint8_t ngathers, 1253dec9fcdSqs uint64_t dma_ioaddr, uint32_t transfer_len); 126*fe930412Sqs hpi_status_t hpi_txdma_control_stop_wait(hpi_handle_t handle, 127*fe930412Sqs uint8_t channel); 1283dec9fcdSqs 1293dec9fcdSqs hpi_status_t hpi_txdma_desc_set_xfer_len(hpi_handle_t handle, 1303dec9fcdSqs p_tx_desc_t desc_p, uint32_t transfer_len); 1313dec9fcdSqs 1323dec9fcdSqs hpi_status_t hpi_txdma_desc_set_zero(hpi_handle_t handle, uint16_t entries); 1333dec9fcdSqs hpi_status_t hpi_txdma_ring_head_get(hpi_handle_t handle, uint8_t channel, 1343dec9fcdSqs tdc_tdr_head_t *hdl_p); 1353dec9fcdSqs void hpi_txdma_dump_desc_one(hpi_handle_t handle, p_tx_desc_t desc_p, 1363dec9fcdSqs int desc_index); 1373dec9fcdSqs 1383dec9fcdSqs #ifdef __cplusplus 1393dec9fcdSqs } 1403dec9fcdSqs #endif 1413dec9fcdSqs 1423dec9fcdSqs #endif /* _HPI_TXDMA_H */ 143