17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 585025c03Sgd * Common Development and Distribution License (the "License"). 685025c03Sgd * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*7a92e70fSZeeshanul Huq - Sun Microsystems - Beijing China * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. 237c478bd9Sstevel@tonic-gate */ 247c478bd9Sstevel@tonic-gate 250219346bSGarrett D'Amore #ifndef HME_MAC_H 260219346bSGarrett D'Amore #define HME_MAC_H 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate /* 297c478bd9Sstevel@tonic-gate * HOST MEMORY DATA STRUCTURES 307c478bd9Sstevel@tonic-gate */ 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate /* The pointers to the Descriptor Ring base Addresses must be 2K-byte aligned */ 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate #define HME_HMDALIGN (2048) 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate /* 377c478bd9Sstevel@tonic-gate * The transmit and receiver Descriptor Rings are organized as "wrap-around 387c478bd9Sstevel@tonic-gate * descriptors of programmable size. 397c478bd9Sstevel@tonic-gate */ 400219346bSGarrett D'Amore #define HME_TMDMAX (64) /* Transmit descriptor ring size */ 410219346bSGarrett D'Amore #define HME_RMDMAX (64) /* Receive descriptor ring size */ 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate /* Transmit descriptor structure */ 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate struct hme_tmd { 467c478bd9Sstevel@tonic-gate uint_t tmd_flags; /* OWN, SOP, EOP, cksum ctl and bufize */ 477c478bd9Sstevel@tonic-gate uint_t tmd_addr; /* 8-bye aligned buffer address */ 487c478bd9Sstevel@tonic-gate }; 497c478bd9Sstevel@tonic-gate 507c478bd9Sstevel@tonic-gate /* fields in the tmd_flags */ 517c478bd9Sstevel@tonic-gate 527c478bd9Sstevel@tonic-gate #define HMETMD_BUFSIZE (0x3fff << 0) /* 0-13 : Tx Data buffer size */ 537c478bd9Sstevel@tonic-gate #define HMETMD_CSSTART (0x3f << 14) /* 14-19 : Checksum start offset */ 547c478bd9Sstevel@tonic-gate #define HMETMD_CSSTUFF (0xff << 20) /* 20-27 : Checksum stuff offset */ 557c478bd9Sstevel@tonic-gate #define HMETMD_CSENABL (1 << 28) /* 28 : Enable checksum computation */ 567c478bd9Sstevel@tonic-gate #define HMETMD_EOP (1 << 29) /* 29 : End Of Packet flag */ 577c478bd9Sstevel@tonic-gate #define HMETMD_SOP (1 << 30) /* 30 : Start Of Packet flag */ 587c478bd9Sstevel@tonic-gate #define HMETMD_OWN (0x80000000) /* 31 : Ownership flag */ 597c478bd9Sstevel@tonic-gate /* 0 - owned by software */ 607c478bd9Sstevel@tonic-gate /* 1 - owned by hardware */ 617c478bd9Sstevel@tonic-gate 62*7a92e70fSZeeshanul Huq - Sun Microsystems - Beijing China #define HMETMD_CSSTART_MAX 0x3f /* Maximum checksum start offset */ 63*7a92e70fSZeeshanul Huq - Sun Microsystems - Beijing China #define HMETMD_CSSTUFF_MAX 0xff /* Maximum checksum stuff offset */ 647c478bd9Sstevel@tonic-gate #define HMETMD_CSSTART_SHIFT 14 /* checksum start bit position */ 657c478bd9Sstevel@tonic-gate #define HMETMD_CSSTUFF_SHIFT 20 /* checksum stuff bit position */ 667c478bd9Sstevel@tonic-gate 677c478bd9Sstevel@tonic-gate /* 687c478bd9Sstevel@tonic-gate * Programming Notes: 697c478bd9Sstevel@tonic-gate * 707c478bd9Sstevel@tonic-gate * 1. If a packet occupies more than one descriptor, the software must 717c478bd9Sstevel@tonic-gate * turn over the ownership of the descriptors to the hardware 727c478bd9Sstevel@tonic-gate * "last-to-first", in order to avoid race conditions. 737c478bd9Sstevel@tonic-gate * 747c478bd9Sstevel@tonic-gate * 2. If a packet resides in more than one buffer, the Checksum_Enable, 757c478bd9Sstevel@tonic-gate * Checksum_Stuff_Offset and Checksum_Start_Offset fields must have the 767c478bd9Sstevel@tonic-gate * same values in all the descriptors that were allocated to the packet. 777c478bd9Sstevel@tonic-gate * 787c478bd9Sstevel@tonic-gate * 3. The hardware implementation relies on the fact that if a buffer 797c478bd9Sstevel@tonic-gate * starts at an "odd" boundary, the DMA state machine can "rewind" 807c478bd9Sstevel@tonic-gate * to the nearest burst boundary and execute a full DVMA burst Read. 817c478bd9Sstevel@tonic-gate * 827c478bd9Sstevel@tonic-gate * There is no other alignment restriction for the transmit data buffer. 837c478bd9Sstevel@tonic-gate */ 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate /* Receive Descriptor structure */ 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate struct hme_rmd { 887c478bd9Sstevel@tonic-gate uint_t rmd_flags; /* OWN, OVFLOW, buf/data size, cksum */ 897c478bd9Sstevel@tonic-gate uint_t rmd_addr; /* 8-byte aligned buffer address */ 907c478bd9Sstevel@tonic-gate }; 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate /* fields in the rmd_flags */ 937c478bd9Sstevel@tonic-gate 947c478bd9Sstevel@tonic-gate #define HMERMD_CKSUM (0xffff << 0) /* 0-15 : checksum computed */ 957c478bd9Sstevel@tonic-gate #define HMERMD_BUFSIZE (0x3fff << 16) /* 16-29 : buffer/data size */ 967c478bd9Sstevel@tonic-gate #define HMERMD_OVFLOW (1 << 30) /* 30 : Rx buffer overflow */ 977c478bd9Sstevel@tonic-gate #define HMERMD_OWN (0x80000000) /* 31 : Ownership flag */ 987c478bd9Sstevel@tonic-gate /* 0 - owned by software */ 997c478bd9Sstevel@tonic-gate /* 1 - owned by hardware */ 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate #define HMERMD_BUFSIZE_SHIFT 16 /* buffer/data size bit position */ 1027c478bd9Sstevel@tonic-gate 1037c478bd9Sstevel@tonic-gate /* ************************************************************************* */ 1047c478bd9Sstevel@tonic-gate 1057c478bd9Sstevel@tonic-gate /* Global Register set in SEB (Shared Ethernet Block) */ 1067c478bd9Sstevel@tonic-gate 1077c478bd9Sstevel@tonic-gate struct hme_global { 1087c478bd9Sstevel@tonic-gate uint_t reset; /* Global Software Reset Command */ 1097c478bd9Sstevel@tonic-gate uint_t config; /* Global Configuration Register */ 1107c478bd9Sstevel@tonic-gate uint_t reserved[62]; 1117c478bd9Sstevel@tonic-gate uint_t status; /* Global Status Register */ 1127c478bd9Sstevel@tonic-gate uint_t intmask; /* Global Interrupt Mask Register */ 1137c478bd9Sstevel@tonic-gate }; 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate 1167c478bd9Sstevel@tonic-gate /* 1177c478bd9Sstevel@tonic-gate * Global Software Reset Command Register - RW 1187c478bd9Sstevel@tonic-gate * These bits become "self cleared" after the corresponding reset command 1197c478bd9Sstevel@tonic-gate * has been executed. After a reset, the software must poll this register 1207c478bd9Sstevel@tonic-gate * till both the bits are read as 0's. 1217c478bd9Sstevel@tonic-gate */ 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate #define HMEG_RESET_ETX (1 << 0) /* Reset ETX */ 1247c478bd9Sstevel@tonic-gate #define HMEG_RESET_ERX (1 << 1) /* Reset ERX */ 1257c478bd9Sstevel@tonic-gate 1267c478bd9Sstevel@tonic-gate #define HMEG_RESET_GLOBAL HMEG_RESET_ETX | HMEG_RESET_ERX 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate 1297c478bd9Sstevel@tonic-gate /* Global Configuration Register - RW */ 1307c478bd9Sstevel@tonic-gate 1317c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_BURSTSZ (0x3 << 0) /* sbus max burst size */ 1327c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_64BIT_XFER (1 << 2) /* Extended transfer mode */ 1337c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_PARITY (1 << 3) /* sbus parity enable */ 1347c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_RES1 (1 << 4) /* reserved, should be 0 */ 1357c478bd9Sstevel@tonic-gate 1367c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_BURST16 0x00 /* sbus max burst size 16 */ 1377c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_BURST32 0x01 /* sbus max burst size 32 */ 1387c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_BURST64 0x02 /* sbus max burst size 64 */ 1397c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_BURST_RES 0x03 /* sbus max burst size - reserved */ 1407c478bd9Sstevel@tonic-gate 1417c478bd9Sstevel@tonic-gate #define HMEG_CONFIG_64BIT_SHIFT 2 1427c478bd9Sstevel@tonic-gate /* 1437c478bd9Sstevel@tonic-gate * Global Status Register - R-AC 1447c478bd9Sstevel@tonic-gate * 1457c478bd9Sstevel@tonic-gate * All the bits in the Global Status Register are automatically cleared when 1467c478bd9Sstevel@tonic-gate * read with the exception of bit 23. The MIF status bit will be cleared after 1477c478bd9Sstevel@tonic-gate * the MIF Status Register is read. 1487c478bd9Sstevel@tonic-gate */ 1497c478bd9Sstevel@tonic-gate 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate #define HMEG_STATUS_FRAME_RCVD (1 << 0) /* from RX_MAC to RxFIFO */ 1527c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RXF_CNT_EXP (1 << 1) /* Rx_frame_counter expired */ 1537c478bd9Sstevel@tonic-gate #define HMEG_STATUS_ALN_CNT_EXP (1 << 2) /* Alignment_Error_cntr exp */ 1547c478bd9Sstevel@tonic-gate #define HMEG_STATUS_CRC_CNT_EXP (1 << 3) /* CRC_Error_counter expired */ 1557c478bd9Sstevel@tonic-gate #define HMEG_STATUS_LEN_CNT_EXP (1 << 4) /* Length_Error_counter exp */ 1567c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RXFIFO_OVFL (1 << 5) /* RxFIFO_Overflow in RX_MAC */ 1577c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RCV_CNT_EXP (1 << 6) /* Code_Violation_counter exp */ 1587c478bd9Sstevel@tonic-gate #define HMEG_STATUS_SQE_TST_ERR (1 << 7) /* SQE Test error in XIF */ 1597c478bd9Sstevel@tonic-gate 1607c478bd9Sstevel@tonic-gate #define HMEG_STATUS_FRAME_SENT (1 << 8) /* Frame sent from TX_MAC */ 1617c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TXFIFO_UNDR (1 << 9) /* TxFIFO Underrun in TX_MAC */ 1627c478bd9Sstevel@tonic-gate #define HMEG_STATUS_MXPKTSZ_ERR (1 << 10) /* Maximum_Packet_Size error */ 1637c478bd9Sstevel@tonic-gate #define HMEG_STATUS_NRMCOLC_EXP (1 << 11) /* Normal_collision_cntr exp */ 1647c478bd9Sstevel@tonic-gate #define HMEG_STATUS_EXCOLC_EXP (1 << 12) /* Excessive_coll_cntr exp */ 1657c478bd9Sstevel@tonic-gate #define HMEG_STATUS_LATCOLC_EXP (1 << 13) /* Late_Collision_cntr exp */ 1667c478bd9Sstevel@tonic-gate #define HMEG_STATUS_FSTCOLC_EXP (1 << 14) /* First_Coll_cntr expired */ 1677c478bd9Sstevel@tonic-gate #define HMEG_STATUS_DEFTIMR_EXP (1 << 15) /* Defer_Timer expired */ 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RINT (1 << 16) /* from RxFIFO to host memory */ 1707c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RX_DROP (1 << 17) /* No free Rx descriptors */ 1717c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */ 1727c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */ 1737c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */ 1747c478bd9Sstevel@tonic-gate #define HMEG_STATUS_RX_TAG_ERR (1 << 21) /* No two consecutiv tag bits */ 1757c478bd9Sstevel@tonic-gate #define HMEG_STATUS_EOP_ERR (1 << 22) /* EOP not set in Tx desc */ 1767c478bd9Sstevel@tonic-gate #define HMEG_STATUS_MIF_INTR (1 << 23) /* MIF interrupt */ 1777c478bd9Sstevel@tonic-gate 1787c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TINT (1 << 24) /* from host mem to TxFIFO */ 1797c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TX_ALL (1 << 25) /* TxFIFO empty */ 1807c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TX_ERR_ACK (1 << 26) /* Error Ack in Tx DMA cycle */ 1817c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TX_LATE_ERR (1 << 27) /* Late error in Tx DMA cycle */ 1827c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TX_PAR_ERR (1 << 28) /* Parity error in Tx DMA */ 1837c478bd9Sstevel@tonic-gate #define HMEG_STATUS_TX_TAG_ERR (1 << 29) /* No two consecutiv tag bits */ 1847c478bd9Sstevel@tonic-gate #define HMEG_STATUS_SLV_ERR_ACK (1 << 30) /* Error Ack in PIO cycle */ 1857c478bd9Sstevel@tonic-gate #define HMEG_STATUS_SLV_PAR_ERR (0x80000000) /* Parity error in PIO write */ 1867c478bd9Sstevel@tonic-gate 1877c478bd9Sstevel@tonic-gate #define HMEG_STATUS_FATAL_ERR 0xfc7c0000 /* all fatal errors */ 1887c478bd9Sstevel@tonic-gate #define HMEG_STATUS_NONFATAL_ERR 0x0002fefc /* all non-fatal errors */ 1897c478bd9Sstevel@tonic-gate #define HMEG_STATUS_NORMAL_INT 0x01810000 /* normal interrupts */ 1907c478bd9Sstevel@tonic-gate 1917c478bd9Sstevel@tonic-gate #define HMEG_STATUS_INTR 0xfefffefc /* All interesting interrupts */ 1927c478bd9Sstevel@tonic-gate 1937c478bd9Sstevel@tonic-gate /* 1947c478bd9Sstevel@tonic-gate * Global Interrupt Mask register 1957c478bd9Sstevel@tonic-gate * 1967c478bd9Sstevel@tonic-gate * There is one-to-one correspondence between the bits in this register and 1977c478bd9Sstevel@tonic-gate * the Global Status register. 1987c478bd9Sstevel@tonic-gate * 1997c478bd9Sstevel@tonic-gate * The MIF interrupt [bit 23] is not maskable here. It should be masked at the 2007c478bd9Sstevel@tonic-gate * source of the interrupt in the MIF. 2017c478bd9Sstevel@tonic-gate * 2027c478bd9Sstevel@tonic-gate * Default value of the Global Interrupt Mask register is 0xFF7FFFFF. 2037c478bd9Sstevel@tonic-gate */ 2047c478bd9Sstevel@tonic-gate 2057c478bd9Sstevel@tonic-gate #define HMEG_MASK_FRAME_RCVD (1 << 0) /* from RX_MAC to RxFIFO */ 2067c478bd9Sstevel@tonic-gate #define HMEG_MASK_RXF_CNT_EXP (1 << 1) /* Rx_frame_counter expired */ 2077c478bd9Sstevel@tonic-gate #define HMEG_MASK_ALN_CNT_EXP (1 << 2) /* Alignment_Error_cntr exp */ 2087c478bd9Sstevel@tonic-gate #define HMEG_MASK_CRC_CNT_EXP (1 << 3) /* CRC_Error_counter expired */ 2097c478bd9Sstevel@tonic-gate #define HMEG_MASK_LEN_CNT_EXP (1 << 4) /* Length_Error_counter exp */ 2107c478bd9Sstevel@tonic-gate #define HMEG_MASK_RXFIFO_OVFL (1 << 5) /* RxFIFO_Overflow in RX_MAC */ 2117c478bd9Sstevel@tonic-gate #define HMEG_MASK_RCV_CNT_EXP (1 << 6) /* Code_Violation_counter exp */ 2127c478bd9Sstevel@tonic-gate #define HMEG_MASK_SQE_TST_ERR (1 << 7) /* SQE Test error in XIF */ 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate #define HMEG_MASK_FRAME_SENT (1 << 8) /* Frame sent from TX_MAC */ 2157c478bd9Sstevel@tonic-gate #define HMEG_MASK_TXFIFO_UNDR (1 << 9) /* TxFIFO Underrun in TX_MAC */ 2167c478bd9Sstevel@tonic-gate #define HMEG_MASK_MXPKTSZ_ERR (1 << 10) /* Maximum_Packet_Size error */ 2177c478bd9Sstevel@tonic-gate #define HMEG_MASK_NRMCOLC_EXP (1 << 11) /* Normal_collision_cntr exp */ 2187c478bd9Sstevel@tonic-gate #define HMEG_MASK_EXECOLC_EXP (1 << 12) /* Excessive_coll_cntr exp */ 2197c478bd9Sstevel@tonic-gate #define HMEG_MASK_LATCOLC_EXP (1 << 13) /* Late_Collision_cntr exp */ 2207c478bd9Sstevel@tonic-gate #define HMEG_MASK_FSTCOLC_EXP (1 << 14) /* First_Coll_cntr expired */ 2217c478bd9Sstevel@tonic-gate #define HMEG_MASK_DEFTIMR_EXP (1 << 15) /* Defer_Timer expired */ 2227c478bd9Sstevel@tonic-gate 2237c478bd9Sstevel@tonic-gate #define HMEG_MASK_RINT (1 << 16) /* from RxFIFO to host memory */ 2247c478bd9Sstevel@tonic-gate #define HMEG_MASK_RX_DROP (1 << 17) /* No free Rx descriptors */ 2257c478bd9Sstevel@tonic-gate #define HMEG_MASK_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */ 2267c478bd9Sstevel@tonic-gate #define HMEG_MASK_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */ 2277c478bd9Sstevel@tonic-gate #define HMEG_MASK_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */ 2287c478bd9Sstevel@tonic-gate #define HMEG_MASK_RX_TAG_ERR (1 << 21) /* No two consecutiv tag bits */ 2297c478bd9Sstevel@tonic-gate #define HMEG_MASK_EOP_ERR (1 << 22) /* EOP not set in Tx desc */ 2307c478bd9Sstevel@tonic-gate #define HMEG_MASK_MIF_INTR (1 << 23) /* MIF interrupt */ 2317c478bd9Sstevel@tonic-gate 2327c478bd9Sstevel@tonic-gate #define HMEG_MASK_TINT (1 << 24) /* from host mem to TxFIFO */ 2337c478bd9Sstevel@tonic-gate #define HMEG_MASK_TX_ALL (1 << 25) /* TxFIFO empty */ 2347c478bd9Sstevel@tonic-gate #define HMEG_MASK_TX_ERR_ACK (1 << 26) /* Error Ack in Tx DMA cycle */ 2357c478bd9Sstevel@tonic-gate #define HMEG_MASK_TX_LATE_ERR (1 << 27) /* Late error in Tx DMA cycle */ 2367c478bd9Sstevel@tonic-gate #define HMEG_MASK_TX_PAR_ERR (1 << 28) /* Parity error in Tx DMA */ 2377c478bd9Sstevel@tonic-gate #define HMEG_MASK_TX_TAG_ERR (1 << 29) /* No two consecutiv tag bits */ 2387c478bd9Sstevel@tonic-gate #define HMEG_MASK_SLV_ERR_ACK (1 << 30) /* Error Ack in PIO cycle */ 2397c478bd9Sstevel@tonic-gate #define HMEG_MASK_SLV_PAR_ERR (0x80000000) /* Parity error in PIO write */ 2407c478bd9Sstevel@tonic-gate 2417c478bd9Sstevel@tonic-gate #define HMEG_MASK_INTR (~HMEG_STATUS_INTR) 2427c478bd9Sstevel@tonic-gate /* uninteresting interrupts */ 2437c478bd9Sstevel@tonic-gate 2447c478bd9Sstevel@tonic-gate /* 2457c478bd9Sstevel@tonic-gate * Interrupts which are not interesting are: 2467c478bd9Sstevel@tonic-gate * HMEG_MASK_FRAME_SENT 2477c478bd9Sstevel@tonic-gate * HMEG_MASK_RXF_CNT_EXP 2487c478bd9Sstevel@tonic-gate * HMEG_MASK_FRAME_RCVD 2497c478bd9Sstevel@tonic-gate */ 2507c478bd9Sstevel@tonic-gate 2517c478bd9Sstevel@tonic-gate /* ************************************************************************* */ 2527c478bd9Sstevel@tonic-gate 2537c478bd9Sstevel@tonic-gate /* ETX Register set */ 2547c478bd9Sstevel@tonic-gate 2557c478bd9Sstevel@tonic-gate struct hme_etx { 2567c478bd9Sstevel@tonic-gate uint_t txpend; /* Transmit Pending Command */ 2577c478bd9Sstevel@tonic-gate uint_t config; /* ETX Configuration Register */ 2587c478bd9Sstevel@tonic-gate uint_t txring; /* Transmit Descriptor Ring Pointer */ 2597c478bd9Sstevel@tonic-gate uint_t txbuf_base; /* Transmit Data Buffer Base Address */ 2607c478bd9Sstevel@tonic-gate uint_t txbuf_disp; /* Transmit Data Buffer Displacement */ 2617c478bd9Sstevel@tonic-gate uint_t txfifo_wr_ptr; /* TxFIFO Write Pointer */ 2627c478bd9Sstevel@tonic-gate uint_t txfifo_sdwr_ptr; /* TxFIFO Shadow Write Pointer */ 2637c478bd9Sstevel@tonic-gate uint_t txfifo_rd_ptr; /* TxFIFO Read pointer */ 2647c478bd9Sstevel@tonic-gate uint_t txfifo_sdrd_ptr; /* TxFIFO Shadow Read pointer */ 2657c478bd9Sstevel@tonic-gate uint_t txfifo_pkt_cnt; /* TxFIFO Packet Counter */ 2667c478bd9Sstevel@tonic-gate uint_t state_mach; /* ETX State Machine Register */ 2677c478bd9Sstevel@tonic-gate uint_t txring_size; /* Descriptor Ring Size */ 2687c478bd9Sstevel@tonic-gate uint_t txbuf_ptr; /* Transmit Data Buffer Pointer */ 2697c478bd9Sstevel@tonic-gate }; 2707c478bd9Sstevel@tonic-gate 2717c478bd9Sstevel@tonic-gate /* 2727c478bd9Sstevel@tonic-gate * ETX Transmit Pending Command Register - RW 2737c478bd9Sstevel@tonic-gate * This 1-bit command must be issued by the software for every packet that the 2747c478bd9Sstevel@tonic-gate * driver posts to the hardware. 2757c478bd9Sstevel@tonic-gate * This bit becomes "self-cleared" after the command is executed. 2767c478bd9Sstevel@tonic-gate */ 2777c478bd9Sstevel@tonic-gate 2787c478bd9Sstevel@tonic-gate #define HMET_TXPEND_TDMD (1 << 0) /* wake up Tx DMA engine */ 2797c478bd9Sstevel@tonic-gate 2807c478bd9Sstevel@tonic-gate /* 2817c478bd9Sstevel@tonic-gate * ETX Configuration Register 2827c478bd9Sstevel@tonic-gate * If the desire is to buffer an entire standard Ethernet frame before its 2837c478bd9Sstevel@tonic-gate * transmission is enabled, the Tx-FIFO-Threshold field has to be proframmed 2847c478bd9Sstevel@tonic-gate * to "0x1ff". 2857c478bd9Sstevel@tonic-gate * The default value for the register is 0x3fe. 2867c478bd9Sstevel@tonic-gate * Bit 10 is used to modify the functionality of the Tx_All interrupt. 2877c478bd9Sstevel@tonic-gate * If it is 0, Tx_All interrupt is generated after processing the last 2887c478bd9Sstevel@tonic-gate * transmit descriptor with the OWN bit set. This only implies that the 2897c478bd9Sstevel@tonic-gate * data has been copied to the FIFO. 2907c478bd9Sstevel@tonic-gate * If it is 1, Tx_All interrupt is generated only after the entire 2917c478bd9Sstevel@tonic-gate * Transmit FIFO has been drained. 2927c478bd9Sstevel@tonic-gate */ 2937c478bd9Sstevel@tonic-gate 2947c478bd9Sstevel@tonic-gate #define HMET_CONFIG_TXDMA_EN (1 << 0) /* Enable Tx DMA */ 2957c478bd9Sstevel@tonic-gate #define HMET_CONFIG_TXFIFOTH (0x1ff << 1) /* 1-9 : TX FIFO Threshold */ 2967c478bd9Sstevel@tonic-gate #define HMET_CONFIG_DRAIN_INT (1 << 10) /* TX_all_int modifier */ 2977c478bd9Sstevel@tonic-gate 2987c478bd9Sstevel@tonic-gate /* 2997c478bd9Sstevel@tonic-gate * Transmit Descriptor Pointer 3007c478bd9Sstevel@tonic-gate * 3017c478bd9Sstevel@tonic-gate * This 29-bit register points to the next descriptor in the ring. The 21 most 3027c478bd9Sstevel@tonic-gate * significant bits are used as the base address for the desriptor ring, 3037c478bd9Sstevel@tonic-gate * and the 8 least significant bits are used as a displacement for the current 3047c478bd9Sstevel@tonic-gate * descriptor. 3057c478bd9Sstevel@tonic-gate * 3067c478bd9Sstevel@tonic-gate * This register should be initialized to a 2KByte-aligned value after power-on 3077c478bd9Sstevel@tonic-gate * or Software Reset. 3087c478bd9Sstevel@tonic-gate * 3097c478bd9Sstevel@tonic-gate */ 3107c478bd9Sstevel@tonic-gate 3117c478bd9Sstevel@tonic-gate /* 3127c478bd9Sstevel@tonic-gate * ETX TX ring size register 3137c478bd9Sstevel@tonic-gate * This is a 4-bit register to determine the no. of descriptor entries in the 3147c478bd9Sstevel@tonic-gate * TX-ring. The number of entries can vary from 16 through 256 in increments of 3157c478bd9Sstevel@tonic-gate * 16. 3167c478bd9Sstevel@tonic-gate */ 3177c478bd9Sstevel@tonic-gate 3187c478bd9Sstevel@tonic-gate #define HMET_RINGSZ_SHIFT 4 3197c478bd9Sstevel@tonic-gate 3207c478bd9Sstevel@tonic-gate /* ************************************************************************* */ 3217c478bd9Sstevel@tonic-gate 3227c478bd9Sstevel@tonic-gate /* ERX Register Set */ 3237c478bd9Sstevel@tonic-gate 3247c478bd9Sstevel@tonic-gate struct hme_erx { 3257c478bd9Sstevel@tonic-gate uint_t config; /* ERX Configuration Register */ 3267c478bd9Sstevel@tonic-gate uint_t rxring; /* Receive Descriptor Ring Pointer */ 3277c478bd9Sstevel@tonic-gate uint_t rxbuf_ptr; /* Receive Data Buffer Pointer */ 3287c478bd9Sstevel@tonic-gate uint_t rxfifo_wr_ptr; /* RxFIFO Write Pointer */ 3297c478bd9Sstevel@tonic-gate uint_t rxfifo_sdwr_ptr; /* RxFIFO Shadow Write Pointer */ 3307c478bd9Sstevel@tonic-gate uint_t rxfifo_rd_ptr; /* RxFIFO Read pointer */ 3317c478bd9Sstevel@tonic-gate uint_t rxfifo_pkt_cnt; /* RxFIFO Packet Counter */ 3327c478bd9Sstevel@tonic-gate uint_t state_mach; /* ERX State Machine Register */ 3337c478bd9Sstevel@tonic-gate }; 3347c478bd9Sstevel@tonic-gate 3357c478bd9Sstevel@tonic-gate /* 3367c478bd9Sstevel@tonic-gate * ERX Configuration Register - RW 3377c478bd9Sstevel@tonic-gate * This 23-bit register determines the ERX-specific parameters that control the 3387c478bd9Sstevel@tonic-gate * operation of the receive DMA channel. 3397c478bd9Sstevel@tonic-gate */ 3407c478bd9Sstevel@tonic-gate 3417c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RXDMA_EN (1 << 0) /* 0 : Enable Rx DMA */ 3427c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RES1 (0x3 << 1) /* 1,2 : reserverd */ 3437c478bd9Sstevel@tonic-gate #define HMER_CONFIG_FBOFFSET (0x7 << 3) /* 3-5 : First Byte Offset */ 3447c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RES2 (0x7 << 6) /* 6-8 : reserverd */ 3457c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RXRINGSZ (0x3 << 9) /* 9,10 : RX desc. ring size */ 3467c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RES3 (0x1f << 11) /* 11-15 : reserverd */ 3477c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RX_CSSTART (0x7f << 16) /* 16-22 : cksum start offset */ 3487c478bd9Sstevel@tonic-gate 3497c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RXRINGSZ32 (0x0 << 9) /* Rx descr. ring size 32 */ 3507c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RXRINGSZ64 (0x1 << 9) /* Rx descr. ring size 64 */ 3517c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RXRINGSZ128 (0x2 << 9) /* Rx descr. ring size 128 */ 3527c478bd9Sstevel@tonic-gate #define HMER_CONFIG_RXRINGSZ256 (0x3 << 9) /* Rx descr. ring size 256 */ 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate #define HMER_CONFIG_FBO_SHIFT 3 3557c478bd9Sstevel@tonic-gate #define HMER_RXRINGSZ_SHIFT 9 35685025c03Sgd #define HMER_RX_CSSTART_SHIFT 16 3577c478bd9Sstevel@tonic-gate 3587c478bd9Sstevel@tonic-gate /* 3597c478bd9Sstevel@tonic-gate * Receive Descriptor Pointer 3607c478bd9Sstevel@tonic-gate * 3617c478bd9Sstevel@tonic-gate * This 29-bit register points to the next descriptor in the ring. The 21 most 3627c478bd9Sstevel@tonic-gate * significant bits are used as the base address for the desriptor ring, 3637c478bd9Sstevel@tonic-gate * and the 8 least significant bits are used as a displacement for the current 3647c478bd9Sstevel@tonic-gate * descriptor. 3657c478bd9Sstevel@tonic-gate * 3667c478bd9Sstevel@tonic-gate * This register should be initialized to a 2KByte-aligned value after power-on 3677c478bd9Sstevel@tonic-gate * or Software Reset. 3687c478bd9Sstevel@tonic-gate * 3697c478bd9Sstevel@tonic-gate */ 3707c478bd9Sstevel@tonic-gate 3717c478bd9Sstevel@tonic-gate /* ************************************************************************* */ 3727c478bd9Sstevel@tonic-gate 3737c478bd9Sstevel@tonic-gate 3747c478bd9Sstevel@tonic-gate 3757c478bd9Sstevel@tonic-gate /* 3767c478bd9Sstevel@tonic-gate * Declarations and definitions specific to the BigMAC functional block. 3777c478bd9Sstevel@tonic-gate * 3787c478bd9Sstevel@tonic-gate * The BigMAC block will provide the MAC functons for 10 or 100 Mbps CSMA/CD 3797c478bd9Sstevel@tonic-gate * protocol based interface. 3807c478bd9Sstevel@tonic-gate * 3817c478bd9Sstevel@tonic-gate */ 3827c478bd9Sstevel@tonic-gate 3837c478bd9Sstevel@tonic-gate /* 3847c478bd9Sstevel@tonic-gate * BigMAC Register Set. 3857c478bd9Sstevel@tonic-gate * BigMAC addresses map on a SBus word boundry. So all registers are 3867c478bd9Sstevel@tonic-gate * declared for a size of 32 bits. Registers that use fewer than 32 3877c478bd9Sstevel@tonic-gate * bits will return 0 in the bits not used. 3887c478bd9Sstevel@tonic-gate */ 3897c478bd9Sstevel@tonic-gate struct hme_bmac { 3907c478bd9Sstevel@tonic-gate uint_t xifc; /* XIF Configuration register [9-0] (RW) */ 3917c478bd9Sstevel@tonic-gate uint_t pad1[129]; /* XXX unused */ 3927c478bd9Sstevel@tonic-gate uint_t txrst; /* tx software reset (RW) */ 3937c478bd9Sstevel@tonic-gate uint_t txcfg; /* tx configuration register [9-0] (RW) */ 3947c478bd9Sstevel@tonic-gate uint_t ipg1; /* Inter Packet Gap 1 [7-0] (RW) */ 3957c478bd9Sstevel@tonic-gate uint_t ipg2; /* Inter Packet Gap 2 [7-0] (RW) */ 3967c478bd9Sstevel@tonic-gate uint_t alimit; /* attempt limit register [7-0] (RW) */ 3977c478bd9Sstevel@tonic-gate uint_t slot; /* slot time register [7-0] (RW) */ 3987c478bd9Sstevel@tonic-gate uint_t palen; /* preamble length register [7-0] (RW) */ 3997c478bd9Sstevel@tonic-gate uint_t papat; /* preamble pattern register [7-0] (RW) */ 4007c478bd9Sstevel@tonic-gate uint_t txsfd; /* tx start frame delimiter [7-0] (RW) */ 4017c478bd9Sstevel@tonic-gate uint_t jam; /* jam size register [7-0] (RW) */ 4027c478bd9Sstevel@tonic-gate uint_t txmax; /* tx maximum packet size [12-0] (RW) */ 4037c478bd9Sstevel@tonic-gate uint_t txmin; /* tx minimum frame size [7-0] (RW) */ 4047c478bd9Sstevel@tonic-gate uint_t parg; /* peak attempt count [7-0] (RW) */ 4057c478bd9Sstevel@tonic-gate uint_t dcnt; /* defer timer counter [15-0] (RW) */ 4067c478bd9Sstevel@tonic-gate uint_t nccnt; /* normal collision counter [15-0] (RW) */ 4077c478bd9Sstevel@tonic-gate uint_t fccnt; /* first succesful coll. counter [15-0] (RW) */ 4087c478bd9Sstevel@tonic-gate uint_t excnt; /* excess collision counter [7-0] (RW) */ 4097c478bd9Sstevel@tonic-gate uint_t ltcnt; /* late collision counter [7-0] (RW) */ 4107c478bd9Sstevel@tonic-gate uint_t rseed; /* random number seed [9-0] (RW) */ 4117c478bd9Sstevel@tonic-gate uint_t txsm; /* tx state machine register [8-0] (R) */ 4127c478bd9Sstevel@tonic-gate uint_t pad2[44]; /* XXX Unused */ 4137c478bd9Sstevel@tonic-gate uint_t rxrst; /* rx software reset register (RW) */ 4147c478bd9Sstevel@tonic-gate uint_t rxcfg; /* rx configuration register [12-0] (RW) */ 4157c478bd9Sstevel@tonic-gate uint_t rxmax; /* rx maximum packet size [12-0] (RW) */ 4167c478bd9Sstevel@tonic-gate uint_t rxmin; /* rx minimum frame size [7-0] (RW) */ 4177c478bd9Sstevel@tonic-gate uint_t madd2; /* mac address register 2 [47-32] (RW) */ 4187c478bd9Sstevel@tonic-gate uint_t madd1; /* mac address register 1 [31-16] (RW) */ 4197c478bd9Sstevel@tonic-gate uint_t madd0; /* mac address register 0 [15-0] (RW) */ 4207c478bd9Sstevel@tonic-gate uint_t frcnt; /* receive frame count [15-0] (RW) */ 4217c478bd9Sstevel@tonic-gate uint_t lecnt; /* rx giant length error count [7-0] (RW) */ 4227c478bd9Sstevel@tonic-gate uint_t aecnt; /* rx alignment error count [7-0] (RW) */ 4237c478bd9Sstevel@tonic-gate uint_t fecnt; /* receive crc error count [7-0] (RW) */ 4247c478bd9Sstevel@tonic-gate uint_t rxsm; /* rx state machine register (R) */ 4257c478bd9Sstevel@tonic-gate uint_t rxcv; /* rx code voilation register (R) */ 4267c478bd9Sstevel@tonic-gate uchar_t pad3[4]; 4277c478bd9Sstevel@tonic-gate uint_t hash3; /* hash table 3 [63-48] (RW) */ 4287c478bd9Sstevel@tonic-gate uint_t hash2; /* hash table 2 [47-32] (RW) */ 4297c478bd9Sstevel@tonic-gate uint_t hash1; /* hash table 1 [31-16] (RW) */ 4307c478bd9Sstevel@tonic-gate uint_t hash0; /* hash table 0 [15-0] (RW) */ 4317c478bd9Sstevel@tonic-gate uint_t afr2; /* addr filter register 0_2 [15-0] (RW) */ 4327c478bd9Sstevel@tonic-gate uint_t afr1; /* addr filter register 0_1 [15-0] (RW) */ 4337c478bd9Sstevel@tonic-gate uint_t afr0; /* addr filter register 0_0 [15-0] (RW) */ 4347c478bd9Sstevel@tonic-gate uint_t afmr; /* addr filter mask reg 0 [15-0] (RW) */ 4357c478bd9Sstevel@tonic-gate }; 4367c478bd9Sstevel@tonic-gate 4377c478bd9Sstevel@tonic-gate /* 4387c478bd9Sstevel@tonic-gate * BigMAC Register Bit Masks. 4397c478bd9Sstevel@tonic-gate */ 4407c478bd9Sstevel@tonic-gate 4417c478bd9Sstevel@tonic-gate /* XIF Configuration Register */ 4427c478bd9Sstevel@tonic-gate 4437c478bd9Sstevel@tonic-gate #define BMAC_XIFC_ENAB (1 << 0) /* Enable XIF output drivers */ 4447c478bd9Sstevel@tonic-gate #define BMAC_XIFC_XIFLPBK (1 << 1) /* Enable XIF Loopback mode */ 4457c478bd9Sstevel@tonic-gate #define BMAC_XIFC_MIILPBK (1 << 2) /* Enable MII Loopback mode */ 4467c478bd9Sstevel@tonic-gate #define BMAC_XIFC_MIIBUFDIS (1 << 3) /* Disable MII Recv Buffers */ 4477c478bd9Sstevel@tonic-gate 4487c478bd9Sstevel@tonic-gate /* IN FEPS 2.1 or earlier rev */ 4497c478bd9Sstevel@tonic-gate #define BMAC_XIFC_SQETSTENB (1 << 4) /* Enable SQE Test */ 4507c478bd9Sstevel@tonic-gate #define BMAC_XIFC_SQETSTWIN (0x1f << 5) /* SQE Test time window */ 4517c478bd9Sstevel@tonic-gate 4527c478bd9Sstevel@tonic-gate /* IN FEPS 2.2 or later rev */ 4537c478bd9Sstevel@tonic-gate #define BMAC_XIFC_LANCE_ENAB (1 << 4) /* Enable LANCE mode */ 4547c478bd9Sstevel@tonic-gate #define BMAC_XIFC_LANCE_IPG0 (0x1f << 5) /* IPG0 for LANCE mode */ 4557c478bd9Sstevel@tonic-gate 4567c478bd9Sstevel@tonic-gate #define BMAC_XIFC_IPG0_SHIFT 5 4577c478bd9Sstevel@tonic-gate 4587c478bd9Sstevel@tonic-gate /* 4597c478bd9Sstevel@tonic-gate * TX_MAC Software Reset Command Register 4607c478bd9Sstevel@tonic-gate * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared. 4617c478bd9Sstevel@tonic-gate * after the command has been executed. 4627c478bd9Sstevel@tonic-gate */ 4637c478bd9Sstevel@tonic-gate 4647c478bd9Sstevel@tonic-gate #define BMAC_TX_RESET (1 << 0) /* TX_MAC Reset Command */ 4657c478bd9Sstevel@tonic-gate 4667c478bd9Sstevel@tonic-gate /* 4677c478bd9Sstevel@tonic-gate * TX_MAC Configuration Register 4687c478bd9Sstevel@tonic-gate * To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always 4697c478bd9Sstevel@tonic-gate * be cleared to 0 and a delay imposed before a PIO write to any of the other 4707c478bd9Sstevel@tonic-gate * bits in the TX_MAC Configuration register or any of the MAC parameter 4717c478bd9Sstevel@tonic-gate * registers is done. 4727c478bd9Sstevel@tonic-gate * 4737c478bd9Sstevel@tonic-gate * The amount of delay required depends on the time required to transmit a max. 4747c478bd9Sstevel@tonic-gate * size frame. 4757c478bd9Sstevel@tonic-gate */ 4767c478bd9Sstevel@tonic-gate 4777c478bd9Sstevel@tonic-gate #define BMACTXRSTDELAY (125) /* 125 us wait period */ 4787c478bd9Sstevel@tonic-gate 4797c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_ENAB (1 << 0) /* tx enable */ 4807c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_RES1 (0xf << 1) /* 1-4 : reserved */ 4817c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_SLOW (1 << 5) /* carrier detect before tx */ 4827c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_IGCOLL (1 << 6) /* tx ignore collision */ 4837c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NFCS (1 << 7) /* no FCS will be generated */ 4847c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NBKOFF (1 << 8) /* No Backoff */ 4857c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_FDX (1 << 9) /* Full Duplex */ 4867c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NGU (1 << 10) /* Never Give Up */ 4877c478bd9Sstevel@tonic-gate 4887c478bd9Sstevel@tonic-gate /* 4897c478bd9Sstevel@tonic-gate * RX_MAC Configuration Register 4907c478bd9Sstevel@tonic-gate * A delay of 3.2 us should be allowed after clearing Rx_MAC_Enable or 4917c478bd9Sstevel@tonic-gate * Hash_Filter_enable or Address_Filter_Enable bits. 4927c478bd9Sstevel@tonic-gate */ 4937c478bd9Sstevel@tonic-gate 4947c478bd9Sstevel@tonic-gate #define BMACRXRSTDELAY (40) /* 3.2 us wait period */ 4957c478bd9Sstevel@tonic-gate 4967c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_ENAB (1 << 0) /* rx enable */ 4977c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_RES1 (0xf << 1) /* 1-4 : reserved */ 4987c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_STRIP (1 << 5) /* rx strip pad bytes */ 4997c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_PROMIS (1 << 6) /* rx enable promiscous */ 5007c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_ERR (1 << 7) /* rx disable error checking */ 5017c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_CRC (1 << 8) /* rx disable CRC stripping */ 5027c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_MYOWN (1 << 9) /* rx filter own packets */ 5037c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_GRPROM (1 << 10) /* rx promiscuous group mode */ 5047c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_HASH (1 << 11) /* rx enable hash filter */ 5057c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_ADDR (1 << 12) /* rx enable address filter */ 5067c478bd9Sstevel@tonic-gate 5077c478bd9Sstevel@tonic-gate 5087c478bd9Sstevel@tonic-gate 5097c478bd9Sstevel@tonic-gate /* ************************************************************************* */ 5107c478bd9Sstevel@tonic-gate 5117c478bd9Sstevel@tonic-gate /* 5127c478bd9Sstevel@tonic-gate * MII Transceiver Interface 5137c478bd9Sstevel@tonic-gate * 5147c478bd9Sstevel@tonic-gate * The Management Interface (MIF) allows the host to program and collect status 5157c478bd9Sstevel@tonic-gate * from two transceivers connected to the MII. MIF supports three modes of 5167c478bd9Sstevel@tonic-gate * operation: 5177c478bd9Sstevel@tonic-gate * 1. Bit-Bang Mode 5187c478bd9Sstevel@tonic-gate * This mode is imlemented using three 1-bit registers: data, clock, 5197c478bd9Sstevel@tonic-gate * and output_enable. 5207c478bd9Sstevel@tonic-gate * 5217c478bd9Sstevel@tonic-gate * 2. Frame Mode 5227c478bd9Sstevel@tonic-gate * This mode is supported using one 32-bit register: Frame register. 5237c478bd9Sstevel@tonic-gate * The software loads the Frame Register with avalid instaruction 5247c478bd9Sstevel@tonic-gate * ("frame"), and polls the Valid Bit for completion. 5257c478bd9Sstevel@tonic-gate * 5267c478bd9Sstevel@tonic-gate * 3. Polling Mode 5277c478bd9Sstevel@tonic-gate * The Polling mechanism is used for detecting a status change in the 5287c478bd9Sstevel@tonic-gate * transceiver. When this mode is enabled, the MIF will continuously 5297c478bd9Sstevel@tonic-gate * poll a specified transceiver register and generate a maskable 5307c478bd9Sstevel@tonic-gate * interrupt when a status change is detected. This mode of operation 5317c478bd9Sstevel@tonic-gate * can only be used when the MIF is in the "Frame mode". 5327c478bd9Sstevel@tonic-gate * 5337c478bd9Sstevel@tonic-gate */ 5347c478bd9Sstevel@tonic-gate 5357c478bd9Sstevel@tonic-gate struct hme_mif { 5367c478bd9Sstevel@tonic-gate uint_t mif_bbclk; /* MIF Bit Bang Clock */ 5377c478bd9Sstevel@tonic-gate uint_t mif_bbdata; /* MIF Bit Bang Data */ 5387c478bd9Sstevel@tonic-gate uint_t mif_bbopenb; /* MIF Bit Bang Output Enable */ 5397c478bd9Sstevel@tonic-gate uint_t mif_frame; /* MIF Frame - ctl and data */ 5407c478bd9Sstevel@tonic-gate uint_t mif_cfg; /* MIF Configuration */ 5417c478bd9Sstevel@tonic-gate uint_t mif_imask; /* MIF Interrupt mask */ 5427c478bd9Sstevel@tonic-gate uint_t mif_bsts; /* MIF Basic/Status register */ 5437c478bd9Sstevel@tonic-gate uint_t mif_fsm; /* MIF State machine register */ 5447c478bd9Sstevel@tonic-gate }; 5457c478bd9Sstevel@tonic-gate 5467c478bd9Sstevel@tonic-gate /* mif_bbc - Bit Bang Clock register */ 5477c478bd9Sstevel@tonic-gate #define HME_MIF_BBCLK (1 << 0); /* Bit Babg Clock */ 5487c478bd9Sstevel@tonic-gate 5497c478bd9Sstevel@tonic-gate #define HME_BBCLK_LOW 0 5507c478bd9Sstevel@tonic-gate #define HME_BBCLK_HIGH 1 5517c478bd9Sstevel@tonic-gate 5527c478bd9Sstevel@tonic-gate /* mif_bbdata - bit Bang Data register */ 5537c478bd9Sstevel@tonic-gate #define HME_MIF_BBDATA (1 << 0); /* Bit Bang Data */ 5547c478bd9Sstevel@tonic-gate 5557c478bd9Sstevel@tonic-gate /* mif_bbopenb - Bit Bang oOutput Enable register */ 5567c478bd9Sstevel@tonic-gate #define HME_MIF_BBOPENB (1 << 0); /* Bit Bang output Enable */ 5577c478bd9Sstevel@tonic-gate 5587c478bd9Sstevel@tonic-gate /* 5597c478bd9Sstevel@tonic-gate * Management Frame Structure: 5607c478bd9Sstevel@tonic-gate * <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE> 5617c478bd9Sstevel@tonic-gate * READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD> 5627c478bd9Sstevel@tonic-gate * WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD> 5637c478bd9Sstevel@tonic-gate */ 5647c478bd9Sstevel@tonic-gate 5657c478bd9Sstevel@tonic-gate /* mif_frame - MIF control and data register */ 5667c478bd9Sstevel@tonic-gate 5677c478bd9Sstevel@tonic-gate #define HME_MIF_FRDATA (0xffff << 0) /* 0-15 : data bits */ 5687c478bd9Sstevel@tonic-gate #define HME_MIF_FRTA0 (0x1 << 16) /* 16 : TA bit, 1 for completion */ 5697c478bd9Sstevel@tonic-gate #define HME_MIF_FRTA1 (0x1 << 17) /* 16-17 : TA bits */ 5707c478bd9Sstevel@tonic-gate #define HME_MIF_FRREGAD (0x1f << 18) /* 18-22 : register address bits */ 5717c478bd9Sstevel@tonic-gate #define HME_MIF_FRPHYAD (0x1f << 23) /* 23-27 : PHY ad, should be 0 */ 5727c478bd9Sstevel@tonic-gate #define HME_MIF_FROP (0x3 << 28) /* 28-29 : Operation - Write/Read */ 5737c478bd9Sstevel@tonic-gate #define HME_MIF_FRST (0xc0000000) /* 30-31 : START bits */ 5747c478bd9Sstevel@tonic-gate 5757c478bd9Sstevel@tonic-gate #define HME_MIF_FRREGAD_SHIFT 18 5767c478bd9Sstevel@tonic-gate #define HME_MIF_FRPHYAD_SHIFT 23 5777c478bd9Sstevel@tonic-gate #define HME_MIF_FRREAD 0x60020000 5787c478bd9Sstevel@tonic-gate #define HME_MIF_FRWRITE 0x50020000 5797c478bd9Sstevel@tonic-gate 5807c478bd9Sstevel@tonic-gate /* maximum delay for MIF Register Read/Write operation */ 5817c478bd9Sstevel@tonic-gate #define HMEMAXMIFDELAY (100) 5827c478bd9Sstevel@tonic-gate 5837c478bd9Sstevel@tonic-gate /* maximum delay for Transceiver Reset */ 5847c478bd9Sstevel@tonic-gate #define HME_PHYRST_MAXDELAY (500) 5857c478bd9Sstevel@tonic-gate 5867c478bd9Sstevel@tonic-gate /* mif_cfg - MIF Configuration Register */ 5877c478bd9Sstevel@tonic-gate 5887c478bd9Sstevel@tonic-gate #define HME_MIF_CFGPS (1 << 0) /* PHY Select */ 5897c478bd9Sstevel@tonic-gate #define HME_MIF_CFGPE (1 << 1) /* Poll Enable */ 5907c478bd9Sstevel@tonic-gate #define HME_MIF_CFGBB (1 << 2) /* Bit Bang Enable */ 5917c478bd9Sstevel@tonic-gate #define HME_MIF_CFGPR (0x1f << 3) /* Poll Register address */ 5927c478bd9Sstevel@tonic-gate #define HME_MIF_CFGM0 (1 << 8) /* MDIO_0 Data / MDIO_0 attached */ 5937c478bd9Sstevel@tonic-gate #define HME_MIF_CFGM1 (1 << 9) /* MDIO_1 Data / MDIO_1 attached */ 5947c478bd9Sstevel@tonic-gate #define HME_MIF_CFGPD (0x1f << 10) /* Poll Device PHY address */ 5957c478bd9Sstevel@tonic-gate 5967c478bd9Sstevel@tonic-gate #define HME_MIF_CFGPR_SHIFT 3 5977c478bd9Sstevel@tonic-gate #define HME_MIF_CFGPD_SHIFT 10 5987c478bd9Sstevel@tonic-gate #define HME_MIF_POLL_DELAY 200 5997c478bd9Sstevel@tonic-gate 6007c478bd9Sstevel@tonic-gate /* 6017c478bd9Sstevel@tonic-gate * MDIO_0 corresponds to the On Board Transceiver. 6027c478bd9Sstevel@tonic-gate * MDIO_1 corresponds to the External Transceiver. 6037c478bd9Sstevel@tonic-gate * The PHYAD for both is 0. 6047c478bd9Sstevel@tonic-gate */ 6057c478bd9Sstevel@tonic-gate 6067c478bd9Sstevel@tonic-gate #define HME_INTERNAL_PHYAD 1 /* PHY address for int. transceiver */ 6077c478bd9Sstevel@tonic-gate #define HME_EXTERNAL_PHYAD 0 /* PHY address for ext. transceiver */ 6087c478bd9Sstevel@tonic-gate 6097c478bd9Sstevel@tonic-gate 6107c478bd9Sstevel@tonic-gate /* mif_imask - MIF Interrupt Mask Register */ 6117c478bd9Sstevel@tonic-gate /* 6127c478bd9Sstevel@tonic-gate * This register is bit-to-bit same as Basic/Status Register 6137c478bd9Sstevel@tonic-gate */ 6147c478bd9Sstevel@tonic-gate #define HME_MIF_INTMASK (0xffff << 0) /* 0-15 : Interrupt mask */ 6157c478bd9Sstevel@tonic-gate 6167c478bd9Sstevel@tonic-gate /* mif_bassts - MIF Basic / Status register */ 6177c478bd9Sstevel@tonic-gate /* 6187c478bd9Sstevel@tonic-gate * The Basic portion of this register indicates the last value of the register 6197c478bd9Sstevel@tonic-gate * read indicated in the POLL REG field of the Configuration Register. 6207c478bd9Sstevel@tonic-gate * The Status portion indicates bit(s) that have changed. 6217c478bd9Sstevel@tonic-gate * The MIF Mask register is corresponding to this register in terms of the 6227c478bd9Sstevel@tonic-gate * bit(s) that need to be masked for generating interrupt on the MIF Interrupt 6237c478bd9Sstevel@tonic-gate * Bit of the Global Status Rgister. 6247c478bd9Sstevel@tonic-gate */ 6257c478bd9Sstevel@tonic-gate 6267c478bd9Sstevel@tonic-gate #define HME_MIF_STATUS (0xffff << 0) /* 0-15 : Status */ 6277c478bd9Sstevel@tonic-gate #define HME_MIF_BASIC (0xffff << 16) /* 16-31 : Basic register */ 6287c478bd9Sstevel@tonic-gate 6297c478bd9Sstevel@tonic-gate /* mif_fsm - MIF State Machine register */ 6307c478bd9Sstevel@tonic-gate 6317c478bd9Sstevel@tonic-gate #define HME_MIF_FSM (0x3ff << 0) /* 0-9 : MIF state */ 6327c478bd9Sstevel@tonic-gate 6337c478bd9Sstevel@tonic-gate /* ************************************************************************ */ 6347c478bd9Sstevel@tonic-gate 6357c478bd9Sstevel@tonic-gate 6367c478bd9Sstevel@tonic-gate /* 6377c478bd9Sstevel@tonic-gate * Definition for the time required to wait after a software 6387c478bd9Sstevel@tonic-gate * reset has been issued. 6397c478bd9Sstevel@tonic-gate */ 6407c478bd9Sstevel@tonic-gate #define HMEMAXRSTDELAY (200) 6417c478bd9Sstevel@tonic-gate #define HMEPERIOD (20) /* period to wait */ 6427c478bd9Sstevel@tonic-gate #define HMEWAITPERIOD HMEPERIOD 6437c478bd9Sstevel@tonic-gate 6447c478bd9Sstevel@tonic-gate #define HMEDELAY(c, n) \ 6457c478bd9Sstevel@tonic-gate { \ 6467c478bd9Sstevel@tonic-gate register int N = n / HMEWAITPERIOD; \ 6477c478bd9Sstevel@tonic-gate while (--N > 0) { \ 6487c478bd9Sstevel@tonic-gate if (c) \ 6497c478bd9Sstevel@tonic-gate break; \ 6507c478bd9Sstevel@tonic-gate drv_usecwait(HMEWAITPERIOD); \ 6517c478bd9Sstevel@tonic-gate } \ 6527c478bd9Sstevel@tonic-gate } 6537c478bd9Sstevel@tonic-gate 6540219346bSGarrett D'Amore #endif /* HME_MAC_H */ 655