xref: /illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c (revision d0b12b66)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2010 QLogic Corporation. All rights reserved.
 */

#include <qlge.h>

static uint32_t ql_dump_buf_8(uint8_t *, uint32_t, uint32_t);
static uint32_t ql_dump_buf_16(uint16_t *, uint32_t, uint32_t);
static uint32_t ql_dump_buf_32(uint32_t *, uint32_t, uint32_t);
static uint32_t ql_dump_buf_64(uint64_t *, uint32_t, uint32_t);
static int ql_binary_core_dump(qlge_t *, uint32_t, uint32_t *);

static char ISP_8100_REGION[] = {
	"nic: nic_boot, nic_param, nic_vpd \n"
	"mpi: mpi_fw, mpi_config, edc_fw\n"
	"fc: fc_boot, fc_fw, fc_nvram, fc_vpd"};
static char ISP_8100_AVAILABLE_DUMPS[] = {"core,register,all"};

/*
 * Get byte from I/O port
 */
uint8_t
ql_get8(qlge_t *qlge, uint32_t index)
{
	uint8_t ret;

	ret = (uint8_t)ddi_get8(qlge->dev_handle,
	    (uint8_t *)(((caddr_t)qlge->iobase) + index));
	return (ret);
}

/*
 * Get word from I/O port
 */
uint16_t
ql_get16(qlge_t *qlge, uint32_t index)
{
	uint16_t ret;

	ret = (uint16_t)ddi_get16(qlge->dev_handle,
	    (uint16_t *)(void *)(((caddr_t)qlge->iobase) + index));
	return (ret);
}

/*
 * Get double word from I/O port
 */
uint32_t
ql_get32(qlge_t *qlge, uint32_t index)
{
	uint32_t ret;

	ret = ddi_get32(qlge->dev_handle,
	    (uint32_t *)(void *)(((caddr_t)qlge->iobase) + index));
	return (ret);
}

/*
 * Send byte to I/O port
 */
void
ql_put8(qlge_t *qlge, uint32_t index, uint8_t data)
{
	ddi_put8(qlge->dev_handle,
	    (uint8_t *)(((caddr_t)qlge->iobase) + index), data);
}

/*
 * Send word to I/O port
 */
void
ql_put16(qlge_t *qlge, uint32_t index, uint16_t data)
{
	ddi_put16(qlge->dev_handle,
	    (uint16_t *)(void *)(((caddr_t)qlge->iobase) + index), data);
}

/*
 * Send double word to I/O port
 */
void
ql_put32(qlge_t *qlge, uint32_t index, uint32_t data)
{
	ddi_put32(qlge->dev_handle,
	    (uint32_t *)(void *)(((caddr_t)qlge->iobase) + index), data);
}

/*
 * Read from a register
 */
uint32_t
ql_read_reg(qlge_t *qlge, uint32_t reg)
{
	uint32_t data = ql_get32(qlge, reg);

	return (data);
}

/*
 * Write 32 bit data to a register
 */
void
ql_write_reg(qlge_t *qlge, uint32_t reg, uint32_t data)
{
	ql_put32(qlge, reg, data);
}

/*
 * Set semaphore register bit to lock access to a shared register
 */
int
ql_sem_lock(qlge_t *qlge, uint32_t sem_mask, uint32_t sem_bits)
{
	uint32_t value;

	ql_put32(qlge, REG_SEMAPHORE, (sem_mask | sem_bits));
	value = ql_get32(qlge, REG_SEMAPHORE);
	return ((value & (sem_mask >> 16)) == sem_bits);
}
/*
 * Wait up to "delay" seconds until the register "reg"'s
 * "wait_bit" is set
 * Default wait time is 5 seconds if "delay" time was not set.
 */
int
ql_wait_reg_bit(qlge_t *qlge, uint32_t reg, uint32_t wait_bit, int set,
    uint32_t delay)
{
	uint32_t reg_status;
	uint32_t timer = 5; /* 5 second */
	int rtn_val = DDI_SUCCESS;
	uint32_t delay_ticks;

	if (delay != 0)
		timer = delay;

	delay_ticks = timer * 100;
	/*
	 * wait for Configuration register test bit to be set,
	 * if not, then it is still busy.
	 */
	do {
		reg_status = ql_read_reg(qlge, reg);
		/* wait for bit set or reset? */
		if (set == BIT_SET) {
			if (reg_status & wait_bit)
				break;
			else
				qlge_delay(QL_ONE_SEC_DELAY / 100);
		} else {
			if (reg_status & wait_bit)
				qlge_delay(QL_ONE_SEC_DELAY / 100);
			else
				break;
		}
	} while (--delay_ticks);

	if (delay_ticks == 0) {
		rtn_val = DDI_FAILURE;
		cmn_err(CE_WARN, "qlge(%d)wait reg %x, bit %x time out",
		    qlge->instance, reg, wait_bit);
		if (qlge->fm_enable) {
			ql_fm_ereport(qlge, DDI_FM_DEVICE_NO_RESPONSE);
			atomic_or_32(&qlge->flags, ADAPTER_ERROR);
		}
	}
	return (rtn_val);
}

/*
 * Dump the value of control registers
 */
void
ql_dump_all_contrl_regs(qlge_t *qlge)
{
	int i;
	uint32_t data;

	for (i = 0; i < 0xff; i = i+4) {
		data = ql_read_reg(qlge, i);
		ql_printf("\tregister# 0x%x value: 0x%x\n", i, data);
	}
}

/*
 * Prints string plus buffer.
 */
void
ql_dump_buf(char *string, uint8_t *buffer, uint8_t wd_size,
    uint32_t count)
{
	uint32_t offset = 0;

	if (strcmp(string, "") != 0)
		ql_printf(string);

	if ((buffer == NULL) || (count == 0))
		return;

	switch (wd_size) {
	case 8:
		while (count) {
			count = ql_dump_buf_8(buffer, count, offset);
			offset += 8;
			buffer += 8;
		}
		break;

	case 16:
		while (count) {
			count = ql_dump_buf_16((uint16_t *)(void *)buffer,
			    count, offset);
			offset += 16;
			buffer += 16;
		}
		break;
	case 32:
		while (count) {
			count = ql_dump_buf_32((uint32_t *)(void *)buffer,
			    count, offset);
			offset += 16;
			buffer += 16;
		}
		break;
	case 64:
		while (count) {
			count = ql_dump_buf_64((uint64_t *)(void *)buffer,
			    count, offset);
			offset += 16;
			buffer += 16;
		}
		break;
	default:
		break;
	}
}

/*
 * Print as 8bit bytes
 */
static uint32_t
ql_dump_buf_8(uint8_t *bp, uint32_t count, uint32_t offset)
{
	switch (count) {
	case 1:
		ql_printf("0x%016x : %02x\n",
		    offset,
		    *bp);
		break;

	case 2:
		ql_printf("0x%016x : %02x %02x\n",
		    offset,
		    *bp, *(bp+1));
		break;

	case 3:
		ql_printf("0x%016x : %02x %02x %02x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2));
		break;

	case 4:
		ql_printf("0x%016x : %02x %02x %02x %02x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3));
		break;

	case 5:
		ql_printf("0x%016x : %02x %02x %02x %02x %02x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4));
		break;

	case 6:
		ql_printf("0x%016x : %02x %02x %02x %02x %02x %02x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5));
		break;

	case 7:
		ql_printf("0x%016x : %02x %02x %02x %02x %02x %02x %02x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5), *(bp+6));
		break;

	default:
		ql_printf("0x%016x : %02x %02x %02x %02x %02x %02x %02x %02x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5), *(bp+6),
		    *(bp+7));
		break;

	}

	if (count < 8) {
		count = 0;
	} else {
		count -= 8;
	}

	return (count);
}

/*
 * Print as 16bit
 */
static uint32_t
ql_dump_buf_16(uint16_t *bp, uint32_t count, uint32_t offset)
{

	switch (count) {
	case 1:
		ql_printf("0x%016x : %04x\n",
		    offset,
		    *bp);
		break;

	case 2:
		ql_printf("0x%016x : %04x %04x\n",
		    offset,
		    *bp, *(bp+1));
		break;

	case 3:
		ql_printf("0x%016x : %04x %04x %04x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2));
		break;

	case 4:
		ql_printf("0x%016x : %04x %04x %04x %04x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3));
		break;

	case 5:
		ql_printf("0x%016x : %04x %04x %04x %04x %04x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4));
		break;

	case 6:
		ql_printf("0x%016x : %04x %04x %04x %04x %04x %04x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5));
		break;

	case 7:
		ql_printf("0x%016x : %04x %04x %04x %04x %04x %04x %04x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5), *(bp+6));
		break;

	default:
		ql_printf("0x%016x : %04x %04x %04x %04x %04x %04x %04x %04x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5), *(bp+6),
		    *(bp+7));
		break;
	}

	if (count < 8) {
		count = 0;
	} else {
		count -= 8;
	}

	return (count);
}

/*
 * Print as 32bit
 */
static uint32_t
ql_dump_buf_32(uint32_t *bp, uint32_t count, uint32_t offset)
{

	switch (count) {
	case 1:
		ql_printf("0x%016x : %08x\n",
		    offset,
		    *bp);
		break;

	case 2:
		ql_printf("0x%016x : %08x %08x\n",
		    offset,
		    *bp, *(bp+1));
		break;

	case 3:
		ql_printf("0x%016x : %08x %08x %08x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2));
		break;

	default:
		ql_printf("0x%016x : %08x %08x %08x %08x\n",
		    offset,
		    *bp, *(bp+1), *(bp+2), *(bp+3));
		break;
	}

	if (count < 4) {
		count = 0;
	} else {
		count -= 4;
	}

	return (count);
}

/*
 * Print as 64bit
 */
static uint32_t
ql_dump_buf_64(uint64_t *bp, uint32_t count, uint32_t offset)
{

	switch (count) {
	case 1:
		ql_printf("0x%016x : %016x\n",
		    offset,
		    *bp);
		break;

	default:
		ql_printf("0x%016x : %016x %016x\n",
		    offset,
		    *bp, *(bp+1));
		break;

	}

	if (count < 2) {
		count = 0;
	} else {
		count -= 2;
	}

	return (count);
}

/*
 * Print CQICB control block information
 */
/* ARGSUSED */
void
ql_dump_cqicb(qlge_t *qlge, struct cqicb_t *cqicb)
{
	_NOTE(ARGUNUSED(qlge));
	ASSERT(qlge != NULL);
	ASSERT(cqicb != NULL);
	ql_printf("ql_dump_cqicb:entered\n");

	ql_printf("\t msix_vect   = 0x%x\n",
	    cqicb->msix_vect);
	ql_printf("\t reserved1  = 0x%x\n",
	    cqicb->reserved1);
	ql_printf("\t reserved2  = 0x%x\n",
	    cqicb->reserved2);
	ql_printf("\t flags  = 0x%x\n",
	    cqicb->flags);
	ql_printf("\t len  = 0x%x\n",
	    le16_to_cpu(cqicb->len));
	ql_printf("\t rid = 0x%x\n",
	    le16_to_cpu(cqicb->rid));
	ql_printf("\t cq_base_addr_lo = 0x%x\n",
	    le32_to_cpu(cqicb->cq_base_addr_lo));
	ql_printf("\t cq_base_addr_hi = 0x%x\n",
	    le32_to_cpu(cqicb->cq_base_addr_hi));
	ql_printf("\t prod_idx_addr_lo = %x\n",
	    le32_to_cpu(cqicb->prod_idx_addr_lo));
	ql_printf("\t prod_idx_addr_hi = %x\n",
	    le32_to_cpu(cqicb->prod_idx_addr_hi));
	ql_printf("\t pkt_delay = %d\n",
	    le16_to_cpu(cqicb->pkt_delay));
	ql_printf("\t irq_delay = 0x%x\n",
	    le16_to_cpu(cqicb->irq_delay));
	ql_printf("\t lbq_addr_lo = 0x%x\n",
	    le32_to_cpu(cqicb->lbq_addr_lo));
	ql_printf("\t lbq_addr_hi = 0x%x\n",
	    le32_to_cpu(cqicb->lbq_addr_hi));
	ql_printf("\t lbq_buf_size = 0x%x\n",
	    le16_to_cpu(cqicb->lbq_buf_size));
	ql_printf("\t lbq_len = 0x%x\n",
	    le16_to_cpu(cqicb->lbq_len));
	ql_printf("\t sbq_addr_lo = 0x%x\n",
	    le32_to_cpu(cqicb->sbq_addr_lo));
	ql_printf("\t sbq_addr_hi = 0x%x\n",
	    le32_to_cpu(cqicb->sbq_addr_hi));
	ql_printf("\t sbq_buf_size = 0x%x\n",
	    le16_to_cpu(cqicb->sbq_buf_size));
	ql_printf("\t sbq_len = 0x%x\n",
	    le16_to_cpu(cqicb->sbq_len));

	ql_printf("ql_dump_cqicb:exiting\n");
}

/*
 * Print WQICB control block information
 */
/* ARGSUSED */
void
ql_dump_wqicb(qlge_t *qlge, struct wqicb_t *wqicb)
{
	_NOTE(ARGUNUSED(qlge));
	ASSERT(qlge != NULL);
	ASSERT(wqicb != NULL);

	ql_printf("ql_dump_wqicb:entered\n");

	ql_printf("\t len = %x\n",
	    le16_to_cpu(wqicb->len));
	ql_printf("\t flags = %x\n",
	    le16_to_cpu(wqicb->flags));
	ql_printf("\t cq_id_rss = %x\n",
	    le16_to_cpu(wqicb->cq_id_rss));
	ql_printf("\t rid = 0x%x\n",
	    le16_to_cpu(wqicb->rid));
	ql_printf("\t wq_addr_lo = 0x%x\n",
	    le32_to_cpu(wqicb->wq_addr_lo));
	ql_printf("\t wq_addr_hi = 0x%x\n",
	    le32_to_cpu(wqicb->wq_addr_hi));
	ql_printf("\t cnsmr_idx_addr_lo = %x\n",
	    le32_to_cpu(wqicb->cnsmr_idx_addr_lo));
	ql_printf("\t cnsmr_idx_addr_hi = %x\n",
	    le32_to_cpu(wqicb->cnsmr_idx_addr_hi));

	ql_printf("ql_dump_wqicb:exit\n");
}

/*
 * Print request descriptor information
 */
void
ql_dump_req_pkt(qlge_t *qlge, struct ob_mac_iocb_req *pkt, void *oal,
    int number)
{
	int i = 0;
	struct oal_entry *oal_entry;

	ql_printf("ql_dump_req_pkt(%d):enter\n", qlge->instance);

	ql_printf("\t opcode = 0x%x\n",
	    pkt->opcode);
	ql_printf("\t flag0  = 0x%x\n",
	    pkt->flag0);
	ql_printf("\t flag1  = 0x%x\n",
	    pkt->flag1);
	ql_printf("\t flag2  = 0x%x\n",
	    pkt->flag2);
	ql_printf("\t frame_len  = 0x%x\n",
	    le16_to_cpu(pkt->frame_len));
	ql_printf("\t transaction_id_low = 0x%x\n",
	    le16_to_cpu(pkt->tid));
	ql_printf("\t txq_idx = 0x%x\n",
	    le16_to_cpu(pkt->txq_idx));
	ql_printf("\t protocol_hdr_len = 0x%x\n",
	    le16_to_cpu(pkt->protocol_hdr_len));
	ql_printf("\t hdr_off = %d\n",
	    le16_to_cpu(pkt->hdr_off));
	ql_printf("\t vlan_tci = %d\n",
	    le16_to_cpu(pkt->vlan_tci));
	ql_printf("\t mss = %d\n",
	    le16_to_cpu(pkt->mss));

	/* if OAL is needed */
	if (number > TX_DESC_PER_IOCB) {
		for (i = 0; i < TX_DESC_PER_IOCB; i++) {
			ql_printf("\t buf_addr%d_low = 0x%x\n",
			    i, pkt->oal_entry[i].buf_addr_low);
			ql_printf("\t buf_addr%d_high = 0x%x\n",
			    i, pkt->oal_entry[i].buf_addr_high);
			ql_printf("\t buf%d_len = 0x%x\n",
			    i, pkt->oal_entry[i].buf_len);
		}
		oal_entry = (struct oal_entry *)oal;
		ql_printf("\t additional %d tx descriptors in OAL\n",
		    (number - TX_DESC_PER_IOCB + 1));
		for (i = 0; i < (number-TX_DESC_PER_IOCB + 1); i++) {
			ql_printf("\t buf_addr%d_low = 0x%x\n",
			    i, oal_entry[i].buf_addr_low);
			ql_printf("\t buf_addr%d_high = 0x%x\n",
			    i, oal_entry[i].buf_addr_high);
			ql_printf("\t buf%d_len = 0x%x\n",
			    i, oal_entry[i].buf_len);
		}
	} else {
		for (i = 0; i < number; i++) {
			ql_printf("\t buf_addr%d_low = 0x%x\n",
			    i, pkt->oal_entry[i].buf_addr_low);
			ql_printf("\t buf_addr%d_high = 0x%x\n",
			    i, pkt->oal_entry[i].buf_addr_high);
			ql_printf("\t buf%d_len = 0x%x\n",
			    i, pkt->oal_entry[i].buf_len);
		}
	}
	ql_printf("ql_dump_req_pkt:exiting\n");
}

/*
 * Print PCI configuration
 */
void
ql_dump_pci_config(qlge_t *qlge)
{
	qlge->pci_cfg.vendor_id = (uint16_t)
	    pci_config_get16(qlge->pci_handle, PCI_CONF_VENID);

	qlge->pci_cfg.device_id = (uint16_t)
	    pci_config_get16(qlge->pci_handle, PCI_CONF_DEVID);

	qlge->pci_cfg.command = (uint16_t)
	    pci_config_get16(qlge->pci_handle, PCI_CONF_COMM);

	qlge->pci_cfg.status = (uint16_t)
	    pci_config_get16(qlge->pci_handle, PCI_CONF_STAT);

	qlge->pci_cfg.revision = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_REVID);

	qlge->pci_cfg.prog_class = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_PROGCLASS);

	qlge->pci_cfg.sub_class = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_SUBCLASS);

	qlge->pci_cfg.base_class = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_BASCLASS);

	qlge->pci_cfg.cache_line_size = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_CACHE_LINESZ);

	qlge->pci_cfg.latency_timer = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_LATENCY_TIMER);

	qlge->pci_cfg.header_type = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_HEADER);

	qlge->pci_cfg.io_base_address =
	    pci_config_get32(qlge->pci_handle, PCI_CONF_BASE0);

	qlge->pci_cfg.pci_cntl_reg_set_mem_base_address_lower =
	    pci_config_get32(qlge->pci_handle, PCI_CONF_BASE1);

	qlge->pci_cfg.pci_cntl_reg_set_mem_base_address_upper =
	    pci_config_get32(qlge->pci_handle, PCI_CONF_BASE2);

	qlge->pci_cfg.pci_doorbell_mem_base_address_lower =
	    pci_config_get32(qlge->pci_handle, PCI_CONF_BASE3);

	qlge->pci_cfg.pci_doorbell_mem_base_address_upper =
	    pci_config_get32(qlge->pci_handle, PCI_CONF_BASE4);

	qlge->pci_cfg.sub_vendor_id = (uint16_t)
	    pci_config_get16(qlge->pci_handle, PCI_CONF_SUBVENID);

	qlge->pci_cfg.sub_device_id = (uint16_t)
	    pci_config_get16(qlge->pci_handle, PCI_CONF_SUBSYSID);

	qlge->pci_cfg.expansion_rom =
	    pci_config_get32(qlge->pci_handle, PCI_CONF_ROM);

	qlge->pci_cfg.intr_line = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_ILINE);

	qlge->pci_cfg.intr_pin = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_IPIN);

	qlge->pci_cfg.min_grant = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_MIN_G);

	qlge->pci_cfg.max_latency = (uint8_t)
	    pci_config_get8(qlge->pci_handle, PCI_CONF_MAX_L);

	qlge->pci_cfg.pcie_device_control = (uint16_t)
	    pci_config_get16(qlge->pci_handle, 0x54);

	qlge->pci_cfg.link_status = (uint16_t)
	    pci_config_get16(qlge->pci_handle, 0x5e);

	qlge->pci_cfg.msi_msg_control = (uint16_t)
	    pci_config_get16(qlge->pci_handle, 0x8a);

	qlge->pci_cfg.msi_x_msg_control = (uint16_t)
	    pci_config_get16(qlge->pci_handle, 0xa2);

	if (qlge->ql_dbgprnt & DBG_GLD) {
		ql_printf("ql_dump_pci_config(%d): enter\n",
		    qlge->instance);
		ql_printf("\tvendorid =0x%x.\n",
		    qlge->pci_cfg.vendor_id);
		ql_printf("\tdeviceid =0x%x.\n",
		    qlge->pci_cfg.device_id);
		ql_printf("\tcommand =0x%x.\n",
		    qlge->pci_cfg.command);
		ql_printf("\tstatus =0x%x.\n",
		    qlge->pci_cfg.status);
		ql_printf("\trevision id =0x%x.\n",
		    qlge->pci_cfg.revision);
		ql_printf("\tprogram class =0x%x.\n",
		    qlge->pci_cfg.prog_class);
		ql_printf("\tsubclass code =0x%x.\n",
		    qlge->pci_cfg.sub_class);
		ql_printf("\tbase class code =0x%x.\n",
		    qlge->pci_cfg.base_class);
		ql_printf("\tcache line size =0x%x.\n",
		    qlge->pci_cfg.cache_line_size);
		ql_printf("\tlatency timer =0x%x.\n",
		    qlge->pci_cfg.latency_timer);
		ql_printf("\theader =0x%x.\n",
		    qlge->pci_cfg.header_type);
		ql_printf("\tI/O Base Register Address0 =0x%x.\n",
		    qlge->pci_cfg.io_base_address);
		ql_printf("\tpci_cntl_reg_set_mem_base_address_lower =0x%x.\n",
		    qlge->pci_cfg.pci_cntl_reg_set_mem_base_address_lower);
		ql_printf("\tpci_cntl_reg_set_mem_base_address_upper =0x%x.\n",
		    qlge->pci_cfg.pci_cntl_reg_set_mem_base_address_upper);
		ql_printf("\tpci_doorbell_mem_base_address_lower =0x%x.\n",
		    qlge->pci_cfg.pci_doorbell_mem_base_address_lower);
		ql_printf("\tpci_doorbell_mem_base_address_upper =0x%x.\n",
		    qlge->pci_cfg.pci_doorbell_mem_base_address_upper);
		ql_printf("\tSubsystem Vendor Id =0x%x.\n",
		    qlge->pci_cfg.sub_vendor_id);
		ql_printf("\tSubsystem Id =0x%x.\n",
		    qlge->pci_cfg.sub_device_id);
		ql_printf("\tExpansion ROM Base Register =0x%x.\n",
		    qlge->pci_cfg.expansion_rom);
		ql_printf("\tInterrupt Line =0x%x.\n",
		    qlge->pci_cfg.intr_line);
		ql_printf("\tInterrupt Pin =0x%x.\n",
		    qlge->pci_cfg.intr_pin);
		ql_printf("\tMin Grant =0x%x.\n",
		    qlge->pci_cfg.min_grant);
		ql_printf("\tMax Grant =0x%x.\n",
		    qlge->pci_cfg.max_latency);
		ql_printf("\tdevice_control =0x%x.\n",
		    qlge->pci_cfg.pcie_device_control);
		ql_printf("\tlink_status =0x%x.\n",
		    qlge->pci_cfg.link_status);
		ql_printf("\tmsi_msg_control =0x%x.\n",
		    qlge->pci_cfg.msi_msg_control);
		ql_printf("\tmsi_x_msg_control =0x%x.\n",
		    qlge->pci_cfg.msi_x_msg_control);

		ql_printf("ql_dump_pci_config(%d): exit\n", qlge->instance);
	}
}

/*
 * Print a formated string
 */
void
ql_printf(const char *fmt, ...)
{
	va_list ap;

	va_start(ap, fmt);
	vcmn_err(CE_CONT, fmt, ap);
	va_end(ap);

}

/*
 * Read all control registers value and save in a string
 */
static uint32_t
read_ctrl_reg_set(qlge_t *qlge, caddr_t bufp)
{
	int i, j;
	uint32_t data;
	caddr_t bp = bufp;
	uint32_t cnt;

	/* read Reg 0 -0xC4 */
	for (i = 0, j = 0; i <= 0xfc; i += 4) {
		data = ql_read_reg(qlge, i);
		(void) sprintf(bp, "Register[%x] = 0x%x\n", i, data);
		bp += strlen(bp);
		if (i == REG_INTERRUPT_ENABLE) {
			/* Read */
			data = INTR_EN_TYPE_READ;
			ql_write_reg(qlge, i, (data | (data << 16)));
			data = ql_read_reg(qlge, i);
			if (data & INTR_EN_EN) {
				(void) sprintf(bp, "Intr0 enabled: 0x%x\n",
				    data);
				bp += strlen(bp);
			} else {
				(void) sprintf(bp, "Intr0 disabled: 0x%x\n",
				    data);
				bp += strlen(bp);
			}
		}
		j++;
	}
	*bp = '\0';
	bp++;
	cnt = (uint32_t)((uintptr_t)bp - (uintptr_t)bufp);
	QL_PRINT(DBG_GLD, ("%s(%d) %x bytes to export\n",
	    __func__, qlge->instance, cnt));
	return (cnt);
}

/*
 * Get address and size of image tables in flash memory
 */
static int
ql_get_flash_table_region_info(qlge_t *qlge, uint32_t region, uint32_t *addr,
    uint32_t *size)
{
	int rval = DDI_SUCCESS;

	switch (region) {
	case FLT_REGION_FDT:
		*addr = ISP_8100_FDT_ADDR;
		*size = ISP_8100_FDT_SIZE;
		break;
	case FLT_REGION_FLT:
		*addr = ISP_8100_FLT_ADDR;
		*size = ISP_8100_FLT_SIZE;
		break;
	case FLT_REGION_NIC_BOOT_CODE:
		*addr = ISP_8100_NIC_BOOT_CODE_ADDR;
		*size = ISP_8100_NIC_BOOT_CODE_SIZE;
		break;
	case FLT_REGION_MPI_FW_USE:
		*addr = ISP_8100_MPI_FW_USE_ADDR;
		*size = ISP_8100_MPI_FW_USE_SIZE;
		break;
	case FLT_REGION_MPI_RISC_FW:
		*addr = ISP_8100_MPI_RISC_FW_ADDR;
		*size = ISP_8100_MPI_RISC_FW_SIZE;
		break;
	case FLT_REGION_VPD0:
		*addr = ISP_8100_VPD0_ADDR;
		*size = ISP_8100_VPD0_SIZE;
		break;
	case FLT_REGION_NIC_PARAM0:
		*addr = ISP_8100_NIC_PARAM0_ADDR;
		*size = ISP_8100_NIC_PARAM0_SIZE;
		break;
	case FLT_REGION_VPD1:
		*addr = ISP_8100_VPD1_ADDR;
		*size = ISP_8100_VPD1_SIZE;
		break;
	case FLT_REGION_NIC_PARAM1:
		*addr = ISP_8100_NIC_PARAM1_ADDR;
		*size = ISP_8100_NIC_PARAM1_SIZE;
		break;
	case FLT_REGION_MPI_CFG:
		*addr = ISP_8100_MPI_CFG_ADDR;
		*size = ISP_8100_MPI_CFG_SIZE;
		break;
	case FLT_REGION_EDC_PHY_FW:
		*addr = ISP_8100_EDC_PHY_FW_ADDR;
		*size =