175eba5b6SRobert Mustacchi /****************************************************************************** 275eba5b6SRobert Mustacchi 349b78600SRobert Mustacchi Copyright (c) 2001-2015, Intel Corporation 475eba5b6SRobert Mustacchi All rights reserved. 575eba5b6SRobert Mustacchi 675eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 775eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 875eba5b6SRobert Mustacchi 975eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1075eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 1175eba5b6SRobert Mustacchi 1275eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 1375eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1475eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 1575eba5b6SRobert Mustacchi 1675eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 1775eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 1875eba5b6SRobert Mustacchi this software without specific prior written permission. 1975eba5b6SRobert Mustacchi 2075eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2175eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2275eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2375eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2475eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2575eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2675eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2775eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2875eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2975eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3075eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 3175eba5b6SRobert Mustacchi 3275eba5b6SRobert Mustacchi ******************************************************************************/ 3375eba5b6SRobert Mustacchi /*$FreeBSD$*/ 3475eba5b6SRobert Mustacchi 3575eba5b6SRobert Mustacchi #ifndef _E1000_HW_H_ 3675eba5b6SRobert Mustacchi #define _E1000_HW_H_ 3775eba5b6SRobert Mustacchi 3875eba5b6SRobert Mustacchi #include "e1000_osdep.h" 3975eba5b6SRobert Mustacchi #include "e1000_regs.h" 4075eba5b6SRobert Mustacchi #include "e1000_defines.h" 4175eba5b6SRobert Mustacchi 4275eba5b6SRobert Mustacchi struct e1000_hw; 4375eba5b6SRobert Mustacchi 4475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82542 0x1000 4575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82543GC_FIBER 0x1001 4675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82543GC_COPPER 0x1004 4775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82544EI_COPPER 0x1008 4875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82544EI_FIBER 0x1009 4975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82544GC_COPPER 0x100C 5075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82544GC_LOM 0x100D 5175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82540EM 0x100E 5275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82540EM_LOM 0x1015 5375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82540EP_LOM 0x1016 5475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82540EP 0x1017 5575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82540EP_LP 0x101E 5675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82545EM_COPPER 0x100F 5775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82545EM_FIBER 0x1011 5875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82545GM_COPPER 0x1026 5975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82545GM_FIBER 0x1027 6075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82545GM_SERDES 0x1028 6175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546EB_COPPER 0x1010 6275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546EB_FIBER 0x1012 6375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 6475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546GB_COPPER 0x1079 6575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546GB_FIBER 0x107A 6675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546GB_SERDES 0x107B 6775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546GB_PCIE 0x108A 6875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 6975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 7075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541EI 0x1013 7175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541EI_MOBILE 0x1018 7275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541ER_LOM 0x1014 7375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541ER 0x1078 7475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541GI 0x1076 7575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541GI_LF 0x107C 7675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82541GI_MOBILE 0x1077 7775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82547EI 0x1019 7875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82547EI_MOBILE 0x101A 7975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82547GI 0x1075 8075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_COPPER 0x105E 8175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_FIBER 0x105F 8275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_SERDES 0x1060 8375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 8475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 8575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 8675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 8775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 8875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 8975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82572EI_COPPER 0x107D 9075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82572EI_FIBER 0x107E 9175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82572EI_SERDES 0x107F 9275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82572EI 0x10B9 9375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82573E 0x108B 9475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82573E_IAMT 0x108C 9575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82573L 0x109A 9675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82574L 0x10D3 9775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82574LA 0x10F6 9875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82583V 0x150C 9975eba5b6SRobert Mustacchi #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 10075eba5b6SRobert Mustacchi #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 10175eba5b6SRobert Mustacchi #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 10275eba5b6SRobert Mustacchi #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 10375eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_82567V_3 0x1501 10475eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 10575eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 10675eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IGP_C 0x104B 10775eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IFE 0x104C 10875eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 10975eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 11075eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH8_IGP_M 0x104D 11175eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 11275eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 11375eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 11475eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 11575eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_BM 0x10E5 11675eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IGP_C 0x294C 11775eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IFE 0x10C0 11875eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 11975eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 12075eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 12175eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 12275eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 12375eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 12475eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 12575eba5b6SRobert Mustacchi #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 12675eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 12775eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 12875eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 12975eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 13075eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH2_LV_LM 0x1502 13175eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH2_LV_V 0x1503 13275eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 13375eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 13475eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 13575eba5b6SRobert Mustacchi #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136c124a83eSRobert Mustacchi #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137c124a83eSRobert Mustacchi #define E1000_DEV_ID_PCH_I218_V2 0x15A1 138c124a83eSRobert Mustacchi #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139c124a83eSRobert Mustacchi #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 14049b78600SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 14149b78600SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 14249b78600SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 14349b78600SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 14449b78600SRobert Mustacchi #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145ea4c6b78SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146ea4c6b78SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147ea4c6b78SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148ea4c6b78SRobert Mustacchi #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 1495bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 1505bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 1515bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 1525bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 1535bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 1545bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 1555bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 1565bb0bdfeSRobert Mustacchi #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 15752873782SRobert Mustacchi #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 15852873782SRobert Mustacchi #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 15952873782SRobert Mustacchi #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 16052873782SRobert Mustacchi #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 16152873782SRobert Mustacchi #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 16252873782SRobert Mustacchi #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 16352873782SRobert Mustacchi #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 16452873782SRobert Mustacchi #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 16552873782SRobert Mustacchi #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 16652873782SRobert Mustacchi #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 16752873782SRobert Mustacchi #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 168f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 169f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E 170f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F 171f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C 172f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D 173f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 174f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 175f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 176f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 177f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_LNP_I219_LM20 0x550E 178f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_LNP_I219_V20 0x550F 179f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_LNP_I219_LM21 0x5510 180f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_LNP_I219_V21 0x5511 181f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 182f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 183f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 184f3682895SRobert Mustacchi #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 185*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0 186*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1 187*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3 188*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4 189*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5 190*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6 191*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7 192*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8 193*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_NVL_I219_LM29 0x57B9 194*1d0ec46fSRobert Mustacchi #define E1000_DEV_ID_PCH_NVL_I219_V29 0x57BA 19575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576 0x10C9 19675eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_FIBER 0x10E6 19775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_SERDES 0x10E7 19875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 19975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 20075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_NS 0x150A 20175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_NS_SERDES 0x1518 20275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 20375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_VF 0x10CA 20475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82576_VF_HV 0x152D 20575eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_VF 0x1520 20675eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_VF_HV 0x152F 20775eba5b6SRobert Mustacchi #define E1000_DEV_ID_82575EB_COPPER 0x10A7 20875eba5b6SRobert Mustacchi #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 20975eba5b6SRobert Mustacchi #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 21075eba5b6SRobert Mustacchi #define E1000_DEV_ID_82580_COPPER 0x150E 21175eba5b6SRobert Mustacchi #define E1000_DEV_ID_82580_FIBER 0x150F 21275eba5b6SRobert Mustacchi #define E1000_DEV_ID_82580_SERDES 0x1510 21375eba5b6SRobert Mustacchi #define E1000_DEV_ID_82580_SGMII 0x1511 21475eba5b6SRobert Mustacchi #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 21575eba5b6SRobert Mustacchi #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 21675eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_COPPER 0x1521 21775eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_FIBER 0x1522 21875eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_SERDES 0x1523 21975eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_SGMII 0x1524 22075eba5b6SRobert Mustacchi #define E1000_DEV_ID_I350_DA4 0x1546 22175eba5b6SRobert Mustacchi #define E1000_DEV_ID_I210_COPPER 0x1533 22275eba5b6SRobert Mustacchi #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 22375eba5b6SRobert Mustacchi #define E1000_DEV_ID_I210_COPPER_IT 0x1535 22475eba5b6SRobert Mustacchi #define E1000_DEV_ID_I210_FIBER 0x1536 22575eba5b6SRobert Mustacchi #define E1000_DEV_ID_I210_SERDES 0x1537 22675eba5b6SRobert Mustacchi #define E1000_DEV_ID_I210_SGMII 0x1538 227c124a83eSRobert Mustacchi #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 228c124a83eSRobert Mustacchi #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 22975eba5b6SRobert Mustacchi #define E1000_DEV_ID_I211_COPPER 0x1539 23013485e69SGarrett D'Amore #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 23113485e69SGarrett D'Amore #define E1000_DEV_ID_I354_SGMII 0x1F41 232c124a83eSRobert Mustacchi #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 23375eba5b6SRobert Mustacchi #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 23475eba5b6SRobert Mustacchi #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 23575eba5b6SRobert Mustacchi #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 23675eba5b6SRobert Mustacchi #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 23775eba5b6SRobert Mustacchi 23875eba5b6SRobert Mustacchi #define E1000_REVISION_0 0 23975eba5b6SRobert Mustacchi #define E1000_REVISION_1 1 24075eba5b6SRobert Mustacchi #define E1000_REVISION_2 2 24175eba5b6SRobert Mustacchi #define E1000_REVISION_3 3 24275eba5b6SRobert Mustacchi #define E1000_REVISION_4 4 24375eba5b6SRobert Mustacchi 24475eba5b6SRobert Mustacchi #define E1000_FUNC_0 0 24575eba5b6SRobert Mustacchi #define E1000_FUNC_1 1 24675eba5b6SRobert Mustacchi #define E1000_FUNC_2 2 24775eba5b6SRobert Mustacchi #define E1000_FUNC_3 3 24875eba5b6SRobert Mustacchi 24975eba5b6SRobert Mustacchi #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 25075eba5b6SRobert Mustacchi #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 25175eba5b6SRobert Mustacchi #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 25275eba5b6SRobert Mustacchi #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 25375eba5b6SRobert Mustacchi 2545bb0bdfeSRobert Mustacchi /* 2555bb0bdfeSRobert Mustacchi * This enumeration represents all of the different kinds of MAC chips that are 2565bb0bdfeSRobert Mustacchi * used by both the e1000g and igb drivers. The ordering here is important as 2575bb0bdfeSRobert Mustacchi * certain classes of MACs are very similar, but have minor differences and so 2585bb0bdfeSRobert Mustacchi * are compared based on the ordering here. Changing the order here should not 2595bb0bdfeSRobert Mustacchi * be done arbitrarily. 2605bb0bdfeSRobert Mustacchi */ 26175eba5b6SRobert Mustacchi enum e1000_mac_type { 26275eba5b6SRobert Mustacchi e1000_undefined = 0, 26375eba5b6SRobert Mustacchi e1000_82542, 26475eba5b6SRobert Mustacchi e1000_82543, 26575eba5b6SRobert Mustacchi e1000_82544, 26675eba5b6SRobert Mustacchi e1000_82540, 26775eba5b6SRobert Mustacchi e1000_82545, 26875eba5b6SRobert Mustacchi e1000_82545_rev_3, 26975eba5b6SRobert Mustacchi e1000_82546, 27075eba5b6SRobert Mustacchi e1000_82546_rev_3, 27175eba5b6SRobert Mustacchi e1000_82541, 27275eba5b6SRobert Mustacchi e1000_82541_rev_2, 27375eba5b6SRobert Mustacchi e1000_82547, 27475eba5b6SRobert Mustacchi e1000_82547_rev_2, 27575eba5b6SRobert Mustacchi e1000_82571, 27675eba5b6SRobert Mustacchi e1000_82572, 27775eba5b6SRobert Mustacchi e1000_82573, 27875eba5b6SRobert Mustacchi e1000_82574, 27975eba5b6SRobert Mustacchi e1000_82583, 28075eba5b6SRobert Mustacchi e1000_80003es2lan, 2815bb0bdfeSRobert Mustacchi /* 2825bb0bdfeSRobert Mustacchi * The following MACs all share the ich8 style of hardware and are 2835bb0bdfeSRobert Mustacchi * implemented in ich8, though some are a little more different than 284f3682895SRobert Mustacchi * others. The pch_lpt, pch_spt, pch_cnp, pch_tgp, pch_adp, pch_mtp, 285*1d0ec46fSRobert Mustacchi * pch_lnp, pch_rpl, pch_arl, pch_ptp, and pch_nvl families are a bit 286*1d0ec46fSRobert Mustacchi * more different than the others and just have slight variants in 287*1d0ec46fSRobert Mustacchi * behavior between them. We call them out just in case we need to deal 288*1d0ec46fSRobert Mustacchi * with the quirks between different device generations. They are 289*1d0ec46fSRobert Mustacchi * ordered based on release. 2905bb0bdfeSRobert Mustacchi */ 29175eba5b6SRobert Mustacchi e1000_ich8lan, 29275eba5b6SRobert Mustacchi e1000_ich9lan, 29375eba5b6SRobert Mustacchi e1000_ich10lan, 29475eba5b6SRobert Mustacchi e1000_pchlan, 29575eba5b6SRobert Mustacchi e1000_pch2lan, 29675eba5b6SRobert Mustacchi e1000_pch_lpt, 29749b78600SRobert Mustacchi e1000_pch_spt, 2985bb0bdfeSRobert Mustacchi e1000_pch_cnp, 29952873782SRobert Mustacchi e1000_pch_tgp, 300f3682895SRobert Mustacchi e1000_pch_adp, 301f3682895SRobert Mustacchi e1000_pch_mtp, 302f3682895SRobert Mustacchi e1000_pch_lnp, 303f3682895SRobert Mustacchi e1000_pch_rpl, 304*1d0ec46fSRobert Mustacchi e1000_pch_arl, 305*1d0ec46fSRobert Mustacchi e1000_pch_ptp, 306*1d0ec46fSRobert Mustacchi e1000_pch_nvl, 3075bb0bdfeSRobert Mustacchi /* 308bbf21555SRichard Lowe * After this point all MACs are used by the igb(4D) driver as opposed 309bbf21555SRichard Lowe * to e1000g(4D). If a new MAC is specific to e1000g series of devices, 3105bb0bdfeSRobert Mustacchi * then it should be added above this. 3115bb0bdfeSRobert Mustacchi */ 31275eba5b6SRobert Mustacchi e1000_82575, 31375eba5b6SRobert Mustacchi e1000_82576, 31475eba5b6SRobert Mustacchi e1000_82580, 31575eba5b6SRobert Mustacchi e1000_i350, 31613485e69SGarrett D'Amore e1000_i354, 31775eba5b6SRobert Mustacchi e1000_i210, 31875eba5b6SRobert Mustacchi e1000_i211, 31975eba5b6SRobert Mustacchi e1000_vfadapt, 32075eba5b6SRobert Mustacchi e1000_vfadapt_i350, 32175eba5b6SRobert Mustacchi e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 32275eba5b6SRobert Mustacchi }; 32375eba5b6SRobert Mustacchi 32475eba5b6SRobert Mustacchi enum e1000_media_type { 32575eba5b6SRobert Mustacchi e1000_media_type_unknown = 0, 32675eba5b6SRobert Mustacchi e1000_media_type_copper = 1, 32775eba5b6SRobert Mustacchi e1000_media_type_fiber = 2, 32875eba5b6SRobert Mustacchi e1000_media_type_internal_serdes = 3, 32975eba5b6SRobert Mustacchi e1000_num_media_types 33075eba5b6SRobert Mustacchi }; 33175eba5b6SRobert Mustacchi 33275eba5b6SRobert Mustacchi enum e1000_nvm_type { 33375eba5b6SRobert Mustacchi e1000_nvm_unknown = 0, 33475eba5b6SRobert Mustacchi e1000_nvm_none, 33575eba5b6SRobert Mustacchi e1000_nvm_eeprom_spi, 33675eba5b6SRobert Mustacchi e1000_nvm_eeprom_microwire, 33775eba5b6SRobert Mustacchi e1000_nvm_flash_hw, 338c124a83eSRobert Mustacchi e1000_nvm_invm, 33975eba5b6SRobert Mustacchi e1000_nvm_flash_sw 34075eba5b6SRobert Mustacchi }; 34175eba5b6SRobert Mustacchi 34275eba5b6SRobert Mustacchi enum e1000_nvm_override { 34375eba5b6SRobert Mustacchi e1000_nvm_override_none = 0, 34475eba5b6SRobert Mustacchi e1000_nvm_override_spi_small, 34575eba5b6SRobert Mustacchi e1000_nvm_override_spi_large, 34675eba5b6SRobert Mustacchi e1000_nvm_override_microwire_small, 34775eba5b6SRobert Mustacchi e1000_nvm_override_microwire_large 34875eba5b6SRobert Mustacchi }; 34975eba5b6SRobert Mustacchi 35075eba5b6SRobert Mustacchi enum e1000_phy_type { 35175eba5b6SRobert Mustacchi e1000_phy_unknown = 0, 35275eba5b6SRobert Mustacchi e1000_phy_none, 35375eba5b6SRobert Mustacchi e1000_phy_m88, 35475eba5b6SRobert Mustacchi e1000_phy_igp, 35575eba5b6SRobert Mustacchi e1000_phy_igp_2, 35675eba5b6SRobert Mustacchi e1000_phy_gg82563, 35775eba5b6SRobert Mustacchi e1000_phy_igp_3, 35875eba5b6SRobert Mustacchi e1000_phy_ife, 35975eba5b6SRobert Mustacchi e1000_phy_bm, 36075eba5b6SRobert Mustacchi e1000_phy_82578, 36175eba5b6SRobert Mustacchi e1000_phy_82577, 36275eba5b6SRobert Mustacchi e1000_phy_82579, 36375eba5b6SRobert Mustacchi e1000_phy_i217, 36475eba5b6SRobert Mustacchi e1000_phy_82580, 36575eba5b6SRobert Mustacchi e1000_phy_vf, 36675eba5b6SRobert Mustacchi e1000_phy_i210, 36775eba5b6SRobert Mustacchi }; 36875eba5b6SRobert Mustacchi 36975eba5b6SRobert Mustacchi enum e1000_bus_type { 37075eba5b6SRobert Mustacchi e1000_bus_type_unknown = 0, 37175eba5b6SRobert Mustacchi e1000_bus_type_pci, 37275eba5b6SRobert Mustacchi e1000_bus_type_pcix, 37375eba5b6SRobert Mustacchi e1000_bus_type_pci_express, 37475eba5b6SRobert Mustacchi e1000_bus_type_reserved 37575eba5b6SRobert Mustacchi }; 37675eba5b6SRobert Mustacchi 37775eba5b6SRobert Mustacchi enum e1000_bus_speed { 37875eba5b6SRobert Mustacchi e1000_bus_speed_unknown = 0, 37975eba5b6SRobert Mustacchi e1000_bus_speed_33, 38075eba5b6SRobert Mustacchi e1000_bus_speed_66, 38175eba5b6SRobert Mustacchi e1000_bus_speed_100, 38275eba5b6SRobert Mustacchi e1000_bus_speed_120, 38375eba5b6SRobert Mustacchi e1000_bus_speed_133, 38475eba5b6SRobert Mustacchi e1000_bus_speed_2500, 38575eba5b6SRobert Mustacchi e1000_bus_speed_5000, 38675eba5b6SRobert Mustacchi e1000_bus_speed_reserved 38775eba5b6SRobert Mustacchi }; 38875eba5b6SRobert Mustacchi 38975eba5b6SRobert Mustacchi enum e1000_bus_width { 39075eba5b6SRobert Mustacchi e1000_bus_width_unknown = 0, 39175eba5b6SRobert Mustacchi e1000_bus_width_pcie_x1, 39275eba5b6SRobert Mustacchi e1000_bus_width_pcie_x2, 39375eba5b6SRobert Mustacchi e1000_bus_width_pcie_x4 = 4, 39475eba5b6SRobert Mustacchi e1000_bus_width_pcie_x8 = 8, 39575eba5b6SRobert Mustacchi e1000_bus_width_32, 39675eba5b6SRobert Mustacchi e1000_bus_width_64, 39775eba5b6SRobert Mustacchi e1000_bus_width_reserved 39875eba5b6SRobert Mustacchi }; 39975eba5b6SRobert Mustacchi 40075eba5b6SRobert Mustacchi enum e1000_1000t_rx_status { 40175eba5b6SRobert Mustacchi e1000_1000t_rx_status_not_ok = 0, 40275eba5b6SRobert Mustacchi e1000_1000t_rx_status_ok, 40375eba5b6SRobert Mustacchi e1000_1000t_rx_status_undefined = 0xFF 40475eba5b6SRobert Mustacchi }; 40575eba5b6SRobert Mustacchi 40675eba5b6SRobert Mustacchi enum e1000_rev_polarity { 40775eba5b6SRobert Mustacchi e1000_rev_polarity_normal = 0, 40875eba5b6SRobert Mustacchi e1000_rev_polarity_reversed, 40975eba5b6SRobert Mustacchi e1000_rev_polarity_undefined = 0xFF 41075eba5b6SRobert Mustacchi }; 41175eba5b6SRobert Mustacchi 41275eba5b6SRobert Mustacchi enum e1000_fc_mode { 41375eba5b6SRobert Mustacchi e1000_fc_none = 0, 41475eba5b6SRobert Mustacchi e1000_fc_rx_pause, 41575eba5b6SRobert Mustacchi e1000_fc_tx_pause, 41675eba5b6SRobert Mustacchi e1000_fc_full, 41775eba5b6SRobert Mustacchi e1000_fc_default = 0xFF 41875eba5b6SRobert Mustacchi }; 41975eba5b6SRobert Mustacchi 42075eba5b6SRobert Mustacchi enum e1000_ffe_config { 42175eba5b6SRobert Mustacchi e1000_ffe_config_enabled = 0, 42275eba5b6SRobert Mustacchi e1000_ffe_config_active, 42375eba5b6SRobert Mustacchi e1000_ffe_config_blocked 42475eba5b6SRobert Mustacchi }; 42575eba5b6SRobert Mustacchi 42675eba5b6SRobert Mustacchi enum e1000_dsp_config { 42775eba5b6SRobert Mustacchi e1000_dsp_config_disabled = 0, 42875eba5b6SRobert Mustacchi e1000_dsp_config_enabled, 42975eba5b6SRobert Mustacchi e1000_dsp_config_activated, 43075eba5b6SRobert Mustacchi e1000_dsp_config_undefined = 0xFF 43175eba5b6SRobert Mustacchi }; 43275eba5b6SRobert Mustacchi 43375eba5b6SRobert Mustacchi enum e1000_ms_type { 43475eba5b6SRobert Mustacchi e1000_ms_hw_default = 0, 43575eba5b6SRobert Mustacchi e1000_ms_force_master, 43675eba5b6SRobert Mustacchi e1000_ms_force_slave, 43775eba5b6SRobert Mustacchi e1000_ms_auto 43875eba5b6SRobert Mustacchi }; 43975eba5b6SRobert Mustacchi 44075eba5b6SRobert Mustacchi enum e1000_smart_speed { 44175eba5b6SRobert Mustacchi e1000_smart_speed_default = 0, 44275eba5b6SRobert Mustacchi e1000_smart_speed_on, 44375eba5b6SRobert Mustacchi e1000_smart_speed_off 44475eba5b6SRobert Mustacchi }; 44575eba5b6SRobert Mustacchi 44675eba5b6SRobert Mustacchi enum e1000_serdes_link_state { 44775eba5b6SRobert Mustacchi e1000_serdes_link_down = 0, 44875eba5b6SRobert Mustacchi e1000_serdes_link_autoneg_progress, 44975eba5b6SRobert Mustacchi e1000_serdes_link_autoneg_complete, 45075eba5b6SRobert Mustacchi e1000_serdes_link_forced_up 45175eba5b6SRobert Mustacchi }; 45275eba5b6SRobert Mustacchi 453c124a83eSRobert Mustacchi #define __le16 u16 454c124a83eSRobert Mustacchi #define __le32 u32 455c124a83eSRobert Mustacchi #define __le64 u64 45675eba5b6SRobert Mustacchi /* Receive Descriptor */ 45775eba5b6SRobert Mustacchi struct e1000_rx_desc { 45875eba5b6SRobert Mustacchi __le64 buffer_addr; /* Address of the descriptor's data buffer */ 45975eba5b6SRobert Mustacchi __le16 length; /* Length of data DMAed into data buffer */ 46075eba5b6SRobert Mustacchi __le16 csum; /* Packet checksum */ 46175eba5b6SRobert Mustacchi u8 status; /* Descriptor status */ 46275eba5b6SRobert Mustacchi u8 errors; /* Descriptor Errors */ 46375eba5b6SRobert Mustacchi __le16 special; 46475eba5b6SRobert Mustacchi }; 46575eba5b6SRobert Mustacchi 46675eba5b6SRobert Mustacchi /* Receive Descriptor - Extended */ 46775eba5b6SRobert Mustacchi union e1000_rx_desc_extended { 46875eba5b6SRobert Mustacchi struct { 46975eba5b6SRobert Mustacchi __le64 buffer_addr; 47075eba5b6SRobert Mustacchi __le64 reserved; 47175eba5b6SRobert Mustacchi } read; 47275eba5b6SRobert Mustacchi struct { 47375eba5b6SRobert Mustacchi struct { 47475eba5b6SRobert Mustacchi __le32 mrq; /* Multiple Rx Queues */ 47575eba5b6SRobert Mustacchi union { 47675eba5b6SRobert Mustacchi __le32 rss; /* RSS Hash */ 47775eba5b6SRobert Mustacchi struct { 47875eba5b6SRobert Mustacchi __le16 ip_id; /* IP id */ 47975eba5b6SRobert Mustacchi __le16 csum; /* Packet Checksum */ 48075eba5b6SRobert Mustacchi } csum_ip; 48175eba5b6SRobert Mustacchi } hi_dword; 48275eba5b6SRobert Mustacchi } lower; 48375eba5b6SRobert Mustacchi struct { 48475eba5b6SRobert Mustacchi __le32 status_error; /* ext status/error */ 48575eba5b6SRobert Mustacchi __le16 length; 48675eba5b6SRobert Mustacchi __le16 vlan; /* VLAN tag */ 48775eba5b6SRobert Mustacchi } upper; 48875eba5b6SRobert Mustacchi } wb; /* writeback */ 48975eba5b6SRobert Mustacchi }; 49075eba5b6SRobert Mustacchi 49175eba5b6SRobert Mustacchi #define MAX_PS_BUFFERS 4 492c124a83eSRobert Mustacchi 493c124a83eSRobert Mustacchi /* Number of packet split data buffers (not including the header buffer) */ 494c124a83eSRobert Mustacchi #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 495c124a83eSRobert Mustacchi 49675eba5b6SRobert Mustacchi /* Receive Descriptor - Packet Split */ 49775eba5b6SRobert Mustacchi union e1000_rx_desc_packet_split { 49875eba5b6SRobert Mustacchi struct { 49975eba5b6SRobert Mustacchi /* one buffer for protocol header(s), three data buffers */ 50075eba5b6SRobert Mustacchi __le64 buffer_addr[MAX_PS_BUFFERS]; 50175eba5b6SRobert Mustacchi } read; 50275eba5b6SRobert Mustacchi struct { 50375eba5b6SRobert Mustacchi struct { 50475eba5b6SRobert Mustacchi __le32 mrq; /* Multiple Rx Queues */ 50575eba5b6SRobert Mustacchi union { 50675eba5b6SRobert Mustacchi __le32 rss; /* RSS Hash */ 50775eba5b6SRobert Mustacchi struct { 50875eba5b6SRobert Mustacchi __le16 ip_id; /* IP id */ 50975eba5b6SRobert Mustacchi __le16 csum; /* Packet Checksum */ 51075eba5b6SRobert Mustacchi } csum_ip; 51175eba5b6SRobert Mustacchi } hi_dword; 51275eba5b6SRobert Mustacchi } lower; 51375eba5b6SRobert Mustacchi struct { 51475eba5b6SRobert Mustacchi __le32 status_error; /* ext status/error */ 51575eba5b6SRobert Mustacchi __le16 length0; /* length of buffer 0 */ 51675eba5b6SRobert Mustacchi __le16 vlan; /* VLAN tag */ 51775eba5b6SRobert Mustacchi } middle; 51875eba5b6SRobert Mustacchi struct { 51975eba5b6SRobert Mustacchi __le16 header_status; 520c124a83eSRobert Mustacchi /* length of buffers 1-3 */ 521c124a83eSRobert Mustacchi __le16 length[PS_PAGE_BUFFERS]; 52275eba5b6SRobert Mustacchi } upper; 52375eba5b6SRobert Mustacchi __le64 reserved; 52475eba5b6SRobert Mustacchi } wb; /* writeback */ 52575eba5b6SRobert Mustacchi }; 52675eba5b6SRobert Mustacchi 52775eba5b6SRobert Mustacchi /* Transmit Descriptor */ 52875eba5b6SRobert Mustacchi struct e1000_tx_desc { 52975eba5b6SRobert Mustacchi __le64 buffer_addr; /* Address of the descriptor's data buffer */ 53075eba5b6SRobert Mustacchi union { 53175eba5b6SRobert Mustacchi __le32 data; 53275eba5b6SRobert Mustacchi struct { 53375eba5b6SRobert Mustacchi __le16 length; /* Data buffer length */ 53475eba5b6SRobert Mustacchi u8 cso; /* Checksum offset */ 53575eba5b6SRobert Mustacchi u8 cmd; /* Descriptor control */ 53675eba5b6SRobert Mustacchi } flags; 53775eba5b6SRobert Mustacchi } lower; 53875eba5b6SRobert Mustacchi union { 53975eba5b6SRobert Mustacchi __le32 data; 54075eba5b6SRobert Mustacchi struct { 54175eba5b6SRobert Mustacchi u8 status; /* Descriptor status */ 54275eba5b6SRobert Mustacchi u8 css; /* Checksum start */ 54375eba5b6SRobert Mustacchi __le16 special; 54475eba5b6SRobert Mustacchi } fields; 54575eba5b6SRobert Mustacchi } upper; 54675eba5b6SRobert Mustacchi }; 54775eba5b6SRobert Mustacchi 54875eba5b6SRobert Mustacchi /* Offload Context Descriptor */ 54975eba5b6SRobert Mustacchi struct e1000_context_desc { 55075eba5b6SRobert Mustacchi union { 55175eba5b6SRobert Mustacchi __le32 ip_config; 55275eba5b6SRobert Mustacchi struct { 55375eba5b6SRobert Mustacchi u8 ipcss; /* IP checksum start */ 55475eba5b6SRobert Mustacchi u8 ipcso; /* IP checksum offset */ 55575eba5b6SRobert Mustacchi __le16 ipcse; /* IP checksum end */ 55675eba5b6SRobert Mustacchi } ip_fields; 55775eba5b6SRobert Mustacchi } lower_setup; 55875eba5b6SRobert Mustacchi union { 55975eba5b6SRobert Mustacchi __le32 tcp_config; 56075eba5b6SRobert Mustacchi struct { 56175eba5b6SRobert Mustacchi u8 tucss; /* TCP checksum start */ 56275eba5b6SRobert Mustacchi u8 tucso; /* TCP checksum offset */ 56375eba5b6SRobert Mustacchi __le16 tucse; /* TCP checksum end */ 56475eba5b6SRobert Mustacchi } tcp_fields; 56575eba5b6SRobert Mustacchi } upper_setup; 56675eba5b6SRobert Mustacchi __le32 cmd_and_length; 56775eba5b6SRobert Mustacchi union { 56875eba5b6SRobert Mustacchi __le32 data; 56975eba5b6SRobert Mustacchi struct { 57075eba5b6SRobert Mustacchi u8 status; /* Descriptor status */ 57175eba5b6SRobert Mustacchi u8 hdr_len; /* Header length */ 57275eba5b6SRobert Mustacchi __le16 mss; /* Maximum segment size */ 57375eba5b6SRobert Mustacchi } fields; 57475eba5b6SRobert Mustacchi } tcp_seg_setup; 57575eba5b6SRobert Mustacchi }; 57675eba5b6SRobert Mustacchi 57775eba5b6SRobert Mustacchi /* Offload data descriptor */ 57875eba5b6SRobert Mustacchi struct e1000_data_desc { 57975eba5b6SRobert Mustacchi __le64 buffer_addr; /* Address of the descriptor's buffer address */ 58075eba5b6SRobert Mustacchi union { 58175eba5b6SRobert Mustacchi __le32 data; 58275eba5b6SRobert Mustacchi struct { 58375eba5b6SRobert Mustacchi __le16 length; /* Data buffer length */ 58475eba5b6SRobert Mustacchi u8 typ_len_ext; 58575eba5b6SRobert Mustacchi u8 cmd; 58675eba5b6SRobert Mustacchi } flags; 58775eba5b6SRobert Mustacchi } lower; 58875eba5b6SRobert Mustacchi union { 58975eba5b6SRobert Mustacchi __le32 data; 59075eba5b6SRobert Mustacchi struct { 59175eba5b6SRobert Mustacchi u8 status; /* Descriptor status */ 59275eba5b6SRobert Mustacchi u8 popts; /* Packet Options */ 59375eba5b6SRobert Mustacchi __le16 special; 59475eba5b6SRobert Mustacchi } fields; 59575eba5b6SRobert Mustacchi } upper; 59675eba5b6SRobert Mustacchi }; 59775eba5b6SRobert Mustacchi 59875eba5b6SRobert Mustacchi /* Statistics counters collected by the MAC */ 59975eba5b6SRobert Mustacchi struct e1000_hw_stats { 60075eba5b6SRobert Mustacchi u64 crcerrs; 60175eba5b6SRobert Mustacchi u64 algnerrc; 60275eba5b6SRobert Mustacchi u64 symerrs; 60375eba5b6SRobert Mustacchi u64 rxerrc; 60475eba5b6SRobert Mustacchi u64 mpc; 60575eba5b6SRobert Mustacchi u64 scc; 60675eba5b6SRobert Mustacchi u64 ecol; 60775eba5b6SRobert Mustacchi u64 mcc; 60875eba5b6SRobert Mustacchi u64 latecol; 60975eba5b6SRobert Mustacchi u64 colc; 61075eba5b6SRobert Mustacchi u64 dc; 61175eba5b6SRobert Mustacchi u64 tncrs; 61275eba5b6SRobert Mustacchi u64 sec; 61375eba5b6SRobert Mustacchi u64 cexterr; 61475eba5b6SRobert Mustacchi u64 rlec; 61575eba5b6SRobert Mustacchi u64 xonrxc; 61675eba5b6SRobert Mustacchi u64 xontxc; 61775eba5b6SRobert Mustacchi u64 xoffrxc; 61875eba5b6SRobert Mustacchi u64 xofftxc; 61975eba5b6SRobert Mustacchi u64 fcruc; 62075eba5b6SRobert Mustacchi u64 prc64; 62175eba5b6SRobert Mustacchi u64 prc127; 62275eba5b6SRobert Mustacchi u64 prc255; 62375eba5b6SRobert Mustacchi u64 prc511; 62475eba5b6SRobert Mustacchi u64 prc1023; 62575eba5b6SRobert Mustacchi u64 prc1522; 62675eba5b6SRobert Mustacchi u64 gprc; 62775eba5b6SRobert Mustacchi u64 bprc; 62875eba5b6SRobert Mustacchi u64 mprc; 62975eba5b6SRobert Mustacchi u64 gptc; 63075eba5b6SRobert Mustacchi u64 gorc; 63175eba5b6SRobert Mustacchi u64 gotc; 63275eba5b6SRobert Mustacchi u64 rnbc; 63375eba5b6SRobert Mustacchi u64 ruc; 63475eba5b6SRobert Mustacchi u64 rfc; 63575eba5b6SRobert Mustacchi u64 roc; 63675eba5b6SRobert Mustacchi u64 rjc; 63775eba5b6SRobert Mustacchi u64 mgprc; 63875eba5b6SRobert Mustacchi u64 mgpdc; 63975eba5b6SRobert Mustacchi u64 mgptc; 64075eba5b6SRobert Mustacchi u64 tor; 64175eba5b6SRobert Mustacchi u64 tot; 64275eba5b6SRobert Mustacchi u64 tpr; 64375eba5b6SRobert Mustacchi u64 tpt; 64475eba5b6SRobert Mustacchi u64 ptc64; 64575eba5b6SRobert Mustacchi u64 ptc127; 64675eba5b6SRobert Mustacchi u64 ptc255; 64775eba5b6SRobert Mustacchi u64 ptc511; 64875eba5b6SRobert Mustacchi u64 ptc1023; 64975eba5b6SRobert Mustacchi u64 ptc1522; 65075eba5b6SRobert Mustacchi u64 mptc; 65175eba5b6SRobert Mustacchi u64 bptc; 65275eba5b6SRobert Mustacchi u64 tsctc; 65375eba5b6SRobert Mustacchi u64 tsctfc; 65475eba5b6SRobert Mustacchi u64 iac; 65575eba5b6SRobert Mustacchi u64 icrxptc; 65675eba5b6SRobert Mustacchi u64 icrxatc; 65775eba5b6SRobert Mustacchi u64 ictxptc; 65875eba5b6SRobert Mustacchi u64 ictxatc; 65975eba5b6SRobert Mustacchi u64 ictxqec; 66075eba5b6SRobert Mustacchi u64 ictxqmtc; 66175eba5b6SRobert Mustacchi u64 icrxdmtc; 66275eba5b6SRobert Mustacchi u64 icrxoc; 66375eba5b6SRobert Mustacchi u64 cbtmpc; 66475eba5b6SRobert Mustacchi u64 htdpmc; 66575eba5b6SRobert Mustacchi u64 cbrdpc; 66675eba5b6SRobert Mustacchi u64 cbrmpc; 66775eba5b6SRobert Mustacchi u64 rpthc; 66875eba5b6SRobert Mustacchi u64 hgptc; 66975eba5b6SRobert Mustacchi u64 htcbdpc; 67075eba5b6SRobert Mustacchi u64 hgorc; 67175eba5b6SRobert Mustacchi u64 hgotc; 67275eba5b6SRobert Mustacchi u64 lenerrs; 67375eba5b6SRobert Mustacchi u64 scvpc; 67475eba5b6SRobert Mustacchi u64 hrmpc; 67575eba5b6SRobert Mustacchi u64 doosync; 67675eba5b6SRobert Mustacchi u64 o2bgptc; 67775eba5b6SRobert Mustacchi u64 o2bspc; 67875eba5b6SRobert Mustacchi u64 b2ospc; 67975eba5b6SRobert Mustacchi u64 b2ogprc; 68075eba5b6SRobert Mustacchi }; 68175eba5b6SRobert Mustacchi 68275eba5b6SRobert Mustacchi struct e1000_vf_stats { 68375eba5b6SRobert Mustacchi u64 base_gprc; 68475eba5b6SRobert Mustacchi u64 base_gptc; 68575eba5b6SRobert Mustacchi u64 base_gorc; 68675eba5b6SRobert Mustacchi u64 base_gotc; 68775eba5b6SRobert Mustacchi u64 base_mprc; 68875eba5b6SRobert Mustacchi u64 base_gotlbc; 68975eba5b6SRobert Mustacchi u64 base_gptlbc; 69075eba5b6SRobert Mustacchi u64 base_gorlbc; 69175eba5b6SRobert Mustacchi u64 base_gprlbc; 69275eba5b6SRobert Mustacchi 69375eba5b6SRobert Mustacchi u32 last_gprc; 69475eba5b6SRobert Mustacchi u32 last_gptc; 69575eba5b6SRobert Mustacchi u32 last_gorc; 69675eba5b6SRobert Mustacchi u32 last_gotc; 69775eba5b6SRobert Mustacchi u32 last_mprc; 69875eba5b6SRobert Mustacchi u32 last_gotlbc; 69975eba5b6SRobert Mustacchi u32 last_gptlbc; 70075eba5b6SRobert Mustacchi u32 last_gorlbc; 70175eba5b6SRobert Mustacchi u32 last_gprlbc; 70275eba5b6SRobert Mustacchi 70375eba5b6SRobert Mustacchi u64 gprc; 70475eba5b6SRobert Mustacchi u64 gptc; 70575eba5b6SRobert Mustacchi u64 gorc; 70675eba5b6SRobert Mustacchi u64 gotc; 70775eba5b6SRobert Mustacchi u64 mprc; 70875eba5b6SRobert Mustacchi u64 gotlbc; 70975eba5b6SRobert Mustacchi u64 gptlbc; 71075eba5b6SRobert Mustacchi u64 gorlbc; 71175eba5b6SRobert Mustacchi u64 gprlbc; 71275eba5b6SRobert Mustacchi }; 71375eba5b6SRobert Mustacchi 71475eba5b6SRobert Mustacchi struct e1000_phy_stats { 71575eba5b6SRobert Mustacchi u32 idle_errors; 71675eba5b6SRobert Mustacchi u32 receive_errors; 71775eba5b6SRobert Mustacchi }; 71875eba5b6SRobert Mustacchi 71975eba5b6SRobert Mustacchi struct e1000_host_mng_dhcp_cookie { 72075eba5b6SRobert Mustacchi u32 signature; 72175eba5b6SRobert Mustacchi u8 status; 72275eba5b6SRobert Mustacchi u8 reserved0; 72375eba5b6SRobert Mustacchi u16 vlan_id; 72475eba5b6SRobert Mustacchi u32 reserved1; 72575eba5b6SRobert Mustacchi u16 reserved2; 72675eba5b6SRobert Mustacchi u8 reserved3; 72775eba5b6SRobert Mustacchi u8 checksum; 72875eba5b6SRobert Mustacchi }; 72975eba5b6SRobert Mustacchi 73075eba5b6SRobert Mustacchi /* Host Interface "Rev 1" */ 73175eba5b6SRobert Mustacchi struct e1000_host_command_header { 73275eba5b6SRobert Mustacchi u8 command_id; 73375eba5b6SRobert Mustacchi u8 command_length; 73475eba5b6SRobert Mustacchi u8 command_options; 73575eba5b6SRobert Mustacchi u8 checksum; 73675eba5b6SRobert Mustacchi }; 73775eba5b6SRobert Mustacchi 73875eba5b6SRobert Mustacchi #define E1000_HI_MAX_DATA_LENGTH 252 73975eba5b6SRobert Mustacchi struct e1000_host_command_info { 74075eba5b6SRobert Mustacchi struct e1000_host_command_header command_header; 74175eba5b6SRobert Mustacchi u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 74275eba5b6SRobert Mustacchi }; 74375eba5b6SRobert Mustacchi 74475eba5b6SRobert Mustacchi /* Host Interface "Rev 2" */ 74575eba5b6SRobert Mustacchi struct e1000_host_mng_command_header { 74675eba5b6SRobert Mustacchi u8 command_id; 74775eba5b6SRobert Mustacchi u8 checksum; 74875eba5b6SRobert Mustacchi u16 reserved1; 74975eba5b6SRobert Mustacchi u16 reserved2; 75075eba5b6SRobert Mustacchi u16 command_length; 75175eba5b6SRobert Mustacchi }; 75275eba5b6SRobert Mustacchi 75375eba5b6SRobert Mustacchi #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 75475eba5b6SRobert Mustacchi struct e1000_host_mng_command_info { 75575eba5b6SRobert Mustacchi struct e1000_host_mng_command_header command_header; 75675eba5b6SRobert Mustacchi u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 75775eba5b6SRobert Mustacchi }; 75875eba5b6SRobert Mustacchi 75975eba5b6SRobert Mustacchi #include "e1000_mac.h" 76075eba5b6SRobert Mustacchi #include "e1000_phy.h" 76175eba5b6SRobert Mustacchi #include "e1000_nvm.h" 76275eba5b6SRobert Mustacchi #include "e1000_manage.h" 76375eba5b6SRobert Mustacchi #include "e1000_mbx.h" 76475eba5b6SRobert Mustacchi 76575eba5b6SRobert Mustacchi /* Function pointers for the MAC. */ 76675eba5b6SRobert Mustacchi struct e1000_mac_operations { 76775eba5b6SRobert Mustacchi s32 (*init_params)(struct e1000_hw *); 76875eba5b6SRobert Mustacchi s32 (*id_led_init)(struct e1000_hw *); 76975eba5b6SRobert Mustacchi s32 (*blink_led)(struct e1000_hw *); 77075eba5b6SRobert Mustacchi bool (*check_mng_mode)(struct e1000_hw *); 77175eba5b6SRobert Mustacchi s32 (*check_for_link)(struct e1000_hw *); 77275eba5b6SRobert Mustacchi s32 (*cleanup_led)(struct e1000_hw *); 77375eba5b6SRobert Mustacchi void (*clear_hw_cntrs)(struct e1000_hw *); 77475eba5b6SRobert Mustacchi void (*clear_vfta)(struct e1000_hw *); 77575eba5b6SRobert Mustacchi s32 (*get_bus_info)(struct e1000_hw *); 77675eba5b6SRobert Mustacchi void (*set_lan_id)(struct e1000_hw *); 77775eba5b6SRobert Mustacchi s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 77875eba5b6SRobert Mustacchi s32 (*led_on)(struct e1000_hw *); 77975eba5b6SRobert Mustacchi s32 (*led_off)(struct e1000_hw *); 78075eba5b6SRobert Mustacchi void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 78175eba5b6SRobert Mustacchi s32 (*reset_hw)(struct e1000_hw *); 78275eba5b6SRobert Mustacchi s32 (*init_hw)(struct e1000_hw *); 78375eba5b6SRobert Mustacchi void (*shutdown_serdes)(struct e1000_hw *); 78475eba5b6SRobert Mustacchi void (*power_up_serdes)(struct e1000_hw *); 78575eba5b6SRobert Mustacchi s32 (*setup_link)(struct e1000_hw *); 78675eba5b6SRobert Mustacchi s32 (*setup_physical_interface)(struct e1000_hw *); 78775eba5b6SRobert Mustacchi s32 (*setup_led)(struct e1000_hw *); 78875eba5b6SRobert Mustacchi void (*write_vfta)(struct e1000_hw *, u32, u32); 78975eba5b6SRobert Mustacchi void (*config_collision_dist)(struct e1000_hw *); 790c124a83eSRobert Mustacchi int (*rar_set)(struct e1000_hw *, u8*, u32); 79175eba5b6SRobert Mustacchi s32 (*read_mac_addr)(struct e1000_hw *); 79275eba5b6SRobert Mustacchi s32 (*validate_mdi_setting)(struct e1000_hw *); 79375eba5b6SRobert Mustacchi s32 (*set_obff_timer)(struct e1000_hw *, u32); 79475eba5b6SRobert Mustacchi s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 79575eba5b6SRobert Mustacchi void (*release_swfw_sync)(struct e1000_hw *, u16); 79675eba5b6SRobert Mustacchi }; 79775eba5b6SRobert Mustacchi 79875eba5b6SRobert Mustacchi /* When to use various PHY register access functions: 79975eba5b6SRobert Mustacchi * 80075eba5b6SRobert Mustacchi * Func Caller 80175eba5b6SRobert Mustacchi * Function Does Does When to use 80275eba5b6SRobert Mustacchi * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 80375eba5b6SRobert Mustacchi * X_reg L,P,A n/a for simple PHY reg accesses 80475eba5b6SRobert Mustacchi * X_reg_locked P,A L for multiple accesses of different regs 80575eba5b6SRobert Mustacchi * on different pages 80675eba5b6SRobert Mustacchi * X_reg_page A L,P for multiple accesses of different regs 80775eba5b6SRobert Mustacchi * on the same page 80875eba5b6SRobert Mustacchi * 80975eba5b6SRobert Mustacchi * Where X=[read|write], L=locking, P=sets page, A=register access 81075eba5b6SRobert Mustacchi * 81175eba5b6SRobert Mustacchi */ 81275eba5b6SRobert Mustacchi struct e1000_phy_operations { 81375eba5b6SRobert Mustacchi s32 (*init_params)(struct e1000_hw *); 81475eba5b6SRobert Mustacchi s32 (*acquire)(struct e1000_hw *); 81575eba5b6SRobert Mustacchi s32 (*cfg_on_link_up)(struct e1000_hw *); 81675eba5b6SRobert Mustacchi s32 (*check_polarity)(struct e1000_hw *); 81775eba5b6SRobert Mustacchi s32 (*check_reset_block)(struct e1000_hw *); 81875eba5b6SRobert Mustacchi s32 (*commit)(struct e1000_hw *); 81975eba5b6SRobert Mustacchi s32 (*force_speed_duplex)(struct e1000_hw *); 82075eba5b6SRobert Mustacchi s32 (*get_cfg_done)(struct e1000_hw *hw); 82175eba5b6SRobert Mustacchi s32 (*get_cable_length)(struct e1000_hw *); 82275eba5b6SRobert Mustacchi s32 (*get_info)(struct e1000_hw *); 82375eba5b6SRobert Mustacchi s32 (*set_page)(struct e1000_hw *, u16); 82475eba5b6SRobert Mustacchi s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 82575eba5b6SRobert Mustacchi s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 82675eba5b6SRobert Mustacchi s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 82775eba5b6SRobert Mustacchi void (*release)(struct e1000_hw *); 82875eba5b6SRobert Mustacchi s32 (*reset)(struct e1000_hw *); 82975eba5b6SRobert Mustacchi s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 83075eba5b6SRobert Mustacchi s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 83175eba5b6SRobert Mustacchi s32 (*write_reg)(struct e1000_hw *, u32, u16); 83275eba5b6SRobert Mustacchi s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 83375eba5b6SRobert Mustacchi s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 83475eba5b6SRobert Mustacchi void (*power_up)(struct e1000_hw *); 83575eba5b6SRobert Mustacchi void (*power_down)(struct e1000_hw *); 83675eba5b6SRobert Mustacchi s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 83775eba5b6SRobert Mustacchi s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 83875eba5b6SRobert Mustacchi }; 83975eba5b6SRobert Mustacchi 84075eba5b6SRobert Mustacchi /* Function pointers for the NVM. */ 84175eba5b6SRobert Mustacchi struct e1000_nvm_operations { 84275eba5b6SRobert Mustacchi s32 (*init_params)(struct e1000_hw *); 84375eba5b6SRobert Mustacchi s32 (*acquire)(struct e1000_hw *); 84475eba5b6SRobert Mustacchi s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 84575eba5b6SRobert Mustacchi void (*release)(struct e1000_hw *); 84675eba5b6SRobert Mustacchi void (*reload)(struct e1000_hw *); 84775eba5b6SRobert Mustacchi s32 (*update)(struct e1000_hw *); 84875eba5b6SRobert Mustacchi s32 (*valid_led_default)(struct e1000_hw *, u16 *); 84975eba5b6SRobert Mustacchi s32 (*validate)(struct e1000_hw *); 85075eba5b6SRobert Mustacchi s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 85175eba5b6SRobert Mustacchi }; 85275eba5b6SRobert Mustacchi 85375eba5b6SRobert Mustacchi struct e1000_mac_info { 85475eba5b6SRobert Mustacchi struct e1000_mac_operations ops; 85575eba5b6SRobert Mustacchi u8 addr[ETH_ADDR_LEN]; 85675eba5b6SRobert Mustacchi u8 perm_addr[ETH_ADDR_LEN]; 85775eba5b6SRobert Mustacchi 85875eba5b6SRobert Mustacchi enum e1000_mac_type type; 85975eba5b6SRobert Mustacchi 86075eba5b6SRobert Mustacchi u32 collision_delta; 86175eba5b6SRobert Mustacchi u32 ledctl_default; 86275eba5b6SRobert Mustacchi u32 ledctl_mode1; 86375eba5b6SRobert Mustacchi u32 ledctl_mode2; 86475eba5b6SRobert Mustacchi u32 mc_filter_type; 86575eba5b6SRobert Mustacchi u32 tx_packet_delta; 86675eba5b6SRobert Mustacchi u32 txcw; 86775eba5b6SRobert Mustacchi 86875eba5b6SRobert Mustacchi u16 current_ifs_val; 86975eba5b6SRobert Mustacchi u16 ifs_max_val; 87075eba5b6SRobert Mustacchi u16 ifs_min_val; 87175eba5b6SRobert Mustacchi u16 ifs_ratio; 87275eba5b6SRobert Mustacchi u16 ifs_step_size; 87375eba5b6SRobert Mustacchi u16 mta_reg_count; 87475eba5b6SRobert Mustacchi u16 uta_reg_count; 87575eba5b6SRobert Mustacchi 87675eba5b6SRobert Mustacchi /* Maximum size of the MTA register table in all supported adapters */ 87749b78600SRobert Mustacchi #define MAX_MTA_REG 128 87875eba5b6SRobert Mustacchi u32 mta_shadow[MAX_MTA_REG]; 87975eba5b6SRobert Mustacchi u16 rar_entry_count; 88075eba5b6SRobert Mustacchi 88175eba5b6SRobert Mustacchi u8 forced_speed_duplex; 88275eba5b6SRobert Mustacchi 88375eba5b6SRobert Mustacchi bool adaptive_ifs; 88475eba5b6SRobert Mustacchi bool has_fwsm; 88575eba5b6SRobert Mustacchi bool arc_subsystem_valid; 88675eba5b6SRobert Mustacchi bool asf_firmware_present; 88775eba5b6SRobert Mustacchi bool autoneg; 88875eba5b6SRobert Mustacchi bool autoneg_failed; 88975eba5b6SRobert Mustacchi bool get_link_status; 89075eba5b6SRobert Mustacchi bool in_ifs_mode; 89175eba5b6SRobert Mustacchi bool report_tx_early; 89275eba5b6SRobert Mustacchi enum e1000_serdes_link_state serdes_link_state; 89375eba5b6SRobert Mustacchi bool serdes_has_link; 89475eba5b6SRobert Mustacchi bool tx_pkt_filtering; 89549b78600SRobert Mustacchi u32 max_frame_size; 89675eba5b6SRobert Mustacchi }; 89775eba5b6SRobert Mustacchi 89875eba5b6SRobert Mustacchi struct e1000_phy_info { 89975eba5b6SRobert Mustacchi struct e1000_phy_operations ops; 90075eba5b6SRobert Mustacchi enum e1000_phy_type type; 90175eba5b6SRobert Mustacchi 90275eba5b6SRobert Mustacchi enum e1000_1000t_rx_status local_rx; 90375eba5b6SRobert Mustacchi enum e1000_1000t_rx_status remote_rx; 90475eba5b6SRobert Mustacchi enum e1000_ms_type ms_type; 90575eba5b6SRobert Mustacchi enum e1000_ms_type original_ms_type; 90675eba5b6SRobert Mustacchi enum e1000_rev_polarity cable_polarity; 90775eba5b6SRobert Mustacchi enum e1000_smart_speed smart_speed; 90875eba5b6SRobert Mustacchi 90975eba5b6SRobert Mustacchi u32 addr; 91075eba5b6SRobert Mustacchi u32 id; 91175eba5b6SRobert Mustacchi u32 reset_delay_us; /* in usec */ 91275eba5b6SRobert Mustacchi u32 revision; 91375eba5b6SRobert Mustacchi 91475eba5b6SRobert Mustacchi enum e1000_media_type media_type; 91575eba5b6SRobert Mustacchi 91675eba5b6SRobert Mustacchi u16 autoneg_advertised; 91775eba5b6SRobert Mustacchi u16 autoneg_mask; 91875eba5b6SRobert Mustacchi u16 cable_length; 91975eba5b6SRobert Mustacchi u16 max_cable_length; 92075eba5b6SRobert Mustacchi u16 min_cable_length; 92175eba5b6SRobert Mustacchi 92275eba5b6SRobert Mustacchi u8 mdix; 92375eba5b6SRobert Mustacchi 92475eba5b6SRobert Mustacchi bool disable_polarity_correction; 92575eba5b6SRobert Mustacchi bool is_mdix; 92675eba5b6SRobert Mustacchi bool polarity_correction; 92775eba5b6SRobert Mustacchi bool speed_downgraded; 92875eba5b6SRobert Mustacchi bool autoneg_wait_to_complete; 92975eba5b6SRobert Mustacchi }; 93075eba5b6SRobert Mustacchi 93175eba5b6SRobert Mustacchi struct e1000_nvm_info { 93275eba5b6SRobert Mustacchi struct e1000_nvm_operations ops; 93375eba5b6SRobert Mustacchi enum e1000_nvm_type type; 93475eba5b6SRobert Mustacchi enum e1000_nvm_override override; 93575eba5b6SRobert Mustacchi 93675eba5b6SRobert Mustacchi u32 flash_bank_size; 93775eba5b6SRobert Mustacchi u32 flash_base_addr; 93875eba5b6SRobert Mustacchi 93975eba5b6SRobert Mustacchi u16 word_size; 94075eba5b6SRobert Mustacchi u16 delay_usec; 94175eba5b6SRobert Mustacchi u16 address_bits; 94275eba5b6SRobert Mustacchi u16 opcode_bits; 94375eba5b6SRobert Mustacchi u16 page_size; 94475eba5b6SRobert Mustacchi }; 94575eba5b6SRobert Mustacchi 94675eba5b6SRobert Mustacchi struct e1000_bus_info { 94775eba5b6SRobert Mustacchi enum e1000_bus_type type; 94875eba5b6SRobert Mustacchi enum e1000_bus_speed speed; 94975eba5b6SRobert Mustacchi enum e1000_bus_width width; 95075eba5b6SRobert Mustacchi 95175eba5b6SRobert Mustacchi u16 func; 95275eba5b6SRobert Mustacchi u16 pci_cmd_word; 95375eba5b6SRobert Mustacchi }; 95475eba5b6SRobert Mustacchi 95575eba5b6SRobert Mustacchi struct e1000_fc_info { 95675eba5b6SRobert Mustacchi u32 high_water; /* Flow control high-water mark */ 95775eba5b6SRobert Mustacchi u32 low_water; /* Flow control low-water mark */ 95875eba5b6SRobert Mustacchi u16 pause_time; /* Flow control pause timer */ 95975eba5b6SRobert Mustacchi u16 refresh_time; /* Flow control refresh timer */ 96075eba5b6SRobert Mustacchi bool send_xon; /* Flow control send XON */ 96175eba5b6SRobert Mustacchi bool strict_ieee; /* Strict IEEE mode */ 96275eba5b6SRobert Mustacchi enum e1000_fc_mode current_mode; /* FC mode in effect */ 96375eba5b6SRobert Mustacchi enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 96475eba5b6SRobert Mustacchi }; 96575eba5b6SRobert Mustacchi 96675eba5b6SRobert Mustacchi struct e1000_mbx_operations { 96775eba5b6SRobert Mustacchi s32 (*init_params)(struct e1000_hw *hw); 96875eba5b6SRobert Mustacchi s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 96975eba5b6SRobert Mustacchi s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 97075eba5b6SRobert Mustacchi s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 97175eba5b6SRobert Mustacchi s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 97275eba5b6SRobert Mustacchi s32 (*check_for_msg)(struct e1000_hw *, u16); 97375eba5b6SRobert Mustacchi s32 (*check_for_ack)(struct e1000_hw *, u16); 97475eba5b6SRobert Mustacchi s32 (*check_for_rst)(struct e1000_hw *, u16); 97575eba5b6SRobert Mustacchi }; 97675eba5b6SRobert Mustacchi 97775eba5b6SRobert Mustacchi struct e1000_mbx_stats { 97875eba5b6SRobert Mustacchi u32 msgs_tx; 97975eba5b6SRobert Mustacchi u32 msgs_rx; 98075eba5b6SRobert Mustacchi 98175eba5b6SRobert Mustacchi u32 acks; 98275eba5b6SRobert Mustacchi u32 reqs; 98375eba5b6SRobert Mustacchi u32 rsts; 98475eba5b6SRobert Mustacchi }; 98575eba5b6SRobert Mustacchi 98675eba5b6SRobert Mustacchi struct e1000_mbx_info { 98775eba5b6SRobert Mustacchi struct e1000_mbx_operations ops; 98875eba5b6SRobert Mustacchi struct e1000_mbx_stats stats; 98975eba5b6SRobert Mustacchi u32 timeout; 99075eba5b6SRobert Mustacchi u32 usec_delay; 99175eba5b6SRobert Mustacchi u16 size; 99275eba5b6SRobert Mustacchi }; 99375eba5b6SRobert Mustacchi 99475eba5b6SRobert Mustacchi struct e1000_dev_spec_82541 { 99575eba5b6SRobert Mustacchi enum e1000_dsp_config dsp_config; 99675eba5b6SRobert Mustacchi enum e1000_ffe_config ffe_config; 99775eba5b6SRobert Mustacchi u32 tx_fifo_head; 99875eba5b6SRobert Mustacchi u32 tx_fifo_start; 99975eba5b6SRobert Mustacchi u32 tx_fifo_size; 100075eba5b6SRobert Mustacchi u16 dsp_reset_counter; 100175eba5b6SRobert Mustacchi u16 spd_default; 100275eba5b6SRobert Mustacchi bool phy_init_script; 100375eba5b6SRobert Mustacchi bool ttl_workaround; 100475eba5b6SRobert Mustacchi }; 100575eba5b6SRobert Mustacchi 100675eba5b6SRobert Mustacchi struct e1000_dev_spec_82542 { 100775eba5b6SRobert Mustacchi bool dma_fairness; 100875eba5b6SRobert Mustacchi }; 100975eba5b6SRobert Mustacchi 101075eba5b6SRobert Mustacchi struct e1000_dev_spec_82543 { 101175eba5b6SRobert Mustacchi u32 tbi_compatibility; 101275eba5b6SRobert Mustacchi bool dma_fairness; 101375eba5b6SRobert Mustacchi bool init_phy_disabled; 101475eba5b6SRobert Mustacchi }; 101575eba5b6SRobert Mustacchi 101675eba5b6SRobert Mustacchi struct e1000_dev_spec_82571 { 101775eba5b6SRobert Mustacchi bool laa_is_present; 101875eba5b6SRobert Mustacchi u32 smb_counter; 101975eba5b6SRobert Mustacchi E1000_MUTEX swflag_mutex; 102075eba5b6SRobert Mustacchi }; 102175eba5b6SRobert Mustacchi 102275eba5b6SRobert Mustacchi struct e1000_dev_spec_80003es2lan { 102375eba5b6SRobert Mustacchi bool mdic_wa_enable; 102475eba5b6SRobert Mustacchi }; 102575eba5b6SRobert Mustacchi 102675eba5b6SRobert Mustacchi struct e1000_shadow_ram { 102775eba5b6SRobert Mustacchi u16 value; 102875eba5b6SRobert Mustacchi bool modified; 102975eba5b6SRobert Mustacchi }; 103075eba5b6SRobert Mustacchi 103175eba5b6SRobert Mustacchi #define E1000_SHADOW_RAM_WORDS 2048 103275eba5b6SRobert Mustacchi 1033c124a83eSRobert Mustacchi /* I218 PHY Ultra Low Power (ULP) states */ 1034c124a83eSRobert Mustacchi enum e1000_ulp_state { 1035c124a83eSRobert Mustacchi e1000_ulp_state_unknown, 1036c124a83eSRobert Mustacchi e1000_ulp_state_off, 1037c124a83eSRobert Mustacchi e1000_ulp_state_on, 1038c124a83eSRobert Mustacchi }; 1039c124a83eSRobert Mustacchi 104075eba5b6SRobert Mustacchi struct e1000_dev_spec_ich8lan { 104175eba5b6SRobert Mustacchi bool kmrn_lock_loss_workaround_enabled; 104275eba5b6SRobert Mustacchi struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 104375eba5b6SRobert Mustacchi E1000_MUTEX nvm_mutex; 104475eba5b6SRobert Mustacchi E1000_MUTEX swflag_mutex; 104575eba5b6SRobert Mustacchi bool nvm_k1_enabled; 1046ea4c6b78SRobert Mustacchi bool disable_k1_off; 104775eba5b6SRobert Mustacchi bool eee_disable; 104875eba5b6SRobert Mustacchi u16 eee_lp_ability; 1049c124a83eSRobert Mustacchi enum e1000_ulp_state ulp_state; 1050ea4c6b78SRobert Mustacchi bool ulp_capability_disabled; 1051ea4c6b78SRobert Mustacchi bool during_suspend_flow; 1052ea4c6b78SRobert Mustacchi bool during_dpg_exit; 105375eba5b6SRobert Mustacchi }; 105475eba5b6SRobert Mustacchi 105575eba5b6SRobert Mustacchi struct e1000_dev_spec_82575 { 105675eba5b6SRobert Mustacchi bool sgmii_active; 105775eba5b6SRobert Mustacchi bool global_device_reset; 105875eba5b6SRobert Mustacchi bool eee_disable; 105975eba5b6SRobert Mustacchi bool module_plugged; 106075eba5b6SRobert Mustacchi bool clear_semaphore_once; 106175eba5b6SRobert Mustacchi u32 mtu; 106275eba5b6SRobert Mustacchi struct sfp_e1000_flags eth_flags; 1063c124a83eSRobert Mustacchi u8 media_port; 1064c124a83eSRobert Mustacchi bool media_changed; 106575eba5b6SRobert Mustacchi }; 106675eba5b6SRobert Mustacchi 106775eba5b6SRobert Mustacchi struct e1000_dev_spec_vf { 106875eba5b6SRobert Mustacchi u32 vf_number; 106975eba5b6SRobert Mustacchi u32 v2p_mailbox; 107075eba5b6SRobert Mustacchi }; 107175eba5b6SRobert Mustacchi 107275eba5b6SRobert Mustacchi struct e1000_hw { 107375eba5b6SRobert Mustacchi void *back; 107475eba5b6SRobert Mustacchi 107575eba5b6SRobert Mustacchi u8 *hw_addr; 107675eba5b6SRobert Mustacchi u8 *flash_address; 107775eba5b6SRobert Mustacchi unsigned long io_base; 107875eba5b6SRobert Mustacchi 107975eba5b6SRobert Mustacchi struct e1000_mac_info mac; 108075eba5b6SRobert Mustacchi struct e1000_fc_info fc; 108175eba5b6SRobert Mustacchi struct e1000_phy_info phy; 108275eba5b6SRobert Mustacchi struct e1000_nvm_info nvm; 108375eba5b6SRobert Mustacchi struct e1000_bus_info bus; 108475eba5b6SRobert Mustacchi struct e1000_mbx_info mbx; 108575eba5b6SRobert Mustacchi struct e1000_host_mng_dhcp_cookie mng_cookie; 108675eba5b6SRobert Mustacchi 108775eba5b6SRobert Mustacchi union { 108875eba5b6SRobert Mustacchi struct e1000_dev_spec_82541 _82541; 108975eba5b6SRobert Mustacchi struct e1000_dev_spec_82542 _82542; 109075eba5b6SRobert Mustacchi struct e1000_dev_spec_82543 _82543; 109175eba5b6SRobert Mustacchi struct e1000_dev_spec_82571 _82571; 109275eba5b6SRobert Mustacchi struct e1000_dev_spec_80003es2lan _80003es2lan; 109375eba5b6SRobert Mustacchi struct e1000_dev_spec_ich8lan ich8lan; 109475eba5b6SRobert Mustacchi struct e1000_dev_spec_82575 _82575; 109575eba5b6SRobert Mustacchi struct e1000_dev_spec_vf vf; 109675eba5b6SRobert Mustacchi } dev_spec; 109775eba5b6SRobert Mustacchi 109875eba5b6SRobert Mustacchi u16 device_id; 109975eba5b6SRobert Mustacchi u16 subsystem_vendor_id; 110075eba5b6SRobert Mustacchi u16 subsystem_device_id; 110175eba5b6SRobert Mustacchi u16 vendor_id; 110275eba5b6SRobert Mustacchi 110375eba5b6SRobert Mustacchi u8 revision_id; 110475eba5b6SRobert Mustacchi }; 110575eba5b6SRobert Mustacchi 110675eba5b6SRobert Mustacchi #include "e1000_82541.h" 110775eba5b6SRobert Mustacchi #include "e1000_82543.h" 110875eba5b6SRobert Mustacchi #include "e1000_82571.h" 110975eba5b6SRobert Mustacchi #include "e1000_80003es2lan.h" 111075eba5b6SRobert Mustacchi #include "e1000_ich8lan.h" 111175eba5b6SRobert Mustacchi #include "e1000_82575.h" 111275eba5b6SRobert Mustacchi #include "e1000_i210.h" 111375eba5b6SRobert Mustacchi 111475eba5b6SRobert Mustacchi /* These functions must be implemented by drivers */ 111575eba5b6SRobert Mustacchi void e1000_pci_clear_mwi(struct e1000_hw *hw); 111675eba5b6SRobert Mustacchi void e1000_pci_set_mwi(struct e1000_hw *hw); 111775eba5b6SRobert Mustacchi s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 111875eba5b6SRobert Mustacchi s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 111975eba5b6SRobert Mustacchi void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 112075eba5b6SRobert Mustacchi void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 112175eba5b6SRobert Mustacchi 112275eba5b6SRobert Mustacchi #endif 1123