175eba5b6SRobert Mustacchi /****************************************************************************** 275eba5b6SRobert Mustacchi 349b78600SRobert Mustacchi Copyright (c) 2001-2015, Intel Corporation 475eba5b6SRobert Mustacchi All rights reserved. 575eba5b6SRobert Mustacchi 675eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 775eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 875eba5b6SRobert Mustacchi 975eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1075eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 1175eba5b6SRobert Mustacchi 1275eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 1375eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1475eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 1575eba5b6SRobert Mustacchi 1675eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 1775eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 1875eba5b6SRobert Mustacchi this software without specific prior written permission. 1975eba5b6SRobert Mustacchi 2075eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2175eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2275eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2375eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2475eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2575eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2675eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2775eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2875eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2975eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3075eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 3175eba5b6SRobert Mustacchi 3275eba5b6SRobert Mustacchi ******************************************************************************/ 3375eba5b6SRobert Mustacchi /*$FreeBSD$*/ 3475eba5b6SRobert Mustacchi 3575eba5b6SRobert Mustacchi #ifndef _E1000_DEFINES_H_ 3675eba5b6SRobert Mustacchi #define _E1000_DEFINES_H_ 3775eba5b6SRobert Mustacchi 3875eba5b6SRobert Mustacchi /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 3975eba5b6SRobert Mustacchi #define REQ_TX_DESCRIPTOR_MULTIPLE 8 4075eba5b6SRobert Mustacchi #define REQ_RX_DESCRIPTOR_MULTIPLE 8 4175eba5b6SRobert Mustacchi 4275eba5b6SRobert Mustacchi /* Definitions for power management and wakeup registers */ 4375eba5b6SRobert Mustacchi /* Wake Up Control */ 4475eba5b6SRobert Mustacchi #define E1000_WUC_APME 0x00000001 /* APM Enable */ 4575eba5b6SRobert Mustacchi #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 46c124a83eSRobert Mustacchi #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 47c124a83eSRobert Mustacchi #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 4875eba5b6SRobert Mustacchi #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 4975eba5b6SRobert Mustacchi 5075eba5b6SRobert Mustacchi /* Wake Up Filter Control */ 5175eba5b6SRobert Mustacchi #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 5275eba5b6SRobert Mustacchi #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 5375eba5b6SRobert Mustacchi #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 5475eba5b6SRobert Mustacchi #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 5575eba5b6SRobert Mustacchi #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 5675eba5b6SRobert Mustacchi #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 5775eba5b6SRobert Mustacchi #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 5875eba5b6SRobert Mustacchi #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 5975eba5b6SRobert Mustacchi 6075eba5b6SRobert Mustacchi /* Wake Up Status */ 6175eba5b6SRobert Mustacchi #define E1000_WUS_LNKC E1000_WUFC_LNKC 6275eba5b6SRobert Mustacchi #define E1000_WUS_MAG E1000_WUFC_MAG 6375eba5b6SRobert Mustacchi #define E1000_WUS_EX E1000_WUFC_EX 6475eba5b6SRobert Mustacchi #define E1000_WUS_MC E1000_WUFC_MC 6575eba5b6SRobert Mustacchi #define E1000_WUS_BC E1000_WUFC_BC 6675eba5b6SRobert Mustacchi 6775eba5b6SRobert Mustacchi /* Extended Device Control */ 6875eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 6975eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 7075eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 7175eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 7275eba5b6SRobert Mustacchi /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 7375eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 7475eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 7575eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 7675eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 7775eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 7875eba5b6SRobert Mustacchi /* Physical Func Reset Done Indication */ 7975eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_PFRSTD 0x00004000 80c124a83eSRobert Mustacchi #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ 8175eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 8275eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 8375eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 8475eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 8575eba5b6SRobert Mustacchi /* Offset of the link mode field in Ctrl Ext register */ 8675eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 8775eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 8875eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 8975eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 9075eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 9175eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_EIAME 0x01000000 9275eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_IRCA 0x00000001 9375eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 9475eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 9575eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 9675eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LSECCK 0x00001000 9775eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_PHYPDEN 0x00100000 9875eba5b6SRobert Mustacchi #define E1000_I2CCMD_REG_ADDR_SHIFT 16 9975eba5b6SRobert Mustacchi #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 10075eba5b6SRobert Mustacchi #define E1000_I2CCMD_OPCODE_READ 0x08000000 10175eba5b6SRobert Mustacchi #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 10275eba5b6SRobert Mustacchi #define E1000_I2CCMD_READY 0x20000000 10375eba5b6SRobert Mustacchi #define E1000_I2CCMD_ERROR 0x80000000 10475eba5b6SRobert Mustacchi #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 10575eba5b6SRobert Mustacchi #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 10675eba5b6SRobert Mustacchi #define E1000_MAX_SGMII_PHY_REG_ADDR 255 10775eba5b6SRobert Mustacchi #define E1000_I2CCMD_PHY_TIMEOUT 200 10875eba5b6SRobert Mustacchi #define E1000_IVAR_VALID 0x80 10975eba5b6SRobert Mustacchi #define E1000_GPIE_NSICR 0x00000001 11075eba5b6SRobert Mustacchi #define E1000_GPIE_MSIX_MODE 0x00000010 11175eba5b6SRobert Mustacchi #define E1000_GPIE_EIAME 0x40000000 11275eba5b6SRobert Mustacchi #define E1000_GPIE_PBA 0x80000000 11375eba5b6SRobert Mustacchi 11475eba5b6SRobert Mustacchi /* Receive Descriptor bit definitions */ 11575eba5b6SRobert Mustacchi #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 11675eba5b6SRobert Mustacchi #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 11775eba5b6SRobert Mustacchi #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 11875eba5b6SRobert Mustacchi #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 11975eba5b6SRobert Mustacchi #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 12075eba5b6SRobert Mustacchi #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 12175eba5b6SRobert Mustacchi #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 12275eba5b6SRobert Mustacchi #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 12375eba5b6SRobert Mustacchi #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 12475eba5b6SRobert Mustacchi #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 12575eba5b6SRobert Mustacchi #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 12675eba5b6SRobert Mustacchi #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 12775eba5b6SRobert Mustacchi #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 12875eba5b6SRobert Mustacchi #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 12975eba5b6SRobert Mustacchi #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 13075eba5b6SRobert Mustacchi #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 13175eba5b6SRobert Mustacchi #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 13275eba5b6SRobert Mustacchi #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 13375eba5b6SRobert Mustacchi #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 13475eba5b6SRobert Mustacchi 13575eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 13675eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_LB 0x00040000 13775eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_CE 0x01000000 13875eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_SE 0x02000000 13975eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_SEQ 0x04000000 14075eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_CXE 0x10000000 14175eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_TCPE 0x20000000 14275eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_IPE 0x40000000 14375eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_RXE 0x80000000 14475eba5b6SRobert Mustacchi 14575eba5b6SRobert Mustacchi /* mask to determine if packets should be dropped due to frame errors */ 14675eba5b6SRobert Mustacchi #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 14775eba5b6SRobert Mustacchi E1000_RXD_ERR_CE | \ 14875eba5b6SRobert Mustacchi E1000_RXD_ERR_SE | \ 14975eba5b6SRobert Mustacchi E1000_RXD_ERR_SEQ | \ 15075eba5b6SRobert Mustacchi E1000_RXD_ERR_CXE | \ 15175eba5b6SRobert Mustacchi E1000_RXD_ERR_RXE) 15275eba5b6SRobert Mustacchi 15375eba5b6SRobert Mustacchi /* Same mask, but for extended and packet split descriptors */ 15475eba5b6SRobert Mustacchi #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 15575eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_CE | \ 15675eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_SE | \ 15775eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_SEQ | \ 15875eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_CXE | \ 15975eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_RXE) 16075eba5b6SRobert Mustacchi 16149b78600SRobert Mustacchi #define E1000_MRQC_RSS_ENABLE_2Q 0x00000001 16275eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 16375eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 16475eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 16575eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 16649b78600SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 16775eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 16875eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 16975eba5b6SRobert Mustacchi 17075eba5b6SRobert Mustacchi #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 17175eba5b6SRobert Mustacchi 17275eba5b6SRobert Mustacchi /* Management Control */ 17375eba5b6SRobert Mustacchi #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 17475eba5b6SRobert Mustacchi #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 17575eba5b6SRobert Mustacchi #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 17675eba5b6SRobert Mustacchi #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 17775eba5b6SRobert Mustacchi #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 17875eba5b6SRobert Mustacchi /* Enable MAC address filtering */ 17975eba5b6SRobert Mustacchi #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 18075eba5b6SRobert Mustacchi /* Enable MNG packets to host memory */ 18175eba5b6SRobert Mustacchi #define E1000_MANC_EN_MNG2HOST 0x00200000 18275eba5b6SRobert Mustacchi 18375eba5b6SRobert Mustacchi #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 18475eba5b6SRobert Mustacchi #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 18575eba5b6SRobert Mustacchi #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 18675eba5b6SRobert Mustacchi #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 18775eba5b6SRobert Mustacchi 18875eba5b6SRobert Mustacchi /* Receive Control */ 18975eba5b6SRobert Mustacchi #define E1000_RCTL_RST 0x00000001 /* Software reset */ 19075eba5b6SRobert Mustacchi #define E1000_RCTL_EN 0x00000002 /* enable */ 19175eba5b6SRobert Mustacchi #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 19275eba5b6SRobert Mustacchi #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 19375eba5b6SRobert Mustacchi #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 19475eba5b6SRobert Mustacchi #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 19575eba5b6SRobert Mustacchi #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 19675eba5b6SRobert Mustacchi #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 19775eba5b6SRobert Mustacchi #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 19875eba5b6SRobert Mustacchi #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 19975eba5b6SRobert Mustacchi #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 20049b78600SRobert Mustacchi #define E1000_RCTL_RDMTS_HEX 0x00010000 20149b78600SRobert Mustacchi #define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX 20275eba5b6SRobert Mustacchi #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 20375eba5b6SRobert Mustacchi #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 20475eba5b6SRobert Mustacchi #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 20575eba5b6SRobert Mustacchi /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 20675eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 20775eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 20875eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 20975eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 21075eba5b6SRobert Mustacchi /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 21175eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 21275eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 21375eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 21475eba5b6SRobert Mustacchi #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 21575eba5b6SRobert Mustacchi #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 21675eba5b6SRobert Mustacchi #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 21775eba5b6SRobert Mustacchi #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 21875eba5b6SRobert Mustacchi #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 21975eba5b6SRobert Mustacchi #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 22075eba5b6SRobert Mustacchi #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 22175eba5b6SRobert Mustacchi 22275eba5b6SRobert Mustacchi /* Use byte values for the following shift parameters 22375eba5b6SRobert Mustacchi * Usage: 22475eba5b6SRobert Mustacchi * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 22575eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE0_MASK) | 22675eba5b6SRobert Mustacchi * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 22775eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE1_MASK) | 22875eba5b6SRobert Mustacchi * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 22975eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE2_MASK) | 23075eba5b6SRobert Mustacchi * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 23175eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE3_MASK)) 23275eba5b6SRobert Mustacchi * where value0 = [128..16256], default=256 23375eba5b6SRobert Mustacchi * value1 = [1024..64512], default=4096 23475eba5b6SRobert Mustacchi * value2 = [0..64512], default=4096 23575eba5b6SRobert Mustacchi * value3 = [0..64512], default=0 23675eba5b6SRobert Mustacchi */ 23775eba5b6SRobert Mustacchi 23875eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 23975eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 24075eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 24175eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 24275eba5b6SRobert Mustacchi 24375eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 24475eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 24575eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 24675eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 24775eba5b6SRobert Mustacchi 24875eba5b6SRobert Mustacchi /* SWFW_SYNC Definitions */ 24975eba5b6SRobert Mustacchi #define E1000_SWFW_EEP_SM 0x01 25075eba5b6SRobert Mustacchi #define E1000_SWFW_PHY0_SM 0x02 25175eba5b6SRobert Mustacchi #define E1000_SWFW_PHY1_SM 0x04 25275eba5b6SRobert Mustacchi #define E1000_SWFW_CSR_SM 0x08 25375eba5b6SRobert Mustacchi #define E1000_SWFW_PHY2_SM 0x20 25475eba5b6SRobert Mustacchi #define E1000_SWFW_PHY3_SM 0x40 255*2509632aSRobert Mustacchi #define E1000_SWFW_PWRTS_SM 0x80 25675eba5b6SRobert Mustacchi #define E1000_SWFW_SW_MNG_SM 0x400 25775eba5b6SRobert Mustacchi 25875eba5b6SRobert Mustacchi /* Device Control */ 25975eba5b6SRobert Mustacchi #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 26075eba5b6SRobert Mustacchi #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 26175eba5b6SRobert Mustacchi #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 26275eba5b6SRobert Mustacchi #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 26375eba5b6SRobert Mustacchi #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 26475eba5b6SRobert Mustacchi #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 26575eba5b6SRobert Mustacchi #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 26675eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 26775eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 26875eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 26975eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 27075eba5b6SRobert Mustacchi #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 27175eba5b6SRobert Mustacchi #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 27275eba5b6SRobert Mustacchi #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 27375eba5b6SRobert Mustacchi #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 27475eba5b6SRobert Mustacchi #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 27575eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 27675eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 27775eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 27875eba5b6SRobert Mustacchi #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 27975eba5b6SRobert Mustacchi #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 28075eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 28175eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 28275eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 28375eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 28475eba5b6SRobert Mustacchi #define E1000_CTRL_RST 0x04000000 /* Global reset */ 28575eba5b6SRobert Mustacchi #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 28675eba5b6SRobert Mustacchi #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 28775eba5b6SRobert Mustacchi #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 28875eba5b6SRobert Mustacchi #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 28975eba5b6SRobert Mustacchi #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 29075eba5b6SRobert Mustacchi 29175eba5b6SRobert Mustacchi #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 29275eba5b6SRobert Mustacchi #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 29375eba5b6SRobert Mustacchi #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 29475eba5b6SRobert Mustacchi #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 29575eba5b6SRobert Mustacchi 29675eba5b6SRobert Mustacchi #define E1000_CONNSW_ENRGSRC 0x4 29775eba5b6SRobert Mustacchi #define E1000_CONNSW_PHYSD 0x400 298c124a83eSRobert Mustacchi #define E1000_CONNSW_PHY_PDN 0x800 29975eba5b6SRobert Mustacchi #define E1000_CONNSW_SERDESD 0x200 300c124a83eSRobert Mustacchi #define E1000_CONNSW_AUTOSENSE_CONF 0x2 301c124a83eSRobert Mustacchi #define E1000_CONNSW_AUTOSENSE_EN 0x1 30275eba5b6SRobert Mustacchi #define E1000_PCS_CFG_PCS_EN 8 30375eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FLV_LINK_UP 1 30475eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSV_10 0 30575eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSV_100 2 30675eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSV_1000 4 30775eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FDV_FULL 8 30875eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSD 0x10 30975eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FORCE_LINK 0x20 31075eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 31175eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_AN_ENABLE 0x10000 31275eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_AN_RESTART 0x20000 31375eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 31475eba5b6SRobert Mustacchi #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 31575eba5b6SRobert Mustacchi 31675eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_LINK_OK 1 31775eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_SPEED_100 2 31875eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_SPEED_1000 4 31975eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_DUPLEX_FULL 8 32075eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_SYNK_OK 0x10 32175eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 32275eba5b6SRobert Mustacchi 32375eba5b6SRobert Mustacchi /* Device Status */ 32475eba5b6SRobert Mustacchi #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 32575eba5b6SRobert Mustacchi #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 32675eba5b6SRobert Mustacchi #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 32775eba5b6SRobert Mustacchi #define E1000_STATUS_FUNC_SHIFT 2 32875eba5b6SRobert Mustacchi #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 32975eba5b6SRobert Mustacchi #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 33075eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_MASK 0x000000C0 33175eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 33275eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 33375eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 33475eba5b6SRobert Mustacchi #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 33575eba5b6SRobert Mustacchi #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 33675eba5b6SRobert Mustacchi #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 33775eba5b6SRobert Mustacchi #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 33875eba5b6SRobert Mustacchi #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 339c124a83eSRobert Mustacchi #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 340c124a83eSRobert Mustacchi #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 34175eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 34275eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 34375eba5b6SRobert Mustacchi 34475eba5b6SRobert Mustacchi /* Constants used to interpret the masked PCI-X bus speed. */ 34575eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ 34675eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ 34775eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ 34875eba5b6SRobert Mustacchi 34975eba5b6SRobert Mustacchi #define SPEED_10 10 35075eba5b6SRobert Mustacchi #define SPEED_100 100 35175eba5b6SRobert Mustacchi #define SPEED_1000 1000 352c124a83eSRobert Mustacchi #define SPEED_2500 2500 35375eba5b6SRobert Mustacchi #define HALF_DUPLEX 1 35475eba5b6SRobert Mustacchi #define FULL_DUPLEX 2 35575eba5b6SRobert Mustacchi 35675eba5b6SRobert Mustacchi #define PHY_FORCE_TIME 20 35775eba5b6SRobert Mustacchi 35875eba5b6SRobert Mustacchi #define ADVERTISE_10_HALF 0x0001 35975eba5b6SRobert Mustacchi #define ADVERTISE_10_FULL 0x0002 36075eba5b6SRobert Mustacchi #define ADVERTISE_100_HALF 0x0004 36175eba5b6SRobert Mustacchi #define ADVERTISE_100_FULL 0x0008 36275eba5b6SRobert Mustacchi #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 36375eba5b6SRobert Mustacchi #define ADVERTISE_1000_FULL 0x0020 36475eba5b6SRobert Mustacchi 36575eba5b6SRobert Mustacchi /* 1000/H is not supported, nor spec-compliant. */ 36675eba5b6SRobert Mustacchi #define E1000_ALL_SPEED_DUPLEX ( \ 36775eba5b6SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 36875eba5b6SRobert Mustacchi ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 36975eba5b6SRobert Mustacchi #define E1000_ALL_NOT_GIG ( \ 37075eba5b6SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 37175eba5b6SRobert Mustacchi ADVERTISE_100_FULL) 37275eba5b6SRobert Mustacchi #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 37375eba5b6SRobert Mustacchi #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 37475eba5b6SRobert Mustacchi #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 37575eba5b6SRobert Mustacchi 37675eba5b6SRobert Mustacchi #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 37775eba5b6SRobert Mustacchi 37875eba5b6SRobert Mustacchi /* LED Control */ 37975eba5b6SRobert Mustacchi #define E1000_PHY_LED0_MODE_MASK 0x00000007 38075eba5b6SRobert Mustacchi #define E1000_PHY_LED0_IVRT 0x00000008 38175eba5b6SRobert Mustacchi #define E1000_PHY_LED0_MASK 0x0000001F 38275eba5b6SRobert Mustacchi 38375eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 38475eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_MODE_SHIFT 0 38575eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_IVRT 0x00000040 38675eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_BLINK 0x00000080 38775eba5b6SRobert Mustacchi 38875eba5b6SRobert Mustacchi #define E1000_LEDCTL_MODE_LINK_UP 0x2 38975eba5b6SRobert Mustacchi #define E1000_LEDCTL_MODE_LED_ON 0xE 39075eba5b6SRobert Mustacchi #define E1000_LEDCTL_MODE_LED_OFF 0xF 39175eba5b6SRobert Mustacchi 39275eba5b6SRobert Mustacchi /* Transmit Descriptor bit definitions */ 39375eba5b6SRobert Mustacchi #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 39475eba5b6SRobert Mustacchi #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 39575eba5b6SRobert Mustacchi #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 39675eba5b6SRobert Mustacchi #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 39775eba5b6SRobert Mustacchi #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 39875eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 39975eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 40075eba5b6SRobert Mustacchi #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 40175eba5b6SRobert Mustacchi #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 40275eba5b6SRobert Mustacchi #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 40375eba5b6SRobert Mustacchi #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 40475eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 40575eba5b6SRobert Mustacchi #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 40675eba5b6SRobert Mustacchi #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 40775eba5b6SRobert Mustacchi #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 40875eba5b6SRobert Mustacchi #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 40975eba5b6SRobert Mustacchi #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 41075eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 41175eba5b6SRobert Mustacchi #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 41275eba5b6SRobert Mustacchi #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 41375eba5b6SRobert Mustacchi #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 41475eba5b6SRobert Mustacchi 41575eba5b6SRobert Mustacchi /* Transmit Control */ 41675eba5b6SRobert Mustacchi #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 41775eba5b6SRobert Mustacchi #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 41875eba5b6SRobert Mustacchi #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 41975eba5b6SRobert Mustacchi #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 42075eba5b6SRobert Mustacchi #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 42175eba5b6SRobert Mustacchi #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 42275eba5b6SRobert Mustacchi 42375eba5b6SRobert Mustacchi /* Transmit Arbitration Count */ 42475eba5b6SRobert Mustacchi #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 42575eba5b6SRobert Mustacchi 42675eba5b6SRobert Mustacchi /* SerDes Control */ 42775eba5b6SRobert Mustacchi #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 42875eba5b6SRobert Mustacchi #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 42975eba5b6SRobert Mustacchi 43075eba5b6SRobert Mustacchi /* Receive Checksum Control */ 43175eba5b6SRobert Mustacchi #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 43275eba5b6SRobert Mustacchi #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 43375eba5b6SRobert Mustacchi #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 43475eba5b6SRobert Mustacchi #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 43575eba5b6SRobert Mustacchi #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 43675eba5b6SRobert Mustacchi 43775eba5b6SRobert Mustacchi /* Header split receive */ 43875eba5b6SRobert Mustacchi #define E1000_RFCTL_NFSW_DIS 0x00000040 43975eba5b6SRobert Mustacchi #define E1000_RFCTL_NFSR_DIS 0x00000080 44075eba5b6SRobert Mustacchi #define E1000_RFCTL_ACK_DIS 0x00001000 44175eba5b6SRobert Mustacchi #define E1000_RFCTL_EXTEN 0x00008000 44275eba5b6SRobert Mustacchi #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 44375eba5b6SRobert Mustacchi #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 44475eba5b6SRobert Mustacchi #define E1000_RFCTL_LEF 0x00040000 44575eba5b6SRobert Mustacchi 44675eba5b6SRobert Mustacchi /* Collision related configuration parameters */ 44775eba5b6SRobert Mustacchi #define E1000_COLLISION_THRESHOLD 15 44875eba5b6SRobert Mustacchi #define E1000_CT_SHIFT 4 44975eba5b6SRobert Mustacchi #define E1000_COLLISION_DISTANCE 63 45075eba5b6SRobert Mustacchi #define E1000_COLD_SHIFT 12 45175eba5b6SRobert Mustacchi 45275eba5b6SRobert Mustacchi /* Default values for the transmit IPG register */ 45375eba5b6SRobert Mustacchi #define DEFAULT_82542_TIPG_IPGT 10 45475eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGT_FIBER 9 45575eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGT_COPPER 8 45675eba5b6SRobert Mustacchi 45775eba5b6SRobert Mustacchi #define E1000_TIPG_IPGT_MASK 0x000003FF 45875eba5b6SRobert Mustacchi 45975eba5b6SRobert Mustacchi #define DEFAULT_82542_TIPG_IPGR1 2 46075eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGR1 8 46175eba5b6SRobert Mustacchi #define E1000_TIPG_IPGR1_SHIFT 10 46275eba5b6SRobert Mustacchi 46375eba5b6SRobert Mustacchi #define DEFAULT_82542_TIPG_IPGR2 10 46475eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGR2 6 46575eba5b6SRobert Mustacchi #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 46675eba5b6SRobert Mustacchi #define E1000_TIPG_IPGR2_SHIFT 20 46775eba5b6SRobert Mustacchi 46875eba5b6SRobert Mustacchi /* Ethertype field values */ 46975eba5b6SRobert Mustacchi #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 47075eba5b6SRobert Mustacchi 47175eba5b6SRobert Mustacchi #define ETHERNET_FCS_SIZE 4 47275eba5b6SRobert Mustacchi #define MAX_JUMBO_FRAME_SIZE 0x3F00 473c124a83eSRobert Mustacchi #define E1000_TX_PTR_GAP 0x1F 47475eba5b6SRobert Mustacchi 47575eba5b6SRobert Mustacchi /* Extended Configuration Control and Size */ 47675eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 47775eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 47875eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 47975eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 48075eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 48175eba5b6SRobert Mustacchi #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 48275eba5b6SRobert Mustacchi #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 48375eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 48475eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 48575eba5b6SRobert Mustacchi 48675eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 48775eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 48875eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 48975eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 49075eba5b6SRobert Mustacchi 49175eba5b6SRobert Mustacchi #define E1000_KABGTXD_BGSQLBIAS 0x00050000 49275eba5b6SRobert Mustacchi 49375eba5b6SRobert Mustacchi /* Low Power IDLE Control */ 49475eba5b6SRobert Mustacchi #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 49575eba5b6SRobert Mustacchi 49675eba5b6SRobert Mustacchi /* PBA constants */ 49775eba5b6SRobert Mustacchi #define E1000_PBA_8K 0x0008 /* 8KB */ 49875eba5b6SRobert Mustacchi #define E1000_PBA_10K 0x000A /* 10KB */ 49975eba5b6SRobert Mustacchi #define E1000_PBA_12K 0x000C /* 12KB */ 50075eba5b6SRobert Mustacchi #define E1000_PBA_14K 0x000E /* 14KB */ 50175eba5b6SRobert Mustacchi #define E1000_PBA_16K 0x0010 /* 16KB */ 50275eba5b6SRobert Mustacchi #define E1000_PBA_18K 0x0012 50375eba5b6SRobert Mustacchi #define E1000_PBA_20K 0x0014 50475eba5b6SRobert Mustacchi #define E1000_PBA_22K 0x0016 50575eba5b6SRobert Mustacchi #define E1000_PBA_24K 0x0018 50675eba5b6SRobert Mustacchi #define E1000_PBA_26K 0x001A 50775eba5b6SRobert Mustacchi #define E1000_PBA_30K 0x001E 50875eba5b6SRobert Mustacchi #define E1000_PBA_32K 0x0020 50975eba5b6SRobert Mustacchi #define E1000_PBA_34K 0x0022 51075eba5b6SRobert Mustacchi #define E1000_PBA_35K 0x0023 51175eba5b6SRobert Mustacchi #define E1000_PBA_38K 0x0026 51275eba5b6SRobert Mustacchi #define E1000_PBA_40K 0x0028 51375eba5b6SRobert Mustacchi #define E1000_PBA_48K 0x0030 /* 48KB */ 51475eba5b6SRobert Mustacchi #define E1000_PBA_64K 0x0040 /* 64KB */ 51575eba5b6SRobert Mustacchi 51675eba5b6SRobert Mustacchi #define E1000_PBA_RXA_MASK 0xFFFF 51775eba5b6SRobert Mustacchi 51875eba5b6SRobert Mustacchi #define E1000_PBS_16K E1000_PBA_16K 51975eba5b6SRobert Mustacchi 52075eba5b6SRobert Mustacchi /* Uncorrectable/correctable ECC Error counts and enable bits */ 52175eba5b6SRobert Mustacchi #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 52275eba5b6SRobert Mustacchi #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 52375eba5b6SRobert Mustacchi #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 52475eba5b6SRobert Mustacchi #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 52575eba5b6SRobert Mustacchi 52675eba5b6SRobert Mustacchi #define IFS_MAX 80 52775eba5b6SRobert Mustacchi #define IFS_MIN 40 52875eba5b6SRobert Mustacchi #define IFS_RATIO 4 52975eba5b6SRobert Mustacchi #define IFS_STEP 10 53075eba5b6SRobert Mustacchi #define MIN_NUM_XMITS 1000 53175eba5b6SRobert Mustacchi 53275eba5b6SRobert Mustacchi /* SW Semaphore Register */ 53375eba5b6SRobert Mustacchi #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 53475eba5b6SRobert Mustacchi #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 53575eba5b6SRobert Mustacchi #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 53675eba5b6SRobert Mustacchi 53775eba5b6SRobert Mustacchi #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 53875eba5b6SRobert Mustacchi 53975eba5b6SRobert Mustacchi /* Interrupt Cause Read */ 54075eba5b6SRobert Mustacchi #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 54175eba5b6SRobert Mustacchi #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 54275eba5b6SRobert Mustacchi #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 54375eba5b6SRobert Mustacchi #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 54475eba5b6SRobert Mustacchi #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 54575eba5b6SRobert Mustacchi #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ 54675eba5b6SRobert Mustacchi #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 54775eba5b6SRobert Mustacchi #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 54875eba5b6SRobert Mustacchi #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 54975eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 55075eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 55175eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 55275eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 55375eba5b6SRobert Mustacchi #define E1000_ICR_TXD_LOW 0x00008000 55475eba5b6SRobert Mustacchi #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 55575eba5b6SRobert Mustacchi #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 55675eba5b6SRobert Mustacchi #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 55775eba5b6SRobert Mustacchi #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 55875eba5b6SRobert Mustacchi /* If this bit asserted, the driver should claim the interrupt */ 55975eba5b6SRobert Mustacchi #define E1000_ICR_INT_ASSERTED 0x80000000 56075eba5b6SRobert Mustacchi #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 56175eba5b6SRobert Mustacchi #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 56275eba5b6SRobert Mustacchi #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 56375eba5b6SRobert Mustacchi #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 56475eba5b6SRobert Mustacchi #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 56575eba5b6SRobert Mustacchi #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 56675eba5b6SRobert Mustacchi #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 56775eba5b6SRobert Mustacchi 56875eba5b6SRobert Mustacchi #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ 56975eba5b6SRobert Mustacchi #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ 57075eba5b6SRobert Mustacchi 57175eba5b6SRobert Mustacchi #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */ 57275eba5b6SRobert Mustacchi #define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */ 57375eba5b6SRobert Mustacchi 57475eba5b6SRobert Mustacchi /* PBA ECC Register */ 57575eba5b6SRobert Mustacchi #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 57675eba5b6SRobert Mustacchi #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 57775eba5b6SRobert Mustacchi #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 57875eba5b6SRobert Mustacchi #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 57975eba5b6SRobert Mustacchi #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 58075eba5b6SRobert Mustacchi 58175eba5b6SRobert Mustacchi /* Extended Interrupt Cause Read */ 58275eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 58375eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 58475eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 58575eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 58675eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 58775eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 58875eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 58975eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 59075eba5b6SRobert Mustacchi #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 59175eba5b6SRobert Mustacchi #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 59275eba5b6SRobert Mustacchi /* TCP Timer */ 59375eba5b6SRobert Mustacchi #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 59475eba5b6SRobert Mustacchi #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 59575eba5b6SRobert Mustacchi #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 59675eba5b6SRobert Mustacchi #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 59775eba5b6SRobert Mustacchi 59875eba5b6SRobert Mustacchi /* This defines the bits that are set in the Interrupt Mask 59975eba5b6SRobert Mustacchi * Set/Read Register. Each bit is documented below: 60075eba5b6SRobert Mustacchi * o RXT0 = Receiver Timer Interrupt (ring 0) 60175eba5b6SRobert Mustacchi * o TXDW = Transmit Descriptor Written Back 60275eba5b6SRobert Mustacchi * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 60375eba5b6SRobert Mustacchi * o RXSEQ = Receive Sequence Error 60475eba5b6SRobert Mustacchi * o LSC = Link Status Change 60575eba5b6SRobert Mustacchi */ 60675eba5b6SRobert Mustacchi #define IMS_ENABLE_MASK ( \ 60775eba5b6SRobert Mustacchi E1000_IMS_RXT0 | \ 60875eba5b6SRobert Mustacchi E1000_IMS_TXDW | \ 60975eba5b6SRobert Mustacchi E1000_IMS_RXDMT0 | \ 61075eba5b6SRobert Mustacchi E1000_IMS_RXSEQ | \ 61175eba5b6SRobert Mustacchi E1000_IMS_LSC) 61275eba5b6SRobert Mustacchi 61375eba5b6SRobert Mustacchi /* Interrupt Mask Set */ 61475eba5b6SRobert Mustacchi #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 61575eba5b6SRobert Mustacchi #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 61675eba5b6SRobert Mustacchi #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 61775eba5b6SRobert Mustacchi #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 61875eba5b6SRobert Mustacchi #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 61975eba5b6SRobert Mustacchi #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 62075eba5b6SRobert Mustacchi #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ 62175eba5b6SRobert Mustacchi #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 62275eba5b6SRobert Mustacchi #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 62375eba5b6SRobert Mustacchi #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 62475eba5b6SRobert Mustacchi #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 62575eba5b6SRobert Mustacchi #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 62675eba5b6SRobert Mustacchi #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 62775eba5b6SRobert Mustacchi #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 62875eba5b6SRobert Mustacchi #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 62975eba5b6SRobert Mustacchi #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 63075eba5b6SRobert Mustacchi #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 63175eba5b6SRobert Mustacchi #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 63275eba5b6SRobert Mustacchi #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ 63375eba5b6SRobert Mustacchi 63475eba5b6SRobert Mustacchi #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 63575eba5b6SRobert Mustacchi #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */ 63675eba5b6SRobert Mustacchi /* Extended Interrupt Mask Set */ 63775eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 63875eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 63975eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 64075eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 64175eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 64275eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 64375eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 64475eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 64575eba5b6SRobert Mustacchi #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 64675eba5b6SRobert Mustacchi #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 64775eba5b6SRobert Mustacchi 64875eba5b6SRobert Mustacchi /* Interrupt Cause Set */ 64975eba5b6SRobert Mustacchi #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 65075eba5b6SRobert Mustacchi #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 65175eba5b6SRobert Mustacchi #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 65275eba5b6SRobert Mustacchi 65375eba5b6SRobert Mustacchi /* Extended Interrupt Cause Set */ 65475eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 65575eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 65675eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 65775eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 65875eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 65975eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 66075eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 66175eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 66275eba5b6SRobert Mustacchi #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 66375eba5b6SRobert Mustacchi #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 66475eba5b6SRobert Mustacchi 66575eba5b6SRobert Mustacchi #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 66675eba5b6SRobert Mustacchi /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 66775eba5b6SRobert Mustacchi #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 668c124a83eSRobert Mustacchi #define E1000_EITR_INTERVAL 0x00007FFC 66975eba5b6SRobert Mustacchi 67075eba5b6SRobert Mustacchi /* Transmit Descriptor Control */ 67175eba5b6SRobert Mustacchi #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 67275eba5b6SRobert Mustacchi #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 67375eba5b6SRobert Mustacchi #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 67475eba5b6SRobert Mustacchi #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 67575eba5b6SRobert Mustacchi #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 67675eba5b6SRobert Mustacchi #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 67775eba5b6SRobert Mustacchi /* Enable the counting of descriptors still to be processed. */ 67875eba5b6SRobert Mustacchi #define E1000_TXDCTL_COUNT_DESC 0x00400000 67975eba5b6SRobert Mustacchi 68075eba5b6SRobert Mustacchi /* Flow Control Constants */ 68175eba5b6SRobert Mustacchi #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 68275eba5b6SRobert Mustacchi #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 68375eba5b6SRobert Mustacchi #define FLOW_CONTROL_TYPE 0x8808 68475eba5b6SRobert Mustacchi 68575eba5b6SRobert Mustacchi /* 802.1q VLAN Packet Size */ 68675eba5b6SRobert Mustacchi #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 68775eba5b6SRobert Mustacchi #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 68875eba5b6SRobert Mustacchi 68975eba5b6SRobert Mustacchi /* Receive Address 69075eba5b6SRobert Mustacchi * Number of high/low register pairs in the RAR. The RAR (Receive Address 69175eba5b6SRobert Mustacchi * Registers) holds the directed and multicast addresses that we monitor. 69275eba5b6SRobert Mustacchi * Technically, we have 16 spots. However, we reserve one of these spots 69375eba5b6SRobert Mustacchi * (RAR[15]) for our directed address used by controllers with 69475eba5b6SRobert Mustacchi * manageability enabled, allowing us room for 15 multicast addresses. 69575eba5b6SRobert Mustacchi */ 69675eba5b6SRobert Mustacchi #define E1000_RAR_ENTRIES 15 69775eba5b6SRobert Mustacchi #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 69875eba5b6SRobert Mustacchi #define E1000_RAL_MAC_ADDR_LEN 4 69975eba5b6SRobert Mustacchi #define E1000_RAH_MAC_ADDR_LEN 2 70075eba5b6SRobert Mustacchi #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 70175eba5b6SRobert Mustacchi #define E1000_RAH_POOL_1 0x00040000 70275eba5b6SRobert Mustacchi 70375eba5b6SRobert Mustacchi /* Error Codes */ 70475eba5b6SRobert Mustacchi #define E1000_SUCCESS 0 70575eba5b6SRobert Mustacchi #define E1000_ERR_NVM 1 70675eba5b6SRobert Mustacchi #define E1000_ERR_PHY 2 70775eba5b6SRobert Mustacchi #define E1000_ERR_CONFIG 3 70875eba5b6SRobert Mustacchi #define E1000_ERR_PARAM 4 70975eba5b6SRobert Mustacchi #define E1000_ERR_MAC_INIT 5 71075eba5b6SRobert Mustacchi #define E1000_ERR_PHY_TYPE 6 71175eba5b6SRobert Mustacchi #define E1000_ERR_RESET 9 71275eba5b6SRobert Mustacchi #define E1000_ERR_MASTER_REQUESTS_PENDING 10 71375eba5b6SRobert Mustacchi #define E1000_ERR_HOST_INTERFACE_COMMAND 11 71475eba5b6SRobert Mustacchi #define E1000_BLK_PHY_RESET 12 71575eba5b6SRobert Mustacchi #define E1000_ERR_SWFW_SYNC 13 71675eba5b6SRobert Mustacchi #define E1000_NOT_IMPLEMENTED 14 71775eba5b6SRobert Mustacchi #define E1000_ERR_MBX 15 71875eba5b6SRobert Mustacchi #define E1000_ERR_INVALID_ARGUMENT 16 71975eba5b6SRobert Mustacchi #define E1000_ERR_NO_SPACE 17 72075eba5b6SRobert Mustacchi #define E1000_ERR_NVM_PBA_SECTION 18 72175eba5b6SRobert Mustacchi #define E1000_ERR_I2C 19 72275eba5b6SRobert Mustacchi #define E1000_ERR_INVM_VALUE_NOT_FOUND 20 72375eba5b6SRobert Mustacchi 72475eba5b6SRobert Mustacchi /* Loop limit on how long we wait for auto-negotiation to complete */ 72575eba5b6SRobert Mustacchi #define FIBER_LINK_UP_LIMIT 50 72675eba5b6SRobert Mustacchi #define COPPER_LINK_UP_LIMIT 10 72775eba5b6SRobert Mustacchi #define PHY_AUTO_NEG_LIMIT 45 72875eba5b6SRobert Mustacchi #define PHY_FORCE_LIMIT 20 72975eba5b6SRobert Mustacchi /* Number of 100 microseconds we wait for PCI Express master disable */ 73075eba5b6SRobert Mustacchi #define MASTER_DISABLE_TIMEOUT 800 73175eba5b6SRobert Mustacchi /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 73275eba5b6SRobert Mustacchi #define PHY_CFG_TIMEOUT 100 73375eba5b6SRobert Mustacchi /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 73475eba5b6SRobert Mustacchi #define MDIO_OWNERSHIP_TIMEOUT 10 73575eba5b6SRobert Mustacchi /* Number of milliseconds for NVM auto read done after MAC reset. */ 73675eba5b6SRobert Mustacchi #define AUTO_READ_DONE_TIMEOUT 10 73775eba5b6SRobert Mustacchi 73875eba5b6SRobert Mustacchi /* Flow Control */ 73975eba5b6SRobert Mustacchi #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 74075eba5b6SRobert Mustacchi #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 74175eba5b6SRobert Mustacchi #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 74275eba5b6SRobert Mustacchi 74375eba5b6SRobert Mustacchi /* Transmit Configuration Word */ 74475eba5b6SRobert Mustacchi #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 74575eba5b6SRobert Mustacchi #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 74675eba5b6SRobert Mustacchi #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 74775eba5b6SRobert Mustacchi #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 74875eba5b6SRobert Mustacchi #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 74975eba5b6SRobert Mustacchi 75075eba5b6SRobert Mustacchi /* Receive Configuration Word */ 75175eba5b6SRobert Mustacchi #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 75275eba5b6SRobert Mustacchi #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 75375eba5b6SRobert Mustacchi #define E1000_RXCW_C 0x20000000 /* Receive config */ 75475eba5b6SRobert Mustacchi #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 75575eba5b6SRobert Mustacchi 75675eba5b6SRobert Mustacchi #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 75775eba5b6SRobert Mustacchi #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 75875eba5b6SRobert Mustacchi 75949b78600SRobert Mustacchi /* HH Time Sync */ 76049b78600SRobert Mustacchi #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 76149b78600SRobert Mustacchi #define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 76249b78600SRobert Mustacchi #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 76349b78600SRobert Mustacchi #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 76449b78600SRobert Mustacchi 76575eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 76675eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 76775eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 76875eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 76975eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 77075eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 77175eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 77275eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 77375eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 77475eba5b6SRobert Mustacchi 77575eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 77675eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 77775eba5b6SRobert Mustacchi 77875eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 77975eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 78075eba5b6SRobert Mustacchi 78175eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 78275eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 78375eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 78475eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 78575eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 78675eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 78775eba5b6SRobert Mustacchi 78875eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 78975eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 79075eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 79175eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 79275eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 79375eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 79475eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 79575eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 79675eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 79775eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 79875eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 79975eba5b6SRobert Mustacchi 80075eba5b6SRobert Mustacchi #define E1000_TIMINCA_16NS_SHIFT 24 80175eba5b6SRobert Mustacchi #define E1000_TIMINCA_INCPERIOD_SHIFT 24 80275eba5b6SRobert Mustacchi #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 80375eba5b6SRobert Mustacchi 80475eba5b6SRobert Mustacchi #define E1000_TSICR_TXTS 0x00000002 80575eba5b6SRobert Mustacchi #define E1000_TSIM_TXTS 0x00000002 80675eba5b6SRobert Mustacchi /* TUPLE Filtering Configuration */ 80775eba5b6SRobert Mustacchi #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 80875eba5b6SRobert Mustacchi #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 80975eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 81075eba5b6SRobert Mustacchi /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 81175eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_TCP 0x0 81275eba5b6SRobert Mustacchi /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 81375eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_UDP 0x1 81475eba5b6SRobert Mustacchi /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 81575eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_SCTP 0x2 81675eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 81775eba5b6SRobert Mustacchi #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 81875eba5b6SRobert Mustacchi #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 81975eba5b6SRobert Mustacchi #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 82075eba5b6SRobert Mustacchi #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 82175eba5b6SRobert Mustacchi #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 82275eba5b6SRobert Mustacchi #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 82375eba5b6SRobert Mustacchi #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 82475eba5b6SRobert Mustacchi 82575eba5b6SRobert Mustacchi #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 82675eba5b6SRobert Mustacchi #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 82775eba5b6SRobert Mustacchi #define E1000_MDICNFG_PHY_MASK 0x03E00000 82875eba5b6SRobert Mustacchi #define E1000_MDICNFG_PHY_SHIFT 21 82975eba5b6SRobert Mustacchi 830c124a83eSRobert Mustacchi #define E1000_MEDIA_PORT_COPPER 1 831c124a83eSRobert Mustacchi #define E1000_MEDIA_PORT_OTHER 2 832c124a83eSRobert Mustacchi #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 833c124a83eSRobert Mustacchi #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 834c124a83eSRobert Mustacchi #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 835c124a83eSRobert Mustacchi #define E1000_M88E1112_MAC_CTRL_1 0x10 836c124a83eSRobert Mustacchi #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 837c124a83eSRobert Mustacchi #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 838c124a83eSRobert Mustacchi #define E1000_M88E1112_PAGE_ADDR 0x16 839c124a83eSRobert Mustacchi #define E1000_M88E1112_STATUS 0x01 840c124a83eSRobert Mustacchi 84175eba5b6SRobert Mustacchi #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 84275eba5b6SRobert Mustacchi #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 84375eba5b6SRobert Mustacchi #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 84475eba5b6SRobert Mustacchi #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 84575eba5b6SRobert Mustacchi #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 84675eba5b6SRobert Mustacchi 84775eba5b6SRobert Mustacchi /* I350 EEE defines */ 84875eba5b6SRobert Mustacchi #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 84975eba5b6SRobert Mustacchi #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 85075eba5b6SRobert Mustacchi #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 85175eba5b6SRobert Mustacchi #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 85275eba5b6SRobert Mustacchi #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 85375eba5b6SRobert Mustacchi /* EEE status */ 85475eba5b6SRobert Mustacchi #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 85575eba5b6SRobert Mustacchi #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 85675eba5b6SRobert Mustacchi #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 857c124a83eSRobert Mustacchi #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 858c124a83eSRobert Mustacchi #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 859c124a83eSRobert Mustacchi #define E1000_M88E1543_EEE_CTRL_1 0x0 860c124a83eSRobert Mustacchi #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 86149b78600SRobert Mustacchi #define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ 862c124a83eSRobert Mustacchi #define E1000_EEE_ADV_DEV_I354 7 863c124a83eSRobert Mustacchi #define E1000_EEE_ADV_ADDR_I354 60 864c124a83eSRobert Mustacchi #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 865c124a83eSRobert Mustacchi #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 866c124a83eSRobert Mustacchi #define E1000_PCS_STATUS_DEV_I354 3 867c124a83eSRobert Mustacchi #define E1000_PCS_STATUS_ADDR_I354 1 868c124a83eSRobert Mustacchi #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 869c124a83eSRobert Mustacchi #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 870c124a83eSRobert Mustacchi #define E1000_M88E1512_CFG_REG_1 0x0010 871c124a83eSRobert Mustacchi #define E1000_M88E1512_CFG_REG_2 0x0011 872c124a83eSRobert Mustacchi #define E1000_M88E1512_CFG_REG_3 0x0007 873c124a83eSRobert Mustacchi #define E1000_M88E1512_MODE 0x0014 87475eba5b6SRobert Mustacchi #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 875c124a83eSRobert Mustacchi #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 876c124a83eSRobert Mustacchi #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 87775eba5b6SRobert Mustacchi /* PCI Express Control */ 87875eba5b6SRobert Mustacchi #define E1000_GCR_RXD_NO_SNOOP 0x00000001 87975eba5b6SRobert Mustacchi #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 88075eba5b6SRobert Mustacchi #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 88175eba5b6SRobert Mustacchi #define E1000_GCR_TXD_NO_SNOOP 0x00000008 88275eba5b6SRobert Mustacchi #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 88375eba5b6SRobert Mustacchi #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 88475eba5b6SRobert Mustacchi #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 88575eba5b6SRobert Mustacchi #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 88675eba5b6SRobert Mustacchi #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 88775eba5b6SRobert Mustacchi #define E1000_GCR_CAP_VER2 0x00040000 88875eba5b6SRobert Mustacchi 88975eba5b6SRobert Mustacchi #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 89075eba5b6SRobert Mustacchi E1000_GCR_RXDSCW_NO_SNOOP | \ 89175eba5b6SRobert Mustacchi E1000_GCR_RXDSCR_NO_SNOOP | \ 89275eba5b6SRobert Mustacchi E1000_GCR_TXD_NO_SNOOP | \ 89375eba5b6SRobert Mustacchi E1000_GCR_TXDSCW_NO_SNOOP | \ 89475eba5b6SRobert Mustacchi E1000_GCR_TXDSCR_NO_SNOOP) 89575eba5b6SRobert Mustacchi 896c124a83eSRobert Mustacchi #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 89713485e69SGarrett D'Amore 89875eba5b6SRobert Mustacchi /* mPHY address control and data registers */ 89975eba5b6SRobert Mustacchi #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ 90075eba5b6SRobert Mustacchi #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 90175eba5b6SRobert Mustacchi #define E1000_MPHY_DATA 0x0E10 /* Data Register */ 90275eba5b6SRobert Mustacchi 90375eba5b6SRobert Mustacchi /* AFE CSR Offset for PCS CLK */ 90475eba5b6SRobert Mustacchi #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 90575eba5b6SRobert Mustacchi /* Override for near end digital loopback. */ 90675eba5b6SRobert Mustacchi #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 90775eba5b6SRobert Mustacchi 90875eba5b6SRobert Mustacchi /* PHY Control Register */ 90975eba5b6SRobert Mustacchi #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 91075eba5b6SRobert Mustacchi #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 91175eba5b6SRobert Mustacchi #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 91275eba5b6SRobert Mustacchi #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 91375eba5b6SRobert Mustacchi #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 91475eba5b6SRobert Mustacchi #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 91575eba5b6SRobert Mustacchi #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 91675eba5b6SRobert Mustacchi #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 91775eba5b6SRobert Mustacchi #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 91875eba5b6SRobert Mustacchi #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 91975eba5b6SRobert Mustacchi #define MII_CR_SPEED_1000 0x0040 92075eba5b6SRobert Mustacchi #define MII_CR_SPEED_100 0x2000 92175eba5b6SRobert Mustacchi #define MII_CR_SPEED_10 0x0000 92275eba5b6SRobert Mustacchi 92375eba5b6SRobert Mustacchi /* PHY Status Register */ 92475eba5b6SRobert Mustacchi #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 92575eba5b6SRobert Mustacchi #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 92675eba5b6SRobert Mustacchi #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 92775eba5b6SRobert Mustacchi #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 92875eba5b6SRobert Mustacchi #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 92975eba5b6SRobert Mustacchi #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 93075eba5b6SRobert Mustacchi #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 93175eba5b6SRobert Mustacchi #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 93275eba5b6SRobert Mustacchi #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 93375eba5b6SRobert Mustacchi #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 93475eba5b6SRobert Mustacchi #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 93575eba5b6SRobert Mustacchi #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 93675eba5b6SRobert Mustacchi #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 93775eba5b6SRobert Mustacchi #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 93875eba5b6SRobert Mustacchi #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 93975eba5b6SRobert Mustacchi 94075eba5b6SRobert Mustacchi /* Autoneg Advertisement Register */ 94175eba5b6SRobert Mustacchi #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 94275eba5b6SRobert Mustacchi #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 94375eba5b6SRobert Mustacchi #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 94475eba5b6SRobert Mustacchi #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 94575eba5b6SRobert Mustacchi #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 94675eba5b6SRobert Mustacchi #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 94775eba5b6SRobert Mustacchi #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 94875eba5b6SRobert Mustacchi #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 94975eba5b6SRobert Mustacchi #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 95075eba5b6SRobert Mustacchi #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 95175eba5b6SRobert Mustacchi 95275eba5b6SRobert Mustacchi /* Link Partner Ability Register (Base Page) */ 95375eba5b6SRobert Mustacchi #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 95475eba5b6SRobert Mustacchi #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 95575eba5b6SRobert Mustacchi #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 95675eba5b6SRobert Mustacchi #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 95775eba5b6SRobert Mustacchi #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 95875eba5b6SRobert Mustacchi #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 95975eba5b6SRobert Mustacchi #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 96075eba5b6SRobert Mustacchi #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 96175eba5b6SRobert Mustacchi #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 96275eba5b6SRobert Mustacchi #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 96375eba5b6SRobert Mustacchi #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 96475eba5b6SRobert Mustacchi 96575eba5b6SRobert Mustacchi /* Autoneg Expansion Register */ 96675eba5b6SRobert Mustacchi #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 96775eba5b6SRobert Mustacchi #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 96875eba5b6SRobert Mustacchi #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 96975eba5b6SRobert Mustacchi #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 97075eba5b6SRobert Mustacchi #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 97175eba5b6SRobert Mustacchi 97275eba5b6SRobert Mustacchi /* 1000BASE-T Control Register */ 97375eba5b6SRobert Mustacchi #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 97475eba5b6SRobert Mustacchi #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 97575eba5b6SRobert Mustacchi #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 97675eba5b6SRobert Mustacchi /* 1=Repeater/switch device port 0=DTE device */ 97775eba5b6SRobert Mustacchi #define CR_1000T_REPEATER_DTE 0x0400 97875eba5b6SRobert Mustacchi /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 97975eba5b6SRobert Mustacchi #define CR_1000T_MS_VALUE 0x0800 98075eba5b6SRobert Mustacchi /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 98175eba5b6SRobert Mustacchi #define CR_1000T_MS_ENABLE 0x1000 98275eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 98375eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 98475eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 98575eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 98675eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 98775eba5b6SRobert Mustacchi 98875eba5b6SRobert Mustacchi /* 1000BASE-T Status Register */ 98975eba5b6SRobert Mustacchi #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 99075eba5b6SRobert Mustacchi #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 99175eba5b6SRobert Mustacchi #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 99275eba5b6SRobert Mustacchi #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 99375eba5b6SRobert Mustacchi #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 99475eba5b6SRobert Mustacchi #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 99575eba5b6SRobert Mustacchi #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 99675eba5b6SRobert Mustacchi #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 99775eba5b6SRobert Mustacchi 99875eba5b6SRobert Mustacchi #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 99975eba5b6SRobert Mustacchi 100075eba5b6SRobert Mustacchi /* PHY 1000 MII Register/Bit Definitions */ 100175eba5b6SRobert Mustacchi /* PHY Registers defined by IEEE */ 100275eba5b6SRobert Mustacchi #define PHY_CONTROL 0x00 /* Control Register */ 100375eba5b6SRobert Mustacchi #define PHY_STATUS 0x01 /* Status Register */ 100475eba5b6SRobert Mustacchi #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 100575eba5b6SRobert Mustacchi #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 100675eba5b6SRobert Mustacchi #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 100775eba5b6SRobert Mustacchi #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 100875eba5b6SRobert Mustacchi #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 100975eba5b6SRobert Mustacchi #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 101075eba5b6SRobert Mustacchi #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 101175eba5b6SRobert Mustacchi #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 101275eba5b6SRobert Mustacchi #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 101375eba5b6SRobert Mustacchi #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 101475eba5b6SRobert Mustacchi 101575eba5b6SRobert Mustacchi #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 101675eba5b6SRobert Mustacchi 101775eba5b6SRobert Mustacchi /* NVM Control */ 101875eba5b6SRobert Mustacchi #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 101975eba5b6SRobert Mustacchi #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 102075eba5b6SRobert Mustacchi #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 102175eba5b6SRobert Mustacchi #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 102275eba5b6SRobert Mustacchi #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 102375eba5b6SRobert Mustacchi #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 102475eba5b6SRobert Mustacchi #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 102575eba5b6SRobert Mustacchi #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 102675eba5b6SRobert Mustacchi #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 102775eba5b6SRobert Mustacchi #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 102875eba5b6SRobert Mustacchi #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 102975eba5b6SRobert Mustacchi #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 103075eba5b6SRobert Mustacchi /* NVM Addressing bits based on type 0=small, 1=large */ 103175eba5b6SRobert Mustacchi #define E1000_EECD_ADDR_BITS 0x00000400 103275eba5b6SRobert Mustacchi #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 103375eba5b6SRobert Mustacchi #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 103475eba5b6SRobert Mustacchi #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 103575eba5b6SRobert Mustacchi #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 103675eba5b6SRobert Mustacchi #define E1000_EECD_SIZE_EX_SHIFT 11 103775eba5b6SRobert Mustacchi #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 103875eba5b6SRobert Mustacchi #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 103975eba5b6SRobert Mustacchi #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 104075eba5b6SRobert Mustacchi #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 104175eba5b6SRobert Mustacchi #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 104275eba5b6SRobert Mustacchi #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 104375eba5b6SRobert Mustacchi #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 104475eba5b6SRobert Mustacchi #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ 104575eba5b6SRobert Mustacchi #define E1000_FLUDONE_ATTEMPTS 20000 104675eba5b6SRobert Mustacchi #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 104775eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_RX 0x00 104875eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 104975eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 105075eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 105175eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 105275eba5b6SRobert Mustacchi 105375eba5b6SRobert Mustacchi #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 105475eba5b6SRobert Mustacchi /* Secure FLASH mode requires removing MSb */ 105575eba5b6SRobert Mustacchi #define E1000_I210_FW_PTR_MASK 0x7FFF 105675eba5b6SRobert Mustacchi /* Firmware code revision field word offset*/ 105775eba5b6SRobert Mustacchi #define E1000_I210_FW_VER_OFFSET 328 105875eba5b6SRobert Mustacchi 105975eba5b6SRobert Mustacchi #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 106075eba5b6SRobert Mustacchi #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 106175eba5b6SRobert Mustacchi #define E1000_NVM_RW_REG_START 1 /* Start operation */ 106275eba5b6SRobert Mustacchi #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 106375eba5b6SRobert Mustacchi #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 106475eba5b6SRobert Mustacchi #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 106575eba5b6SRobert Mustacchi #define E1000_FLASH_UPDATES 2000 106675eba5b6SRobert Mustacchi 106775eba5b6SRobert Mustacchi /* NVM Word Offsets */ 106875eba5b6SRobert Mustacchi #define NVM_COMPAT 0x0003 106975eba5b6SRobert Mustacchi #define NVM_ID_LED_SETTINGS 0x0004 107075eba5b6SRobert Mustacchi #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 107175eba5b6SRobert Mustacchi #define NVM_PHY_CLASS_WORD 0x0007 107275eba5b6SRobert Mustacchi #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 107375eba5b6SRobert Mustacchi #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 107475eba5b6SRobert Mustacchi #define NVM_FUTURE_INIT_WORD1 0x0019 107575eba5b6SRobert Mustacchi #define NVM_MAC_ADDR 0x0000 107675eba5b6SRobert Mustacchi #define NVM_SUB_DEV_ID 0x000B 107775eba5b6SRobert Mustacchi #define NVM_SUB_VEN_ID 0x000C 107875eba5b6SRobert Mustacchi #define NVM_DEV_ID 0x000D 107975eba5b6SRobert Mustacchi #define NVM_VEN_ID 0x000E 108075eba5b6SRobert Mustacchi #define NVM_INIT_CTRL_2 0x000F 108175eba5b6SRobert Mustacchi #define NVM_INIT_CTRL_4 0x0013 108275eba5b6SRobert Mustacchi #define NVM_LED_1_CFG 0x001C 108375eba5b6SRobert Mustacchi #define NVM_LED_0_2_CFG 0x001F 108475eba5b6SRobert Mustacchi 108575eba5b6SRobert Mustacchi #define NVM_COMPAT_VALID_CSUM 0x0001 108675eba5b6SRobert Mustacchi #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 108775eba5b6SRobert Mustacchi 108875eba5b6SRobert Mustacchi #define NVM_INIT_CONTROL2_REG 0x000F 108975eba5b6SRobert Mustacchi #define NVM_INIT_CONTROL3_PORT_B 0x0014 109075eba5b6SRobert Mustacchi #define NVM_INIT_3GIO_3 0x001A 109175eba5b6SRobert Mustacchi #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 109275eba5b6SRobert Mustacchi #define NVM_INIT_CONTROL3_PORT_A 0x0024 109375eba5b6SRobert Mustacchi #define NVM_CFG 0x0012 109475eba5b6SRobert Mustacchi #define NVM_ALT_MAC_ADDR_PTR 0x0037 109575eba5b6SRobert Mustacchi #define NVM_CHECKSUM_REG 0x003F 109675eba5b6SRobert Mustacchi #define NVM_COMPATIBILITY_REG_3 0x0003 109775eba5b6SRobert Mustacchi #define NVM_COMPATIBILITY_BIT_MASK 0x8000 109875eba5b6SRobert Mustacchi 109975eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 110075eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 110175eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 110275eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 110375eba5b6SRobert Mustacchi 110475eba5b6SRobert Mustacchi #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) 110575eba5b6SRobert Mustacchi 110675eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x24 of the NVM */ 110775eba5b6SRobert Mustacchi #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 110875eba5b6SRobert Mustacchi #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ 110975eba5b6SRobert Mustacchi /* Offset of Link Mode bits for 82575/82576 */ 111075eba5b6SRobert Mustacchi #define NVM_WORD24_LNK_MODE_OFFSET 8 111175eba5b6SRobert Mustacchi /* Offset of Link Mode bits for 82580 up */ 111275eba5b6SRobert Mustacchi #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 111375eba5b6SRobert Mustacchi 111475eba5b6SRobert Mustacchi 111575eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x0f of the NVM */ 111675eba5b6SRobert Mustacchi #define NVM_WORD0F_PAUSE_MASK 0x3000 111775eba5b6SRobert Mustacchi #define NVM_WORD0F_PAUSE 0x1000 111875eba5b6SRobert Mustacchi #define NVM_WORD0F_ASM_DIR 0x2000 111975eba5b6SRobert Mustacchi #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 112075eba5b6SRobert Mustacchi 112175eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x1a of the NVM */ 112275eba5b6SRobert Mustacchi #define NVM_WORD1A_ASPM_MASK 0x000C 112375eba5b6SRobert Mustacchi 112475eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x03 of the EEPROM */ 112575eba5b6SRobert Mustacchi #define NVM_COMPAT_LOM 0x0800 112675eba5b6SRobert Mustacchi 112775eba5b6SRobert Mustacchi /* length of string needed to store PBA number */ 112875eba5b6SRobert Mustacchi #define E1000_PBANUM_LENGTH 11 112975eba5b6SRobert Mustacchi 113075eba5b6SRobert Mustacchi /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 113175eba5b6SRobert Mustacchi #define NVM_SUM 0xBABA 113275eba5b6SRobert Mustacchi 113375eba5b6SRobert Mustacchi /* PBA (printed board assembly) number words */ 113475eba5b6SRobert Mustacchi #define NVM_PBA_OFFSET_0 8 113575eba5b6SRobert Mustacchi #define NVM_PBA_OFFSET_1 9 113675eba5b6SRobert Mustacchi #define NVM_PBA_PTR_GUARD 0xFAFA 113775eba5b6SRobert Mustacchi #define NVM_RESERVED_WORD 0xFFFF 113875eba5b6SRobert Mustacchi #define NVM_PHY_CLASS_A 0x8000 113975eba5b6SRobert Mustacchi #define NVM_SERDES_AMPLITUDE_MASK 0x000F 114075eba5b6SRobert Mustacchi #define NVM_SIZE_MASK 0x1C00 114175eba5b6SRobert Mustacchi #define NVM_SIZE_SHIFT 10 114275eba5b6SRobert Mustacchi #define NVM_WORD_SIZE_BASE_SHIFT 6 114375eba5b6SRobert Mustacchi #define NVM_SWDPIO_EXT_SHIFT 4 114475eba5b6SRobert Mustacchi 114575eba5b6SRobert Mustacchi /* NVM Commands - Microwire */ 114675eba5b6SRobert Mustacchi #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 114775eba5b6SRobert Mustacchi #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 114875eba5b6SRobert Mustacchi #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 114975eba5b6SRobert Mustacchi #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 115075eba5b6SRobert Mustacchi #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 115175eba5b6SRobert Mustacchi 115275eba5b6SRobert Mustacchi /* NVM Commands - SPI */ 115375eba5b6SRobert Mustacchi #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 115475eba5b6SRobert Mustacchi #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 115575eba5b6SRobert Mustacchi #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 115675eba5b6SRobert Mustacchi #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 115775eba5b6SRobert Mustacchi #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 115875eba5b6SRobert Mustacchi #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 115975eba5b6SRobert Mustacchi 116075eba5b6SRobert Mustacchi /* SPI NVM Status Register */ 116175eba5b6SRobert Mustacchi #define NVM_STATUS_RDY_SPI 0x01 116275eba5b6SRobert Mustacchi 116375eba5b6SRobert Mustacchi /* Word definitions for ID LED Settings */ 116475eba5b6SRobert Mustacchi #define ID_LED_RESERVED_0000 0x0000 116575eba5b6SRobert Mustacchi #define ID_LED_RESERVED_FFFF 0xFFFF 116675eba5b6SRobert Mustacchi #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 116775eba5b6SRobert Mustacchi (ID_LED_OFF1_OFF2 << 8) | \ 116875eba5b6SRobert Mustacchi (ID_LED_DEF1_DEF2 << 4) | \ 116975eba5b6SRobert Mustacchi (ID_LED_DEF1_DEF2)) 117075eba5b6SRobert Mustacchi #define ID_LED_DEF1_DEF2 0x1 117175eba5b6SRobert Mustacchi #define ID_LED_DEF1_ON2 0x2 117275eba5b6SRobert Mustacchi #define ID_LED_DEF1_OFF2 0x3 117375eba5b6SRobert Mustacchi #define ID_LED_ON1_DEF2 0x4 117475eba5b6SRobert Mustacchi #define ID_LED_ON1_ON2 0x5 117575eba5b6SRobert Mustacchi #define ID_LED_ON1_OFF2 0x6 117675eba5b6SRobert Mustacchi #define ID_LED_OFF1_DEF2 0x7 117775eba5b6SRobert Mustacchi #define ID_LED_OFF1_ON2 0x8 117875eba5b6SRobert Mustacchi #define ID_LED_OFF1_OFF2 0x9 117975eba5b6SRobert Mustacchi 118075eba5b6SRobert Mustacchi #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 118175eba5b6SRobert Mustacchi #define IGP_ACTIVITY_LED_ENABLE 0x0300 118275eba5b6SRobert Mustacchi #define IGP_LED3_MODE 0x07000000 118375eba5b6SRobert Mustacchi 118475eba5b6SRobert Mustacchi /* PCI/PCI-X/PCI-EX Config space */ 118575eba5b6SRobert Mustacchi #define PCIX_COMMAND_REGISTER 0xE6 118675eba5b6SRobert Mustacchi #define PCIX_STATUS_REGISTER_LO 0xE8 118775eba5b6SRobert Mustacchi #define PCIX_STATUS_REGISTER_HI 0xEA 118875eba5b6SRobert Mustacchi #define PCI_HEADER_TYPE_REGISTER 0x0E 118975eba5b6SRobert Mustacchi #define PCIE_LINK_STATUS 0x12 119075eba5b6SRobert Mustacchi #define PCIE_DEVICE_CONTROL2 0x28 119175eba5b6SRobert Mustacchi 119275eba5b6SRobert Mustacchi #define PCIX_COMMAND_MMRBC_MASK 0x000C 119375eba5b6SRobert Mustacchi #define PCIX_COMMAND_MMRBC_SHIFT 0x2 119475eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 119575eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 119675eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_4K 0x3 119775eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_2K 0x2 119875eba5b6SRobert Mustacchi #define PCIX_STATUS_LO_FUNC_MASK 0x7 119975eba5b6SRobert Mustacchi #define PCI_HEADER_TYPE_MULTIFUNC 0x80 120075eba5b6SRobert Mustacchi #define PCIE_LINK_WIDTH_MASK 0x3F0 120175eba5b6SRobert Mustacchi #define PCIE_LINK_WIDTH_SHIFT 4 120275eba5b6SRobert Mustacchi #define PCIE_LINK_SPEED_MASK 0x0F 120375eba5b6SRobert Mustacchi #define PCIE_LINK_SPEED_2500 0x01 120475eba5b6SRobert Mustacchi #define PCIE_LINK_SPEED_5000 0x02 120575eba5b6SRobert Mustacchi #define PCIE_DEVICE_CONTROL2_16ms 0x0005 120675eba5b6SRobert Mustacchi 120775eba5b6SRobert Mustacchi #ifndef ETH_ADDR_LEN 120875eba5b6SRobert Mustacchi #define ETH_ADDR_LEN 6 120975eba5b6SRobert Mustacchi #endif 121075eba5b6SRobert Mustacchi 121175eba5b6SRobert Mustacchi #define PHY_REVISION_MASK 0xFFFFFFF0 121275eba5b6SRobert Mustacchi #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 121375eba5b6SRobert Mustacchi #define MAX_PHY_MULTI_PAGE_REG 0xF 121475eba5b6SRobert Mustacchi 121575eba5b6SRobert Mustacchi /* Bit definitions for valid PHY IDs. 121675eba5b6SRobert Mustacchi * I = Integrated 121775eba5b6SRobert Mustacchi * E = External 121875eba5b6SRobert Mustacchi */ 121975eba5b6SRobert Mustacchi #define M88E1000_E_PHY_ID 0x01410C50 122075eba5b6SRobert Mustacchi #define M88E1000_I_PHY_ID 0x01410C30 122175eba5b6SRobert Mustacchi #define M88E1011_I_PHY_ID 0x01410C20 122275eba5b6SRobert Mustacchi #define IGP01E1000_I_PHY_ID 0x02A80380 122375eba5b6SRobert Mustacchi #define M88E1111_I_PHY_ID 0x01410CC0 1224c124a83eSRobert Mustacchi #define M88E1543_E_PHY_ID 0x01410EA0 1225c124a83eSRobert Mustacchi #define M88E1512_E_PHY_ID 0x01410DD0 122675eba5b6SRobert Mustacchi #define M88E1112_E_PHY_ID 0x01410C90 122775eba5b6SRobert Mustacchi #define I347AT4_E_PHY_ID 0x01410DC0 122875eba5b6SRobert Mustacchi #define M88E1340M_E_PHY_ID 0x01410DF0 122975eba5b6SRobert Mustacchi #define GG82563_E_PHY_ID 0x01410CA0 123075eba5b6SRobert Mustacchi #define IGP03E1000_E_PHY_ID 0x02A80390 123175eba5b6SRobert Mustacchi #define IFE_E_PHY_ID 0x02A80330 123275eba5b6SRobert Mustacchi #define IFE_PLUS_E_PHY_ID 0x02A80320 123375eba5b6SRobert Mustacchi #define IFE_C_E_PHY_ID 0x02A80310 123475eba5b6SRobert Mustacchi #define BME1000_E_PHY_ID 0x01410CB0 123575eba5b6SRobert Mustacchi #define BME1000_E_PHY_ID_R2 0x01410CB1 123675eba5b6SRobert Mustacchi #define I82577_E_PHY_ID 0x01540050 123775eba5b6SRobert Mustacchi #define I82578_E_PHY_ID 0x004DD040 123875eba5b6SRobert Mustacchi #define I82579_E_PHY_ID 0x01540090 123975eba5b6SRobert Mustacchi #define I217_E_PHY_ID 0x015400A0 124075eba5b6SRobert Mustacchi #define I82580_I_PHY_ID 0x015403A0 124175eba5b6SRobert Mustacchi #define I350_I_PHY_ID 0x015403B0 124275eba5b6SRobert Mustacchi #define I210_I_PHY_ID 0x01410C00 124375eba5b6SRobert Mustacchi #define IGP04E1000_E_PHY_ID 0x02A80391 124475eba5b6SRobert Mustacchi #define M88_VENDOR 0x0141 124575eba5b6SRobert Mustacchi 124675eba5b6SRobert Mustacchi /* M88E1000 Specific Registers */ 124775eba5b6SRobert Mustacchi #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 124875eba5b6SRobert Mustacchi #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 124975eba5b6SRobert Mustacchi #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 125075eba5b6SRobert Mustacchi #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 125175eba5b6SRobert Mustacchi 125275eba5b6SRobert Mustacchi #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 125375eba5b6SRobert Mustacchi #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 125475eba5b6SRobert Mustacchi #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 125575eba5b6SRobert Mustacchi #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 125675eba5b6SRobert Mustacchi #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 125775eba5b6SRobert Mustacchi 125875eba5b6SRobert Mustacchi /* M88E1000 PHY Specific Control Register */ 125975eba5b6SRobert Mustacchi #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 126075eba5b6SRobert Mustacchi /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 126175eba5b6SRobert Mustacchi #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 126275eba5b6SRobert Mustacchi #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 126375eba5b6SRobert Mustacchi /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 126475eba5b6SRobert Mustacchi #define M88E1000_PSCR_AUTO_X_1000T 0x0040 126575eba5b6SRobert Mustacchi /* Auto crossover enabled all speeds */ 126675eba5b6SRobert Mustacchi #define M88E1000_PSCR_AUTO_X_MODE 0x0060 126775eba5b6SRobert Mustacchi #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 126875eba5b6SRobert Mustacchi 126975eba5b6SRobert Mustacchi /* M88E1000 PHY Specific Status Register */ 127075eba5b6SRobert Mustacchi #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 127175eba5b6SRobert Mustacchi #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 127275eba5b6SRobert Mustacchi #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 127375eba5b6SRobert Mustacchi /* 0 = <50M 127475eba5b6SRobert Mustacchi * 1 = 50-80M 127575eba5b6SRobert Mustacchi * 2 = 80-110M 127675eba5b6SRobert Mustacchi * 3 = 110-140M 127775eba5b6SRobert Mustacchi * 4 = >140M 127875eba5b6SRobert Mustacchi */ 127975eba5b6SRobert Mustacchi #define M88E1000_PSSR_CABLE_LENGTH 0x0380 128075eba5b6SRobert Mustacchi #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 128175eba5b6SRobert Mustacchi #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 128275eba5b6SRobert Mustacchi #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 128375eba5b6SRobert Mustacchi #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 128475eba5b6SRobert Mustacchi #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 128575eba5b6SRobert Mustacchi #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 128675eba5b6SRobert Mustacchi 128775eba5b6SRobert Mustacchi #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 128875eba5b6SRobert Mustacchi 128975eba5b6SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 129075eba5b6SRobert Mustacchi * are the master 129175eba5b6SRobert Mustacchi */ 129275eba5b6SRobert Mustacchi #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 129375eba5b6SRobert Mustacchi #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 129475eba5b6SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 129575eba5b6SRobert Mustacchi * are the slave 129675eba5b6SRobert Mustacchi */ 129775eba5b6SRobert Mustacchi #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 129875eba5b6SRobert Mustacchi #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 129975eba5b6SRobert Mustacchi #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 130075eba5b6SRobert Mustacchi 130175eba5b6SRobert Mustacchi /* Intel I347AT4 Registers */ 130275eba5b6SRobert Mustacchi #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 130375eba5b6SRobert Mustacchi #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 130475eba5b6SRobert Mustacchi #define I347AT4_PAGE_SELECT 0x16 130575eba5b6SRobert Mustacchi 130675eba5b6SRobert Mustacchi /* I347AT4 Extended PHY Specific Control Register */ 130775eba5b6SRobert Mustacchi 130875eba5b6SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 130975eba5b6SRobert Mustacchi * are the master 131075eba5b6SRobert Mustacchi */ 131175eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 131275eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 131375eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 131475eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 131575eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 131675eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 131775eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 131875eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 131975eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 132075eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 132175eba5b6SRobert Mustacchi 132275eba5b6SRobert Mustacchi /* I347AT4 PHY Cable Diagnostics Control */ 132375eba5b6SRobert Mustacchi #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 132475eba5b6SRobert Mustacchi 132575eba5b6SRobert Mustacchi /* M88E1112 only registers */ 132675eba5b6SRobert Mustacchi #define M88E1112_VCT_DSP_DISTANCE 0x001A 132775eba5b6SRobert Mustacchi 132875eba5b6SRobert Mustacchi /* M88EC018 Rev 2 specific DownShift settings */ 132975eba5b6SRobert Mustacchi #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 133075eba5b6SRobert Mustacchi #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 133175eba5b6SRobert Mustacchi 133275eba5b6SRobert Mustacchi #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 133375eba5b6SRobert Mustacchi #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 133475eba5b6SRobert Mustacchi 133575eba5b6SRobert Mustacchi /* BME1000 PHY Specific Control Register */ 133675eba5b6SRobert Mustacchi #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 133775eba5b6SRobert Mustacchi 133875eba5b6SRobert Mustacchi /* Bits... 133975eba5b6SRobert Mustacchi * 15-5: page 134075eba5b6SRobert Mustacchi * 4-0: register offset 134175eba5b6SRobert Mustacchi */ 134275eba5b6SRobert Mustacchi #define GG82563_PAGE_SHIFT 5 134375eba5b6SRobert Mustacchi #define GG82563_REG(page, reg) \ 134475eba5b6SRobert Mustacchi (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 134575eba5b6SRobert Mustacchi #define GG82563_MIN_ALT_REG 30 134675eba5b6SRobert Mustacchi 134775eba5b6SRobert Mustacchi /* GG82563 Specific Registers */ 134875eba5b6SRobert Mustacchi #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 134975eba5b6SRobert Mustacchi #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 135075eba5b6SRobert Mustacchi #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 135175eba5b6SRobert Mustacchi #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 135275eba5b6SRobert Mustacchi 135375eba5b6SRobert Mustacchi /* MAC Specific Control Register */ 135475eba5b6SRobert Mustacchi #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 135575eba5b6SRobert Mustacchi 135675eba5b6SRobert Mustacchi #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 135775eba5b6SRobert Mustacchi 135875eba5b6SRobert Mustacchi /* Page 193 - Port Control Registers */ 135975eba5b6SRobert Mustacchi /* Kumeran Mode Control */ 136075eba5b6SRobert Mustacchi #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 136175eba5b6SRobert Mustacchi #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 136275eba5b6SRobert Mustacchi 136375eba5b6SRobert Mustacchi /* Page 194 - KMRN Registers */ 136475eba5b6SRobert Mustacchi #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 136575eba5b6SRobert Mustacchi 136675eba5b6SRobert Mustacchi /* MDI Control */ 136775eba5b6SRobert Mustacchi #define E1000_MDIC_REG_MASK 0x001F0000 136875eba5b6SRobert Mustacchi #define E1000_MDIC_REG_SHIFT 16 136975eba5b6SRobert Mustacchi #define E1000_MDIC_PHY_MASK 0x03E00000 137075eba5b6SRobert Mustacchi #define E1000_MDIC_PHY_SHIFT 21 137175eba5b6SRobert Mustacchi #define E1000_MDIC_OP_WRITE 0x04000000 137275eba5b6SRobert Mustacchi #define E1000_MDIC_OP_READ 0x08000000 137375eba5b6SRobert Mustacchi #define E1000_MDIC_READY 0x10000000 137475eba5b6SRobert Mustacchi #define E1000_MDIC_ERROR 0x40000000 137575eba5b6SRobert Mustacchi #define E1000_MDIC_DEST 0x80000000 137675eba5b6SRobert Mustacchi 137775eba5b6SRobert Mustacchi /* SerDes Control */ 137875eba5b6SRobert Mustacchi #define E1000_GEN_CTL_READY 0x80000000 137975eba5b6SRobert Mustacchi #define E1000_GEN_CTL_ADDRESS_SHIFT 8 138075eba5b6SRobert Mustacchi #define E1000_GEN_POLL_TIMEOUT 640 138175eba5b6SRobert Mustacchi 138275eba5b6SRobert Mustacchi /* LinkSec register fields */ 138375eba5b6SRobert Mustacchi #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 138475eba5b6SRobert Mustacchi #define E1000_LSECTXCAP_SUM_SHIFT 16 138575eba5b6SRobert Mustacchi #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 138675eba5b6SRobert Mustacchi #define E1000_LSECRXCAP_SUM_SHIFT 16 138775eba5b6SRobert Mustacchi 138875eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_EN_MASK 0x00000003 138975eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_DISABLE 0x0 139075eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_AUTH 0x1 139175eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 139275eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_AISCI 0x00000020 139375eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 139475eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 139575eba5b6SRobert Mustacchi 139675eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 139775eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_EN_SHIFT 2 139875eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_DISABLE 0x0 139975eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_CHECK 0x1 140075eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_STRICT 0x2 140175eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_DROP 0x3 140275eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_PLSH 0x00000040 140375eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_RP 0x00000080 140475eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 140575eba5b6SRobert Mustacchi 140675eba5b6SRobert Mustacchi /* Tx Rate-Scheduler Config fields */ 140775eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RS_ENA 0x80000000 140875eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 140975eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RF_INT_SHIFT 14 141075eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RF_INT_MASK \ 141175eba5b6SRobert Mustacchi (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 141275eba5b6SRobert Mustacchi 141375eba5b6SRobert Mustacchi /* DMA Coalescing register fields */ 141475eba5b6SRobert Mustacchi /* DMA Coalescing Watchdog Timer */ 141575eba5b6SRobert Mustacchi #define E1000_DMACR_DMACWT_MASK 0x00003FFF 141675eba5b6SRobert Mustacchi /* DMA Coalescing Rx Threshold */ 141775eba5b6SRobert Mustacchi #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 141875eba5b6SRobert Mustacchi #define E1000_DMACR_DMACTHR_SHIFT 16 141975eba5b6SRobert Mustacchi /* Lx when no PCIe transactions */ 142075eba5b6SRobert Mustacchi #define E1000_DMACR_DMAC_LX_MASK 0x30000000 142175eba5b6SRobert Mustacchi #define E1000_DMACR_DMAC_LX_SHIFT 28 142275eba5b6SRobert Mustacchi #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 142375eba5b6SRobert Mustacchi /* DMA Coalescing BMC-to-OS Watchdog Enable */ 142475eba5b6SRobert Mustacchi #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 142575eba5b6SRobert Mustacchi 142675eba5b6SRobert Mustacchi /* DMA Coalescing Transmit Threshold */ 142775eba5b6SRobert Mustacchi #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 142875eba5b6SRobert Mustacchi 142975eba5b6SRobert Mustacchi #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 143075eba5b6SRobert Mustacchi 143175eba5b6SRobert Mustacchi /* Rx Traffic Rate Threshold */ 143275eba5b6SRobert Mustacchi #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF 143375eba5b6SRobert Mustacchi /* Rx packet rate in current window */ 143475eba5b6SRobert Mustacchi #define E1000_DMCRTRH_LRPRCW 0x80000000 143575eba5b6SRobert Mustacchi 143675eba5b6SRobert Mustacchi /* DMA Coal Rx Traffic Current Count */ 143775eba5b6SRobert Mustacchi #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 143875eba5b6SRobert Mustacchi 143975eba5b6SRobert Mustacchi /* Flow ctrl Rx Threshold High val */ 144075eba5b6SRobert Mustacchi #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 144175eba5b6SRobert Mustacchi #define E1000_FCRTC_RTH_COAL_SHIFT 4 144275eba5b6SRobert Mustacchi /* Lx power decision based on DMA coal */ 144375eba5b6SRobert Mustacchi #define E1000_PCIEMISC_LX_DECISION 0x00000080 144475eba5b6SRobert Mustacchi 144575eba5b6SRobert Mustacchi #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 144675eba5b6SRobert Mustacchi #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 144775eba5b6SRobert Mustacchi #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1448c124a83eSRobert Mustacchi #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1449c124a83eSRobert Mustacchi #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1450c124a83eSRobert Mustacchi 145175eba5b6SRobert Mustacchi #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ 145275eba5b6SRobert Mustacchi #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ 145375eba5b6SRobert Mustacchi 145475eba5b6SRobert Mustacchi /* Proxy Filter Control */ 145575eba5b6SRobert Mustacchi #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 145675eba5b6SRobert Mustacchi #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 145775eba5b6SRobert Mustacchi #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 145875eba5b6SRobert Mustacchi #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 145975eba5b6SRobert Mustacchi #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 146075eba5b6SRobert Mustacchi #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 146175eba5b6SRobert Mustacchi #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 146275eba5b6SRobert Mustacchi #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 146375eba5b6SRobert Mustacchi #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 146475eba5b6SRobert Mustacchi /* Proxy Status */ 146575eba5b6SRobert Mustacchi #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 146675eba5b6SRobert Mustacchi 146775eba5b6SRobert Mustacchi /* Firmware Status */ 146875eba5b6SRobert Mustacchi #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 146975eba5b6SRobert Mustacchi /* VF Control */ 147075eba5b6SRobert Mustacchi #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */ 147175eba5b6SRobert Mustacchi 147275eba5b6SRobert Mustacchi #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 147375eba5b6SRobert Mustacchi /* Lan ID bit field offset in status register */ 147475eba5b6SRobert Mustacchi #define E1000_STATUS_LAN_ID_OFFSET 2 147575eba5b6SRobert Mustacchi #define E1000_VFTA_ENTRIES 128 1476c124a83eSRobert Mustacchi #define E1000_UNUSEDARG 1477c124a83eSRobert Mustacchi #ifndef ERROR_REPORT 1478c124a83eSRobert Mustacchi #define ERROR_REPORT(fmt) do { } while (0) 1479c124a83eSRobert Mustacchi #endif /* ERROR_REPORT */ 148049b78600SRobert Mustacchi 148149b78600SRobert Mustacchi /* 148249b78600SRobert Mustacchi * illumos additions 148349b78600SRobert Mustacchi */ 148449b78600SRobert Mustacchi #define NVM_VERSION 0x0005 148549b78600SRobert Mustacchi #define NVM_OEM_OFFSET_0 6 148649b78600SRobert Mustacchi #define NVM_OEM_OFFSET_1 7 148749b78600SRobert Mustacchi 148875eba5b6SRobert Mustacchi #endif /* _E1000_DEFINES_H_ */ 1489