175eba5b6SRobert Mustacchi /****************************************************************************** 275eba5b6SRobert Mustacchi 3*49b78600SRobert Mustacchi Copyright (c) 2001-2015, Intel Corporation 475eba5b6SRobert Mustacchi All rights reserved. 575eba5b6SRobert Mustacchi 675eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 775eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 875eba5b6SRobert Mustacchi 975eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1075eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 1175eba5b6SRobert Mustacchi 1275eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 1375eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1475eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 1575eba5b6SRobert Mustacchi 1675eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 1775eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 1875eba5b6SRobert Mustacchi this software without specific prior written permission. 1975eba5b6SRobert Mustacchi 2075eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2175eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2275eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2375eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2475eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2575eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2675eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2775eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2875eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2975eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3075eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 3175eba5b6SRobert Mustacchi 3275eba5b6SRobert Mustacchi ******************************************************************************/ 3375eba5b6SRobert Mustacchi /*$FreeBSD$*/ 3475eba5b6SRobert Mustacchi 3575eba5b6SRobert Mustacchi #ifndef _E1000_82575_H_ 3675eba5b6SRobert Mustacchi #define _E1000_82575_H_ 3775eba5b6SRobert Mustacchi 3875eba5b6SRobert Mustacchi #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 3975eba5b6SRobert Mustacchi (ID_LED_DEF1_DEF2 << 8) | \ 4075eba5b6SRobert Mustacchi (ID_LED_DEF1_DEF2 << 4) | \ 4175eba5b6SRobert Mustacchi (ID_LED_OFF1_ON2)) 4275eba5b6SRobert Mustacchi /* 4375eba5b6SRobert Mustacchi * Receive Address Register Count 4475eba5b6SRobert Mustacchi * Number of high/low register pairs in the RAR. The RAR (Receive Address 4575eba5b6SRobert Mustacchi * Registers) holds the directed and multicast addresses that we monitor. 4675eba5b6SRobert Mustacchi * These entries are also used for MAC-based filtering. 4775eba5b6SRobert Mustacchi */ 4875eba5b6SRobert Mustacchi /* 4975eba5b6SRobert Mustacchi * For 82576, there are an additional set of RARs that begin at an offset 5075eba5b6SRobert Mustacchi * separate from the first set of RARs. 5175eba5b6SRobert Mustacchi */ 5275eba5b6SRobert Mustacchi #define E1000_RAR_ENTRIES_82575 16 5375eba5b6SRobert Mustacchi #define E1000_RAR_ENTRIES_82576 24 5475eba5b6SRobert Mustacchi #define E1000_RAR_ENTRIES_82580 24 5575eba5b6SRobert Mustacchi #define E1000_RAR_ENTRIES_I350 32 5675eba5b6SRobert Mustacchi #define E1000_SW_SYNCH_MB 0x00000100 5775eba5b6SRobert Mustacchi #define E1000_STAT_DEV_RST_SET 0x00100000 5875eba5b6SRobert Mustacchi #define E1000_CTRL_DEV_RST 0x20000000 5975eba5b6SRobert Mustacchi 6075eba5b6SRobert Mustacchi #ifdef E1000_BIT_FIELDS 6175eba5b6SRobert Mustacchi struct e1000_adv_data_desc { 6275eba5b6SRobert Mustacchi __le64 buffer_addr; /* Address of the descriptor's data buffer */ 6375eba5b6SRobert Mustacchi union { 6475eba5b6SRobert Mustacchi u32 data; 6575eba5b6SRobert Mustacchi struct { 6675eba5b6SRobert Mustacchi u32 datalen:16; /* Data buffer length */ 6775eba5b6SRobert Mustacchi u32 rsvd:4; 6875eba5b6SRobert Mustacchi u32 dtyp:4; /* Descriptor type */ 6975eba5b6SRobert Mustacchi u32 dcmd:8; /* Descriptor command */ 7075eba5b6SRobert Mustacchi } config; 7175eba5b6SRobert Mustacchi } lower; 7275eba5b6SRobert Mustacchi union { 7375eba5b6SRobert Mustacchi u32 data; 7475eba5b6SRobert Mustacchi struct { 7575eba5b6SRobert Mustacchi u32 status:4; /* Descriptor status */ 7675eba5b6SRobert Mustacchi u32 idx:4; 7775eba5b6SRobert Mustacchi u32 popts:6; /* Packet Options */ 7875eba5b6SRobert Mustacchi u32 paylen:18; /* Payload length */ 7975eba5b6SRobert Mustacchi } options; 8075eba5b6SRobert Mustacchi } upper; 8175eba5b6SRobert Mustacchi }; 8275eba5b6SRobert Mustacchi 8375eba5b6SRobert Mustacchi #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 8475eba5b6SRobert Mustacchi #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 8575eba5b6SRobert Mustacchi #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 8675eba5b6SRobert Mustacchi #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 8775eba5b6SRobert Mustacchi #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 8875eba5b6SRobert Mustacchi #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 8975eba5b6SRobert Mustacchi #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 9075eba5b6SRobert Mustacchi #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 9175eba5b6SRobert Mustacchi #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ 9275eba5b6SRobert Mustacchi #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 9375eba5b6SRobert Mustacchi #define E1000_ADV_DCMD_RS 0x8 /* Report Status */ 9475eba5b6SRobert Mustacchi #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 9575eba5b6SRobert Mustacchi #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 9675eba5b6SRobert Mustacchi /* Extended Device Control */ 9775eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 9875eba5b6SRobert Mustacchi 9975eba5b6SRobert Mustacchi struct e1000_adv_context_desc { 10075eba5b6SRobert Mustacchi union { 10175eba5b6SRobert Mustacchi u32 ip_config; 10275eba5b6SRobert Mustacchi struct { 10375eba5b6SRobert Mustacchi u32 iplen:9; 10475eba5b6SRobert Mustacchi u32 maclen:7; 10575eba5b6SRobert Mustacchi u32 vlan_tag:16; 10675eba5b6SRobert Mustacchi } fields; 10775eba5b6SRobert Mustacchi } ip_setup; 10875eba5b6SRobert Mustacchi u32 seq_num; 10975eba5b6SRobert Mustacchi union { 11075eba5b6SRobert Mustacchi u64 l4_config; 11175eba5b6SRobert Mustacchi struct { 11275eba5b6SRobert Mustacchi u32 mkrloc:9; 11375eba5b6SRobert Mustacchi u32 tucmd:11; 11475eba5b6SRobert Mustacchi u32 dtyp:4; 11575eba5b6SRobert Mustacchi u32 adv:8; 11675eba5b6SRobert Mustacchi u32 rsvd:4; 11775eba5b6SRobert Mustacchi u32 idx:4; 11875eba5b6SRobert Mustacchi u32 l4len:8; 11975eba5b6SRobert Mustacchi u32 mss:16; 12075eba5b6SRobert Mustacchi } fields; 12175eba5b6SRobert Mustacchi } l4_setup; 12275eba5b6SRobert Mustacchi }; 12375eba5b6SRobert Mustacchi #endif 12475eba5b6SRobert Mustacchi 12575eba5b6SRobert Mustacchi /* SRRCTL bit definitions */ 12675eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 12775eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 12875eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 12975eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 13075eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 13175eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 13275eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 13375eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 13475eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 13575eba5b6SRobert Mustacchi #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 13675eba5b6SRobert Mustacchi #define E1000_SRRCTL_TIMESTAMP 0x40000000 13775eba5b6SRobert Mustacchi #define E1000_SRRCTL_DROP_EN 0x80000000 13875eba5b6SRobert Mustacchi 13975eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 14075eba5b6SRobert Mustacchi #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 14175eba5b6SRobert Mustacchi 14275eba5b6SRobert Mustacchi #define E1000_TX_HEAD_WB_ENABLE 0x1 14375eba5b6SRobert Mustacchi #define E1000_TX_SEQNUM_WB_ENABLE 0x2 14475eba5b6SRobert Mustacchi 14575eba5b6SRobert Mustacchi #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 14675eba5b6SRobert Mustacchi #define E1000_MRQC_ENABLE_VMDQ 0x00000003 14775eba5b6SRobert Mustacchi #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 14875eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 14975eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 15075eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 15175eba5b6SRobert Mustacchi #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 15275eba5b6SRobert Mustacchi 15375eba5b6SRobert Mustacchi #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 15475eba5b6SRobert Mustacchi #define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ 15575eba5b6SRobert Mustacchi E1000_VMRCTL_MIRROR_PORT_SHIFT) 15675eba5b6SRobert Mustacchi #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 15775eba5b6SRobert Mustacchi #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 15875eba5b6SRobert Mustacchi #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 15975eba5b6SRobert Mustacchi 16075eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE ( \ 16175eba5b6SRobert Mustacchi E1000_EICR_TX_QUEUE0 | \ 16275eba5b6SRobert Mustacchi E1000_EICR_TX_QUEUE1 | \ 16375eba5b6SRobert Mustacchi E1000_EICR_TX_QUEUE2 | \ 16475eba5b6SRobert Mustacchi E1000_EICR_TX_QUEUE3) 16575eba5b6SRobert Mustacchi 16675eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE ( \ 16775eba5b6SRobert Mustacchi E1000_EICR_RX_QUEUE0 | \ 16875eba5b6SRobert Mustacchi E1000_EICR_RX_QUEUE1 | \ 16975eba5b6SRobert Mustacchi E1000_EICR_RX_QUEUE2 | \ 17075eba5b6SRobert Mustacchi E1000_EICR_RX_QUEUE3) 17175eba5b6SRobert Mustacchi 17275eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 17375eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 17475eba5b6SRobert Mustacchi 17575eba5b6SRobert Mustacchi #define EIMS_ENABLE_MASK ( \ 17675eba5b6SRobert Mustacchi E1000_EIMS_RX_QUEUE | \ 17775eba5b6SRobert Mustacchi E1000_EIMS_TX_QUEUE | \ 17875eba5b6SRobert Mustacchi E1000_EIMS_TCP_TIMER | \ 17975eba5b6SRobert Mustacchi E1000_EIMS_OTHER) 18075eba5b6SRobert Mustacchi 18175eba5b6SRobert Mustacchi /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 18275eba5b6SRobert Mustacchi #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 18375eba5b6SRobert Mustacchi #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 18475eba5b6SRobert Mustacchi #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 18575eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 18675eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 18775eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 18875eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 18975eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 19075eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 19175eba5b6SRobert Mustacchi #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 19275eba5b6SRobert Mustacchi 19375eba5b6SRobert Mustacchi /* Receive Descriptor - Advanced */ 19475eba5b6SRobert Mustacchi union e1000_adv_rx_desc { 19575eba5b6SRobert Mustacchi struct { 19675eba5b6SRobert Mustacchi __le64 pkt_addr; /* Packet buffer address */ 19775eba5b6SRobert Mustacchi __le64 hdr_addr; /* Header buffer address */ 19875eba5b6SRobert Mustacchi } read; 19975eba5b6SRobert Mustacchi struct { 20075eba5b6SRobert Mustacchi struct { 20175eba5b6SRobert Mustacchi union { 20275eba5b6SRobert Mustacchi __le32 data; 20375eba5b6SRobert Mustacchi struct { 20475eba5b6SRobert Mustacchi __le16 pkt_info; /*RSS type, Pkt type*/ 20575eba5b6SRobert Mustacchi /* Split Header, header buffer len */ 20675eba5b6SRobert Mustacchi __le16 hdr_info; 20775eba5b6SRobert Mustacchi } hs_rss; 20875eba5b6SRobert Mustacchi } lo_dword; 20975eba5b6SRobert Mustacchi union { 21075eba5b6SRobert Mustacchi __le32 rss; /* RSS Hash */ 21175eba5b6SRobert Mustacchi struct { 21275eba5b6SRobert Mustacchi __le16 ip_id; /* IP id */ 21375eba5b6SRobert Mustacchi __le16 csum; /* Packet Checksum */ 21475eba5b6SRobert Mustacchi } csum_ip; 21575eba5b6SRobert Mustacchi } hi_dword; 21675eba5b6SRobert Mustacchi } lower; 21775eba5b6SRobert Mustacchi struct { 21875eba5b6SRobert Mustacchi __le32 status_error; /* ext status/error */ 21975eba5b6SRobert Mustacchi __le16 length; /* Packet length */ 22075eba5b6SRobert Mustacchi __le16 vlan; /* VLAN tag */ 22175eba5b6SRobert Mustacchi } upper; 22275eba5b6SRobert Mustacchi } wb; /* writeback */ 22375eba5b6SRobert Mustacchi }; 22475eba5b6SRobert Mustacchi 22575eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F 22675eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_SHIFT 12 22775eba5b6SRobert Mustacchi #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 22875eba5b6SRobert Mustacchi #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 22975eba5b6SRobert Mustacchi #define E1000_RXDADV_SPLITHEADER_EN 0x00001000 23075eba5b6SRobert Mustacchi #define E1000_RXDADV_SPH 0x8000 23175eba5b6SRobert Mustacchi #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 23275eba5b6SRobert Mustacchi #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 23375eba5b6SRobert Mustacchi #define E1000_RXDADV_ERR_HBO 0x00800000 23475eba5b6SRobert Mustacchi 23575eba5b6SRobert Mustacchi /* RSS Hash results */ 23675eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_NONE 0x00000000 23775eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 23875eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 23975eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 24075eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 24175eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 24275eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 24375eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 24475eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 24575eba5b6SRobert Mustacchi #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 24675eba5b6SRobert Mustacchi 24775eba5b6SRobert Mustacchi /* RSS Packet Types as indicated in the receive descriptor */ 248c124a83eSRobert Mustacchi #define E1000_RXDADV_PKTTYPE_ILMASK 0x000000F0 249c124a83eSRobert Mustacchi #define E1000_RXDADV_PKTTYPE_TLMASK 0x00000F00 25075eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_NONE 0x00000000 25175eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 25275eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 25375eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 25475eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 25575eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 25675eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 25775eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 25875eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 25975eba5b6SRobert Mustacchi 26075eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 26175eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 26275eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 26375eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 26475eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 26575eba5b6SRobert Mustacchi #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 26675eba5b6SRobert Mustacchi 26775eba5b6SRobert Mustacchi /* LinkSec results */ 26875eba5b6SRobert Mustacchi /* Security Processing bit Indication */ 26975eba5b6SRobert Mustacchi #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 27075eba5b6SRobert Mustacchi #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 27175eba5b6SRobert Mustacchi #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 27275eba5b6SRobert Mustacchi #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 27375eba5b6SRobert Mustacchi #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 27475eba5b6SRobert Mustacchi 27575eba5b6SRobert Mustacchi #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 27675eba5b6SRobert Mustacchi #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 27775eba5b6SRobert Mustacchi #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 27875eba5b6SRobert Mustacchi #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 27975eba5b6SRobert Mustacchi #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 28075eba5b6SRobert Mustacchi 28175eba5b6SRobert Mustacchi /* Transmit Descriptor - Advanced */ 28275eba5b6SRobert Mustacchi union e1000_adv_tx_desc { 28375eba5b6SRobert Mustacchi struct { 28475eba5b6SRobert Mustacchi __le64 buffer_addr; /* Address of descriptor's data buf */ 28575eba5b6SRobert Mustacchi __le32 cmd_type_len; 28675eba5b6SRobert Mustacchi __le32 olinfo_status; 28775eba5b6SRobert Mustacchi } read; 28875eba5b6SRobert Mustacchi struct { 28975eba5b6SRobert Mustacchi __le64 rsvd; /* Reserved */ 29075eba5b6SRobert Mustacchi __le32 nxtseq_seed; 29175eba5b6SRobert Mustacchi __le32 status; 29275eba5b6SRobert Mustacchi } wb; 29375eba5b6SRobert Mustacchi }; 29475eba5b6SRobert Mustacchi 29575eba5b6SRobert Mustacchi /* Adv Transmit Descriptor Config Masks */ 29675eba5b6SRobert Mustacchi #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 29775eba5b6SRobert Mustacchi #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 29875eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 29975eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 30075eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 30175eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 30275eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 30375eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 30475eba5b6SRobert Mustacchi #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 30575eba5b6SRobert Mustacchi #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 30675eba5b6SRobert Mustacchi #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 30775eba5b6SRobert Mustacchi #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 30875eba5b6SRobert Mustacchi #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 30975eba5b6SRobert Mustacchi #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 31075eba5b6SRobert Mustacchi #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 31175eba5b6SRobert Mustacchi #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 31275eba5b6SRobert Mustacchi /* 1st & Last TSO-full iSCSI PDU*/ 31375eba5b6SRobert Mustacchi #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 31475eba5b6SRobert Mustacchi #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 31575eba5b6SRobert Mustacchi #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 31675eba5b6SRobert Mustacchi 31775eba5b6SRobert Mustacchi /* Context descriptors */ 31875eba5b6SRobert Mustacchi struct e1000_adv_tx_context_desc { 31975eba5b6SRobert Mustacchi __le32 vlan_macip_lens; 32075eba5b6SRobert Mustacchi __le32 seqnum_seed; 32175eba5b6SRobert Mustacchi __le32 type_tucmd_mlhl; 32275eba5b6SRobert Mustacchi __le32 mss_l4len_idx; 32375eba5b6SRobert Mustacchi }; 32475eba5b6SRobert Mustacchi 32575eba5b6SRobert Mustacchi #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 32675eba5b6SRobert Mustacchi #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 32775eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 32875eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 32975eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 33075eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 33175eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 33275eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 33375eba5b6SRobert Mustacchi /* IPSec Encrypt Enable for ESP */ 33475eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 33575eba5b6SRobert Mustacchi /* Req requires Markers and CRC */ 33675eba5b6SRobert Mustacchi #define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 33775eba5b6SRobert Mustacchi #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 33875eba5b6SRobert Mustacchi #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 33975eba5b6SRobert Mustacchi /* Adv ctxt IPSec SA IDX mask */ 34075eba5b6SRobert Mustacchi #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 34175eba5b6SRobert Mustacchi /* Adv ctxt IPSec ESP len mask */ 34275eba5b6SRobert Mustacchi #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 34375eba5b6SRobert Mustacchi 34475eba5b6SRobert Mustacchi /* Additional Transmit Descriptor Control definitions */ 34575eba5b6SRobert Mustacchi #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 34675eba5b6SRobert Mustacchi #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ 34775eba5b6SRobert Mustacchi /* Tx Queue Arbitration Priority 0=low, 1=high */ 34875eba5b6SRobert Mustacchi #define E1000_TXDCTL_PRIORITY 0x08000000 34975eba5b6SRobert Mustacchi 35075eba5b6SRobert Mustacchi /* Additional Receive Descriptor Control definitions */ 35175eba5b6SRobert Mustacchi #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 35275eba5b6SRobert Mustacchi #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ 35375eba5b6SRobert Mustacchi 35475eba5b6SRobert Mustacchi /* Direct Cache Access (DCA) definitions */ 35575eba5b6SRobert Mustacchi #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 35675eba5b6SRobert Mustacchi #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 35775eba5b6SRobert Mustacchi 35875eba5b6SRobert Mustacchi #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 35975eba5b6SRobert Mustacchi #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 36075eba5b6SRobert Mustacchi 36175eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 36275eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 36375eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ 36475eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ 36575eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ 36675eba5b6SRobert Mustacchi 36775eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 36875eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 36975eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 37075eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 37175eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 37275eba5b6SRobert Mustacchi 37375eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 37475eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 37575eba5b6SRobert Mustacchi #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 37675eba5b6SRobert Mustacchi #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 37775eba5b6SRobert Mustacchi 37875eba5b6SRobert Mustacchi /* Additional interrupt register bit definitions */ 37975eba5b6SRobert Mustacchi #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 38075eba5b6SRobert Mustacchi #define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 38175eba5b6SRobert Mustacchi #define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 38275eba5b6SRobert Mustacchi 38375eba5b6SRobert Mustacchi /* ETQF register bit definitions */ 38475eba5b6SRobert Mustacchi #define E1000_ETQF_FILTER_ENABLE (1 << 26) 38575eba5b6SRobert Mustacchi #define E1000_ETQF_IMM_INT (1 << 29) 38675eba5b6SRobert Mustacchi #define E1000_ETQF_1588 (1 << 30) 387c124a83eSRobert Mustacchi #define E1000_ETQF_QUEUE_ENABLE (1UL << 31) 38875eba5b6SRobert Mustacchi /* 38975eba5b6SRobert Mustacchi * ETQF filter list: one static filter per filter consumer. This is 39075eba5b6SRobert Mustacchi * to avoid filter collisions later. Add new filters 39175eba5b6SRobert Mustacchi * here!! 39275eba5b6SRobert Mustacchi * 39375eba5b6SRobert Mustacchi * Current filters: 39475eba5b6SRobert Mustacchi * EAPOL 802.1x (0x888e): Filter 0 39575eba5b6SRobert Mustacchi */ 39675eba5b6SRobert Mustacchi #define E1000_ETQF_FILTER_EAPOL 0 39775eba5b6SRobert Mustacchi 39875eba5b6SRobert Mustacchi #define E1000_FTQF_VF_BP 0x00008000 39975eba5b6SRobert Mustacchi #define E1000_FTQF_1588_TIME_STAMP 0x08000000 40075eba5b6SRobert Mustacchi #define E1000_FTQF_MASK 0xF0000000 40175eba5b6SRobert Mustacchi #define E1000_FTQF_MASK_PROTO_BP 0x10000000 40275eba5b6SRobert Mustacchi #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 40375eba5b6SRobert Mustacchi #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 40475eba5b6SRobert Mustacchi #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 40575eba5b6SRobert Mustacchi 40675eba5b6SRobert Mustacchi #define E1000_NVM_APME_82575 0x0400 40775eba5b6SRobert Mustacchi #define MAX_NUM_VFS 7 40875eba5b6SRobert Mustacchi 40975eba5b6SRobert Mustacchi #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ 41075eba5b6SRobert Mustacchi #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ 41175eba5b6SRobert Mustacchi #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 41275eba5b6SRobert Mustacchi #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 41375eba5b6SRobert Mustacchi #define E1000_DTXSWC_LLE_SHIFT 16 41475eba5b6SRobert Mustacchi #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1UL << 31) /* global VF LB enable */ 41575eba5b6SRobert Mustacchi 41675eba5b6SRobert Mustacchi /* Easy defines for setting default pool, would normally be left a zero */ 41775eba5b6SRobert Mustacchi #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 41875eba5b6SRobert Mustacchi #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 41975eba5b6SRobert Mustacchi 42075eba5b6SRobert Mustacchi /* Other useful VMD_CTL register defines */ 42175eba5b6SRobert Mustacchi #define E1000_VT_CTL_IGNORE_MAC (1 << 28) 42275eba5b6SRobert Mustacchi #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 42375eba5b6SRobert Mustacchi #define E1000_VT_CTL_VM_REPL_EN (1 << 30) 42475eba5b6SRobert Mustacchi 42575eba5b6SRobert Mustacchi /* Per VM Offload register setup */ 42675eba5b6SRobert Mustacchi #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 42775eba5b6SRobert Mustacchi #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 42875eba5b6SRobert Mustacchi #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 42975eba5b6SRobert Mustacchi #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 43075eba5b6SRobert Mustacchi #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 43175eba5b6SRobert Mustacchi #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 43275eba5b6SRobert Mustacchi #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 43375eba5b6SRobert Mustacchi #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 43475eba5b6SRobert Mustacchi #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 43575eba5b6SRobert Mustacchi #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 43675eba5b6SRobert Mustacchi 43775eba5b6SRobert Mustacchi #define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */ 43875eba5b6SRobert Mustacchi #define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */ 43975eba5b6SRobert Mustacchi #define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */ 44075eba5b6SRobert Mustacchi #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 44175eba5b6SRobert Mustacchi #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 44275eba5b6SRobert Mustacchi 44375eba5b6SRobert Mustacchi #define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */ 44475eba5b6SRobert Mustacchi #define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */ 44575eba5b6SRobert Mustacchi 44675eba5b6SRobert Mustacchi #define E1000_VLVF_ARRAY_SIZE 32 44775eba5b6SRobert Mustacchi #define E1000_VLVF_VLANID_MASK 0x00000FFF 44875eba5b6SRobert Mustacchi #define E1000_VLVF_POOLSEL_SHIFT 12 44975eba5b6SRobert Mustacchi #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 45075eba5b6SRobert Mustacchi #define E1000_VLVF_LVLAN 0x00100000 45175eba5b6SRobert Mustacchi #define E1000_VLVF_VLANID_ENABLE 0x80000000 45275eba5b6SRobert Mustacchi 45375eba5b6SRobert Mustacchi #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 45475eba5b6SRobert Mustacchi #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 45575eba5b6SRobert Mustacchi 45675eba5b6SRobert Mustacchi #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 45775eba5b6SRobert Mustacchi 45875eba5b6SRobert Mustacchi #define E1000_IOVCTL 0x05BBC 45975eba5b6SRobert Mustacchi #define E1000_IOVCTL_REUSE_VFQ 0x00000001 46075eba5b6SRobert Mustacchi 46175eba5b6SRobert Mustacchi #define E1000_RPLOLR_STRVLAN 0x40000000 46275eba5b6SRobert Mustacchi #define E1000_RPLOLR_STRCRC 0x80000000 46375eba5b6SRobert Mustacchi 46475eba5b6SRobert Mustacchi #define E1000_TCTL_EXT_COLD 0x000FFC00 46575eba5b6SRobert Mustacchi #define E1000_TCTL_EXT_COLD_SHIFT 10 46675eba5b6SRobert Mustacchi 46775eba5b6SRobert Mustacchi #define E1000_DTXCTL_8023LL 0x0004 46875eba5b6SRobert Mustacchi #define E1000_DTXCTL_VLAN_ADDED 0x0008 46975eba5b6SRobert Mustacchi #define E1000_DTXCTL_OOS_ENABLE 0x0010 47075eba5b6SRobert Mustacchi #define E1000_DTXCTL_MDP_EN 0x0020 47175eba5b6SRobert Mustacchi #define E1000_DTXCTL_SPOOF_INT 0x0040 47275eba5b6SRobert Mustacchi 47375eba5b6SRobert Mustacchi #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 47475eba5b6SRobert Mustacchi 47575eba5b6SRobert Mustacchi #define ALL_QUEUES 0xFFFF 47675eba5b6SRobert Mustacchi 47775eba5b6SRobert Mustacchi /* Rx packet buffer size defines */ 47875eba5b6SRobert Mustacchi #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 47975eba5b6SRobert Mustacchi void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); 48075eba5b6SRobert Mustacchi void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf); 48175eba5b6SRobert Mustacchi void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); 48275eba5b6SRobert Mustacchi s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 483c124a83eSRobert Mustacchi s32 e1000_init_hw_82575(struct e1000_hw *hw); 48475eba5b6SRobert Mustacchi 48575eba5b6SRobert Mustacchi enum e1000_promisc_type { 48675eba5b6SRobert Mustacchi e1000_promisc_disabled = 0, /* all promisc modes disabled */ 48775eba5b6SRobert Mustacchi e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 48875eba5b6SRobert Mustacchi e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 48975eba5b6SRobert Mustacchi e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 49075eba5b6SRobert Mustacchi e1000_num_promisc_types 49175eba5b6SRobert Mustacchi }; 49275eba5b6SRobert Mustacchi 49375eba5b6SRobert Mustacchi void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 49475eba5b6SRobert Mustacchi void e1000_rlpml_set_vf(struct e1000_hw *, u16); 49575eba5b6SRobert Mustacchi s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type); 49675eba5b6SRobert Mustacchi u16 e1000_rxpbs_adjust_82580(u32 data); 497c124a83eSRobert Mustacchi s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data); 498*49b78600SRobert Mustacchi s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M); 499*49b78600SRobert Mustacchi s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M); 50013485e69SGarrett D'Amore s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *); 501c124a83eSRobert Mustacchi s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw); 502*49b78600SRobert Mustacchi s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw); 50375eba5b6SRobert Mustacchi 50475eba5b6SRobert Mustacchi /* I2C SDA and SCL timing parameters for standard mode */ 50575eba5b6SRobert Mustacchi #define E1000_I2C_T_HD_STA 4 50675eba5b6SRobert Mustacchi #define E1000_I2C_T_LOW 5 50775eba5b6SRobert Mustacchi #define E1000_I2C_T_HIGH 4 50875eba5b6SRobert Mustacchi #define E1000_I2C_T_SU_STA 5 50975eba5b6SRobert Mustacchi #define E1000_I2C_T_HD_DATA 5 51075eba5b6SRobert Mustacchi #define E1000_I2C_T_SU_DATA 1 51175eba5b6SRobert Mustacchi #define E1000_I2C_T_RISE 1 51275eba5b6SRobert Mustacchi #define E1000_I2C_T_FALL 1 51375eba5b6SRobert Mustacchi #define E1000_I2C_T_SU_STO 4 51475eba5b6SRobert Mustacchi #define E1000_I2C_T_BUF 5 51575eba5b6SRobert Mustacchi 51675eba5b6SRobert Mustacchi s32 e1000_set_i2c_bb(struct e1000_hw *hw); 51775eba5b6SRobert Mustacchi s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 51875eba5b6SRobert Mustacchi u8 dev_addr, u8 *data); 51975eba5b6SRobert Mustacchi s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 52075eba5b6SRobert Mustacchi u8 dev_addr, u8 data); 52175eba5b6SRobert Mustacchi void e1000_i2c_bus_clear(struct e1000_hw *hw); 52275eba5b6SRobert Mustacchi #endif /* _E1000_82575_H_ */ 523