1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #include <sys/ddi.h> 24 #include <sys/sunddi.h> 25 #include <sys/sunndi.h> 26 #include <sys/modctl.h> 27 #include <sys/conf.h> 28 #include <sys/devops.h> 29 #include <sys/pci.h> 30 #include <sys/atomic.h> 31 #include <sys/types.h> 32 #include <sys/file.h> 33 #include <sys/errno.h> 34 #include <sys/open.h> 35 #include <sys/cred.h> 36 #include <sys/stat.h> 37 #include <sys/mkdev.h> 38 #include <sys/queue.h> 39 40 #include "version.h" 41 #include "common/common.h" 42 #include "common/t4_msg.h" 43 #include "common/t4_regs.h" 44 #include "firmware/t4_fw.h" 45 #include "firmware/t4_cfg.h" 46 #include "firmware/t5_fw.h" 47 #include "firmware/t5_cfg.h" 48 #include "t4_l2t.h" 49 50 static int t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp); 51 static int t4_cb_close(dev_t dev, int flag, int otyp, cred_t *credp); 52 static int t4_cb_ioctl(dev_t dev, int cmd, intptr_t d, int mode, cred_t *credp, 53 int *rp); 54 struct cb_ops t4_cb_ops = { 55 .cb_open = t4_cb_open, 56 .cb_close = t4_cb_close, 57 .cb_strategy = nodev, 58 .cb_print = nodev, 59 .cb_dump = nodev, 60 .cb_read = nodev, 61 .cb_write = nodev, 62 .cb_ioctl = t4_cb_ioctl, 63 .cb_devmap = nodev, 64 .cb_mmap = nodev, 65 .cb_segmap = nodev, 66 .cb_chpoll = nochpoll, 67 .cb_prop_op = ddi_prop_op, 68 .cb_flag = D_MP, 69 .cb_rev = CB_REV, 70 .cb_aread = nodev, 71 .cb_awrite = nodev 72 }; 73 74 static int t4_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, 75 void *arg, void *result); 76 static int t4_bus_config(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, 77 void *arg, dev_info_t **cdipp); 78 static int t4_bus_unconfig(dev_info_t *dip, uint_t flags, 79 ddi_bus_config_op_t op, void *arg); 80 struct bus_ops t4_bus_ops = { 81 .busops_rev = BUSO_REV, 82 .bus_ctl = t4_bus_ctl, 83 .bus_prop_op = ddi_bus_prop_op, 84 .bus_config = t4_bus_config, 85 .bus_unconfig = t4_bus_unconfig, 86 }; 87 88 static int t4_devo_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, 89 void **rp); 90 static int t4_devo_probe(dev_info_t *dip); 91 static int t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 92 static int t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 93 static int t4_devo_quiesce(dev_info_t *dip); 94 struct dev_ops t4_dev_ops = { 95 .devo_rev = DEVO_REV, 96 .devo_getinfo = t4_devo_getinfo, 97 .devo_identify = nulldev, 98 .devo_probe = t4_devo_probe, 99 .devo_attach = t4_devo_attach, 100 .devo_detach = t4_devo_detach, 101 .devo_reset = nodev, 102 .devo_cb_ops = &t4_cb_ops, 103 .devo_bus_ops = &t4_bus_ops, 104 .devo_quiesce = &t4_devo_quiesce, 105 }; 106 107 static struct modldrv modldrv = { 108 .drv_modops = &mod_driverops, 109 .drv_linkinfo = "Chelsio T4 nexus " DRV_VERSION, 110 .drv_dev_ops = &t4_dev_ops 111 }; 112 113 static struct modlinkage modlinkage = { 114 .ml_rev = MODREV_1, 115 .ml_linkage = {&modldrv, NULL}, 116 }; 117 118 void *t4_list; 119 120 struct intrs_and_queues { 121 int intr_type; /* DDI_INTR_TYPE_* */ 122 int nirq; /* Number of vectors */ 123 int intr_fwd; /* Interrupts forwarded */ 124 int ntxq10g; /* # of NIC txq's for each 10G port */ 125 int nrxq10g; /* # of NIC rxq's for each 10G port */ 126 int ntxq1g; /* # of NIC txq's for each 1G port */ 127 int nrxq1g; /* # of NIC rxq's for each 1G port */ 128 #ifndef TCP_OFFLOAD_DISABLE 129 int nofldtxq10g; /* # of TOE txq's for each 10G port */ 130 int nofldrxq10g; /* # of TOE rxq's for each 10G port */ 131 int nofldtxq1g; /* # of TOE txq's for each 1G port */ 132 int nofldrxq1g; /* # of TOE rxq's for each 1G port */ 133 #endif 134 }; 135 136 static int cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, 137 mblk_t *m); 138 static int fw_msg_not_handled(struct adapter *, const __be64 *); 139 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); 140 static unsigned int getpf(struct adapter *sc); 141 static int prep_firmware(struct adapter *sc); 142 static int upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma); 143 static int partition_resources(struct adapter *sc); 144 static int get_params__pre_init(struct adapter *sc); 145 static int get_params__post_init(struct adapter *sc); 146 static int set_params__post_init(struct adapter *); 147 static void setup_memwin(struct adapter *sc); 148 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 149 uint32_t *); 150 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 151 uint32_t position_memwin(struct adapter *, int, uint32_t); 152 static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, 153 uint_t count); 154 static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, 155 uint_t count); 156 static int init_driver_props(struct adapter *sc, struct driver_properties *p); 157 static int remove_extra_props(struct adapter *sc, int n10g, int n1g); 158 static int cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 159 struct intrs_and_queues *iaq); 160 static int add_child_node(struct adapter *sc, int idx); 161 static int remove_child_node(struct adapter *sc, int idx); 162 static kstat_t *setup_kstats(struct adapter *sc); 163 static kstat_t *setup_wc_kstats(struct adapter *); 164 static int update_wc_kstats(kstat_t *, int); 165 #ifndef TCP_OFFLOAD_DISABLE 166 static int toe_capability(struct port_info *pi, int enable); 167 static int activate_uld(struct adapter *sc, int id, struct uld_softc *usc); 168 static int deactivate_uld(struct uld_softc *usc); 169 #endif 170 static kmutex_t t4_adapter_list_lock; 171 static SLIST_HEAD(, adapter) t4_adapter_list; 172 #ifndef TCP_OFFLOAD_DISABLE 173 static kmutex_t t4_uld_list_lock; 174 static SLIST_HEAD(, uld_info) t4_uld_list; 175 #endif 176 177 int 178 _init(void) 179 { 180 int rc; 181 182 rc = ddi_soft_state_init(&t4_list, sizeof (struct adapter), 0); 183 if (rc != 0) 184 return (rc); 185 186 rc = mod_install(&modlinkage); 187 if (rc != 0) 188 ddi_soft_state_fini(&t4_list); 189 190 mutex_init(&t4_adapter_list_lock, NULL, MUTEX_DRIVER, NULL); 191 SLIST_INIT(&t4_adapter_list); 192 193 #ifndef TCP_OFFLOAD_DISABLE 194 mutex_init(&t4_uld_list_lock, NULL, MUTEX_DRIVER, NULL); 195 SLIST_INIT(&t4_uld_list); 196 #endif 197 198 return (rc); 199 } 200 201 int 202 _fini(void) 203 { 204 int rc; 205 206 rc = mod_remove(&modlinkage); 207 if (rc != 0) 208 return (rc); 209 210 ddi_soft_state_fini(&t4_list); 211 return (0); 212 } 213 214 int 215 _info(struct modinfo *mi) 216 { 217 return (mod_info(&modlinkage, mi)); 218 } 219 220 /* ARGSUSED */ 221 static int 222 t4_devo_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **rp) 223 { 224 struct adapter *sc; 225 minor_t minor; 226 227 minor = getminor((dev_t)arg); /* same as instance# in our case */ 228 229 if (cmd == DDI_INFO_DEVT2DEVINFO) { 230 sc = ddi_get_soft_state(t4_list, minor); 231 if (sc == NULL) 232 return (DDI_FAILURE); 233 234 ASSERT(sc->dev == (dev_t)arg); 235 *rp = (void *)sc->dip; 236 } else if (cmd == DDI_INFO_DEVT2INSTANCE) 237 *rp = (void *) (unsigned long) minor; 238 else 239 ASSERT(0); 240 241 return (DDI_SUCCESS); 242 } 243 244 static int 245 t4_devo_probe(dev_info_t *dip) 246 { 247 int rc, id, *reg; 248 uint_t n, pf; 249 250 id = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 251 "device-id", 0xffff); 252 if (id == 0xffff) 253 return (DDI_PROBE_DONTCARE); 254 255 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 256 "reg", ®, &n); 257 if (rc != DDI_SUCCESS) 258 return (DDI_PROBE_DONTCARE); 259 260 pf = PCI_REG_FUNC_G(reg[0]); 261 ddi_prop_free(reg); 262 263 /* Prevent driver attachment on any PF except 0 on the FPGA */ 264 if (id == 0xa000 && pf != 0) 265 return (DDI_PROBE_FAILURE); 266 267 return (DDI_PROBE_DONTCARE); 268 } 269 270 static int 271 t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 272 { 273 struct adapter *sc = NULL; 274 struct sge *s; 275 int i, instance, rc = DDI_SUCCESS, n10g, n1g, rqidx, tqidx, q; 276 int irq = 0; 277 #ifndef TCP_OFFLOAD_DISABLE 278 int ofld_rqidx, ofld_tqidx; 279 #endif 280 char name[16]; 281 struct driver_properties *prp; 282 struct intrs_and_queues iaq; 283 ddi_device_acc_attr_t da = { 284 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 285 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 286 .devacc_attr_dataorder = DDI_UNORDERED_OK_ACC 287 }; 288 ddi_device_acc_attr_t da1 = { 289 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 290 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 291 .devacc_attr_dataorder = DDI_MERGING_OK_ACC 292 }; 293 294 if (cmd != DDI_ATTACH) 295 return (DDI_FAILURE); 296 297 /* 298 * Allocate space for soft state. 299 */ 300 instance = ddi_get_instance(dip); 301 rc = ddi_soft_state_zalloc(t4_list, instance); 302 if (rc != DDI_SUCCESS) { 303 cxgb_printf(dip, CE_WARN, 304 "failed to allocate soft state: %d", rc); 305 return (DDI_FAILURE); 306 } 307 308 sc = ddi_get_soft_state(t4_list, instance); 309 sc->dip = dip; 310 sc->dev = makedevice(ddi_driver_major(dip), instance); 311 mutex_init(&sc->lock, NULL, MUTEX_DRIVER, NULL); 312 cv_init(&sc->cv, NULL, CV_DRIVER, NULL); 313 mutex_init(&sc->sfl_lock, NULL, MUTEX_DRIVER, NULL); 314 315 mutex_enter(&t4_adapter_list_lock); 316 SLIST_INSERT_HEAD(&t4_adapter_list, sc, link); 317 mutex_exit(&t4_adapter_list_lock); 318 319 sc->pf = getpf(sc); 320 if (sc->pf > 8) { 321 rc = EINVAL; 322 cxgb_printf(dip, CE_WARN, 323 "failed to determine PCI PF# of device"); 324 goto done; 325 } 326 sc->mbox = sc->pf; 327 328 /* Initialize the driver properties */ 329 prp = &sc->props; 330 (void)init_driver_props(sc, prp); 331 332 /* 333 * Enable access to the PCI config space. 334 */ 335 rc = pci_config_setup(dip, &sc->pci_regh); 336 if (rc != DDI_SUCCESS) { 337 cxgb_printf(dip, CE_WARN, 338 "failed to enable PCI config space access: %d", rc); 339 goto done; 340 } 341 342 /* TODO: Set max read request to 4K */ 343 344 /* 345 * Enable MMIO access. 346 */ 347 rc = ddi_regs_map_setup(dip, 1, &sc->regp, 0, 0, &da, &sc->regh); 348 if (rc != DDI_SUCCESS) { 349 cxgb_printf(dip, CE_WARN, 350 "failed to map device registers: %d", rc); 351 goto done; 352 } 353 354 (void) memset(sc->chan_map, 0xff, sizeof (sc->chan_map)); 355 356 /* 357 * Initialize cpl handler. 358 */ 359 for (i = 0; i < ARRAY_SIZE(sc->cpl_handler); i++) { 360 sc->cpl_handler[i] = cpl_not_handled; 361 } 362 363 for (i = 0; i < ARRAY_SIZE(sc->fw_msg_handler); i++) { 364 sc->fw_msg_handler[i] = fw_msg_not_handled; 365 } 366 367 /* 368 * Prepare the adapter for operation. 369 */ 370 rc = -t4_prep_adapter(sc); 371 if (rc != 0) { 372 cxgb_printf(dip, CE_WARN, "failed to prepare adapter: %d", rc); 373 goto done; 374 } 375 376 /* 377 * Enable BAR1 access. 378 */ 379 sc->doorbells |= DOORBELL_KDB; 380 rc = ddi_regs_map_setup(dip, 2, &sc->reg1p, 0, 0, &da1, &sc->reg1h); 381 if (rc != DDI_SUCCESS) { 382 cxgb_printf(dip, CE_WARN, 383 "failed to map BAR1 device registers: %d", rc); 384 goto done; 385 } else { 386 if (is_t5(sc->params.chip)) { 387 sc->doorbells |= DOORBELL_UDB; 388 if (prp->wc) { 389 /* 390 * Enable write combining on BAR2. This is the 391 * userspace doorbell BAR and is split into 128B 392 * (UDBS_SEG_SIZE) doorbell regions, each associated 393 * with an egress queue. The first 64B has the doorbell 394 * and the second 64B can be used to submit a tx work 395 * request with an implicit doorbell. 396 */ 397 sc->doorbells &= ~DOORBELL_UDB; 398 sc->doorbells |= (DOORBELL_WCWR | 399 DOORBELL_UDBWC); 400 t4_write_reg(sc, A_SGE_STAT_CFG, 401 V_STATSOURCE_T5(7) | V_STATMODE(0)); 402 } 403 } 404 } 405 406 /* 407 * Do this really early. Note that minor number = instance. 408 */ 409 (void) snprintf(name, sizeof (name), "%s,%d", T4_NEXUS_NAME, instance); 410 rc = ddi_create_minor_node(dip, name, S_IFCHR, instance, 411 DDI_NT_NEXUS, 0); 412 if (rc != DDI_SUCCESS) { 413 cxgb_printf(dip, CE_WARN, 414 "failed to create device node: %d", rc); 415 rc = DDI_SUCCESS; /* carry on */ 416 } 417 418 /* Do this early. Memory window is required for loading config file. */ 419 setup_memwin(sc); 420 421 /* Prepare the firmware for operation */ 422 rc = prep_firmware(sc); 423 if (rc != 0) 424 goto done; /* error message displayed already */ 425 426 rc = get_params__pre_init(sc); 427 if (rc != 0) 428 goto done; /* error message displayed already */ 429 430 t4_sge_init(sc); 431 432 if (sc->flags & MASTER_PF) { 433 /* get basic stuff going */ 434 rc = -t4_fw_initialize(sc, sc->mbox); 435 if (rc != 0) { 436 cxgb_printf(sc->dip, CE_WARN, 437 "early init failed: %d.\n", rc); 438 goto done; 439 } 440 } 441 442 rc = get_params__post_init(sc); 443 if (rc != 0) 444 goto done; /* error message displayed already */ 445 446 rc = set_params__post_init(sc); 447 if (rc != 0) 448 goto done; /* error message displayed already */ 449 450 /* 451 * TODO: This is the place to call t4_set_filter_mode() 452 */ 453 454 /* tweak some settings */ 455 t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | 456 V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | 457 V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9)); 458 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 459 460 /* 461 * Work-around for bug 2619 462 * Set DisableVlan field in TP_RSS_CONFIG_VRT register so that the 463 * VLAN tag extraction is disabled. 464 */ 465 t4_set_reg_field(sc, A_TP_RSS_CONFIG_VRT, F_DISABLEVLAN, F_DISABLEVLAN); 466 467 /* Store filter mode */ 468 t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &sc->filter_mode, 1, 469 A_TP_VLAN_PRI_MAP); 470 471 /* 472 * First pass over all the ports - allocate VIs and initialize some 473 * basic parameters like mac address, port type, etc. We also figure 474 * out whether a port is 10G or 1G and use that information when 475 * calculating how many interrupts to attempt to allocate. 476 */ 477 n10g = n1g = 0; 478 for_each_port(sc, i) { 479 struct port_info *pi; 480 481 pi = kmem_zalloc(sizeof (*pi), KM_SLEEP); 482 sc->port[i] = pi; 483 484 /* These must be set before t4_port_init */ 485 pi->adapter = sc; 486 /* LINTED: E_ASSIGN_NARROW_CONV */ 487 pi->port_id = i; 488 489 /* Allocate the vi and initialize parameters like mac addr */ 490 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0); 491 if (rc != 0) { 492 cxgb_printf(dip, CE_WARN, 493 "unable to initialize port %d: %d", i, rc); 494 kmem_free(pi, sizeof (*pi)); 495 sc->port[i] = NULL; /* indicates init failed */ 496 continue; 497 } 498 499 mutex_init(&pi->lock, NULL, MUTEX_DRIVER, NULL); 500 pi->mtu = ETHERMTU; 501 502 if (is_10G_port(pi) || is_40G_port(pi)) { 503 n10g++; 504 pi->tmr_idx = prp->tmr_idx_10g; 505 pi->pktc_idx = prp->pktc_idx_10g; 506 } else { 507 n1g++; 508 pi->tmr_idx = prp->tmr_idx_1g; 509 pi->pktc_idx = prp->pktc_idx_1g; 510 } 511 512 pi->xact_addr_filt = -1; 513 t4_mc_init(pi); 514 515 setbit(&sc->registered_device_map, i); 516 } 517 (void) remove_extra_props(sc, n10g, n1g); 518 519 if (sc->registered_device_map == 0) { 520 cxgb_printf(dip, CE_WARN, "no usable ports"); 521 rc = DDI_FAILURE; 522 goto done; 523 } 524 525 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq); 526 if (rc != 0) 527 goto done; /* error message displayed already */ 528 529 sc->intr_type = iaq.intr_type; 530 sc->intr_count = iaq.nirq; 531 532 s = &sc->sge; 533 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 534 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 535 s->neq = s->ntxq + s->nrxq; /* the fl in an rxq is an eq */ 536 #ifndef TCP_OFFLOAD_DISABLE 537 /* control queues, 1 per port + 1 mgmtq */ 538 s->neq += sc->params.nports + 1; 539 #endif 540 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 541 if (iaq.intr_fwd != 0) 542 sc->flags |= INTR_FWD; 543 #ifndef TCP_OFFLOAD_DISABLE 544 if (is_offload(sc) != 0) { 545 546 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g; 547 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g; 548 s->neq += s->nofldtxq + s->nofldrxq; 549 s->niq += s->nofldrxq; 550 551 s->ofld_rxq = kmem_zalloc(s->nofldrxq * 552 sizeof (struct sge_ofld_rxq), KM_SLEEP); 553 s->ofld_txq = kmem_zalloc(s->nofldtxq * 554 sizeof (struct sge_wrq), KM_SLEEP); 555 s->ctrlq = kmem_zalloc(sc->params.nports * 556 sizeof (struct sge_wrq), KM_SLEEP); 557 558 } 559 #endif 560 s->rxq = kmem_zalloc(s->nrxq * sizeof (struct sge_rxq), KM_SLEEP); 561 s->txq = kmem_zalloc(s->ntxq * sizeof (struct sge_txq), KM_SLEEP); 562 s->iqmap = kmem_zalloc(s->niq * sizeof (struct sge_iq *), KM_SLEEP); 563 s->eqmap = kmem_zalloc(s->neq * sizeof (struct sge_eq *), KM_SLEEP); 564 565 sc->intr_handle = kmem_zalloc(sc->intr_count * 566 sizeof (ddi_intr_handle_t), KM_SLEEP); 567 568 /* 569 * Second pass over the ports. This time we know the number of rx and 570 * tx queues that each port should get. 571 */ 572 rqidx = tqidx = 0; 573 #ifndef TCP_OFFLOAD_DISABLE 574 ofld_rqidx = ofld_tqidx = 0; 575 #endif 576 for_each_port(sc, i) { 577 struct port_info *pi = sc->port[i]; 578 579 if (pi == NULL) 580 continue; 581 582 /* LINTED: E_ASSIGN_NARROW_CONV */ 583 pi->first_rxq = rqidx; 584 /* LINTED: E_ASSIGN_NARROW_CONV */ 585 pi->nrxq = (is_10G_port(pi) || is_40G_port(pi)) ? iaq.nrxq10g 586 : iaq.nrxq1g; 587 /* LINTED: E_ASSIGN_NARROW_CONV */ 588 pi->first_txq = tqidx; 589 /* LINTED: E_ASSIGN_NARROW_CONV */ 590 pi->ntxq = (is_10G_port(pi) || is_40G_port(pi)) ? iaq.ntxq10g 591 : iaq.ntxq1g; 592 593 rqidx += pi->nrxq; 594 tqidx += pi->ntxq; 595 596 #ifndef TCP_OFFLOAD_DISABLE 597 if (is_offload(sc) != 0) { 598 /* LINTED: E_ASSIGN_NARROW_CONV */ 599 pi->first_ofld_rxq = ofld_rqidx; 600 pi->nofldrxq = max(1, pi->nrxq / 4); 601 602 /* LINTED: E_ASSIGN_NARROW_CONV */ 603 pi->first_ofld_txq = ofld_tqidx; 604 pi->nofldtxq = max(1, pi->ntxq / 2); 605 606 ofld_rqidx += pi->nofldrxq; 607 ofld_tqidx += pi->nofldtxq; 608 } 609 #endif 610 611 /* 612 * Enable hw checksumming and LSO for all ports by default. 613 * They can be disabled using ndd (hw_csum and hw_lso). 614 */ 615 pi->features |= (CXGBE_HW_CSUM | CXGBE_HW_LSO); 616 } 617 618 #ifndef TCP_OFFLOAD_DISABLE 619 sc->l2t = t4_init_l2t(sc); 620 #endif 621 622 /* 623 * Setup Interrupts. 624 */ 625 626 i = 0; 627 rc = ddi_intr_alloc(dip, sc->intr_handle, sc->intr_type, 0, 628 sc->intr_count, &i, DDI_INTR_ALLOC_STRICT); 629 if (rc != DDI_SUCCESS) { 630 cxgb_printf(dip, CE_WARN, 631 "failed to allocate %d interrupt(s) of type %d: %d, %d", 632 sc->intr_count, sc->intr_type, rc, i); 633 goto done; 634 } 635 ASSERT(sc->intr_count == i); /* allocation was STRICT */ 636 (void) ddi_intr_get_cap(sc->intr_handle[0], &sc->intr_cap); 637 (void) ddi_intr_get_pri(sc->intr_handle[0], &sc->intr_pri); 638 if (sc->intr_count == 1) { 639 ASSERT(sc->flags & INTR_FWD); 640 (void) ddi_intr_add_handler(sc->intr_handle[0], t4_intr_all, sc, 641 &s->fwq); 642 } else { 643 /* Multiple interrupts. The first one is always error intr */ 644 (void) ddi_intr_add_handler(sc->intr_handle[0], t4_intr_err, sc, 645 NULL); 646 irq++; 647 648 /* The second one is always the firmware event queue */ 649 (void) ddi_intr_add_handler(sc->intr_handle[1], t4_intr, sc, 650 &s->fwq); 651 irq++; 652 /* 653 * Note that if INTR_FWD is set then either the NIC rx 654 * queues or (exclusive or) the TOE rx queueus will be taking 655 * direct interrupts. 656 * 657 * There is no need to check for is_offload(sc) as nofldrxq 658 * will be 0 if offload is disabled. 659 */ 660 for_each_port(sc, i) { 661 struct port_info *pi = sc->port[i]; 662 struct sge_rxq *rxq; 663 struct sge_ofld_rxq *ofld_rxq; 664 665 #ifndef TCP_OFFLOAD_DISABLE 666 /* 667 * Skip over the NIC queues if they aren't taking direct 668 * interrupts. 669 */ 670 if ((sc->flags & INTR_FWD) && 671 pi->nofldrxq > pi->nrxq) 672 goto ofld_queues; 673 #endif 674 rxq = &s->rxq[pi->first_rxq]; 675 for (q = 0; q < pi->nrxq; q++, rxq++) { 676 (void) ddi_intr_add_handler( 677 sc->intr_handle[irq], t4_intr, sc, 678 &rxq->iq); 679 irq++; 680 } 681 682 #ifndef TCP_OFFLOAD_DISABLE 683 /* 684 * Skip over the offload queues if they aren't taking 685 * direct interrupts. 686 */ 687 if ((sc->flags & INTR_FWD)) 688 continue; 689 ofld_queues: 690 ofld_rxq = &s->ofld_rxq[pi->first_ofld_rxq]; 691 for (q = 0; q < pi->nofldrxq; q++, ofld_rxq++) { 692 (void) ddi_intr_add_handler( 693 sc->intr_handle[irq], t4_intr, sc, 694 &ofld_rxq->iq); 695 irq++; 696 } 697 #endif 698 } 699 700 } 701 sc->flags |= INTR_ALLOCATED; 702 703 ASSERT(rc == DDI_SUCCESS); 704 ddi_report_dev(dip); 705 706 if (n10g && n1g) { 707 cxgb_printf(dip, CE_NOTE, 708 "%dx10G %dx1G (%d rxq, %d txq total) %d %s.", 709 n10g, n1g, rqidx, tqidx, sc->intr_count, 710 sc->intr_type == DDI_INTR_TYPE_MSIX ? "MSI-X interrupts" : 711 sc->intr_type == DDI_INTR_TYPE_MSI ? "MSI interrupts" : 712 "fixed interrupt"); 713 } else { 714 cxgb_printf(dip, CE_NOTE, 715 "%dx%sG (%d rxq, %d txq per port) %d %s.", 716 n10g ? n10g : n1g, 717 n10g ? "10" : "1", 718 n10g ? iaq.nrxq10g : iaq.nrxq1g, 719 n10g ? iaq.ntxq10g : iaq.ntxq1g, 720 sc->intr_count, 721 sc->intr_type == DDI_INTR_TYPE_MSIX ? "MSI-X interrupts" : 722 sc->intr_type == DDI_INTR_TYPE_MSI ? "MSI interrupts" : 723 "fixed interrupt"); 724 } 725 726 sc->ksp = setup_kstats(sc); 727 sc->ksp_stat = setup_wc_kstats(sc); 728 729 done: 730 if (rc != DDI_SUCCESS) { 731 (void) t4_devo_detach(dip, DDI_DETACH); 732 733 /* rc may have errno style errors or DDI errors */ 734 rc = DDI_FAILURE; 735 } 736 737 return (rc); 738 } 739 740 static int 741 t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 742 { 743 int instance, i; 744 struct adapter *sc; 745 struct port_info *pi; 746 struct sge *s; 747 748 if (cmd != DDI_DETACH) 749 return (DDI_FAILURE); 750 751 instance = ddi_get_instance(dip); 752 sc = ddi_get_soft_state(t4_list, instance); 753 if (sc == NULL) 754 return (DDI_SUCCESS); 755 756 if (sc->flags & FULL_INIT_DONE) { 757 t4_intr_disable(sc); 758 for_each_port(sc, i) { 759 pi = sc->port[i]; 760 if (pi && pi->flags & PORT_INIT_DONE) 761 (void) port_full_uninit(pi); 762 } 763 (void) adapter_full_uninit(sc); 764 } 765 766 /* Safe to call no matter what */ 767 ddi_prop_remove_all(dip); 768 ddi_remove_minor_node(dip, NULL); 769 770 if (sc->ksp != NULL) 771 kstat_delete(sc->ksp); 772 if (sc->ksp_stat != NULL) 773 kstat_delete(sc->ksp_stat); 774 775 s = &sc->sge; 776 if (s->rxq != NULL) 777 kmem_free(s->rxq, s->nrxq * sizeof (struct sge_rxq)); 778 #ifndef TCP_OFFLOAD_DISABLE 779 if (s->ofld_txq != NULL) 780 kmem_free(s->ofld_txq, s->nofldtxq * sizeof (struct sge_wrq)); 781 if (s->ofld_rxq != NULL) 782 kmem_free(s->ofld_rxq, 783 s->nofldrxq * sizeof (struct sge_ofld_rxq)); 784 if (s->ctrlq != NULL) 785 kmem_free(s->ctrlq, 786 sc->params.nports * sizeof (struct sge_wrq)); 787 #endif 788 if (s->txq != NULL) 789 kmem_free(s->txq, s->ntxq * sizeof (struct sge_txq)); 790 if (s->iqmap != NULL) 791 kmem_free(s->iqmap, s->niq * sizeof (struct sge_iq *)); 792 if (s->eqmap != NULL) 793 kmem_free(s->eqmap, s->neq * sizeof (struct sge_eq *)); 794 795 if (s->rxbuf_cache != NULL) 796 rxbuf_cache_destroy(s->rxbuf_cache); 797 798 if (sc->flags & INTR_ALLOCATED) { 799 for (i = 0; i < sc->intr_count; i++) { 800 (void) ddi_intr_remove_handler(sc->intr_handle[i]); 801 (void) ddi_intr_free(sc->intr_handle[i]); 802 } 803 sc->flags &= ~INTR_ALLOCATED; 804 } 805 806 if (sc->intr_handle != NULL) { 807 kmem_free(sc->intr_handle, 808 sc->intr_count * sizeof (*sc->intr_handle)); 809 } 810 811 for_each_port(sc, i) { 812 pi = sc->port[i]; 813 if (pi != NULL) { 814 mutex_destroy(&pi->lock); 815 kmem_free(pi, sizeof (*pi)); 816 clrbit(&sc->registered_device_map, i); 817 } 818 } 819 820 if (sc->flags & FW_OK) 821 (void) t4_fw_bye(sc, sc->mbox); 822 823 if (sc->reg1h != NULL) 824 ddi_regs_map_free(&sc->reg1h); 825 826 if (sc->regh != NULL) 827 ddi_regs_map_free(&sc->regh); 828 829 if (sc->pci_regh != NULL) 830 pci_config_teardown(&sc->pci_regh); 831 832 mutex_enter(&t4_adapter_list_lock); 833 SLIST_REMOVE_HEAD(&t4_adapter_list, link); 834 mutex_exit(&t4_adapter_list_lock); 835 836 mutex_destroy(&sc->lock); 837 cv_destroy(&sc->cv); 838 mutex_destroy(&sc->sfl_lock); 839 840 #ifdef DEBUG 841 bzero(sc, sizeof (*sc)); 842 #endif 843 ddi_soft_state_free(t4_list, instance); 844 845 return (DDI_SUCCESS); 846 } 847 848 static int 849 t4_devo_quiesce(dev_info_t *dip) 850 { 851 int instance; 852 struct adapter *sc; 853 854 instance = ddi_get_instance(dip); 855 sc = ddi_get_soft_state(t4_list, instance); 856 if (sc == NULL) 857 return (DDI_SUCCESS); 858 859 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 860 t4_intr_disable(sc); 861 t4_write_reg(sc, A_PL_RST, F_PIORSTMODE | F_PIORST); 862 863 return (DDI_SUCCESS); 864 } 865 866 static int 867 t4_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, void *arg, 868 void *result) 869 { 870 char s[4]; 871 struct port_info *pi; 872 dev_info_t *child = (dev_info_t *)arg; 873 874 switch (op) { 875 case DDI_CTLOPS_REPORTDEV: 876 pi = ddi_get_parent_data(rdip); 877 pi->instance = ddi_get_instance(dip); 878 pi->child_inst = ddi_get_instance(rdip); 879 cmn_err(CE_CONT, "?%s%d is port %s on %s%d\n", 880 ddi_node_name(rdip), ddi_get_instance(rdip), 881 ddi_get_name_addr(rdip), ddi_driver_name(dip), 882 ddi_get_instance(dip)); 883 return (DDI_SUCCESS); 884 885 case DDI_CTLOPS_INITCHILD: 886 pi = ddi_get_parent_data(child); 887 if (pi == NULL) 888 return (DDI_NOT_WELL_FORMED); 889 (void) snprintf(s, sizeof (s), "%d", pi->port_id); 890 ddi_set_name_addr(child, s); 891 return (DDI_SUCCESS); 892 893 case DDI_CTLOPS_UNINITCHILD: 894 ddi_set_name_addr(child, NULL); 895 return (DDI_SUCCESS); 896 897 case DDI_CTLOPS_ATTACH: 898 case DDI_CTLOPS_DETACH: 899 return (DDI_SUCCESS); 900 901 default: 902 return (ddi_ctlops(dip, rdip, op, arg, result)); 903 } 904 } 905 906 static int 907 t4_bus_config(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, void *arg, 908 dev_info_t **cdipp) 909 { 910 int instance, i; 911 struct adapter *sc; 912 913 instance = ddi_get_instance(dip); 914 sc = ddi_get_soft_state(t4_list, instance); 915 916 if (op == BUS_CONFIG_ONE) { 917 char *c; 918 919 /* 920 * arg is something like "cxgb@0" where 0 is the port_id hanging 921 * off this nexus. 922 */ 923 924 c = arg; 925 while (*(c + 1)) 926 c++; 927 928 /* There should be exactly 1 digit after '@' */ 929 if (*(c - 1) != '@') 930 return (NDI_FAILURE); 931 932 i = *c - '0'; 933 934 if (add_child_node(sc, i) != 0) 935 return (NDI_FAILURE); 936 937 flags |= NDI_ONLINE_ATTACH; 938 939 } else if (op == BUS_CONFIG_ALL || op == BUS_CONFIG_DRIVER) { 940 /* Allocate and bind all child device nodes */ 941 for_each_port(sc, i) 942 (void) add_child_node(sc, i); 943 flags |= NDI_ONLINE_ATTACH; 944 } 945 946 return (ndi_busop_bus_config(dip, flags, op, arg, cdipp, 0)); 947 } 948 949 static int 950 t4_bus_unconfig(dev_info_t *dip, uint_t flags, ddi_bus_config_op_t op, 951 void *arg) 952 { 953 int instance, i, rc; 954 struct adapter *sc; 955 956 instance = ddi_get_instance(dip); 957 sc = ddi_get_soft_state(t4_list, instance); 958 959 if (op == BUS_CONFIG_ONE || op == BUS_UNCONFIG_ALL || 960 op == BUS_UNCONFIG_DRIVER) 961 flags |= NDI_UNCONFIG; 962 963 rc = ndi_busop_bus_unconfig(dip, flags, op, arg); 964 if (rc != 0) 965 return (rc); 966 967 if (op == BUS_UNCONFIG_ONE) { 968 char *c; 969 970 c = arg; 971 while (*(c + 1)) 972 c++; 973 974 if (*(c - 1) != '@') 975 return (NDI_SUCCESS); 976 977 i = *c - '0'; 978 979 rc = remove_child_node(sc, i); 980 981 } else if (op == BUS_UNCONFIG_ALL || op == BUS_UNCONFIG_DRIVER) { 982 983 for_each_port(sc, i) 984 (void) remove_child_node(sc, i); 985 } 986 987 return (rc); 988 } 989 990 /* ARGSUSED */ 991 static int 992 t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp) 993 { 994 struct adapter *sc; 995 996 if (otyp != OTYP_CHR) 997 return (EINVAL); 998 999 sc = ddi_get_soft_state(t4_list, getminor(*devp)); 1000 if (sc == NULL) 1001 return (ENXIO); 1002 1003 return (atomic_cas_uint(&sc->open, 0, EBUSY)); 1004 } 1005 1006 /* ARGSUSED */ 1007 static int 1008 t4_cb_close(dev_t dev, int flag, int otyp, cred_t *credp) 1009 { 1010 struct adapter *sc; 1011 1012 sc = ddi_get_soft_state(t4_list, getminor(dev)); 1013 if (sc == NULL) 1014 return (EINVAL); 1015 1016 (void) atomic_swap_uint(&sc->open, 0); 1017 return (0); 1018 } 1019 1020 /* ARGSUSED */ 1021 static int 1022 t4_cb_ioctl(dev_t dev, int cmd, intptr_t d, int mode, cred_t *credp, int *rp) 1023 { 1024 int instance; 1025 struct adapter *sc; 1026 void *data = (void *)d; 1027 1028 if (crgetuid(credp) != 0) 1029 return (EPERM); 1030 1031 instance = getminor(dev); 1032 sc = ddi_get_soft_state(t4_list, instance); 1033 if (sc == NULL) 1034 return (EINVAL); 1035 1036 return (t4_ioctl(sc, cmd, data, mode)); 1037 } 1038 1039 static unsigned int 1040 getpf(struct adapter *sc) 1041 { 1042 int rc, *data; 1043 uint_t n, pf; 1044 1045 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, 1046 DDI_PROP_DONTPASS, "reg", &data, &n); 1047 if (rc != DDI_SUCCESS) { 1048 cxgb_printf(sc->dip, CE_WARN, 1049 "failed to lookup \"reg\" property: %d", rc); 1050 return (0xff); 1051 } 1052 1053 pf = PCI_REG_FUNC_G(data[0]); 1054 ddi_prop_free(data); 1055 1056 return (pf); 1057 } 1058 1059 /* 1060 * Install a compatible firmware (if required), establish contact with it, 1061 * become the master, and reset the device. 1062 */ 1063 static int 1064 prep_firmware(struct adapter *sc) 1065 { 1066 int rc; 1067 enum dev_state state; 1068 1069 /* Check firmware version and install a different one if necessary */ 1070 rc = t4_check_fw_version(sc); 1071 if (rc != 0) { 1072 uint32_t v; 1073 if (is_t4(sc->params.chip)) { 1074 /* This is what the driver has */ 1075 v = V_FW_HDR_FW_VER_MAJOR(T4FW_VERSION_MAJOR) | 1076 V_FW_HDR_FW_VER_MINOR(T4FW_VERSION_MINOR) | 1077 V_FW_HDR_FW_VER_MICRO(T4FW_VERSION_MICRO) | 1078 V_FW_HDR_FW_VER_BUILD(T4FW_VERSION_BUILD); 1079 1080 /* 1081 * Always upgrade, even for minor/micro/build mismatches. 1082 * Downgrade only for a major version mismatch. 1083 */ 1084 if (rc < 0 || v > sc->params.fw_vers) { 1085 cxgb_printf(sc->dip, CE_NOTE, 1086 "installing firmware %d.%d.%d.%d on card.", 1087 T4FW_VERSION_MAJOR, T4FW_VERSION_MINOR, 1088 T4FW_VERSION_MICRO, T4FW_VERSION_BUILD); 1089 rc = -t4_load_fw(sc, t4fw_data, t4fw_size); 1090 if (rc != 0) { 1091 cxgb_printf(sc->dip, CE_WARN, 1092 "failed to install firmware: %d", rc); 1093 return (rc); 1094 } else { 1095 /* refresh */ 1096 (void) t4_check_fw_version(sc); 1097 } 1098 } 1099 } else { 1100 v = V_FW_HDR_FW_VER_MAJOR(T5FW_VERSION_MAJOR) | 1101 V_FW_HDR_FW_VER_MINOR(T5FW_VERSION_MINOR) | 1102 V_FW_HDR_FW_VER_MICRO(T5FW_VERSION_MICRO) | 1103 V_FW_HDR_FW_VER_BUILD(T5FW_VERSION_BUILD); 1104 if (rc < 0 || v > sc->params.fw_vers) { 1105 cxgb_printf(sc->dip, CE_NOTE, 1106 "installing firmware %d.%d.%d.%d on card.", 1107 T5FW_VERSION_MAJOR, T5FW_VERSION_MINOR, 1108 T5FW_VERSION_MICRO, T5FW_VERSION_BUILD); 1109 rc = -t4_load_fw(sc, t5fw_data, t5fw_size); 1110 if (rc != 0) { 1111 cxgb_printf(sc->dip, CE_WARN, 1112 "failed to install firmware: %d", rc); 1113 return (rc); 1114 } else { 1115 /* refresh */ 1116 (void) t4_check_fw_version(sc); 1117 } 1118 1119 } 1120 } 1121 } 1122 1123 /* Contact firmware, request master */ 1124 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state); 1125 if (rc < 0) { 1126 rc = -rc; 1127 cxgb_printf(sc->dip, CE_WARN, 1128 "failed to connect to the firmware: %d.", rc); 1129 return (rc); 1130 } 1131 1132 if (rc == sc->mbox) 1133 sc->flags |= MASTER_PF; 1134 1135 /* Reset device */ 1136 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 1137 if (rc != 0) { 1138 cxgb_printf(sc->dip, CE_WARN, 1139 "firmware reset failed: %d.", rc); 1140 if (rc != ETIMEDOUT && rc != EIO) 1141 (void) t4_fw_bye(sc, sc->mbox); 1142 return (rc); 1143 } 1144 1145 /* Partition adapter resources as specified in the config file. */ 1146 if (sc->flags & MASTER_PF) { 1147 /* Handle default vs special T4 config file */ 1148 1149 rc = partition_resources(sc); 1150 if (rc != 0) 1151 goto err; /* error message displayed already */ 1152 } 1153 1154 sc->flags |= FW_OK; 1155 return (0); 1156 err: 1157 return (rc); 1158 1159 } 1160 1161 static const struct memwin t4_memwin[] = { 1162 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1163 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1164 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 1165 }; 1166 1167 static const struct memwin t5_memwin[] = { 1168 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1169 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1170 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 1171 }; 1172 1173 #define FW_PARAM_DEV(param) \ 1174 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1175 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1176 #define FW_PARAM_PFVF(param) \ 1177 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1178 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 1179 1180 /* 1181 * Verify that the memory range specified by the memtype/offset/len pair is 1182 * valid and lies entirely within the memtype specified. The global address of 1183 * the start of the range is returned in addr. 1184 */ 1185 int 1186 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 1187 uint32_t *addr) 1188 { 1189 uint32_t em, addr_len, maddr, mlen; 1190 1191 /* Memory can only be accessed in naturally aligned 4 byte units */ 1192 if (off & 3 || len & 3 || len == 0) 1193 return (EINVAL); 1194 1195 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 1196 switch (mtype) { 1197 case MEM_EDC0: 1198 if (!(em & F_EDRAM0_ENABLE)) 1199 return (EINVAL); 1200 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 1201 maddr = G_EDRAM0_BASE(addr_len) << 20; 1202 mlen = G_EDRAM0_SIZE(addr_len) << 20; 1203 break; 1204 case MEM_EDC1: 1205 if (!(em & F_EDRAM1_ENABLE)) 1206 return (EINVAL); 1207 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 1208 maddr = G_EDRAM1_BASE(addr_len) << 20; 1209 mlen = G_EDRAM1_SIZE(addr_len) << 20; 1210 break; 1211 case MEM_MC: 1212 if (!(em & F_EXT_MEM_ENABLE)) 1213 return (EINVAL); 1214 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 1215 maddr = G_EXT_MEM_BASE(addr_len) << 20; 1216 mlen = G_EXT_MEM_SIZE(addr_len) << 20; 1217 break; 1218 case MEM_MC1: 1219 if (is_t4(sc->params.chip) || !(em & F_EXT_MEM1_ENABLE)) 1220 return (EINVAL); 1221 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 1222 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 1223 mlen = G_EXT_MEM1_SIZE(addr_len) << 20; 1224 break; 1225 default: 1226 return (EINVAL); 1227 } 1228 1229 if (mlen > 0 && off < mlen && off + len <= mlen) { 1230 *addr = maddr + off; /* global address */ 1231 return (0); 1232 } 1233 1234 return (EFAULT); 1235 } 1236 1237 void 1238 memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture) 1239 { 1240 const struct memwin *mw; 1241 1242 if (is_t4(sc->params.chip)) { 1243 mw = &t4_memwin[win]; 1244 } else { 1245 mw = &t5_memwin[win]; 1246 } 1247 1248 if (base != NULL) 1249 *base = mw->base; 1250 if (aperture != NULL) 1251 *aperture = mw->aperture; 1252 } 1253 1254 /* 1255 * Upload configuration file to card's memory. 1256 */ 1257 static int 1258 upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma) 1259 { 1260 int rc = 0, cflen; 1261 u_int i, n; 1262 uint32_t param, val, addr, mtype, maddr; 1263 uint32_t off, mw_base, mw_aperture; 1264 const uint32_t *cfdata; 1265 1266 /* Figure out where the firmware wants us to upload it. */ 1267 param = FW_PARAM_DEV(CF); 1268 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1269 if (rc != 0) { 1270 /* Firmwares without config file support will fail this way */ 1271 cxgb_printf(sc->dip, CE_WARN, 1272 "failed to query config file location: %d.\n", rc); 1273 return (rc); 1274 } 1275 *mt = mtype = G_FW_PARAMS_PARAM_Y(val); 1276 *ma = maddr = G_FW_PARAMS_PARAM_Z(val) << 16; 1277 1278 if (is_t4(sc->params.chip)) { 1279 cflen = t4cfg_size & ~3; 1280 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 1281 cfdata = (const uint32_t *)t4cfg_data; 1282 } else { 1283 cflen = t5cfg_size & ~3; 1284 /* LINTED: E_BAD_PTR_CAST_ALIGN */ 1285 cfdata = (const uint32_t *)t5cfg_data; 1286 } 1287 1288 if (cflen > FLASH_CFG_MAX_SIZE) { 1289 cxgb_printf(sc->dip, CE_WARN, 1290 "config file too long (%d, max allowed is %d). ", 1291 cflen, FLASH_CFG_MAX_SIZE); 1292 return (EFBIG); 1293 } 1294 1295 rc = validate_mt_off_len(sc, mtype, maddr, cflen, &addr); 1296 if (rc != 0) { 1297 1298 cxgb_printf(sc->dip, CE_WARN, 1299 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 1300 "Will try to use the config on the card, if any.\n", 1301 __func__, mtype, maddr, cflen, rc); 1302 return (EFAULT); 1303 } 1304 1305 memwin_info(sc, 2, &mw_base, &mw_aperture); 1306 while (cflen) { 1307 off = position_memwin(sc, 2, addr); 1308 n = min(cflen, mw_aperture - off); 1309 for (i = 0; i < n; i += 4) 1310 t4_write_reg(sc, mw_base + off + i, *cfdata++); 1311 cflen -= n; 1312 addr += n; 1313 } 1314 1315 return (rc); 1316 } 1317 1318 /* 1319 * Partition chip resources for use between various PFs, VFs, etc. This is done 1320 * by uploading the firmware configuration file to the adapter and instructing 1321 * the firmware to process it. 1322 */ 1323 static int 1324 partition_resources(struct adapter *sc) 1325 { 1326 int rc; 1327 struct fw_caps_config_cmd caps; 1328 uint32_t mtype, maddr, finicsum, cfcsum; 1329 1330 rc = upload_config_file(sc, &mtype, &maddr); 1331 if (rc != 0) { 1332 mtype = FW_MEMTYPE_CF_FLASH; 1333 maddr = t4_flash_cfg_addr(sc); 1334 } 1335 1336 bzero(&caps, sizeof (caps)); 1337 caps.op_to_write = BE_32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1338 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1339 caps.cfvalid_to_len16 = BE_32(F_FW_CAPS_CONFIG_CMD_CFVALID | 1340 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 1341 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | FW_LEN16(caps)); 1342 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), &caps); 1343 if (rc != 0) { 1344 cxgb_printf(sc->dip, CE_WARN, 1345 "failed to pre-process config file: %d.\n", rc); 1346 return (rc); 1347 } 1348 1349 finicsum = ntohl(caps.finicsum); 1350 cfcsum = ntohl(caps.cfcsum); 1351 if (finicsum != cfcsum) { 1352 cxgb_printf(sc->dip, CE_WARN, 1353 "WARNING: config file checksum mismatch: %08x %08x\n", 1354 finicsum, cfcsum); 1355 } 1356 sc->cfcsum = cfcsum; 1357 1358 /* TODO: Need to configure this correctly */ 1359 caps.toecaps = htons(FW_CAPS_CONFIG_TOE); 1360 caps.iscsicaps = 0; 1361 caps.rdmacaps = 0; 1362 caps.fcoecaps = 0; 1363 /* TODO: Disable VNIC cap for now */ 1364 caps.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); 1365 1366 caps.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1367 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1368 caps.cfvalid_to_len16 = htonl(FW_LEN16(caps)); 1369 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), NULL); 1370 if (rc != 0) { 1371 cxgb_printf(sc->dip, CE_WARN, 1372 "failed to process config file: %d.\n", rc); 1373 return (rc); 1374 } 1375 1376 return (0); 1377 } 1378 1379 /* 1380 * Retrieve parameters that are needed (or nice to have) prior to calling 1381 * t4_sge_init and t4_fw_initialize. 1382 */ 1383 static int 1384 get_params__pre_init(struct adapter *sc) 1385 { 1386 int rc; 1387 uint32_t param[2], val[2]; 1388 struct fw_devlog_cmd cmd; 1389 struct devlog_params *dlog = &sc->params.devlog; 1390 1391 param[0] = FW_PARAM_DEV(PORTVEC); 1392 param[1] = FW_PARAM_DEV(CCLK); 1393 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 1394 if (rc != 0) { 1395 cxgb_printf(sc->dip, CE_WARN, 1396 "failed to query parameters (pre_init): %d.\n", rc); 1397 return (rc); 1398 } 1399 1400 sc->params.portvec = val[0]; 1401 sc->params.nports = 0; 1402 while (val[0]) { 1403 sc->params.nports++; 1404 val[0] &= val[0] - 1; 1405 } 1406 1407 sc->params.vpd.cclk = val[1]; 1408 1409 /* Read device log parameters. */ 1410 bzero(&cmd, sizeof (cmd)); 1411 cmd.op_to_write = htonl(V_FW_CMD_OP(FW_DEVLOG_CMD) | 1412 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1413 cmd.retval_len16 = htonl(FW_LEN16(cmd)); 1414 rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof (cmd), &cmd); 1415 if (rc != 0) { 1416 cxgb_printf(sc->dip, CE_WARN, 1417 "failed to get devlog parameters: %d.\n", rc); 1418 bzero(dlog, sizeof (*dlog)); 1419 rc = 0; /* devlog isn't critical for device operation */ 1420 } else { 1421 val[0] = ntohl(cmd.memtype_devlog_memaddr16_devlog); 1422 dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]); 1423 dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4; 1424 dlog->size = ntohl(cmd.memsize_devlog); 1425 } 1426 1427 return (rc); 1428 } 1429 1430 /* 1431 * Retrieve various parameters that are of interest to the driver. The device 1432 * has been initialized by the firmware at this point. 1433 */ 1434 static int 1435 get_params__post_init(struct adapter *sc) 1436 { 1437 int rc; 1438 uint32_t param[7], val[7]; 1439 struct fw_caps_config_cmd caps; 1440 1441 param[0] = FW_PARAM_PFVF(IQFLINT_START); 1442 param[1] = FW_PARAM_PFVF(EQ_START); 1443 param[2] = FW_PARAM_PFVF(FILTER_START); 1444 param[3] = FW_PARAM_PFVF(FILTER_END); 1445 param[4] = FW_PARAM_PFVF(L2T_START); 1446 param[5] = FW_PARAM_PFVF(L2T_END); 1447 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 1448 if (rc != 0) { 1449 cxgb_printf(sc->dip, CE_WARN, 1450 "failed to query parameters (post_init): %d.\n", rc); 1451 return (rc); 1452 } 1453 1454 /* LINTED: E_ASSIGN_NARROW_CONV */ 1455 sc->sge.iq_start = val[0]; 1456 sc->sge.eq_start = val[1]; 1457 sc->tids.ftid_base = val[2]; 1458 sc->tids.nftids = val[3] - val[2] + 1; 1459 sc->vres.l2t.start = val[4]; 1460 sc->vres.l2t.size = val[5] - val[4] + 1; 1461 1462 /* get capabilites */ 1463 bzero(&caps, sizeof (caps)); 1464 caps.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1465 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1466 caps.cfvalid_to_len16 = htonl(FW_LEN16(caps)); 1467 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof (caps), &caps); 1468 if (rc != 0) { 1469 cxgb_printf(sc->dip, CE_WARN, 1470 "failed to get card capabilities: %d.\n", rc); 1471 return (rc); 1472 } 1473 1474 if (caps.toecaps != 0) { 1475 /* query offload-related parameters */ 1476 param[0] = FW_PARAM_DEV(NTID); 1477 param[1] = FW_PARAM_PFVF(SERVER_START); 1478 param[2] = FW_PARAM_PFVF(SERVER_END); 1479 param[3] = FW_PARAM_PFVF(TDDP_START); 1480 param[4] = FW_PARAM_PFVF(TDDP_END); 1481 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 1482 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 1483 if (rc != 0) { 1484 cxgb_printf(sc->dip, CE_WARN, 1485 "failed to query TOE parameters: %d.\n", rc); 1486 return (rc); 1487 } 1488 sc->tids.ntids = val[0]; 1489 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 1490 sc->tids.stid_base = val[1]; 1491 sc->tids.nstids = val[2] - val[1] + 1; 1492 sc->vres.ddp.start = val[3]; 1493 sc->vres.ddp.size = val[4] - val[3] + 1; 1494 sc->params.ofldq_wr_cred = val[5]; 1495 sc->params.offload = 1; 1496 } 1497 1498 /* These are finalized by FW initialization, load their values now */ 1499 val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 1500 sc->params.tp.tre = G_TIMERRESOLUTION(val[0]); 1501 sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(val[0]); 1502 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 1503 1504 return (rc); 1505 } 1506 1507 static int 1508 set_params__post_init(struct adapter *sc) 1509 { 1510 uint32_t param, val; 1511 1512 /* ask for encapsulated CPLs */ 1513 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1514 val = 1; 1515 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1516 1517 return (0); 1518 } 1519 1520 /* TODO: verify */ 1521 static void 1522 setup_memwin(struct adapter *sc) 1523 { 1524 pci_regspec_t *data; 1525 int rc; 1526 uint_t n; 1527 uintptr_t bar0; 1528 uintptr_t mem_win0_base, mem_win1_base, mem_win2_base; 1529 uintptr_t mem_win2_aperture; 1530 1531 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, 1532 DDI_PROP_DONTPASS, "assigned-addresses", (int **)&data, &n); 1533 if (rc != DDI_SUCCESS) { 1534 cxgb_printf(sc->dip, CE_WARN, 1535 "failed to lookup \"assigned-addresses\" property: %d", rc); 1536 return; 1537 } 1538 n /= sizeof (*data); 1539 1540 bar0 = ((uint64_t)data[0].pci_phys_mid << 32) | data[0].pci_phys_low; 1541 ddi_prop_free(data); 1542 1543 if (is_t4(sc->params.chip)) { 1544 mem_win0_base = bar0 + MEMWIN0_BASE; 1545 mem_win1_base = bar0 + MEMWIN1_BASE; 1546 mem_win2_base = bar0 + MEMWIN2_BASE_T4; 1547 mem_win2_aperture = MEMWIN2_APERTURE_T4; 1548 } else { 1549 /* For T5, only relative offset inside the PCIe BAR is passed */ 1550 mem_win0_base = MEMWIN0_BASE; 1551 mem_win1_base = MEMWIN1_BASE; 1552 mem_win2_base = MEMWIN2_BASE_T5; 1553 mem_win2_aperture = MEMWIN2_APERTURE_T5; 1554 } 1555 1556 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), 1557 mem_win0_base | V_BIR(0) | 1558 V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); 1559 1560 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), 1561 mem_win1_base | V_BIR(0) | 1562 V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); 1563 1564 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), 1565 mem_win2_base | V_BIR(0) | 1566 V_WINDOW(ilog2(mem_win2_aperture) - 10)); 1567 1568 /* flush */ 1569 (void)t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 1570 } 1571 1572 /* 1573 * Positions the memory window such that it can be used to access the specified 1574 * address in the chip's address space. The return value is the offset of addr 1575 * from the start of the window. 1576 */ 1577 uint32_t 1578 position_memwin(struct adapter *sc, int n, uint32_t addr) 1579 { 1580 uint32_t start, pf; 1581 uint32_t reg; 1582 1583 if (addr & 3) { 1584 cxgb_printf(sc->dip, CE_WARN, 1585 "addr (0x%x) is not at a 4B boundary.\n", addr); 1586 return (EFAULT); 1587 } 1588 1589 if (is_t4(sc->params.chip)) { 1590 pf = 0; 1591 start = addr & ~0xf; /* start must be 16B aligned */ 1592 } else { 1593 pf = V_PFNUM(sc->pf); 1594 start = addr & ~0x7f; /* start must be 128B aligned */ 1595 } 1596 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n); 1597 1598 t4_write_reg(sc, reg, start | pf); 1599 (void) t4_read_reg(sc, reg); 1600 1601 return (addr - start); 1602 } 1603 1604 1605 /* 1606 * Reads the named property and fills up the "data" array (which has at least 1607 * "count" elements). We first try and lookup the property for our dev_t and 1608 * then retry with DDI_DEV_T_ANY if it's not found. 1609 * 1610 * Returns non-zero if the property was found and "data" has been updated. 1611 */ 1612 static int 1613 prop_lookup_int_array(struct adapter *sc, char *name, int *data, uint_t count) 1614 { 1615 dev_info_t *dip = sc->dip; 1616 dev_t dev = sc->dev; 1617 int rc, *d; 1618 uint_t i, n; 1619 1620 rc = ddi_prop_lookup_int_array(dev, dip, DDI_PROP_DONTPASS, 1621 name, &d, &n); 1622 if (rc == DDI_PROP_SUCCESS) 1623 goto found; 1624 1625 if (rc != DDI_PROP_NOT_FOUND) { 1626 cxgb_printf(dip, CE_WARN, 1627 "failed to lookup property %s for minor %d: %d.", 1628 name, getminor(dev), rc); 1629 return (0); 1630 } 1631 1632 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1633 name, &d, &n); 1634 if (rc == DDI_PROP_SUCCESS) 1635 goto found; 1636 1637 if (rc != DDI_PROP_NOT_FOUND) { 1638 cxgb_printf(dip, CE_WARN, 1639 "failed to lookup property %s: %d.", name, rc); 1640 return (0); 1641 } 1642 1643 return (0); 1644 1645 found: 1646 if (n > count) { 1647 cxgb_printf(dip, CE_NOTE, 1648 "property %s has too many elements (%d), ignoring extras", 1649 name, n); 1650 } 1651 1652 for (i = 0; i < n && i < count; i++) 1653 data[i] = d[i]; 1654 ddi_prop_free(d); 1655 1656 return (1); 1657 } 1658 1659 static int 1660 prop_lookup_int(struct adapter *sc, char *name, int defval) 1661 { 1662 int rc; 1663 1664 rc = ddi_prop_get_int(sc->dev, sc->dip, DDI_PROP_DONTPASS, name, -1); 1665 if (rc != -1) 1666 return (rc); 1667 1668 return (ddi_prop_get_int(DDI_DEV_T_ANY, sc->dip, DDI_PROP_DONTPASS, 1669 name, defval)); 1670 } 1671 1672 static int 1673 init_driver_props(struct adapter *sc, struct driver_properties *p) 1674 { 1675 dev_t dev = sc->dev; 1676 dev_info_t *dip = sc->dip; 1677 int i, *data; 1678 uint_t tmr[SGE_NTIMERS] = {5, 10, 20, 50, 100, 200}; 1679 uint_t cnt[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 1680 1681 /* 1682 * Holdoff timer 1683 */ 1684 data = &p->timer_val[0]; 1685 for (i = 0; i < SGE_NTIMERS; i++) 1686 data[i] = tmr[i]; 1687 (void) prop_lookup_int_array(sc, "holdoff-timer-values", data, 1688 SGE_NTIMERS); 1689 for (i = 0; i < SGE_NTIMERS; i++) { 1690 int limit = 200U; 1691 if (data[i] > limit) { 1692 cxgb_printf(dip, CE_WARN, 1693 "holdoff timer %d is too high (%d), lowered to %d.", 1694 i, data[i], limit); 1695 data[i] = limit; 1696 } 1697 } 1698 (void) ddi_prop_update_int_array(dev, dip, "holdoff-timer-values", 1699 data, SGE_NTIMERS); 1700 1701 /* 1702 * Holdoff packet counter 1703 */ 1704 data = &p->counter_val[0]; 1705 for (i = 0; i < SGE_NCOUNTERS; i++) 1706 data[i] = cnt[i]; 1707 (void) prop_lookup_int_array(sc, "holdoff-pkt-counter-values", data, 1708 SGE_NCOUNTERS); 1709 for (i = 0; i < SGE_NCOUNTERS; i++) { 1710 int limit = M_THRESHOLD_0; 1711 if (data[i] > limit) { 1712 cxgb_printf(dip, CE_WARN, 1713 "holdoff pkt-counter %d is too high (%d), " 1714 "lowered to %d.", i, data[i], limit); 1715 data[i] = limit; 1716 } 1717 } 1718 (void) ddi_prop_update_int_array(dev, dip, "holdoff-pkt-counter-values", 1719 data, SGE_NCOUNTERS); 1720 1721 /* 1722 * Maximum # of tx and rx queues to use for each 10G and 1G port. 1723 */ 1724 p->max_ntxq_10g = prop_lookup_int(sc, "max-ntxq-10G-port", 8); 1725 (void) ddi_prop_update_int(dev, dip, "max-ntxq-10G-port", 1726 p->max_ntxq_10g); 1727 1728 p->max_nrxq_10g = prop_lookup_int(sc, "max-nrxq-10G-port", 8); 1729 (void) ddi_prop_update_int(dev, dip, "max-nrxq-10G-port", 1730 p->max_nrxq_10g); 1731 1732 p->max_ntxq_1g = prop_lookup_int(sc, "max-ntxq-1G-port", 2); 1733 (void) ddi_prop_update_int(dev, dip, "max-ntxq-1G-port", 1734 p->max_ntxq_1g); 1735 1736 p->max_nrxq_1g = prop_lookup_int(sc, "max-nrxq-1G-port", 2); 1737 (void) ddi_prop_update_int(dev, dip, "max-nrxq-1G-port", 1738 p->max_nrxq_1g); 1739 1740 #ifndef TCP_OFFLOAD_DISABLE 1741 p->max_nofldtxq_10g = prop_lookup_int(sc, "max-nofldtxq-10G-port", 8); 1742 (void) ddi_prop_update_int(dev, dip, "max-ntxq-10G-port", 1743 p->max_nofldtxq_10g); 1744 1745 p->max_nofldrxq_10g = prop_lookup_int(sc, "max-nofldrxq-10G-port", 2); 1746 (void) ddi_prop_update_int(dev, dip, "max-nrxq-10G-port", 1747 p->max_nofldrxq_10g); 1748 1749 p->max_nofldtxq_1g = prop_lookup_int(sc, "max-nofldtxq-1G-port", 2); 1750 (void) ddi_prop_update_int(dev, dip, "max-ntxq-1G-port", 1751 p->max_nofldtxq_1g); 1752 1753 p->max_nofldrxq_1g = prop_lookup_int(sc, "max-nofldrxq-1G-port", 1); 1754 (void) ddi_prop_update_int(dev, dip, "max-nrxq-1G-port", 1755 p->max_nofldrxq_1g); 1756 #endif 1757 1758 /* 1759 * Holdoff parameters for 10G and 1G ports. 1760 */ 1761 p->tmr_idx_10g = prop_lookup_int(sc, "holdoff-timer-idx-10G", 0); 1762 (void) ddi_prop_update_int(dev, dip, "holdoff-timer-idx-10G", 1763 p->tmr_idx_10g); 1764 1765 p->pktc_idx_10g = prop_lookup_int(sc, "holdoff-pktc-idx-10G", 2); 1766 (void) ddi_prop_update_int(dev, dip, "holdoff-pktc-idx-10G", 1767 p->pktc_idx_10g); 1768 1769 p->tmr_idx_1g = prop_lookup_int(sc, "holdoff-timer-idx-1G", 0); 1770 (void) ddi_prop_update_int(dev, dip, "holdoff-timer-idx-1G", 1771 p->tmr_idx_1g); 1772 1773 p->pktc_idx_1g = prop_lookup_int(sc, "holdoff-pktc-idx-1G", 2); 1774 (void) ddi_prop_update_int(dev, dip, "holdoff-pktc-idx-1G", 1775 p->pktc_idx_1g); 1776 1777 /* 1778 * Size (number of entries) of each tx and rx queue. 1779 */ 1780 i = prop_lookup_int(sc, "qsize-txq", TX_EQ_QSIZE); 1781 p->qsize_txq = max(i, 128); 1782 if (p->qsize_txq != i) { 1783 cxgb_printf(dip, CE_WARN, 1784 "using %d instead of %d as the tx queue size", 1785 p->qsize_txq, i); 1786 } 1787 (void) ddi_prop_update_int(dev, dip, "qsize-txq", p->qsize_txq); 1788 1789 i = prop_lookup_int(sc, "qsize-rxq", RX_IQ_QSIZE); 1790 p->qsize_rxq = max(i, 128); 1791 while (p->qsize_rxq & 7) 1792 p->qsize_rxq--; 1793 if (p->qsize_rxq != i) { 1794 cxgb_printf(dip, CE_WARN, 1795 "using %d instead of %d as the rx queue size", 1796 p->qsize_rxq, i); 1797 } 1798 (void) ddi_prop_update_int(dev, dip, "qsize-rxq", p->qsize_rxq); 1799 1800 /* 1801 * Interrupt types allowed. 1802 * Bits 0, 1, 2 = INTx, MSI, MSI-X respectively. See sys/ddi_intr.h 1803 */ 1804 p->intr_types = prop_lookup_int(sc, "interrupt-types", 1805 DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_FIXED); 1806 (void) ddi_prop_update_int(dev, dip, "interrupt-types", p->intr_types); 1807 1808 /* 1809 * Forwarded interrupt queues. Create this property to force the driver 1810 * to use forwarded interrupt queues. 1811 */ 1812 if (ddi_prop_exists(dev, dip, DDI_PROP_DONTPASS, 1813 "interrupt-forwarding") != 0 || 1814 ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1815 "interrupt-forwarding") != 0) { 1816 UNIMPLEMENTED(); 1817 (void) ddi_prop_create(dev, dip, DDI_PROP_CANSLEEP, 1818 "interrupt-forwarding", NULL, 0); 1819 } 1820 1821 /* 1822 * Write combining 1823 * 0 to disable, 1 to enable 1824 */ 1825 p->wc = prop_lookup_int(sc, "write-combine", 1); 1826 cxgb_printf(dip, CE_WARN, "write-combine: using of %d", p->wc); 1827 if (p->wc != 0 && p->wc != 1) { 1828 cxgb_printf(dip, CE_WARN, 1829 "write-combine: using 1 instead of %d", p->wc); 1830 p->wc = 1; 1831 } 1832 (void) ddi_prop_update_int(dev, dip, "write-combine", p->wc); 1833 1834 return (0); 1835 } 1836 1837 static int 1838 remove_extra_props(struct adapter *sc, int n10g, int n1g) 1839 { 1840 if (n10g == 0) { 1841 (void) ddi_prop_remove(sc->dev, sc->dip, "max-ntxq-10G-port"); 1842 (void) ddi_prop_remove(sc->dev, sc->dip, "max-nrxq-10G-port"); 1843 (void) ddi_prop_remove(sc->dev, sc->dip, 1844 "holdoff-timer-idx-10G"); 1845 (void) ddi_prop_remove(sc->dev, sc->dip, 1846 "holdoff-pktc-idx-10G"); 1847 } 1848 1849 if (n1g == 0) { 1850 (void) ddi_prop_remove(sc->dev, sc->dip, "max-ntxq-1G-port"); 1851 (void) ddi_prop_remove(sc->dev, sc->dip, "max-nrxq-1G-port"); 1852 (void) ddi_prop_remove(sc->dev, sc->dip, 1853 "holdoff-timer-idx-1G"); 1854 (void) ddi_prop_remove(sc->dev, sc->dip, "holdoff-pktc-idx-1G"); 1855 } 1856 1857 return (0); 1858 } 1859 1860 static int 1861 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 1862 struct intrs_and_queues *iaq) 1863 { 1864 struct driver_properties *p = &sc->props; 1865 int rc, itype, itypes, navail, nc, nrxq10g, nrxq1g, n; 1866 int nofldrxq10g = 0, nofldrxq1g = 0; 1867 1868 bzero(iaq, sizeof (*iaq)); 1869 nc = ncpus; /* our snapshot of the number of CPUs */ 1870 iaq->ntxq10g = min(nc, p->max_ntxq_10g); 1871 iaq->ntxq1g = min(nc, p->max_ntxq_1g); 1872 iaq->nrxq10g = nrxq10g = min(nc, p->max_nrxq_10g); 1873 iaq->nrxq1g = nrxq1g = min(nc, p->max_nrxq_1g); 1874 #ifndef TCP_OFFLOAD_DISABLE 1875 iaq->nofldtxq10g = min(nc, p->max_nofldtxq_10g); 1876 iaq->nofldtxq1g = min(nc, p->max_nofldtxq_1g); 1877 iaq->nofldrxq10g = nofldrxq10g = min(nc, p->max_nofldrxq_10g); 1878 iaq->nofldrxq1g = nofldrxq1g = min(nc, p->max_nofldrxq_1g); 1879 #endif 1880 1881 rc = ddi_intr_get_supported_types(sc->dip, &itypes); 1882 if (rc != DDI_SUCCESS) { 1883 cxgb_printf(sc->dip, CE_WARN, 1884 "failed to determine supported interrupt types: %d", rc); 1885 return (rc); 1886 } 1887 1888 for (itype = DDI_INTR_TYPE_MSIX; itype; itype >>= 1) { 1889 ASSERT(itype == DDI_INTR_TYPE_MSIX || 1890 itype == DDI_INTR_TYPE_MSI || 1891 itype == DDI_INTR_TYPE_FIXED); 1892 1893 if ((itype & itypes & p->intr_types) == 0) 1894 continue; /* not supported or not allowed */ 1895 1896 navail = 0; 1897 rc = ddi_intr_get_navail(sc->dip, itype, &navail); 1898 if (rc != DDI_SUCCESS || navail == 0) { 1899 cxgb_printf(sc->dip, CE_WARN, 1900 "failed to get # of interrupts for type %d: %d", 1901 itype, rc); 1902 continue; /* carry on */ 1903 } 1904 1905 iaq->intr_type = itype; 1906 1907 #if MAC_VERSION == 1 1908 iaq->ntxq10g = 1; 1909 iaq->ntxq1g = 1; 1910 #endif 1911 1912 if (navail == 0) 1913 continue; 1914 1915 /* 1916 * Best option: an interrupt vector for errors, one for the 1917 * firmware event queue, and one each for each rxq (NIC as well 1918 * as offload). 1919 */ 1920 iaq->nirq = T4_EXTRA_INTR; 1921 iaq->nirq += n10g * (nrxq10g + nofldrxq10g); 1922 iaq->nirq += n1g * (nrxq1g + nofldrxq1g); 1923 1924 if (iaq->nirq <= navail && 1925 (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq))) { 1926 iaq->intr_fwd = 0; 1927 goto allocate; 1928 } 1929 1930 /* 1931 * Second best option: an interrupt vector for errors, one for 1932 * the firmware event queue, and one each for either NIC or 1933 * offload rxq's. 1934 */ 1935 iaq->nirq = T4_EXTRA_INTR; 1936 iaq->nirq += n10g * max(nrxq10g, nofldrxq10g); 1937 iaq->nirq += n1g * max(nrxq1g, nofldrxq1g); 1938 if (iaq->nirq <= navail && 1939 (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq))) { 1940 iaq->intr_fwd = 1; 1941 goto allocate; 1942 } 1943 1944 /* 1945 * Next best option: an interrupt vector for errors, one for the 1946 * firmware event queue, and at least one per port. At this 1947 * point we know we'll have to downsize nrxq or nofldrxq to fit 1948 * what's available to us. 1949 */ 1950 iaq->nirq = T4_EXTRA_INTR; 1951 iaq->nirq += n10g + n1g; 1952 if (iaq->nirq <= navail) { 1953 int leftover = navail - iaq->nirq; 1954 1955 if (n10g > 0) { 1956 int target = max(nrxq10g, nofldrxq10g); 1957 1958 n = 1; 1959 while (n < target && leftover >= n10g) { 1960 leftover -= n10g; 1961 iaq->nirq += n10g; 1962 n++; 1963 } 1964 iaq->nrxq10g = min(n, nrxq10g); 1965 #ifndef TCP_OFFLOAD_DISABLE 1966 iaq->nofldrxq10g = min(n, nofldrxq10g); 1967 #endif 1968 } 1969 1970 if (n1g > 0) { 1971 int target = max(nrxq1g, nofldrxq1g); 1972 1973 n = 1; 1974 while (n < target && leftover >= n1g) { 1975 leftover -= n1g; 1976 iaq->nirq += n1g; 1977 n++; 1978 } 1979 iaq->nrxq1g = min(n, nrxq1g); 1980 #ifndef TCP_OFFLOAD_DISABLE 1981 iaq->nofldrxq1g = min(n, nofldrxq1g); 1982 #endif 1983 } 1984 1985 if (itype != DDI_INTR_TYPE_MSI || ISP2(iaq->nirq)) { 1986 iaq->intr_fwd = 1; 1987 goto allocate; 1988 } 1989 } 1990 1991 /* 1992 * Least desirable option: one interrupt vector for everything. 1993 */ 1994 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 1995 #ifndef TCP_OFFLOAD_DISABLE 1996 iaq->nofldrxq10g = iaq->nofldrxq1g = 1; 1997 #endif 1998 iaq->intr_fwd = 1; 1999 2000 allocate: 2001 return (0); 2002 } 2003 2004 cxgb_printf(sc->dip, CE_WARN, 2005 "failed to find a usable interrupt type. supported=%d, allowed=%d", 2006 itypes, p->intr_types); 2007 return (DDI_FAILURE); 2008 } 2009 2010 static int 2011 add_child_node(struct adapter *sc, int idx) 2012 { 2013 int rc; 2014 struct port_info *pi; 2015 2016 if (idx < 0 || idx >= sc->params.nports) 2017 return (EINVAL); 2018 2019 pi = sc->port[idx]; 2020 if (pi == NULL) 2021 return (ENODEV); /* t4_port_init failed earlier */ 2022 2023 PORT_LOCK(pi); 2024 if (pi->dip != NULL) { 2025 rc = 0; /* EEXIST really, but then bus_config fails */ 2026 goto done; 2027 } 2028 2029 rc = ndi_devi_alloc(sc->dip, T4_PORT_NAME, DEVI_SID_NODEID, &pi->dip); 2030 if (rc != DDI_SUCCESS || pi->dip == NULL) { 2031 rc = ENOMEM; 2032 goto done; 2033 } 2034 2035 (void) ddi_set_parent_data(pi->dip, pi); 2036 (void) ndi_devi_bind_driver(pi->dip, 0); 2037 rc = 0; 2038 done: 2039 PORT_UNLOCK(pi); 2040 return (rc); 2041 } 2042 2043 static int 2044 remove_child_node(struct adapter *sc, int idx) 2045 { 2046 int rc; 2047 struct port_info *pi; 2048 2049 if (idx < 0 || idx >= sc->params.nports) 2050 return (EINVAL); 2051 2052 pi = sc->port[idx]; 2053 if (pi == NULL) 2054 return (ENODEV); 2055 2056 PORT_LOCK(pi); 2057 if (pi->dip == NULL) { 2058 rc = ENODEV; 2059 goto done; 2060 } 2061 2062 rc = ndi_devi_free(pi->dip); 2063 if (rc == 0) 2064 pi->dip = NULL; 2065 done: 2066 PORT_UNLOCK(pi); 2067 return (rc); 2068 } 2069 2070 #define KS_UINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_ULONG) 2071 #define KS_CINIT(x) kstat_named_init(&kstatp->x, #x, KSTAT_DATA_CHAR) 2072 #define KS_U_SET(x, y) kstatp->x.value.ul = (y) 2073 #define KS_C_SET(x, ...) \ 2074 (void) snprintf(kstatp->x.value.c, 16, __VA_ARGS__) 2075 2076 /* 2077 * t4nex:X:config 2078 */ 2079 struct t4_kstats { 2080 kstat_named_t chip_ver; 2081 kstat_named_t fw_vers; 2082 kstat_named_t tp_vers; 2083 kstat_named_t driver_version; 2084 kstat_named_t serial_number; 2085 kstat_named_t ec_level; 2086 kstat_named_t id; 2087 kstat_named_t bus_type; 2088 kstat_named_t bus_width; 2089 kstat_named_t bus_speed; 2090 kstat_named_t core_clock; 2091 kstat_named_t port_cnt; 2092 kstat_named_t port_type; 2093 kstat_named_t pci_vendor_id; 2094 kstat_named_t pci_device_id; 2095 }; 2096 static kstat_t * 2097 setup_kstats(struct adapter *sc) 2098 { 2099 kstat_t *ksp; 2100 struct t4_kstats *kstatp; 2101 int ndata; 2102 struct pci_params *p = &sc->params.pci; 2103 struct vpd_params *v = &sc->params.vpd; 2104 uint16_t pci_vendor, pci_device; 2105 2106 ndata = sizeof (struct t4_kstats) / sizeof (kstat_named_t); 2107 2108 ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "config", 2109 "nexus", KSTAT_TYPE_NAMED, ndata, 0); 2110 if (ksp == NULL) { 2111 cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); 2112 return (NULL); 2113 } 2114 2115 kstatp = (struct t4_kstats *)ksp->ks_data; 2116 2117 KS_UINIT(chip_ver); 2118 KS_CINIT(fw_vers); 2119 KS_CINIT(tp_vers); 2120 KS_CINIT(driver_version); 2121 KS_CINIT(serial_number); 2122 KS_CINIT(ec_level); 2123 KS_CINIT(id); 2124 KS_CINIT(bus_type); 2125 KS_CINIT(bus_width); 2126 KS_CINIT(bus_speed); 2127 KS_UINIT(core_clock); 2128 KS_UINIT(port_cnt); 2129 KS_CINIT(port_type); 2130 KS_CINIT(pci_vendor_id); 2131 KS_CINIT(pci_device_id); 2132 2133 KS_U_SET(chip_ver, sc->params.rev); 2134 KS_C_SET(fw_vers, "%d.%d.%d.%d", 2135 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 2136 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 2137 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 2138 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 2139 KS_C_SET(tp_vers, "%d.%d.%d.%d", 2140 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 2141 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 2142 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 2143 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 2144 KS_C_SET(driver_version, DRV_VERSION); 2145 KS_C_SET(serial_number, "%s", v->sn); 2146 KS_C_SET(ec_level, "%s", v->ec); 2147 KS_C_SET(id, "%s", v->id); 2148 KS_C_SET(bus_type, "pci-express"); 2149 KS_C_SET(bus_width, "x%d lanes", p->width); 2150 KS_C_SET(bus_speed, "%d", p->speed); 2151 KS_U_SET(core_clock, v->cclk); 2152 KS_U_SET(port_cnt, sc->params.nports); 2153 2154 t4_os_pci_read_cfg2(sc, PCI_CONF_VENID, &pci_vendor); 2155 KS_C_SET(pci_vendor_id, "0x%x", pci_vendor); 2156 2157 t4_os_pci_read_cfg2(sc, PCI_CONF_DEVID, &pci_device); 2158 KS_C_SET(pci_device_id, "0x%x", pci_device); 2159 2160 #define PSTR(pi) (pi ? (is_40G_port(pi) ? "40G" : \ 2161 (is_10G_port(pi) ? "10G" : "1G")) : "-") 2162 KS_C_SET(port_type, "%s/%s/%s/%s", PSTR(sc->port[0]), PSTR(sc->port[1]), 2163 PSTR(sc->port[2]), PSTR(sc->port[3])); 2164 #undef PSTR 2165 2166 /* Do NOT set ksp->ks_update. These kstats do not change. */ 2167 2168 /* Install the kstat */ 2169 ksp->ks_private = (void *)sc; 2170 kstat_install(ksp); 2171 2172 return (ksp); 2173 } 2174 2175 /* 2176 * t4nex:X:stat 2177 */ 2178 struct t4_wc_kstats { 2179 kstat_named_t write_coal_success; 2180 kstat_named_t write_coal_failure; 2181 }; 2182 static kstat_t * 2183 setup_wc_kstats(struct adapter *sc) 2184 { 2185 kstat_t *ksp; 2186 struct t4_wc_kstats *kstatp; 2187 int ndata; 2188 2189 ndata = sizeof(struct t4_wc_kstats) / sizeof(kstat_named_t); 2190 ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "stats", 2191 "nexus", KSTAT_TYPE_NAMED, ndata, 0); 2192 if (ksp == NULL) { 2193 cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); 2194 return (NULL); 2195 } 2196 2197 kstatp = (struct t4_wc_kstats *)ksp->ks_data; 2198 2199 KS_UINIT(write_coal_success); 2200 KS_UINIT(write_coal_failure); 2201 2202 ksp->ks_update = update_wc_kstats; 2203 /* Install the kstat */ 2204 ksp->ks_private = (void *)sc; 2205 kstat_install(ksp); 2206 2207 return (ksp); 2208 } 2209 2210 static int 2211 update_wc_kstats(kstat_t *ksp, int rw) 2212 { 2213 struct t4_wc_kstats *kstatp = (struct t4_wc_kstats *)ksp->ks_data; 2214 struct adapter *sc = ksp->ks_private; 2215 uint32_t wc_total, wc_success, wc_failure; 2216 2217 if (rw == KSTAT_WRITE) 2218 return (0); 2219 2220 if (is_t5(sc->params.chip)) { 2221 wc_total = t4_read_reg(sc, A_SGE_STAT_TOTAL); 2222 wc_failure = t4_read_reg(sc, A_SGE_STAT_MATCH); 2223 wc_success = wc_total - wc_failure; 2224 } else { 2225 wc_success = 0; 2226 wc_failure = 0; 2227 } 2228 2229 KS_U_SET(write_coal_success, wc_success); 2230 KS_U_SET(write_coal_failure, wc_failure); 2231 2232 return (0); 2233 } 2234 2235 int 2236 adapter_full_init(struct adapter *sc) 2237 { 2238 int i, rc = 0; 2239 2240 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2241 2242 rc = t4_setup_adapter_queues(sc); 2243 if (rc != 0) 2244 goto done; 2245 2246 if (sc->intr_cap & DDI_INTR_FLAG_BLOCK) 2247 (void) ddi_intr_block_enable(sc->intr_handle, sc->intr_count); 2248 else { 2249 for (i = 0; i < sc->intr_count; i++) 2250 (void) ddi_intr_enable(sc->intr_handle[i]); 2251 } 2252 t4_intr_enable(sc); 2253 sc->flags |= FULL_INIT_DONE; 2254 2255 #ifndef TCP_OFFLOAD_DISABLE 2256 /* TODO: wrong place to enable TOE capability */ 2257 if (is_offload(sc) != 0) { 2258 for_each_port(sc, i) { 2259 struct port_info *pi = sc->port[i]; 2260 rc = toe_capability(pi, 1); 2261 if (rc != 0) { 2262 cxgb_printf(pi->dip, CE_WARN, 2263 "Failed to activate toe capability: %d", 2264 rc); 2265 rc = 0; /* not a fatal error */ 2266 } 2267 } 2268 } 2269 #endif 2270 2271 done: 2272 if (rc != 0) 2273 (void) adapter_full_uninit(sc); 2274 2275 return (rc); 2276 } 2277 2278 int 2279 adapter_full_uninit(struct adapter *sc) 2280 { 2281 int i, rc = 0; 2282 2283 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2284 2285 if (sc->intr_cap & DDI_INTR_FLAG_BLOCK) 2286 (void) ddi_intr_block_disable(sc->intr_handle, sc->intr_count); 2287 else { 2288 for (i = 0; i < sc->intr_count; i++) 2289 (void) ddi_intr_disable(sc->intr_handle[i]); 2290 } 2291 2292 rc = t4_teardown_adapter_queues(sc); 2293 if (rc != 0) 2294 return (rc); 2295 2296 sc->flags &= ~FULL_INIT_DONE; 2297 2298 return (0); 2299 } 2300 2301 int 2302 port_full_init(struct port_info *pi) 2303 { 2304 struct adapter *sc = pi->adapter; 2305 uint16_t *rss; 2306 struct sge_rxq *rxq; 2307 int rc, i; 2308 2309 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2310 ASSERT((pi->flags & PORT_INIT_DONE) == 0); 2311 2312 /* 2313 * Allocate tx/rx/fl queues for this port. 2314 */ 2315 rc = t4_setup_port_queues(pi); 2316 if (rc != 0) 2317 goto done; /* error message displayed already */ 2318 2319 /* 2320 * Setup RSS for this port. 2321 */ 2322 rss = kmem_zalloc(pi->nrxq * sizeof (*rss), KM_SLEEP); 2323 for_each_rxq(pi, i, rxq) { 2324 rss[i] = rxq->iq.abs_id; 2325 } 2326 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, 2327 pi->rss_size, rss, pi->nrxq); 2328 kmem_free(rss, pi->nrxq * sizeof (*rss)); 2329 if (rc != 0) { 2330 cxgb_printf(pi->dip, CE_WARN, "rss_config failed: %d", rc); 2331 goto done; 2332 } 2333 2334 pi->flags |= PORT_INIT_DONE; 2335 done: 2336 if (rc != 0) 2337 (void) port_full_uninit(pi); 2338 2339 return (rc); 2340 } 2341 2342 /* 2343 * Idempotent. 2344 */ 2345 int 2346 port_full_uninit(struct port_info *pi) 2347 { 2348 2349 ASSERT(pi->flags & PORT_INIT_DONE); 2350 2351 (void) t4_teardown_port_queues(pi); 2352 pi->flags &= ~PORT_INIT_DONE; 2353 2354 return (0); 2355 } 2356 2357 void 2358 enable_port_queues(struct port_info *pi) 2359 { 2360 struct adapter *sc = pi->adapter; 2361 int i; 2362 struct sge_iq *iq; 2363 struct sge_rxq *rxq; 2364 #ifndef TCP_OFFLOAD_DISABLE 2365 struct sge_ofld_rxq *ofld_rxq; 2366 #endif 2367 2368 ASSERT(pi->flags & PORT_INIT_DONE); 2369 2370 /* 2371 * TODO: whatever was queued up after we set iq->state to IQS_DISABLED 2372 * back in disable_port_queues will be processed now, after an unbounded 2373 * delay. This can't be good. 2374 */ 2375 2376 #ifndef TCP_OFFLOAD_DISABLE 2377 for_each_ofld_rxq(pi, i, ofld_rxq) { 2378 iq = &ofld_rxq->iq; 2379 if (atomic_cas_uint(&iq->state, IQS_DISABLED, IQS_IDLE) != 2380 IQS_DISABLED) 2381 panic("%s: iq %p wasn't disabled", __func__, 2382 (void *)iq); 2383 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 2384 V_SEINTARM(iq->intr_params) | V_INGRESSQID(iq->cntxt_id)); 2385 } 2386 #endif 2387 2388 for_each_rxq(pi, i, rxq) { 2389 iq = &rxq->iq; 2390 if (atomic_cas_uint(&iq->state, IQS_DISABLED, IQS_IDLE) != 2391 IQS_DISABLED) 2392 panic("%s: iq %p wasn't disabled", __func__, 2393 (void *) iq); 2394 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 2395 V_SEINTARM(iq->intr_params) | V_INGRESSQID(iq->cntxt_id)); 2396 } 2397 } 2398 2399 void 2400 disable_port_queues(struct port_info *pi) 2401 { 2402 int i; 2403 struct adapter *sc = pi->adapter; 2404 struct sge_rxq *rxq; 2405 #ifndef TCP_OFFLOAD_DISABLE 2406 struct sge_ofld_rxq *ofld_rxq; 2407 #endif 2408 2409 ASSERT(pi->flags & PORT_INIT_DONE); 2410 2411 /* 2412 * TODO: need proper implementation for all tx queues (ctrl, eth, ofld). 2413 */ 2414 2415 #ifndef TCP_OFFLOAD_DISABLE 2416 for_each_ofld_rxq(pi, i, ofld_rxq) { 2417 while (atomic_cas_uint(&ofld_rxq->iq.state, IQS_IDLE, 2418 IQS_DISABLED) != IQS_IDLE) 2419 msleep(1); 2420 } 2421 #endif 2422 2423 for_each_rxq(pi, i, rxq) { 2424 while (atomic_cas_uint(&rxq->iq.state, IQS_IDLE, 2425 IQS_DISABLED) != IQS_IDLE) 2426 msleep(1); 2427 } 2428 2429 mutex_enter(&sc->sfl_lock); 2430 #ifndef TCP_OFFLOAD_DISABLE 2431 for_each_ofld_rxq(pi, i, ofld_rxq) 2432 ofld_rxq->fl.flags |= FL_DOOMED; 2433 #endif 2434 for_each_rxq(pi, i, rxq) 2435 rxq->fl.flags |= FL_DOOMED; 2436 mutex_exit(&sc->sfl_lock); 2437 /* TODO: need to wait for all fl's to be removed from sc->sfl */ 2438 } 2439 2440 void 2441 t4_fatal_err(struct adapter *sc) 2442 { 2443 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2444 t4_intr_disable(sc); 2445 cxgb_printf(sc->dip, CE_WARN, 2446 "encountered fatal error, adapter stopped."); 2447 } 2448 2449 int 2450 t4_os_find_pci_capability(struct adapter *sc, int cap) 2451 { 2452 uint16_t stat; 2453 uint8_t cap_ptr, cap_id; 2454 2455 t4_os_pci_read_cfg2(sc, PCI_CONF_STAT, &stat); 2456 if ((stat & PCI_STAT_CAP) == 0) 2457 return (0); /* does not implement capabilities */ 2458 2459 t4_os_pci_read_cfg1(sc, PCI_CONF_CAP_PTR, &cap_ptr); 2460 while (cap_ptr) { 2461 t4_os_pci_read_cfg1(sc, cap_ptr + PCI_CAP_ID, &cap_id); 2462 if (cap_id == cap) 2463 return (cap_ptr); /* found */ 2464 t4_os_pci_read_cfg1(sc, cap_ptr + PCI_CAP_NEXT_PTR, &cap_ptr); 2465 } 2466 2467 return (0); /* not found */ 2468 } 2469 2470 void 2471 t4_os_portmod_changed(const struct adapter *sc, int idx) 2472 { 2473 static const char *mod_str[] = { 2474 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 2475 }; 2476 const struct port_info *pi = sc->port[idx]; 2477 2478 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 2479 cxgb_printf(pi->dip, CE_NOTE, "transceiver unplugged."); 2480 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 2481 cxgb_printf(pi->dip, CE_NOTE, 2482 "unknown transceiver inserted.\n"); 2483 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 2484 cxgb_printf(pi->dip, CE_NOTE, 2485 "unsupported transceiver inserted.\n"); 2486 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) 2487 cxgb_printf(pi->dip, CE_NOTE, "%s transceiver inserted.\n", 2488 mod_str[pi->mod_type]); 2489 else 2490 cxgb_printf(pi->dip, CE_NOTE, "transceiver (type %d) inserted.", 2491 pi->mod_type); 2492 } 2493 2494 /* ARGSUSED */ 2495 static int 2496 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) 2497 { 2498 if (m != NULL) 2499 freemsg(m); 2500 return (0); 2501 } 2502 2503 int 2504 t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h) 2505 { 2506 uint_t *loc, new; 2507 2508 if (opcode >= ARRAY_SIZE(sc->cpl_handler)) 2509 return (EINVAL); 2510 2511 new = (uint_t)(unsigned long) (h ? h : cpl_not_handled); 2512 loc = (uint_t *)&sc->cpl_handler[opcode]; 2513 (void) atomic_swap_uint(loc, new); 2514 2515 return (0); 2516 } 2517 2518 static int 2519 fw_msg_not_handled(struct adapter *sc, const __be64 *data) 2520 { 2521 struct cpl_fw6_msg *cpl = container_of(data, struct cpl_fw6_msg, data); 2522 2523 cxgb_printf(sc->dip, CE_WARN, "%s fw_msg type %d", __func__, cpl->type); 2524 return (0); 2525 } 2526 2527 int 2528 t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h) 2529 { 2530 fw_msg_handler_t *loc, new; 2531 2532 if (type >= ARRAY_SIZE(sc->fw_msg_handler)) 2533 return (EINVAL); 2534 2535 /* 2536 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 2537 * handler dispatch table. Reject any attempt to install a handler for 2538 * this subtype. 2539 */ 2540 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) 2541 return (EINVAL); 2542 2543 new = h ? h : fw_msg_not_handled; 2544 loc = &sc->fw_msg_handler[type]; 2545 (void)atomic_swap_ptr(loc, (void *)new); 2546 2547 return (0); 2548 } 2549 2550 #ifndef TCP_OFFLOAD_DISABLE 2551 static int 2552 toe_capability(struct port_info *pi, int enable) 2553 { 2554 int rc; 2555 struct adapter *sc = pi->adapter; 2556 2557 if (!is_offload(sc)) 2558 return (ENODEV); 2559 2560 if (enable != 0) { 2561 if (isset(&sc->offload_map, pi->port_id) != 0) 2562 return (0); 2563 2564 if (sc->offload_map == 0) { 2565 rc = activate_uld(sc, ULD_TOM, &sc->tom); 2566 if (rc != 0) 2567 return (rc); 2568 } 2569 2570 setbit(&sc->offload_map, pi->port_id); 2571 } else { 2572 if (!isset(&sc->offload_map, pi->port_id)) 2573 return (0); 2574 2575 clrbit(&sc->offload_map, pi->port_id); 2576 2577 if (sc->offload_map == 0) { 2578 rc = deactivate_uld(&sc->tom); 2579 if (rc != 0) { 2580 setbit(&sc->offload_map, pi->port_id); 2581 return (rc); 2582 } 2583 } 2584 } 2585 2586 return (0); 2587 } 2588 2589 /* 2590 * Add an upper layer driver to the global list. 2591 */ 2592 int 2593 t4_register_uld(struct uld_info *ui) 2594 { 2595 int rc = 0; 2596 struct uld_info *u; 2597 2598 mutex_enter(&t4_uld_list_lock); 2599 SLIST_FOREACH(u, &t4_uld_list, link) { 2600 if (u->uld_id == ui->uld_id) { 2601 rc = EEXIST; 2602 goto done; 2603 } 2604 } 2605 2606 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 2607 ui->refcount = 0; 2608 done: 2609 mutex_exit(&t4_uld_list_lock); 2610 return (rc); 2611 } 2612 2613 int 2614 t4_unregister_uld(struct uld_info *ui) 2615 { 2616 int rc = EINVAL; 2617 struct uld_info *u; 2618 2619 mutex_enter(&t4_uld_list_lock); 2620 2621 SLIST_FOREACH(u, &t4_uld_list, link) { 2622 if (u == ui) { 2623 if (ui->refcount > 0) { 2624 rc = EBUSY; 2625 goto done; 2626 } 2627 2628 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 2629 rc = 0; 2630 goto done; 2631 } 2632 } 2633 done: 2634 mutex_exit(&t4_uld_list_lock); 2635 return (rc); 2636 } 2637 2638 static int 2639 activate_uld(struct adapter *sc, int id, struct uld_softc *usc) 2640 { 2641 int rc = EAGAIN; 2642 struct uld_info *ui; 2643 2644 mutex_enter(&t4_uld_list_lock); 2645 2646 SLIST_FOREACH(ui, &t4_uld_list, link) { 2647 if (ui->uld_id == id) { 2648 rc = ui->attach(sc, &usc->softc); 2649 if (rc == 0) { 2650 ASSERT(usc->softc != NULL); 2651 ui->refcount++; 2652 usc->uld = ui; 2653 } 2654 goto done; 2655 } 2656 } 2657 done: 2658 mutex_exit(&t4_uld_list_lock); 2659 2660 return (rc); 2661 } 2662 2663 static int 2664 deactivate_uld(struct uld_softc *usc) 2665 { 2666 int rc; 2667 2668 mutex_enter(&t4_uld_list_lock); 2669 2670 if (usc->uld == NULL || usc->softc == NULL) { 2671 rc = EINVAL; 2672 goto done; 2673 } 2674 2675 rc = usc->uld->detach(usc->softc); 2676 if (rc == 0) { 2677 ASSERT(usc->uld->refcount > 0); 2678 usc->uld->refcount--; 2679 usc->uld = NULL; 2680 usc->softc = NULL; 2681 } 2682 done: 2683 mutex_exit(&t4_uld_list_lock); 2684 2685 return (rc); 2686 } 2687 2688 void 2689 t4_iterate(void (*func)(int, void *), void *arg) 2690 { 2691 struct adapter *sc; 2692 2693 mutex_enter(&t4_adapter_list_lock); 2694 SLIST_FOREACH(sc, &t4_adapter_list, link) { 2695 /* 2696 * func should not make any assumptions about what state sc is 2697 * in - the only guarantee is that sc->sc_lock is a valid lock. 2698 */ 2699 func(ddi_get_instance(sc->dip), arg); 2700 } 2701 mutex_exit(&t4_adapter_list_lock); 2702 } 2703 2704 #endif 2705