156b2bdd1SGireesh Nagabhushana /*
256b2bdd1SGireesh Nagabhushana  * Chelsio Terminator 4 (T4) Firmware interface header file.
356b2bdd1SGireesh Nagabhushana  *
43dde7c95SVishal Kulkarni  * Copyright (C) 2009-2014 Chelsio Communications.  All rights reserved.
556b2bdd1SGireesh Nagabhushana  *
656b2bdd1SGireesh Nagabhushana  * Written by felix marti (felix@chelsio.com)
756b2bdd1SGireesh Nagabhushana  *
856b2bdd1SGireesh Nagabhushana  * This program is distributed in the hope that it will be useful, but WITHOUT
956b2bdd1SGireesh Nagabhushana  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1056b2bdd1SGireesh Nagabhushana  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
1156b2bdd1SGireesh Nagabhushana  * release for licensing terms and conditions.
1256b2bdd1SGireesh Nagabhushana  */
133dde7c95SVishal Kulkarni 
14*d77e6e0fSPaul Winder /*
15*d77e6e0fSPaul Winder  * Copyright 2020 RackTop Systems, Inc.
16*d77e6e0fSPaul Winder  */
17*d77e6e0fSPaul Winder 
1856b2bdd1SGireesh Nagabhushana #ifndef _T4FW_INTERFACE_H_
193dde7c95SVishal Kulkarni #define _T4FW_INTERFACE_H_
2056b2bdd1SGireesh Nagabhushana 
213dde7c95SVishal Kulkarni /******************************************************************************
223dde7c95SVishal Kulkarni  *   R E T U R N   V A L U E S
233dde7c95SVishal Kulkarni  ********************************/
2456b2bdd1SGireesh Nagabhushana 
2556b2bdd1SGireesh Nagabhushana enum fw_retval {
2656b2bdd1SGireesh Nagabhushana 	FW_SUCCESS		= 0,	/* completed sucessfully */
2756b2bdd1SGireesh Nagabhushana 	FW_EPERM		= 1,	/* operation not permitted */
2856b2bdd1SGireesh Nagabhushana 	FW_ENOENT		= 2,	/* no such file or directory */
2956b2bdd1SGireesh Nagabhushana 	FW_EIO			= 5,	/* input/output error; hw bad */
3056b2bdd1SGireesh Nagabhushana 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
3156b2bdd1SGireesh Nagabhushana 	FW_EAGAIN		= 11,	/* try again */
3256b2bdd1SGireesh Nagabhushana 	FW_ENOMEM		= 12,	/* out of memory */
3356b2bdd1SGireesh Nagabhushana 	FW_EFAULT		= 14,	/* bad address; fw bad */
3456b2bdd1SGireesh Nagabhushana 	FW_EBUSY		= 16,	/* resource busy */
3556b2bdd1SGireesh Nagabhushana 	FW_EEXIST		= 17,	/* file exists */
36de483253SVishal Kulkarni 	FW_ENODEV		= 19,	/* no such device */
3756b2bdd1SGireesh Nagabhushana 	FW_EINVAL		= 22,	/* invalid argument */
3856b2bdd1SGireesh Nagabhushana 	FW_ENOSPC		= 28,	/* no space left on device */
3956b2bdd1SGireesh Nagabhushana 	FW_ENOSYS		= 38,	/* functionality not implemented */
40de483253SVishal Kulkarni 	FW_ENODATA		= 61,	/* no data available */
4156b2bdd1SGireesh Nagabhushana 	FW_EPROTO		= 71,	/* protocol error */
4256b2bdd1SGireesh Nagabhushana 	FW_EADDRINUSE		= 98,	/* address already in use */
4356b2bdd1SGireesh Nagabhushana 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
4456b2bdd1SGireesh Nagabhushana 	FW_ENETDOWN		= 100,	/* network is down */
4556b2bdd1SGireesh Nagabhushana 	FW_ENETUNREACH		= 101,	/* network is unreachable */
4656b2bdd1SGireesh Nagabhushana 	FW_ENOBUFS		= 105,	/* no buffer space available */
4756b2bdd1SGireesh Nagabhushana 	FW_ETIMEDOUT		= 110,	/* timeout */
4856b2bdd1SGireesh Nagabhushana 	FW_EINPROGRESS		= 115,	/* fw internal */
4956b2bdd1SGireesh Nagabhushana 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
5056b2bdd1SGireesh Nagabhushana 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
5156b2bdd1SGireesh Nagabhushana 	FW_SCSI_ABORTED		= 130,	/* */
5256b2bdd1SGireesh Nagabhushana 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
5356b2bdd1SGireesh Nagabhushana 	FW_ERR_LINK_DOWN	= 132,	/* */
5456b2bdd1SGireesh Nagabhushana 	FW_RDEV_NOT_READY	= 133,	/* */
5556b2bdd1SGireesh Nagabhushana 	FW_ERR_RDEV_LOST	= 134,	/* */
5656b2bdd1SGireesh Nagabhushana 	FW_ERR_RDEV_LOGO	= 135,	/* */
5756b2bdd1SGireesh Nagabhushana 	FW_FCOE_NO_XCHG		= 136,	/* */
5856b2bdd1SGireesh Nagabhushana 	FW_SCSI_RSP_ERR		= 137,	/* */
5956b2bdd1SGireesh Nagabhushana 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
6056b2bdd1SGireesh Nagabhushana 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
6156b2bdd1SGireesh Nagabhushana 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
623dde7c95SVishal Kulkarni 	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
6356b2bdd1SGireesh Nagabhushana 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
6456b2bdd1SGireesh Nagabhushana };
6556b2bdd1SGireesh Nagabhushana 
663dde7c95SVishal Kulkarni /******************************************************************************
673dde7c95SVishal Kulkarni  *   M E M O R Y   T Y P E s
683dde7c95SVishal Kulkarni  ******************************/
693dde7c95SVishal Kulkarni 
703dde7c95SVishal Kulkarni enum fw_memtype {
713dde7c95SVishal Kulkarni 	FW_MEMTYPE_EDC0		= 0x0,
723dde7c95SVishal Kulkarni 	FW_MEMTYPE_EDC1		= 0x1,
733dde7c95SVishal Kulkarni 	FW_MEMTYPE_EXTMEM	= 0x2,
743dde7c95SVishal Kulkarni 	FW_MEMTYPE_FLASH	= 0x4,
753dde7c95SVishal Kulkarni 	FW_MEMTYPE_INTERNAL	= 0x5,
763dde7c95SVishal Kulkarni 	FW_MEMTYPE_EXTMEM1	= 0x6,
777e6ad469SVishal Kulkarni 	FW_MEMTYPE_HMA          = 0x7,
783dde7c95SVishal Kulkarni };
793dde7c95SVishal Kulkarni 
803dde7c95SVishal Kulkarni /******************************************************************************
813dde7c95SVishal Kulkarni  *   W O R K   R E Q U E S T s
823dde7c95SVishal Kulkarni  ********************************/
8356b2bdd1SGireesh Nagabhushana 
8456b2bdd1SGireesh Nagabhushana enum fw_wr_opcodes {
85de483253SVishal Kulkarni 	FW_FRAG_WR		= 0x1d,
8656b2bdd1SGireesh Nagabhushana 	FW_FILTER_WR		= 0x02,
8756b2bdd1SGireesh Nagabhushana 	FW_ULPTX_WR		= 0x04,
8856b2bdd1SGireesh Nagabhushana 	FW_TP_WR		= 0x05,
8956b2bdd1SGireesh Nagabhushana 	FW_ETH_TX_PKT_WR	= 0x08,
90de483253SVishal Kulkarni 	FW_ETH_TX_PKT2_WR	= 0x44,
9156b2bdd1SGireesh Nagabhushana 	FW_ETH_TX_PKTS_WR	= 0x09,
923dde7c95SVishal Kulkarni 	FW_ETH_TX_PKTS2_WR	= 0x78,
933dde7c95SVishal Kulkarni 	FW_ETH_TX_EO_WR		= 0x1c,
9456b2bdd1SGireesh Nagabhushana 	FW_EQ_FLUSH_WR		= 0x1b,
9556b2bdd1SGireesh Nagabhushana 	FW_OFLD_CONNECTION_WR	= 0x2f,
9656b2bdd1SGireesh Nagabhushana 	FW_FLOWC_WR		= 0x0a,
9756b2bdd1SGireesh Nagabhushana 	FW_OFLD_TX_DATA_WR	= 0x0b,
9856b2bdd1SGireesh Nagabhushana 	FW_CMD_WR		= 0x10,
9956b2bdd1SGireesh Nagabhushana 	FW_ETH_TX_PKT_VM_WR	= 0x11,
1007e6ad469SVishal Kulkarni 	FW_ETH_TX_PKTS_VM_WR	= 0x12,
10156b2bdd1SGireesh Nagabhushana 	FW_RI_RES_WR		= 0x0c,
10256b2bdd1SGireesh Nagabhushana 	FW_RI_RDMA_WRITE_WR	= 0x14,
10356b2bdd1SGireesh Nagabhushana 	FW_RI_SEND_WR		= 0x15,
10456b2bdd1SGireesh Nagabhushana 	FW_RI_RDMA_READ_WR	= 0x16,
10556b2bdd1SGireesh Nagabhushana 	FW_RI_RECV_WR		= 0x17,
10656b2bdd1SGireesh Nagabhushana 	FW_RI_BIND_MW_WR	= 0x18,
10756b2bdd1SGireesh Nagabhushana 	FW_RI_FR_NSMR_WR	= 0x19,
1083dde7c95SVishal Kulkarni 	FW_RI_FR_NSMR_TPTE_WR	= 0x20,
1097e6ad469SVishal Kulkarni 	FW_RI_RDMA_WRITE_CMPL_WR =  0x21,
11056b2bdd1SGireesh Nagabhushana 	FW_RI_INV_LSTAG_WR	= 0x1a,
11156b2bdd1SGireesh Nagabhushana 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
11256b2bdd1SGireesh Nagabhushana 	FW_RI_ATOMIC_WR		= 0x16,
11356b2bdd1SGireesh Nagabhushana 	FW_RI_WR		= 0x0d,
11456b2bdd1SGireesh Nagabhushana 	FW_CHNET_IFCONF_WR	= 0x6b,
11556b2bdd1SGireesh Nagabhushana 	FW_RDEV_WR		= 0x38,
11656b2bdd1SGireesh Nagabhushana 	FW_FOISCSI_NODE_WR	= 0x60,
11756b2bdd1SGireesh Nagabhushana 	FW_FOISCSI_CTRL_WR	= 0x6a,
11856b2bdd1SGireesh Nagabhushana 	FW_FOISCSI_CHAP_WR	= 0x6c,
11956b2bdd1SGireesh Nagabhushana 	FW_FCOE_ELS_CT_WR	= 0x30,
12056b2bdd1SGireesh Nagabhushana 	FW_SCSI_WRITE_WR	= 0x31,
12156b2bdd1SGireesh Nagabhushana 	FW_SCSI_READ_WR		= 0x32,
12256b2bdd1SGireesh Nagabhushana 	FW_SCSI_CMD_WR		= 0x33,
12356b2bdd1SGireesh Nagabhushana 	FW_SCSI_ABRT_CLS_WR	= 0x34,
12456b2bdd1SGireesh Nagabhushana 	FW_SCSI_TGT_ACC_WR	= 0x35,
12556b2bdd1SGireesh Nagabhushana 	FW_SCSI_TGT_XMIT_WR	= 0x36,
12656b2bdd1SGireesh Nagabhushana 	FW_SCSI_TGT_RSP_WR	= 0x37,
127de483253SVishal Kulkarni 	FW_POFCOE_TCB_WR	= 0x42,
128de483253SVishal Kulkarni 	FW_POFCOE_ULPTX_WR	= 0x43,
1293dde7c95SVishal Kulkarni 	FW_ISCSI_TX_DATA_WR	= 0x45,
1303dde7c95SVishal Kulkarni 	FW_PTP_TX_PKT_WR        = 0x46,
1313dde7c95SVishal Kulkarni 	FW_TLSTX_DATA_WR	= 0x68,
1323dde7c95SVishal Kulkarni 	FW_TLS_KEYCTX_TX_WR	= 0x69,
1333dde7c95SVishal Kulkarni 	FW_CRYPTO_LOOKASIDE_WR	= 0x6d,
1343dde7c95SVishal Kulkarni 	FW_COiSCSI_TGT_WR	= 0x70,
1353dde7c95SVishal Kulkarni 	FW_COiSCSI_TGT_CONN_WR	= 0x71,
1363dde7c95SVishal Kulkarni 	FW_COiSCSI_TGT_XMIT_WR	= 0x72,
1373dde7c95SVishal Kulkarni 	FW_ISNS_WR		= 0x75,
1383dde7c95SVishal Kulkarni 	FW_ISNS_XMIT_WR		= 0x76,
1393dde7c95SVishal Kulkarni 	FW_FILTER2_WR		= 0x77,
1403dde7c95SVishal Kulkarni 	FW_LASTC2E_WR		= 0x80
14156b2bdd1SGireesh Nagabhushana };
14256b2bdd1SGireesh Nagabhushana 
14356b2bdd1SGireesh Nagabhushana /*
14456b2bdd1SGireesh Nagabhushana  * Generic work request header flit0
14556b2bdd1SGireesh Nagabhushana  */
14656b2bdd1SGireesh Nagabhushana struct fw_wr_hdr {
14756b2bdd1SGireesh Nagabhushana 	__be32 hi;
14856b2bdd1SGireesh Nagabhushana 	__be32 lo;
14956b2bdd1SGireesh Nagabhushana };
15056b2bdd1SGireesh Nagabhushana 
1513dde7c95SVishal Kulkarni /*	work request opcode (hi)
1523dde7c95SVishal Kulkarni  */
1533dde7c95SVishal Kulkarni #define S_FW_WR_OP		24
1543dde7c95SVishal Kulkarni #define M_FW_WR_OP		0xff
1553dde7c95SVishal Kulkarni #define V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
1563dde7c95SVishal Kulkarni #define G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
1573dde7c95SVishal Kulkarni 
1583dde7c95SVishal Kulkarni /*	atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
1593dde7c95SVishal Kulkarni  */
1603dde7c95SVishal Kulkarni #define S_FW_WR_ATOMIC		23
1613dde7c95SVishal Kulkarni #define M_FW_WR_ATOMIC		0x1
1623dde7c95SVishal Kulkarni #define V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
1633dde7c95SVishal Kulkarni #define G_FW_WR_ATOMIC(x)	\
1643dde7c95SVishal Kulkarni     (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
1653dde7c95SVishal Kulkarni #define F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
1663dde7c95SVishal Kulkarni 
1673dde7c95SVishal Kulkarni /*	flush flag (hi) - firmware flushes flushable work request buffered
1683dde7c95SVishal Kulkarni  *			      in the flow context.
1693dde7c95SVishal Kulkarni  */
1703dde7c95SVishal Kulkarni #define S_FW_WR_FLUSH     22
1713dde7c95SVishal Kulkarni #define M_FW_WR_FLUSH     0x1
1723dde7c95SVishal Kulkarni #define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
1733dde7c95SVishal Kulkarni #define G_FW_WR_FLUSH(x)  \
1743dde7c95SVishal Kulkarni     (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
1753dde7c95SVishal Kulkarni #define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)
1763dde7c95SVishal Kulkarni 
1773dde7c95SVishal Kulkarni /*	completion flag (hi) - firmware generates a cpl_fw6_ack
1783dde7c95SVishal Kulkarni  */
1793dde7c95SVishal Kulkarni #define S_FW_WR_COMPL     21
1803dde7c95SVishal Kulkarni #define M_FW_WR_COMPL     0x1
1813dde7c95SVishal Kulkarni #define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
1823dde7c95SVishal Kulkarni #define G_FW_WR_COMPL(x)  \
1833dde7c95SVishal Kulkarni     (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
1843dde7c95SVishal Kulkarni #define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)
1853dde7c95SVishal Kulkarni 
18656b2bdd1SGireesh Nagabhushana 
1873dde7c95SVishal Kulkarni /*	work request immediate data lengh (hi)
1883dde7c95SVishal Kulkarni  */
1893dde7c95SVishal Kulkarni #define S_FW_WR_IMMDLEN	0
1903dde7c95SVishal Kulkarni #define M_FW_WR_IMMDLEN	0xff
1913dde7c95SVishal Kulkarni #define V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
1923dde7c95SVishal Kulkarni #define G_FW_WR_IMMDLEN(x)	\
1933dde7c95SVishal Kulkarni     (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
19456b2bdd1SGireesh Nagabhushana 
1953dde7c95SVishal Kulkarni /*	egress queue status update to associated ingress queue entry (lo)
19656b2bdd1SGireesh Nagabhushana  */
1973dde7c95SVishal Kulkarni #define S_FW_WR_EQUIQ		31
1983dde7c95SVishal Kulkarni #define M_FW_WR_EQUIQ		0x1
1993dde7c95SVishal Kulkarni #define V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
2003dde7c95SVishal Kulkarni #define G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
2013dde7c95SVishal Kulkarni #define F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
2023dde7c95SVishal Kulkarni 
2033dde7c95SVishal Kulkarni /*	egress queue status update to egress queue status entry (lo)
2043dde7c95SVishal Kulkarni  */
2053dde7c95SVishal Kulkarni #define S_FW_WR_EQUEQ		30
2063dde7c95SVishal Kulkarni #define M_FW_WR_EQUEQ		0x1
2073dde7c95SVishal Kulkarni #define V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
2083dde7c95SVishal Kulkarni #define G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
2093dde7c95SVishal Kulkarni #define F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
2103dde7c95SVishal Kulkarni 
2113dde7c95SVishal Kulkarni /*	flow context identifier (lo)
2123dde7c95SVishal Kulkarni  */
2133dde7c95SVishal Kulkarni #define S_FW_WR_FLOWID		8
2143dde7c95SVishal Kulkarni #define M_FW_WR_FLOWID		0xfffff
2153dde7c95SVishal Kulkarni #define V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
2163dde7c95SVishal Kulkarni #define G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
2173dde7c95SVishal Kulkarni 
2183dde7c95SVishal Kulkarni /*	length in units of 16-bytes (lo)
2193dde7c95SVishal Kulkarni  */
2203dde7c95SVishal Kulkarni #define S_FW_WR_LEN16		0
2213dde7c95SVishal Kulkarni #define M_FW_WR_LEN16		0xff
2223dde7c95SVishal Kulkarni #define V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
2233dde7c95SVishal Kulkarni #define G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
22456b2bdd1SGireesh Nagabhushana 
225de483253SVishal Kulkarni struct fw_frag_wr {
226de483253SVishal Kulkarni 	__be32 op_to_fragoff16;
227de483253SVishal Kulkarni 	__be32 flowid_len16;
228de483253SVishal Kulkarni 	__be64 r4;
229de483253SVishal Kulkarni };
230de483253SVishal Kulkarni 
231de483253SVishal Kulkarni #define S_FW_FRAG_WR_EOF	15
232de483253SVishal Kulkarni #define M_FW_FRAG_WR_EOF	0x1
233de483253SVishal Kulkarni #define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
234de483253SVishal Kulkarni #define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
235de483253SVishal Kulkarni #define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
236de483253SVishal Kulkarni 
237de483253SVishal Kulkarni #define S_FW_FRAG_WR_FRAGOFF16		8
238de483253SVishal Kulkarni #define M_FW_FRAG_WR_FRAGOFF16		0x7f
239de483253SVishal Kulkarni #define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
240de483253SVishal Kulkarni #define G_FW_FRAG_WR_FRAGOFF16(x)	\
241de483253SVishal Kulkarni     (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
242de483253SVishal Kulkarni 
2433dde7c95SVishal Kulkarni /* valid filter configurations for compressed tuple
24456b2bdd1SGireesh Nagabhushana  * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
24556b2bdd1SGireesh Nagabhushana  * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
24656b2bdd1SGireesh Nagabhushana  * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
24756b2bdd1SGireesh Nagabhushana  * OV - Outer VLAN/VNIC_ID,
2483dde7c95SVishal Kulkarni */
2493dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_E_P_FC		0x3C3
2503dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_PR_T_FC		0x3B3
2513dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_IV_P_FC		0x38B
2523dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_OV_P_FC		0x387
2533dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_PR_T		0x370
2543dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_PR_P_FC		0X363
2553dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_T_P_FC		0X353
2563dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_PR_IV_P_FC		0X32B
2573dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_PR_OV_P_FC		0X327
2583dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_T_IV_P_FC		0X31B
2593dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_T_OV_P_FC		0X317
2603dde7c95SVishal Kulkarni #define HW_TPL_FR_M_E_PR_FC		0X2E1
2613dde7c95SVishal Kulkarni #define HW_TPL_FR_M_E_T_FC		0X2D1
2623dde7c95SVishal Kulkarni #define HW_TPL_FR_M_PR_IV_FC		0X2A9
2633dde7c95SVishal Kulkarni #define HW_TPL_FR_M_PR_OV_FC		0X2A5
2643dde7c95SVishal Kulkarni #define HW_TPL_FR_M_T_IV_FC		0X299
2653dde7c95SVishal Kulkarni #define HW_TPL_FR_M_T_OV_FC		0X295
2663dde7c95SVishal Kulkarni #define HW_TPL_FR_E_PR_T_P		0X272
2673dde7c95SVishal Kulkarni #define HW_TPL_FR_E_PR_T_FC		0X271
2683dde7c95SVishal Kulkarni #define HW_TPL_FR_E_IV_FC		0X249
2693dde7c95SVishal Kulkarni #define HW_TPL_FR_E_OV_FC		0X245
2703dde7c95SVishal Kulkarni #define HW_TPL_FR_PR_T_IV_FC		0X239
2713dde7c95SVishal Kulkarni #define HW_TPL_FR_PR_T_OV_FC		0X235
2723dde7c95SVishal Kulkarni #define HW_TPL_FR_IV_OV_FC		0X20D
2733dde7c95SVishal Kulkarni #define HW_TPL_MT_M_E_PR		0X1E0
2743dde7c95SVishal Kulkarni #define HW_TPL_MT_M_E_T			0X1D0
2753dde7c95SVishal Kulkarni #define HW_TPL_MT_E_PR_T_FC		0X171
2763dde7c95SVishal Kulkarni #define HW_TPL_MT_E_IV			0X148
2773dde7c95SVishal Kulkarni #define HW_TPL_MT_E_OV			0X144
2783dde7c95SVishal Kulkarni #define HW_TPL_MT_PR_T_IV		0X138
2793dde7c95SVishal Kulkarni #define HW_TPL_MT_PR_T_OV		0X134
2803dde7c95SVishal Kulkarni #define HW_TPL_M_E_PR_P			0X0E2
2813dde7c95SVishal Kulkarni #define HW_TPL_M_E_T_P			0X0D2
2823dde7c95SVishal Kulkarni #define HW_TPL_E_PR_T_P_FC		0X073
2833dde7c95SVishal Kulkarni #define HW_TPL_E_IV_P			0X04A
2843dde7c95SVishal Kulkarni #define HW_TPL_E_OV_P			0X046
2853dde7c95SVishal Kulkarni #define HW_TPL_PR_T_IV_P		0X03A
2863dde7c95SVishal Kulkarni #define HW_TPL_PR_T_OV_P		0X036
28756b2bdd1SGireesh Nagabhushana 
28856b2bdd1SGireesh Nagabhushana /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
28956b2bdd1SGireesh Nagabhushana enum fw_filter_wr_cookie {
29056b2bdd1SGireesh Nagabhushana 	FW_FILTER_WR_SUCCESS,
29156b2bdd1SGireesh Nagabhushana 	FW_FILTER_WR_FLT_ADDED,
29256b2bdd1SGireesh Nagabhushana 	FW_FILTER_WR_FLT_DELETED,
29356b2bdd1SGireesh Nagabhushana 	FW_FILTER_WR_SMT_TBL_FULL,
29456b2bdd1SGireesh Nagabhushana 	FW_FILTER_WR_EINVAL,
29556b2bdd1SGireesh Nagabhushana };
29656b2bdd1SGireesh Nagabhushana 
2973dde7c95SVishal Kulkarni enum fw_filter_wr_nat_mode {
2983dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_NONE = 0,
2993dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_DIP ,
3003dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_DIPDP,
3013dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_DIPDPSIP,
3023dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_DIPDPSP,
3033dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_SIPSP,
3043dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_DIPSIPSP,
3053dde7c95SVishal Kulkarni 	FW_FILTER_WR_NATMODE_FOURTUPLE,
3063dde7c95SVishal Kulkarni };
3073dde7c95SVishal Kulkarni 
30856b2bdd1SGireesh Nagabhushana struct fw_filter_wr {
30956b2bdd1SGireesh Nagabhushana 	__be32 op_pkd;
31056b2bdd1SGireesh Nagabhushana 	__be32 len16_pkd;
31156b2bdd1SGireesh Nagabhushana 	__be64 r3;
31256b2bdd1SGireesh Nagabhushana 	__be32 tid_to_iq;
31356b2bdd1SGireesh Nagabhushana 	__be32 del_filter_to_l2tix;
31456b2bdd1SGireesh Nagabhushana 	__be16 ethtype;
31556b2bdd1SGireesh Nagabhushana 	__be16 ethtypem;
31656b2bdd1SGireesh Nagabhushana 	__u8   frag_to_ovlan_vldm;
31756b2bdd1SGireesh Nagabhushana 	__u8   smac_sel;
31856b2bdd1SGireesh Nagabhushana 	__be16 rx_chan_rx_rpl_iq;
31956b2bdd1SGireesh Nagabhushana 	__be32 maci_to_matchtypem;
32056b2bdd1SGireesh Nagabhushana 	__u8   ptcl;
32156b2bdd1SGireesh Nagabhushana 	__u8   ptclm;
32256b2bdd1SGireesh Nagabhushana 	__u8   ttyp;
32356b2bdd1SGireesh Nagabhushana 	__u8   ttypm;
32456b2bdd1SGireesh Nagabhushana 	__be16 ivlan;
32556b2bdd1SGireesh Nagabhushana 	__be16 ivlanm;
32656b2bdd1SGireesh Nagabhushana 	__be16 ovlan;
32756b2bdd1SGireesh Nagabhushana 	__be16 ovlanm;
32856b2bdd1SGireesh Nagabhushana 	__u8   lip[16];
32956b2bdd1SGireesh Nagabhushana 	__u8   lipm[16];
33056b2bdd1SGireesh Nagabhushana 	__u8   fip[16];
33156b2bdd1SGireesh Nagabhushana 	__u8   fipm[16];
33256b2bdd1SGireesh Nagabhushana 	__be16 lp;
33356b2bdd1SGireesh Nagabhushana 	__be16 lpm;
33456b2bdd1SGireesh Nagabhushana 	__be16 fp;
33556b2bdd1SGireesh Nagabhushana 	__be16 fpm;
33656b2bdd1SGireesh Nagabhushana 	__be16 r7;
33756b2bdd1SGireesh Nagabhushana 	__u8   sma[6];
33856b2bdd1SGireesh Nagabhushana };
33956b2bdd1SGireesh Nagabhushana 
3403dde7c95SVishal Kulkarni struct fw_filter2_wr {
3413dde7c95SVishal Kulkarni 	__be32 op_pkd;
3423dde7c95SVishal Kulkarni 	__be32 len16_pkd;
3433dde7c95SVishal Kulkarni 	__be64 r3;
3443dde7c95SVishal Kulkarni 	__be32 tid_to_iq;
3453dde7c95SVishal Kulkarni 	__be32 del_filter_to_l2tix;
3463dde7c95SVishal Kulkarni 	__be16 ethtype;
3473dde7c95SVishal Kulkarni 	__be16 ethtypem;
3483dde7c95SVishal Kulkarni 	__u8   frag_to_ovlan_vldm;
3493dde7c95SVishal Kulkarni 	__u8   smac_sel;
3503dde7c95SVishal Kulkarni 	__be16 rx_chan_rx_rpl_iq;
3513dde7c95SVishal Kulkarni 	__be32 maci_to_matchtypem;
3523dde7c95SVishal Kulkarni 	__u8   ptcl;
3533dde7c95SVishal Kulkarni 	__u8   ptclm;
3543dde7c95SVishal Kulkarni 	__u8   ttyp;
3553dde7c95SVishal Kulkarni 	__u8   ttypm;
3563dde7c95SVishal Kulkarni 	__be16 ivlan;
3573dde7c95SVishal Kulkarni 	__be16 ivlanm;
3583dde7c95SVishal Kulkarni 	__be16 ovlan;
3593dde7c95SVishal Kulkarni 	__be16 ovlanm;
3603dde7c95SVishal Kulkarni 	__u8   lip[16];
3613dde7c95SVishal Kulkarni 	__u8   lipm[16];
3623dde7c95SVishal Kulkarni 	__u8   fip[16];
3633dde7c95SVishal Kulkarni 	__u8   fipm[16];
3643dde7c95SVishal Kulkarni 	__be16 lp;
3653dde7c95SVishal Kulkarni 	__be16 lpm;
3663dde7c95SVishal Kulkarni 	__be16 fp;
3673dde7c95SVishal Kulkarni 	__be16 fpm;
3683dde7c95SVishal Kulkarni 	__be16 r7;
3693dde7c95SVishal Kulkarni 	__u8   sma[6];
3707e6ad469SVishal Kulkarni 	__be16 r8;
3713dde7c95SVishal Kulkarni 	__u8   filter_type_swapmac;
3723dde7c95SVishal Kulkarni 	__u8   natmode_to_ulp_type;
3733dde7c95SVishal Kulkarni 	__be16 newlport;
3743dde7c95SVishal Kulkarni 	__be16 newfport;
3753dde7c95SVishal Kulkarni 	__u8   newlip[16];
3763dde7c95SVishal Kulkarni 	__u8   newfip[16];
3773dde7c95SVishal Kulkarni 	__be32 natseqcheck;
3787e6ad469SVishal Kulkarni 	__be32 r9;
3793dde7c95SVishal Kulkarni 	__be64 r10;
3803dde7c95SVishal Kulkarni 	__be64 r11;
3813dde7c95SVishal Kulkarni 	__be64 r12;
3823dde7c95SVishal Kulkarni 	__be64 r13;
3833dde7c95SVishal Kulkarni };
3843dde7c95SVishal Kulkarni 
3853dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_TID	12
3863dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_TID	0xfffff
3873dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
3883dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_TID(x)	\
3893dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
3903dde7c95SVishal Kulkarni 
3913dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RQTYPE		11
3923dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RQTYPE		0x1
3933dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
3943dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RQTYPE(x)	\
3953dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
3963dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
3973dde7c95SVishal Kulkarni 
3983dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_NOREPLY		10
3993dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_NOREPLY		0x1
4003dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
4013dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_NOREPLY(x)	\
4023dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
4033dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
4043dde7c95SVishal Kulkarni 
4053dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IQ	0
4063dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IQ	0x3ff
4073dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
4083dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IQ(x)	\
4093dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
4103dde7c95SVishal Kulkarni 
4113dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DEL_FILTER	31
4123dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DEL_FILTER	0x1
4133dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
4143dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DEL_FILTER(x)	\
4153dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
4163dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
4173dde7c95SVishal Kulkarni 
4187e6ad469SVishal Kulkarni #define S_FW_FILTER2_WR_DROP_ENCAP	30
4197e6ad469SVishal Kulkarni #define M_FW_FILTER2_WR_DROP_ENCAP	0x1
4207e6ad469SVishal Kulkarni #define V_FW_FILTER2_WR_DROP_ENCAP(x)	((x) << S_FW_FILTER2_WR_DROP_ENCAP)
4217e6ad469SVishal Kulkarni #define G_FW_FILTER2_WR_DROP_ENCAP(x)	\
4227e6ad469SVishal Kulkarni     (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)
4237e6ad469SVishal Kulkarni #define F_FW_FILTER2_WR_DROP_ENCAP	V_FW_FILTER2_WR_DROP_ENCAP(1U)
4247e6ad469SVishal Kulkarni 
4257e6ad469SVishal Kulkarni #define S_FW_FILTER2_WR_TX_LOOP         29
4267e6ad469SVishal Kulkarni #define M_FW_FILTER2_WR_TX_LOOP         0x1
4277e6ad469SVishal Kulkarni #define V_FW_FILTER2_WR_TX_LOOP(x)      ((x) << S_FW_FILTER2_WR_TX_LOOP)
4287e6ad469SVishal Kulkarni #define G_FW_FILTER2_WR_TX_LOOP(x)      \
4297e6ad469SVishal Kulkarni 	    (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)
4307e6ad469SVishal Kulkarni #define F_FW_FILTER2_WR_TX_LOOP         V_FW_FILTER2_WR_TX_LOOP(1U)
4317e6ad469SVishal Kulkarni 
4323dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RPTTID		25
4333dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RPTTID		0x1
4343dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
4353dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RPTTID(x)	\
4363dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
4373dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
4383dde7c95SVishal Kulkarni 
4393dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DROP	24
4403dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DROP	0x1
4413dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
4423dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DROP(x)	\
4433dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
4443dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
4453dde7c95SVishal Kulkarni 
4463dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DIRSTEER		23
4473dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DIRSTEER		0x1
4483dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
4493dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DIRSTEER(x)	\
4503dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
4513dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
4523dde7c95SVishal Kulkarni 
4533dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MASKHASH		22
4543dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MASKHASH		0x1
4553dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
4563dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MASKHASH(x)	\
4573dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
4583dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
4593dde7c95SVishal Kulkarni 
4603dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DIRSTEERHASH	21
4613dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DIRSTEERHASH	0x1
4623dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
4633dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DIRSTEERHASH(x)	\
4643dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
4653dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
4663dde7c95SVishal Kulkarni 
4673dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_LPBK	20
4683dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_LPBK	0x1
4693dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
4703dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_LPBK(x)	\
4713dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
4723dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
4733dde7c95SVishal Kulkarni 
4743dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DMAC	19
4753dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DMAC	0x1
4763dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
4773dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DMAC(x)	\
4783dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
4793dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
4803dde7c95SVishal Kulkarni 
4813dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_SMAC	18
4823dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_SMAC	0x1
4833dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
4843dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_SMAC(x)	\
4853dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
4863dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
4873dde7c95SVishal Kulkarni 
4883dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_INSVLAN		17
4893dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_INSVLAN		0x1
4903dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
4913dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_INSVLAN(x)	\
4923dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
4933dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
4943dde7c95SVishal Kulkarni 
4953dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RMVLAN		16
4963dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RMVLAN		0x1
4973dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
4983dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RMVLAN(x)	\
4993dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
5003dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
5013dde7c95SVishal Kulkarni 
5023dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_HITCNTS		15
5033dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_HITCNTS		0x1
5043dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
5053dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_HITCNTS(x)	\
5063dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
5073dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
5083dde7c95SVishal Kulkarni 
5093dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_TXCHAN		13
5103dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_TXCHAN		0x3
5113dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
5123dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_TXCHAN(x)	\
5133dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
5143dde7c95SVishal Kulkarni 
5153dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PRIO	12
5163dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PRIO	0x1
5173dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
5183dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PRIO(x)	\
5193dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
5203dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
5213dde7c95SVishal Kulkarni 
5223dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_L2TIX	0
5233dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_L2TIX	0xfff
5243dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
5253dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_L2TIX(x)	\
5263dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
5273dde7c95SVishal Kulkarni 
5283dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FRAG	7
5293dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FRAG	0x1
5303dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
5313dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FRAG(x)	\
5323dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
5333dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
5343dde7c95SVishal Kulkarni 
5353dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FRAGM	6
5363dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FRAGM	0x1
5373dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
5383dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FRAGM(x)	\
5393dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
5403dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
5413dde7c95SVishal Kulkarni 
5423dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IVLAN_VLD	5
5433dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IVLAN_VLD	0x1
5443dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
5453dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IVLAN_VLD(x)	\
5463dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
5473dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
5483dde7c95SVishal Kulkarni 
5493dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_OVLAN_VLD	4
5503dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_OVLAN_VLD	0x1
5513dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
5523dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_OVLAN_VLD(x)	\
5533dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
5543dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
5553dde7c95SVishal Kulkarni 
5563dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IVLAN_VLDM	3
5573dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IVLAN_VLDM	0x1
5583dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
5593dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IVLAN_VLDM(x)	\
5603dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
5613dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
5623dde7c95SVishal Kulkarni 
5633dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_OVLAN_VLDM	2
5643dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_OVLAN_VLDM	0x1
5653dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
5663dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_OVLAN_VLDM(x)	\
5673dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
5683dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
5693dde7c95SVishal Kulkarni 
5703dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RX_CHAN		15
5713dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RX_CHAN		0x1
5723dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
5733dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RX_CHAN(x)	\
5743dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
5753dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
5763dde7c95SVishal Kulkarni 
5773dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RX_RPL_IQ	0
5783dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
5793dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
5803dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RX_RPL_IQ(x)	\
5813dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
5823dde7c95SVishal Kulkarni 
5833dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_FILTER_TYPE	1
5843dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_FILTER_TYPE	0x1
5853dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_FILTER_TYPE(x)	((x) << S_FW_FILTER2_WR_FILTER_TYPE)
5863dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_FILTER_TYPE(x)	\
5873dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
5883dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_FILTER_TYPE	V_FW_FILTER2_WR_FILTER_TYPE(1U)
5893dde7c95SVishal Kulkarni 
5903dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_SWAPMAC		0
5913dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_SWAPMAC		0x1
5923dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_SWAPMAC(x)	((x) << S_FW_FILTER2_WR_SWAPMAC)
5933dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_SWAPMAC(x)	\
5943dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
5953dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_SWAPMAC		V_FW_FILTER2_WR_SWAPMAC(1U)
5963dde7c95SVishal Kulkarni 
5973dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_NATMODE		5
5983dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_NATMODE		0x7
5993dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_NATMODE(x)	((x) << S_FW_FILTER2_WR_NATMODE)
6003dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_NATMODE(x)	\
6013dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
6023dde7c95SVishal Kulkarni 
6033dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_NATFLAGCHECK	4
6043dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_NATFLAGCHECK	0x1
6053dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_NATFLAGCHECK(x)	((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
6063dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_NATFLAGCHECK(x)	\
6073dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
6083dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_NATFLAGCHECK	V_FW_FILTER2_WR_NATFLAGCHECK(1U)
6093dde7c95SVishal Kulkarni 
6103dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_ULP_TYPE	0
6113dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_ULP_TYPE	0xf
6123dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_ULP_TYPE(x)	((x) << S_FW_FILTER2_WR_ULP_TYPE)
6133dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_ULP_TYPE(x)	\
6143dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
6153dde7c95SVishal Kulkarni 
6163dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MACI	23
6173dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MACI	0x1ff
6183dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
6193dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MACI(x)	\
6203dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
6213dde7c95SVishal Kulkarni 
6223dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MACIM	14
6233dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MACIM	0x1ff
6243dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
6253dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MACIM(x)	\
6263dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
6273dde7c95SVishal Kulkarni 
6283dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FCOE	13
6293dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FCOE	0x1
6303dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
6313dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FCOE(x)	\
6323dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
6333dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
6343dde7c95SVishal Kulkarni 
6353dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FCOEM	12
6363dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FCOEM	0x1
6373dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
6383dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FCOEM(x)	\
6393dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
6403dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
6413dde7c95SVishal Kulkarni 
6423dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PORT	9
6433dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PORT	0x7
6443dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
6453dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PORT(x)	\
6463dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
6473dde7c95SVishal Kulkarni 
6483dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PORTM	6
6493dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PORTM	0x7
6503dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
6513dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PORTM(x)	\
6523dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
6533dde7c95SVishal Kulkarni 
6543dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MATCHTYPE	3
6553dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MATCHTYPE	0x7
6563dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
6573dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MATCHTYPE(x)	\
6583dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
6593dde7c95SVishal Kulkarni 
6603dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MATCHTYPEM	0
6613dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MATCHTYPEM	0x7
6623dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
6633dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MATCHTYPEM(x)	\
6643dde7c95SVishal Kulkarni     (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
66556b2bdd1SGireesh Nagabhushana 
66656b2bdd1SGireesh Nagabhushana struct fw_ulptx_wr {
66756b2bdd1SGireesh Nagabhushana 	__be32 op_to_compl;
66856b2bdd1SGireesh Nagabhushana 	__be32 flowid_len16;
66956b2bdd1SGireesh Nagabhushana 	__u64  cookie;
67056b2bdd1SGireesh Nagabhushana };
67156b2bdd1SGireesh Nagabhushana 
6727e6ad469SVishal Kulkarni /*	flag for packet type - control packet (0), data packet (1)
6737e6ad469SVishal Kulkarni  */
6747e6ad469SVishal Kulkarni #define S_FW_ULPTX_WR_DATA	28
6757e6ad469SVishal Kulkarni #define M_FW_ULPTX_WR_DATA	0x1
6767e6ad469SVishal Kulkarni #define V_FW_ULPTX_WR_DATA(x)	((x) << S_FW_ULPTX_WR_DATA)
6777e6ad469SVishal Kulkarni #define G_FW_ULPTX_WR_DATA(x)	\
6787e6ad469SVishal Kulkarni     (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
6797e6ad469SVishal Kulkarni #define F_FW_ULPTX_WR_DATA	V_FW_ULPTX_WR_DATA(1U)
6807e6ad469SVishal Kulkarni 
68156b2bdd1SGireesh Nagabhushana struct fw_tp_wr {
68256b2bdd1SGireesh Nagabhushana 	__be32 op_to_immdlen;
68356b2bdd1SGireesh Nagabhushana 	__be32 flowid_len16;
68456b2bdd1SGireesh Nagabhushana 	__u64  cookie;
68556b2bdd1SGireesh Nagabhushana };
68656b2bdd1SGireesh Nagabhushana 
68756b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_wr {
68856b2bdd1SGireesh Nagabhushana 	__be32 op_immdlen;
68956b2bdd1SGireesh Nagabhushana 	__be32 equiq_to_len16;
69056b2bdd1SGireesh Nagabhushana 	__be64 r3;
69156b2bdd1SGireesh Nagabhushana };
69256b2bdd1SGireesh Nagabhushana 
6933dde7c95SVishal Kulkarni #define S_FW_ETH_TX_PKT_WR_IMMDLEN	0
6943dde7c95SVishal Kulkarni #define M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
6953dde7c95SVishal Kulkarni #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
6963dde7c95SVishal Kulkarni #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
6973dde7c95SVishal Kulkarni     (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
69856b2bdd1SGireesh Nagabhushana 
699de483253SVishal Kulkarni struct fw_eth_tx_pkt2_wr {
700de483253SVishal Kulkarni 	__be32 op_immdlen;
701de483253SVishal Kulkarni 	__be32 equiq_to_len16;
702de483253SVishal Kulkarni 	__be32 r3;
703de483253SVishal Kulkarni 	__be32 L4ChkDisable_to_IpHdrLen;
704de483253SVishal Kulkarni };
705de483253SVishal Kulkarni 
706de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
707de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
708de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
709de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
710de483253SVishal Kulkarni     (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
711de483253SVishal Kulkarni 
712de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
713de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
714de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
715de483253SVishal Kulkarni     ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
716de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
717de483253SVishal Kulkarni     (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
718de483253SVishal Kulkarni      M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
719de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
720de483253SVishal Kulkarni     V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
721de483253SVishal Kulkarni 
722de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
723de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
724de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
725de483253SVishal Kulkarni     ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
726de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
727de483253SVishal Kulkarni     (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
728de483253SVishal Kulkarni      M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
729de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
730de483253SVishal Kulkarni     V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
731de483253SVishal Kulkarni 
732de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLAN	28
733de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
734de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
735de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
736de483253SVishal Kulkarni     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN