1 /*
2  * Chelsio Terminator 4 (T4) Firmware interface header file.
3  *
4  * Copyright (C) 2009-2014 Chelsio Communications.  All rights reserved.
5  *
6  * Written by felix marti (felix@chelsio.com)
7  *
8  * This program is distributed in the hope that it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
11  * release for licensing terms and conditions.
12  */
13 
14 #ifndef _T4FW_INTERFACE_H_
15 #define _T4FW_INTERFACE_H_
16 
17 /******************************************************************************
18  *   R E T U R N   V A L U E S
19  ********************************/
20 
21 enum fw_retval {
22 	FW_SUCCESS		= 0,	/* completed sucessfully */
23 	FW_EPERM		= 1,	/* operation not permitted */
24 	FW_ENOENT		= 2,	/* no such file or directory */
25 	FW_EIO			= 5,	/* input/output error; hw bad */
26 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
27 	FW_EAGAIN		= 11,	/* try again */
28 	FW_ENOMEM		= 12,	/* out of memory */
29 	FW_EFAULT		= 14,	/* bad address; fw bad */
30 	FW_EBUSY		= 16,	/* resource busy */
31 	FW_EEXIST		= 17,	/* file exists */
32 	FW_ENODEV		= 19,	/* no such device */
33 	FW_EINVAL		= 22,	/* invalid argument */
34 	FW_ENOSPC		= 28,	/* no space left on device */
35 	FW_ENOSYS		= 38,	/* functionality not implemented */
36 	FW_ENODATA		= 61,	/* no data available */
37 	FW_EPROTO		= 71,	/* protocol error */
38 	FW_EADDRINUSE		= 98,	/* address already in use */
39 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
40 	FW_ENETDOWN		= 100,	/* network is down */
41 	FW_ENETUNREACH		= 101,	/* network is unreachable */
42 	FW_ENOBUFS		= 105,	/* no buffer space available */
43 	FW_ETIMEDOUT		= 110,	/* timeout */
44 	FW_EINPROGRESS		= 115,	/* fw internal */
45 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
46 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
47 	FW_SCSI_ABORTED		= 130,	/* */
48 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
49 	FW_ERR_LINK_DOWN	= 132,	/* */
50 	FW_RDEV_NOT_READY	= 133,	/* */
51 	FW_ERR_RDEV_LOST	= 134,	/* */
52 	FW_ERR_RDEV_LOGO	= 135,	/* */
53 	FW_FCOE_NO_XCHG		= 136,	/* */
54 	FW_SCSI_RSP_ERR		= 137,	/* */
55 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
56 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
57 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
58 	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
59 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
60 };
61 
62 /******************************************************************************
63  *   M E M O R Y   T Y P E s
64  ******************************/
65 
66 enum fw_memtype {
67 	FW_MEMTYPE_EDC0		= 0x0,
68 	FW_MEMTYPE_EDC1		= 0x1,
69 	FW_MEMTYPE_EXTMEM	= 0x2,
70 	FW_MEMTYPE_FLASH	= 0x4,
71 	FW_MEMTYPE_INTERNAL	= 0x5,
72 	FW_MEMTYPE_EXTMEM1	= 0x6,
73 	FW_MEMTYPE_HMA          = 0x7,
74 };
75 
76 /******************************************************************************
77  *   W O R K   R E Q U E S T s
78  ********************************/
79 
80 enum fw_wr_opcodes {
81 	FW_FRAG_WR		= 0x1d,
82 	FW_FILTER_WR		= 0x02,
83 	FW_ULPTX_WR		= 0x04,
84 	FW_TP_WR		= 0x05,
85 	FW_ETH_TX_PKT_WR	= 0x08,
86 	FW_ETH_TX_PKT2_WR	= 0x44,
87 	FW_ETH_TX_PKTS_WR	= 0x09,
88 	FW_ETH_TX_PKTS2_WR	= 0x78,
89 	FW_ETH_TX_EO_WR		= 0x1c,
90 	FW_EQ_FLUSH_WR		= 0x1b,
91 	FW_OFLD_CONNECTION_WR	= 0x2f,
92 	FW_FLOWC_WR		= 0x0a,
93 	FW_OFLD_TX_DATA_WR	= 0x0b,
94 	FW_CMD_WR		= 0x10,
95 	FW_ETH_TX_PKT_VM_WR	= 0x11,
96 	FW_ETH_TX_PKTS_VM_WR	= 0x12,
97 	FW_RI_RES_WR		= 0x0c,
98 	FW_RI_RDMA_WRITE_WR	= 0x14,
99 	FW_RI_SEND_WR		= 0x15,
100 	FW_RI_RDMA_READ_WR	= 0x16,
101 	FW_RI_RECV_WR		= 0x17,
102 	FW_RI_BIND_MW_WR	= 0x18,
103 	FW_RI_FR_NSMR_WR	= 0x19,
104 	FW_RI_FR_NSMR_TPTE_WR	= 0x20,
105 	FW_RI_RDMA_WRITE_CMPL_WR =  0x21,
106 	FW_RI_INV_LSTAG_WR	= 0x1a,
107 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
108 	FW_RI_ATOMIC_WR		= 0x16,
109 	FW_RI_WR		= 0x0d,
110 	FW_CHNET_IFCONF_WR	= 0x6b,
111 	FW_RDEV_WR		= 0x38,
112 	FW_FOISCSI_NODE_WR	= 0x60,
113 	FW_FOISCSI_CTRL_WR	= 0x6a,
114 	FW_FOISCSI_CHAP_WR	= 0x6c,
115 	FW_FCOE_ELS_CT_WR	= 0x30,
116 	FW_SCSI_WRITE_WR	= 0x31,
117 	FW_SCSI_READ_WR		= 0x32,
118 	FW_SCSI_CMD_WR		= 0x33,
119 	FW_SCSI_ABRT_CLS_WR	= 0x34,
120 	FW_SCSI_TGT_ACC_WR	= 0x35,
121 	FW_SCSI_TGT_XMIT_WR	= 0x36,
122 	FW_SCSI_TGT_RSP_WR	= 0x37,
123 	FW_POFCOE_TCB_WR	= 0x42,
124 	FW_POFCOE_ULPTX_WR	= 0x43,
125 	FW_ISCSI_TX_DATA_WR	= 0x45,
126 	FW_PTP_TX_PKT_WR        = 0x46,
127 	FW_TLSTX_DATA_WR	= 0x68,
128 	FW_TLS_KEYCTX_TX_WR	= 0x69,
129 	FW_CRYPTO_LOOKASIDE_WR	= 0x6d,
130 	FW_COiSCSI_TGT_WR	= 0x70,
131 	FW_COiSCSI_TGT_CONN_WR	= 0x71,
132 	FW_COiSCSI_TGT_XMIT_WR	= 0x72,
133 	FW_ISNS_WR		= 0x75,
134 	FW_ISNS_XMIT_WR		= 0x76,
135 	FW_FILTER2_WR		= 0x77,
136 	FW_LASTC2E_WR		= 0x80
137 };
138 
139 /*
140  * Generic work request header flit0
141  */
142 struct fw_wr_hdr {
143 	__be32 hi;
144 	__be32 lo;
145 };
146 
147 /*	work request opcode (hi)
148  */
149 #define S_FW_WR_OP		24
150 #define M_FW_WR_OP		0xff
151 #define V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
152 #define G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
153 
154 /*	atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
155  */
156 #define S_FW_WR_ATOMIC		23
157 #define M_FW_WR_ATOMIC		0x1
158 #define V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
159 #define G_FW_WR_ATOMIC(x)	\
160     (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
161 #define F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
162 
163 /*	flush flag (hi) - firmware flushes flushable work request buffered
164  *			      in the flow context.
165  */
166 #define S_FW_WR_FLUSH     22
167 #define M_FW_WR_FLUSH     0x1
168 #define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
169 #define G_FW_WR_FLUSH(x)  \
170     (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
171 #define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)
172 
173 /*	completion flag (hi) - firmware generates a cpl_fw6_ack
174  */
175 #define S_FW_WR_COMPL     21
176 #define M_FW_WR_COMPL     0x1
177 #define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
178 #define G_FW_WR_COMPL(x)  \
179     (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
180 #define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)
181 
182 
183 /*	work request immediate data lengh (hi)
184  */
185 #define S_FW_WR_IMMDLEN	0
186 #define M_FW_WR_IMMDLEN	0xff
187 #define V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
188 #define G_FW_WR_IMMDLEN(x)	\
189     (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
190 
191 /*	egress queue status update to associated ingress queue entry (lo)
192  */
193 #define S_FW_WR_EQUIQ		31
194 #define M_FW_WR_EQUIQ		0x1
195 #define V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
196 #define G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
197 #define F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
198 
199 /*	egress queue status update to egress queue status entry (lo)
200  */
201 #define S_FW_WR_EQUEQ		30
202 #define M_FW_WR_EQUEQ		0x1
203 #define V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
204 #define G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
205 #define F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
206 
207 /*	flow context identifier (lo)
208  */
209 #define S_FW_WR_FLOWID		8
210 #define M_FW_WR_FLOWID		0xfffff
211 #define V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
212 #define G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
213 
214 /*	length in units of 16-bytes (lo)
215  */
216 #define S_FW_WR_LEN16		0
217 #define M_FW_WR_LEN16		0xff
218 #define V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
219 #define G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
220 
221 struct fw_frag_wr {
222 	__be32 op_to_fragoff16;
223 	__be32 flowid_len16;
224 	__be64 r4;
225 };
226 
227 #define S_FW_FRAG_WR_EOF	15
228 #define M_FW_FRAG_WR_EOF	0x1
229 #define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
230 #define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
231 #define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
232 
233 #define S_FW_FRAG_WR_FRAGOFF16		8
234 #define M_FW_FRAG_WR_FRAGOFF16		0x7f
235 #define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
236 #define G_FW_FRAG_WR_FRAGOFF16(x)	\
237     (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
238 
239 /* valid filter configurations for compressed tuple
240  * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
241  * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
242  * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
243  * OV - Outer VLAN/VNIC_ID,
244 */
245 #define HW_TPL_FR_MT_M_E_P_FC		0x3C3
246 #define HW_TPL_FR_MT_M_PR_T_FC		0x3B3
247 #define HW_TPL_FR_MT_M_IV_P_FC		0x38B
248 #define HW_TPL_FR_MT_M_OV_P_FC		0x387
249 #define HW_TPL_FR_MT_E_PR_T		0x370
250 #define HW_TPL_FR_MT_E_PR_P_FC		0X363
251 #define HW_TPL_FR_MT_E_T_P_FC		0X353
252 #define HW_TPL_FR_MT_PR_IV_P_FC		0X32B
253 #define HW_TPL_FR_MT_PR_OV_P_FC		0X327
254 #define HW_TPL_FR_MT_T_IV_P_FC		0X31B
255 #define HW_TPL_FR_MT_T_OV_P_FC		0X317
256 #define HW_TPL_FR_M_E_PR_FC		0X2E1
257 #define HW_TPL_FR_M_E_T_FC		0X2D1
258 #define HW_TPL_FR_M_PR_IV_FC		0X2A9
259 #define HW_TPL_FR_M_PR_OV_FC		0X2A5
260 #define HW_TPL_FR_M_T_IV_FC		0X299
261 #define HW_TPL_FR_M_T_OV_FC		0X295
262 #define HW_TPL_FR_E_PR_T_P		0X272
263 #define HW_TPL_FR_E_PR_T_FC		0X271
264 #define HW_TPL_FR_E_IV_FC		0X249
265 #define HW_TPL_FR_E_OV_FC		0X245
266 #define HW_TPL_FR_PR_T_IV_FC		0X239
267 #define HW_TPL_FR_PR_T_OV_FC		0X235
268 #define HW_TPL_FR_IV_OV_FC		0X20D
269 #define HW_TPL_MT_M_E_PR		0X1E0
270 #define HW_TPL_MT_M_E_T			0X1D0
271 #define HW_TPL_MT_E_PR_T_FC		0X171
272 #define HW_TPL_MT_E_IV			0X148
273 #define HW_TPL_MT_E_OV			0X144
274 #define HW_TPL_MT_PR_T_IV		0X138
275 #define HW_TPL_MT_PR_T_OV		0X134
276 #define HW_TPL_M_E_PR_P			0X0E2
277 #define HW_TPL_M_E_T_P			0X0D2
278 #define HW_TPL_E_PR_T_P_FC		0X073
279 #define HW_TPL_E_IV_P			0X04A
280 #define HW_TPL_E_OV_P			0X046
281 #define HW_TPL_PR_T_IV_P		0X03A
282 #define HW_TPL_PR_T_OV_P		0X036
283 
284 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
285 enum fw_filter_wr_cookie {
286 	FW_FILTER_WR_SUCCESS,
287 	FW_FILTER_WR_FLT_ADDED,
288 	FW_FILTER_WR_FLT_DELETED,
289 	FW_FILTER_WR_SMT_TBL_FULL,
290 	FW_FILTER_WR_EINVAL,
291 };
292 
293 enum fw_filter_wr_nat_mode {
294 	FW_FILTER_WR_NATMODE_NONE = 0,
295 	FW_FILTER_WR_NATMODE_DIP ,
296 	FW_FILTER_WR_NATMODE_DIPDP,
297 	FW_FILTER_WR_NATMODE_DIPDPSIP,
298 	FW_FILTER_WR_NATMODE_DIPDPSP,
299 	FW_FILTER_WR_NATMODE_SIPSP,
300 	FW_FILTER_WR_NATMODE_DIPSIPSP,
301 	FW_FILTER_WR_NATMODE_FOURTUPLE,
302 };
303 
304 struct fw_filter_wr {
305 	__be32 op_pkd;
306 	__be32 len16_pkd;
307 	__be64 r3;
308 	__be32 tid_to_iq;
309 	__be32 del_filter_to_l2tix;
310 	__be16 ethtype;
311 	__be16 ethtypem;
312 	__u8   frag_to_ovlan_vldm;
313 	__u8   smac_sel;
314 	__be16 rx_chan_rx_rpl_iq;
315 	__be32 maci_to_matchtypem;
316 	__u8   ptcl;
317 	__u8   ptclm;
318 	__u8   ttyp;
319 	__u8   ttypm;
320 	__be16 ivlan;
321 	__be16 ivlanm;
322 	__be16 ovlan;
323 	__be16 ovlanm;
324 	__u8   lip[16];
325 	__u8   lipm[16];
326 	__u8   fip[16];
327 	__u8   fipm[16];
328 	__be16 lp;
329 	__be16 lpm;
330 	__be16 fp;
331 	__be16 fpm;
332 	__be16 r7;
333 	__u8   sma[6];
334 };
335 
336 struct fw_filter2_wr {
337 	__be32 op_pkd;
338 	__be32 len16_pkd;
339 	__be64 r3;
340 	__be32 tid_to_iq;
341 	__be32 del_filter_to_l2tix;
342 	__be16 ethtype;
343 	__be16 ethtypem;
344 	__u8   frag_to_ovlan_vldm;
345 	__u8   smac_sel;
346 	__be16 rx_chan_rx_rpl_iq;
347 	__be32 maci_to_matchtypem;
348 	__u8   ptcl;
349 	__u8   ptclm;
350 	__u8   ttyp;
351 	__u8   ttypm;
352 	__be16 ivlan;
353 	__be16 ivlanm;
354 	__be16 ovlan;
355 	__be16 ovlanm;
356 	__u8   lip[16];
357 	__u8   lipm[16];
358 	__u8   fip[16];
359 	__u8   fipm[16];
360 	__be16 lp;
361 	__be16 lpm;
362 	__be16 fp;
363 	__be16 fpm;
364 	__be16 r7;
365 	__u8   sma[6];
366 	__be16 r8;
367 	__u8   filter_type_swapmac;
368 	__u8   natmode_to_ulp_type;
369 	__be16 newlport;
370 	__be16 newfport;
371 	__u8   newlip[16];
372 	__u8   newfip[16];
373 	__be32 natseqcheck;
374 	__be32 r9;
375 	__be64 r10;
376 	__be64 r11;
377 	__be64 r12;
378 	__be64 r13;
379 };
380 
381 #define S_FW_FILTER_WR_TID	12
382 #define M_FW_FILTER_WR_TID	0xfffff
383 #define V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
384 #define G_FW_FILTER_WR_TID(x)	\
385     (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
386 
387 #define S_FW_FILTER_WR_RQTYPE		11
388 #define M_FW_FILTER_WR_RQTYPE		0x1
389 #define V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
390 #define G_FW_FILTER_WR_RQTYPE(x)	\
391     (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
392 #define F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
393 
394 #define S_FW_FILTER_WR_NOREPLY		10
395 #define M_FW_FILTER_WR_NOREPLY		0x1
396 #define V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
397 #define G_FW_FILTER_WR_NOREPLY(x)	\
398     (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
399 #define F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
400 
401 #define S_FW_FILTER_WR_IQ	0
402 #define M_FW_FILTER_WR_IQ	0x3ff
403 #define V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
404 #define G_FW_FILTER_WR_IQ(x)	\
405     (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
406 
407 #define S_FW_FILTER_WR_DEL_FILTER	31
408 #define M_FW_FILTER_WR_DEL_FILTER	0x1
409 #define V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
410 #define G_FW_FILTER_WR_DEL_FILTER(x)	\
411     (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
412 #define F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
413 
414 #define S_FW_FILTER2_WR_DROP_ENCAP	30
415 #define M_FW_FILTER2_WR_DROP_ENCAP	0x1
416 #define V_FW_FILTER2_WR_DROP_ENCAP(x)	((x) << S_FW_FILTER2_WR_DROP_ENCAP)
417 #define G_FW_FILTER2_WR_DROP_ENCAP(x)	\
418     (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)
419 #define F_FW_FILTER2_WR_DROP_ENCAP	V_FW_FILTER2_WR_DROP_ENCAP(1U)
420 
421 #define S_FW_FILTER2_WR_TX_LOOP         29
422 #define M_FW_FILTER2_WR_TX_LOOP         0x1
423 #define V_FW_FILTER2_WR_TX_LOOP(x)      ((x) << S_FW_FILTER2_WR_TX_LOOP)
424 #define G_FW_FILTER2_WR_TX_LOOP(x)      \
425 	    (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)
426 #define F_FW_FILTER2_WR_TX_LOOP         V_FW_FILTER2_WR_TX_LOOP(1U)
427 
428 #define S_FW_FILTER_WR_RPTTID		25
429 #define M_FW_FILTER_WR_RPTTID		0x1
430 #define V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
431 #define G_FW_FILTER_WR_RPTTID(x)	\
432     (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
433 #define F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
434 
435 #define S_FW_FILTER_WR_DROP	24
436 #define M_FW_FILTER_WR_DROP	0x1
437 #define V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
438 #define G_FW_FILTER_WR_DROP(x)	\
439     (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
440 #define F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
441 
442 #define S_FW_FILTER_WR_DIRSTEER		23
443 #define M_FW_FILTER_WR_DIRSTEER		0x1
444 #define V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
445 #define G_FW_FILTER_WR_DIRSTEER(x)	\
446     (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
447 #define F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
448 
449 #define S_FW_FILTER_WR_MASKHASH		22
450 #define M_FW_FILTER_WR_MASKHASH		0x1
451 #define V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
452 #define G_FW_FILTER_WR_MASKHASH(x)	\
453     (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
454 #define F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
455 
456 #define S_FW_FILTER_WR_DIRSTEERHASH	21
457 #define M_FW_FILTER_WR_DIRSTEERHASH	0x1
458 #define V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
459 #define G_FW_FILTER_WR_DIRSTEERHASH(x)	\
460     (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
461 #define F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
462 
463 #define S_FW_FILTER_WR_LPBK	20
464 #define M_FW_FILTER_WR_LPBK	0x1
465 #define V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
466 #define G_FW_FILTER_WR_LPBK(x)	\
467     (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
468 #define F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
469 
470 #define S_FW_FILTER_WR_DMAC	19
471 #define M_FW_FILTER_WR_DMAC	0x1
472 #define V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
473 #define G_FW_FILTER_WR_DMAC(x)	\
474     (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
475 #define F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
476 
477 #define S_FW_FILTER_WR_SMAC	18
478 #define M_FW_FILTER_WR_SMAC	0x1
479 #define V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
480 #define G_FW_FILTER_WR_SMAC(x)	\
481     (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
482 #define F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
483 
484 #define S_FW_FILTER_WR_INSVLAN		17
485 #define M_FW_FILTER_WR_INSVLAN		0x1
486 #define V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
487 #define G_FW_FILTER_WR_INSVLAN(x)	\
488     (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
489 #define F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
490 
491 #define S_FW_FILTER_WR_RMVLAN		16
492 #define M_FW_FILTER_WR_RMVLAN		0x1
493 #define V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
494 #define G_FW_FILTER_WR_RMVLAN(x)	\
495     (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
496 #define F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
497 
498 #define S_FW_FILTER_WR_HITCNTS		15
499 #define M_FW_FILTER_WR_HITCNTS		0x1
500 #define V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
501 #define G_FW_FILTER_WR_HITCNTS(x)	\
502     (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
503 #define F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
504 
505 #define S_FW_FILTER_WR_TXCHAN		13
506 #define M_FW_FILTER_WR_TXCHAN		0x3
507 #define V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
508 #define G_FW_FILTER_WR_TXCHAN(x)	\
509     (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
510 
511 #define S_FW_FILTER_WR_PRIO	12
512 #define M_FW_FILTER_WR_PRIO	0x1
513 #define V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
514 #define G_FW_FILTER_WR_PRIO(x)	\
515     (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
516 #define F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
517 
518 #define S_FW_FILTER_WR_L2TIX	0
519 #define M_FW_FILTER_WR_L2TIX	0xfff
520 #define V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
521 #define G_FW_FILTER_WR_L2TIX(x)	\
522     (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
523 
524 #define S_FW_FILTER_WR_FRAG	7
525 #define M_FW_FILTER_WR_FRAG	0x1
526 #define V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
527 #define G_FW_FILTER_WR_FRAG(x)	\
528     (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
529 #define F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
530 
531 #define S_FW_FILTER_WR_FRAGM	6
532 #define M_FW_FILTER_WR_FRAGM	0x1
533 #define V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
534 #define G_FW_FILTER_WR_FRAGM(x)	\
535     (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
536 #define F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
537 
538 #define S_FW_FILTER_WR_IVLAN_VLD	5
539 #define M_FW_FILTER_WR_IVLAN_VLD	0x1
540 #define V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
541 #define G_FW_FILTER_WR_IVLAN_VLD(x)	\
542     (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
543 #define F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
544 
545 #define S_FW_FILTER_WR_OVLAN_VLD	4
546 #define M_FW_FILTER_WR_OVLAN_VLD	0x1
547 #define V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
548 #define G_FW_FILTER_WR_OVLAN_VLD(x)	\
549     (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
550 #define F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
551 
552 #define S_FW_FILTER_WR_IVLAN_VLDM	3
553 #define M_FW_FILTER_WR_IVLAN_VLDM	0x1
554 #define V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
555 #define G_FW_FILTER_WR_IVLAN_VLDM(x)	\
556     (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
557 #define F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
558 
559 #define S_FW_FILTER_WR_OVLAN_VLDM	2
560 #define M_FW_FILTER_WR_OVLAN_VLDM	0x1
561 #define V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
562 #define G_FW_FILTER_WR_OVLAN_VLDM(x)	\
563     (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
564 #define F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
565 
566 #define S_FW_FILTER_WR_RX_CHAN		15
567 #define M_FW_FILTER_WR_RX_CHAN		0x1
568 #define V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
569 #define G_FW_FILTER_WR_RX_CHAN(x)	\
570     (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
571 #define F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
572 
573 #define S_FW_FILTER_WR_RX_RPL_IQ	0
574 #define M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
575 #define V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
576 #define G_FW_FILTER_WR_RX_RPL_IQ(x)	\
577     (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
578 
579 #define S_FW_FILTER2_WR_FILTER_TYPE	1
580 #define M_FW_FILTER2_WR_FILTER_TYPE	0x1
581 #define V_FW_FILTER2_WR_FILTER_TYPE(x)	((x) << S_FW_FILTER2_WR_FILTER_TYPE)
582 #define G_FW_FILTER2_WR_FILTER_TYPE(x)	\
583     (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
584 #define F_FW_FILTER2_WR_FILTER_TYPE	V_FW_FILTER2_WR_FILTER_TYPE(1U)
585 
586 #define S_FW_FILTER2_WR_SWAPMAC		0
587 #define M_FW_FILTER2_WR_SWAPMAC		0x1
588 #define V_FW_FILTER2_WR_SWAPMAC(x)	((x) << S_FW_FILTER2_WR_SWAPMAC)
589 #define G_FW_FILTER2_WR_SWAPMAC(x)	\
590     (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
591 #define F_FW_FILTER2_WR_SWAPMAC		V_FW_FILTER2_WR_SWAPMAC(1U)
592 
593 #define S_FW_FILTER2_WR_NATMODE		5
594 #define M_FW_FILTER2_WR_NATMODE		0x7
595 #define V_FW_FILTER2_WR_NATMODE(x)	((x) << S_FW_FILTER2_WR_NATMODE)
596 #define G_FW_FILTER2_WR_NATMODE(x)	\
597     (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
598 
599 #define S_FW_FILTER2_WR_NATFLAGCHECK	4
600 #define M_FW_FILTER2_WR_NATFLAGCHECK	0x1
601 #define V_FW_FILTER2_WR_NATFLAGCHECK(x)	((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
602 #define G_FW_FILTER2_WR_NATFLAGCHECK(x)	\
603     (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
604 #define F_FW_FILTER2_WR_NATFLAGCHECK	V_FW_FILTER2_WR_NATFLAGCHECK(1U)
605 
606 #define S_FW_FILTER2_WR_ULP_TYPE	0
607 #define M_FW_FILTER2_WR_ULP_TYPE	0xf
608 #define V_FW_FILTER2_WR_ULP_TYPE(x)	((x) << S_FW_FILTER2_WR_ULP_TYPE)
609 #define G_FW_FILTER2_WR_ULP_TYPE(x)	\
610     (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
611 
612 #define S_FW_FILTER_WR_MACI	23
613 #define M_FW_FILTER_WR_MACI	0x1ff
614 #define V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
615 #define G_FW_FILTER_WR_MACI(x)	\
616     (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
617 
618 #define S_FW_FILTER_WR_MACIM	14
619 #define M_FW_FILTER_WR_MACIM	0x1ff
620 #define V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
621 #define G_FW_FILTER_WR_MACIM(x)	\
622     (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
623 
624 #define S_FW_FILTER_WR_FCOE	13
625 #define M_FW_FILTER_WR_FCOE	0x1
626 #define V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
627 #define G_FW_FILTER_WR_FCOE(x)	\
628     (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
629 #define F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
630 
631 #define S_FW_FILTER_WR_FCOEM	12
632 #define M_FW_FILTER_WR_FCOEM	0x1
633 #define V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
634 #define G_FW_FILTER_WR_FCOEM(x)	\
635     (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
636 #define F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
637 
638 #define S_FW_FILTER_WR_PORT	9
639 #define M_FW_FILTER_WR_PORT	0x7
640 #define V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
641 #define G_FW_FILTER_WR_PORT(x)	\
642     (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
643 
644 #define S_FW_FILTER_WR_PORTM	6
645 #define M_FW_FILTER_WR_PORTM	0x7
646 #define V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
647 #define G_FW_FILTER_WR_PORTM(x)	\
648     (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
649 
650 #define S_FW_FILTER_WR_MATCHTYPE	3
651 #define M_FW_FILTER_WR_MATCHTYPE	0x7
652 #define V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
653 #define G_FW_FILTER_WR_MATCHTYPE(x)	\
654     (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
655 
656 #define S_FW_FILTER_WR_MATCHTYPEM	0
657 #define M_FW_FILTER_WR_MATCHTYPEM	0x7
658 #define V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
659 #define G_FW_FILTER_WR_MATCHTYPEM(x)	\
660     (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
661 
662 struct fw_ulptx_wr {
663 	__be32 op_to_compl;
664 	__be32 flowid_len16;
665 	__u64  cookie;
666 };
667 
668 /*	flag for packet type - control packet (0), data packet (1)
669  */
670 #define S_FW_ULPTX_WR_DATA	28
671 #define M_FW_ULPTX_WR_DATA	0x1
672 #define V_FW_ULPTX_WR_DATA(x)	((x) << S_FW_ULPTX_WR_DATA)
673 #define G_FW_ULPTX_WR_DATA(x)	\
674     (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
675 #define F_FW_ULPTX_WR_DATA	V_FW_ULPTX_WR_DATA(1U)
676 
677 struct fw_tp_wr {
678 	__be32 op_to_immdlen;
679 	__be32 flowid_len16;
680 	__u64  cookie;
681 };
682 
683 struct fw_eth_tx_pkt_wr {
684 	__be32 op_immdlen;
685 	__be32 equiq_to_len16;
686 	__be64 r3;
687 };
688 
689 #define S_FW_ETH_TX_PKT_WR_IMMDLEN	0
690 #define M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
691 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
692 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
693     (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
694 
695 struct fw_eth_tx_pkt2_wr {
696 	__be32 op_immdlen;
697 	__be32 equiq_to_len16;
698 	__be32 r3;
699 	__be32 L4ChkDisable_to_IpHdrLen;
700 };
701 
702 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
703 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
704 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
705 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
706     (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
707 
708 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
709 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
710 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
711     ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
712 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
713     (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
714      M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
715 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
716     V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
717 
718 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
719 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
720 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
721     ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
722 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
723     (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
724      M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
725 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
726     V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
727 
728 #define S_FW_ETH_TX_PKT2_WR_IVLAN	28
729 #define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
730 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
731 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
732     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
733 #define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
734 
735 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG	12
736 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG	0xffff
737 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
738 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
739     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
740 
741 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE	8
742 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE	0xf
743 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
744 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
745     (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
746 
747 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN	0
748 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN	0xff
749 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
750 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
751     (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
752 
753 struct fw_eth_tx_pkts_wr {
754 	__be32 op_pkd;
755 	__be32 equiq_to_len16;
756 	__be32 r3;
757 	__be16 plen;
758 	__u8   npkt;
759 	__u8   type;
760 };
761 
762 #define S_FW_PTP_TX_PKT_WR_IMMDLEN      0
763 #define M_FW_PTP_TX_PKT_WR_IMMDLEN      0x1ff
764 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x)   ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
765 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x)   \
766     (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
767 
768 struct fw_eth_tx_pkt_ptp_wr {
769 	__be32 op_immdlen;
770 	__be32 equiq_to_len16;
771 	__be64 r3;
772 };
773 
774 enum fw_eth_tx_eo_type {
775 	FW_ETH_TX_EO_TYPE_UDPSEG,
776 	FW_ETH_TX_EO_TYPE_TCPSEG,
777 	FW_ETH_TX_EO_TYPE_NVGRESEG,
778 	FW_ETH_TX_EO_TYPE_VXLANSEG,
779 	FW_ETH_TX_EO_TYPE_GENEVESEG,
780 };
781 
782 struct fw_eth_tx_eo_wr {
783 	__be32 op_immdlen;
784 	__be32 equiq_to_len16;
785 	__be64 r3;
786 	union fw_eth_tx_eo {
787 		struct fw_eth_tx_eo_udpseg {
788 			__u8   type;
789 			__u8   ethlen;
790 			__be16 iplen;
791 			__u8   udplen;
792 			__u8   rtplen;
793 			__be16 r4;
794 			__be16 mss;
795 			__be16 schedpktsize;
796 			__be32 plen;
797 		} udpseg;
798 		struct fw_eth_tx_eo_tcpseg {
799 			__u8   type;
800 			__u8   ethlen;
801 			__be16 iplen;
802 			__u8   tcplen;
803 			__u8   tsclk_tsoff;
804 			__be16 r4;
805 			__be16 mss;
806 			__be16 r5;
807 			__be32 plen;
808 		} tcpseg;
809 		struct fw_eth_tx_eo_nvgreseg {
810 			__u8   type;
811 			__u8   iphdroffout;
812 			__be16 grehdroff;
813 			__be16 iphdroffin;
814 			__be16 tcphdroffin;
815 			__be16 mss;
816 			__be16 r4;
817 			__be32 plen;
818 		} nvgreseg;
819 		struct fw_eth_tx_eo_vxlanseg {
820 			__u8   type;
821 			__u8   iphdroffout;
822 			__be16 vxlanhdroff;
823 			__be16 iphdroffin;
824 			__be16 tcphdroffin;
825 			__be16 mss;
826 			__be16 r4;
827 			__be32 plen;
828 
829 		} vxlanseg;
830 		struct fw_eth_tx_eo_geneveseg {
831 			__u8   type;
832 			__u8   iphdroffout;
833 			__be16 genevehdroff;
834 			__be16 iphdroffin;
835 			__be16 tcphdroffin;
836 			__be16 mss;
837 			__be16 r4;
838 			__be32 plen;
839 		} geneveseg;
840 	} u;
841 };
842 
843 #define S_FW_ETH_TX_EO_WR_IMMDLEN	0
844 #define M_FW_ETH_TX_EO_WR_IMMDLEN	0x1ff
845 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
846 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x)	\
847     (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
848 
849 #define S_FW_ETH_TX_EO_WR_TSCLK		6
850 #define M_FW_ETH_TX_EO_WR_TSCLK		0x3
851 #define V_FW_ETH_TX_EO_WR_TSCLK(x)	((x) << S_FW_ETH_TX_EO_WR_TSCLK)
852 #define G_FW_ETH_TX_EO_WR_TSCLK(x)	\
853     (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
854 
855 #define S_FW_ETH_TX_EO_WR_TSOFF		0
856 #define M_FW_ETH_TX_EO_WR_TSOFF		0x3f
857 #define V_FW_ETH_TX_EO_WR_TSOFF(x)	((x) << S_FW_ETH_TX_EO_WR_TSOFF)
858 #define G_FW_ETH_TX_EO_WR_TSOFF(x)	\
859     (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
860 
861 struct fw_eq_flush_wr {
862 	__u8   opcode;
863 	__u8   r1[3];
864 	__be32 equiq_to_len16;
865 	__be64 r3;
866 };
867 
868 struct fw_ofld_connection_wr {
869 	__be32 op_compl;
870 	__be32 len16_pkd;
871 	__u64  cookie;
872 	__be64 r2;
873 	__be64 r3;
874 	struct fw_ofld_connection_le {
875 		__be32 version_cpl;
876 		__be32 filter;
877 		__be32 r1;
878 		__be16 lport;
879 		__be16 pport;
880 		union fw_ofld_connection_leip {
881 			struct fw_ofld_connection_le_ipv4 {
882 				__be32 pip;
883 				__be32 lip;
884 				__be64 r0;
885 				__be64 r1;
886 				__be64 r2;
887 			} ipv4;
888 			struct fw_ofld_connection_le_ipv6 {
889 				__be64 pip_hi;
890 				__be64 pip_lo;
891 				__be64 lip_hi;
892 				__be64 lip_lo;
893 			} ipv6;
894 		} u;
895 	} le;
896 	struct fw_ofld_connection_tcb {
897 		__be32 t_state_to_astid;
898 		__be16 cplrxdataack_cplpassacceptrpl;
899 		__be16 rcv_adv;
900 		__be32 rcv_nxt;
901 		__be32 tx_max;
902 		__be64 opt0;
903 		__be32 opt2;
904 		__be32 r1;
905 		__be64 r2;
906 		__be64 r3;
907 	} tcb;
908 };
909 
910 #define S_FW_OFLD_CONNECTION_WR_VERSION		31
911 #define M_FW_OFLD_CONNECTION_WR_VERSION		0x1
912 #define V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
913     ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
914 #define G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
915     (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
916      M_FW_OFLD_CONNECTION_WR_VERSION)
917 #define F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
918 
919 #define S_FW_OFLD_CONNECTION_WR_CPL	30
920 #define M_FW_OFLD_CONNECTION_WR_CPL	0x1
921 #define V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
922 #define G_FW_OFLD_CONNECTION_WR_CPL(x)	\
923     (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
924 #define F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
925 
926 #define S_FW_OFLD_CONNECTION_WR_T_STATE		28
927 #define M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
928 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
929     ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
930 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
931     (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
932      M_FW_OFLD_CONNECTION_WR_T_STATE)
933 
934 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
935 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
936 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
937     ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
938 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
939     (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
940      M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
941 
942 #define S_FW_OFLD_CONNECTION_WR_ASTID		0
943 #define M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
944 #define V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
945     ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
946 #define G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
947     (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
948 
949 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
950 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
951 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
952     ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
953 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
954     (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
955      M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
956 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
957     V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
958 
959 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
960 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
961 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
962     ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
963 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
964     (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
965      M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
966 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
967     V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
968 
969 enum fw_flowc_mnem_tcpstate {
970 	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0, /* illegal */
971 	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1, /* illegal */
972 	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2, /* illegal */
973 	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
974 	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
975 	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
976 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6, /* haven't gotten ACK for FIN and
977 					      * will resend FIN - equiv ESTAB
978 					      */
979 	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7, /* haven't gotten ACK for FIN and
980 					      * will resend FIN but have
981 					      * received FIN
982 					      */
983 	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8, /* haven't gotten ACK for FIN and
984 					      * will resend FIN but have
985 					      * received FIN
986 					      */
987 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9, /* sent FIN and got FIN + ACK,
988 					      * waiting for FIN
989 					      */
990 	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10, /* not expected */
991 };
992 
993 enum fw_flowc_mnem_eostate {
994 	FW_FLOWC_MNEM_EOSTATE_CLOSED	= 0, /* illegal */
995 	FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
996 	FW_FLOWC_MNEM_EOSTATE_CLOSING	= 2, /* graceful close, after sending
997 					      * outstanding payload
998 					      */
999 	FW_FLOWC_MNEM_EOSTATE_ABORTING	= 3, /* immediate close, after
1000 					      * discarding outstanding payload
1001 					      */
1002 };
1003 
1004 enum fw_flowc_mnem {
1005 	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
1006 	FW_FLOWC_MNEM_CH		= 1,
1007 	FW_FLOWC_MNEM_PORT		= 2,
1008 	FW_FLOWC_MNEM_IQID		= 3,
1009 	FW_FLOWC_MNEM_SNDNXT		= 4,
1010 	FW_FLOWC_MNEM_RCVNXT		= 5,
1011 	FW_FLOWC_MNEM_SNDBUF		= 6,
1012 	FW_FLOWC_MNEM_MSS		= 7,
1013 	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
1014 	FW_FLOWC_MNEM_TCPSTATE		= 9,
1015 	FW_FLOWC_MNEM_EOSTATE		= 10,
1016 	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
1017 	FW_FLOWC_MNEM_DCBPRIO		= 12,
1018 	FW_FLOWC_MNEM_SND_SCALE		= 13,
1019 	FW_FLOWC_MNEM_RCV_SCALE		= 14,
1020 	FW_FLOWC_MNEM_ULP_MODE		= 15,
1021 	FW_FLOWC_MNEM_MAX		= 16,
1022 };
1023 
1024 struct fw_flowc_mnemval {
1025 	__u8   mnemonic;
1026 	__u8   r4[3];
1027 	__be32 val;
1028 };
1029 
1030 struct fw_flowc_wr {
1031 	__be32 op_to_nparams;
1032 	__be32 flowid_len16;
1033 #ifndef C99_NOT_SUPPORTED
1034 	struct fw_flowc_mnemval mnemval[0];
1035 #endif
1036 };
1037 
1038 #define S_FW_FLOWC_WR_NPARAMS		0
1039 #define M_FW_FLOWC_WR_NPARAMS		0xff
1040 #define V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
1041 #define G_FW_FLOWC_WR_NPARAMS(x)	\
1042     (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1043 
1044 struct fw_ofld_tx_data_wr {
1045 	__be32 op_to_immdlen;
1046 	__be32 flowid_len16;
1047 	__be32 plen;
1048 	__be32 lsodisable_to_flags;
1049 };
1050 
1051 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE		31
1052 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE		0x1
1053 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
1054     ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1055 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
1056     (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1057      M_FW_OFLD_TX_DATA_WR_LSODISABLE)
1058 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE	V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1059 
1060 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD		30
1061 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD		0x1
1062 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
1063     ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1064 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
1065     (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1066 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD	V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1067 
1068 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	29
1069 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	0x1
1070 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
1071     ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1072 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
1073     (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1074      M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1075 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	\
1076     V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1077 
1078 #define S_FW_OFLD_TX_DATA_WR_FLAGS	0
1079 #define M_FW_OFLD_TX_DATA_WR_FLAGS	0xfffffff
1080 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1081 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x)	\
1082     (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1083 
1084 
1085 /* Use fw_ofld_tx_data_wr structure */
1086 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI		10
1087 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI		0x3fffff
1088 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
1089     ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1090 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
1091     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1092 
1093 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	9
1094 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	0x1
1095 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
1096     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1097 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
1098     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1099      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1100 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	\
1101     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1102 
1103 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	8
1104 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	0x1
1105 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1106     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1107 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1108     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1109      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1110 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	\
1111     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1112 
1113 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC		7
1114 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC		0x1
1115 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1116     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1117 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1118     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1119      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1120 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC	\
1121     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1122 
1123 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC		6
1124 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC		0x1
1125 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1126     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1127 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1128     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1129      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1130 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC	\
1131     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1132 
1133 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO		0
1134 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO		0x3f
1135 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1136     ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1137 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1138     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1139 
1140 struct fw_cmd_wr {
1141 	__be32 op_dma;
1142 	__be32 len16_pkd;
1143 	__be64 cookie_daddr;
1144 };
1145 
1146 #define S_FW_CMD_WR_DMA		17
1147 #define M_FW_CMD_WR_DMA		0x1
1148 #define V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
1149 #define G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1150 #define F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
1151 
1152 struct fw_eth_tx_pkt_vm_wr {
1153 	__be32 op_immdlen;
1154 	__be32 equiq_to_len16;
1155 	__be32 r3[2];
1156 	__u8   ethmacdst[6];
1157 	__u8   ethmacsrc[6];
1158 	__be16 ethtype;
1159 	__be16 vlantci;
1160 };
1161 
1162 struct fw_eth_tx_pkts_vm_wr {
1163 	__be32 op_pkd;
1164 	__be32 equiq_to_len16;
1165 	__be32 r3;
1166 	__be16 plen;
1167 	__u8   npkt;
1168 	__u8   r4;
1169 	__u8   ethmacdst[6];
1170 	__u8   ethmacsrc[6];
1171 	__be16 ethtype;
1172 	__be16 vlantci;
1173 };
1174 
1175 /******************************************************************************
1176  *   R I   W O R K   R E Q U E S T s
1177  **************************************/
1178 
1179 enum fw_ri_wr_opcode {
1180 	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
1181 	FW_RI_READ_REQ			= 0x1,
1182 	FW_RI_READ_RESP			= 0x2,
1183 	FW_RI_SEND			= 0x3,
1184 	FW_RI_SEND_WITH_INV		= 0x4,
1185 	FW_RI_SEND_WITH_SE		= 0x5,
1186 	FW_RI_SEND_WITH_SE_INV		= 0x6,
1187 	FW_RI_TERMINATE			= 0x7,
1188 	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
1189 	FW_RI_BIND_MW			= 0x9,
1190 	FW_RI_FAST_REGISTER		= 0xa,
1191 	FW_RI_LOCAL_INV			= 0xb,
1192 	FW_RI_QP_MODIFY			= 0xc,
1193 	FW_RI_BYPASS			= 0xd,
1194 	FW_RI_RECEIVE			= 0xe,
1195 #if 0
1196 	FW_RI_SEND_IMMEDIATE		= 0x8,
1197 	FW_RI_SEND_IMMEDIATE_WITH_SE	= 0x9,
1198 	FW_RI_ATOMIC_REQUEST		= 0xa,
1199 	FW_RI_ATOMIC_RESPONSE		= 0xb,
1200 
1201 	FW_RI_BIND_MW			= 0xc, /* CHELSIO RI specific ... */
1202 	FW_RI_FAST_REGISTER		= 0xd,
1203 	FW_RI_LOCAL_INV			= 0xe,
1204 #endif
1205 	FW_RI_SGE_EC_CR_RETURN		= 0xf,
1206 	FW_RI_WRITE_IMMEDIATE	= FW_RI_RDMA_INIT,
1207 };
1208 
1209 enum fw_ri_wr_flags {
1210 	FW_RI_COMPLETION_FLAG		= 0x01,
1211 	FW_RI_NOTIFICATION_FLAG		= 0x02,
1212 	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
1213 	FW_RI_READ_FENCE_FLAG		= 0x08,
1214 	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
1215 	FW_RI_RDMA_READ_INVALIDATE	= 0x20,
1216 	FW_RI_RDMA_WRITE_WITH_IMMEDIATE	= 0x40
1217 };
1218 
1219 enum fw_ri_mpa_attrs {
1220 	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
1221 	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
1222 	FW_RI_MPA_CRC_ENABLE		= 0x04,
1223 	FW_RI_MPA_IETF_ENABLE		= 0x08
1224 };
1225 
1226 enum fw_ri_qp_caps {
1227 	FW_RI_QP_RDMA_READ_ENABLE	= 0x01,
1228 	FW_RI_QP_RDMA_WRITE_ENABLE	= 0x02,
1229 	FW_RI_QP_BIND_ENABLE		= 0x04,
1230 	FW_RI_QP_FAST_REGISTER_ENABLE	= 0x08,
1231 	FW_RI_QP_STAG0_ENABLE		= 0x10,
1232 	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1233 };
1234 
1235 enum fw_ri_addr_type {
1236 	FW_RI_ZERO_BASED_TO		= 0x00,
1237 	FW_RI_VA_BASED_TO		= 0x01
1238 };
1239 
1240 enum fw_ri_mem_perms {
1241 	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
1242 	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
1243 	FW_RI_MEM_ACCESS_REM		= 0x03,
1244 	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
1245 	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
1246 	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
1247 };
1248 
1249 enum fw_ri_stag_type {
1250 	FW_RI_STAG_NSMR			= 0x00,
1251 	FW_RI_STAG_SMR			= 0x01,
1252 	FW_RI_STAG_MW			= 0x02,
1253 	FW_RI_STAG_MW_RELAXED		= 0x03
1254 };
1255 
1256 enum fw_ri_data_op {
1257 	FW_RI_DATA_IMMD			= 0x81,
1258 	FW_RI_DATA_DSGL			= 0x82,
1259 	FW_RI_DATA_ISGL			= 0x83
1260 };
1261 
1262 enum fw_ri_sgl_depth {
1263 	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
1264 	FW_RI_SGL_DEPTH_MAX_RQ		= 4
1265 };
1266 
1267 enum fw_ri_cqe_err {
1268 	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
1269 	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
1270 	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
1271 	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
1272 	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
1273 	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
1274 	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
1275 	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1276 	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1277 	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
1278 	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1279 	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B, /* pbl address out of bound : software error */
1280 	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
1281 	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
1282 	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
1283 	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
1284 	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
1285 	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
1286 	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
1287 	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
1288 	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
1289 	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
1290 	FW_RI_CQE_ERR_MO		= 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1291 	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
1292 	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
1293 	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
1294 	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E, /*  RQE address out of bound : software error */
1295 	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F  /* internel error (opcode mismatch) */
1296 
1297 };
1298 
1299 struct fw_ri_dsge_pair {
1300 	__be32	len[2];
1301 	__be64	addr[2];
1302 };
1303 
1304 struct fw_ri_dsgl {
1305 	__u8	op;
1306 	__u8	r1;
1307 	__be16	nsge;
1308 	__be32	len0;
1309 	__be64	addr0;
1310 #ifndef C99_NOT_SUPPORTED
1311 	struct fw_ri_dsge_pair sge[0];
1312 #endif
1313 };
1314 
1315 struct fw_ri_sge {
1316 	__be32 stag;
1317 	__be32 len;
1318 	__be64 to;
1319 };
1320 
1321 struct fw_ri_isgl {
1322 	__u8	op;
1323 	__u8	r1;
1324 	__be16	nsge;
1325 	__be32	r2;
1326 #ifndef C99_NOT_SUPPORTED
1327 	struct fw_ri_sge sge[0];
1328 #endif
1329 };
1330 
1331 struct fw_ri_immd {
1332 	__u8	op;
1333 	__u8	r1;
1334 	__be16	r2;
1335 	__be32	immdlen;
1336 #ifndef C99_NOT_SUPPORTED
1337 	__u8	data[0];
1338 #endif
1339 };
1340 
1341 struct fw_ri_tpte {
1342 	__be32 valid_to_pdid;
1343 	__be32 locread_to_qpid;
1344 	__be32 nosnoop_pbladdr;
1345 	__be32 len_lo;
1346 	__be32 va_hi;
1347 	__be32 va_lo_fbo;
1348 	__be32 dca_mwbcnt_pstag;
1349 	__be32 len_hi;
1350 };
1351 
1352 #define S_FW_RI_TPTE_VALID		31
1353 #define M_FW_RI_TPTE_VALID		0x1
1354 #define V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
1355 #define G_FW_RI_TPTE_VALID(x)		\
1356     (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1357 #define F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
1358 
1359 #define S_FW_RI_TPTE_STAGKEY		23
1360 #define M_FW_RI_TPTE_STAGKEY		0xff
1361 #define V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
1362 #define G_FW_RI_TPTE_STAGKEY(x)		\
1363     (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1364 
1365 #define S_FW_RI_TPTE_STAGSTATE		22
1366 #define M_FW_RI_TPTE_STAGSTATE		0x1
1367 #define V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
1368 #define G_FW_RI_TPTE_STAGSTATE(x)	\
1369     (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1370 #define F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
1371 
1372 #define S_FW_RI_TPTE_STAGTYPE		20
1373 #define M_FW_RI_TPTE_STAGTYPE		0x3
1374 #define V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
1375 #define G_FW_RI_TPTE_STAGTYPE(x)	\
1376     (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1377 
1378 #define S_FW_RI_TPTE_PDID		0
1379 #define M_FW_RI_TPTE_PDID		0xfffff
1380 #define V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
1381 #define G_FW_RI_TPTE_PDID(x)		\
1382     (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1383 
1384 #define S_FW_RI_TPTE_PERM		28
1385 #define M_FW_RI_TPTE_PERM		0xf
1386 #define V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
1387 #define G_FW_RI_TPTE_PERM(x)		\
1388     (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1389 
1390 #define S_FW_RI_TPTE_REMINVDIS		27
1391 #define M_FW_RI_TPTE_REMINVDIS		0x1
1392 #define V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
1393 #define G_FW_RI_TPTE_REMINVDIS(x)	\
1394     (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1395 #define F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
1396 
1397 #define S_FW_RI_TPTE_ADDRTYPE		26
1398 #define M_FW_RI_TPTE_ADDRTYPE		1
1399 #define V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
1400 #define G_FW_RI_TPTE_ADDRTYPE(x)	\
1401     (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1402 #define F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
1403 
1404 #define S_FW_RI_TPTE_MWBINDEN		25
1405 #define M_FW_RI_TPTE_MWBINDEN		0x1
1406 #define V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
1407 #define G_FW_RI_TPTE_MWBINDEN(x)	\
1408     (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1409 #define F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
1410 
1411 #define S_FW_RI_TPTE_PS			20
1412 #define M_FW_RI_TPTE_PS			0x1f
1413 #define V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
1414 #define G_FW_RI_TPTE_PS(x)		\
1415     (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1416 
1417 #define S_FW_RI_TPTE_QPID		0
1418 #define M_FW_RI_TPTE_QPID		0xfffff
1419 #define V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
1420 #define G_FW_RI_TPTE_QPID(x)		\
1421     (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1422 
1423 #define S_FW_RI_TPTE_NOSNOOP		31
1424 #define M_FW_RI_TPTE_NOSNOOP		0x1
1425 #define V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
1426 #define G_FW_RI_TPTE_NOSNOOP(x)		\
1427     (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1428 #define F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
1429 
1430 #define S_FW_RI_TPTE_PBLADDR		0
1431 #define M_FW_RI_TPTE_PBLADDR		0x1fffffff
1432 #define V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
1433 #define G_FW_RI_TPTE_PBLADDR(x)		\
1434     (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1435 
1436 #define S_FW_RI_TPTE_DCA		24
1437 #define M_FW_RI_TPTE_DCA		0x1f
1438 #define V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
1439 #define G_FW_RI_TPTE_DCA(x)		\
1440     (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1441 
1442 #define S_FW_RI_TPTE_MWBCNT_PSTAG	0
1443 #define M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
1444 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
1445     ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1446 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
1447     (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1448 
1449 enum fw_ri_cqe_rxtx {
1450 	FW_RI_CQE_RXTX_RX = 0x0,
1451 	FW_RI_CQE_RXTX_TX = 0x1,
1452 };
1453 
1454 struct fw_ri_cqe {
1455 	union fw_ri_rxtx {
1456 		struct fw_ri_scqe {
1457 		__be32	qpid_n_stat_rxtx_type;
1458 		__be32	plen;
1459 		__be32	stag;
1460 		__be32	wrid;
1461 		} scqe;
1462 		struct fw_ri_rcqe {
1463 		__be32	qpid_n_stat_rxtx_type;
1464 		__be32	plen;
1465 		__be32	stag;
1466 		__be32	msn;
1467 		} rcqe;
1468 		struct fw_ri_rcqe_imm {
1469 		__be32	qpid_n_stat_rxtx_type;
1470 		__be32	plen;
1471 		__be32	mo;
1472 		__be32	msn;
1473 		__u64	imm_data;
1474 		} imm_data_rcqe;
1475 	} u;
1476 };
1477 
1478 #define S_FW_RI_CQE_QPID      12
1479 #define M_FW_RI_CQE_QPID      0xfffff
1480 #define V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
1481 #define G_FW_RI_CQE_QPID(x)   \
1482     (((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
1483 
1484 #define S_FW_RI_CQE_NOTIFY    10
1485 #define M_FW_RI_CQE_NOTIFY    0x1
1486 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1487 #define G_FW_RI_CQE_NOTIFY(x) \
1488     (((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
1489 
1490 #define S_FW_RI_CQE_STATUS    5
1491 #define M_FW_RI_CQE_STATUS    0x1f
1492 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1493 #define G_FW_RI_CQE_STATUS(x) \
1494     (((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
1495 
1496 
1497 #define S_FW_RI_CQE_RXTX      4
1498 #define M_FW_RI_CQE_RXTX      0x1
1499 #define V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
1500 #define G_FW_RI_CQE_RXTX(x)   \
1501     (((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
1502 
1503 #define S_FW_RI_CQE_TYPE      0
1504 #define M_FW_RI_CQE_TYPE      0xf
1505 #define V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
1506 #define G_FW_RI_CQE_TYPE(x)   \
1507     (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
1508 
1509 enum fw_ri_res_type {
1510 	FW_RI_RES_TYPE_SQ,
1511 	FW_RI_RES_TYPE_RQ,
1512 	FW_RI_RES_TYPE_CQ,
1513 	FW_RI_RES_TYPE_SRQ,
1514 };
1515 
1516 enum fw_ri_res_op {
1517 	FW_RI_RES_OP_WRITE,
1518 	FW_RI_RES_OP_RESET,
1519 };
1520 
1521 struct fw_ri_res {
1522 	union fw_ri_restype {
1523 		struct fw_ri_res_sqrq {
1524 			__u8   restype;
1525 			__u8   op;
1526 			__be16 r3;
1527 			__be32 eqid;
1528 			__be32 r4[2];
1529 			__be32 fetchszm_to_iqid;
1530 			__be32 dcaen_to_eqsize;
1531 			__be64 eqaddr;
1532 		} sqrq;
1533 		struct fw_ri_res_cq {
1534 			__u8   restype;
1535 			__u8   op;
1536 			__be16 r3;
1537 			__be32 iqid;
1538 			__be32 r4[2];
1539 			__be32 iqandst_to_iqandstindex;
1540 			__be16 iqdroprss_to_iqesize;
1541 			__be16 iqsize;
1542 			__be64 iqaddr;
1543 			__be32 iqns_iqro;
1544 			__be32 r6_lo;
1545 			__be64 r7;
1546 		} cq;
1547 		struct fw_ri_res_srq {
1548 			__u8   restype;
1549 			__u8   op;
1550 			__be16 r3;
1551 			__be32 eqid;
1552 			__be32 r4[2];
1553 			__be32 fetchszm_to_iqid;
1554 			__be32 dcaen_to_eqsize;
1555 			__be64 eqaddr;
1556 			__be32 srqid;
1557 			__be32 pdid;
1558 			__be32 hwsrqsize;
1559 			__be32 hwsrqaddr;
1560 		} srq;
1561 	} u;
1562 };
1563 
1564 struct fw_ri_res_wr {
1565 	__be32 op_nres;
1566 	__be32 len16_pkd;
1567 	__u64  cookie;
1568 #ifndef C99_NOT_SUPPORTED
1569 	struct fw_ri_res res[0];
1570 #endif
1571 };
1572 
1573 #define S_FW_RI_RES_WR_VFN		8
1574 #define M_FW_RI_RES_WR_VFN		0xff
1575 #define V_FW_RI_RES_WR_VFN(x)		((x) << S_FW_RI_RES_WR_VFN)
1576 #define G_FW_RI_RES_WR_VFN(x)		\
1577     (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1578 
1579 #define S_FW_RI_RES_WR_NRES	0
1580 #define M_FW_RI_RES_WR_NRES	0xff
1581 #define V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
1582 #define G_FW_RI_RES_WR_NRES(x)	\
1583     (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1584 
1585 #define S_FW_RI_RES_WR_FETCHSZM		26
1586 #define M_FW_RI_RES_WR_FETCHSZM		0x1
1587 #define V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
1588 #define G_FW_RI_RES_WR_FETCHSZM(x)	\
1589     (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1590 #define F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
1591 
1592 #define S_FW_RI_RES_WR_STATUSPGNS	25
1593 #define M_FW_RI_RES_WR_STATUSPGNS	0x1
1594 #define V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
1595 #define G_FW_RI_RES_WR_STATUSPGNS(x)	\
1596     (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1597 #define F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
1598 
1599 #define S_FW_RI_RES_WR_STATUSPGRO	24
1600 #define M_FW_RI_RES_WR_STATUSPGRO	0x1
1601 #define V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
1602 #define G_FW_RI_RES_WR_STATUSPGRO(x)	\
1603     (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1604 #define F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
1605 
1606 #define S_FW_RI_RES_WR_FETCHNS		23
1607 #define M_FW_RI_RES_WR_FETCHNS		0x1
1608 #define V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
1609 #define G_FW_RI_RES_WR_FETCHNS(x)	\
1610     (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1611 #define F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
1612 
1613 #define S_FW_RI_RES_WR_FETCHRO		22
1614 #define M_FW_RI_RES_WR_FETCHRO		0x1
1615 #define V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
1616 #define G_FW_RI_RES_WR_FETCHRO(x)	\
1617     (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1618 #define F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
1619 
1620 #define S_FW_RI_RES_WR_HOSTFCMODE	20
1621 #define M_FW_RI_RES_WR_HOSTFCMODE	0x3
1622 #define V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1623 #define G_FW_RI_RES_WR_HOSTFCMODE(x)	\
1624     (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1625 
1626 #define S_FW_RI_RES_WR_CPRIO	19
1627 #define M_FW_RI_RES_WR_CPRIO	0x1
1628 #define V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
1629 #define G_FW_RI_RES_WR_CPRIO(x)	\
1630     (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1631 #define F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
1632 
1633 #define S_FW_RI_RES_WR_ONCHIP		18
1634 #define M_FW_RI_RES_WR_ONCHIP		0x1
1635 #define V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
1636 #define G_FW_RI_RES_WR_ONCHIP(x)	\
1637     (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1638 #define F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
1639 
1640 #define S_FW_RI_RES_WR_PCIECHN		16
1641 #define M_FW_RI_RES_WR_PCIECHN		0x3
1642 #define V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
1643 #define G_FW_RI_RES_WR_PCIECHN(x)	\
1644     (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1645 
1646 #define S_FW_RI_RES_WR_IQID	0
1647 #define M_FW_RI_RES_WR_IQID	0xffff
1648 #define V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
1649 #define G_FW_RI_RES_WR_IQID(x)	\
1650     (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1651 
1652 #define S_FW_RI_RES_WR_DCAEN	31
1653 #define M_FW_RI_RES_WR_DCAEN	0x1
1654 #define V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
1655 #define G_FW_RI_RES_WR_DCAEN(x)	\
1656     (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1657 #define F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
1658 
1659 #define S_FW_RI_RES_WR_DCACPU		26
1660 #define M_FW_RI_RES_WR_DCACPU		0x1f
1661 #define V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
1662 #define G_FW_RI_RES_WR_DCACPU(x)	\
1663     (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1664 
1665 #define S_FW_RI_RES_WR_FBMIN	23
1666 #define M_FW_RI_RES_WR_FBMIN	0x7
1667 #define V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
1668 #define G_FW_RI_RES_WR_FBMIN(x)	\
1669     (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1670 
1671 #define S_FW_RI_RES_WR_FBMAX	20
1672 #define M_FW_RI_RES_WR_FBMAX	0x7
1673 #define V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
1674 #define G_FW_RI_RES_WR_FBMAX(x)	\
1675     (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1676 
1677 #define S_FW_RI_RES_WR_CIDXFTHRESHO	19
1678 #define M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
1679 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1680 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
1681     (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1682 #define F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1683 
1684 #define S_FW_RI_RES_WR_CIDXFTHRESH	16
1685 #define M_FW_RI_RES_WR_CIDXFTHRESH	0x7
1686 #define V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1687 #define G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
1688     (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1689 
1690 #define S_FW_RI_RES_WR_EQSIZE		0
1691 #define M_FW_RI_RES_WR_EQSIZE		0xffff
1692 #define V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
1693 #define G_FW_RI_RES_WR_EQSIZE(x)	\
1694     (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1695 
1696 #define S_FW_RI_RES_WR_IQANDST		15
1697 #define M_FW_RI_RES_WR_IQANDST		0x1
1698 #define V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
1699 #define G_FW_RI_RES_WR_IQANDST(x)	\
1700     (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1701 #define F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
1702 
1703 #define S_FW_RI_RES_WR_IQANUS		14
1704 #define M_FW_RI_RES_WR_IQANUS		0x1
1705 #define V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
1706 #define G_FW_RI_RES_WR_IQANUS(x)	\
1707     (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1708 #define F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
1709 
1710 #define S_FW_RI_RES_WR_IQANUD		12
1711 #define M_FW_RI_RES_WR_IQANUD		0x3
1712 #define V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
1713 #define G_FW_RI_RES_WR_IQANUD(x)	\
1714     (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1715 
1716 #define S_FW_RI_RES_WR_IQANDSTINDEX	0
1717 #define M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
1718 #define V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1719 #define G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
1720     (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1721 
1722 #define S_FW_RI_RES_WR_IQDROPRSS	15
1723 #define M_FW_RI_RES_WR_IQDROPRSS	0x1
1724 #define V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
1725 #define G_FW_RI_RES_WR_IQDROPRSS(x)	\
1726     (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1727 #define F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
1728 
1729 #define S_FW_RI_RES_WR_IQGTSMODE	14
1730 #define M_FW_RI_RES_WR_IQGTSMODE	0x1
1731 #define V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
1732 #define G_FW_RI_RES_WR_IQGTSMODE(x)	\
1733     (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1734 #define F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
1735 
1736 #define S_FW_RI_RES_WR_IQPCIECH		12
1737 #define M_FW_RI_RES_WR_IQPCIECH		0x3
1738 #define V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
1739 #define G_FW_RI_RES_WR_IQPCIECH(x)	\
1740     (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1741 
1742 #define S_FW_RI_RES_WR_IQDCAEN		11
1743 #define M_FW_RI_RES_WR_IQDCAEN		0x1
1744 #define V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
1745 #define G_FW_RI_RES_WR_IQDCAEN(x)	\
1746     (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1747 #define F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
1748 
1749 #define S_FW_RI_RES_WR_IQDCACPU		6
1750 #define M_FW_RI_RES_WR_IQDCACPU		0x1f
1751 #define V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
1752 #define G_FW_RI_RES_WR_IQDCACPU(x)	\
1753     (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1754 
1755 #define S_FW_RI_RES_WR_IQINTCNTTHRESH		4
1756 #define M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
1757 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1758     ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1759 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1760     (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1761 
1762 #define S_FW_RI_RES_WR_IQO	3
1763 #define M_FW_RI_RES_WR_IQO	0x1
1764 #define V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
1765 #define G_FW_RI_RES_WR_IQO(x)	\
1766     (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1767 #define F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
1768 
1769 #define S_FW_RI_RES_WR_IQCPRIO		2
1770 #define M_FW_RI_RES_WR_IQCPRIO		0x1
1771 #define V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
1772 #define G_FW_RI_RES_WR_IQCPRIO(x)	\
1773     (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1774 #define F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
1775 
1776 #define S_FW_RI_RES_WR_IQESIZE		0
1777 #define M_FW_RI_RES_WR_IQESIZE		0x3
1778 #define V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
1779 #define G_FW_RI_RES_WR_IQESIZE(x)	\
1780     (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1781 
1782 #define S_FW_RI_RES_WR_IQNS	31
1783 #define M_FW_RI_RES_WR_IQNS	0x1
1784 #define V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
1785 #define G_FW_RI_RES_WR_IQNS(x)	\
1786     (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1787 #define F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
1788 
1789 #define S_FW_RI_RES_WR_IQRO	30
1790 #define M_FW_RI_RES_WR_IQRO	0x1
1791 #define V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
1792 #define G_FW_RI_RES_WR_IQRO(x)	\
1793     (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1794 #define F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
1795 
1796 struct fw_ri_rdma_write_wr {
1797 	__u8   opcode;
1798 	__u8   flags;
1799 	__u16  wrid;
1800 	__u8   r1[3];
1801 	__u8   len16;
1802 	__u64  immd_data;
1803 	__be32 plen;
1804 	__be32 stag_sink;
1805 	__be64 to_sink;
1806 #ifndef C99_NOT_SUPPORTED
1807 	union {
1808 		struct fw_ri_immd immd_src[0];
1809 		struct fw_ri_isgl isgl_src[0];
1810 	} u;
1811 #endif
1812 };
1813 
1814 struct fw_ri_send_wr {
1815 	__u8   opcode;
1816 	__u8   flags;
1817 	__u16  wrid;
1818 	__u8   r1[3];
1819 	__u8   len16;
1820 	__be32 sendop_pkd;
1821 	__be32 stag_inv;
1822 	__be32 plen;
1823 	__be32 r3;
1824 	__be64 r4;
1825 #ifndef C99_NOT_SUPPORTED
1826 	union {
1827 		struct fw_ri_immd immd_src[0];
1828 		struct fw_ri_isgl isgl_src[0];
1829 	} u;
1830 #endif
1831 };
1832 
1833 #define S_FW_RI_SEND_WR_SENDOP		0
1834 #define M_FW_RI_SEND_WR_SENDOP		0xf
1835 #define V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
1836 #define G_FW_RI_SEND_WR_SENDOP(x)	\
1837     (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1838 
1839 struct fw_ri_rdma_write_cmpl_wr {
1840 	__u8   opcode;
1841 	__u8   flags;
1842 	__u16  wrid;
1843 	__u8   r1[3];
1844 	__u8   len16;
1845 	__u8   r2;
1846 	__u8   flags_send;
1847 	__u16  wrid_send;
1848 	__be32 stag_inv;
1849 	__be32 plen;
1850 	__be32 stag_sink;
1851 	__be64 to_sink;
1852 	union fw_ri_cmpl {
1853 		struct fw_ri_immd_cmpl {
1854 			__u8   op;
1855 			__u8   r1[6];
1856 			__u8   immdlen;
1857 			__u8   data[16];
1858 		} immd_src;
1859 		struct fw_ri_isgl isgl_src;
1860 	} u_cmpl;
1861 	__be64 r3;
1862 #ifndef C99_NOT_SUPPORTED
1863 	union fw_ri_write {
1864 		struct fw_ri_immd immd_src[0];
1865 		struct fw_ri_isgl isgl_src[0];
1866 	} u;
1867 #endif
1868 };
1869 
1870 struct fw_ri_rdma_read_wr {
1871 	__u8   opcode;
1872 	__u8   flags;
1873 	__u16  wrid;
1874 	__u8   r1[3];
1875 	__u8   len16;
1876 	__be64 r2;
1877 	__be32 stag_sink;
1878 	__be32 to_sink_hi;
1879 	__be32 to_sink_lo;
1880 	__be32 plen;
1881 	__be32 stag_src;
1882 	__be32 to_src_hi;
1883 	__be32 to_src_lo;
1884 	__be32 r5;
1885 };
1886 
1887 struct fw_ri_recv_wr {
1888 	__u8   opcode;
1889 	__u8   r1;
1890 	__u16  wrid;
1891 	__u8   r2[3];
1892 	__u8   len16;
1893 	struct fw_ri_isgl isgl;
1894 };
1895 
1896 struct fw_ri_bind_mw_wr {
1897 	__u8   opcode;
1898 	__u8   flags;
1899 	__u16  wrid;
1900 	__u8   r1[3];
1901 	__u8   len16;
1902 	__u8   qpbinde_to_dcacpu;
1903 	__u8   pgsz_shift;
1904 	__u8   addr_type;
1905 	__u8   mem_perms;
1906 	__be32 stag_mr;
1907 	__be32 stag_mw;
1908 	__be32 r3;
1909 	__be64 len_mw;
1910 	__be64 va_fbo;
1911 	__be64 r4;
1912 };
1913 
1914 #define S_FW_RI_BIND_MW_WR_QPBINDE	6
1915 #define M_FW_RI_BIND_MW_WR_QPBINDE	0x1
1916 #define V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1917 #define G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
1918     (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1919 #define F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1920 
1921 #define S_FW_RI_BIND_MW_WR_NS		5
1922 #define M_FW_RI_BIND_MW_WR_NS		0x1
1923 #define V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
1924 #define G_FW_RI_BIND_MW_WR_NS(x)	\
1925     (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1926 #define F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
1927 
1928 #define S_FW_RI_BIND_MW_WR_DCACPU	0
1929 #define M_FW_RI_BIND_MW_WR_DCACPU	0x1f
1930 #define V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1931 #define G_FW_RI_BIND_MW_WR_DCACPU(x)	\
1932     (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1933 
1934 struct fw_ri_fr_nsmr_wr {
1935 	__u8   opcode;
1936 	__u8   flags;
1937 	__u16  wrid;
1938 	__u8   r1[3];
1939 	__u8   len16;
1940 	__u8   qpbinde_to_dcacpu;
1941 	__u8   pgsz_shift;
1942 	__u8   addr_type;
1943 	__u8   mem_perms;
1944 	__be32 stag;
1945 	__be32 len_hi;
1946 	__be32 len_lo;
1947 	__be32 va_hi;
1948 	__be32 va_lo_fbo;
1949 };
1950 
1951 #define S_FW_RI_FR_NSMR_WR_QPBINDE	6
1952 #define M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
1953 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1954 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
1955     (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1956 #define F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1957 
1958 #define S_FW_RI_FR_NSMR_WR_NS		5
1959 #define M_FW_RI_FR_NSMR_WR_NS		0x1
1960 #define V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
1961 #define G_FW_RI_FR_NSMR_WR_NS(x)	\
1962     (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1963 #define F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
1964 
1965 #define S_FW_RI_FR_NSMR_WR_DCACPU	0
1966 #define M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
1967 #define V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1968 #define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
1969     (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1970 
1971 struct fw_ri_fr_nsmr_tpte_wr {
1972 	__u8   opcode;
1973 	__u8   flags;
1974 	__u16  wrid;
1975 	__u8   r1[3];
1976 	__u8   len16;
1977 	__be32 r2;
1978 	__be32 stag;
1979 	struct fw_ri_tpte tpte;
1980 	__be64 pbl[2];
1981 };
1982 
1983 struct fw_ri_inv_lstag_wr {
1984 	__u8   opcode;
1985 	__u8   flags;
1986 	__u16  wrid;
1987 	__u8   r1[3];
1988 	__u8   len16;
1989 	__be32 r2;
1990 	__be32 stag_inv;
1991 };
1992 
1993 struct fw_ri_send_immediate_wr {
1994 	__u8   opcode;
1995 	__u8   flags;
1996 	__u16  wrid;
1997 	__u8   r1[3];
1998 	__u8   len16;
1999 	__be32 sendimmop_pkd;
2000 	__be32 r3;
2001 	__be32 plen;
2002 	__be32 r4;
2003 	__be64 r5;
2004 #ifndef C99_NOT_SUPPORTED
2005 	struct fw_ri_immd immd_src[0];
2006 #endif
2007 };
2008 
2009 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
2010 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
2011 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
2012     ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2013 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
2014     (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
2015      M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2016 
2017 enum fw_ri_atomic_op {
2018 	FW_RI_ATOMIC_OP_FETCHADD,
2019 	FW_RI_ATOMIC_OP_SWAP,
2020 	FW_RI_ATOMIC_OP_CMDSWAP,
2021 };
2022 
2023 struct fw_ri_atomic_wr {
2024 	__u8   opcode;
2025 	__u8   flags;
2026 	__u16  wrid;
2027 	__u8   r1[3];
2028 	__u8   len16;
2029 	__be32 atomicop_pkd;
2030 	__be64 r3;
2031 	__be32 aopcode_pkd;
2032 	__be32 reqid;
2033 	__be32 stag;
2034 	__be32 to_hi;
2035 	__be32 to_lo;
2036 	__be32 addswap_data_hi;
2037 	__be32 addswap_data_lo;
2038 	__be32 addswap_mask_hi;
2039 	__be32 addswap_mask_lo;
2040 	__be32 compare_data_hi;
2041 	__be32 compare_data_lo;
2042 	__be32 compare_mask_hi;
2043 	__be32 compare_mask_lo;
2044 	__be32 r5;
2045 };
2046 
2047 #define S_FW_RI_ATOMIC_WR_ATOMICOP	0
2048 #define M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
2049 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
2050 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
2051     (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
2052 
2053 #define S_FW_RI_ATOMIC_WR_AOPCODE	0
2054 #define M_FW_RI_ATOMIC_WR_AOPCODE	0xf
2055 #define V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
2056 #define G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
2057     (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
2058 
2059 enum fw_ri_type {
2060 	FW_RI_TYPE_INIT,
2061 	FW_RI_TYPE_FINI,
2062 	FW_RI_TYPE_TERMINATE
2063 };
2064 
2065 enum fw_ri_init_p2ptype {
2066 	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
2067 	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
2068 	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
2069 	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
2070 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
2071 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
2072 	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
2073 };
2074 
2075 enum fw_ri_init_rqeqid_srq {
2076 	FW_RI_INIT_RQEQID_SRQ			= 1U << 31,
2077 };
2078 
2079 struct fw_ri_wr {
2080 	__be32 op_compl;
2081 	__be32 flowid_len16;
2082 	__u64  cookie;
2083 	union fw_ri {
2084 		struct fw_ri_init {
2085 			__u8   type;
2086 			__u8   mpareqbit_p2ptype;
2087 			__u8   r4[2];
2088 			__u8   mpa_attrs;
2089 			__u8   qp_caps;
2090 			__be16 nrqe;
2091 			__be32 pdid;
2092 			__be32 qpid;
2093 			__be32 sq_eqid;
2094 			__be32 rq_eqid;
2095 			__be32 scqid;
2096 			__be32 rcqid;
2097 			__be32 ord_max;
2098 			__be32 ird_max;
2099 			__be32 iss;
2100 			__be32 irs;
2101 			__be32 hwrqsize;
2102 			__be32 hwrqaddr;
2103 			__be64 r5;
2104 			union fw_ri_init_p2p {
2105 				struct fw_ri_rdma_write_wr write;
2106 				struct fw_ri_rdma_read_wr read;
2107 				struct fw_ri_send_wr send;
2108 			} u;
2109 		} init;
2110 		struct fw_ri_fini {
2111 			__u8   type;
2112 			__u8   r3[7];
2113 			__be64 r4;
2114 		} fini;
2115 		struct fw_ri_terminate {
2116 			__u8   type;
2117 			__u8   r3[3];
2118 			__be32 immdlen;
2119 			__u8   termmsg[40];
2120 		} terminate;
2121 	} u;
2122 };
2123 
2124 #define S_FW_RI_WR_MPAREQBIT	7
2125 #define M_FW_RI_WR_MPAREQBIT	0x1
2126 #define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
2127 #define G_FW_RI_WR_MPAREQBIT(x)	\
2128     (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2129 #define F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
2130 
2131 #define S_FW_RI_WR_0BRRBIT	6
2132 #define M_FW_RI_WR_0BRRBIT	0x1
2133 #define V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
2134 #define G_FW_RI_WR_0BRRBIT(x)	\
2135     (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2136 #define F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
2137 
2138 #define S_FW_RI_WR_P2PTYPE	0
2139 #define M_FW_RI_WR_P2PTYPE	0xf
2140 #define V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
2141 #define G_FW_RI_WR_P2PTYPE(x)	\
2142     (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2143 
2144 /******************************************************************************
2145  *  F O i S C S I   W O R K R E Q U E S T s
2146  *********************************************/
2147 
2148 #define	FW_FOISCSI_NAME_MAX_LEN		224
2149 #define	FW_FOISCSI_ALIAS_MAX_LEN	224
2150 #define FW_FOISCSI_CHAP_SEC_MAX_LEN	128
2151 #define	FW_FOISCSI_INIT_NODE_MAX	8
2152 
2153 enum fw_chnet_ifconf_wr_subop {
2154 	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
2155 
2156 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
2157 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
2158 
2159 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2160 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2161 
2162 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2163 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2164 
2165 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2166 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2167 
2168 	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2169 	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2170 
2171 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2172 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2173 
2174 	FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2175 	FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2176 
2177 	FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2178 	FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2179 	FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2180 
2181 	FW_CHNET_IFCONF_WR_SUBOP_MAX,
2182 };
2183 
2184 struct fw_chnet_ifconf_wr {
2185 	__be32 op_compl;
2186 	__be32 flowid_len16;
2187 	__be64 cookie;
2188 	__be32 if_flowid;
2189 	__u8   idx;
2190 	__u8   subop;
2191 	__u8   retval;
2192 	__u8   r2;
2193 	__be64 r3;
2194 	struct fw_chnet_ifconf_params {
2195 		__be32 r0;
2196 		__be16 vlanid;
2197 		__be16 mtu;
2198 		union fw_chnet_ifconf_addr_type {
2199 			struct fw_chnet_ifconf_ipv4 {
2200 				__be32 addr;
2201 				__be32 mask;
2202 				__be32 router;
2203 				__be32 r0;
2204 				__be64 r1;
2205 			} ipv4;
2206 			struct fw_chnet_ifconf_ipv6 {
2207 				__u8   prefix_len;
2208 				__u8   r0;
2209 				__be16 r1;
2210 				__be32 r2;
2211 				__be64 addr_hi;
2212 				__be64 addr_lo;
2213 				__be64 router_hi;
2214 				__be64 router_lo;
2215 			} ipv6;
2216 		} in_attr;
2217 	} param;
2218 };
2219 
2220 enum fw_foiscsi_node_type {
2221 	FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2222 	FW_FOISCSI_NODE_TYPE_TARGET,
2223 };
2224 
2225 enum fw_foiscsi_session_type {
2226 	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2227 	FW_FOISCSI_SESSION_TYPE_NORMAL,
2228 };
2229 
2230 enum fw_foiscsi_auth_policy {
2231 	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2232 	FW_FOISCSI_AUTH_POLICY_MUTUAL,
2233 };
2234 
2235 enum fw_foiscsi_auth_method {
2236 	FW_FOISCSI_AUTH_METHOD_NONE = 0,
2237 	FW_FOISCSI_AUTH_METHOD_CHAP,
2238 	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2239 	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2240 };
2241 
2242 enum fw_foiscsi_digest_type {
2243 	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2244 	FW_FOISCSI_DIGEST_TYPE_CRC32,
2245 	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2246 	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2247 };
2248 
2249 enum fw_foiscsi_wr_subop {
2250 	FW_FOISCSI_WR_SUBOP_ADD = 1,
2251 	FW_FOISCSI_WR_SUBOP_DEL = 2,
2252 	FW_FOISCSI_WR_SUBOP_MOD = 4,
2253 };
2254 
2255 enum fw_foiscsi_ctrl_state {
2256 	FW_FOISCSI_CTRL_STATE_FREE = 0,
2257 	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2258 	FW_FOISCSI_CTRL_STATE_FAILED,
2259 	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2260 	FW_FOISCSI_CTRL_STATE_REDIRECT,
2261 };
2262 
2263 struct fw_rdev_wr {
2264 	__be32 op_to_immdlen;
2265 	__be32 alloc_to_len16;
2266 	__be64 cookie;
2267 	__u8   protocol;
2268 	__u8   event_cause;
2269 	__u8   cur_state;
2270 	__u8   prev_state;
2271 	__be32 flags_to_assoc_flowid;
2272 	union rdev_entry {
2273 		struct fcoe_rdev_entry {
2274 			__be32 flowid;
2275 			__u8   protocol;
2276 			__u8   event_cause;
2277 			__u8   flags;
2278 			__u8   rjt_reason;
2279 			__u8   cur_login_st;
2280 			__u8   prev_login_st;
2281 			__be16 rcv_fr_sz;
2282 			__u8   rd_xfer_rdy_to_rport_type;
2283 			__u8   vft_to_qos;
2284 			__u8   org_proc_assoc_to_acc_rsp_code;
2285 			__u8   enh_disc_to_tgt;
2286 			__u8   wwnn[8];
2287 			__u8   wwpn[8];
2288 			__be16 iqid;
2289 			__u8   fc_oui[3];
2290 			__u8   r_id[3];
2291 		} fcoe_rdev;
2292 		struct iscsi_rdev_entry {
2293 			__be32 flowid;
2294 			__u8   protocol;
2295 			__u8   event_cause;
2296 			__u8   flags;
2297 			__u8   r3;
2298 			__be16 iscsi_opts;
2299 			__be16 tcp_opts;
2300 			__be16 ip_opts;
2301 			__be16 max_rcv_len;
2302 			__be16 max_snd_len;
2303 			__be16 first_brst_len;
2304 			__be16 max_brst_len;
2305 			__be16 r4;
2306 			__be16 def_time2wait;
2307 			__be16 def_time2ret;
2308 			__be16 nop_out_intrvl;
2309 			__be16 non_scsi_to;
2310 			__be16 isid;
2311 			__be16 tsid;
2312 			__be16 port;
2313 			__be16 tpgt;
2314 			__u8   r5[6];
2315 			__be16 iqid;
2316 		} iscsi_rdev;
2317 	} u;
2318 };
2319 
2320 #define S_FW_RDEV_WR_IMMDLEN	0
2321 #define M_FW_RDEV_WR_IMMDLEN	0xff
2322 #define V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
2323 #define G_FW_RDEV_WR_IMMDLEN(x)	\
2324     (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2325 
2326 #define S_FW_RDEV_WR_ALLOC	31
2327 #define M_FW_RDEV_WR_ALLOC	0x1
2328 #define V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
2329 #define G_FW_RDEV_WR_ALLOC(x)	\
2330     (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2331 #define F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
2332 
2333 #define S_FW_RDEV_WR_FREE	30
2334 #define M_FW_RDEV_WR_FREE	0x1
2335 #define V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
2336 #define G_FW_RDEV_WR_FREE(x)	\
2337     (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2338 #define F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
2339 
2340 #define S_FW_RDEV_WR_MODIFY	29
2341 #define M_FW_RDEV_WR_MODIFY	0x1
2342 #define V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
2343 #define G_FW_RDEV_WR_MODIFY(x)	\
2344     (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2345 #define F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
2346 
2347 #define S_FW_RDEV_WR_FLOWID	8
2348 #define M_FW_RDEV_WR_FLOWID	0xfffff
2349 #define V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
2350 #define G_FW_RDEV_WR_FLOWID(x)	\
2351     (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2352 
2353 #define S_FW_RDEV_WR_LEN16	0
2354 #define M_FW_RDEV_WR_LEN16	0xff
2355 #define V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
2356 #define G_FW_RDEV_WR_LEN16(x)	\
2357     (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2358 
2359 #define S_FW_RDEV_WR_FLAGS	24
2360 #define M_FW_RDEV_WR_FLAGS	0xff
2361 #define V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
2362 #define G_FW_RDEV_WR_FLAGS(x)	\
2363     (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2364 
2365 #define S_FW_RDEV_WR_GET_NEXT		20
2366 #define M_FW_RDEV_WR_GET_NEXT		0xf
2367 #define V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
2368 #define G_FW_RDEV_WR_GET_NEXT(x)	\
2369     (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2370 
2371 #define S_FW_RDEV_WR_ASSOC_FLOWID	0
2372 #define M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
2373 #define V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2374 #define G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
2375     (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2376 
2377 #define S_FW_RDEV_WR_RJT	7
2378 #define M_FW_RDEV_WR_RJT	0x1
2379 #define V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
2380 #define G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2381 #define F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
2382 
2383 #define S_FW_RDEV_WR_REASON	0
2384 #define M_FW_RDEV_WR_REASON	0x7f
2385 #define V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
2386 #define G_FW_RDEV_WR_REASON(x)	\
2387     (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2388 
2389 #define S_FW_RDEV_WR_RD_XFER_RDY	7
2390 #define M_FW_RDEV_WR_RD_XFER_RDY	0x1
2391 #define V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2392 #define G_FW_RDEV_WR_RD_XFER_RDY(x)	\
2393     (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2394 #define F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
2395 
2396 #define S_FW_RDEV_WR_WR_XFER_RDY	6
2397 #define M_FW_RDEV_WR_WR_XFER_RDY	0x1
2398 #define V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2399 #define G_FW_RDEV_WR_WR_XFER_RDY(x)	\
2400     (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2401 #define F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
2402 
2403 #define S_FW_RDEV_WR_FC_SP	5
2404 #define M_FW_RDEV_WR_FC_SP	0x1
2405 #define V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
2406 #define G_FW_RDEV_WR_FC_SP(x)	\
2407     (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2408 #define F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
2409 
2410 #define S_FW_RDEV_WR_RPORT_TYPE		0
2411 #define M_FW_RDEV_WR_RPORT_TYPE		0x1f
2412 #define V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
2413 #define G_FW_RDEV_WR_RPORT_TYPE(x)	\
2414     (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2415 
2416 #define S_FW_RDEV_WR_VFT	7
2417 #define M_FW_RDEV_WR_VFT	0x1
2418 #define V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
2419 #define G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2420 #define F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
2421 
2422 #define S_FW_RDEV_WR_NPIV	6
2423 #define M_FW_RDEV_WR_NPIV	0x1
2424 #define V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
2425 #define G_FW_RDEV_WR_NPIV(x)	\
2426     (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2427 #define F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
2428 
2429 #define S_FW_RDEV_WR_CLASS	4
2430 #define M_FW_RDEV_WR_CLASS	0x3
2431 #define V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
2432 #define G_FW_RDEV_WR_CLASS(x)	\
2433     (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2434 
2435 #define S_FW_RDEV_WR_SEQ_DEL	3
2436 #define M_FW_RDEV_WR_SEQ_DEL	0x1
2437 #define V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
2438 #define G_FW_RDEV_WR_SEQ_DEL(x)	\
2439     (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2440 #define F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
2441 
2442 #define S_FW_RDEV_WR_PRIO_PREEMP	2
2443 #define M_FW_RDEV_WR_PRIO_PREEMP	0x1
2444 #define V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2445 #define G_FW_RDEV_WR_PRIO_PREEMP(x)	\
2446     (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2447 #define F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
2448 
2449 #define S_FW_RDEV_WR_PREF	1
2450 #define M_FW_RDEV_WR_PREF	0x1
2451 #define V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
2452 #define G_FW_RDEV_WR_PREF(x)	\
2453     (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2454 #define F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
2455 
2456 #define S_FW_RDEV_WR_QOS	0
2457 #define M_FW_RDEV_WR_QOS	0x1
2458 #define V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
2459 #define G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2460 #define F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
2461 
2462 #define S_FW_RDEV_WR_ORG_PROC_ASSOC	7
2463 #define M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
2464 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2465 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
2466     (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2467 #define F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2468 
2469 #define S_FW_RDEV_WR_RSP_PROC_ASSOC	6
2470 #define M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
2471 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2472 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
2473     (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2474 #define F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2475 
2476 #define S_FW_RDEV_WR_IMAGE_PAIR		5
2477 #define M_FW_RDEV_WR_IMAGE_PAIR		0x1
2478 #define V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2479 #define G_FW_RDEV_WR_IMAGE_PAIR(x)	\
2480     (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2481 #define F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
2482 
2483 #define S_FW_RDEV_WR_ACC_RSP_CODE	0
2484 #define M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
2485 #define V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2486 #define G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
2487     (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2488 
2489 #define S_FW_RDEV_WR_ENH_DISC		7
2490 #define M_FW_RDEV_WR_ENH_DISC		0x1
2491 #define V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
2492 #define G_FW_RDEV_WR_ENH_DISC(x)	\
2493     (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2494 #define F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
2495 
2496 #define S_FW_RDEV_WR_REC	6
2497 #define M_FW_RDEV_WR_REC	0x1
2498 #define V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
2499 #define G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2500 #define F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
2501 
2502 #define S_FW_RDEV_WR_TASK_RETRY_ID	5
2503 #define M_FW_RDEV_WR_TASK_RETRY_ID	0x1
2504 #define V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2505 #define G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
2506     (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2507 #define F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2508 
2509 #define S_FW_RDEV_WR_RETRY	4
2510 #define M_FW_RDEV_WR_RETRY	0x1
2511 #define V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
2512 #define G_FW_RDEV_WR_RETRY(x)	\
2513     (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2514 #define F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
2515 
2516 #define S_FW_RDEV_WR_CONF_CMPL		3
2517 #define M_FW_RDEV_WR_CONF_CMPL		0x1
2518 #define V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
2519 #define G_FW_RDEV_WR_CONF_CMPL(x)	\
2520     (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2521 #define F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
2522 
2523 #define S_FW_RDEV_WR_DATA_OVLY		2
2524 #define M_FW_RDEV_WR_DATA_OVLY		0x1
2525 #define V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
2526 #define G_FW_RDEV_WR_DATA_OVLY(x)	\
2527     (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2528 #define F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
2529 
2530 #define S_FW_RDEV_WR_INI	1
2531 #define M_FW_RDEV_WR_INI	0x1
2532 #define V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
2533 #define G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2534 #define F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
2535 
2536 #define S_FW_RDEV_WR_TGT	0
2537 #define M_FW_RDEV_WR_TGT	0x1
2538 #define V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
2539 #define G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2540 #define F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
2541 
2542 struct fw_foiscsi_node_wr {
2543 	__be32 op_to_immdlen;
2544 	__be32 flowid_len16;
2545 	__u64  cookie;
2546 	__u8   subop;
2547 	__u8   status;
2548 	__u8   alias_len;
2549 	__u8   iqn_len;
2550 	__be32 node_flowid;
2551 	__be16 nodeid;
2552 	__be16 login_retry;
2553 	__be16 retry_timeout;
2554 	__be16 r3;
2555 	__u8   iqn[224];
2556 	__u8   alias[224];
2557 };
2558 
2559 #define S_FW_FOISCSI_NODE_WR_IMMDLEN	0
2560 #define M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
2561 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2562 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
2563     (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2564 
2565 struct fw_foiscsi_ctrl_wr {
2566 	__be32 op_compl;
2567 	__be32 flowid_len16;
2568 	__u64  cookie;
2569 	__u8   subop;
2570 	__u8   status;
2571 	__u8   ctrl_state;
2572 	__u8   io_state;
2573 	__be32 node_id;
2574 	__be32 ctrl_id;
2575 	__be32 io_id;
2576 	struct fw_foiscsi_sess_attr {
2577 		__be32 sess_type_to_erl;
2578 		__be16 max_conn;
2579 		__be16 max_r2t;
2580 		__be16 time2wait;
2581 		__be16 time2retain;
2582 		__be32 max_burst;
2583 		__be32 first_burst;
2584 		__be32 r1;
2585 	} sess_attr;
2586 	struct fw_foiscsi_conn_attr {
2587 		__be32 hdigest_to_ddp_pgsz;
2588 		__be32 max_rcv_dsl;
2589 		__be32 ping_tmo;
2590 		__be16 dst_port;
2591 		__be16 src_port;
2592 		union fw_foiscsi_conn_attr_addr {
2593 			struct fw_foiscsi_conn_attr_ipv6 {
2594 				__be64 dst_addr[2];
2595 				__be64 src_addr[2];
2596 			} ipv6_addr;
2597 			struct fw_foiscsi_conn_attr_ipv4 {
2598 				__be32 dst_addr;
2599 				__be32 src_addr;
2600 			} ipv4_addr;
2601 		} u;
2602 	} conn_attr;
2603 	__u8   tgt_name_len;
2604 	__u8   r3[7];
2605 	__u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2606 };
2607 
2608 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
2609 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
2610 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2611     ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2612 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2613     (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2614 
2615 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
2616 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
2617 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2618     ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2619 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2620     (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2621      M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2622 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
2623     V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2624 
2625 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
2626 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
2627 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2628     ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2629 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2630     (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2631      M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2632 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
2633     V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2634 
2635 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
2636 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
2637 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2638     ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2639 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2640     (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2641      M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2642 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
2643     V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2644 
2645 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
2646 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
2647 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2648     ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2649 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2650     (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2651      M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2652 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
2653     V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2654 
2655 #define S_FW_FOISCSI_CTRL_WR_ERL	24
2656 #define M_FW_FOISCSI_CTRL_WR_ERL	0x3
2657 #define V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2658 #define G_FW_FOISCSI_CTRL_WR_ERL(x)	\
2659     (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2660 
2661 #define S_FW_FOISCSI_CTRL_WR_HDIGEST	30
2662 #define M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
2663 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2664 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
2665     (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2666 
2667 #define S_FW_FOISCSI_CTRL_WR_DDIGEST	28
2668 #define M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
2669 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2670 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
2671     (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2672 
2673 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
2674 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
2675 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2676     ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2677 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2678     (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2679      M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2680 
2681 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
2682 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
2683 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2684     ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2685 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2686     (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2687      M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2688 
2689 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ		21
2690 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ		0x3
2691 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2692     ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2693 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2694     (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2695 
2696 #define S_FW_FOISCSI_CTRL_WR_IPV6	20
2697 #define M_FW_FOISCSI_CTRL_WR_IPV6	0x1
2698 #define V_FW_FOISCSI_CTRL_WR_IPV6(x)	((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2699 #define G_FW_FOISCSI_CTRL_WR_IPV6(x)	\
2700     (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2701 #define F_FW_FOISCSI_CTRL_WR_IPV6	V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2702 
2703 struct fw_foiscsi_chap_wr {
2704 	__be32 op_compl;
2705 	__be32 flowid_len16;
2706 	__u64  cookie;
2707 	__u8   status;
2708 	__u8   id_len;
2709 	__u8   sec_len;
2710 	__u8   node_type;
2711 	__be16 node_id;
2712 	__u8   r3[2];
2713 	__u8   chap_id[FW_FOISCSI_NAME_MAX_LEN];
2714 	__u8   chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2715 };
2716 
2717 /******************************************************************************
2718  *  C O i S C S I  W O R K R E Q U E S T S
2719  ********************************************/
2720 
2721 enum fw_chnet_addr_type {
2722 	FW_CHNET_ADDD_TYPE_NONE = 0,
2723 	FW_CHNET_ADDR_TYPE_IPV4,
2724 	FW_CHNET_ADDR_TYPE_IPV6,
2725 };
2726 
2727 enum fw_msg_wr_type {
2728 	FW_MSG_WR_TYPE_RPL = 0,
2729 	FW_MSG_WR_TYPE_ERR,
2730 	FW_MSG_WR_TYPE_PLD,
2731 };
2732 
2733 struct fw_coiscsi_tgt_wr {
2734 	__be32 op_compl;
2735 	__be32 flowid_len16;
2736 	__u64  cookie;
2737 	__u8   subop;
2738 	__u8   status;
2739 	__be16 r4;
2740 	__be32 flags;
2741 	struct fw_coiscsi_tgt_conn_attr {
2742 		__be32 in_tid;
2743 		__be16 in_port;
2744 		__u8   in_type;
2745 		__u8   r6;
2746 		union fw_coiscsi_tgt_conn_attr_addr {
2747 			struct fw_coiscsi_tgt_conn_attr_in_addr {
2748 				__be32 addr;
2749 				__be32 r7;
2750 				__be32 r8[2];
2751 			} in_addr;
2752 			struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2753 				__be64 addr[2];
2754 			} in_addr6;
2755 		} u;
2756 	} conn_attr;
2757 };
2758 
2759 struct fw_coiscsi_tgt_xmit_wr {
2760 	__be32 op_to_immdlen;
2761 	__be32 flowid_len16;
2762 	__be64 cookie;
2763 	__be16 iq_id;
2764 	__be16 r4;
2765 	__be32 datasn;
2766 	__be32 t_xfer_len;
2767 	__be32 flags;
2768 	__be32 tag;
2769 	__be32 tidx;
2770 	__be32 r5[2];
2771 };
2772 
2773 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST		23
2774 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST		0x1
2775 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x)	\
2776     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2777 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x)	\
2778     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2779 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST	V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U)
2780 
2781 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST		22
2782 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST		0x1
2783 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x)	\
2784     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2785 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x)	\
2786     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2787 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST	V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U)
2788 
2789 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP	20
2790 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP	0x1
2791 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x)	((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP)
2792 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x)	\
2793     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP)
2794 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP	V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U)
2795 
2796 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT		19
2797 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT		0x1
2798 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x)	\
2799     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2800 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x)	\
2801     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2802 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT	V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U)
2803 
2804 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL		18
2805 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL		0x1
2806 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x)	\
2807     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2808 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x)	\
2809     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2810 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL	V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U)
2811 
2812 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN		16
2813 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN		0x3
2814 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x)	\
2815     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2816 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x)	\
2817     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \
2818      M_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2819 
2820 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN	0
2821 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN	0xff
2822 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2823     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2824 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2825     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \
2826      M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2827 
2828 struct fw_isns_wr {
2829 	__be32 op_compl;
2830 	__be32 flowid_len16;
2831 	__u64  cookie;
2832 	__u8   subop;
2833 	__u8   status;
2834 	__be16 iq_id;
2835 	__be32 r4;
2836 	struct fw_tcp_conn_attr {
2837 		__be32 in_tid;
2838 		__be16 in_port;
2839 		__u8   in_type;
2840 		__u8   r6;
2841 		union fw_tcp_conn_attr_addr {
2842 			struct fw_tcp_conn_attr_in_addr {
2843 				__be32 addr;
2844 				__be32 r7;
2845 				__be32 r8[2];
2846 			} in_addr;
2847 			struct fw_tcp_conn_attr_in_addr6 {
2848 				__be64 addr[2];
2849 			} in_addr6;
2850 		} u;
2851 	} conn_attr;
2852 };
2853 
2854 struct fw_isns_xmit_wr {
2855 	__be32 op_to_immdlen;
2856 	__be32 flowid_len16;
2857 	__be64 cookie;
2858 	__be16 iq_id;
2859 	__be16 r4;
2860 	__be32 xfer_len;
2861 	__be64 r5;
2862 };
2863 
2864 #define S_FW_ISNS_XMIT_WR_IMMDLEN	0
2865 #define M_FW_ISNS_XMIT_WR_IMMDLEN	0xff
2866 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x)	((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
2867 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x)	\
2868     (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
2869 
2870 /******************************************************************************
2871  *  F O F C O E   W O R K R E Q U E S T s
2872  *******************************************/
2873 
2874 struct fw_fcoe_els_ct_wr {
2875 	__be32 op_immdlen;
2876 	__be32 flowid_len16;
2877 	__be64 cookie;
2878 	__be16 iqid;
2879 	__u8   tmo_val;
2880 	__u8   els_ct_type;
2881 	__u8   ctl_pri;
2882 	__u8   cp_en_class;
2883 	__be16 xfer_cnt;
2884 	__u8   fl_to_sp;
2885 	__u8   l_id[3];
2886 	__u8   r5;
2887 	__u8   r_id[3];
2888 	__be64 rsp_dmaaddr;
2889 	__be32 rsp_dmalen;
2890 	__be32 r6;
2891 };
2892 
2893 #define S_FW_FCOE_ELS_CT_WR_OPCODE	24
2894 #define M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
2895 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2896 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
2897     (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2898 
2899 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
2900 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
2901 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2902 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
2903     (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2904 
2905 #define S_FW_FCOE_ELS_CT_WR_FLOWID	8
2906 #define M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
2907 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2908 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
2909     (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2910 
2911 #define S_FW_FCOE_ELS_CT_WR_LEN16	0
2912 #define M_FW_FCOE_ELS_CT_WR_LEN16	0xff
2913 #define V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2914 #define G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
2915     (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2916 
2917 #define S_FW_FCOE_ELS_CT_WR_CP_EN	6
2918 #define M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
2919 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2920 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
2921     (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2922 
2923 #define S_FW_FCOE_ELS_CT_WR_CLASS	4
2924 #define M_FW_FCOE_ELS_CT_WR_CLASS	0x3
2925 #define V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2926 #define G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
2927     (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2928 
2929 #define S_FW_FCOE_ELS_CT_WR_FL		2
2930 #define M_FW_FCOE_ELS_CT_WR_FL		0x1
2931 #define V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
2932 #define G_FW_FCOE_ELS_CT_WR_FL(x)	\
2933     (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2934 #define F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
2935 
2936 #define S_FW_FCOE_ELS_CT_WR_NPIV	1
2937 #define M_FW_FCOE_ELS_CT_WR_NPIV	0x1
2938 #define V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2939 #define G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
2940     (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2941 #define F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2942 
2943 #define S_FW_FCOE_ELS_CT_WR_SP		0
2944 #define M_FW_FCOE_ELS_CT_WR_SP		0x1
2945 #define V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
2946 #define G_FW_FCOE_ELS_CT_WR_SP(x)	\
2947     (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2948 #define F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
2949 
2950 /******************************************************************************
2951  *  S C S I   W O R K R E Q U E S T s   (FOiSCSI and FCOE unified data path)
2952  *****************************************************************************/
2953 
2954 struct fw_scsi_write_wr {
2955 	__be32 op_immdlen;
2956 	__be32 flowid_len16;
2957 	__be64 cookie;
2958 	__be16 iqid;
2959 	__u8   tmo_val;
2960 	__u8   use_xfer_cnt;
2961 	union fw_scsi_write_priv {
2962 		struct fcoe_write_priv {
2963 			__u8   ctl_pri;
2964 			__u8   cp_en_class;
2965 			__u8   r3_lo[2];
2966 		} fcoe;
2967 		struct iscsi_write_priv {
2968 			__u8   r3[4];
2969 		} iscsi;
2970 	} u;
2971 	__be32 xfer_cnt;
2972 	__be32 ini_xfer_cnt;
2973 	__be64 rsp_dmaaddr;
2974 	__be32 rsp_dmalen;
2975 	__be32 r4;
2976 };
2977 
2978 #define S_FW_SCSI_WRITE_WR_OPCODE	24
2979 #define M_FW_SCSI_WRITE_WR_OPCODE	0xff
2980 #define V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2981 #define G_FW_SCSI_WRITE_WR_OPCODE(x)	\
2982     (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2983 
2984 #define S_FW_SCSI_WRITE_WR_IMMDLEN	0
2985 #define M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
2986 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2987 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
2988     (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2989 
2990 #define S_FW_SCSI_WRITE_WR_FLOWID	8
2991 #define M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
2992 #define V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2993 #define G_FW_SCSI_WRITE_WR_FLOWID(x)	\
2994     (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2995 
2996 #define S_FW_SCSI_WRITE_WR_LEN16	0
2997 #define M_FW_SCSI_WRITE_WR_LEN16	0xff
2998 #define V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
2999 #define G_FW_SCSI_WRITE_WR_LEN16(x)	\
3000     (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
3001 
3002 #define S_FW_SCSI_WRITE_WR_CP_EN	6
3003 #define M_FW_SCSI_WRITE_WR_CP_EN	0x3
3004 #define V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
3005 #define G_FW_SCSI_WRITE_WR_CP_EN(x)	\
3006     (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
3007 
3008 #define S_FW_SCSI_WRITE_WR_CLASS	4
3009 #define M_FW_SCSI_WRITE_WR_CLASS	0x3
3010 #define V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
3011 #define G_FW_SCSI_WRITE_WR_CLASS(x)	\
3012     (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
3013 
3014 struct fw_scsi_read_wr {
3015 	__be32 op_immdlen;
3016 	__be32 flowid_len16;
3017 	__be64 cookie;
3018 	__be16 iqid;
3019 	__u8   tmo_val;
3020 	__u8   use_xfer_cnt;
3021 	union fw_scsi_read_priv {
3022 		struct fcoe_read_priv {
3023 			__u8   ctl_pri;
3024 			__u8   cp_en_class;
3025 			__u8   r3_lo[2];
3026 		} fcoe;
3027 		struct iscsi_read_priv {
3028 			__u8   r3[4];
3029 		} iscsi;
3030 	} u;
3031 	__be32 xfer_cnt;
3032 	__be32 ini_xfer_cnt;
3033 	__be64 rsp_dmaaddr;
3034 	__be32 rsp_dmalen;
3035 	__be32 r4;
3036 };
3037 
3038 #define S_FW_SCSI_READ_WR_OPCODE	24
3039 #define M_FW_SCSI_READ_WR_OPCODE	0xff
3040 #define V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
3041 #define G_FW_SCSI_READ_WR_OPCODE(x)	\
3042     (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
3043 
3044 #define S_FW_SCSI_READ_WR_IMMDLEN	0
3045 #define M_FW_SCSI_READ_WR_IMMDLEN	0xff
3046 #define V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
3047 #define G_FW_SCSI_READ_WR_IMMDLEN(x)	\
3048     (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
3049 
3050 #define S_FW_SCSI_READ_WR_FLOWID	8
3051 #define M_FW_SCSI_READ_WR_FLOWID	0xfffff
3052 #define V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
3053 #define G_FW_SCSI_READ_WR_FLOWID(x)	\
3054     (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
3055 
3056 #define S_FW_SCSI_READ_WR_LEN16		0
3057 #define M_FW_SCSI_READ_WR_LEN16		0xff
3058 #define V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
3059 #define G_FW_SCSI_READ_WR_LEN16(x)	\
3060     (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
3061 
3062 #define S_FW_SCSI_READ_WR_CP_EN		6
3063 #define M_FW_SCSI_READ_WR_CP_EN		0x3
3064 #define V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
3065 #define G_FW_SCSI_READ_WR_CP_EN(x)	\
3066     (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
3067 
3068 #define S_FW_SCSI_READ_WR_CLASS		4
3069 #define M_FW_SCSI_READ_WR_CLASS		0x3
3070 #define V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
3071 #define G_FW_SCSI_READ_WR_CLASS(x)	\
3072     (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
3073 
3074 struct fw_scsi_cmd_wr {
3075 	__be32 op_immdlen;
3076 	__be32 flowid_len16;
3077 	__be64 cookie;
3078 	__be16 iqid;
3079 	__u8   tmo_val;
3080 	__u8   r3;
3081 	union fw_scsi_cmd_priv {
3082 		struct fcoe_cmd_priv {
3083 			__u8   ctl_pri;
3084 			__u8   cp_en_class;
3085 			__u8   r4_lo[2];
3086 		} fcoe;
3087 		struct iscsi_cmd_priv {
3088 			__u8   r4[4];
3089 		} iscsi;
3090 	} u;
3091 	__u8   r5[8];
3092 	__be64 rsp_dmaaddr;
3093 	__be32 rsp_dmalen;
3094 	__be32 r6;
3095 };
3096 
3097 #define S_FW_SCSI_CMD_WR_OPCODE		24
3098 #define M_FW_SCSI_CMD_WR_OPCODE		0xff
3099 #define V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
3100 #define G_FW_SCSI_CMD_WR_OPCODE(x)	\
3101     (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
3102 
3103 #define S_FW_SCSI_CMD_WR_IMMDLEN	0
3104 #define M_FW_SCSI_CMD_WR_IMMDLEN	0xff
3105 #define V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
3106 #define G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
3107     (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
3108 
3109 #define S_FW_SCSI_CMD_WR_FLOWID		8
3110 #define M_FW_SCSI_CMD_WR_FLOWID		0xfffff
3111 #define V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
3112 #define G_FW_SCSI_CMD_WR_FLOWID(x)	\
3113     (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
3114 
3115 #define S_FW_SCSI_CMD_WR_LEN16		0
3116 #define M_FW_SCSI_CMD_WR_LEN16		0xff
3117 #define V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
3118 #define G_FW_SCSI_CMD_WR_LEN16(x)	\
3119     (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
3120 
3121 #define S_FW_SCSI_CMD_WR_CP_EN		6
3122 #define M_FW_SCSI_CMD_WR_CP_EN		0x3
3123 #define V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
3124 #define G_FW_SCSI_CMD_WR_CP_EN(x)	\
3125     (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3126 
3127 #define S_FW_SCSI_CMD_WR_CLASS		4
3128 #define M_FW_SCSI_CMD_WR_CLASS		0x3
3129 #define V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
3130 #define G_FW_SCSI_CMD_WR_CLASS(x)	\
3131     (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3132 
3133 struct fw_scsi_abrt_cls_wr {
3134 	__be32 op_immdlen;
3135 	__be32 flowid_len16;
3136 	__be64 cookie;
3137 	__be16 iqid;
3138 	__u8   tmo_val;
3139 	__u8   sub_opcode_to_chk_all_io;
3140 	__u8   r3[4];
3141 	__be64 t_cookie;
3142 };
3143 
3144 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE	24
3145 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE	0xff
3146 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
3147 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
3148     (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
3149 
3150 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0
3151 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0xff
3152 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
3153     ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3154 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
3155     (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3156 
3157 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID	8
3158 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID	0xfffff
3159 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
3160 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
3161     (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
3162 
3163 #define S_FW_SCSI_ABRT_CLS_WR_LEN16	0
3164 #define M_FW_SCSI_ABRT_CLS_WR_LEN16	0xff
3165 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
3166 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
3167     (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
3168 
3169 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	2
3170 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	0x3f
3171 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
3172     ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3173 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
3174     (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
3175      M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3176 
3177 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
3178 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL	0x1
3179 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
3180 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
3181     (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
3182 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
3183 
3184 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0
3185 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0x1
3186 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
3187     ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3188 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
3189     (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
3190      M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3191 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	\
3192     V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
3193 
3194 struct fw_scsi_tgt_acc_wr {
3195 	__be32 op_immdlen;
3196 	__be32 flowid_len16;
3197 	__be64 cookie;
3198 	__be16 iqid;
3199 	__u8   r3;
3200 	__u8   use_burst_len;
3201 	union fw_scsi_tgt_acc_priv {
3202 		struct fcoe_tgt_acc_priv {
3203 			__u8   ctl_pri;
3204 			__u8   cp_en_class;
3205 			__u8   r4_lo[2];
3206 		} fcoe;
3207 		struct iscsi_tgt_acc_priv {
3208 			__u8   r4[4];
3209 		} iscsi;
3210 	} u;
3211 	__be32 burst_len;
3212 	__be32 rel_off;
3213 	__be64 r5;
3214 	__be32 r6;
3215 	__be32 tot_xfer_len;
3216 };
3217 
3218 #define S_FW_SCSI_TGT_ACC_WR_OPCODE	24
3219 #define M_FW_SCSI_TGT_ACC_WR_OPCODE	0xff
3220 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
3221 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
3222     (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
3223 
3224 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN	0
3225 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN	0xff
3226 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3227 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
3228     (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3229 
3230 #define S_FW_SCSI_TGT_ACC_WR_FLOWID	8
3231 #define M_FW_SCSI_TGT_ACC_WR_FLOWID	0xfffff
3232 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
3233 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
3234     (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
3235 
3236 #define S_FW_SCSI_TGT_ACC_WR_LEN16	0
3237 #define M_FW_SCSI_TGT_ACC_WR_LEN16	0xff
3238 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
3239 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
3240     (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
3241 
3242 #define S_FW_SCSI_TGT_ACC_WR_CP_EN	6
3243 #define M_FW_SCSI_TGT_ACC_WR_CP_EN	0x3
3244 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
3245 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
3246     (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
3247 
3248 #define S_FW_SCSI_TGT_ACC_WR_CLASS	4
3249 #define M_FW_SCSI_TGT_ACC_WR_CLASS	0x3
3250 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
3251 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
3252     (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
3253 
3254 struct fw_scsi_tgt_xmit_wr {
3255 	__be32 op_immdlen;
3256 	__be32 flowid_len16;
3257 	__be64 cookie;
3258 	__be16 iqid;
3259 	__u8   auto_rsp;
3260 	__u8   use_xfer_cnt;
3261 	union fw_scsi_tgt_xmit_priv {
3262 		struct fcoe_tgt_xmit_priv {
3263 			__u8   ctl_pri;
3264 			__u8   cp_en_class;
3265 			__u8   r3_lo[2];
3266 		} fcoe;
3267 		struct iscsi_tgt_xmit_priv {
3268 			__u8   r3[4];
3269 		} iscsi;
3270 	} u;
3271 	__be32 xfer_cnt;
3272 	__be32 r4;
3273 	__be64 r5;
3274 	__be32 r6;
3275 	__be32 tot_xfer_len;
3276 };
3277 
3278 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE	24
3279 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE	0xff
3280 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
3281 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
3282     (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
3283 
3284 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0
3285 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0xff
3286 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
3287     ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3288 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
3289     (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3290 
3291 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID	8
3292 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID	0xfffff
3293 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
3294 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
3295     (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
3296 
3297 #define S_FW_SCSI_TGT_XMIT_WR_LEN16	0
3298 #define M_FW_SCSI_TGT_XMIT_WR_LEN16	0xff
3299 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
3300 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
3301     (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
3302 
3303 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN	6
3304 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN	0x3
3305 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
3306 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
3307     (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
3308 
3309 #define S_FW_SCSI_TGT_XMIT_WR_CLASS	4
3310 #define M_FW_SCSI_TGT_XMIT_WR_CLASS	0x3
3311 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
3312 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
3313     (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
3314 
3315 struct fw_scsi_tgt_rsp_wr {
3316 	__be32 op_immdlen;
3317 	__be32 flowid_len16;
3318 	__be64 cookie;
3319 	__be16 iqid;
3320 	__u8   r3[2];
3321 	union fw_scsi_tgt_rsp_priv {
3322 		struct fcoe_tgt_rsp_priv {
3323 			__u8   ctl_pri;
3324 			__u8   cp_en_class;
3325 			__u8   r4_lo[2];
3326 		} fcoe;
3327 		struct iscsi_tgt_rsp_priv {
3328 			__u8   r4[4];
3329 		} iscsi;
3330 	} u;
3331 	__u8   r5[8];
3332 };
3333 
3334 #define S_FW_SCSI_TGT_RSP_WR_OPCODE	24
3335 #define M_FW_SCSI_TGT_RSP_WR_OPCODE	0xff
3336 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
3337 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
3338     (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
3339 
3340 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN	0
3341 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN	0xff
3342 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3343 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
3344     (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3345 
3346 #define S_FW_SCSI_TGT_RSP_WR_FLOWID	8
3347 #define M_FW_SCSI_TGT_RSP_WR_FLOWID	0xfffff
3348 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
3349 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
3350     (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
3351 
3352 #define S_FW_SCSI_TGT_RSP_WR_LEN16	0
3353 #define M_FW_SCSI_TGT_RSP_WR_LEN16	0xff
3354 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
3355 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
3356     (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
3357 
3358 #define S_FW_SCSI_TGT_RSP_WR_CP_EN	6
3359 #define M_FW_SCSI_TGT_RSP_WR_CP_EN	0x3
3360 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
3361 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
3362     (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
3363 
3364 #define S_FW_SCSI_TGT_RSP_WR_CLASS	4
3365 #define M_FW_SCSI_TGT_RSP_WR_CLASS	0x3
3366 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
3367 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
3368     (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
3369 
3370 struct fw_pofcoe_tcb_wr {
3371 	__be32 op_compl;
3372 	__be32 equiq_to_len16;
3373 	__be32 r4;
3374 	__be32 xfer_len;
3375 	__be32 tid_to_port;
3376 	__be16 x_id;
3377 	__be16 vlan_id;
3378 	__be64 cookie;
3379 	__be32 s_id;
3380 	__be32 d_id;
3381 	__be32 tag;
3382 	__be16 r6;
3383 	__be16 iqid;
3384 };
3385 
3386 #define S_FW_POFCOE_TCB_WR_TID		12
3387 #define M_FW_POFCOE_TCB_WR_TID		0xfffff
3388 #define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
3389 #define G_FW_POFCOE_TCB_WR_TID(x)	\
3390     (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
3391 
3392 #define S_FW_POFCOE_TCB_WR_ALLOC	4
3393 #define M_FW_POFCOE_TCB_WR_ALLOC	0x1
3394 #define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
3395 #define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
3396     (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
3397 #define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)
3398 
3399 #define S_FW_POFCOE_TCB_WR_FREE		3
3400 #define M_FW_POFCOE_TCB_WR_FREE		0x1
3401 #define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
3402 #define G_FW_POFCOE_TCB_WR_FREE(x)	\
3403     (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
3404 #define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)
3405 
3406 #define S_FW_POFCOE_TCB_WR_PORT		0
3407 #define M_FW_POFCOE_TCB_WR_PORT		0x7
3408 #define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
3409 #define G_FW_POFCOE_TCB_WR_PORT(x)	\
3410     (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
3411 
3412 struct fw_pofcoe_ulptx_wr {
3413 	__be32 op_pkd;
3414 	__be32 equiq_to_len16;
3415 	__u64  cookie;
3416 };
3417 
3418 /*******************************************************************
3419  *  T10 DIF related definition
3420  *******************************************************************/
3421 struct fw_tx_pi_header {
3422 	__be16 op_to_inline;
3423 	__u8   pi_interval_tag_type;
3424 	__u8   num_pi;
3425 	__be32 pi_start4_pi_end4;
3426 	__u8   tag_gen_enabled_pkd;
3427 	__u8   num_pi_dsg;
3428 	__be16 app_tag;
3429 	__be32 ref_tag;
3430 };
3431 
3432 #define S_FW_TX_PI_HEADER_OP	8
3433 #define M_FW_TX_PI_HEADER_OP	0xff
3434 #define V_FW_TX_PI_HEADER_OP(x)	((x) << S_FW_TX_PI_HEADER_OP)
3435 #define G_FW_TX_PI_HEADER_OP(x)	\
3436     (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
3437 
3438 #define S_FW_TX_PI_HEADER_ULPTXMORE	7
3439 #define M_FW_TX_PI_HEADER_ULPTXMORE	0x1
3440 #define V_FW_TX_PI_HEADER_ULPTXMORE(x)	((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
3441 #define G_FW_TX_PI_HEADER_ULPTXMORE(x)	\
3442     (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
3443 #define F_FW_TX_PI_HEADER_ULPTXMORE	V_FW_TX_PI_HEADER_ULPTXMORE(1U)
3444 
3445 #define S_FW_TX_PI_HEADER_PI_CONTROL	4
3446 #define M_FW_TX_PI_HEADER_PI_CONTROL	0x7
3447 #define V_FW_TX_PI_HEADER_PI_CONTROL(x)	((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
3448 #define G_FW_TX_PI_HEADER_PI_CONTROL(x)	\
3449     (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
3450 
3451 #define S_FW_TX_PI_HEADER_GUARD_TYPE	2
3452 #define M_FW_TX_PI_HEADER_GUARD_TYPE	0x1
3453 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x)	((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
3454 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x)	\
3455     (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
3456 #define F_FW_TX_PI_HEADER_GUARD_TYPE	V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
3457 
3458 #define S_FW_TX_PI_HEADER_VALIDATE	1
3459 #define M_FW_TX_PI_HEADER_VALIDATE	0x1
3460 #define V_FW_TX_PI_HEADER_VALIDATE(x)	((x) << S_FW_TX_PI_HEADER_VALIDATE)
3461 #define G_FW_TX_PI_HEADER_VALIDATE(x)	\
3462     (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
3463 #define F_FW_TX_PI_HEADER_VALIDATE	V_FW_TX_PI_HEADER_VALIDATE(1U)
3464 
3465 #define S_FW_TX_PI_HEADER_INLINE	0
3466 #define M_FW_TX_PI_HEADER_INLINE	0x1
3467 #define V_FW_TX_PI_HEADER_INLINE(x)	((x) << S_FW_TX_PI_HEADER_INLINE)
3468 #define G_FW_TX_PI_HEADER_INLINE(x)	\
3469     (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
3470 #define F_FW_TX_PI_HEADER_INLINE	V_FW_TX_PI_HEADER_INLINE(1U)
3471 
3472 #define S_FW_TX_PI_HEADER_PI_INTERVAL		7
3473 #define M_FW_TX_PI_HEADER_PI_INTERVAL		0x1
3474 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x)	\
3475     ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
3476 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x)	\
3477     (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
3478 #define F_FW_TX_PI_HEADER_PI_INTERVAL	V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
3479 
3480 #define S_FW_TX_PI_HEADER_TAG_TYPE	5
3481 #define M_FW_TX_PI_HEADER_TAG_TYPE	0x3
3482 #define V_FW_TX_PI_HEADER_TAG_TYPE(x)	((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
3483 #define G_FW_TX_PI_HEADER_TAG_TYPE(x)	\
3484     (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
3485 
3486 #define S_FW_TX_PI_HEADER_PI_START4	22
3487 #define M_FW_TX_PI_HEADER_PI_START4	0x3ff
3488 #define V_FW_TX_PI_HEADER_PI_START4(x)	((x) << S_FW_TX_PI_HEADER_PI_START4)
3489 #define G_FW_TX_PI_HEADER_PI_START4(x)	\
3490     (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
3491 
3492 #define S_FW_TX_PI_HEADER_PI_END4	0
3493 #define M_FW_TX_PI_HEADER_PI_END4	0x3fffff
3494 #define V_FW_TX_PI_HEADER_PI_END4(x)	((x) << S_FW_TX_PI_HEADER_PI_END4)
3495 #define G_FW_TX_PI_HEADER_PI_END4(x)	\
3496     (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
3497 
3498 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED	6
3499 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED	0x3
3500 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)	\
3501     ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3502 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)	\
3503     (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
3504      M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3505 
3506 enum fw_pi_error_type {
3507 	FW_PI_ERROR_GUARD_CHECK_FAILED = 0,
3508 };
3509 
3510 struct fw_pi_error {
3511 	__be32 err_type_pkd;
3512 	__be32 flowid_len16;
3513 	__be16 r2;
3514 	__be16 app_tag;
3515 	__be32 ref_tag;
3516 	__be32  pisc[4];
3517 };
3518 
3519 #define S_FW_PI_ERROR_ERR_TYPE		24
3520 #define M_FW_PI_ERROR_ERR_TYPE		0xff
3521 #define V_FW_PI_ERROR_ERR_TYPE(x)	((x) << S_FW_PI_ERROR_ERR_TYPE)
3522 #define G_FW_PI_ERROR_ERR_TYPE(x)	\
3523     (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
3524 
3525 struct fw_tlstx_data_wr {
3526         __be32 op_to_immdlen;
3527         __be32 flowid_len16;
3528         __be32 plen;
3529         __be32 lsodisable_to_flags;
3530         __be32 r5;
3531         __be32 ctxloc_to_exp;
3532         __be16 mfs;
3533         __be16 adjustedplen_pkd;
3534         __be16 expinplenmax_pkd;
3535         __u8   pdusinplenmax_pkd;
3536         __u8   r10;
3537 };
3538 
3539 #define S_FW_TLSTX_DATA_WR_OPCODE       24
3540 #define M_FW_TLSTX_DATA_WR_OPCODE       0xff
3541 #define V_FW_TLSTX_DATA_WR_OPCODE(x)    ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
3542 #define G_FW_TLSTX_DATA_WR_OPCODE(x)    \
3543     (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
3544 
3545 #define S_FW_TLSTX_DATA_WR_COMPL        21
3546 #define M_FW_TLSTX_DATA_WR_COMPL        0x1
3547 #define V_FW_TLSTX_DATA_WR_COMPL(x)     ((x) << S_FW_TLSTX_DATA_WR_COMPL)
3548 #define G_FW_TLSTX_DATA_WR_COMPL(x)     \
3549     (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
3550 #define F_FW_TLSTX_DATA_WR_COMPL        V_FW_TLSTX_DATA_WR_COMPL(1U)
3551 
3552 #define S_FW_TLSTX_DATA_WR_IMMDLEN      0
3553 #define M_FW_TLSTX_DATA_WR_IMMDLEN      0xff
3554 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x)   ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
3555 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x)   \
3556     (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
3557 
3558 #define S_FW_TLSTX_DATA_WR_FLOWID       8
3559 #define M_FW_TLSTX_DATA_WR_FLOWID       0xfffff
3560 #define V_FW_TLSTX_DATA_WR_FLOWID(x)    ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
3561 #define G_FW_TLSTX_DATA_WR_FLOWID(x)    \
3562     (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
3563 
3564 #define S_FW_TLSTX_DATA_WR_LEN16        0
3565 #define M_FW_TLSTX_DATA_WR_LEN16        0xff
3566 #define V_FW_TLSTX_DATA_WR_LEN16(x)     ((x) << S_FW_TLSTX_DATA_WR_LEN16)
3567 #define G_FW_TLSTX_DATA_WR_LEN16(x)     \
3568     (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
3569 
3570 #define S_FW_TLSTX_DATA_WR_LSODISABLE   31
3571 #define M_FW_TLSTX_DATA_WR_LSODISABLE   0x1
3572 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3573     ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
3574 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3575     (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
3576 #define F_FW_TLSTX_DATA_WR_LSODISABLE   V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
3577 
3578 #define S_FW_TLSTX_DATA_WR_ALIGNPLD     30
3579 #define M_FW_TLSTX_DATA_WR_ALIGNPLD     0x1
3580 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x)  ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
3581 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x)  \
3582     (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
3583 #define F_FW_TLSTX_DATA_WR_ALIGNPLD     V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
3584 
3585 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
3586 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
3587 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3588     ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3589 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3590     (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
3591      M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3592 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
3593 
3594 #define S_FW_TLSTX_DATA_WR_FLAGS        0
3595 #define M_FW_TLSTX_DATA_WR_FLAGS        0xfffffff
3596 #define V_FW_TLSTX_DATA_WR_FLAGS(x)     ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
3597 #define G_FW_TLSTX_DATA_WR_FLAGS(x)     \
3598     (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
3599 
3600 #define S_FW_TLSTX_DATA_WR_CTXLOC       30
3601 #define M_FW_TLSTX_DATA_WR_CTXLOC       0x3
3602 #define V_FW_TLSTX_DATA_WR_CTXLOC(x)    ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
3603 #define G_FW_TLSTX_DATA_WR_CTXLOC(x)    \
3604     (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
3605 
3606 #define S_FW_TLSTX_DATA_WR_IVDSGL       29
3607 #define M_FW_TLSTX_DATA_WR_IVDSGL       0x1
3608 #define V_FW_TLSTX_DATA_WR_IVDSGL(x)    ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
3609 #define G_FW_TLSTX_DATA_WR_IVDSGL(x)    \
3610     (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
3611 #define F_FW_TLSTX_DATA_WR_IVDSGL       V_FW_TLSTX_DATA_WR_IVDSGL(1U)
3612 
3613 #define S_FW_TLSTX_DATA_WR_KEYSIZE      24
3614 #define M_FW_TLSTX_DATA_WR_KEYSIZE      0x1f
3615 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x)   ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
3616 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x)   \
3617     (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
3618 
3619 #define S_FW_TLSTX_DATA_WR_NUMIVS       14
3620 #define M_FW_TLSTX_DATA_WR_NUMIVS       0xff
3621 #define V_FW_TLSTX_DATA_WR_NUMIVS(x)    ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
3622 #define G_FW_TLSTX_DATA_WR_NUMIVS(x)    \
3623     (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
3624 
3625 #define S_FW_TLSTX_DATA_WR_EXP          0
3626 #define M_FW_TLSTX_DATA_WR_EXP          0x3fff
3627 #define V_FW_TLSTX_DATA_WR_EXP(x)       ((x) << S_FW_TLSTX_DATA_WR_EXP)
3628 #define G_FW_TLSTX_DATA_WR_EXP(x)       \
3629     (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
3630 
3631 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
3632 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
3633 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3634     ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3635 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3636     (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
3637      M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3638 
3639 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
3640 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
3641 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3642     ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3643 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3644     (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
3645      M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3646 
3647 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
3648 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
3649 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3650     ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3651 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3652     (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
3653      M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3654 
3655 struct fw_tls_keyctx_tx_wr {
3656         __be32 op_to_compl;
3657         __be32 flowid_len16;
3658         union fw_key_ctx {
3659                 struct fw_tx_keyctx_hdr {
3660                         __u8   ctxlen;
3661                         __u8   r2;
3662                         __be16 dualck_to_txvalid;
3663                         __u8   txsalt[4];
3664                         __be64 r5;
3665                 } txhdr;
3666                 struct fw_rx_keyctx_hdr {
3667                         __u8   flitcnt_hmacctrl;
3668                         __u8   protover_ciphmode;
3669                         __u8   authmode_to_rxvalid;
3670                         __u8   ivpresent_to_rxmk_size;
3671                         __u8   rxsalt[4];
3672                         __be64 ivinsert_to_authinsrt;
3673                 } rxhdr;
3674                 struct fw_keyctx_clear {
3675                         __be32 tx_key;
3676                         __be32 rx_key;
3677                 } kctx_clr;
3678         } u;
3679         struct keys {
3680                 __u8   edkey[32];
3681                 __u8   ipad[64];
3682                 __u8   opad[64];
3683         } keys;
3684         __u8   reneg_to_write_rx;
3685         __u8   protocol;
3686         __be16 mfs;
3687         __be32 ftid;
3688 };
3689 
3690 #define S_FW_TLS_KEYCTX_TX_WR_OPCODE    24
3691 #define M_FW_TLS_KEYCTX_TX_WR_OPCODE    0xff
3692 #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE)
3693 #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \
3694     (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE)
3695 
3696 #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC    23
3697 #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC    0x1
3698 #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC)
3699 #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \
3700     (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC)
3701 #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC    V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U)
3702 
3703 #define S_FW_TLS_KEYCTX_TX_WR_FLUSH     22
3704 #define M_FW_TLS_KEYCTX_TX_WR_FLUSH     0x1
3705 #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH)
3706 #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x)  \
3707     (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH)
3708 #define F_FW_TLS_KEYCTX_TX_WR_FLUSH     V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U)
3709 
3710 #define S_FW_TLS_KEYCTX_TX_WR_COMPL     21
3711 #define M_FW_TLS_KEYCTX_TX_WR_COMPL     0x1
3712 #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL)
3713 #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x)  \
3714     (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL)
3715 #define F_FW_TLS_KEYCTX_TX_WR_COMPL     V_FW_TLS_KEYCTX_TX_WR_COMPL(1U)
3716 
3717 #define S_FW_TLS_KEYCTX_TX_WR_FLOWID    8
3718 #define M_FW_TLS_KEYCTX_TX_WR_FLOWID    0xfffff
3719 #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID)
3720 #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \
3721     (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID)
3722 
3723 #define S_FW_TLS_KEYCTX_TX_WR_LEN16     0
3724 #define M_FW_TLS_KEYCTX_TX_WR_LEN16     0xff
3725 #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16)
3726 #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x)  \
3727     (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16)
3728 
3729 #define S_FW_TLS_KEYCTX_TX_WR_DUALCK    12
3730 #define M_FW_TLS_KEYCTX_TX_WR_DUALCK    0x1
3731 #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK)
3732 #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \
3733     (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK)
3734 #define F_FW_TLS_KEYCTX_TX_WR_DUALCK    V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U)
3735 
3736 #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11
3737 #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1
3738 #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
3739     ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
3740 #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
3741     (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \
3742      M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
3743 #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \
3744     V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U)
3745 
3746 #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10
3747 #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1
3748 #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
3749     ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
3750 #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
3751     (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \
3752      M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
3753 #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \
3754     V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U)
3755 
3756 #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6
3757 #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf
3758 #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
3759     ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
3760 #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
3761     (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \
3762      M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
3763 
3764 #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2
3765 #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf
3766 #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
3767     ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
3768 #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
3769     (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \
3770      M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
3771 
3772 #define S_FW_TLS_KEYCTX_TX_WR_TXVALID   0
3773 #define M_FW_TLS_KEYCTX_TX_WR_TXVALID   0x1
3774 #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
3775     ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID)
3776 #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
3777     (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID)
3778 #define F_FW_TLS_KEYCTX_TX_WR_TXVALID   V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U)
3779 
3780 #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT   3
3781 #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT   0x1f
3782 #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
3783     ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT)
3784 #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
3785     (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT)
3786 
3787 #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL  0
3788 #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL  0x7
3789 #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
3790     ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
3791 #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
3792     (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
3793 
3794 #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER  4
3795 #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER  0xf
3796 #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
3797     ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER)
3798 #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
3799     (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER)
3800 
3801 #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE  0
3802 #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE  0xf
3803 #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
3804     ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
3805 #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
3806     (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
3807 
3808 #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE  4
3809 #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE  0xf
3810 #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
3811     ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
3812 #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
3813     (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
3814 
3815 #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3
3816 #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1
3817 #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
3818     ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
3819 #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
3820     (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \
3821      M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
3822 #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \
3823     V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U)
3824 
3825 #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1
3826 #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3
3827 #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
3828     ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
3829 #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
3830     (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \
3831      M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
3832 
3833 #define S_FW_TLS_KEYCTX_TX_WR_RXVALID   0
3834 #define M_FW_TLS_KEYCTX_TX_WR_RXVALID   0x1
3835 #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
3836     ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID)
3837 #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
3838     (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID)
3839 #define F_FW_TLS_KEYCTX_TX_WR_RXVALID   V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U)
3840 
3841 #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7
3842 #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1
3843 #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
3844     ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
3845 #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
3846     (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \
3847      M_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
3848 #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U)
3849 
3850 #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6
3851 #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1
3852 #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
3853     ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
3854 #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
3855     (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \
3856      M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
3857 #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \
3858     V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U)
3859 
3860 #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3
3861 #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7
3862 #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
3863     ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
3864 #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
3865     (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \
3866      M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
3867 
3868 #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0
3869 #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7
3870 #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
3871     ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
3872 #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
3873     (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \
3874      M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
3875 
3876 #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT  55
3877 #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT  0x1ffULL
3878 #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
3879     ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT)
3880 #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
3881     (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT)
3882 
3883 #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47
3884 #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL
3885 #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
3886     ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
3887 #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
3888     (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \
3889      M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
3890 
3891 #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39
3892 #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL
3893 #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
3894     ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
3895 #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
3896     (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \
3897      M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
3898 
3899 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30
3900 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL
3901 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
3902     ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
3903 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
3904     (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \
3905      M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
3906 
3907 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23
3908 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f
3909 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
3910     ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
3911 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
3912     (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \
3913      M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
3914 
3915 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14
3916 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff
3917 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
3918     ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
3919 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
3920     (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \
3921      M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
3922 
3923 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7
3924 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f
3925 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
3926     ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
3927 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
3928     (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \
3929      M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
3930 
3931 #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0
3932 #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f
3933 #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
3934     ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
3935 #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
3936     (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \
3937      M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
3938 
3939 #define S_FW_TLS_KEYCTX_TX_WR_RENEG     4
3940 #define M_FW_TLS_KEYCTX_TX_WR_RENEG     0x1
3941 #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG)
3942 #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x)  \
3943     (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG)
3944 #define F_FW_TLS_KEYCTX_TX_WR_RENEG     V_FW_TLS_KEYCTX_TX_WR_RENEG(1U)
3945 
3946 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3
3947 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1
3948 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
3949     ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
3950 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
3951     (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \
3952      M_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
3953 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U)
3954 
3955 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2
3956 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1
3957 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
3958     ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
3959 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
3960     (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \
3961      M_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
3962 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U)
3963 
3964 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX  1
3965 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX  0x1
3966 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
3967     ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
3968 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
3969     (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
3970 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX  V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U)
3971 
3972 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX  0
3973 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX  0x1
3974 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
3975     ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
3976 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
3977     (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
3978 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX  V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U)
3979 
3980 struct fw_crypto_lookaside_wr {
3981         __be32 op_to_cctx_size;
3982         __be32 len16_pkd;
3983         __be32 session_id;
3984         __be32 rx_chid_to_rx_q_id;
3985         __be32 key_addr;
3986         __be32 pld_size_hash_size;
3987         __be64 cookie;
3988 };
3989 
3990 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
3991 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
3992 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3993     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3994 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3995     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
3996      M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3997 
3998 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
3999 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
4000 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
4001     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
4002 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
4003     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
4004      M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
4005 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
4006 
4007 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
4008 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
4009 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
4010     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
4011 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
4012     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
4013      M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
4014 
4015 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
4016 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
4017 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
4018     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
4019 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
4020     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
4021      M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
4022 
4023 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
4024 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
4025 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4026     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4027 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4028     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
4029      M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4030 
4031 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
4032 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
4033 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4034     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4035 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4036     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
4037      M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4038 
4039 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
4040 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
4041 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4042     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4043 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4044     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
4045      M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4046 
4047 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB  27
4048 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB  0x3
4049 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4050     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
4051 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4052     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
4053 
4054 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
4055 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
4056 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4057     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4058 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4059     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
4060      M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4061 
4062 #define S_FW_CRYPTO_LOOKASIDE_WR_IV   23
4063 #define M_FW_CRYPTO_LOOKASIDE_WR_IV   0x3
4064 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4065     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
4066 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4067     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
4068 
4069 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX  15
4070 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX  0xff
4071 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4072 	((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4073 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4074 	(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
4075 	  M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4076 
4077 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
4078 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
4079 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4080     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4081 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4082     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
4083      M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4084 
4085 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
4086 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
4087 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4088     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4089 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4090     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
4091      M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4092 
4093 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
4094 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
4095 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4096     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4097 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4098     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
4099      M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4100 
4101 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
4102 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
4103 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4104     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4105 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4106     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
4107      M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4108 
4109 /******************************************************************************
4110  *  C O M M A N D s
4111  *********************/
4112 
4113 /*
4114  * The maximum length of time, in miliseconds, that we expect any firmware
4115  * command to take to execute and return a reply to the host.  The RESET
4116  * and INITIALIZE commands can take a fair amount of time to execute but
4117  * most execute in far less time than this maximum.  This constant is used
4118  * by host software to determine how long to wait for a firmware command
4119  * reply before declaring the firmware as dead/unreachable ...
4120  */
4121 #define FW_CMD_MAX_TIMEOUT	10000
4122 
4123 /*
4124  * If a host driver does a HELLO and discovers that there's already a MASTER
4125  * selected, we may have to wait for that MASTER to finish issuing RESET,
4126  * configuration and INITIALIZE commands.  Also, there's a possibility that
4127  * our own HELLO may get lost if it happens right as the MASTER is issuign a
4128  * RESET command, so we need to be willing to make a few retries of our HELLO.
4129  */
4130 #define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
4131 #define FW_CMD_HELLO_RETRIES	3
4132 
4133 enum fw_cmd_opcodes {
4134 	FW_LDST_CMD                    = 0x01,
4135 	FW_RESET_CMD                   = 0x03,
4136 	FW_HELLO_CMD                   = 0x04,
4137 	FW_BYE_CMD                     = 0x05,
4138 	FW_INITIALIZE_CMD              = 0x06,
4139 	FW_CAPS_CONFIG_CMD             = 0x07,
4140 	FW_PARAMS_CMD                  = 0x08,
4141 	FW_PFVF_CMD                    = 0x09,
4142 	FW_IQ_CMD                      = 0x10,
4143 	FW_EQ_MNGT_CMD                 = 0x11,
4144 	FW_EQ_ETH_CMD                  = 0x12,
4145 	FW_EQ_CTRL_CMD                 = 0x13,
4146 	FW_EQ_OFLD_CMD                 = 0x21,
4147 	FW_VI_CMD                      = 0x14,
4148 	FW_VI_MAC_CMD                  = 0x15,
4149 	FW_VI_RXMODE_CMD               = 0x16,
4150 	FW_VI_ENABLE_CMD               = 0x17,
4151 	FW_VI_STATS_CMD                = 0x1a,
4152 	FW_ACL_MAC_CMD                 = 0x18,
4153 	FW_ACL_VLAN_CMD                = 0x19,
4154 	FW_PORT_CMD                    = 0x1b,
4155 	FW_PORT_STATS_CMD              = 0x1c,
4156 	FW_PORT_LB_STATS_CMD           = 0x1d,
4157 	FW_PORT_TRACE_CMD              = 0x1e,
4158 	FW_PORT_TRACE_MMAP_CMD         = 0x1f,
4159 	FW_RSS_IND_TBL_CMD             = 0x20,
4160 	FW_RSS_GLB_CONFIG_CMD          = 0x22,
4161 	FW_RSS_VI_CONFIG_CMD           = 0x23,
4162 	FW_SCHED_CMD                   = 0x24,
4163 	FW_DEVLOG_CMD                  = 0x25,
4164 	FW_WATCHDOG_CMD                = 0x27,
4165 	FW_CLIP_CMD                    = 0x28,
4166 	FW_CHNET_IFACE_CMD             = 0x26,
4167 	FW_FCOE_RES_INFO_CMD           = 0x31,
4168 	FW_FCOE_LINK_CMD               = 0x32,
4169 	FW_FCOE_VNP_CMD                = 0x33,
4170 	FW_FCOE_SPARAMS_CMD            = 0x35,
4171 	FW_FCOE_STATS_CMD              = 0x37,
4172 	FW_FCOE_FCF_CMD                = 0x38,
4173 	FW_DCB_IEEE_CMD		       = 0x3a,
4174 	FW_DIAG_CMD		       = 0x3d,
4175 	FW_PTP_CMD                     = 0x3e,
4176 	FW_HMA_CMD                     = 0x3f,
4177 	FW_LASTC2E_CMD                 = 0x40,
4178 	FW_ERROR_CMD                   = 0x80,
4179 	FW_DEBUG_CMD                   = 0x81,
4180 };
4181 
4182 enum fw_cmd_cap {
4183 	FW_CMD_CAP_PF                  = 0x01,
4184 	FW_CMD_CAP_DMAQ                = 0x02,
4185 	FW_CMD_CAP_PORT                = 0x04,
4186 	FW_CMD_CAP_PORTPROMISC         = 0x08,
4187 	FW_CMD_CAP_PORTSTATS           = 0x10,
4188 	FW_CMD_CAP_VF                  = 0x80,
4189 };
4190 
4191 /*
4192  * Generic command header flit0
4193  */
4194 struct fw_cmd_hdr {
4195 	__be32 hi;
4196 	__be32 lo;
4197 };
4198 
4199 #define S_FW_CMD_OP		24
4200 #define M_FW_CMD_OP		0xff
4201 #define V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
4202 #define G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
4203 
4204 #define S_FW_CMD_REQUEST	23
4205 #define M_FW_CMD_REQUEST	0x1
4206 #define V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
4207 #define G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
4208 #define F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)
4209 
4210 #define S_FW_CMD_READ		22
4211 #define M_FW_CMD_READ		0x1
4212 #define V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
4213 #define G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
4214 #define F_FW_CMD_READ		V_FW_CMD_READ(1U)
4215 
4216 #define S_FW_CMD_WRITE		21
4217 #define M_FW_CMD_WRITE		0x1
4218 #define V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
4219 #define G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
4220 #define F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)
4221 
4222 #define S_FW_CMD_EXEC		20
4223 #define M_FW_CMD_EXEC		0x1
4224 #define V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
4225 #define G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
4226 #define F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)
4227 
4228 #define S_FW_CMD_RAMASK		20
4229 #define M_FW_CMD_RAMASK		0xf
4230 #define V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
4231 #define G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
4232 
4233 #define S_FW_CMD_RETVAL		8
4234 #define M_FW_CMD_RETVAL		0xff
4235 #define V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
4236 #define G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
4237 
4238 #define S_FW_CMD_LEN16		0
4239 #define M_FW_CMD_LEN16		0xff
4240 #define V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
4241 #define G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
4242 
4243 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
4244 
4245 /*
4246  *	address spaces
4247  */
4248 enum fw_ldst_addrspc {
4249 	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
4250 	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
4251 	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
4252 	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
4253 	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
4254 	FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
4255 	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
4256 	FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
4257 	FW_LDST_ADDRSPC_MDIO      = 0x0018,
4258 	FW_LDST_ADDRSPC_MPS       = 0x0020,
4259 	FW_LDST_ADDRSPC_FUNC      = 0x0028,
4260 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
4261 	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
4262 	FW_LDST_ADDRSPC_LE	  = 0x0030,
4263 	FW_LDST_ADDRSPC_I2C       = 0x0038,
4264 	FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
4265 	FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,
4266 	FW_LDST_ADDRSPC_PCIE_PHY  = 0x0042,
4267 	FW_LDST_ADDRSPC_CIM_Q	  = 0x0048,
4268 };
4269 
4270 /*
4271  *	MDIO VSC8634 register access control field
4272  */
4273 enum fw_ldst_mdio_vsc8634_aid {
4274 	FW_LDST_MDIO_VS_STANDARD,
4275 	FW_LDST_MDIO_VS_EXTENDED,
4276 	FW_LDST_MDIO_VS_GPIO
4277 };
4278 
4279 enum fw_ldst_mps_fid {
4280 	FW_LDST_MPS_ATRB,
4281 	FW_LDST_MPS_RPLC
4282 };
4283 
4284 enum fw_ldst_func_access_ctl {
4285 	FW_LDST_FUNC_ACC_CTL_VIID,
4286 	FW_LDST_FUNC_ACC_CTL_FID
4287 };
4288 
4289 enum fw_ldst_func_mod_index {
4290 	FW_LDST_FUNC_MPS
4291 };
4292 
4293 struct fw_ldst_cmd {
4294 	__be32 op_to_addrspace;
4295 	__be32 cycles_to_len16;
4296 	union fw_ldst {
4297 		struct fw_ldst_addrval {
4298 			__be32 addr;
4299 			__be32 val;
4300 		} addrval;
4301 		struct fw_ldst_idctxt {
4302 			__be32 physid;
4303 			__be32 msg_ctxtflush;
4304 			__be32 ctxt_data7;
4305 			__be32 ctxt_data6;
4306 			__be32 ctxt_data5;
4307 			__be32 ctxt_data4;
4308 			__be32 ctxt_data3;
4309 			__be32 ctxt_data2;
4310 			__be32 ctxt_data1;
4311 			__be32 ctxt_data0;
4312 		} idctxt;
4313 		struct fw_ldst_mdio {
4314 			__be16 paddr_mmd;
4315 			__be16 raddr;
4316 			__be16 vctl;
4317 			__be16 rval;
4318 		} mdio;
4319 		struct fw_ldst_cim_rq {
4320 			__u8   req_first64[8];
4321 			__u8   req_second64[8];
4322 			__u8   resp_first64[8];
4323 			__u8   resp_second64[8];
4324 			__be32 r3[2];
4325 		} cim_rq;
4326 		union fw_ldst_mps {
4327 			struct fw_ldst_mps_rplc {
4328 				__be16 fid_idx;
4329 				__be16 rplcpf_pkd;
4330 				__be32 rplc255_224;
4331 				__be32 rplc223_192;
4332 				__be32 rplc191_160;
4333 				__be32 rplc159_128;
4334 				__be32 rplc127_96;
4335 				__be32 rplc95_64;
4336 				__be32 rplc63_32;
4337 				__be32 rplc31_0;
4338 			} rplc;
4339 			struct fw_ldst_mps_atrb {
4340 				__be16 fid_mpsid;
4341 				__be16 r2[3];
4342 				__be32 r3[2];
4343 				__be32 r4;
4344 				__be32 atrb;
4345 				__be16 vlan[16];
4346 			} atrb;
4347 		} mps;
4348 		struct fw_ldst_func {
4349 			__u8   access_ctl;
4350 			__u8   mod_index;
4351 			__be16 ctl_id;
4352 			__be32 offset;
4353 			__be64 data0;
4354 			__be64 data1;
4355 		} func;
4356 		struct fw_ldst_pcie {
4357 			__u8   ctrl_to_fn;
4358 			__u8   bnum;
4359 			__u8   r;
4360 			__u8   ext_r;
4361 			__u8   select_naccess;
4362 			__u8   pcie_fn;
4363 			__be16 nset_pkd;
4364 			__be32 data[12];
4365 		} pcie;
4366 		struct fw_ldst_i2c_deprecated {
4367 			__u8   pid_pkd;
4368 			__u8   base;
4369 			__u8   boffset;
4370 			__u8   data;
4371 			__be32 r9;
4372 		} i2c_deprecated;
4373 		struct fw_ldst_i2c {
4374 			__u8   pid;
4375 			__u8   did;
4376 			__u8   boffset;
4377 			__u8   blen;
4378 			__be32 r9;
4379 			__u8   data[48];
4380 		} i2c;
4381 		struct fw_ldst_le {
4382 			__be32 index;
4383 			__be32 r9;
4384 			__u8   val[33];
4385 			__u8   r11[7];
4386 		} le;
4387 	} u;
4388 };
4389 
4390 #define S_FW_LDST_CMD_ADDRSPACE		0
4391 #define M_FW_LDST_CMD_ADDRSPACE		0xff
4392 #define V_FW_LDST_CMD_ADDRSPACE(x)	((x) << S_FW_LDST_CMD_ADDRSPACE)
4393 #define G_FW_LDST_CMD_ADDRSPACE(x)	\
4394     (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
4395 
4396 #define S_FW_LDST_CMD_CYCLES		16
4397 #define M_FW_LDST_CMD_CYCLES		0xffff
4398 #define V_FW_LDST_CMD_CYCLES(x)		((x) << S_FW_LDST_CMD_CYCLES)
4399 #define G_FW_LDST_CMD_CYCLES(x)		\
4400     (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
4401 
4402 #define S_FW_LDST_CMD_MSG		31
4403 #define M_FW_LDST_CMD_MSG		0x1
4404 #define V_FW_LDST_CMD_MSG(x)		((x) << S_FW_LDST_CMD_MSG)
4405 #define G_FW_LDST_CMD_MSG(x)		\
4406     (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
4407 #define F_FW_LDST_CMD_MSG		V_FW_LDST_CMD_MSG(1U)
4408 
4409 #define S_FW_LDST_CMD_CTXTFLUSH		30
4410 #define M_FW_LDST_CMD_CTXTFLUSH		0x1
4411 #define V_FW_LDST_CMD_CTXTFLUSH(x)	((x) << S_FW_LDST_CMD_CTXTFLUSH)
4412 #define G_FW_LDST_CMD_CTXTFLUSH(x)	\
4413     (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
4414 #define F_FW_LDST_CMD_CTXTFLUSH		V_FW_LDST_CMD_CTXTFLUSH(1U)
4415 
4416 #define S_FW_LDST_CMD_PADDR		8
4417 #define M_FW_LDST_CMD_PADDR		0x1f
4418 #define V_FW_LDST_CMD_PADDR(x)		((x) << S_FW_LDST_CMD_PADDR)
4419 #define G_FW_LDST_CMD_PADDR(x)		\
4420     (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
4421 
4422 #define S_FW_LDST_CMD_MMD		0
4423 #define M_FW_LDST_CMD_MMD		0x1f
4424 #define V_FW_LDST_CMD_MMD(x)		((x) << S_FW_LDST_CMD_MMD)
4425 #define G_FW_LDST_CMD_MMD(x)		\
4426     (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
4427 
4428 #define S_FW_LDST_CMD_FID		15
4429 #define M_FW_LDST_CMD_FID		0x1
4430 #define V_FW_LDST_CMD_FID(x)		((x) << S_FW_LDST_CMD_FID)
4431 #define G_FW_LDST_CMD_FID(x)		\
4432     (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
4433 #define F_FW_LDST_CMD_FID		V_FW_LDST_CMD_FID(1U)
4434 
4435 #define S_FW_LDST_CMD_IDX		0
4436 #define M_FW_LDST_CMD_IDX		0x7fff
4437 #define V_FW_LDST_CMD_IDX(x)		((x) << S_FW_LDST_CMD_IDX)
4438 #define G_FW_LDST_CMD_IDX(x)		\
4439     (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
4440 
4441 #define S_FW_LDST_CMD_RPLCPF		0
4442 #define M_FW_LDST_CMD_RPLCPF		0xff
4443 #define V_FW_LDST_CMD_RPLCPF(x)		((x) << S_FW_LDST_CMD_RPLCPF)
4444 #define G_FW_LDST_CMD_RPLCPF(x)		\
4445     (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
4446 
4447 #define S_FW_LDST_CMD_MPSID		0
4448 #define M_FW_LDST_CMD_MPSID		0x7fff
4449 #define V_FW_LDST_CMD_MPSID(x)		((x) << S_FW_LDST_CMD_MPSID)
4450 #define G_FW_LDST_CMD_MPSID(x)		\
4451     (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
4452 
4453 #define S_FW_LDST_CMD_CTRL		7
4454 #define M_FW_LDST_CMD_CTRL		0x1
4455 #define V_FW_LDST_CMD_CTRL(x)		((x) << S_FW_LDST_CMD_CTRL)
4456 #define G_FW_LDST_CMD_CTRL(x)		\
4457     (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
4458 #define F_FW_LDST_CMD_CTRL		V_FW_LDST_CMD_CTRL(1U)
4459 
4460 #define S_FW_LDST_CMD_LC		4
4461 #define M_FW_LDST_CMD_LC		0x1
4462 #define V_FW_LDST_CMD_LC(x)		((x) << S_FW_LDST_CMD_LC)
4463 #define G_FW_LDST_CMD_LC(x)		\
4464     (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
4465 #define F_FW_LDST_CMD_LC		V_FW_LDST_CMD_LC(1U)
4466 
4467 #define S_FW_LDST_CMD_AI		3
4468 #define M_FW_LDST_CMD_AI		0x1
4469 #define V_FW_LDST_CMD_AI(x)		((x) << S_FW_LDST_CMD_AI)
4470 #define G_FW_LDST_CMD_AI(x)		\
4471     (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
4472 #define F_FW_LDST_CMD_AI		V_FW_LDST_CMD_AI(1U)
4473 
4474 #define S_FW_LDST_CMD_FN		0
4475 #define M_FW_LDST_CMD_FN		0x7
4476 #define V_FW_LDST_CMD_FN(x)		((x) << S_FW_LDST_CMD_FN)
4477 #define G_FW_LDST_CMD_FN(x)		\
4478     (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
4479 
4480 #define S_FW_LDST_CMD_SELECT		4
4481 #define M_FW_LDST_CMD_SELECT		0xf
4482 #define V_FW_LDST_CMD_SELECT(x)		((x) << S_FW_LDST_CMD_SELECT)
4483 #define G_FW_LDST_CMD_SELECT(x)		\
4484     (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
4485 
4486 #define S_FW_LDST_CMD_NACCESS		0
4487 #define M_FW_LDST_CMD_NACCESS		0xf
4488 #define V_FW_LDST_CMD_NACCESS(x)	((x) << S_FW_LDST_CMD_NACCESS)
4489 #define G_FW_LDST_CMD_NACCESS(x)	\
4490     (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
4491 
4492 #define S_FW_LDST_CMD_NSET		14
4493 #define M_FW_LDST_CMD_NSET		0x3
4494 #define V_FW_LDST_CMD_NSET(x)		((x) << S_FW_LDST_CMD_NSET)
4495 #define G_FW_LDST_CMD_NSET(x)		\
4496     (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
4497 
4498 #define S_FW_LDST_CMD_PID		6
4499 #define M_FW_LDST_CMD_PID		0x3
4500 #define V_FW_LDST_CMD_PID(x)		((x) << S_FW_LDST_CMD_PID)
4501 #define G_FW_LDST_CMD_PID(x)		\
4502     (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
4503 
4504 struct fw_reset_cmd {
4505 	__be32 op_to_write;
4506 	__be32 retval_len16;
4507 	__be32 val;
4508 	__be32 halt_pkd;
4509 };
4510 
4511 #define S_FW_RESET_CMD_HALT		31
4512 #define M_FW_RESET_CMD_HALT		0x1
4513 #define V_FW_RESET_CMD_HALT(x)		((x) << S_FW_RESET_CMD_HALT)
4514 #define G_FW_RESET_CMD_HALT(x)		\
4515     (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
4516 #define F_FW_RESET_CMD_HALT		V_FW_RESET_CMD_HALT(1U)
4517 
4518 enum {
4519 	FW_HELLO_CMD_STAGE_OS		= 0,
4520 	FW_HELLO_CMD_STAGE_PREOS0	= 1,
4521 	FW_HELLO_CMD_STAGE_PREOS1	= 2,
4522 	FW_HELLO_CMD_STAGE_POSTOS	= 3,
4523 };
4524 
4525 struct fw_hello_cmd {
4526 	__be32 op_to_write;
4527 	__be32 retval_len16;
4528 	__be32 err_to_clearinit;
4529 	__be32 fwrev;
4530 };
4531 
4532 #define S_FW_HELLO_CMD_ERR		31
4533 #define M_FW_HELLO_CMD_ERR		0x1
4534 #define V_FW_HELLO_CMD_ERR(x)		((x) << S_FW_HELLO_CMD_ERR)
4535 #define G_FW_HELLO_CMD_ERR(x)		\
4536     (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
4537 #define F_FW_HELLO_CMD_ERR		V_FW_HELLO_CMD_ERR(1U)
4538 
4539 #define S_FW_HELLO_CMD_INIT		30
4540 #define M_FW_HELLO_CMD_INIT		0x1
4541 #define V_FW_HELLO_CMD_INIT(x)		((x) << S_FW_HELLO_CMD_INIT)
4542 #define G_FW_HELLO_CMD_INIT(x)		\
4543     (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
4544 #define F_FW_HELLO_CMD_INIT		V_FW_HELLO_CMD_INIT(1U)
4545 
4546 #define S_FW_HELLO_CMD_MASTERDIS	29
4547 #define M_FW_HELLO_CMD_MASTERDIS	0x1
4548 #define V_FW_HELLO_CMD_MASTERDIS(x)	((x) << S_FW_HELLO_CMD_MASTERDIS)
4549 #define G_FW_HELLO_CMD_MASTERDIS(x)	\
4550     (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
4551 #define F_FW_HELLO_CMD_MASTERDIS	V_FW_HELLO_CMD_MASTERDIS(1U)
4552 
4553 #define S_FW_HELLO_CMD_MASTERFORCE	28
4554 #define M_FW_HELLO_CMD_MASTERFORCE	0x1
4555 #define V_FW_HELLO_CMD_MASTERFORCE(x)	((x) << S_FW_HELLO_CMD_MASTERFORCE)
4556 #define G_FW_HELLO_CMD_MASTERFORCE(x)	\
4557     (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
4558 #define F_FW_HELLO_CMD_MASTERFORCE	V_FW_HELLO_CMD_MASTERFORCE(1U)
4559 
4560 #define S_FW_HELLO_CMD_MBMASTER		24
4561 #define M_FW_HELLO_CMD_MBMASTER		0xf
4562 #define V_FW_HELLO_CMD_MBMASTER(x)	((x) << S_FW_HELLO_CMD_MBMASTER)
4563 #define G_FW_HELLO_CMD_MBMASTER(x)	\
4564     (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
4565 
4566 #define S_FW_HELLO_CMD_MBASYNCNOTINT	23
4567 #define M_FW_HELLO_CMD_MBASYNCNOTINT	0x1
4568 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
4569 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x)	\
4570     (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
4571 #define F_FW_HELLO_CMD_MBASYNCNOTINT	V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
4572 
4573 #define S_FW_HELLO_CMD_MBASYNCNOT	20
4574 #define M_FW_HELLO_CMD_MBASYNCNOT	0x7
4575 #define V_FW_HELLO_CMD_MBASYNCNOT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOT)
4576 #define G_FW_HELLO_CMD_MBASYNCNOT(x)	\
4577     (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
4578 
4579 #define S_FW_HELLO_CMD_STAGE		17
4580 #define M_FW_HELLO_CMD_STAGE		0x7
4581 #define V_FW_HELLO_CMD_STAGE(x)		((x) << S_FW_HELLO_CMD_STAGE)
4582 #define G_FW_HELLO_CMD_STAGE(x)		\
4583     (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
4584 
4585 #define S_FW_HELLO_CMD_CLEARINIT	16
4586 #define M_FW_HELLO_CMD_CLEARINIT	0x1
4587 #define V_FW_HELLO_CMD_CLEARINIT(x)	((x) << S_FW_HELLO_CMD_CLEARINIT)
4588 #define G_FW_HELLO_CMD_CLEARINIT(x)	\
4589     (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
4590 #define F_FW_HELLO_CMD_CLEARINIT	V_FW_HELLO_CMD_CLEARINIT(1U)
4591 
4592 struct fw_bye_cmd {
4593 	__be32 op_to_write;
4594 	__be32 retval_len16;
4595 	__be64 r3;
4596 };
4597 
4598 struct fw_initialize_cmd {
4599 	__be32 op_to_write;
4600 	__be32 retval_len16;
4601 	__be64 r3;
4602 };
4603 
4604 enum fw_caps_config_hm {
4605 	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
4606 	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
4607 	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
4608 	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
4609 	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
4610 	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
4611 	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
4612 	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
4613 	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
4614 	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
4615 	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
4616 	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
4617 	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
4618 	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
4619 	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
4620 	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
4621 	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
4622 	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
4623 	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
4624 	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
4625 	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
4626 	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
4627 	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
4628 	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
4629 };
4630 
4631 /*
4632  * The VF Register Map.
4633  *
4634  * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
4635  * bus module (PL) and CPU Interface Module (CIM) components are mapped via
4636  * the Slice to Module Map Table (see below) in the Physical Function Register
4637  * Map.  The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
4638  * and Offset registers in the PF Register Map.  The MBDATA base address is
4639  * quite constrained as it determines the Mailbox Data addresses for both PFs
4640  * and VFs, and therefore must fit in both the VF and PF Register Maps without
4641  * overlapping other registers.
4642  */
4643 #define FW_T4VF_SGE_BASE_ADDR      0x0000
4644 #define FW_T4VF_MPS_BASE_ADDR      0x0100
4645 #define FW_T4VF_PL_BASE_ADDR       0x0200
4646 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
4647 #define FW_T6VF_MBDATA_BASE_ADDR   0x0280 /* aligned to mbox size 128B */
4648 #define FW_T4VF_CIM_BASE_ADDR      0x0300
4649 
4650 #define FW_T4VF_REGMAP_START       0x0000
4651 #define FW_T4VF_REGMAP_SIZE        0x0400
4652 
4653 enum fw_caps_config_nbm {
4654 	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
4655 	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
4656 };
4657 
4658 enum fw_caps_config_link {
4659 	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
4660 	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
4661 	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
4662 };
4663 
4664 enum fw_caps_config_switch {
4665 	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
4666 	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
4667 };
4668 
4669 enum fw_caps_config_nic {
4670 	FW_CAPS_CONFIG_NIC		= 0x00000001,
4671 	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
4672 	FW_CAPS_CONFIG_NIC_IDS		= 0x00000004,
4673 	FW_CAPS_CONFIG_NIC_UM		= 0x00000008,
4674 	FW_CAPS_CONFIG_NIC_UM_ISGL	= 0x00000010,
4675 	FW_CAPS_CONFIG_NIC_HASHFILTER	= 0x00000020,
4676 	FW_CAPS_CONFIG_NIC_ETHOFLD	= 0x00000040,
4677 };
4678 
4679 enum fw_caps_config_toe {
4680 	FW_CAPS_CONFIG_TOE		= 0x00000001,
4681 };
4682 
4683 enum fw_caps_config_rdma {
4684 	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
4685 	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
4686 };
4687 
4688 enum fw_caps_config_iscsi {
4689 	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
4690 	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
4691 	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
4692 	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
4693 	FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
4694 	FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
4695 	FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
4696 	FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
4697 	FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
4698 };
4699 
4700 enum fw_caps_config_crypto {
4701 	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
4702 	FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
4703 };
4704 
4705 enum fw_caps_config_fcoe {
4706 	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
4707 	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
4708 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
4709 	FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
4710 	FW_CAPS_CONFIG_POFCOE_TARGET    = 0x00000010,
4711 };
4712 
4713 enum fw_memtype_cf {
4714 	FW_MEMTYPE_CF_EDC0		= FW_MEMTYPE_EDC0,
4715 	FW_MEMTYPE_CF_EDC1		= FW_MEMTYPE_EDC1,
4716 	FW_MEMTYPE_CF_EXTMEM		= FW_MEMTYPE_EXTMEM,
4717 	FW_MEMTYPE_CF_FLASH		= FW_MEMTYPE_FLASH,
4718 	FW_MEMTYPE_CF_INTERNAL		= FW_MEMTYPE_INTERNAL,
4719 	FW_MEMTYPE_CF_EXTMEM1		= FW_MEMTYPE_EXTMEM1,
4720 };
4721 
4722 struct fw_caps_config_cmd {
4723 	__be32 op_to_write;
4724 	__be32 cfvalid_to_len16;
4725 	__be32 r2;
4726 	__be32 hwmbitmap;
4727 	__be16 nbmcaps;
4728 	__be16 linkcaps;
4729 	__be16 switchcaps;
4730 	__be16 r3;
4731 	__be16 niccaps;
4732 	__be16 toecaps;
4733 	__be16 rdmacaps;
4734 	__be16 cryptocaps;
4735 	__be16 iscsicaps;
4736 	__be16 fcoecaps;
4737 	__be32 cfcsum;
4738 	__be32 finiver;
4739 	__be32 finicsum;
4740 };
4741 
4742 #define S_FW_CAPS_CONFIG_CMD_CFVALID	27
4743 #define M_FW_CAPS_CONFIG_CMD_CFVALID	0x1
4744 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x)	((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
4745 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x)	\
4746     (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
4747 #define F_FW_CAPS_CONFIG_CMD_CFVALID	V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
4748 
4749 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF	24
4750 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF	0x7
4751 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4752     ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4753 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4754     (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
4755      M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4756 
4757 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
4758 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
4759 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4760     ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4761 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4762     (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
4763      M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4764 
4765 /*
4766  * params command mnemonics
4767  */
4768 enum fw_params_mnem {
4769 	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
4770 	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
4771 	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
4772 	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
4773 	FW_PARAMS_MNEM_CHNET		= 5,	/* chnet params */
4774 	FW_PARAMS_MNEM_LAST
4775 };
4776 
4777 /*
4778  * device parameters
4779  */
4780 #define S_FW_PARAMS_PARAM_FILTER_MODE 16
4781 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
4782 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
4783     ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
4784 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
4785     (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
4786 	M_FW_PARAMS_PARAM_FILTER_MODE)
4787 
4788 #define S_FW_PARAMS_PARAM_FILTER_MASK 0
4789 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
4790 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
4791     ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
4792 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
4793     (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
4794 	M_FW_PARAMS_PARAM_FILTER_MASK)
4795 
4796 enum fw_params_param_dev {
4797 	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
4798 	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
4799 	FW_PARAMS_PARAM_DEV_NTID	= 0x02, /* reads the number of TIDs
4800 						 * allocated by the device's
4801 						 * Lookup Engine
4802 						 */
4803 	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
4804 	FW_PARAMS_PARAM_DEV_INTFVER_NIC	= 0x04,
4805 	FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
4806 	FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
4807 	FW_PARAMS_PARAM_DEV_INTFVER_RI	= 0x07,
4808 	FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
4809 	FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
4810 	FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
4811 	FW_PARAMS_PARAM_DEV_FWREV	= 0x0B,
4812 	FW_PARAMS_PARAM_DEV_TPREV	= 0x0C,
4813 	FW_PARAMS_PARAM_DEV_CF		= 0x0D,
4814 	FW_PARAMS_PARAM_DEV_BYPASS	= 0x0E,
4815 	FW_PARAMS_PARAM_DEV_PHYFW	= 0x0F,
4816 	FW_PARAMS_PARAM_DEV_LOAD	= 0x10,
4817 	FW_PARAMS_PARAM_DEV_DIAG	= 0x11,
4818 	FW_PARAMS_PARAM_DEV_UCLK	= 0x12, /* uP clock in khz */
4819 	FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
4820 						 */
4821 	FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
4822 						 */
4823 	FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
4824 	FW_PARAMS_PARAM_DEV_MCINIT	= 0x16,
4825 	FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
4826 	FW_PARAMS_PARAM_DEV_FWCACHE	= 0x18,
4827 	FW_PARAMS_PARAM_DEV_RSSINFO	= 0x19,
4828 	FW_PARAMS_PARAM_DEV_SCFGREV	= 0x1A,
4829 	FW_PARAMS_PARAM_DEV_VPDREV	= 0x1B,
4830 	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
4831 	FW_PARAMS_PARAM_DEV_FILTER2_WR	= 0x1D,
4832 
4833 	FW_PARAMS_PARAM_DEV_MPSBGMAP	= 0x1E,
4834 	FW_PARAMS_PARAM_DEV_TPCHMAP	= 0x1F,
4835 	FW_PARAMS_PARAM_DEV_HMA_SIZE	= 0x20,
4836 	FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM	= 0x21,
4837 	FW_PARAMS_PARAM_DEV_RING_BACKBONE	= 0x22,
4838 	FW_PARAMS_PARAM_DEV_PPOD_EDRAM	= 0x23,
4839 	FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR	= 0x24,
4840 	FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25,
4841 	FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
4842 	FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
4843 	FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
4844 	FW_PARAMS_PARAM_DEV_DBQ_TIMER	= 0x29,
4845 	FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
4846 	FW_PARAMS_PARAM_DEV_NUM_TM_CLASS	= 0x2B,
4847 	FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C,
4848 	FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D,
4849 	FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
4850 };
4851 
4852 /*
4853  * dev bypass parameters; actions and modes
4854  */
4855 enum fw_params_param_dev_bypass {
4856 
4857 	/* actions
4858 	 */
4859 	FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
4860 	FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
4861 
4862 	/* modes
4863 	 */
4864 	FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
4865 	FW_PARAMS_PARAM_DEV_BYPASS_DROP	= 0x1,
4866 	FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
4867 };
4868 
4869 enum fw_params_param_dev_phyfw {
4870 	FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
4871 	FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
4872 };
4873 
4874 enum fw_params_param_dev_diag {
4875 	FW_PARAM_DEV_DIAG_TMP		= 0x00,
4876 	FW_PARAM_DEV_DIAG_VDD		= 0x01,
4877 	FW_PARAM_DEV_DIAG_MAXTMPTHRESH	= 0x02,
4878 };
4879 
4880 enum fw_params_param_dev_filter{
4881 	FW_PARAM_DEV_FILTER_VNIC_MODE	= 0x00,
4882 	FW_PARAM_DEV_FILTER_MODE_MASK	= 0x01,
4883 };
4884 
4885 enum fw_params_param_dev_fwcache {
4886 	FW_PARAM_DEV_FWCACHE_FLUSH	= 0x00,
4887 	FW_PARAM_DEV_FWCACHE_FLUSHINV	= 0x01,
4888 };
4889 
4890 /*
4891  * physical and virtual function parameters
4892  */
4893 enum fw_params_param_pfvf {
4894 	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
4895 	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
4896 	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
4897 	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
4898 	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
4899 	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
4900 	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
4901 	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
4902 	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
4903 	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
4904 	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
4905 	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
4906 	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
4907 	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
4908 	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
4909 	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
4910 	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
4911 	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
4912 	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
4913 	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
4914 	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
4915 	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
4916 	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
4917 	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
4918 	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
4919 	FW_PARAMS_PARAM_PFVF_SRQ_START	= 0x19,
4920 	FW_PARAMS_PARAM_PFVF_SRQ_END	= 0x1A,
4921 	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
4922 	FW_PARAMS_PARAM_PFVF_VIID	= 0x24,
4923 	FW_PARAMS_PARAM_PFVF_CPMASK	= 0x25,
4924 	FW_PARAMS_PARAM_PFVF_OCQ_START	= 0x26,
4925 	FW_PARAMS_PARAM_PFVF_OCQ_END	= 0x27,
4926 	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
4927 	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
4928 	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
4929 	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
4930 	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
4931 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
4932 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
4933 	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
4934 	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
4935 	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
4936 	FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
4937 	FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
4938 	FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
4939         FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
4940 	FW_PARAMS_PARAM_PFVF_RAWF_START	= 0x36,
4941 	FW_PARAMS_PARAM_PFVF_RAWF_END	= 0x37,
4942 	FW_PARAMS_PARAM_PFVF_RSSKEYINFO	= 0x38,
4943 	FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
4944 	FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
4945 	FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
4946 	FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
4947 	FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
4948 	FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
4949 	FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
4950 	FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
4951 };
4952 
4953 /*
4954  * virtual link state as seen by the specified VF
4955  */
4956 enum vf_link_states {
4957 	VF_LINK_STATE_AUTO		= 0x00,
4958 	VF_LINK_STATE_ENABLE		= 0x01,
4959 	VF_LINK_STATE_DISABLE		= 0x02,
4960 };
4961 
4962 /*
4963  * dma queue parameters
4964  */
4965 enum fw_params_param_dmaq {
4966 	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
4967 	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
4968 	FW_PARAMS_PARAM_DMAQ_IQ_INTIDX	= 0x02,
4969 	FW_PARAMS_PARAM_DMAQ_IQ_DCA	= 0x03,
4970 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
4971 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
4972 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
4973 	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
4974 	FW_PARAMS_PARAM_DMAQ_EQ_DCA	= 0x14,
4975 	FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX	= 0x15,
4976 	FW_PARAMS_PARAM_DMAQ_CONM_CTXT	= 0x20,
4977 	FW_PARAMS_PARAM_DMAQ_FLM_DCA	= 0x30
4978 };
4979 
4980 /*
4981  * chnet parameters
4982  */
4983 enum fw_params_param_chnet {
4984 	FW_PARAMS_PARAM_CHNET_FLAGS		= 0x00,
4985 };
4986 
4987 enum fw_params_param_chnet_flags {
4988 	FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6	= 0x1,
4989 	FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD	= 0x2,
4990 	FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
4991 };
4992 
4993 #define S_FW_PARAMS_MNEM	24
4994 #define M_FW_PARAMS_MNEM	0xff
4995 #define V_FW_PARAMS_MNEM(x)	((x) << S_FW_PARAMS_MNEM)
4996 #define G_FW_PARAMS_MNEM(x)	\
4997     (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
4998 
4999 #define S_FW_PARAMS_PARAM_X	16
5000 #define M_FW_PARAMS_PARAM_X	0xff
5001 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
5002 #define G_FW_PARAMS_PARAM_X(x) \
5003     (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
5004 
5005 #define S_FW_PARAMS_PARAM_Y	8
5006 #define M_FW_PARAMS_PARAM_Y	0xff
5007 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
5008 #define G_FW_PARAMS_PARAM_Y(x) \
5009     (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
5010 
5011 #define S_FW_PARAMS_PARAM_Z	0
5012 #define M_FW_PARAMS_PARAM_Z	0xff
5013 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
5014 #define G_FW_PARAMS_PARAM_Z(x) \
5015     (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
5016 
5017 #define S_FW_PARAMS_PARAM_XYZ	0
5018 #define M_FW_PARAMS_PARAM_XYZ	0xffffff
5019 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
5020 #define G_FW_PARAMS_PARAM_XYZ(x) \
5021     (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
5022 
5023 #define S_FW_PARAMS_PARAM_YZ	0
5024 #define M_FW_PARAMS_PARAM_YZ	0xffff
5025 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
5026 #define G_FW_PARAMS_PARAM_YZ(x) \
5027     (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
5028 
5029 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
5030 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
5031 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
5032     ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
5033 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
5034     (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
5035 	M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
5036 
5037 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
5038 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
5039 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
5040     ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
5041 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
5042     (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
5043 	M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
5044 
5045 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST	0
5046 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST	0x7ff
5047 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
5048     ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
5049 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
5050     (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
5051 
5052 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE	29
5053 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE	0x7
5054 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x)	\
5055     ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
5056 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x)	\
5057     (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
5058      M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
5059 
5060 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX	0
5061 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX	0x3ff
5062 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x)	\
5063     ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
5064 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x)	\
5065     (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
5066      M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
5067 
5068 struct fw_params_cmd {
5069 	__be32 op_to_vfn;
5070 	__be32 retval_len16;
5071 	struct fw_params_param {
5072 		__be32 mnem;
5073 		__be32 val;
5074 	} param[7];
5075 };
5076 
5077 #define S_FW_PARAMS_CMD_PFN		8
5078 #define M_FW_PARAMS_CMD_PFN		0x7
5079 #define V_FW_PARAMS_CMD_PFN(x)		((x) << S_FW_PARAMS_CMD_PFN)
5080 #define G_FW_PARAMS_CMD_PFN(x)		\
5081     (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
5082 
5083 #define S_FW_PARAMS_CMD_VFN		0
5084 #define M_FW_PARAMS_CMD_VFN		0xff
5085 #define V_FW_PARAMS_CMD_VFN(x)		((x) << S_FW_PARAMS_CMD_VFN)
5086 #define G_FW_PARAMS_CMD_VFN(x)		\
5087     (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
5088 
5089 struct fw_pfvf_cmd {
5090 	__be32 op_to_vfn;
5091 	__be32 retval_len16;
5092 	__be32 niqflint_niq;
5093 	__be32 type_to_neq;
5094 	__be32 tc_to_nexactf;
5095 	__be32 r_caps_to_nethctrl;
5096 	__be16 nricq;
5097 	__be16 nriqp;
5098 	__be32 r4;
5099 };
5100 
5101 #define S_FW_PFVF_CMD_PFN		8
5102 #define M_FW_PFVF_CMD_PFN		0x7
5103 #define V_FW_PFVF_CMD_PFN(x)		((x) << S_FW_PFVF_CMD_PFN)
5104 #define G_FW_PFVF_CMD_PFN(x)		\
5105     (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
5106 
5107 #define S_FW_PFVF_CMD_VFN		0
5108 #define M_FW_PFVF_CMD_VFN		0xff
5109 #define V_FW_PFVF_CMD_VFN(x)		((x) << S_FW_PFVF_CMD_VFN)
5110 #define G_FW_PFVF_CMD_VFN(x)		\
5111     (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
5112 
5113 #define S_FW_PFVF_CMD_NIQFLINT		20
5114 #define M_FW_PFVF_CMD_NIQFLINT		0xfff
5115 #define V_FW_PFVF_CMD_NIQFLINT(x)	((x) << S_FW_PFVF_CMD_NIQFLINT)
5116 #define G_FW_PFVF_CMD_NIQFLINT(x)	\
5117     (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
5118 
5119 #define S_FW_PFVF_CMD_NIQ		0
5120 #define M_FW_PFVF_CMD_NIQ		0xfffff
5121 #define V_FW_PFVF_CMD_NIQ(x)		((x) << S_FW_PFVF_CMD_NIQ)
5122 #define G_FW_PFVF_CMD_NIQ(x)		\
5123     (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
5124 
5125 #define S_FW_PFVF_CMD_TYPE		31
5126 #define M_FW_PFVF_CMD_TYPE		0x1
5127 #define V_FW_PFVF_CMD_TYPE(x)		((x) << S_FW_PFVF_CMD_TYPE)
5128 #define G_FW_PFVF_CMD_TYPE(x)		\
5129     (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
5130 #define F_FW_PFVF_CMD_TYPE		V_FW_PFVF_CMD_TYPE(1U)
5131 
5132 #define S_FW_PFVF_CMD_CMASK		24
5133 #define M_FW_PFVF_CMD_CMASK		0xf
5134 #define V_FW_PFVF_CMD_CMASK(x)		((x) << S_FW_PFVF_CMD_CMASK)
5135 #define G_FW_PFVF_CMD_CMASK(x)		\
5136     (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
5137 
5138 #define S_FW_PFVF_CMD_PMASK		20
5139 #define M_FW_PFVF_CMD_PMASK		0xf
5140 #define V_FW_PFVF_CMD_PMASK(x)		((x) << S_FW_PFVF_CMD_PMASK)
5141 #define G_FW_PFVF_CMD_PMASK(x)		\
5142     (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
5143 
5144 #define S_FW_PFVF_CMD_NEQ		0
5145 #define M_FW_PFVF_CMD_NEQ		0xfffff
5146 #define V_FW_PFVF_CMD_NEQ(x)		((x) << S_FW_PFVF_CMD_NEQ)
5147 #define G_FW_PFVF_CMD_NEQ(x)		\
5148     (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
5149 
5150 #define S_FW_PFVF_CMD_TC		24
5151 #define M_FW_PFVF_CMD_TC		0xff
5152 #define V_FW_PFVF_CMD_TC(x)		((x) << S_FW_PFVF_CMD_TC)
5153 #define G_FW_PFVF_CMD_TC(x)		\
5154     (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
5155 
5156 #define S_FW_PFVF_CMD_NVI		16
5157 #define M_FW_PFVF_CMD_NVI		0xff
5158 #define V_FW_PFVF_CMD_NVI(x)		((x) << S_FW_PFVF_CMD_NVI)
5159 #define G_FW_PFVF_CMD_NVI(x)		\
5160     (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
5161 
5162 #define S_FW_PFVF_CMD_NEXACTF		0
5163 #define M_FW_PFVF_CMD_NEXACTF		0xffff
5164 #define V_FW_PFVF_CMD_NEXACTF(x)	((x) << S_FW_PFVF_CMD_NEXACTF)
5165 #define G_FW_PFVF_CMD_NEXACTF(x)	\
5166     (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
5167 
5168 #define S_FW_PFVF_CMD_R_CAPS		24
5169 #define M_FW_PFVF_CMD_R_CAPS		0xff
5170 #define V_FW_PFVF_CMD_R_CAPS(x)		((x) << S_FW_PFVF_CMD_R_CAPS)
5171 #define G_FW_PFVF_CMD_R_CAPS(x)		\
5172     (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
5173 
5174 #define S_FW_PFVF_CMD_WX_CAPS		16
5175 #define M_FW_PFVF_CMD_WX_CAPS		0xff
5176 #define V_FW_PFVF_CMD_WX_CAPS(x)	((x) << S_FW_PFVF_CMD_WX_CAPS)
5177 #define G_FW_PFVF_CMD_WX_CAPS(x)	\
5178     (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
5179 
5180 #define S_FW_PFVF_CMD_NETHCTRL		0
5181 #define M_FW_PFVF_CMD_NETHCTRL		0xffff
5182 #define V_FW_PFVF_CMD_NETHCTRL(x)	((x) << S_FW_PFVF_CMD_NETHCTRL)
5183 #define G_FW_PFVF_CMD_NETHCTRL(x)	\
5184     (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
5185 
5186 /*
5187  *	ingress queue type; the first 1K ingress queues can have associated 0,
5188  *	1 or 2 free lists and an interrupt, all other ingress queues lack these
5189  *	capabilities
5190  */
5191 enum fw_iq_type {
5192 	FW_IQ_TYPE_FL_INT_CAP,
5193 	FW_IQ_TYPE_NO_FL_INT_CAP,
5194 	FW_IQ_TYPE_VF_CQ
5195 };
5196 
5197 enum fw_iq_iqtype {
5198 	FW_IQ_IQTYPE_OTHER,
5199 	FW_IQ_IQTYPE_NIC,
5200 	FW_IQ_IQTYPE_OFLD,
5201 };
5202 
5203 struct fw_iq_cmd {
5204 	__be32 op_to_vfn;
5205 	__be32 alloc_to_len16;
5206 	__be16 physiqid;
5207 	__be16 iqid;
5208 	__be16 fl0id;
5209 	__be16 fl1id;
5210 	__be32 type_to_iqandstindex;
5211 	__be16 iqdroprss_to_iqesize;
5212 	__be16 iqsize;
5213 	__be64 iqaddr;
5214 	__be32 iqns_to_fl0congen;
5215 	__be16 fl0dcaen_to_fl0cidxfthresh;
5216 	__be16 fl0size;
5217 	__be64 fl0addr;
5218 	__be32 fl1cngchmap_to_fl1congen;
5219 	__be16 fl1dcaen_to_fl1cidxfthresh;
5220 	__be16 fl1size;
5221 	__be64 fl1addr;
5222 };
5223 
5224 #define S_FW_IQ_CMD_PFN			8
5225 #define M_FW_IQ_CMD_PFN			0x7
5226 #define V_FW_IQ_CMD_PFN(x)		((x) << S_FW_IQ_CMD_PFN)
5227 #define G_FW_IQ_CMD_PFN(x)		\
5228     (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
5229 
5230 #define S_FW_IQ_CMD_VFN			0
5231 #define M_FW_IQ_CMD_VFN			0xff
5232 #define V_FW_IQ_CMD_VFN(x)		((x) << S_FW_IQ_CMD_VFN)
5233 #define G_FW_IQ_CMD_VFN(x)		\
5234     (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
5235 
5236 #define S_FW_IQ_CMD_ALLOC		31
5237 #define M_FW_IQ_CMD_ALLOC		0x1
5238 #define V_FW_IQ_CMD_ALLOC(x)		((x) << S_FW_IQ_CMD_ALLOC)
5239 #define G_FW_IQ_CMD_ALLOC(x)		\
5240     (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
5241 #define F_FW_IQ_CMD_ALLOC		V_FW_IQ_CMD_ALLOC(1U)
5242 
5243 #define S_FW_IQ_CMD_FREE		30
5244 #define M_FW_IQ_CMD_FREE		0x1
5245 #define V_FW_IQ_CMD_FREE(x)		((x) << S_FW_IQ_CMD_FREE)
5246 #define G_FW_IQ_CMD_FREE(x)		\
5247     (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
5248 #define F_FW_IQ_CMD_FREE		V_FW_IQ_CMD_FREE(1U)
5249 
5250 #define S_FW_IQ_CMD_MODIFY		29
5251 #define M_FW_IQ_CMD_MODIFY		0x1
5252 #define V_FW_IQ_CMD_MODIFY(x)		((x) << S_FW_IQ_CMD_MODIFY)
5253 #define G_FW_IQ_CMD_MODIFY(x)		\
5254     (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
5255 #define F_FW_IQ_CMD_MODIFY		V_FW_IQ_CMD_MODIFY(1U)
5256 
5257 #define S_FW_IQ_CMD_IQSTART		28
5258 #define M_FW_IQ_CMD_IQSTART		0x1
5259 #define V_FW_IQ_CMD_IQSTART(x)		((x) << S_FW_IQ_CMD_IQSTART)
5260 #define G_FW_IQ_CMD_IQSTART(x)		\
5261     (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
5262 #define F_FW_IQ_CMD_IQSTART		V_FW_IQ_CMD_IQSTART(1U)
5263 
5264 #define S_FW_IQ_CMD_IQSTOP		27
5265 #define M_FW_IQ_CMD_IQSTOP		0x1
5266 #define V_FW_IQ_CMD_IQSTOP(x)		((x) << S_FW_IQ_CMD_IQSTOP)
5267 #define G_FW_IQ_CMD_IQSTOP(x)		\
5268     (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
5269 #define F_FW_IQ_CMD_IQSTOP		V_FW_IQ_CMD_IQSTOP(1U)
5270 
5271 #define S_FW_IQ_CMD_TYPE		29
5272 #define M_FW_IQ_CMD_TYPE		0x7
5273 #define V_FW_IQ_CMD_TYPE(x)		((x) << S_FW_IQ_CMD_TYPE)
5274 #define G_FW_IQ_CMD_TYPE(x)		\
5275     (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
5276 
5277 #define S_FW_IQ_CMD_IQASYNCH		28
5278 #define M_FW_IQ_CMD_IQASYNCH		0x1
5279 #define V_FW_IQ_CMD_IQASYNCH(x)		((x) << S_FW_IQ_CMD_IQASYNCH)
5280 #define G_FW_IQ_CMD_IQASYNCH(x)		\
5281     (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
5282 #define F_FW_IQ_CMD_IQASYNCH		V_FW_IQ_CMD_IQASYNCH(1U)
5283 
5284 #define S_FW_IQ_CMD_VIID		16
5285 #define M_FW_IQ_CMD_VIID		0xfff
5286 #define V_FW_IQ_CMD_VIID(x)		((x) << S_FW_IQ_CMD_VIID)
5287 #define G_FW_IQ_CMD_VIID(x)		\
5288     (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
5289 
5290 #define S_FW_IQ_CMD_IQANDST		15
5291 #define M_FW_IQ_CMD_IQANDST		0x1
5292 #define V_FW_IQ_CMD_IQANDST(x)		((x) << S_FW_IQ_CMD_IQANDST)
5293 #define G_FW_IQ_CMD_IQANDST(x)		\
5294     (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
5295 #define F_FW_IQ_CMD_IQANDST		V_FW_IQ_CMD_IQANDST(1U)
5296 
5297 #define S_FW_IQ_CMD_IQANUS		14
5298 #define M_FW_IQ_CMD_IQANUS		0x1
5299 #define V_FW_IQ_CMD_IQANUS(x)		((x) << S_FW_IQ_CMD_IQANUS)
5300 #define G_FW_IQ_CMD_IQANUS(x)		\
5301     (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
5302 #define F_FW_IQ_CMD_IQANUS		V_FW_IQ_CMD_IQANUS(1U)
5303 
5304 #define S_FW_IQ_CMD_IQANUD		12
5305 #define M_FW_IQ_CMD_IQANUD		0x3
5306 #define V_FW_IQ_CMD_IQANUD(x)		((x) << S_FW_IQ_CMD_IQANUD)
5307 #define G_FW_IQ_CMD_IQANUD(x)		\
5308     (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
5309 
5310 #define S_FW_IQ_CMD_IQANDSTINDEX	0
5311 #define M_FW_IQ_CMD_IQANDSTINDEX	0xfff
5312 #define V_FW_IQ_CMD_IQANDSTINDEX(x)	((x) << S_FW_IQ_CMD_IQANDSTINDEX)
5313 #define G_FW_IQ_CMD_IQANDSTINDEX(x)	\
5314     (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
5315 
5316 #define S_FW_IQ_CMD_IQDROPRSS		15
5317 #define M_FW_IQ_CMD_IQDROPRSS		0x1
5318 #define V_FW_IQ_CMD_IQDROPRSS(x)	((x) << S_FW_IQ_CMD_IQDROPRSS)
5319 #define G_FW_IQ_CMD_IQDROPRSS(x)	\
5320     (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
5321 #define F_FW_IQ_CMD_IQDROPRSS		V_FW_IQ_CMD_IQDROPRSS(1U)
5322 
5323 #define S_FW_IQ_CMD_IQGTSMODE		14
5324 #define M_FW_IQ_CMD_IQGTSMODE		0x1
5325 #define V_FW_IQ_CMD_IQGTSMODE(x)	((x) << S_FW_IQ_CMD_IQGTSMODE)
5326 #define G_FW_IQ_CMD_IQGTSMODE(x)	\
5327     (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
5328 #define F_FW_IQ_CMD_IQGTSMODE		V_FW_IQ_CMD_IQGTSMODE(1U)
5329 
5330 #define S_FW_IQ_CMD_IQPCIECH		12
5331 #define M_FW_IQ_CMD_IQPCIECH		0x3
5332 #define V_FW_IQ_CMD_IQPCIECH(x)		((x) << S_FW_IQ_CMD_IQPCIECH)
5333 #define G_FW_IQ_CMD_IQPCIECH(x)		\
5334     (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
5335 
5336 #define S_FW_IQ_CMD_IQDCAEN		11
5337 #define M_FW_IQ_CMD_IQDCAEN		0x1
5338 #define V_FW_IQ_CMD_IQDCAEN(x)		((x) << S_FW_IQ_CMD_IQDCAEN)
5339 #define G_FW_IQ_CMD_IQDCAEN(x)		\
5340     (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
5341 #define F_FW_IQ_CMD_IQDCAEN		V_FW_IQ_CMD_IQDCAEN(1U)
5342 
5343 #define S_FW_IQ_CMD_IQDCACPU		6
5344 #define M_FW_IQ_CMD_IQDCACPU		0x1f
5345 #define V_FW_IQ_CMD_IQDCACPU(x)		((x) << S_FW_IQ_CMD_IQDCACPU)
5346 #define G_FW_IQ_CMD_IQDCACPU(x)		\
5347     (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
5348 
5349 #define S_FW_IQ_CMD_IQINTCNTTHRESH	4
5350 #define M_FW_IQ_CMD_IQINTCNTTHRESH	0x3
5351 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x)	((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
5352 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x)	\
5353     (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
5354 
5355 #define S_FW_IQ_CMD_IQO			3
5356 #define M_FW_IQ_CMD_IQO			0x1
5357 #define V_FW_IQ_CMD_IQO(x)		((x) << S_FW_IQ_CMD_IQO)
5358 #define G_FW_IQ_CMD_IQO(x)		\
5359     (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
5360 #define F_FW_IQ_CMD_IQO			V_FW_IQ_CMD_IQO(1U)
5361 
5362 #define S_FW_IQ_CMD_IQCPRIO		2
5363 #define M_FW_IQ_CMD_IQCPRIO		0x1
5364 #define V_FW_IQ_CMD_IQCPRIO(x)		((x) << S_FW_IQ_CMD_IQCPRIO)
5365 #define G_FW_IQ_CMD_IQCPRIO(x)		\
5366     (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
5367 #define F_FW_IQ_CMD_IQCPRIO		V_FW_IQ_CMD_IQCPRIO(1U)
5368 
5369 #define S_FW_IQ_CMD_IQESIZE		0
5370 #define M_FW_IQ_CMD_IQESIZE		0x3
5371 #define V_FW_IQ_CMD_IQESIZE(x)		((x) << S_FW_IQ_CMD_IQESIZE)
5372 #define G_FW_IQ_CMD_IQESIZE(x)		\
5373     (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
5374 
5375 #define S_FW_IQ_CMD_IQNS		31
5376 #define M_FW_IQ_CMD_IQNS		0x1
5377 #define V_FW_IQ_CMD_IQNS(x)		((x) << S_FW_IQ_CMD_IQNS)
5378 #define G_FW_IQ_CMD_IQNS(x)		\
5379     (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
5380 #define F_FW_IQ_CMD_IQNS		V_FW_IQ_CMD_IQNS(1U)
5381 
5382 #define S_FW_IQ_CMD_IQRO		30
5383 #define M_FW_IQ_CMD_IQRO		0x1
5384 #define V_FW_IQ_CMD_IQRO(x)		((x) << S_FW_IQ_CMD_IQRO)
5385 #define G_FW_IQ_CMD_IQRO(x)		\
5386     (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
5387 #define F_FW_IQ_CMD_IQRO		V_FW_IQ_CMD_IQRO(1U)
5388 
5389 #define S_FW_IQ_CMD_IQFLINTIQHSEN	28
5390 #define M_FW_IQ_CMD_IQFLINTIQHSEN	0x3
5391 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x)	((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
5392 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x)	\
5393     (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
5394 
5395 #define S_FW_IQ_CMD_IQFLINTCONGEN	27
5396 #define M_FW_IQ_CMD_IQFLINTCONGEN	0x1
5397 #define V_FW_IQ_CMD_IQFLINTCONGEN(x)	((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
5398 #define G_FW_IQ_CMD_IQFLINTCONGEN(x)	\
5399     (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
5400 #define F_FW_IQ_CMD_IQFLINTCONGEN	V_FW_IQ_CMD_IQFLINTCONGEN(1U)
5401 
5402 #define S_FW_IQ_CMD_IQFLINTISCSIC	26
5403 #define M_FW_IQ_CMD_IQFLINTISCSIC	0x1
5404 #define V_FW_IQ_CMD_IQFLINTISCSIC(x)	((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
5405 #define G_FW_IQ_CMD_IQFLINTISCSIC(x)	\
5406     (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
5407 #define F_FW_IQ_CMD_IQFLINTISCSIC	V_FW_IQ_CMD_IQFLINTISCSIC(1U)
5408 
5409 #define S_FW_IQ_CMD_IQTYPE	24
5410 #define M_FW_IQ_CMD_IQTYPE	0x3
5411 #define V_FW_IQ_CMD_IQTYPE(x)	((x) << S_FW_IQ_CMD_IQTYPE)
5412 #define G_FW_IQ_CMD_IQTYPE(x)	\
5413     (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)
5414 
5415 #define S_FW_IQ_CMD_FL0CNGCHMAP		20
5416 #define M_FW_IQ_CMD_FL0CNGCHMAP		0xf
5417 #define V_FW_IQ_CMD_FL0CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
5418 #define G_FW_IQ_CMD_FL0CNGCHMAP(x)	\
5419     (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
5420 
5421 #define S_FW_IQ_CMD_FL0CONGDROP		16
5422 #define M_FW_IQ_CMD_FL0CONGDROP		0x1
5423 #define V_FW_IQ_CMD_FL0CONGDROP(x)	((x) << S_FW_IQ_CMD_FL0CONGDROP)
5424 #define G_FW_IQ_CMD_FL0CONGDROP(x)	\
5425     (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
5426 #define F_FW_IQ_CMD_FL0CONGDROP		V_FW_IQ_CMD_FL0CONGDROP(1U)
5427 
5428 #define S_FW_IQ_CMD_FL0CACHELOCK	15
5429 #define M_FW_IQ_CMD_FL0CACHELOCK	0x1
5430 #define V_FW_IQ_CMD_FL0CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL0CACHELOCK)
5431 #define G_FW_IQ_CMD_FL0CACHELOCK(x)	\
5432     (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
5433 #define F_FW_IQ_CMD_FL0CACHELOCK	V_FW_IQ_CMD_FL0CACHELOCK(1U)
5434 
5435 #define S_FW_IQ_CMD_FL0DBP		14
5436 #define M_FW_IQ_CMD_FL0DBP		0x1
5437 #define V_FW_IQ_CMD_FL0DBP(x)		((x) << S_FW_IQ_CMD_FL0DBP)
5438 #define G_FW_IQ_CMD_FL0DBP(x)		\
5439     (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
5440 #define F_FW_IQ_CMD_FL0DBP		V_FW_IQ_CMD_FL0DBP(1U)
5441 
5442 #define S_FW_IQ_CMD_FL0DATANS		13
5443 #define M_FW_IQ_CMD_FL0DATANS		0x1
5444 #define V_FW_IQ_CMD_FL0DATANS(x)	((x) << S_FW_IQ_CMD_FL0DATANS)
5445 #define G_FW_IQ_CMD_FL0DATANS(x)	\
5446     (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
5447 #define F_FW_IQ_CMD_FL0DATANS		V_FW_IQ_CMD_FL0DATANS(1U)
5448 
5449 #define S_FW_IQ_CMD_FL0DATARO		12
5450 #define M_FW_IQ_CMD_FL0DATARO		0x1
5451 #define V_FW_IQ_CMD_FL0DATARO(x)	((x) << S_FW_IQ_CMD_FL0DATARO)
5452 #define G_FW_IQ_CMD_FL0DATARO(x)	\
5453     (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
5454 #define F_FW_IQ_CMD_FL0DATARO		V_FW_IQ_CMD_FL0DATARO(1U)
5455 
5456 #define S_FW_IQ_CMD_FL0CONGCIF		11
5457 #define M_FW_IQ_CMD_FL0CONGCIF		0x1
5458 #define V_FW_IQ_CMD_FL0CONGCIF(x)	((x) << S_FW_IQ_CMD_FL0CONGCIF)
5459 #define G_FW_IQ_CMD_FL0CONGCIF(x)	\
5460     (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
5461 #define F_FW_IQ_CMD_FL0CONGCIF		V_FW_IQ_CMD_FL0CONGCIF(1U)
5462 
5463 #define S_FW_IQ_CMD_FL0ONCHIP		10
5464 #define M_FW_IQ_CMD_FL0ONCHIP		0x1
5465 #define V_FW_IQ_CMD_FL0ONCHIP(x)	((x) << S_FW_IQ_CMD_FL0ONCHIP)
5466 #define G_FW_IQ_CMD_FL0ONCHIP(x)	\
5467     (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
5468 #define F_FW_IQ_CMD_FL0ONCHIP		V_FW_IQ_CMD_FL0ONCHIP(1U)
5469 
5470 #define S_FW_IQ_CMD_FL0STATUSPGNS	9
5471 #define M_FW_IQ_CMD_FL0STATUSPGNS	0x1
5472 #define V_FW_IQ_CMD_FL0STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
5473 #define G_FW_IQ_CMD_FL0STATUSPGNS(x)	\
5474     (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
5475 #define F_FW_IQ_CMD_FL0STATUSPGNS	V_FW_IQ_CMD_FL0STATUSPGNS(1U)
5476 
5477 #define S_FW_IQ_CMD_FL0STATUSPGRO	8
5478 #define M_FW_IQ_CMD_FL0STATUSPGRO	0x1
5479 #define V_FW_IQ_CMD_FL0STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
5480 #define G_FW_IQ_CMD_FL0STATUSPGRO(x)	\
5481     (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
5482 #define F_FW_IQ_CMD_FL0STATUSPGRO	V_FW_IQ_CMD_FL0STATUSPGRO(1U)
5483 
5484 #define S_FW_IQ_CMD_FL0FETCHNS		7
5485 #define M_FW_IQ_CMD_FL0FETCHNS		0x1
5486 #define V_FW_IQ_CMD_FL0FETCHNS(x)	((x) << S_FW_IQ_CMD_FL0FETCHNS)
5487 #define G_FW_IQ_CMD_FL0FETCHNS(x)	\
5488     (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
5489 #define F_FW_IQ_CMD_FL0FETCHNS		V_FW_IQ_CMD_FL0FETCHNS(1U)
5490 
5491 #define S_FW_IQ_CMD_FL0FETCHRO		6
5492 #define M_FW_IQ_CMD_FL0FETCHRO		0x1
5493 #define V_FW_IQ_CMD_FL0FETCHRO(x)	((x) << S_FW_IQ_CMD_FL0FETCHRO)
5494 #define G_FW_IQ_CMD_FL0FETCHRO(x)	\
5495     (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
5496 #define F_FW_IQ_CMD_FL0FETCHRO		V_FW_IQ_CMD_FL0FETCHRO(1U)
5497 
5498 #define S_FW_IQ_CMD_FL0HOSTFCMODE	4
5499 #define M_FW_IQ_CMD_FL0HOSTFCMODE	0x3
5500 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
5501 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x)	\
5502     (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
5503 
5504 #define S_FW_IQ_CMD_FL0CPRIO		3
5505 #define M_FW_IQ_CMD_FL0CPRIO		0x1
5506 #define V_FW_IQ_CMD_FL0CPRIO(x)		((x) << S_FW_IQ_CMD_FL0CPRIO)
5507 #define G_FW_IQ_CMD_FL0CPRIO(x)		\
5508     (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
5509 #define F_FW_IQ_CMD_FL0CPRIO		V_FW_IQ_CMD_FL0CPRIO(1U)
5510 
5511 #define S_FW_IQ_CMD_FL0PADEN		2
5512 #define M_FW_IQ_CMD_FL0PADEN		0x1
5513 #define V_FW_IQ_CMD_FL0PADEN(x)		((x) << S_FW_IQ_CMD_FL0PADEN)
5514 #define G_FW_IQ_CMD_FL0PADEN(x)		\
5515     (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
5516 #define F_FW_IQ_CMD_FL0PADEN		V_FW_IQ_CMD_FL0PADEN(1U)
5517 
5518 #define S_FW_IQ_CMD_FL0PACKEN		1
5519 #define M_FW_IQ_CMD_FL0PACKEN		0x1
5520 #define V_FW_IQ_CMD_FL0PACKEN(x)	((x) << S_FW_IQ_CMD_FL0PACKEN)
5521 #define G_FW_IQ_CMD_FL0PACKEN(x)	\
5522     (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
5523 #define F_FW_IQ_CMD_FL0PACKEN		V_FW_IQ_CMD_FL0PACKEN(1U)
5524 
5525 #define S_FW_IQ_CMD_FL0CONGEN		0
5526 #define M_FW_IQ_CMD_FL0CONGEN		0x1
5527 #define V_FW_IQ_CMD_FL0CONGEN(x)	((x) << S_FW_IQ_CMD_FL0CONGEN)
5528 #define G_FW_IQ_CMD_FL0CONGEN(x)	\
5529     (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
5530 #define F_FW_IQ_CMD_FL0CONGEN		V_FW_IQ_CMD_FL0CONGEN(1U)
5531 
5532 #define S_FW_IQ_CMD_FL0DCAEN		15
5533 #define M_FW_IQ_CMD_FL0DCAEN		0x1
5534 #define V_FW_IQ_CMD_FL0DCAEN(x)		((x) << S_FW_IQ_CMD_FL0DCAEN)
5535 #define G_FW_IQ_CMD_FL0DCAEN(x)		\
5536     (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
5537 #define F_FW_IQ_CMD_FL0DCAEN		V_FW_IQ_CMD_FL0DCAEN(1U)
5538 
5539 #define S_FW_IQ_CMD_FL0DCACPU		10
5540 #define M_FW_IQ_CMD_FL0DCACPU		0x1f
5541 #define V_FW_IQ_CMD_FL0DCACPU(x)	((x) << S_FW_IQ_CMD_FL0DCACPU)
5542 #define G_FW_IQ_CMD_FL0DCACPU(x)	\
5543     (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
5544 
5545 #define S_FW_IQ_CMD_FL0FBMIN		7
5546 #define M_FW_IQ_CMD_FL0FBMIN		0x7
5547 #define V_FW_IQ_CMD_FL0FBMIN(x)		((x) << S_FW_IQ_CMD_FL0FBMIN)
5548 #define G_FW_IQ_CMD_FL0FBMIN(x)		\
5549     (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
5550 
5551 #define S_FW_IQ_CMD_FL0FBMAX		4
5552 #define M_FW_IQ_CMD_FL0FBMAX		0x7
5553 #define V_FW_IQ_CMD_FL0FBMAX(x)		((x) << S_FW_IQ_CMD_FL0FBMAX)
5554 #define G_FW_IQ_CMD_FL0FBMAX(x)		\
5555     (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
5556 
5557 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO	3
5558 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO	0x1
5559 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
5560 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	\
5561     (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
5562 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO	V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
5563 
5564 #define S_FW_IQ_CMD_FL0CIDXFTHRESH	0
5565 #define M_FW_IQ_CMD_FL0CIDXFTHRESH	0x7
5566 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
5567 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x)	\
5568     (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
5569 
5570 #define S_FW_IQ_CMD_FL1CNGCHMAP		20
5571 #define M_FW_IQ_CMD_FL1CNGCHMAP		0xf
5572 #define V_FW_IQ_CMD_FL1CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
5573 #define G_FW_IQ_CMD_FL1CNGCHMAP(x)	\
5574     (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
5575 
5576 #define S_FW_IQ_CMD_FL1CONGDROP		16
5577 #define M_FW_IQ_CMD_FL1CONGDROP		0x1
5578 #define V_FW_IQ_CMD_FL1CONGDROP(x)	((x) << S_FW_IQ_CMD_FL1CONGDROP)
5579 #define G_FW_IQ_CMD_FL1CONGDROP(x)	\
5580     (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
5581 #define F_FW_IQ_CMD_FL1CONGDROP		V_FW_IQ_CMD_FL1CONGDROP(1U)
5582 
5583 #define S_FW_IQ_CMD_FL1CACHELOCK	15
5584 #define M_FW_IQ_CMD_FL1CACHELOCK	0x1
5585 #define V_FW_IQ_CMD_FL1CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL1CACHELOCK)
5586 #define G_FW_IQ_CMD_FL1CACHELOCK(x)	\
5587     (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
5588 #define F_FW_IQ_CMD_FL1CACHELOCK	V_FW_IQ_CMD_FL1CACHELOCK(1U)
5589 
5590 #define S_FW_IQ_CMD_FL1DBP		14
5591 #define M_FW_IQ_CMD_FL1DBP		0x1
5592 #define V_FW_IQ_CMD_FL1DBP(x)		((x) << S_FW_IQ_CMD_FL1DBP)
5593 #define G_FW_IQ_CMD_FL1DBP(x)		\
5594     (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
5595 #define F_FW_IQ_CMD_FL1DBP		V_FW_IQ_CMD_FL1DBP(1U)
5596 
5597 #define S_FW_IQ_CMD_FL1DATANS		13
5598 #define M_FW_IQ_CMD_FL1DATANS		0x1
5599 #define V_FW_IQ_CMD_FL1DATANS(x)	((x) << S_FW_IQ_CMD_FL1DATANS)
5600 #define G_FW_IQ_CMD_FL1DATANS(x)	\
5601     (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
5602 #define F_FW_IQ_CMD_FL1DATANS		V_FW_IQ_CMD_FL1DATANS(1U)
5603 
5604 #define S_FW_IQ_CMD_FL1DATARO		12
5605 #define M_FW_IQ_CMD_FL1DATARO		0x1
5606 #define V_FW_IQ_CMD_FL1DATARO(x)	((x) << S_FW_IQ_CMD_FL1DATARO)
5607 #define G_FW_IQ_CMD_FL1DATARO(x)	\
5608     (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
5609 #define F_FW_IQ_CMD_FL1DATARO		V_FW_IQ_CMD_FL1DATARO(1U)
5610 
5611 #define S_FW_IQ_CMD_FL1CONGCIF		11
5612 #define M_FW_IQ_CMD_FL1CONGCIF		0x1
5613 #define V_FW_IQ_CMD_FL1CONGCIF(x)	((x) << S_FW_IQ_CMD_FL1CONGCIF)
5614 #define G_FW_IQ_CMD_FL1CONGCIF(x)	\
5615     (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
5616 #define F_FW_IQ_CMD_FL1CONGCIF		V_FW_IQ_CMD_FL1CONGCIF(1U)
5617 
5618 #define S_FW_IQ_CMD_FL1ONCHIP		10
5619 #define M_FW_IQ_CMD_FL1ONCHIP		0x1
5620 #define V_FW_IQ_CMD_FL1ONCHIP(x)	((x) << S_FW_IQ_CMD_FL1ONCHIP)
5621 #define G_FW_IQ_CMD_FL1ONCHIP(x)	\
5622     (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
5623 #define F_FW_IQ_CMD_FL1ONCHIP		V_FW_IQ_CMD_FL1ONCHIP(1U)
5624 
5625 #define S_FW_IQ_CMD_FL1STATUSPGNS	9
5626 #define M_FW_IQ_CMD_FL1STATUSPGNS	0x1
5627 #define V_FW_IQ_CMD_FL1STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
5628 #define G_FW_IQ_CMD_FL1STATUSPGNS(x)	\
5629     (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
5630 #define F_FW_IQ_CMD_FL1STATUSPGNS	V_FW_IQ_CMD_FL1STATUSPGNS(1U)
5631 
5632 #define S_FW_IQ_CMD_FL1STATUSPGRO	8
5633 #define M_FW_IQ_CMD_FL1STATUSPGRO	0x1
5634 #define V_FW_IQ_CMD_FL1STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
5635 #define G_FW_IQ_CMD_FL1STATUSPGRO(x)	\
5636     (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
5637 #define F_FW_IQ_CMD_FL1STATUSPGRO	V_FW_IQ_CMD_FL1STATUSPGRO(1U)
5638 
5639 #define S_FW_IQ_CMD_FL1FETCHNS		7
5640 #define M_FW_IQ_CMD_FL1FETCHNS		0x1
5641 #define V_FW_IQ_CMD_FL1FETCHNS(x)	((x) << S_FW_IQ_CMD_FL1FETCHNS)
5642 #define G_FW_IQ_CMD_FL1FETCHNS(x)	\
5643     (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
5644 #define F_FW_IQ_CMD_FL1FETCHNS		V_FW_IQ_CMD_FL1FETCHNS(1U)
5645 
5646 #define S_FW_IQ_CMD_FL1FETCHRO		6
5647 #define M_FW_IQ_CMD_FL1FETCHRO		0x1
5648 #define V_FW_IQ_CMD_FL1FETCHRO(x)	((x) << S_FW_IQ_CMD_FL1FETCHRO)
5649 #define G_FW_IQ_CMD_FL1FETCHRO(x)	\
5650     (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
5651 #define F_FW_IQ_CMD_FL1FETCHRO		V_FW_IQ_CMD_FL1FETCHRO(1U)
5652 
5653 #define S_FW_IQ_CMD_FL1HOSTFCMODE	4
5654 #define M_FW_IQ_CMD_FL1HOSTFCMODE	0x3
5655 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
5656 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x)	\
5657     (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
5658 
5659 #define S_FW_IQ_CMD_FL1CPRIO		3
5660 #define M_FW_IQ_CMD_FL1CPRIO		0x1
5661 #define V_FW_IQ_CMD_FL1CPRIO(x)		((x) << S_FW_IQ_CMD_FL1CPRIO)
5662 #define G_FW_IQ_CMD_FL1CPRIO(x)		\
5663     (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
5664 #define F_FW_IQ_CMD_FL1CPRIO		V_FW_IQ_CMD_FL1CPRIO(1U)
5665 
5666 #define S_FW_IQ_CMD_FL1PADEN		2
5667 #define M_FW_IQ_CMD_FL1PADEN		0x1
5668 #define V_FW_IQ_CMD_FL1PADEN(x)		((x) << S_FW_IQ_CMD_FL1PADEN)
5669 #define G_FW_IQ_CMD_FL1PADEN(x)		\
5670     (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
5671 #define F_FW_IQ_CMD_FL1PADEN		V_FW_IQ_CMD_FL1PADEN(1U)
5672 
5673 #define S_FW_IQ_CMD_FL1PACKEN		1
5674 #define M_FW_IQ_CMD_FL1PACKEN		0x1
5675 #define V_FW_IQ_CMD_FL1PACKEN(x)	((x) << S_FW_IQ_CMD_FL1PACKEN)
5676 #define G_FW_IQ_CMD_FL1PACKEN(x)	\
5677     (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
5678 #define F_FW_IQ_CMD_FL1PACKEN		V_FW_IQ_CMD_FL1PACKEN(1U)
5679 
5680 #define S_FW_IQ_CMD_FL1CONGEN		0
5681 #define M_FW_IQ_CMD_FL1CONGEN		0x1
5682 #define V_FW_IQ_CMD_FL1CONGEN(x)	((x) << S_FW_IQ_CMD_FL1CONGEN)
5683 #define G_FW_IQ_CMD_FL1CONGEN(x)	\
5684     (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
5685 #define F_FW_IQ_CMD_FL1CONGEN		V_FW_IQ_CMD_FL1CONGEN(1U)
5686 
5687 #define S_FW_IQ_CMD_FL1DCAEN		15
5688 #define M_FW_IQ_CMD_FL1DCAEN		0x1
5689 #define V_FW_IQ_CMD_FL1DCAEN(x)		((x) << S_FW_IQ_CMD_FL1DCAEN)
5690 #define G_FW_IQ_CMD_FL1DCAEN(x)		\
5691     (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
5692 #define F_FW_IQ_CMD_FL1DCAEN		V_FW_IQ_CMD_FL1DCAEN(1U)
5693 
5694 #define S_FW_IQ_CMD_FL1DCACPU		10
5695 #define M_FW_IQ_CMD_FL1DCACPU		0x1f
5696 #define V_FW_IQ_CMD_FL1DCACPU(x)	((x) << S_FW_IQ_CMD_FL1DCACPU)
5697 #define G_FW_IQ_CMD_FL1DCACPU(x)	\
5698     (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
5699 
5700 #define S_FW_IQ_CMD_FL1FBMIN		7
5701 #define M_FW_IQ_CMD_FL1FBMIN		0x7
5702 #define V_FW_IQ_CMD_FL1FBMIN(x)		((x) << S_FW_IQ_CMD_FL1FBMIN)
5703 #define G_FW_IQ_CMD_FL1FBMIN(x)		\
5704     (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
5705 
5706 #define S_FW_IQ_CMD_FL1FBMAX		4
5707 #define M_FW_IQ_CMD_FL1FBMAX		0x7
5708 #define V_FW_IQ_CMD_FL1FBMAX(x)		((x) << S_FW_IQ_CMD_FL1FBMAX)
5709 #define G_FW_IQ_CMD_FL1FBMAX(x)		\
5710     (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
5711 
5712 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO	3
5713 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO	0x1
5714 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
5715 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	\
5716     (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
5717 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO	V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
5718 
5719 #define S_FW_IQ_CMD_FL1CIDXFTHRESH	0
5720 #define M_FW_IQ_CMD_FL1CIDXFTHRESH	0x7
5721 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
5722 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x)	\
5723     (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
5724 
5725 struct fw_eq_mngt_cmd {
5726 	__be32 op_to_vfn;
5727 	__be32 alloc_to_len16;
5728 	__be32 cmpliqid_eqid;
5729 	__be32 physeqid_pkd;
5730 	__be32 fetchszm_to_iqid;
5731 	__be32 dcaen_to_eqsize;
5732 	__be64 eqaddr;
5733 };
5734 
5735 #define S_FW_EQ_MNGT_CMD_PFN		8
5736 #define M_FW_EQ_MNGT_CMD_PFN		0x7
5737 #define V_FW_EQ_MNGT_CMD_PFN(x)		((x) << S_FW_EQ_MNGT_CMD_PFN)
5738 #define G_FW_EQ_MNGT_CMD_PFN(x)		\
5739     (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
5740 
5741 #define S_FW_EQ_MNGT_CMD_VFN		0
5742 #define M_FW_EQ_MNGT_CMD_VFN		0xff
5743 #define V_FW_EQ_MNGT_CMD_VFN(x)		((x) << S_FW_EQ_MNGT_CMD_VFN)
5744 #define G_FW_EQ_MNGT_CMD_VFN(x)		\
5745     (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
5746 
5747 #define S_FW_EQ_MNGT_CMD_ALLOC		31
5748 #define M_FW_EQ_MNGT_CMD_ALLOC		0x1
5749 #define V_FW_EQ_MNGT_CMD_ALLOC(x)	((x) << S_FW_EQ_MNGT_CMD_ALLOC)
5750 #define G_FW_EQ_MNGT_CMD_ALLOC(x)	\
5751     (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
5752 #define F_FW_EQ_MNGT_CMD_ALLOC		V_FW_EQ_MNGT_CMD_ALLOC(1U)
5753 
5754 #define S_FW_EQ_MNGT_CMD_FREE		30
5755 #define M_FW_EQ_MNGT_CMD_FREE		0x1
5756 #define V_FW_EQ_MNGT_CMD_FREE(x)	((x) << S_FW_EQ_MNGT_CMD_FREE)
5757 #define G_FW_EQ_MNGT_CMD_FREE(x)	\
5758     (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
5759 #define F_FW_EQ_MNGT_CMD_FREE		V_FW_EQ_MNGT_CMD_FREE(1U)
5760 
5761 #define S_FW_EQ_MNGT_CMD_MODIFY		29
5762 #define M_FW_EQ_MNGT_CMD_MODIFY		0x1
5763 #define V_FW_EQ_MNGT_CMD_MODIFY(x)	((x) << S_FW_EQ_MNGT_CMD_MODIFY)
5764 #define G_FW_EQ_MNGT_CMD_MODIFY(x)	\
5765     (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
5766 #define F_FW_EQ_MNGT_CMD_MODIFY		V_FW_EQ_MNGT_CMD_MODIFY(1U)
5767 
5768 #define S_FW_EQ_MNGT_CMD_EQSTART	28
5769 #define M_FW_EQ_MNGT_CMD_EQSTART	0x1
5770 #define V_FW_EQ_MNGT_CMD_EQSTART(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTART)
5771 #define G_FW_EQ_MNGT_CMD_EQSTART(x)	\
5772     (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
5773 #define F_FW_EQ_MNGT_CMD_EQSTART	V_FW_EQ_MNGT_CMD_EQSTART(1U)
5774 
5775 #define S_FW_EQ_MNGT_CMD_EQSTOP		27
5776 #define M_FW_EQ_MNGT_CMD_EQSTOP		0x1
5777 #define V_FW_EQ_MNGT_CMD_EQSTOP(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
5778 #define G_FW_EQ_MNGT_CMD_EQSTOP(x)	\
5779     (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
5780 #define F_FW_EQ_MNGT_CMD_EQSTOP		V_FW_EQ_MNGT_CMD_EQSTOP(1U)
5781 
5782 #define S_FW_EQ_MNGT_CMD_CMPLIQID	20
5783 #define M_FW_EQ_MNGT_CMD_CMPLIQID	0xfff
5784 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x)	((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
5785 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x)	\
5786     (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
5787 
5788 #define S_FW_EQ_MNGT_CMD_EQID		0
5789 #define M_FW_EQ_MNGT_CMD_EQID		0xfffff
5790 #define V_FW_EQ_MNGT_CMD_EQID(x)	((x) << S_FW_EQ_MNGT_CMD_EQID)
5791 #define G_FW_EQ_MNGT_CMD_EQID(x)	\
5792     (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
5793 
5794 #define S_FW_EQ_MNGT_CMD_PHYSEQID	0
5795 #define M_FW_EQ_MNGT_CMD_PHYSEQID	0xfffff
5796 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x)	((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
5797 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x)	\
5798     (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
5799 
5800 #define S_FW_EQ_MNGT_CMD_FETCHSZM	26
5801 #define M_FW_EQ_MNGT_CMD_FETCHSZM	0x1
5802 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
5803 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x)	\
5804     (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
5805 #define F_FW_EQ_MNGT_CMD_FETCHSZM	V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
5806 
5807 #define S_FW_EQ_MNGT_CMD_STATUSPGNS	25
5808 #define M_FW_EQ_MNGT_CMD_STATUSPGNS	0x1
5809 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
5810 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x)	\
5811     (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
5812 #define F_FW_EQ_MNGT_CMD_STATUSPGNS	V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
5813 
5814 #define S_FW_EQ_MNGT_CMD_STATUSPGRO	24
5815 #define M_FW_EQ_MNGT_CMD_STATUSPGRO	0x1
5816 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
5817 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x)	\
5818     (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
5819 #define F_FW_EQ_MNGT_CMD_STATUSPGRO	V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
5820 
5821 #define S_FW_EQ_MNGT_CMD_FETCHNS	23
5822 #define M_FW_EQ_MNGT_CMD_FETCHNS	0x1
5823 #define V_FW_EQ_MNGT_CMD_FETCHNS(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
5824 #define G_FW_EQ_MNGT_CMD_FETCHNS(x)	\
5825     (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
5826 #define F_FW_EQ_MNGT_CMD_FETCHNS	V_FW_EQ_MNGT_CMD_FETCHNS(1U)
5827 
5828 #define S_FW_EQ_MNGT_CMD_FETCHRO	22
5829 #define M_FW_EQ_MNGT_CMD_FETCHRO	0x1
5830 #define V_FW_EQ_MNGT_CMD_FETCHRO(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
5831 #define G_FW_EQ_MNGT_CMD_FETCHRO(x)	\
5832     (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
5833 #define F_FW_EQ_MNGT_CMD_FETCHRO	V_FW_EQ_MNGT_CMD_FETCHRO(1U)
5834 
5835 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE	20
5836 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE	0x3
5837 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
5838 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	\
5839     (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
5840 
5841 #define S_FW_EQ_MNGT_CMD_CPRIO		19
5842 #define M_FW_EQ_MNGT_CMD_CPRIO		0x1
5843 #define V_FW_EQ_MNGT_CMD_CPRIO(x)	((x) << S_FW_EQ_MNGT_CMD_CPRIO)
5844 #define G_FW_EQ_MNGT_CMD_CPRIO(x)	\
5845     (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
5846 #define F_FW_EQ_MNGT_CMD_CPRIO		V_FW_EQ_MNGT_CMD_CPRIO(1U)
5847 
5848 #define S_FW_EQ_MNGT_CMD_ONCHIP		18
5849 #define M_FW_EQ_MNGT_CMD_ONCHIP		0x1
5850 #define V_FW_EQ_MNGT_CMD_ONCHIP(x)	((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
5851 #define G_FW_EQ_MNGT_CMD_ONCHIP(x)	\
5852     (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
5853 #define F_FW_EQ_MNGT_CMD_ONCHIP		V_FW_EQ_MNGT_CMD_ONCHIP(1U)
5854 
5855 #define S_FW_EQ_MNGT_CMD_PCIECHN	16
5856 #define M_FW_EQ_MNGT_CMD_PCIECHN	0x3
5857 #define V_FW_EQ_MNGT_CMD_PCIECHN(x)	((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
5858 #define G_FW_EQ_MNGT_CMD_PCIECHN(x)	\
5859     (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
5860 
5861 #define S_FW_EQ_MNGT_CMD_IQID		0
5862 #define M_FW_EQ_MNGT_CMD_IQID		0xffff
5863 #define V_FW_EQ_MNGT_CMD_IQID(x)	((x) << S_FW_EQ_MNGT_CMD_IQID)
5864 #define G_FW_EQ_MNGT_CMD_IQID(x)	\
5865     (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
5866 
5867 #define S_FW_EQ_MNGT_CMD_DCAEN		31
5868 #define M_FW_EQ_MNGT_CMD_DCAEN		0x1
5869 #define V_FW_EQ_MNGT_CMD_DCAEN(x)	((x) << S_FW_EQ_MNGT_CMD_DCAEN)
5870 #define G_FW_EQ_MNGT_CMD_DCAEN(x)	\
5871     (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
5872 #define F_FW_EQ_MNGT_CMD_DCAEN		V_FW_EQ_MNGT_CMD_DCAEN(1U)
5873 
5874 #define S_FW_EQ_MNGT_CMD_DCACPU		26
5875 #define M_FW_EQ_MNGT_CMD_DCACPU		0x1f
5876 #define V_FW_EQ_MNGT_CMD_DCACPU(x)	((x) << S_FW_EQ_MNGT_CMD_DCACPU)
5877 #define G_FW_EQ_MNGT_CMD_DCACPU(x)	\
5878     (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
5879 
5880 #define S_FW_EQ_MNGT_CMD_FBMIN		23
5881 #define M_FW_EQ_MNGT_CMD_FBMIN		0x7
5882 #define V_FW_EQ_MNGT_CMD_FBMIN(x)	((x) << S_FW_EQ_MNGT_CMD_FBMIN)
5883 #define G_FW_EQ_MNGT_CMD_FBMIN(x)	\
5884     (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
5885 
5886 #define S_FW_EQ_MNGT_CMD_FBMAX		20
5887 #define M_FW_EQ_MNGT_CMD_FBMAX		0x7
5888 #define V_FW_EQ_MNGT_CMD_FBMAX(x)	((x) << S_FW_EQ_MNGT_CMD_FBMAX)
5889 #define G_FW_EQ_MNGT_CMD_FBMAX(x)	\
5890     (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
5891 
5892 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO	19
5893 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO	0x1
5894 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5895     ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5896 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5897     (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5898 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO	V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
5899 
5900 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH	16
5901 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH	0x7
5902 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5903 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	\
5904     (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5905 
5906 #define S_FW_EQ_MNGT_CMD_EQSIZE		0
5907 #define M_FW_EQ_MNGT_CMD_EQSIZE		0xffff
5908 #define V_FW_EQ_MNGT_CMD_EQSIZE(x)	((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
5909 #define G_FW_EQ_MNGT_CMD_EQSIZE(x)	\
5910     (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
5911 
5912 struct fw_eq_eth_cmd {
5913 	__be32 op_to_vfn;
5914 	__be32 alloc_to_len16;
5915 	__be32 eqid_pkd;
5916 	__be32 physeqid_pkd;
5917 	__be32 fetchszm_to_iqid;
5918 	__be32 dcaen_to_eqsize;
5919 	__be64 eqaddr;
5920 	__be32 autoequiqe_to_viid;
5921 	__be32 timeren_timerix;
5922 	__be64 r9;
5923 };
5924 
5925 #define S_FW_EQ_ETH_CMD_PFN		8
5926 #define M_FW_EQ_ETH_CMD_PFN		0x7
5927 #define V_FW_EQ_ETH_CMD_PFN(x)		((x) << S_FW_EQ_ETH_CMD_PFN)
5928 #define G_FW_EQ_ETH_CMD_PFN(x)		\
5929     (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
5930 
5931 #define S_FW_EQ_ETH_CMD_VFN		0
5932 #define M_FW_EQ_ETH_CMD_VFN		0xff
5933 #define V_FW_EQ_ETH_CMD_VFN(x)		((x) << S_FW_EQ_ETH_CMD_VFN)
5934 #define G_FW_EQ_ETH_CMD_VFN(x)		\
5935     (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
5936 
5937 #define S_FW_EQ_ETH_CMD_ALLOC		31
5938 #define M_FW_EQ_ETH_CMD_ALLOC		0x1
5939 #define V_FW_EQ_ETH_CMD_ALLOC(x)	((x) << S_FW_EQ_ETH_CMD_ALLOC)
5940 #define G_FW_EQ_ETH_CMD_ALLOC(x)	\
5941     (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
5942 #define F_FW_EQ_ETH_CMD_ALLOC		V_FW_EQ_ETH_CMD_ALLOC(1U)
5943 
5944 #define S_FW_EQ_ETH_CMD_FREE		30
5945 #define M_FW_EQ_ETH_CMD_FREE		0x1
5946 #define V_FW_EQ_ETH_CMD_FREE(x)		((x) << S_FW_EQ_ETH_CMD_FREE)
5947 #define G_FW_EQ_ETH_CMD_FREE(x)		\
5948     (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
5949 #define F_FW_EQ_ETH_CMD_FREE		V_FW_EQ_ETH_CMD_FREE(1U)
5950 
5951 #define S_FW_EQ_ETH_CMD_MODIFY		29
5952 #define M_FW_EQ_ETH_CMD_MODIFY		0x1
5953 #define V_FW_EQ_ETH_CMD_MODIFY(x)	((x) << S_FW_EQ_ETH_CMD_MODIFY)
5954 #define G_FW_EQ_ETH_CMD_MODIFY(x)	\
5955     (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
5956 #define F_FW_EQ_ETH_CMD_MODIFY		V_FW_EQ_ETH_CMD_MODIFY(1U)
5957 
5958 #define S_FW_EQ_ETH_CMD_EQSTART		28
5959 #define M_FW_EQ_ETH_CMD_EQSTART		0x1
5960 #define V_FW_EQ_ETH_CMD_EQSTART(x)	((x) << S_FW_EQ_ETH_CMD_EQSTART)
5961 #define G_FW_EQ_ETH_CMD_EQSTART(x)	\
5962     (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
5963 #define F_FW_EQ_ETH_CMD_EQSTART		V_FW_EQ_ETH_CMD_EQSTART(1U)
5964 
5965 #define S_FW_EQ_ETH_CMD_EQSTOP		27
5966 #define M_FW_EQ_ETH_CMD_EQSTOP		0x1
5967 #define V_FW_EQ_ETH_CMD_EQSTOP(x)	((x) << S_FW_EQ_ETH_CMD_EQSTOP)
5968 #define G_FW_EQ_ETH_CMD_EQSTOP(x)	\
5969     (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
5970 #define F_FW_EQ_ETH_CMD_EQSTOP		V_FW_EQ_ETH_CMD_EQSTOP(1U)
5971 
5972 #define S_FW_EQ_ETH_CMD_EQID		0
5973 #define M_FW_EQ_ETH_CMD_EQID		0xfffff
5974 #define V_FW_EQ_ETH_CMD_EQID(x)		((x) << S_FW_EQ_ETH_CMD_EQID)
5975 #define G_FW_EQ_ETH_CMD_EQID(x)		\
5976     (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
5977 
5978 #define S_FW_EQ_ETH_CMD_PHYSEQID	0
5979 #define M_FW_EQ_ETH_CMD_PHYSEQID	0xfffff
5980 #define V_FW_EQ_ETH_CMD_PHYSEQID(x)	((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
5981 #define G_FW_EQ_ETH_CMD_PHYSEQID(x)	\
5982     (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
5983 
5984 #define S_FW_EQ_ETH_CMD_FETCHSZM	26
5985 #define M_FW_EQ_ETH_CMD_FETCHSZM	0x1
5986 #define V_FW_EQ_ETH_CMD_FETCHSZM(x)	((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
5987 #define G_FW_EQ_ETH_CMD_FETCHSZM(x)	\
5988     (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
5989 #define F_FW_EQ_ETH_CMD_FETCHSZM	V_FW_EQ_ETH_CMD_FETCHSZM(1U)
5990 
5991 #define S_FW_EQ_ETH_CMD_STATUSPGNS	25
5992 #define M_FW_EQ_ETH_CMD_STATUSPGNS	0x1
5993 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
5994 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x)	\
5995     (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
5996 #define F_FW_EQ_ETH_CMD_STATUSPGNS	V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
5997 
5998 #define S_FW_EQ_ETH_CMD_STATUSPGRO	24
5999 #define M_FW_EQ_ETH_CMD_STATUSPGRO	0x1
6000 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
6001 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x)	\
6002     (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
6003 #define F_FW_EQ_ETH_CMD_STATUSPGRO	V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
6004 
6005 #define S_FW_EQ_ETH_CMD_FETCHNS		23
6006 #define M_FW_EQ_ETH_CMD_FETCHNS		0x1
6007 #define V_FW_EQ_ETH_CMD_FETCHNS(x)	((x) << S_FW_EQ_ETH_CMD_FETCHNS)
6008 #define G_FW_EQ_ETH_CMD_FETCHNS(x)	\
6009     (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
6010 #define F_FW_EQ_ETH_CMD_FETCHNS		V_FW_EQ_ETH_CMD_FETCHNS(1U)
6011 
6012 #define S_FW_EQ_ETH_CMD_FETCHRO		22
6013 #define M_FW_EQ_ETH_CMD_FETCHRO		0x1
6014 #define V_FW_EQ_ETH_CMD_FETCHRO(x)	((x) << S_FW_EQ_ETH_CMD_FETCHRO)
6015 #define G_FW_EQ_ETH_CMD_FETCHRO(x)	\
6016     (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
6017 #define F_FW_EQ_ETH_CMD_FETCHRO		V_FW_EQ_ETH_CMD_FETCHRO(1U)
6018 
6019 #define S_FW_EQ_ETH_CMD_HOSTFCMODE	20
6020 #define M_FW_EQ_ETH_CMD_HOSTFCMODE	0x3
6021 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
6022 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x)	\
6023     (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
6024 
6025 #define S_FW_EQ_ETH_CMD_CPRIO		19
6026 #define M_FW_EQ_ETH_CMD_CPRIO		0x1
6027 #define V_FW_EQ_ETH_CMD_CPRIO(x)	((x) << S_FW_EQ_ETH_CMD_CPRIO)
6028 #define G_FW_EQ_ETH_CMD_CPRIO(x)	\
6029     (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
6030 #define F_FW_EQ_ETH_CMD_CPRIO		V_FW_EQ_ETH_CMD_CPRIO(1U)
6031 
6032 #define S_FW_EQ_ETH_CMD_ONCHIP		18
6033 #define M_FW_EQ_ETH_CMD_ONCHIP		0x1
6034 #define V_FW_EQ_ETH_CMD_ONCHIP(x)	((x) << S_FW_EQ_ETH_CMD_ONCHIP)
6035 #define G_FW_EQ_ETH_CMD_ONCHIP(x)	\
6036     (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
6037 #define F_FW_EQ_ETH_CMD_ONCHIP		V_FW_EQ_ETH_CMD_ONCHIP(1U)
6038 
6039 #define S_FW_EQ_ETH_CMD_PCIECHN		16
6040 #define M_FW_EQ_ETH_CMD_PCIECHN		0x3
6041 #define V_FW_EQ_ETH_CMD_PCIECHN(x)	((x) << S_FW_EQ_ETH_CMD_PCIECHN)
6042 #define G_FW_EQ_ETH_CMD_PCIECHN(x)	\
6043     (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
6044 
6045 #define S_FW_EQ_ETH_CMD_IQID		0
6046 #define M_FW_EQ_ETH_CMD_IQID		0xffff
6047 #define V_FW_EQ_ETH_CMD_IQID(x)		((x) << S_FW_EQ_ETH_CMD_IQID)
6048 #define G_FW_EQ_ETH_CMD_IQID(x)		\
6049     (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
6050 
6051 #define S_FW_EQ_ETH_CMD_DCAEN		31
6052 #define M_FW_EQ_ETH_CMD_DCAEN		0x1
6053 #define V_FW_EQ_ETH_CMD_DCAEN(x)	((x) << S_FW_EQ_ETH_CMD_DCAEN)
6054 #define G_FW_EQ_ETH_CMD_DCAEN(x)	\
6055     (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
6056 #define F_FW_EQ_ETH_CMD_DCAEN		V_FW_EQ_ETH_CMD_DCAEN(1U)
6057 
6058 #define S_FW_EQ_ETH_CMD_DCACPU		26
6059 #define M_FW_EQ_ETH_CMD_DCACPU		0x1f
6060 #define V_FW_EQ_ETH_CMD_DCACPU(x)	((x) << S_FW_EQ_ETH_CMD_DCACPU)
6061 #define G_FW_EQ_ETH_CMD_DCACPU(x)	\
6062     (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
6063 
6064 #define S_FW_EQ_ETH_CMD_FBMIN		23
6065 #define M_FW_EQ_ETH_CMD_FBMIN		0x7
6066 #define V_FW_EQ_ETH_CMD_FBMIN(x)	((x) << S_FW_EQ_ETH_CMD_FBMIN)
6067 #define G_FW_EQ_ETH_CMD_FBMIN(x)	\
6068     (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
6069 
6070 #define S_FW_EQ_ETH_CMD_FBMAX		20
6071 #define M_FW_EQ_ETH_CMD_FBMAX		0x7
6072 #define V_FW_EQ_ETH_CMD_FBMAX(x)	((x) << S_FW_EQ_ETH_CMD_FBMAX)
6073 #define G_FW_EQ_ETH_CMD_FBMAX(x)	\
6074     (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
6075 
6076 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO	19
6077 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO	0x1
6078 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
6079 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	\
6080     (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
6081 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO	V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
6082 
6083 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH	16
6084 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH	0x7
6085 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
6086 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	\
6087     (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
6088 
6089 #define S_FW_EQ_ETH_CMD_EQSIZE		0
6090 #define M_FW_EQ_ETH_CMD_EQSIZE		0xffff
6091 #define V_FW_EQ_ETH_CMD_EQSIZE(x)	((x) << S_FW_EQ_ETH_CMD_EQSIZE)
6092 #define G_FW_EQ_ETH_CMD_EQSIZE(x)	\
6093     (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
6094 
6095 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE	31
6096 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE	0x1
6097 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x)	((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
6098 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x)	\
6099     (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
6100 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE	V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
6101 
6102 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE	30
6103 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE	0x1
6104 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x)	((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
6105 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x)	\
6106     (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
6107 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE	V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
6108 
6109 #define S_FW_EQ_ETH_CMD_VIID		16
6110 #define M_FW_EQ_ETH_CMD_VIID		0xfff
6111 #define V_FW_EQ_ETH_CMD_VIID(x)		((x) << S_FW_EQ_ETH_CMD_VIID)
6112 #define G_FW_EQ_ETH_CMD_VIID(x)		\
6113     (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
6114 
6115 #define S_FW_EQ_ETH_CMD_TIMEREN		3
6116 #define M_FW_EQ_ETH_CMD_TIMEREN		0x1
6117 #define V_FW_EQ_ETH_CMD_TIMEREN(x)	((x) << S_FW_EQ_ETH_CMD_TIMEREN)
6118 #define G_FW_EQ_ETH_CMD_TIMEREN(x)	\
6119     (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)
6120 #define F_FW_EQ_ETH_CMD_TIMEREN	V_FW_EQ_ETH_CMD_TIMEREN(1U)
6121 
6122 #define S_FW_EQ_ETH_CMD_TIMERIX		0
6123 #define M_FW_EQ_ETH_CMD_TIMERIX		0x7
6124 #define V_FW_EQ_ETH_CMD_TIMERIX(x)	((x) << S_FW_EQ_ETH_CMD_TIMERIX)
6125 #define G_FW_EQ_ETH_CMD_TIMERIX(x)	\
6126     (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)
6127 
6128 struct fw_eq_ctrl_cmd {
6129 	__be32 op_to_vfn;
6130 	__be32 alloc_to_len16;
6131 	__be32 cmpliqid_eqid;
6132 	__be32 physeqid_pkd;
6133 	__be32 fetchszm_to_iqid;
6134 	__be32 dcaen_to_eqsize;
6135 	__be64 eqaddr;
6136 };
6137 
6138 #define S_FW_EQ_CTRL_CMD_PFN		8
6139 #define M_FW_EQ_CTRL_CMD_PFN		0x7
6140 #define V_FW_EQ_CTRL_CMD_PFN(x)		((x) << S_FW_EQ_CTRL_CMD_PFN)
6141 #define G_FW_EQ_CTRL_CMD_PFN(x)		\
6142     (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
6143 
6144 #define S_FW_EQ_CTRL_CMD_VFN		0
6145 #define M_FW_EQ_CTRL_CMD_VFN		0xff
6146 #define V_FW_EQ_CTRL_CMD_VFN(x)		((x) << S_FW_EQ_CTRL_CMD_VFN)
6147 #define G_FW_EQ_CTRL_CMD_VFN(x)		\
6148     (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
6149 
6150 #define S_FW_EQ_CTRL_CMD_ALLOC		31
6151 #define M_FW_EQ_CTRL_CMD_ALLOC		0x1
6152 #define V_FW_EQ_CTRL_CMD_ALLOC(x)	((x) << S_FW_EQ_CTRL_CMD_ALLOC)
6153 #define G_FW_EQ_CTRL_CMD_ALLOC(x)	\
6154     (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
6155 #define F_FW_EQ_CTRL_CMD_ALLOC		V_FW_EQ_CTRL_CMD_ALLOC(1U)
6156 
6157 #define S_FW_EQ_CTRL_CMD_FREE		30
6158 #define M_FW_EQ_CTRL_CMD_FREE		0x1
6159 #define V_FW_EQ_CTRL_CMD_FREE(x)	((x) << S_FW_EQ_CTRL_CMD_FREE)
6160 #define G_FW_EQ_CTRL_CMD_FREE(x)	\
6161     (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
6162 #define F_FW_EQ_CTRL_CMD_FREE		V_FW_EQ_CTRL_CMD_FREE(1U)
6163 
6164 #define S_FW_EQ_CTRL_CMD_MODIFY		29
6165 #define M_FW_EQ_CTRL_CMD_MODIFY		0x1
6166 #define V_FW_EQ_CTRL_CMD_MODIFY(x)	((x) << S_FW_EQ_CTRL_CMD_MODIFY)
6167 #define G_FW_EQ_CTRL_CMD_MODIFY(x)	\
6168     (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
6169 #define F_FW_EQ_CTRL_CMD_MODIFY		V_FW_EQ_CTRL_CMD_MODIFY(1U)
6170 
6171 #define S_FW_EQ_CTRL_CMD_EQSTART	28
6172 #define M_FW_EQ_CTRL_CMD_EQSTART	0x1
6173 #define V_FW_EQ_CTRL_CMD_EQSTART(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTART)
6174 #define G_FW_EQ_CTRL_CMD_EQSTART(x)	\
6175     (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
6176 #define F_FW_EQ_CTRL_CMD_EQSTART	V_FW_EQ_CTRL_CMD_EQSTART(1U)
6177 
6178 #define S_FW_EQ_CTRL_CMD_EQSTOP		27
6179 #define M_FW_EQ_CTRL_CMD_EQSTOP		0x1
6180 #define V_FW_EQ_CTRL_CMD_EQSTOP(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
6181 #define G_FW_EQ_CTRL_CMD_EQSTOP(x)	\
6182     (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
6183 #define F_FW_EQ_CTRL_CMD_EQSTOP		V_FW_EQ_CTRL_CMD_EQSTOP(1U)
6184 
6185 #define S_FW_EQ_CTRL_CMD_CMPLIQID	20
6186 #define M_FW_EQ_CTRL_CMD_CMPLIQID	0xfff
6187 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x)	((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
6188 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x)	\
6189     (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
6190 
6191 #define S_FW_EQ_CTRL_CMD_EQID		0
6192 #define M_FW_EQ_CTRL_CMD_EQID		0xfffff
6193 #define V_FW_EQ_CTRL_CMD_EQID(x)	((x) << S_FW_EQ_CTRL_CMD_EQID)
6194 #define G_FW_EQ_CTRL_CMD_EQID(x)	\
6195     (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
6196 
6197 #define S_FW_EQ_CTRL_CMD_PHYSEQID	0
6198 #define M_FW_EQ_CTRL_CMD_PHYSEQID	0xfffff
6199 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x)	((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
6200 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x)	\
6201     (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
6202 
6203 #define S_FW_EQ_CTRL_CMD_FETCHSZM	26
6204 #define M_FW_EQ_CTRL_CMD_FETCHSZM	0x1
6205 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
6206 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x)	\
6207     (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
6208 #define F_FW_EQ_CTRL_CMD_FETCHSZM	V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
6209 
6210 #define S_FW_EQ_CTRL_CMD_STATUSPGNS	25
6211 #define M_FW_EQ_CTRL_CMD_STATUSPGNS	0x1
6212 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
6213 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x)	\
6214     (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
6215 #define F_FW_EQ_CTRL_CMD_STATUSPGNS	V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
6216 
6217 #define S_FW_EQ_CTRL_CMD_STATUSPGRO	24
6218 #define M_FW_EQ_CTRL_CMD_STATUSPGRO	0x1
6219 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
6220 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x)	\
6221     (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
6222 #define F_FW_EQ_CTRL_CMD_STATUSPGRO	V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
6223 
6224 #define S_FW_EQ_CTRL_CMD_FETCHNS	23
6225 #define M_FW_EQ_CTRL_CMD_FETCHNS	0x1
6226 #define V_FW_EQ_CTRL_CMD_FETCHNS(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
6227 #define G_FW_EQ_CTRL_CMD_FETCHNS(x)	\
6228     (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
6229 #define F_FW_EQ_CTRL_CMD_FETCHNS	V_FW_EQ_CTRL_CMD_FETCHNS(1U)
6230 
6231 #define S_FW_EQ_CTRL_CMD_FETCHRO	22
6232 #define M_FW_EQ_CTRL_CMD_FETCHRO	0x1
6233 #define V_FW_EQ_CTRL_CMD_FETCHRO(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
6234 #define G_FW_EQ_CTRL_CMD_FETCHRO(x)	\
6235     (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
6236 #define F_FW_EQ_CTRL_CMD_FETCHRO	V_FW_EQ_CTRL_CMD_FETCHRO(1U)
6237 
6238 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE	20
6239 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE	0x3
6240 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
6241 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	\
6242     (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
6243 
6244 #define S_FW_EQ_CTRL_CMD_CPRIO		19
6245 #define M_FW_EQ_CTRL_CMD_CPRIO		0x1
6246 #define V_FW_EQ_CTRL_CMD_CPRIO(x)	((x) << S_FW_EQ_CTRL_CMD_CPRIO)
6247 #define G_FW_EQ_CTRL_CMD_CPRIO(x)	\
6248     (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
6249 #define F_FW_EQ_CTRL_CMD_CPRIO		V_FW_EQ_CTRL_CMD_CPRIO(1U)
6250 
6251 #define S_FW_EQ_CTRL_CMD_ONCHIP		18
6252 #define M_FW_EQ_CTRL_CMD_ONCHIP		0x1
6253 #define V_FW_EQ_CTRL_CMD_ONCHIP(x)	((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
6254 #define G_FW_EQ_CTRL_CMD_ONCHIP(x)	\
6255     (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
6256 #define F_FW_EQ_CTRL_CMD_ONCHIP		V_FW_EQ_CTRL_CMD_ONCHIP(1U)
6257 
6258 #define S_FW_EQ_CTRL_CMD_PCIECHN	16
6259 #define M_FW_EQ_CTRL_CMD_PCIECHN	0x3
6260 #define V_FW_EQ_CTRL_CMD_PCIECHN(x)	((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
6261 #define G_FW_EQ_CTRL_CMD_PCIECHN(x)	\
6262     (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
6263 
6264 #define S_FW_EQ_CTRL_CMD_IQID		0
6265 #define M_FW_EQ_CTRL_CMD_IQID		0xffff
6266 #define V_FW_EQ_CTRL_CMD_IQID(x)	((x) << S_FW_EQ_CTRL_CMD_IQID)
6267 #define G_FW_EQ_CTRL_CMD_IQID(x)	\
6268     (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
6269 
6270 #define S_FW_EQ_CTRL_CMD_DCAEN		31
6271 #define M_FW_EQ_CTRL_CMD_DCAEN		0x1
6272 #define V_FW_EQ_CTRL_CMD_DCAEN(x)	((x) << S_FW_EQ_CTRL_CMD_DCAEN)
6273 #define G_FW_EQ_CTRL_CMD_DCAEN(x)	\
6274     (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
6275 #define F_FW_EQ_CTRL_CMD_DCAEN		V_FW_EQ_CTRL_CMD_DCAEN(1U)
6276 
6277 #define S_FW_EQ_CTRL_CMD_DCACPU		26
6278 #define M_FW_EQ_CTRL_CMD_DCACPU		0x1f
6279 #define V_FW_EQ_CTRL_CMD_DCACPU(x)	((x) << S_FW_EQ_CTRL_CMD_DCACPU)
6280 #define G_FW_EQ_CTRL_CMD_DCACPU(x)	\
6281     (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
6282 
6283 #define S_FW_EQ_CTRL_CMD_FBMIN		23
6284 #define M_FW_EQ_CTRL_CMD_FBMIN		0x7
6285 #define V_FW_EQ_CTRL_CMD_FBMIN(x)	((x) << S_FW_EQ_CTRL_CMD_FBMIN)
6286 #define G_FW_EQ_CTRL_CMD_FBMIN(x)	\
6287     (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
6288 
6289 #define S_FW_EQ_CTRL_CMD_FBMAX		20
6290 #define M_FW_EQ_CTRL_CMD_FBMAX		0x7
6291 #define V_FW_EQ_CTRL_CMD_FBMAX(x)	((x) << S_FW_EQ_CTRL_CMD_FBMAX)
6292 #define G_FW_EQ_CTRL_CMD_FBMAX(x)	\
6293     (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
6294 
6295 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO	19
6296 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO	0x1
6297 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6298     ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6299 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6300     (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6301 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO	V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
6302 
6303 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH	16
6304 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH	0x7
6305 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6306 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	\
6307     (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6308 
6309 #define S_FW_EQ_CTRL_CMD_EQSIZE		0
6310 #define M_FW_EQ_CTRL_CMD_EQSIZE		0xffff
6311 #define V_FW_EQ_CTRL_CMD_EQSIZE(x)	((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
6312 #define G_FW_EQ_CTRL_CMD_EQSIZE(x)	\
6313     (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
6314 
6315 struct fw_eq_ofld_cmd {
6316 	__be32 op_to_vfn;
6317 	__be32 alloc_to_len16;
6318 	__be32 eqid_pkd;
6319 	__be32 physeqid_pkd;
6320 	__be32 fetchszm_to_iqid;
6321 	__be32 dcaen_to_eqsize;
6322 	__be64 eqaddr;
6323 };
6324 
6325 #define S_FW_EQ_OFLD_CMD_PFN		8
6326 #define M_FW_EQ_OFLD_CMD_PFN		0x7
6327 #define V_FW_EQ_OFLD_CMD_PFN(x)		((x) << S_FW_EQ_OFLD_CMD_PFN)
6328 #define G_FW_EQ_OFLD_CMD_PFN(x)		\
6329     (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
6330 
6331 #define S_FW_EQ_OFLD_CMD_VFN		0
6332 #define M_FW_EQ_OFLD_CMD_VFN		0xff
6333 #define V_FW_EQ_OFLD_CMD_VFN(x)		((x) << S_FW_EQ_OFLD_CMD_VFN)
6334 #define G_FW_EQ_OFLD_CMD_VFN(x)		\
6335     (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
6336 
6337 #define S_FW_EQ_OFLD_CMD_ALLOC		31
6338 #define M_FW_EQ_OFLD_CMD_ALLOC		0x1
6339 #define V_FW_EQ_OFLD_CMD_ALLOC(x)	((x) << S_FW_EQ_OFLD_CMD_ALLOC)
6340 #define G_FW_EQ_OFLD_CMD_ALLOC(x)	\
6341     (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
6342 #define F_FW_EQ_OFLD_CMD_ALLOC		V_FW_EQ_OFLD_CMD_ALLOC(1U)
6343 
6344 #define S_FW_EQ_OFLD_CMD_FREE		30
6345 #define M_FW_EQ_OFLD_CMD_FREE		0x1
6346 #define V_FW_EQ_OFLD_CMD_FREE(x)	((x) << S_FW_EQ_OFLD_CMD_FREE)
6347 #define G_FW_EQ_OFLD_CMD_FREE(x)	\
6348     (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
6349 #define F_FW_EQ_OFLD_CMD_FREE		V_FW_EQ_OFLD_CMD_FREE(1U)
6350 
6351 #define S_FW_EQ_OFLD_CMD_MODIFY		29
6352 #define M_FW_EQ_OFLD_CMD_MODIFY		0x1
6353 #define V_FW_EQ_OFLD_CMD_MODIFY(x)	((x) << S_FW_EQ_OFLD_CMD_MODIFY)
6354 #define G_FW_EQ_OFLD_CMD_MODIFY(x)	\
6355     (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
6356 #define F_FW_EQ_OFLD_CMD_MODIFY		V_FW_EQ_OFLD_CMD_MODIFY(1U)
6357 
6358 #define S_FW_EQ_OFLD_CMD_EQSTART	28
6359 #define M_FW_EQ_OFLD_CMD_EQSTART	0x1
6360 #define V_FW_EQ_OFLD_CMD_EQSTART(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTART)
6361 #define G_FW_EQ_OFLD_CMD_EQSTART(x)	\
6362     (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
6363 #define F_FW_EQ_OFLD_CMD_EQSTART	V_FW_EQ_OFLD_CMD_EQSTART(1U)
6364 
6365 #define S_FW_EQ_OFLD_CMD_EQSTOP		27
6366 #define M_FW_EQ_OFLD_CMD_EQSTOP		0x1
6367 #define V_FW_EQ_OFLD_CMD_EQSTOP(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
6368 #define G_FW_EQ_OFLD_CMD_EQSTOP(x)	\
6369     (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
6370 #define F_FW_EQ_OFLD_CMD_EQSTOP		V_FW_EQ_OFLD_CMD_EQSTOP(1U)
6371 
6372 #define S_FW_EQ_OFLD_CMD_EQID		0
6373 #define M_FW_EQ_OFLD_CMD_EQID		0xfffff
6374 #define V_FW_EQ_OFLD_CMD_EQID(x)	((x) << S_FW_EQ_OFLD_CMD_EQID)
6375 #define G_FW_EQ_OFLD_CMD_EQID(x)	\
6376     (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
6377 
6378 #define S_FW_EQ_OFLD_CMD_PHYSEQID	0
6379 #define M_FW_EQ_OFLD_CMD_PHYSEQID	0xfffff
6380 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x)	((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
6381 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x)	\
6382     (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
6383 
6384 #define S_FW_EQ_OFLD_CMD_FETCHSZM	26
6385 #define M_FW_EQ_OFLD_CMD_FETCHSZM	0x1
6386 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
6387 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x)	\
6388     (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
6389 #define F_FW_EQ_OFLD_CMD_FETCHSZM	V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
6390 
6391 #define S_FW_EQ_OFLD_CMD_STATUSPGNS	25
6392 #define M_FW_EQ_OFLD_CMD_STATUSPGNS	0x1
6393 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
6394 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x)	\
6395     (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
6396 #define F_FW_EQ_OFLD_CMD_STATUSPGNS	V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
6397 
6398 #define S_FW_EQ_OFLD_CMD_STATUSPGRO	24
6399 #define M_FW_EQ_OFLD_CMD_STATUSPGRO	0x1
6400 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
6401 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x)	\
6402     (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
6403 #define F_FW_EQ_OFLD_CMD_STATUSPGRO	V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
6404 
6405 #define S_FW_EQ_OFLD_CMD_FETCHNS	23
6406 #define M_FW_EQ_OFLD_CMD_FETCHNS	0x1
6407 #define V_FW_EQ_OFLD_CMD_FETCHNS(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
6408 #define G_FW_EQ_OFLD_CMD_FETCHNS(x)	\
6409     (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
6410 #define F_FW_EQ_OFLD_CMD_FETCHNS	V_FW_EQ_OFLD_CMD_FETCHNS(1U)
6411 
6412 #define S_FW_EQ_OFLD_CMD_FETCHRO	22
6413 #define M_FW_EQ_OFLD_CMD_FETCHRO	0x1
6414 #define V_FW_EQ_OFLD_CMD_FETCHRO(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
6415 #define G_FW_EQ_OFLD_CMD_FETCHRO(x)	\
6416     (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
6417 #define F_FW_EQ_OFLD_CMD_FETCHRO	V_FW_EQ_OFLD_CMD_FETCHRO(1U)
6418 
6419 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE	20
6420 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE	0x3
6421 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
6422 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	\
6423     (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
6424 
6425 #define S_FW_EQ_OFLD_CMD_CPRIO		19
6426 #define M_FW_EQ_OFLD_CMD_CPRIO		0x1
6427 #define V_FW_EQ_OFLD_CMD_CPRIO(x)	((x) << S_FW_EQ_OFLD_CMD_CPRIO)
6428 #define G_FW_EQ_OFLD_CMD_CPRIO(x)	\
6429     (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
6430 #define F_FW_EQ_OFLD_CMD_CPRIO		V_FW_EQ_OFLD_CMD_CPRIO(1U)
6431 
6432 #define S_FW_EQ_OFLD_CMD_ONCHIP		18
6433 #define M_FW_EQ_OFLD_CMD_ONCHIP		0x1
6434 #define V_FW_EQ_OFLD_CMD_ONCHIP(x)	((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
6435 #define G_FW_EQ_OFLD_CMD_ONCHIP(x)	\
6436     (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
6437 #define F_FW_EQ_OFLD_CMD_ONCHIP		V_FW_EQ_OFLD_CMD_ONCHIP(1U)
6438 
6439 #define S_FW_EQ_OFLD_CMD_PCIECHN	16
6440 #define M_FW_EQ_OFLD_CMD_PCIECHN	0x3
6441 #define V_FW_EQ_OFLD_CMD_PCIECHN(x)	((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
6442 #define G_FW_EQ_OFLD_CMD_PCIECHN(x)	\
6443     (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
6444 
6445 #define S_FW_EQ_OFLD_CMD_IQID		0
6446 #define M_FW_EQ_OFLD_CMD_IQID		0xffff
6447 #define V_FW_EQ_OFLD_CMD_IQID(x)	((x) << S_FW_EQ_OFLD_CMD_IQID)
6448 #define G_FW_EQ_OFLD_CMD_IQID(x)	\
6449     (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
6450 
6451 #define S_FW_EQ_OFLD_CMD_DCAEN		31
6452 #define M_FW_EQ_OFLD_CMD_DCAEN		0x1
6453 #define V_FW_EQ_OFLD_CMD_DCAEN(x)	((x) << S_FW_EQ_OFLD_CMD_DCAEN)
6454 #define G_FW_EQ_OFLD_CMD_DCAEN(x)	\
6455     (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
6456 #define F_FW_EQ_OFLD_CMD_DCAEN		V_FW_EQ_OFLD_CMD_DCAEN(1U)
6457 
6458 #define S_FW_EQ_OFLD_CMD_DCACPU		26
6459 #define M_FW_EQ_OFLD_CMD_DCACPU		0x1f
6460 #define V_FW_EQ_OFLD_CMD_DCACPU(x)	((x) << S_FW_EQ_OFLD_CMD_DCACPU)
6461 #define G_FW_EQ_OFLD_CMD_DCACPU(x)	\
6462     (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
6463 
6464 #define S_FW_EQ_OFLD_CMD_FBMIN		23
6465 #define M_FW_EQ_OFLD_CMD_FBMIN		0x7
6466 #define V_FW_EQ_OFLD_CMD_FBMIN(x)	((x) << S_FW_EQ_OFLD_CMD_FBMIN)
6467 #define G_FW_EQ_OFLD_CMD_FBMIN(x)	\
6468     (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
6469 
6470 #define S_FW_EQ_OFLD_CMD_FBMAX		20
6471 #define M_FW_EQ_OFLD_CMD_FBMAX		0x7
6472 #define V_FW_EQ_OFLD_CMD_FBMAX(x)	((x) << S_FW_EQ_OFLD_CMD_FBMAX)
6473 #define G_FW_EQ_OFLD_CMD_FBMAX(x)	\
6474     (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
6475 
6476 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO	19
6477 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO	0x1
6478 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6479     ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6480 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6481     (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6482 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO	V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
6483 
6484 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH	16
6485 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH	0x7
6486 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6487 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	\
6488     (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6489 
6490 #define S_FW_EQ_OFLD_CMD_EQSIZE		0
6491 #define M_FW_EQ_OFLD_CMD_EQSIZE		0xffff
6492 #define V_FW_EQ_OFLD_CMD_EQSIZE(x)	((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
6493 #define G_FW_EQ_OFLD_CMD_EQSIZE(x)	\
6494     (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
6495 
6496 /* Macros for VIID parsing:
6497    VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
6498 #define S_FW_VIID_PFN		8
6499 #define M_FW_VIID_PFN		0x7
6500 #define V_FW_VIID_PFN(x)	((x) << S_FW_VIID_PFN)
6501 #define G_FW_VIID_PFN(x)	(((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
6502 
6503 #define S_FW_VIID_VIVLD		7
6504 #define M_FW_VIID_VIVLD		0x1
6505 #define V_FW_VIID_VIVLD(x)	((x) << S_FW_VIID_VIVLD)
6506 #define G_FW_VIID_VIVLD(x)	(((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
6507 
6508 #define S_FW_VIID_VIN		0
6509 #define M_FW_VIID_VIN		0x7F
6510 #define V_FW_VIID_VIN(x)	((x) << S_FW_VIID_VIN)
6511 #define G_FW_VIID_VIN(x)	(((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
6512 
6513 /* Macros for VIID parsing:
6514    VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */
6515 #define S_FW_256VIID_PFN		9
6516 #define M_FW_256VIID_PFN		0x7
6517 #define V_FW_256VIID_PFN(x)		((x) << S_FW_256VIID_PFN)
6518 #define G_FW_256VIID_PFN(x)		(((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)
6519 
6520 #define S_FW_256VIID_VIVLD		8
6521 #define M_FW_256VIID_VIVLD		0x1
6522 #define V_FW_256VIID_VIVLD(x)		((x) << S_FW_256VIID_VIVLD)
6523 #define G_FW_256VIID_VIVLD(x)		(((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)
6524 
6525 #define S_FW_256VIID_VIN		0
6526 #define M_FW_256VIID_VIN		0xFF
6527 #define V_FW_256VIID_VIN(x)		((x) << S_FW_256VIID_VIN)
6528 #define G_FW_256VIID_VIN(x)		(((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)
6529 
6530 enum fw_vi_func {
6531 	FW_VI_FUNC_ETH,
6532 	FW_VI_FUNC_OFLD,
6533 	FW_VI_FUNC_IWARP,
6534 	FW_VI_FUNC_OPENISCSI,
6535 	FW_VI_FUNC_OPENFCOE,
6536 	FW_VI_FUNC_FOISCSI,
6537 	FW_VI_FUNC_FOFCOE,
6538 	FW_VI_FUNC_FW,
6539 };
6540 
6541 struct fw_vi_cmd {
6542 	__be32 op_to_vfn;
6543 	__be32 alloc_to_len16;
6544 	__be16 type_to_viid;
6545 	__u8   mac[6];
6546 	__u8   portid_pkd;
6547 	__u8   nmac;
6548 	__u8   nmac0[6];
6549 	__be16 norss_rsssize;
6550 	__u8   nmac1[6];
6551 	__be16 idsiiq_pkd;
6552 	__u8   nmac2[6];
6553 	__be16 idseiq_pkd;
6554 	__u8   nmac3[6];
6555 	__be64 r9;
6556 	__be64 r10;
6557 };
6558 
6559 #define S_FW_VI_CMD_PFN			8
6560 #define M_FW_VI_CMD_PFN			0x7
6561 #define V_FW_VI_CMD_PFN(x)		((x) << S_FW_VI_CMD_PFN)
6562 #define G_FW_VI_CMD_PFN(x)		\
6563     (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
6564 
6565 #define S_FW_VI_CMD_VFN			0
6566 #define M_FW_VI_CMD_VFN			0xff
6567 #define V_FW_VI_CMD_VFN(x)		((x) << S_FW_VI_CMD_VFN)
6568 #define G_FW_VI_CMD_VFN(x)		\
6569     (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
6570 
6571 #define S_FW_VI_CMD_ALLOC		31
6572 #define M_FW_VI_CMD_ALLOC		0x1
6573 #define V_FW_VI_CMD_ALLOC(x)		((x) << S_FW_VI_CMD_ALLOC)
6574 #define G_FW_VI_CMD_ALLOC(x)		\
6575     (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
6576 #define F_FW_VI_CMD_ALLOC		V_FW_VI_CMD_ALLOC(1U)
6577 
6578 #define S_FW_VI_CMD_FREE		30
6579 #define M_FW_VI_CMD_FREE		0x1
6580 #define V_FW_VI_CMD_FREE(x)		((x) << S_FW_VI_CMD_FREE)
6581 #define G_FW_VI_CMD_FREE(x)		\
6582     (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
6583 #define F_FW_VI_CMD_FREE		V_FW_VI_CMD_FREE(1U)
6584 
6585 #define S_FW_VI_CMD_VFVLD		24
6586 #define M_FW_VI_CMD_VFVLD		0x1
6587 #define V_FW_VI_CMD_VFVLD(x)		((x) << S_FW_VI_CMD_VFVLD)
6588 #define G_FW_VI_CMD_VFVLD(x)		\
6589     (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
6590 #define F_FW_VI_CMD_VFVLD		V_FW_VI_CMD_VFVLD(1U)
6591 
6592 #define S_FW_VI_CMD_VIN			16
6593 #define M_FW_VI_CMD_VIN			0xff
6594 #define V_FW_VI_CMD_VIN(x)		((x) << S_FW_VI_CMD_VIN)
6595 #define G_FW_VI_CMD_VIN(x)		\
6596     (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
6597 
6598 #define S_FW_VI_CMD_TYPE		15
6599 #define M_FW_VI_CMD_TYPE		0x1
6600 #define V_FW_VI_CMD_TYPE(x)		((x) << S_FW_VI_CMD_TYPE)
6601 #define G_FW_VI_CMD_TYPE(x)		\
6602     (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
6603 #define F_FW_VI_CMD_TYPE		V_FW_VI_CMD_TYPE(1U)
6604 
6605 #define S_FW_VI_CMD_FUNC		12
6606 #define M_FW_VI_CMD_FUNC		0x7
6607 #define V_FW_VI_CMD_FUNC(x)		((x) << S_FW_VI_CMD_FUNC)
6608 #define G_FW_VI_CMD_FUNC(x)		\
6609     (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
6610 
6611 #define S_FW_VI_CMD_VIID		0
6612 #define M_FW_VI_CMD_VIID		0xfff
6613 #define V_FW_VI_CMD_VIID(x)		((x) << S_FW_VI_CMD_VIID)
6614 #define G_FW_VI_CMD_VIID(x)		\
6615     (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
6616 
6617 #define S_FW_VI_CMD_PORTID		4
6618 #define M_FW_VI_CMD_PORTID		0xf
6619 #define V_FW_VI_CMD_PORTID(x)		((x) << S_FW_VI_CMD_PORTID)
6620 #define G_FW_VI_CMD_PORTID(x)		\
6621     (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
6622 
6623 #define S_FW_VI_CMD_NORSS		11
6624 #define M_FW_VI_CMD_NORSS		0x1
6625 #define V_FW_VI_CMD_NORSS(x)		((x) << S_FW_VI_CMD_NORSS)
6626 #define G_FW_VI_CMD_NORSS(x)		\
6627     (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
6628 #define F_FW_VI_CMD_NORSS		V_FW_VI_CMD_NORSS(1U)
6629 
6630 #define S_FW_VI_CMD_RSSSIZE		0
6631 #define M_FW_VI_CMD_RSSSIZE		0x7ff
6632 #define V_FW_VI_CMD_RSSSIZE(x)		((x) << S_FW_VI_CMD_RSSSIZE)
6633 #define G_FW_VI_CMD_RSSSIZE(x)		\
6634     (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
6635 
6636 #define S_FW_VI_CMD_IDSIIQ		0
6637 #define M_FW_VI_CMD_IDSIIQ		0x3ff
6638 #define V_FW_VI_CMD_IDSIIQ(x)		((x) << S_FW_VI_CMD_IDSIIQ)
6639 #define G_FW_VI_CMD_IDSIIQ(x)		\
6640     (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
6641 
6642 #define S_FW_VI_CMD_IDSEIQ		0
6643 #define M_FW_VI_CMD_IDSEIQ		0x3ff
6644 #define V_FW_VI_CMD_IDSEIQ(x)		((x) << S_FW_VI_CMD_IDSEIQ)
6645 #define G_FW_VI_CMD_IDSEIQ(x)		\
6646     (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
6647 
6648 /* Special VI_MAC command index ids */
6649 #define FW_VI_MAC_ADD_MAC		0x3FF
6650 #define FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
6651 #define FW_VI_MAC_MAC_BASED_FREE	0x3FD
6652 #define FW_VI_MAC_ID_BASED_FREE		0x3FC
6653 
6654 enum fw_vi_mac_smac {
6655 	FW_VI_MAC_MPS_TCAM_ENTRY,
6656 	FW_VI_MAC_MPS_TCAM_ONLY,
6657 	FW_VI_MAC_SMT_ONLY,
6658 	FW_VI_MAC_SMT_AND_MPSTCAM
6659 };
6660 
6661 enum fw_vi_mac_result {
6662 	FW_VI_MAC_R_SUCCESS,
6663 	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
6664 	FW_VI_MAC_R_SMAC_FAIL,
6665 	FW_VI_MAC_R_F_ACL_CHECK
6666 };
6667 
6668 enum fw_vi_mac_entry_types {
6669 	FW_VI_MAC_TYPE_EXACTMAC,
6670 	FW_VI_MAC_TYPE_HASHVEC,
6671 	FW_VI_MAC_TYPE_RAW,
6672 	FW_VI_MAC_TYPE_EXACTMAC_VNI,
6673 };
6674 
6675 struct fw_vi_mac_cmd {
6676 	__be32 op_to_viid;
6677 	__be32 freemacs_to_len16;
6678 	union fw_vi_mac {
6679 		struct fw_vi_mac_exact {
6680 			__be16 valid_to_idx;
6681 			__u8   macaddr[6];
6682 		} exact[7];
6683 		struct fw_vi_mac_hash {
6684 			__be64 hashvec;
6685 		} hash;
6686 		struct fw_vi_mac_raw {
6687 			__be32 raw_idx_pkd;
6688 			__be32 data0_pkd;
6689 			__be32 data1[2];
6690 			__be64 data0m_pkd;
6691 			__be32 data1m[2];
6692 		} raw;
6693 		struct fw_vi_mac_vni {
6694 			__be16 valid_to_idx;
6695 			__u8   macaddr[6];
6696 			__be16 r7;
6697 			__u8   macaddr_mask[6];
6698 			__be32 lookup_type_to_vni;
6699 			__be32 vni_mask_pkd;
6700 		} exact_vni[2];
6701 	} u;
6702 };
6703 
6704 #define S_FW_VI_MAC_CMD_SMTID		12
6705 #define M_FW_VI_MAC_CMD_SMTID		0xff
6706 #define V_FW_VI_MAC_CMD_SMTID(x)	((x) << S_FW_VI_MAC_CMD_SMTID)
6707 #define G_FW_VI_MAC_CMD_SMTID(x)	\
6708     (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID)
6709 
6710 #define S_FW_VI_MAC_CMD_VIID		0
6711 #define M_FW_VI_MAC_CMD_VIID		0xfff
6712 #define V_FW_VI_MAC_CMD_VIID(x)		((x) << S_FW_VI_MAC_CMD_VIID)
6713 #define G_FW_VI_MAC_CMD_VIID(x)		\
6714     (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
6715 
6716 #define S_FW_VI_MAC_CMD_FREEMACS	31
6717 #define M_FW_VI_MAC_CMD_FREEMACS	0x1
6718 #define V_FW_VI_MAC_CMD_FREEMACS(x)	((x) << S_FW_VI_MAC_CMD_FREEMACS)
6719 #define G_FW_VI_MAC_CMD_FREEMACS(x)	\
6720     (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
6721 #define F_FW_VI_MAC_CMD_FREEMACS	V_FW_VI_MAC_CMD_FREEMACS(1U)
6722 
6723 #define S_FW_VI_MAC_CMD_IS_SMAC		30
6724 #define M_FW_VI_MAC_CMD_IS_SMAC		0x1
6725 #define V_FW_VI_MAC_CMD_IS_SMAC(x)	((x) << S_FW_VI_MAC_CMD_IS_SMAC)
6726 #define G_FW_VI_MAC_CMD_IS_SMAC(x)	\
6727     (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC)
6728 #define F_FW_VI_MAC_CMD_IS_SMAC	V_FW_VI_MAC_CMD_IS_SMAC(1U)
6729 
6730 #define S_FW_VI_MAC_CMD_ENTRY_TYPE	23
6731 #define M_FW_VI_MAC_CMD_ENTRY_TYPE	0x7
6732 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)	((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
6733 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x)	\
6734     (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
6735 
6736 #define S_FW_VI_MAC_CMD_HASHUNIEN	22
6737 #define M_FW_VI_MAC_CMD_HASHUNIEN	0x1
6738 #define V_FW_VI_MAC_CMD_HASHUNIEN(x)	((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
6739 #define G_FW_VI_MAC_CMD_HASHUNIEN(x)	\
6740     (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
6741 #define F_FW_VI_MAC_CMD_HASHUNIEN	V_FW_VI_MAC_CMD_HASHUNIEN(1U)
6742 
6743 #define S_FW_VI_MAC_CMD_VALID		15
6744 #define M_FW_VI_MAC_CMD_VALID		0x1
6745 #define V_FW_VI_MAC_CMD_VALID(x)	((x) << S_FW_VI_MAC_CMD_VALID)
6746 #define G_FW_VI_MAC_CMD_VALID(x)	\
6747     (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
6748 #define F_FW_VI_MAC_CMD_VALID		V_FW_VI_MAC_CMD_VALID(1U)
6749 
6750 #define S_FW_VI_MAC_CMD_PRIO		12
6751 #define M_FW_VI_MAC_CMD_PRIO		0x7
6752 #define V_FW_VI_MAC_CMD_PRIO(x)		((x) << S_FW_VI_MAC_CMD_PRIO)
6753 #define G_FW_VI_MAC_CMD_PRIO(x)		\
6754     (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
6755 
6756 #define S_FW_VI_MAC_CMD_SMAC_RESULT	10
6757 #define M_FW_VI_MAC_CMD_SMAC_RESULT	0x3
6758 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x)	((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
6759 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x)	\
6760     (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
6761 
6762 #define S_FW_VI_MAC_CMD_IDX		0
6763 #define M_FW_VI_MAC_CMD_IDX		0x3ff
6764 #define V_FW_VI_MAC_CMD_IDX(x)		((x) << S_FW_VI_MAC_CMD_IDX)
6765 #define G_FW_VI_MAC_CMD_IDX(x)		\
6766     (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
6767 
6768 #define S_FW_VI_MAC_CMD_RAW_IDX		16
6769 #define M_FW_VI_MAC_CMD_RAW_IDX		0xffff
6770 #define V_FW_VI_MAC_CMD_RAW_IDX(x)	((x) << S_FW_VI_MAC_CMD_RAW_IDX)
6771 #define G_FW_VI_MAC_CMD_RAW_IDX(x)	\
6772     (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
6773 
6774 #define S_FW_VI_MAC_CMD_DATA0		0
6775 #define M_FW_VI_MAC_CMD_DATA0		0xffff
6776 #define V_FW_VI_MAC_CMD_DATA0(x)	((x) << S_FW_VI_MAC_CMD_DATA0)
6777 #define G_FW_VI_MAC_CMD_DATA0(x)	\
6778     (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
6779 
6780 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE	31
6781 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE	0x1
6782 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x)	((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)
6783 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x)	\
6784     (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)
6785 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE	V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)
6786 
6787 #define S_FW_VI_MAC_CMD_DIP_HIT		30
6788 #define M_FW_VI_MAC_CMD_DIP_HIT		0x1
6789 #define V_FW_VI_MAC_CMD_DIP_HIT(x)	((x) << S_FW_VI_MAC_CMD_DIP_HIT)
6790 #define G_FW_VI_MAC_CMD_DIP_HIT(x)	\
6791     (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)
6792 #define F_FW_VI_MAC_CMD_DIP_HIT	V_FW_VI_MAC_CMD_DIP_HIT(1U)
6793 
6794 #define S_FW_VI_MAC_CMD_VNI	0
6795 #define M_FW_VI_MAC_CMD_VNI	0xffffff
6796 #define V_FW_VI_MAC_CMD_VNI(x)	((x) << S_FW_VI_MAC_CMD_VNI)
6797 #define G_FW_VI_MAC_CMD_VNI(x)	\
6798     (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)
6799 
6800 /* Extracting loopback port number passed from driver.
6801  * as a part of fw_vi_mac_vni For non loopback entries
6802  * ignore the field and update port number from flowc.
6803  * Fw will ignore if physical port number received.
6804  * expected range (4-7).
6805  */
6806 
6807 #define S_FW_VI_MAC_CMD_PORT            24
6808 #define M_FW_VI_MAC_CMD_PORT            0x7
6809 #define V_FW_VI_MAC_CMD_PORT(x)         ((x) << S_FW_VI_MAC_CMD_PORT)
6810 #define G_FW_VI_MAC_CMD_PORT(x)         \
6811     (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT)
6812 
6813 #define S_FW_VI_MAC_CMD_VNI_MASK	0
6814 #define M_FW_VI_MAC_CMD_VNI_MASK	0xffffff
6815 #define V_FW_VI_MAC_CMD_VNI_MASK(x)	((x) << S_FW_VI_MAC_CMD_VNI_MASK)
6816 #define G_FW_VI_MAC_CMD_VNI_MASK(x)	\
6817     (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)
6818 
6819 /* T4 max MTU supported */
6820 #define T4_MAX_MTU_SUPPORTED	9600
6821 #define FW_RXMODE_MTU_NO_CHG	65535
6822 
6823 struct fw_vi_rxmode_cmd {
6824 	__be32 op_to_viid;
6825 	__be32 retval_len16;
6826 	__be32 mtu_to_vlanexen;
6827 	__be32 r4_lo;
6828 };
6829 
6830 #define S_FW_VI_RXMODE_CMD_VIID		0
6831 #define M_FW_VI_RXMODE_CMD_VIID		0xfff
6832 #define V_FW_VI_RXMODE_CMD_VIID(x)	((x) << S_FW_VI_RXMODE_CMD_VIID)
6833 #define G_FW_VI_RXMODE_CMD_VIID(x)	\
6834     (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
6835 
6836 #define S_FW_VI_RXMODE_CMD_MTU		16
6837 #define M_FW_VI_RXMODE_CMD_MTU		0xffff
6838 #define V_FW_VI_RXMODE_CMD_MTU(x)	((x) << S_FW_VI_RXMODE_CMD_MTU)
6839 #define G_FW_VI_RXMODE_CMD_MTU(x)	\
6840     (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
6841 
6842 #define S_FW_VI_RXMODE_CMD_PROMISCEN	14
6843 #define M_FW_VI_RXMODE_CMD_PROMISCEN	0x3
6844 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x)	((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
6845 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x)	\
6846     (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
6847 
6848 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN	12
6849 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN	0x3
6850 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6851     ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
6852 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6853     (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
6854 
6855 #define S_FW_VI_RXMODE_CMD_BROADCASTEN	10
6856 #define M_FW_VI_RXMODE_CMD_BROADCASTEN	0x3
6857 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6858     ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
6859 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6860     (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
6861 
6862 #define S_FW_VI_RXMODE_CMD_VLANEXEN	8
6863 #define M_FW_VI_RXMODE_CMD_VLANEXEN	0x3
6864 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x)	((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
6865 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x)	\
6866     (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
6867 
6868 struct fw_vi_enable_cmd {
6869 	__be32 op_to_viid;
6870 	__be32 ien_to_len16;
6871 	__be16 blinkdur;
6872 	__be16 r3;
6873 	__be32 r4;
6874 };
6875 
6876 #define S_FW_VI_ENABLE_CMD_VIID		0
6877 #define M_FW_VI_ENABLE_CMD_VIID		0xfff
6878 #define V_FW_VI_ENABLE_CMD_VIID(x)	((x) << S_FW_VI_ENABLE_CMD_VIID)
6879 #define G_FW_VI_ENABLE_CMD_VIID(x)	\
6880     (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
6881 
6882 #define S_FW_VI_ENABLE_CMD_IEN		31
6883 #define M_FW_VI_ENABLE_CMD_IEN		0x1
6884 #define V_FW_VI_ENABLE_CMD_IEN(x)	((x) << S_FW_VI_ENABLE_CMD_IEN)
6885 #define G_FW_VI_ENABLE_CMD_IEN(x)	\
6886     (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
6887 #define F_FW_VI_ENABLE_CMD_IEN		V_FW_VI_ENABLE_CMD_IEN(1U)
6888 
6889 #define S_FW_VI_ENABLE_CMD_EEN		30
6890 #define M_FW_VI_ENABLE_CMD_EEN		0x1
6891 #define V_FW_VI_ENABLE_CMD_EEN(x)	((x) << S_FW_VI_ENABLE_CMD_EEN)
6892 #define G_FW_VI_ENABLE_CMD_EEN(x)	\
6893     (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
6894 #define F_FW_VI_ENABLE_CMD_EEN		V_FW_VI_ENABLE_CMD_EEN(1U)
6895 
6896 #define S_FW_VI_ENABLE_CMD_LED		29
6897 #define M_FW_VI_ENABLE_CMD_LED		0x1
6898 #define V_FW_VI_ENABLE_CMD_LED(x)	((x) << S_FW_VI_ENABLE_CMD_LED)
6899 #define G_FW_VI_ENABLE_CMD_LED(x)	\
6900     (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
6901 #define F_FW_VI_ENABLE_CMD_LED		V_FW_VI_ENABLE_CMD_LED(1U)
6902 
6903 #define S_FW_VI_ENABLE_CMD_DCB_INFO	28
6904 #define M_FW_VI_ENABLE_CMD_DCB_INFO	0x1
6905 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x)	((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
6906 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x)	\
6907     (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
6908 #define F_FW_VI_ENABLE_CMD_DCB_INFO	V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
6909 
6910 /* VI VF stats offset definitions */
6911 #define VI_VF_NUM_STATS	16
6912 enum fw_vi_stats_vf_index {
6913 	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
6914 	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
6915 	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
6916 	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
6917 	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
6918 	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
6919 	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
6920 	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
6921 	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
6922 	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
6923 	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
6924 	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
6925 	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
6926 	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
6927 	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
6928 	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
6929 };
6930 
6931 /* VI PF stats offset definitions */
6932 #define VI_PF_NUM_STATS	17
6933 enum fw_vi_stats_pf_index {
6934 	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
6935 	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
6936 	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
6937 	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
6938 	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
6939 	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
6940 	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
6941 	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
6942 	FW_VI_PF_STAT_RX_BYTES_IX,
6943 	FW_VI_PF_STAT_RX_FRAMES_IX,
6944 	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
6945 	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
6946 	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
6947 	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
6948 	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
6949 	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
6950 	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
6951 };
6952 
6953 struct fw_vi_stats_cmd {
6954 	__be32 op_to_viid;
6955 	__be32 retval_len16;
6956 	union fw_vi_stats {
6957 		struct fw_vi_stats_ctl {
6958 			__be16 nstats_ix;
6959 			__be16 r6;
6960 			__be32 r7;
6961 			__be64 stat0;
6962 			__be64 stat1;
6963 			__be64 stat2;
6964 			__be64 stat3;
6965 			__be64 stat4;
6966 			__be64 stat5;
6967 		} ctl;
6968 		struct fw_vi_stats_pf {
6969 			__be64 tx_bcast_bytes;
6970 			__be64 tx_bcast_frames;
6971 			__be64 tx_mcast_bytes;
6972 			__be64 tx_mcast_frames;
6973 			__be64 tx_ucast_bytes;
6974 			__be64 tx_ucast_frames;
6975 			__be64 tx_offload_bytes;
6976 			__be64 tx_offload_frames;
6977 			__be64 rx_pf_bytes;
6978 			__be64 rx_pf_frames;
6979 			__be64 rx_bcast_bytes;
6980 			__be64 rx_bcast_frames;
6981 			__be64 rx_mcast_bytes;
6982 			__be64 rx_mcast_frames;
6983 			__be64 rx_ucast_bytes;
6984 			__be64 rx_ucast_frames;
6985 			__be64 rx_err_frames;
6986 		} pf;
6987 		struct fw_vi_stats_vf {
6988 			__be64 tx_bcast_bytes;
6989 			__be64 tx_bcast_frames;
6990 			__be64 tx_mcast_bytes;
6991 			__be64 tx_mcast_frames;
6992 			__be64 tx_ucast_bytes;
6993 			__be64 tx_ucast_frames;
6994 			__be64 tx_drop_frames;
6995 			__be64 tx_offload_bytes;
6996 			__be64 tx_offload_frames;
6997 			__be64 rx_bcast_bytes;
6998 			__be64 rx_bcast_frames;
6999 			__be64 rx_mcast_bytes;
7000 			__be64 rx_mcast_frames;
7001 			__be64 rx_ucast_bytes;
7002 			__be64 rx_ucast_frames;
7003 			__be64 rx_err_frames;
7004 		} vf;
7005 	} u;
7006 };
7007 
7008 #define S_FW_VI_STATS_CMD_VIID		0
7009 #define M_FW_VI_STATS_CMD_VIID		0xfff
7010 #define V_FW_VI_STATS_CMD_VIID(x)	((x) << S_FW_VI_STATS_CMD_VIID)
7011 #define G_FW_VI_STATS_CMD_VIID(x)	\
7012     (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
7013 
7014 #define S_FW_VI_STATS_CMD_NSTATS	12
7015 #define M_FW_VI_STATS_CMD_NSTATS	0x7
7016 #define V_FW_VI_STATS_CMD_NSTATS(x)	((x) << S_FW_VI_STATS_CMD_NSTATS)
7017 #define G_FW_VI_STATS_CMD_NSTATS(x)	\
7018     (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
7019 
7020 #define S_FW_VI_STATS_CMD_IX		0
7021 #define M_FW_VI_STATS_CMD_IX		0x1f
7022 #define V_FW_VI_STATS_CMD_IX(x)		((x) << S_FW_VI_STATS_CMD_IX)
7023 #define G_FW_VI_STATS_CMD_IX(x)		\
7024     (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
7025 
7026 struct fw_acl_mac_cmd {
7027 	__be32 op_to_vfn;
7028 	__be32 en_to_len16;
7029 	__u8   nmac;
7030 	__u8   r3[7];
7031 	__be16 r4;
7032 	__u8   macaddr0[6];
7033 	__be16 r5;
7034 	__u8   macaddr1[6];
7035 	__be16 r6;
7036 	__u8   macaddr2[6];
7037 	__be16 r7;
7038 	__u8   macaddr3[6];
7039 };
7040 
7041 #define S_FW_ACL_MAC_CMD_PFN		8
7042 #define M_FW_ACL_MAC_CMD_PFN		0x7
7043 #define V_FW_ACL_MAC_CMD_PFN(x)		((x) << S_FW_ACL_MAC_CMD_PFN)
7044 #define G_FW_ACL_MAC_CMD_PFN(x)		\
7045     (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
7046 
7047 #define S_FW_ACL_MAC_CMD_VFN		0
7048 #define M_FW_ACL_MAC_CMD_VFN		0xff
7049 #define V_FW_ACL_MAC_CMD_VFN(x)		((x) << S_FW_ACL_MAC_CMD_VFN)
7050 #define G_FW_ACL_MAC_CMD_VFN(x)		\
7051     (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
7052 
7053 #define S_FW_ACL_MAC_CMD_EN		31
7054 #define M_FW_ACL_MAC_CMD_EN		0x1
7055 #define V_FW_ACL_MAC_CMD_EN(x)		((x) << S_FW_ACL_MAC_CMD_EN)
7056 #define G_FW_ACL_MAC_CMD_EN(x)		\
7057     (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
7058 #define F_FW_ACL_MAC_CMD_EN		V_FW_ACL_MAC_CMD_EN(1U)
7059 
7060 struct fw_acl_vlan_cmd {
7061 	__be32 op_to_vfn;
7062 	__be32 en_to_len16;
7063 	__u8   nvlan;
7064 	__u8   dropnovlan_fm;
7065 	__u8   r3_lo[6];
7066 	__be16 vlanid[16];
7067 };
7068 
7069 #define S_FW_ACL_VLAN_CMD_PFN		8
7070 #define M_FW_ACL_VLAN_CMD_PFN		0x7
7071 #define V_FW_ACL_VLAN_CMD_PFN(x)	((x) << S_FW_ACL_VLAN_CMD_PFN)
7072 #define G_FW_ACL_VLAN_CMD_PFN(x)	\
7073     (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
7074 
7075 #define S_FW_ACL_VLAN_CMD_VFN		0
7076 #define M_FW_ACL_VLAN_CMD_VFN		0xff
7077 #define V_FW_ACL_VLAN_CMD_VFN(x)	((x) << S_FW_ACL_VLAN_CMD_VFN)
7078 #define G_FW_ACL_VLAN_CMD_VFN(x)	\
7079     (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
7080 
7081 #define S_FW_ACL_VLAN_CMD_EN		31
7082 #define M_FW_ACL_VLAN_CMD_EN		0x1
7083 #define V_FW_ACL_VLAN_CMD_EN(x)		((x) << S_FW_ACL_VLAN_CMD_EN)
7084 #define G_FW_ACL_VLAN_CMD_EN(x)		\
7085     (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
7086 #define F_FW_ACL_VLAN_CMD_EN		V_FW_ACL_VLAN_CMD_EN(1U)
7087 
7088 #define S_FW_ACL_VLAN_CMD_TRANSPARENT	30
7089 #define M_FW_ACL_VLAN_CMD_TRANSPARENT	0x1
7090 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
7091     ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT)
7092 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
7093     (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT)
7094 #define F_FW_ACL_VLAN_CMD_TRANSPARENT	V_FW_ACL_VLAN_CMD_TRANSPARENT(1U)
7095 
7096 #define S_FW_ACL_VLAN_CMD_PMASK		16
7097 #define M_FW_ACL_VLAN_CMD_PMASK		0xf
7098 #define V_FW_ACL_VLAN_CMD_PMASK(x)	((x) << S_FW_ACL_VLAN_CMD_PMASK)
7099 #define G_FW_ACL_VLAN_CMD_PMASK(x)	\
7100     (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK)
7101 
7102 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN	7
7103 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN	0x1
7104 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
7105 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	\
7106     (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
7107 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN	V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
7108 
7109 #define S_FW_ACL_VLAN_CMD_FM		6
7110 #define M_FW_ACL_VLAN_CMD_FM		0x1
7111 #define V_FW_ACL_VLAN_CMD_FM(x)		((x) << S_FW_ACL_VLAN_CMD_FM)
7112 #define G_FW_ACL_VLAN_CMD_FM(x)		\
7113     (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
7114 #define F_FW_ACL_VLAN_CMD_FM		V_FW_ACL_VLAN_CMD_FM(1U)
7115 
7116 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
7117 enum fw_port_cap {
7118 	FW_PORT_CAP_SPEED_100M		= 0x0001,
7119 	FW_PORT_CAP_SPEED_1G		= 0x0002,
7120 	FW_PORT_CAP_SPEED_25G		= 0x0004,
7121 	FW_PORT_CAP_SPEED_10G		= 0x0008,
7122 	FW_PORT_CAP_SPEED_40G		= 0x0010,
7123 	FW_PORT_CAP_SPEED_100G		= 0x0020,
7124 	FW_PORT_CAP_FC_RX		= 0x0040,
7125 	FW_PORT_CAP_FC_TX		= 0x0080,
7126 	FW_PORT_CAP_ANEG		= 0x0100,
7127 	FW_PORT_CAP_MDIAUTO		= 0x0200,
7128 	FW_PORT_CAP_MDISTRAIGHT		= 0x0400,
7129 	FW_PORT_CAP_FEC_RS		= 0x0800,
7130 	FW_PORT_CAP_FEC_BASER_RS	= 0x1000,
7131 	FW_PORT_CAP_FORCE_PAUSE		= 0x2000,
7132 	FW_PORT_CAP_802_3_PAUSE		= 0x4000,
7133 	FW_PORT_CAP_802_3_ASM_DIR	= 0x8000,
7134 };
7135 
7136 #define S_FW_PORT_CAP_SPEED	0
7137 #define M_FW_PORT_CAP_SPEED	0x3f
7138 #define V_FW_PORT_CAP_SPEED(x)	((x) << S_FW_PORT_CAP_SPEED)
7139 #define G_FW_PORT_CAP_SPEED(x) \
7140     (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
7141 
7142 #define S_FW_PORT_CAP_FC	6
7143 #define M_FW_PORT_CAP_FC	0x3
7144 #define V_FW_PORT_CAP_FC(x)	((x) << S_FW_PORT_CAP_FC)
7145 #define G_FW_PORT_CAP_FC(x) \
7146     (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
7147 
7148 #define S_FW_PORT_CAP_ANEG	8
7149 #define M_FW_PORT_CAP_ANEG	0x1
7150 #define V_FW_PORT_CAP_ANEG(x)	((x) << S_FW_PORT_CAP_ANEG)
7151 #define G_FW_PORT_CAP_ANEG(x) \
7152     (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
7153 
7154 #define S_FW_PORT_CAP_FEC	11
7155 #define M_FW_PORT_CAP_FEC	0x3
7156 #define V_FW_PORT_CAP_FEC(x)	((x) << S_FW_PORT_CAP_FEC)
7157 #define G_FW_PORT_CAP_FEC(x) \
7158     (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
7159 
7160 #define S_FW_PORT_CAP_FORCE_PAUSE	13
7161 #define M_FW_PORT_CAP_FORCE_PAUSE	0x1
7162 #define V_FW_PORT_CAP_FORCE_PAUSE(x)	((x) << S_FW_PORT_CAP_FORCE_PAUSE)
7163 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \
7164     (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)
7165 
7166 #define S_FW_PORT_CAP_802_3	14
7167 #define M_FW_PORT_CAP_802_3	0x3
7168 #define V_FW_PORT_CAP_802_3(x)	((x) << S_FW_PORT_CAP_802_3)
7169 #define G_FW_PORT_CAP_802_3(x) \
7170     (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
7171 
7172 enum fw_port_mdi {
7173 	FW_PORT_CAP_MDI_UNCHANGED,
7174 	FW_PORT_CAP_MDI_AUTO,
7175 	FW_PORT_CAP_MDI_F_STRAIGHT,
7176 	FW_PORT_CAP_MDI_F_CROSSOVER
7177 };
7178 
7179 #define S_FW_PORT_CAP_MDI 9
7180 #define M_FW_PORT_CAP_MDI 3
7181 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
7182 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
7183 
7184 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
7185 #define	FW_PORT_CAP32_SPEED_100M	0x00000001UL
7186 #define	FW_PORT_CAP32_SPEED_1G		0x00000002UL
7187 #define	FW_PORT_CAP32_SPEED_10G		0x00000004UL
7188 #define	FW_PORT_CAP32_SPEED_25G		0x00000008UL
7189 #define	FW_PORT_CAP32_SPEED_40G		0x00000010UL
7190 #define	FW_PORT_CAP32_SPEED_50G		0x00000020UL
7191 #define	FW_PORT_CAP32_SPEED_100G	0x00000040UL
7192 #define	FW_PORT_CAP32_SPEED_200G	0x00000080UL
7193 #define	FW_PORT_CAP32_SPEED_400G	0x00000100UL
7194 #define	FW_PORT_CAP32_SPEED_RESERVED1	0x00000200UL
7195 #define	FW_PORT_CAP32_SPEED_RESERVED2	0x00000400UL
7196 #define	FW_PORT_CAP32_SPEED_RESERVED3	0x00000800UL
7197 #define	FW_PORT_CAP32_RESERVED1		0x0000f000UL
7198 #define	FW_PORT_CAP32_FC_RX		0x00010000UL
7199 #define	FW_PORT_CAP32_FC_TX		0x00020000UL
7200 #define	FW_PORT_CAP32_802_3_PAUSE	0x00040000UL
7201 #define	FW_PORT_CAP32_802_3_ASM_DIR	0x00080000UL
7202 #define	FW_PORT_CAP32_ANEG		0x00100000UL
7203 #define	FW_PORT_CAP32_MDIAUTO		0x00200000UL
7204 #define	FW_PORT_CAP32_MDISTRAIGHT	0x00400000UL
7205 #define	FW_PORT_CAP32_FEC_RS		0x00800000UL
7206 #define	FW_PORT_CAP32_FEC_BASER_RS	0x01000000UL
7207 #define	FW_PORT_CAP32_FEC_RESERVED1	0x02000000UL
7208 #define	FW_PORT_CAP32_FEC_RESERVED2	0x04000000UL
7209 #define	FW_PORT_CAP32_FEC_RESERVED3	0x08000000UL
7210 #define	FW_PORT_CAP32_FORCE_PAUSE	0x10000000UL
7211 #define	FW_PORT_CAP32_RESERVED2		0xe0000000UL
7212 
7213 #define S_FW_PORT_CAP32_SPEED	0
7214 #define M_FW_PORT_CAP32_SPEED	0xfff
7215 #define V_FW_PORT_CAP32_SPEED(x)	((x) << S_FW_PORT_CAP32_SPEED)
7216 #define G_FW_PORT_CAP32_SPEED(x) \
7217     (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
7218 
7219 #define S_FW_PORT_CAP32_FC	16
7220 #define M_FW_PORT_CAP32_FC	0x3
7221 #define V_FW_PORT_CAP32_FC(x)	((x) << S_FW_PORT_CAP32_FC)
7222 #define G_FW_PORT_CAP32_FC(x) \
7223     (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)
7224 
7225 #define S_FW_PORT_CAP32_802_3	18
7226 #define M_FW_PORT_CAP32_802_3	0x3
7227 #define V_FW_PORT_CAP32_802_3(x)	((x) << S_FW_PORT_CAP32_802_3)
7228 #define G_FW_PORT_CAP32_802_3(x) \
7229     (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)
7230 
7231 #define S_FW_PORT_CAP32_ANEG	20
7232 #define M_FW_PORT_CAP32_ANEG	0x1
7233 #define V_FW_PORT_CAP32_ANEG(x)	((x) << S_FW_PORT_CAP32_ANEG)
7234 #define G_FW_PORT_CAP32_ANEG(x) \
7235     (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
7236 
7237 #define S_FW_PORT_CAP32_FORCE_PAUSE	28
7238 #define M_FW_PORT_CAP32_FORCE_PAUSE	0x1
7239 #define V_FW_PORT_CAP32_FORCE_PAUSE(x)	((x) << S_FW_PORT_CAP32_FORCE_PAUSE)
7240 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \
7241     (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)
7242 
7243 enum fw_port_mdi32 {
7244 	FW_PORT_CAP32_MDI_UNCHANGED,
7245 	FW_PORT_CAP32_MDI_AUTO,
7246 	FW_PORT_CAP32_MDI_F_STRAIGHT,
7247 	FW_PORT_CAP32_MDI_F_CROSSOVER
7248 };
7249 
7250 #define S_FW_PORT_CAP32_MDI 21
7251 #define M_FW_PORT_CAP32_MDI 3
7252 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
7253 #define G_FW_PORT_CAP32_MDI(x) \
7254     (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
7255 
7256 #define S_FW_PORT_CAP32_FEC	23
7257 #define M_FW_PORT_CAP32_FEC	0x1f
7258 #define V_FW_PORT_CAP32_FEC(x)	((x) << S_FW_PORT_CAP32_FEC)
7259 #define G_FW_PORT_CAP32_FEC(x) \
7260     (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)
7261 
7262 /* macros to isolate various 32-bit Port Capabilities sub-fields */
7263 #define CAP32_SPEED(__cap32) \
7264 	(V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32)
7265 
7266 #define CAP32_FEC(__cap32) \
7267 	(V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)
7268 
7269 #define CAP32_FC(__cap32) \
7270 	(V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)
7271 
7272 enum fw_port_action {
7273 	FW_PORT_ACTION_L1_CFG		= 0x0001,
7274 	FW_PORT_ACTION_L2_CFG		= 0x0002,
7275 	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
7276 	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
7277 	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
7278 	FW_PORT_ACTION_DCB_READ_TRANS	= 0x0006,
7279 	FW_PORT_ACTION_DCB_READ_RECV	= 0x0007,
7280 	FW_PORT_ACTION_DCB_READ_DET	= 0x0008,
7281 	FW_PORT_ACTION_L1_CFG32		= 0x0009,
7282 	FW_PORT_ACTION_GET_PORT_INFO32	= 0x000a,
7283 	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
7284 	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
7285 	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
7286 	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
7287 	FW_PORT_ACTION_LPBK_SS_ASIC	= 0x0022,
7288 	FW_PORT_ACTION_LPBK_WS_ASIC	= 0x0023,
7289 	FW_PORT_ACTION_LPBK_WS_EXT_PHY	= 0x0025,
7290 	FW_PORT_ACTION_LPBK_SS_EXT	= 0x0026,
7291 	FW_PORT_ACTION_DIAGNOSTICS	= 0x0027,
7292 	FW_PORT_ACTION_LPBK_SS_EXT_PHY	= 0x0028,
7293 	FW_PORT_ACTION_PHY_RESET	= 0x0040,
7294 	FW_PORT_ACTION_PMA_RESET	= 0x0041,
7295 	FW_PORT_ACTION_PCS_RESET	= 0x0042,
7296 	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
7297 	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
7298 	FW_PORT_ACTION_AN_RESET		= 0x0045,
7299 
7300 };
7301 
7302 enum fw_port_l2cfg_ctlbf {
7303 	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
7304 	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
7305 	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
7306 	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
7307 	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
7308 	FW_PORT_L2_CTLBF_TXIPG	= 0x20,
7309 	FW_PORT_L2_CTLBF_MTU	= 0x40,
7310 	FW_PORT_L2_CTLBF_OVLAN_FILT	= 0x80,
7311 };
7312 
7313 enum fw_dcb_app_tlv_sf {
7314 	FW_DCB_APP_SF_ETHERTYPE,
7315 	FW_DCB_APP_SF_SOCKET_TCP,
7316 	FW_DCB_APP_SF_SOCKET_UDP,
7317 	FW_DCB_APP_SF_SOCKET_ALL,
7318 };
7319 
7320 enum fw_port_dcb_versions {
7321 	FW_PORT_DCB_VER_UNKNOWN,
7322 	FW_PORT_DCB_VER_CEE1D0,
7323 	FW_PORT_DCB_VER_CEE1D01,
7324 	FW_PORT_DCB_VER_IEEE,
7325 	FW_PORT_DCB_VER_AUTO=7
7326 };
7327 
7328 enum fw_port_dcb_cfg {
7329 	FW_PORT_DCB_CFG_PG	= 0x01,
7330 	FW_PORT_DCB_CFG_PFC	= 0x02,
7331 	FW_PORT_DCB_CFG_APPL	= 0x04
7332 };
7333 
7334 enum fw_port_dcb_cfg_rc {
7335 	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
7336 	FW_PORT_DCB_CFG_ERROR	= 0x1
7337 };
7338 
7339 enum fw_port_dcb_type {
7340 	FW_PORT_DCB_TYPE_PGID		= 0x00,
7341 	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
7342 	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
7343 	FW_PORT_DCB_TYPE_PFC		= 0x03,
7344 	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
7345 	FW_PORT_DCB_TYPE_CONTROL	= 0x05,
7346 };
7347 
7348 enum fw_port_dcb_feature_state {
7349 	FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
7350 	FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
7351 	FW_PORT_DCB_FEATURE_STATE_ERROR	= 0x2,
7352 	FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
7353 };
7354 
7355 enum fw_port_diag_ops {
7356 	FW_PORT_DIAGS_TEMP		= 0x00,
7357 	FW_PORT_DIAGS_TX_POWER		= 0x01,
7358 	FW_PORT_DIAGS_RX_POWER		= 0x02,
7359 	FW_PORT_DIAGS_TX_DIS		= 0x03,
7360 };
7361 
7362 struct fw_port_cmd {
7363 	__be32 op_to_portid;
7364 	__be32 action_to_len16;
7365 	union fw_port {
7366 		struct fw_port_l1cfg {
7367 			__be32 rcap;
7368 			__be32 r;
7369 		} l1cfg;
7370 		struct fw_port_l2cfg {
7371 			__u8   ctlbf;
7372 			__u8   ovlan3_to_ivlan0;
7373 			__be16 ivlantype;
7374 			__be16 txipg_force_pinfo;
7375 			__be16 mtu;
7376 			__be16 ovlan0mask;
7377 			__be16 ovlan0type;
7378 			__be16 ovlan1mask;
7379 			__be16 ovlan1type;
7380 			__be16 ovlan2mask;
7381 			__be16 ovlan2type;
7382 			__be16 ovlan3mask;
7383 			__be16 ovlan3type;
7384 		} l2cfg;
7385 		struct fw_port_info {
7386 			__be32 lstatus_to_modtype;
7387 			__be16 pcap;
7388 			__be16 acap;
7389 			__be16 mtu;
7390 			__u8   cbllen;
7391 			__u8   auxlinfo;
7392 			__u8   dcbxdis_pkd;
7393 			__u8   r8_lo;
7394 			__be16 lpacap;
7395 			__be64 r9;
7396 		} info;
7397 		struct fw_port_diags {
7398 			__u8   diagop;
7399 			__u8   r[3];
7400 			__be32 diagval;
7401 		} diags;
7402 		union fw_port_dcb {
7403 			struct fw_port_dcb_pgid {
7404 				__u8   type;
7405 				__u8   apply_pkd;
7406 				__u8   r10_lo[2];
7407 				__be32 pgid;
7408 				__be64 r11;
7409 			} pgid;
7410 			struct fw_port_dcb_pgrate {
7411 				__u8   type;
7412 				__u8   apply_pkd;
7413 				__u8   r10_lo[5];
7414 				__u8   num_tcs_supported;
7415 				__u8   pgrate[8];
7416 				__u8   tsa[8];
7417 			} pgrate;
7418 			struct fw_port_dcb_priorate {
7419 				__u8   type;
7420 				__u8   apply_pkd;
7421 				__u8   r10_lo[6];
7422 				__u8   strict_priorate[8];
7423 			} priorate;
7424 			struct fw_port_dcb_pfc {
7425 				__u8   type;
7426 				__u8   pfcen;
7427 				__u8   apply_pkd;
7428 				__u8   r10_lo[4];
7429 				__u8   max_pfc_tcs;
7430 				__be64 r11;
7431 			} pfc;
7432 			struct fw_port_app_priority {
7433 				__u8   type;
7434 				__u8   apply_pkd;
7435 				__u8   r10_lo;
7436 				__u8   idx;
7437 				__u8   user_prio_map;
7438 				__u8   sel_field;
7439 				__be16 protocolid;
7440 				__be64 r12;
7441 			} app_priority;
7442 			struct fw_port_dcb_control {
7443 				__u8   type;
7444 				__u8   all_syncd_pkd;
7445 				__be16 dcb_version_to_app_state;
7446 				__be32 r11;
7447 				__be64 r12;
7448 			} control;
7449 		} dcb;
7450 		struct fw_port_l1cfg32 {
7451 			__be32 rcap32;
7452 			__be32 r;
7453 		} l1cfg32;
7454 		struct fw_port_info32 {
7455 			__be32 lstatus32_to_cbllen32;
7456 			__be32 auxlinfo32_mtu32;
7457 			__be32 linkattr32;
7458 			__be32 pcaps32;
7459 			__be32 acaps32;
7460 			__be32 lpacaps32;
7461 		} info32;
7462 	} u;
7463 };
7464 
7465 #define S_FW_PORT_CMD_READ		22
7466 #define M_FW_PORT_CMD_READ		0x1
7467 #define V_FW_PORT_CMD_READ(x)		((x) << S_FW_PORT_CMD_READ)
7468 #define G_FW_PORT_CMD_READ(x)		\
7469     (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
7470 #define F_FW_PORT_CMD_READ		V_FW_PORT_CMD_READ(1U)
7471 
7472 #define S_FW_PORT_CMD_PORTID		0
7473 #define M_FW_PORT_CMD_PORTID		0xf
7474 #define V_FW_PORT_CMD_PORTID(x)		((x) << S_FW_PORT_CMD_PORTID)
7475 #define G_FW_PORT_CMD_PORTID(x)		\
7476     (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
7477 
7478 #define S_FW_PORT_CMD_ACTION		16
7479 #define M_FW_PORT_CMD_ACTION		0xffff
7480 #define V_FW_PORT_CMD_ACTION(x)		((x) << S_FW_PORT_CMD_ACTION)
7481 #define G_FW_PORT_CMD_ACTION(x)		\
7482     (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
7483 
7484 #define S_FW_PORT_CMD_OVLAN3		7
7485 #define M_FW_PORT_CMD_OVLAN3		0x1
7486 #define V_FW_PORT_CMD_OVLAN3(x)		((x) << S_FW_PORT_CMD_OVLAN3)
7487 #define G_FW_PORT_CMD_OVLAN3(x)		\
7488     (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
7489 #define F_FW_PORT_CMD_OVLAN3		V_FW_PORT_CMD_OVLAN3(1U)
7490 
7491 #define S_FW_PORT_CMD_OVLAN2		6
7492 #define M_FW_PORT_CMD_OVLAN2		0x1
7493 #define V_FW_PORT_CMD_OVLAN2(x)		((x) << S_FW_PORT_CMD_OVLAN2)
7494 #define G_FW_PORT_CMD_OVLAN2(x)		\
7495     (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
7496 #define F_FW_PORT_CMD_OVLAN2		V_FW_PORT_CMD_OVLAN2(1U)
7497 
7498 #define S_FW_PORT_CMD_OVLAN1		5
7499 #define M_FW_PORT_CMD_OVLAN1		0x1
7500 #define V_FW_PORT_CMD_OVLAN1(x)		((x) << S_FW_PORT_CMD_OVLAN1)
7501 #define G_FW_PORT_CMD_OVLAN1(x)		\
7502     (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
7503 #define F_FW_PORT_CMD_OVLAN1		V_FW_PORT_CMD_OVLAN1(1U)
7504 
7505 #define S_FW_PORT_CMD_OVLAN0		4
7506 #define M_FW_PORT_CMD_OVLAN0		0x1
7507 #define V_FW_PORT_CMD_OVLAN0(x)		((x) << S_FW_PORT_CMD_OVLAN0)
7508 #define G_FW_PORT_CMD_OVLAN0(x)		\
7509     (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
7510 #define F_FW_PORT_CMD_OVLAN0		V_FW_PORT_CMD_OVLAN0(1U)
7511 
7512 #define S_FW_PORT_CMD_IVLAN0		3
7513 #define M_FW_PORT_CMD_IVLAN0		0x1
7514 #define V_FW_PORT_CMD_IVLAN0(x)		((x) << S_FW_PORT_CMD_IVLAN0)
7515 #define G_FW_PORT_CMD_IVLAN0(x)		\
7516     (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
7517 #define F_FW_PORT_CMD_IVLAN0		V_FW_PORT_CMD_IVLAN0(1U)
7518 
7519 #define S_FW_PORT_CMD_OVLAN_FILT	2
7520 #define M_FW_PORT_CMD_OVLAN_FILT	0x1
7521 #define V_FW_PORT_CMD_OVLAN_FILT(x)	((x) << S_FW_PORT_CMD_OVLAN_FILT)
7522 #define G_FW_PORT_CMD_OVLAN_FILT(x)	\
7523     (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)
7524 #define F_FW_PORT_CMD_OVLAN_FILT	V_FW_PORT_CMD_OVLAN_FILT(1U)
7525 
7526 #define S_FW_PORT_CMD_TXIPG		3
7527 #define M_FW_PORT_CMD_TXIPG		0x1fff
7528 #define V_FW_PORT_CMD_TXIPG(x)		((x) << S_FW_PORT_CMD_TXIPG)
7529 #define G_FW_PORT_CMD_TXIPG(x)		\
7530     (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
7531 
7532 #define S_FW_PORT_CMD_FORCE_PINFO	0
7533 #define M_FW_PORT_CMD_FORCE_PINFO	0x1
7534 #define V_FW_PORT_CMD_FORCE_PINFO(x)	((x) << S_FW_PORT_CMD_FORCE_PINFO)
7535 #define G_FW_PORT_CMD_FORCE_PINFO(x)	\
7536     (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
7537 #define F_FW_PORT_CMD_FORCE_PINFO	V_FW_PORT_CMD_FORCE_PINFO(1U)
7538 
7539 #define S_FW_PORT_CMD_LSTATUS		31
7540 #define M_FW_PORT_CMD_LSTATUS		0x1
7541 #define V_FW_PORT_CMD_LSTATUS(x)	((x) << S_FW_PORT_CMD_LSTATUS)
7542 #define G_FW_PORT_CMD_LSTATUS(x)	\
7543     (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
7544 #define F_FW_PORT_CMD_LSTATUS		V_FW_PORT_CMD_LSTATUS(1U)
7545 
7546 #define S_FW_PORT_CMD_LSPEED		24
7547 #define M_FW_PORT_CMD_LSPEED		0x3f
7548 #define V_FW_PORT_CMD_LSPEED(x)		((x) << S_FW_PORT_CMD_LSPEED)
7549 #define G_FW_PORT_CMD_LSPEED(x)		\
7550     (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
7551 
7552 #define S_FW_PORT_CMD_TXPAUSE		23
7553 #define M_FW_PORT_CMD_TXPAUSE		0x1
7554 #define V_FW_PORT_CMD_TXPAUSE(x)	((x) << S_FW_PORT_CMD_TXPAUSE)
7555 #define G_FW_PORT_CMD_TXPAUSE(x)	\
7556     (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
7557 #define F_FW_PORT_CMD_TXPAUSE		V_FW_PORT_CMD_TXPAUSE(1U)
7558 
7559 #define S_FW_PORT_CMD_RXPAUSE		22
7560 #define M_FW_PORT_CMD_RXPAUSE		0x1
7561 #define V_FW_PORT_CMD_RXPAUSE(x)	((x) << S_FW_PORT_CMD_RXPAUSE)
7562 #define G_FW_PORT_CMD_RXPAUSE(x)	\
7563     (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
7564 #define F_FW_PORT_CMD_RXPAUSE		V_FW_PORT_CMD_RXPAUSE(1U)
7565 
7566 #define S_FW_PORT_CMD_MDIOCAP		21
7567 #define M_FW_PORT_CMD_MDIOCAP		0x1
7568 #define V_FW_PORT_CMD_MDIOCAP(x)	((x) << S_FW_PORT_CMD_MDIOCAP)
7569 #define G_FW_PORT_CMD_MDIOCAP(x)	\
7570     (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
7571 #define F_FW_PORT_CMD_MDIOCAP		V_FW_PORT_CMD_MDIOCAP(1U)
7572 
7573 #define S_FW_PORT_CMD_MDIOADDR		16
7574 #define M_FW_PORT_CMD_MDIOADDR		0x1f
7575 #define V_FW_PORT_CMD_MDIOADDR(x)	((x) << S_FW_PORT_CMD_MDIOADDR)
7576 #define G_FW_PORT_CMD_MDIOADDR(x)	\
7577     (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
7578 
7579 #define S_FW_PORT_CMD_LPTXPAUSE		15
7580 #define M_FW_PORT_CMD_LPTXPAUSE		0x1
7581 #define V_FW_PORT_CMD_LPTXPAUSE(x)	((x) << S_FW_PORT_CMD_LPTXPAUSE)
7582 #define G_FW_PORT_CMD_LPTXPAUSE(x)	\
7583     (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
7584 #define F_FW_PORT_CMD_LPTXPAUSE		V_FW_PORT_CMD_LPTXPAUSE(1U)
7585 
7586 #define S_FW_PORT_CMD_LPRXPAUSE		14
7587 #define M_FW_PORT_CMD_LPRXPAUSE		0x1
7588 #define V_FW_PORT_CMD_LPRXPAUSE(x)	((x) << S_FW_PORT_CMD_LPRXPAUSE)
7589 #define G_FW_PORT_CMD_LPRXPAUSE(x)	\
7590     (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
7591 #define F_FW_PORT_CMD_LPRXPAUSE		V_FW_PORT_CMD_LPRXPAUSE(1U)
7592 
7593 #define S_FW_PORT_CMD_PTYPE		8
7594 #define M_FW_PORT_CMD_PTYPE		0x1f
7595 #define V_FW_PORT_CMD_PTYPE(x)		((x) << S_FW_PORT_CMD_PTYPE)
7596 #define G_FW_PORT_CMD_PTYPE(x)		\
7597     (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
7598 
7599 #define S_FW_PORT_CMD_LINKDNRC		5
7600 #define M_FW_PORT_CMD_LINKDNRC		0x7
7601 #define V_FW_PORT_CMD_LINKDNRC(x)	((x) << S_FW_PORT_CMD_LINKDNRC)
7602 #define G_FW_PORT_CMD_LINKDNRC(x)	\
7603     (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
7604 
7605 #define S_FW_PORT_CMD_MODTYPE		0
7606 #define M_FW_PORT_CMD_MODTYPE		0x1f
7607 #define V_FW_PORT_CMD_MODTYPE(x)	((x) << S_FW_PORT_CMD_MODTYPE)
7608 #define G_FW_PORT_CMD_MODTYPE(x)	\
7609     (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
7610 
7611 #define S_FW_PORT_AUXLINFO_KX4	2
7612 #define M_FW_PORT_AUXLINFO_KX4	0x1
7613 #define V_FW_PORT_AUXLINFO_KX4(x) \
7614     ((x) << S_FW_PORT_AUXLINFO_KX4)
7615 #define G_FW_PORT_AUXLINFO_KX4(x) \
7616     (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
7617 #define F_FW_PORT_AUXLINFO_KX4	V_FW_PORT_AUXLINFO_KX4(1U)
7618 
7619 #define S_FW_PORT_AUXLINFO_KR	1
7620 #define M_FW_PORT_AUXLINFO_KR	0x1
7621 #define V_FW_PORT_AUXLINFO_KR(x) \
7622     ((x) << S_FW_PORT_AUXLINFO_KR)
7623 #define G_FW_PORT_AUXLINFO_KR(x) \
7624     (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
7625 #define F_FW_PORT_AUXLINFO_KR	V_FW_PORT_AUXLINFO_KR(1U)
7626 
7627 #define S_FW_PORT_CMD_DCBXDIS		7
7628 #define M_FW_PORT_CMD_DCBXDIS		0x1
7629 #define V_FW_PORT_CMD_DCBXDIS(x)	((x) << S_FW_PORT_CMD_DCBXDIS)
7630 #define G_FW_PORT_CMD_DCBXDIS(x)	\
7631     (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
7632 #define F_FW_PORT_CMD_DCBXDIS		V_FW_PORT_CMD_DCBXDIS(1U)
7633 
7634 #define S_FW_PORT_CMD_APPLY		7
7635 #define M_FW_PORT_CMD_APPLY		0x1
7636 #define V_FW_PORT_CMD_APPLY(x)		((x) << S_FW_PORT_CMD_APPLY)
7637 #define G_FW_PORT_CMD_APPLY(x)		\
7638     (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
7639 #define F_FW_PORT_CMD_APPLY		V_FW_PORT_CMD_APPLY(1U)
7640 
7641 #define S_FW_PORT_CMD_ALL_SYNCD		7
7642 #define M_FW_PORT_CMD_ALL_SYNCD		0x1
7643 #define V_FW_PORT_CMD_ALL_SYNCD(x)	((x) << S_FW_PORT_CMD_ALL_SYNCD)
7644 #define G_FW_PORT_CMD_ALL_SYNCD(x)	\
7645     (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
7646 #define F_FW_PORT_CMD_ALL_SYNCD		V_FW_PORT_CMD_ALL_SYNCD(1U)
7647 
7648 #define S_FW_PORT_CMD_DCB_VERSION	12
7649 #define M_FW_PORT_CMD_DCB_VERSION	0x7
7650 #define V_FW_PORT_CMD_DCB_VERSION(x)	((x) << S_FW_PORT_CMD_DCB_VERSION)
7651 #define G_FW_PORT_CMD_DCB_VERSION(x)	\
7652     (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
7653 
7654 #define S_FW_PORT_CMD_PFC_STATE		8
7655 #define M_FW_PORT_CMD_PFC_STATE		0xf
7656 #define V_FW_PORT_CMD_PFC_STATE(x)	((x) << S_FW_PORT_CMD_PFC_STATE)
7657 #define G_FW_PORT_CMD_PFC_STATE(x)	\
7658     (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
7659 
7660 #define S_FW_PORT_CMD_ETS_STATE		4
7661 #define M_FW_PORT_CMD_ETS_STATE		0xf
7662 #define V_FW_PORT_CMD_ETS_STATE(x)	((x) << S_FW_PORT_CMD_ETS_STATE)
7663 #define G_FW_PORT_CMD_ETS_STATE(x)	\
7664     (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
7665 
7666 #define S_FW_PORT_CMD_APP_STATE		0
7667 #define M_FW_PORT_CMD_APP_STATE		0xf
7668 #define V_FW_PORT_CMD_APP_STATE(x)	((x) << S_FW_PORT_CMD_APP_STATE)
7669 #define G_FW_PORT_CMD_APP_STATE(x)	\
7670     (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
7671 
7672 #define S_FW_PORT_CMD_LSTATUS32		31
7673 #define M_FW_PORT_CMD_LSTATUS32		0x1
7674 #define V_FW_PORT_CMD_LSTATUS32(x)	((x) << S_FW_PORT_CMD_LSTATUS32)
7675 #define G_FW_PORT_CMD_LSTATUS32(x)	\
7676     (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)
7677 #define F_FW_PORT_CMD_LSTATUS32	V_FW_PORT_CMD_LSTATUS32(1U)
7678 
7679 #define S_FW_PORT_CMD_LINKDNRC32	28
7680 #define M_FW_PORT_CMD_LINKDNRC32	0x7
7681 #define V_FW_PORT_CMD_LINKDNRC32(x)	((x) << S_FW_PORT_CMD_LINKDNRC32)
7682 #define G_FW_PORT_CMD_LINKDNRC32(x)	\
7683     (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
7684 
7685 #define S_FW_PORT_CMD_DCBXDIS32		27
7686 #define M_FW_PORT_CMD_DCBXDIS32		0x1
7687 #define V_FW_PORT_CMD_DCBXDIS32(x)	((x) << S_FW_PORT_CMD_DCBXDIS32)
7688 #define G_FW_PORT_CMD_DCBXDIS32(x)	\
7689     (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)
7690 #define F_FW_PORT_CMD_DCBXDIS32	V_FW_PORT_CMD_DCBXDIS32(1U)
7691 
7692 #define S_FW_PORT_CMD_MDIOCAP32		26
7693 #define M_FW_PORT_CMD_MDIOCAP32		0x1
7694 #define V_FW_PORT_CMD_MDIOCAP32(x)	((x) << S_FW_PORT_CMD_MDIOCAP32)
7695 #define G_FW_PORT_CMD_MDIOCAP32(x)	\
7696     (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)
7697 #define F_FW_PORT_CMD_MDIOCAP32	V_FW_PORT_CMD_MDIOCAP32(1U)
7698 
7699 #define S_FW_PORT_CMD_MDIOADDR32	21
7700 #define M_FW_PORT_CMD_MDIOADDR32	0x1f
7701 #define V_FW_PORT_CMD_MDIOADDR32(x)	((x) << S_FW_PORT_CMD_MDIOADDR32)
7702 #define G_FW_PORT_CMD_MDIOADDR32(x)	\
7703     (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
7704 
7705 #define S_FW_PORT_CMD_PORTTYPE32	13
7706 #define M_FW_PORT_CMD_PORTTYPE32	0xff
7707 #define V_FW_PORT_CMD_PORTTYPE32(x)	((x) << S_FW_PORT_CMD_PORTTYPE32)
7708 #define G_FW_PORT_CMD_PORTTYPE32(x)	\
7709     (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
7710 
7711 #define S_FW_PORT_CMD_MODTYPE32		8
7712 #define M_FW_PORT_CMD_MODTYPE32		0x1f
7713 #define V_FW_PORT_CMD_MODTYPE32(x)	((x) << S_FW_PORT_CMD_MODTYPE32)
7714 #define G_FW_PORT_CMD_MODTYPE32(x)	\
7715     (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
7716 
7717 #define S_FW_PORT_CMD_CBLLEN32		0
7718 #define M_FW_PORT_CMD_CBLLEN32		0xff
7719 #define V_FW_PORT_CMD_CBLLEN32(x)	((x) << S_FW_PORT_CMD_CBLLEN32)
7720 #define G_FW_PORT_CMD_CBLLEN32(x)	\
7721     (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)
7722 
7723 #define S_FW_PORT_CMD_AUXLINFO32	24
7724 #define M_FW_PORT_CMD_AUXLINFO32	0xff
7725 #define V_FW_PORT_CMD_AUXLINFO32(x)	((x) << S_FW_PORT_CMD_AUXLINFO32)
7726 #define G_FW_PORT_CMD_AUXLINFO32(x)	\
7727     (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)
7728 
7729 #define S_FW_PORT_AUXLINFO32_KX4	2
7730 #define M_FW_PORT_AUXLINFO32_KX4	0x1
7731 #define V_FW_PORT_AUXLINFO32_KX4(x) \
7732     ((x) << S_FW_PORT_AUXLINFO32_KX4)
7733 #define G_FW_PORT_AUXLINFO32_KX4(x) \
7734     (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)
7735 #define F_FW_PORT_AUXLINFO32_KX4	V_FW_PORT_AUXLINFO32_KX4(1U)
7736 
7737 #define S_FW_PORT_AUXLINFO32_KR	1
7738 #define M_FW_PORT_AUXLINFO32_KR	0x1
7739 #define V_FW_PORT_AUXLINFO32_KR(x) \
7740     ((x) << S_FW_PORT_AUXLINFO32_KR)
7741 #define G_FW_PORT_AUXLINFO32_KR(x) \
7742     (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)
7743 #define F_FW_PORT_AUXLINFO32_KR	V_FW_PORT_AUXLINFO32_KR(1U)
7744 
7745 #define S_FW_PORT_CMD_MTU32	0
7746 #define M_FW_PORT_CMD_MTU32	0xffff
7747 #define V_FW_PORT_CMD_MTU32(x)	((x) << S_FW_PORT_CMD_MTU32)
7748 #define G_FW_PORT_CMD_MTU32(x)	\
7749     (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)
7750 
7751 /*
7752  *	These are configured into the VPD and hence tools that generate
7753  *	VPD may use this enumeration.
7754  *	extPHY	#lanes	T4_I2C	extI2C	BP_Eq	BP_ANEG	Speed
7755  *
7756  *	REMEMBER:
7757  *	    Update the Common Code t4_hw.c:t4_get_port_type_description()
7758  *	    with any new Firmware Port Technology Types!
7759  */
7760 enum fw_port_type {
7761 	FW_PORT_TYPE_FIBER_XFI	=  0,	/* Y, 1, N, Y, N, N, 10G */
7762 	FW_PORT_TYPE_FIBER_XAUI	=  1,	/* Y, 4, N, Y, N, N, 10G */
7763 	FW_PORT_TYPE_BT_SGMII	=  2,	/* Y, 1, No, No, No, No, 1G/100M */
7764 	FW_PORT_TYPE_BT_XFI	=  3,	/* Y, 1, No, No, No, No, 10G/1G/100M */
7765 	FW_PORT_TYPE_BT_XAUI	=  4,	/* Y, 4, No, No, No, No, 10G/1G/100M */
7766 	FW_PORT_TYPE_KX4	=  5,	/* No, 4, No, No, Yes, Yes, 10G */
7767 	FW_PORT_TYPE_CX4	=  6,	/* No, 4, No, No, No, No, 10G */
7768 	FW_PORT_TYPE_KX		=  7,	/* No, 1, No, No, Yes, No, 1G */
7769 	FW_PORT_TYPE_KR		=  8,	/* No, 1, No, No, Yes, Yes, 10G */
7770 	FW_PORT_TYPE_SFP	=  9,	/* No, 1, Yes, No, No, No, 10G */
7771 	FW_PORT_TYPE_BP_AP	= 10,	/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
7772 	FW_PORT_TYPE_BP4_AP	= 11,	/* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
7773 	FW_PORT_TYPE_QSFP_10G	= 12,	/* No, 1, Yes, No, No, No, 10G */
7774 	FW_PORT_TYPE_QSA	= 13,	/* No, 1, Yes, No, No, No, 10G */
7775 	FW_PORT_TYPE_QSFP	= 14,	/* No, 4, Yes, No, No, No, 40G */
7776 	FW_PORT_TYPE_BP40_BA	= 15,	/* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
7777 	FW_PORT_TYPE_KR4_100G	= 16,	/* No, 4, 100G/40G/25G, Backplane */
7778 	FW_PORT_TYPE_CR4_QSFP	= 17,	/* No, 4, 100G/40G/25G */
7779 	FW_PORT_TYPE_CR_QSFP	= 18,	/* No, 1, 25G Spider cable */
7780 	FW_PORT_TYPE_CR2_QSFP	= 19,	/* No, 2, 50G */
7781 	FW_PORT_TYPE_SFP28	= 20,	/* No, 1, 25G/10G/1G */
7782 	FW_PORT_TYPE_KR_SFP28	= 21,	/* No, 1, 25G/10G/1G using Backplane */
7783 	FW_PORT_TYPE_KR_XLAUI	= 22,	/* No, 4, 40G/10G/1G, No AN*/
7784 	FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
7785 };
7786 
7787 /* These are read from module's EEPROM and determined once the
7788    module is inserted. */
7789 enum fw_port_module_type {
7790 	FW_PORT_MOD_TYPE_NA		= 0x0,
7791 	FW_PORT_MOD_TYPE_LR		= 0x1,
7792 	FW_PORT_MOD_TYPE_SR		= 0x2,
7793 	FW_PORT_MOD_TYPE_ER		= 0x3,
7794 	FW_PORT_MOD_TYPE_TWINAX_PASSIVE	= 0x4,
7795 	FW_PORT_MOD_TYPE_TWINAX_ACTIVE	= 0x5,
7796 	FW_PORT_MOD_TYPE_LRM		= 0x6,
7797 	FW_PORT_MOD_TYPE_ERROR		= M_FW_PORT_CMD_MODTYPE - 3,
7798 	FW_PORT_MOD_TYPE_UNKNOWN	= M_FW_PORT_CMD_MODTYPE - 2,
7799 	FW_PORT_MOD_TYPE_NOTSUPPORTED	= M_FW_PORT_CMD_MODTYPE - 1,
7800 	FW_PORT_MOD_TYPE_NONE		= M_FW_PORT_CMD_MODTYPE
7801 };
7802 
7803 /* used by FW and tools may use this to generate VPD */
7804 enum fw_port_mod_sub_type {
7805 	FW_PORT_MOD_SUB_TYPE_NA,
7806 	FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
7807 	FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
7808 	FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
7809 	FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
7810 	FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
7811 	FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
7812 	FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,
7813 	FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
7814 
7815 	/*
7816 	 * The following will never been in the VPD.  They are TWINAX cable
7817 	 * lengths decoded from SFP+ module i2c PROMs.  These should almost
7818 	 * certainly go somewhere else ...
7819 	 */
7820 	FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
7821 	FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
7822 	FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
7823 	FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
7824 };
7825 
7826 /* link down reason codes (3b) */
7827 enum fw_port_link_dn_rc {
7828 	FW_PORT_LINK_DN_RC_NONE,
7829 	FW_PORT_LINK_DN_RC_REMFLT,	/* Remote fault detected */
7830 	FW_PORT_LINK_DN_ANEG_F,		/* Auto-negotiation fault */
7831 	FW_PORT_LINK_DN_RESERVED3,
7832 	FW_PORT_LINK_DN_OVERHEAT,	/* Port overheated */
7833 	FW_PORT_LINK_DN_UNKNOWN,	/* Unable to determine reason */
7834 	FW_PORT_LINK_DN_RX_LOS,		/* No RX signal detected */
7835 	FW_PORT_LINK_DN_RESERVED7
7836 };
7837 enum fw_port_stats_tx_index {
7838 	FW_STAT_TX_PORT_BYTES_IX = 0,
7839 	FW_STAT_TX_PORT_FRAMES_IX,
7840 	FW_STAT_TX_PORT_BCAST_IX,
7841 	FW_STAT_TX_PORT_MCAST_IX,
7842 	FW_STAT_TX_PORT_UCAST_IX,
7843 	FW_STAT_TX_PORT_ERROR_IX,
7844 	FW_STAT_TX_PORT_64B_IX,
7845 	FW_STAT_TX_PORT_65B_127B_IX,
7846 	FW_STAT_TX_PORT_128B_255B_IX,
7847 	FW_STAT_TX_PORT_256B_511B_IX,
7848 	FW_STAT_TX_PORT_512B_1023B_IX,
7849 	FW_STAT_TX_PORT_1024B_1518B_IX,
7850 	FW_STAT_TX_PORT_1519B_MAX_IX,
7851 	FW_STAT_TX_PORT_DROP_IX,
7852 	FW_STAT_TX_PORT_PAUSE_IX,
7853 	FW_STAT_TX_PORT_PPP0_IX,
7854 	FW_STAT_TX_PORT_PPP1_IX,
7855 	FW_STAT_TX_PORT_PPP2_IX,
7856 	FW_STAT_TX_PORT_PPP3_IX,
7857 	FW_STAT_TX_PORT_PPP4_IX,
7858 	FW_STAT_TX_PORT_PPP5_IX,
7859 	FW_STAT_TX_PORT_PPP6_IX,
7860 	FW_STAT_TX_PORT_PPP7_IX,
7861 	FW_NUM_PORT_TX_STATS
7862 };
7863 
7864 enum fw_port_stat_rx_index {
7865 	FW_STAT_RX_PORT_BYTES_IX = 0,
7866 	FW_STAT_RX_PORT_FRAMES_IX,
7867 	FW_STAT_RX_PORT_BCAST_IX,
7868 	FW_STAT_RX_PORT_MCAST_IX,
7869 	FW_STAT_RX_PORT_UCAST_IX,
7870 	FW_STAT_RX_PORT_MTU_ERROR_IX,
7871 	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
7872 	FW_STAT_RX_PORT_CRC_ERROR_IX,
7873 	FW_STAT_RX_PORT_LEN_ERROR_IX,
7874 	FW_STAT_RX_PORT_SYM_ERROR_IX,
7875 	FW_STAT_RX_PORT_64B_IX,
7876 	FW_STAT_RX_PORT_65B_127B_IX,
7877 	FW_STAT_RX_PORT_128B_255B_IX,
7878 	FW_STAT_RX_PORT_256B_511B_IX,
7879 	FW_STAT_RX_PORT_512B_1023B_IX,
7880 	FW_STAT_RX_PORT_1024B_1518B_IX,
7881 	FW_STAT_RX_PORT_1519B_MAX_IX,
7882 	FW_STAT_RX_PORT_PAUSE_IX,
7883 	FW_STAT_RX_PORT_PPP0_IX,
7884 	FW_STAT_RX_PORT_PPP1_IX,
7885 	FW_STAT_RX_PORT_PPP2_IX,
7886 	FW_STAT_RX_PORT_PPP3_IX,
7887 	FW_STAT_RX_PORT_PPP4_IX,
7888 	FW_STAT_RX_PORT_PPP5_IX,
7889 	FW_STAT_RX_PORT_PPP6_IX,
7890 	FW_STAT_RX_PORT_PPP7_IX,
7891 	FW_STAT_RX_PORT_LESS_64B_IX,
7892         FW_STAT_RX_PORT_MAC_ERROR_IX,
7893         FW_NUM_PORT_RX_STATS
7894 };
7895 /* port stats */
7896 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \
7897                                  FW_NUM_PORT_RX_STATS)
7898 
7899 
7900 struct fw_port_stats_cmd {
7901 	__be32 op_to_portid;
7902 	__be32 retval_len16;
7903 	union fw_port_stats {
7904 		struct fw_port_stats_ctl {
7905 			__u8   nstats_bg_bm;
7906 			__u8   tx_ix;
7907 			__be16 r6;
7908 			__be32 r7;
7909 			__be64 stat0;
7910 			__be64 stat1;
7911 			__be64 stat2;
7912 			__be64 stat3;
7913 			__be64 stat4;
7914 			__be64 stat5;
7915 		} ctl;
7916 		struct fw_port_stats_all {
7917 			__be64 tx_bytes;
7918 			__be64 tx_frames;
7919 			__be64 tx_bcast;
7920 			__be64 tx_mcast;
7921 			__be64 tx_ucast;
7922 			__be64 tx_error;
7923 			__be64 tx_64b;
7924 			__be64 tx_65b_127b;
7925 			__be64 tx_128b_255b;
7926 			__be64 tx_256b_511b;
7927 			__be64 tx_512b_1023b;
7928 			__be64 tx_1024b_1518b;
7929 			__be64 tx_1519b_max;
7930 			__be64 tx_drop;
7931 			__be64 tx_pause;
7932 			__be64 tx_ppp0;
7933 			__be64 tx_ppp1;
7934 			__be64 tx_ppp2;
7935 			__be64 tx_ppp3;
7936 			__be64 tx_ppp4;
7937 			__be64 tx_ppp5;
7938 			__be64 tx_ppp6;
7939 			__be64 tx_ppp7;
7940 			__be64 rx_bytes;
7941 			__be64 rx_frames;
7942 			__be64 rx_bcast;
7943 			__be64 rx_mcast;
7944 			__be64 rx_ucast;
7945 			__be64 rx_mtu_error;
7946 			__be64 rx_mtu_crc_error;
7947 			__be64 rx_crc_error;
7948 			__be64 rx_len_error;
7949 			__be64 rx_sym_error;
7950 			__be64 rx_64b;
7951 			__be64 rx_65b_127b;
7952 			__be64 rx_128b_255b;
7953 			__be64 rx_256b_511b;
7954 			__be64 rx_512b_1023b;
7955 			__be64 rx_1024b_1518b;
7956 			__be64 rx_1519b_max;
7957 			__be64 rx_pause;
7958 			__be64 rx_ppp0;
7959 			__be64 rx_ppp1;
7960 			__be64 rx_ppp2;
7961 			__be64 rx_ppp3;
7962 			__be64 rx_ppp4;
7963 			__be64 rx_ppp5;
7964 			__be64 rx_ppp6;
7965 			__be64 rx_ppp7;
7966 			__be64 rx_less_64b;
7967 			__be64 rx_bg_drop;
7968 			__be64 rx_bg_trunc;
7969 		} all;
7970 	} u;
7971 };
7972 
7973 #define S_FW_PORT_STATS_CMD_NSTATS	4
7974 #define M_FW_PORT_STATS_CMD_NSTATS	0x7
7975 #define V_FW_PORT_STATS_CMD_NSTATS(x)	((x) << S_FW_PORT_STATS_CMD_NSTATS)
7976 #define G_FW_PORT_STATS_CMD_NSTATS(x)	\
7977     (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
7978 
7979 #define S_FW_PORT_STATS_CMD_BG_BM	0
7980 #define M_FW_PORT_STATS_CMD_BG_BM	0x3
7981 #define V_FW_PORT_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_STATS_CMD_BG_BM)
7982 #define G_FW_PORT_STATS_CMD_BG_BM(x)	\
7983     (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
7984 
7985 #define S_FW_PORT_STATS_CMD_TX		7
7986 #define M_FW_PORT_STATS_CMD_TX		0x1
7987 #define V_FW_PORT_STATS_CMD_TX(x)	((x) << S_FW_PORT_STATS_CMD_TX)
7988 #define G_FW_PORT_STATS_CMD_TX(x)	\
7989     (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
7990 #define F_FW_PORT_STATS_CMD_TX		V_FW_PORT_STATS_CMD_TX(1U)
7991 
7992 #define S_FW_PORT_STATS_CMD_IX		0
7993 #define M_FW_PORT_STATS_CMD_IX		0x3f
7994 #define V_FW_PORT_STATS_CMD_IX(x)	((x) << S_FW_PORT_STATS_CMD_IX)
7995 #define G_FW_PORT_STATS_CMD_IX(x)	\
7996     (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
7997 
7998 /* port loopback stats */
7999 #define FW_NUM_LB_STATS 14
8000 enum fw_port_lb_stats_index {
8001 	FW_STAT_LB_PORT_BYTES_IX,
8002 	FW_STAT_LB_PORT_FRAMES_IX,
8003 	FW_STAT_LB_PORT_BCAST_IX,
8004 	FW_STAT_LB_PORT_MCAST_IX,
8005 	FW_STAT_LB_PORT_UCAST_IX,
8006 	FW_STAT_LB_PORT_ERROR_IX,
8007 	FW_STAT_LB_PORT_64B_IX,
8008 	FW_STAT_LB_PORT_65B_127B_IX,
8009 	FW_STAT_LB_PORT_128B_255B_IX,
8010 	FW_STAT_LB_PORT_256B_511B_IX,
8011 	FW_STAT_LB_PORT_512B_1023B_IX,
8012 	FW_STAT_LB_PORT_1024B_1518B_IX,
8013 	FW_STAT_LB_PORT_1519B_MAX_IX,
8014 	FW_STAT_LB_PORT_DROP_FRAMES_IX
8015 };
8016 
8017 struct fw_port_lb_stats_cmd {
8018 	__be32 op_to_lbport;
8019 	__be32 retval_len16;
8020 	union fw_port_lb_stats {
8021 		struct fw_port_lb_stats_ctl {
8022 			__u8   nstats_bg_bm;
8023 			__u8   ix_pkd;
8024 			__be16 r6;
8025 			__be32 r7;
8026 			__be64 stat0;
8027 			__be64 stat1;
8028 			__be64 stat2;
8029 			__be64 stat3;
8030 			__be64 stat4;
8031 			__be64 stat5;
8032 		} ctl;
8033 		struct fw_port_lb_stats_all {
8034 			__be64 tx_bytes;
8035 			__be64 tx_frames;
8036 			__be64 tx_bcast;
8037 			__be64 tx_mcast;
8038 			__be64 tx_ucast;
8039 			__be64 tx_error;
8040 			__be64 tx_64b;
8041 			__be64 tx_65b_127b;
8042 			__be64 tx_128b_255b;
8043 			__be64 tx_256b_511b;
8044 			__be64 tx_512b_1023b;
8045 			__be64 tx_1024b_1518b;
8046 			__be64 tx_1519b_max;
8047 			__be64 rx_lb_drop;
8048 			__be64 rx_lb_trunc;
8049 		} all;
8050 	} u;
8051 };
8052 
8053 #define S_FW_PORT_LB_STATS_CMD_LBPORT	0
8054 #define M_FW_PORT_LB_STATS_CMD_LBPORT	0xf
8055 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
8056     ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
8057 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
8058     (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
8059 
8060 #define S_FW_PORT_LB_STATS_CMD_NSTATS	4
8061 #define M_FW_PORT_LB_STATS_CMD_NSTATS	0x7
8062 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
8063     ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
8064 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
8065     (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
8066 
8067 #define S_FW_PORT_LB_STATS_CMD_BG_BM	0
8068 #define M_FW_PORT_LB_STATS_CMD_BG_BM	0x3
8069 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
8070 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x)	\
8071     (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
8072 
8073 #define S_FW_PORT_LB_STATS_CMD_IX	0
8074 #define M_FW_PORT_LB_STATS_CMD_IX	0xf
8075 #define V_FW_PORT_LB_STATS_CMD_IX(x)	((x) << S_FW_PORT_LB_STATS_CMD_IX)
8076 #define G_FW_PORT_LB_STATS_CMD_IX(x)	\
8077     (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
8078 
8079 /* Trace related defines */
8080 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
8081 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE  2560
8082 
8083 struct fw_port_trace_cmd {
8084 	__be32 op_to_portid;
8085 	__be32 retval_len16;
8086 	__be16 traceen_to_pciech;
8087 	__be16 qnum;
8088 	__be32 r5;
8089 };
8090 
8091 #define S_FW_PORT_TRACE_CMD_PORTID	0
8092 #define M_FW_PORT_TRACE_CMD_PORTID	0xf
8093 #define V_FW_PORT_TRACE_CMD_PORTID(x)	((x) << S_FW_PORT_TRACE_CMD_PORTID)
8094 #define G_FW_PORT_TRACE_CMD_PORTID(x)	\
8095     (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
8096 
8097 #define S_FW_PORT_TRACE_CMD_TRACEEN	15
8098 #define M_FW_PORT_TRACE_CMD_TRACEEN	0x1
8099 #define V_FW_PORT_TRACE_CMD_TRACEEN(x)	((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
8100 #define G_FW_PORT_TRACE_CMD_TRACEEN(x)	\
8101     (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
8102 #define F_FW_PORT_TRACE_CMD_TRACEEN	V_FW_PORT_TRACE_CMD_TRACEEN(1U)
8103 
8104 #define S_FW_PORT_TRACE_CMD_FLTMODE	14
8105 #define M_FW_PORT_TRACE_CMD_FLTMODE	0x1
8106 #define V_FW_PORT_TRACE_CMD_FLTMODE(x)	((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
8107 #define G_FW_PORT_TRACE_CMD_FLTMODE(x)	\
8108     (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
8109 #define F_FW_PORT_TRACE_CMD_FLTMODE	V_FW_PORT_TRACE_CMD_FLTMODE(1U)
8110 
8111 #define S_FW_PORT_TRACE_CMD_DUPLEN	13
8112 #define M_FW_PORT_TRACE_CMD_DUPLEN	0x1
8113 #define V_FW_PORT_TRACE_CMD_DUPLEN(x)	((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
8114 #define G_FW_PORT_TRACE_CMD_DUPLEN(x)	\
8115     (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
8116 #define F_FW_PORT_TRACE_CMD_DUPLEN	V_FW_PORT_TRACE_CMD_DUPLEN(1U)
8117 
8118 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE	8
8119 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE	0x1f
8120 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
8121     ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
8122 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
8123     (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
8124      M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
8125 
8126 #define S_FW_PORT_TRACE_CMD_PCIECH	6
8127 #define M_FW_PORT_TRACE_CMD_PCIECH	0x3
8128 #define V_FW_PORT_TRACE_CMD_PCIECH(x)	((x) << S_FW_PORT_TRACE_CMD_PCIECH)
8129 #define G_FW_PORT_TRACE_CMD_PCIECH(x)	\
8130     (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
8131 
8132 struct fw_port_trace_mmap_cmd {
8133 	__be32 op_to_portid;
8134 	__be32 retval_len16;
8135 	__be32 fid_to_skipoffset;
8136 	__be32 minpktsize_capturemax;
8137 	__u8   map[224];
8138 };
8139 
8140 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID	0
8141 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID	0xf
8142 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
8143     ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
8144 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
8145     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
8146      M_FW_PORT_TRACE_MMAP_CMD_PORTID)
8147 
8148 #define S_FW_PORT_TRACE_MMAP_CMD_FID	30
8149 #define M_FW_PORT_TRACE_MMAP_CMD_FID	0x3
8150 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x)	((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
8151 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x)	\
8152     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
8153 
8154 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN	29
8155 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN	0x1
8156 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
8157     ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
8158 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
8159     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
8160      M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
8161 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN	V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
8162 
8163 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
8164 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
8165 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
8166     ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
8167 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
8168     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
8169      M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
8170 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
8171 
8172 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
8173 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
8174 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
8175     ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
8176 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
8177     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
8178      M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
8179 
8180 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
8181 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
8182 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
8183     ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
8184 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
8185     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
8186      M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
8187 
8188 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
8189 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
8190 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
8191     ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
8192 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
8193     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
8194      M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
8195 
8196 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
8197 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
8198 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
8199     ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
8200 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
8201     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
8202      M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
8203 
8204 enum fw_ptp_subop {
8205 
8206 	/* none */
8207 	FW_PTP_SC_INIT_TIMER		= 0x00,
8208 	FW_PTP_SC_TX_TYPE		= 0x01,
8209 
8210 	/* init */
8211 	FW_PTP_SC_RXTIME_STAMP		= 0x08,
8212 	FW_PTP_SC_RDRX_TYPE		= 0x09,
8213 
8214 	/* ts */
8215 	FW_PTP_SC_ADJ_FREQ		= 0x10,
8216 	FW_PTP_SC_ADJ_TIME		= 0x11,
8217 	FW_PTP_SC_ADJ_FTIME		= 0x12,
8218 	FW_PTP_SC_WALL_CLOCK		= 0x13,
8219 	FW_PTP_SC_GET_TIME		= 0x14,
8220 	FW_PTP_SC_SET_TIME		= 0x15,
8221 };
8222 
8223 struct fw_ptp_cmd {
8224 	__be32 op_to_portid;
8225 	__be32 retval_len16;
8226 	union fw_ptp {
8227 		struct fw_ptp_sc {
8228 			__u8   sc;
8229 			__u8   r3[7];
8230 		} scmd;
8231 		struct fw_ptp_init {
8232 			__u8   sc;
8233 			__u8   txchan;
8234 			__be16 absid;
8235 			__be16 mode;
8236 			__be16 ptp_rx_ctrl_pkd;
8237 		} init;
8238 		struct fw_ptp_ts {
8239 			__u8   sc;
8240 			__u8   sign;
8241 			__be16 r3;
8242 			__be32 ppb;
8243 			__be64 tm;
8244 		} ts;
8245 	} u;
8246 	__be64 r3;
8247 };
8248 
8249 #define S_FW_PTP_CMD_PORTID		0
8250 #define M_FW_PTP_CMD_PORTID		0xf
8251 #define V_FW_PTP_CMD_PORTID(x)		((x) << S_FW_PTP_CMD_PORTID)
8252 #define G_FW_PTP_CMD_PORTID(x)		\
8253     (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
8254 
8255 #define S_FW_PTP_CMD_PTP_RX_CTRL	15
8256 #define M_FW_PTP_CMD_PTP_RX_CTRL	0x1
8257 #define V_FW_PTP_CMD_PTP_RX_CTRL(x)	((x) << S_FW_PTP_CMD_PTP_RX_CTRL)
8258 #define G_FW_PTP_CMD_PTP_RX_CTRL(x)	\
8259     (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)
8260 #define F_FW_PTP_CMD_PTP_RX_CTRL	V_FW_PTP_CMD_PTP_RX_CTRL(1U)
8261 
8262 
8263 struct fw_rss_ind_tbl_cmd {
8264 	__be32 op_to_viid;
8265 	__be32 retval_len16;
8266 	__be16 niqid;
8267 	__be16 startidx;
8268 	__be32 r3;
8269 	__be32 iq0_to_iq2;
8270 	__be32 iq3_to_iq5;
8271 	__be32 iq6_to_iq8;
8272 	__be32 iq9_to_iq11;
8273 	__be32 iq12_to_iq14;
8274 	__be32 iq15_to_iq17;
8275 	__be32 iq18_to_iq20;
8276 	__be32 iq21_to_iq23;
8277 	__be32 iq24_to_iq26;
8278 	__be32 iq27_to_iq29;
8279 	__be32 iq30_iq31;
8280 	__be32 r15_lo;
8281 };
8282 
8283 #define S_FW_RSS_IND_TBL_CMD_VIID	0
8284 #define M_FW_RSS_IND_TBL_CMD_VIID	0xfff
8285 #define V_FW_RSS_IND_TBL_CMD_VIID(x)	((x) << S_FW_RSS_IND_TBL_CMD_VIID)
8286 #define G_FW_RSS_IND_TBL_CMD_VIID(x)	\
8287     (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
8288 
8289 #define S_FW_RSS_IND_TBL_CMD_IQ0	20
8290 #define M_FW_RSS_IND_TBL_CMD_IQ0	0x3ff
8291 #define V_FW_RSS_IND_TBL_CMD_IQ0(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
8292 #define G_FW_RSS_IND_TBL_CMD_IQ0(x)	\
8293     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
8294 
8295 #define S_FW_RSS_IND_TBL_CMD_IQ1	10
8296 #define M_FW_RSS_IND_TBL_CMD_IQ1	0x3ff
8297 #define V_FW_RSS_IND_TBL_CMD_IQ1(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
8298 #define G_FW_RSS_IND_TBL_CMD_IQ1(x)	\
8299     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
8300 
8301 #define S_FW_RSS_IND_TBL_CMD_IQ2	0
8302 #define M_FW_RSS_IND_TBL_CMD_IQ2	0x3ff
8303 #define V_FW_RSS_IND_TBL_CMD_IQ2(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
8304 #define G_FW_RSS_IND_TBL_CMD_IQ2(x)	\
8305     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
8306 
8307 #define S_FW_RSS_IND_TBL_CMD_IQ3	20
8308 #define M_FW_RSS_IND_TBL_CMD_IQ3	0x3ff
8309 #define V_FW_RSS_IND_TBL_CMD_IQ3(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
8310 #define G_FW_RSS_IND_TBL_CMD_IQ3(x)	\
8311     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
8312 
8313 #define S_FW_RSS_IND_TBL_CMD_IQ4	10
8314 #define M_FW_RSS_IND_TBL_CMD_IQ4	0x3ff
8315 #define V_FW_RSS_IND_TBL_CMD_IQ4(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
8316 #define G_FW_RSS_IND_TBL_CMD_IQ4(x)	\
8317     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
8318 
8319 #define S_FW_RSS_IND_TBL_CMD_IQ5	0
8320 #define M_FW_RSS_IND_TBL_CMD_IQ5	0x3ff
8321 #define V_FW_RSS_IND_TBL_CMD_IQ5(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
8322 #define G_FW_RSS_IND_TBL_CMD_IQ5(x)	\
8323     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
8324 
8325 #define S_FW_RSS_IND_TBL_CMD_IQ6	20
8326 #define M_FW_RSS_IND_TBL_CMD_IQ6	0x3ff
8327 #define V_FW_RSS_IND_TBL_CMD_IQ6(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
8328 #define G_FW_RSS_IND_TBL_CMD_IQ6(x)	\
8329     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
8330 
8331 #define S_FW_RSS_IND_TBL_CMD_IQ7	10
8332 #define M_FW_RSS_IND_TBL_CMD_IQ7	0x3ff
8333 #define V_FW_RSS_IND_TBL_CMD_IQ7(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
8334 #define G_FW_RSS_IND_TBL_CMD_IQ7(x)	\
8335     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
8336 
8337 #define S_FW_RSS_IND_TBL_CMD_IQ8	0
8338 #define M_FW_RSS_IND_TBL_CMD_IQ8	0x3ff
8339 #define V_FW_RSS_IND_TBL_CMD_IQ8(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
8340 #define G_FW_RSS_IND_TBL_CMD_IQ8(x)	\
8341     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
8342 
8343 #define S_FW_RSS_IND_TBL_CMD_IQ9	20
8344 #define M_FW_RSS_IND_TBL_CMD_IQ9	0x3ff
8345 #define V_FW_RSS_IND_TBL_CMD_IQ9(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
8346 #define G_FW_RSS_IND_TBL_CMD_IQ9(x)	\
8347     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
8348 
8349 #define S_FW_RSS_IND_TBL_CMD_IQ10	10
8350 #define M_FW_RSS_IND_TBL_CMD_IQ10	0x3ff
8351 #define V_FW_RSS_IND_TBL_CMD_IQ10(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
8352 #define G_FW_RSS_IND_TBL_CMD_IQ10(x)	\
8353     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
8354 
8355 #define S_FW_RSS_IND_TBL_CMD_IQ11	0
8356 #define M_FW_RSS_IND_TBL_CMD_IQ11	0x3ff
8357 #define V_FW_RSS_IND_TBL_CMD_IQ11(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
8358 #define G_FW_RSS_IND_TBL_CMD_IQ11(x)	\
8359     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
8360 
8361 #define S_FW_RSS_IND_TBL_CMD_IQ12	20
8362 #define M_FW_RSS_IND_TBL_CMD_IQ12	0x3ff
8363 #define V_FW_RSS_IND_TBL_CMD_IQ12(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
8364 #define G_FW_RSS_IND_TBL_CMD_IQ12(x)	\
8365     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
8366 
8367 #define S_FW_RSS_IND_TBL_CMD_IQ13	10
8368 #define M_FW_RSS_IND_TBL_CMD_IQ13	0x3ff
8369 #define V_FW_RSS_IND_TBL_CMD_IQ13(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
8370 #define G_FW_RSS_IND_TBL_CMD_IQ13(x)	\
8371     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
8372 
8373 #define S_FW_RSS_IND_TBL_CMD_IQ14	0
8374 #define M_FW_RSS_IND_TBL_CMD_IQ14	0x3ff
8375 #define V_FW_RSS_IND_TBL_CMD_IQ14(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
8376 #define G_FW_RSS_IND_TBL_CMD_IQ14(x)	\
8377     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
8378 
8379 #define S_FW_RSS_IND_TBL_CMD_IQ15	20
8380 #define M_FW_RSS_IND_TBL_CMD_IQ15	0x3ff
8381 #define V_FW_RSS_IND_TBL_CMD_IQ15(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
8382 #define G_FW_RSS_IND_TBL_CMD_IQ15(x)	\
8383     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
8384 
8385 #define S_FW_RSS_IND_TBL_CMD_IQ16	10
8386 #define M_FW_RSS_IND_TBL_CMD_IQ16	0x3ff
8387 #define V_FW_RSS_IND_TBL_CMD_IQ16(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
8388 #define G_FW_RSS_IND_TBL_CMD_IQ16(x)	\
8389     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
8390 
8391 #define S_FW_RSS_IND_TBL_CMD_IQ17	0
8392 #define M_FW_RSS_IND_TBL_CMD_IQ17	0x3ff
8393 #define V_FW_RSS_IND_TBL_CMD_IQ17(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
8394 #define G_FW_RSS_IND_TBL_CMD_IQ17(x)	\
8395     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
8396 
8397 #define S_FW_RSS_IND_TBL_CMD_IQ18	20
8398 #define M_FW_RSS_IND_TBL_CMD_IQ18	0x3ff
8399 #define V_FW_RSS_IND_TBL_CMD_IQ18(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
8400 #define G_FW_RSS_IND_TBL_CMD_IQ18(x)	\
8401     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
8402 
8403 #define S_FW_RSS_IND_TBL_CMD_IQ19	10
8404 #define M_FW_RSS_IND_TBL_CMD_IQ19	0x3ff
8405 #define V_FW_RSS_IND_TBL_CMD_IQ19(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
8406 #define G_FW_RSS_IND_TBL_CMD_IQ19(x)	\
8407     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
8408 
8409 #define S_FW_RSS_IND_TBL_CMD_IQ20	0
8410 #define M_FW_RSS_IND_TBL_CMD_IQ20	0x3ff
8411 #define V_FW_RSS_IND_TBL_CMD_IQ20(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
8412 #define G_FW_RSS_IND_TBL_CMD_IQ20(x)	\
8413     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
8414 
8415 #define S_FW_RSS_IND_TBL_CMD_IQ21	20
8416 #define M_FW_RSS_IND_TBL_CMD_IQ21	0x3ff
8417 #define V_FW_RSS_IND_TBL_CMD_IQ21(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
8418 #define G_FW_RSS_IND_TBL_CMD_IQ21(x)	\
8419     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
8420 
8421 #define S_FW_RSS_IND_TBL_CMD_IQ22	10
8422 #define M_FW_RSS_IND_TBL_CMD_IQ22	0x3ff
8423 #define V_FW_RSS_IND_TBL_CMD_IQ22(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
8424 #define G_FW_RSS_IND_TBL_CMD_IQ22(x)	\
8425     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
8426 
8427 #define S_FW_RSS_IND_TBL_CMD_IQ23	0
8428 #define M_FW_RSS_IND_TBL_CMD_IQ23	0x3ff
8429 #define V_FW_RSS_IND_TBL_CMD_IQ23(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
8430 #define G_FW_RSS_IND_TBL_CMD_IQ23(x)	\
8431     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
8432 
8433 #define S_FW_RSS_IND_TBL_CMD_IQ24	20
8434 #define M_FW_RSS_IND_TBL_CMD_IQ24	0x3ff
8435 #define V_FW_RSS_IND_TBL_CMD_IQ24(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
8436 #define G_FW_RSS_IND_TBL_CMD_IQ24(x)	\
8437     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
8438 
8439 #define S_FW_RSS_IND_TBL_CMD_IQ25	10
8440 #define M_FW_RSS_IND_TBL_CMD_IQ25	0x3ff
8441 #define V_FW_RSS_IND_TBL_CMD_IQ25(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
8442 #define G_FW_RSS_IND_TBL_CMD_IQ25(x)	\
8443     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
8444 
8445 #define S_FW_RSS_IND_TBL_CMD_IQ26	0
8446 #define M_FW_RSS_IND_TBL_CMD_IQ26	0x3ff
8447 #define V_FW_RSS_IND_TBL_CMD_IQ26(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
8448 #define G_FW_RSS_IND_TBL_CMD_IQ26(x)	\
8449     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
8450 
8451 #define S_FW_RSS_IND_TBL_CMD_IQ27	20
8452 #define M_FW_RSS_IND_TBL_CMD_IQ27	0x3ff
8453 #define V_FW_RSS_IND_TBL_CMD_IQ27(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
8454 #define G_FW_RSS_IND_TBL_CMD_IQ27(x)	\
8455     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
8456 
8457 #define S_FW_RSS_IND_TBL_CMD_IQ28	10
8458 #define M_FW_RSS_IND_TBL_CMD_IQ28	0x3ff
8459 #define V_FW_RSS_IND_TBL_CMD_IQ28(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
8460 #define G_FW_RSS_IND_TBL_CMD_IQ28(x)	\
8461     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
8462 
8463 #define S_FW_RSS_IND_TBL_CMD_IQ29	0
8464 #define M_FW_RSS_IND_TBL_CMD_IQ29	0x3ff
8465 #define V_FW_RSS_IND_TBL_CMD_IQ29(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
8466 #define G_FW_RSS_IND_TBL_CMD_IQ29(x)	\
8467     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
8468 
8469 #define S_FW_RSS_IND_TBL_CMD_IQ30	20
8470 #define M_FW_RSS_IND_TBL_CMD_IQ30	0x3ff
8471 #define V_FW_RSS_IND_TBL_CMD_IQ30(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
8472 #define G_FW_RSS_IND_TBL_CMD_IQ30(x)	\
8473     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
8474 
8475 #define S_FW_RSS_IND_TBL_CMD_IQ31	10
8476 #define M_FW_RSS_IND_TBL_CMD_IQ31	0x3ff
8477 #define V_FW_RSS_IND_TBL_CMD_IQ31(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
8478 #define G_FW_RSS_IND_TBL_CMD_IQ31(x)	\
8479     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
8480 
8481 struct fw_rss_glb_config_cmd {
8482 	__be32 op_to_write;
8483 	__be32 retval_len16;
8484 	union fw_rss_glb_config {
8485 		struct fw_rss_glb_config_manual {
8486 			__be32 mode_pkd;
8487 			__be32 r3;
8488 			__be64 r4;
8489 			__be64 r5;
8490 		} manual;
8491 		struct fw_rss_glb_config_basicvirtual {
8492 			__be32 mode_keymode;
8493 			__be32 synmapen_to_hashtoeplitz;
8494 			__be64 r8;
8495 			__be64 r9;
8496 		} basicvirtual;
8497 	} u;
8498 };
8499 
8500 #define S_FW_RSS_GLB_CONFIG_CMD_MODE	28
8501 #define M_FW_RSS_GLB_CONFIG_CMD_MODE	0xf
8502 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x)	((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
8503 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x)	\
8504     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
8505 
8506 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
8507 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
8508 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX		1
8509 
8510 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE	26
8511 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE	0x3
8512 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8513     ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8514 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8515     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
8516      M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8517 
8518 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY	0
8519 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY	1
8520 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY	2
8521 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY	3
8522 
8523 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
8524 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
8525 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8526     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8527 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8528     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
8529      M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8530 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
8531 
8532 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
8533 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
8534 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8535     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8536 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8537     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
8538      M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8539 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
8540     V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
8541 
8542 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
8543 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
8544 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8545     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8546 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8547     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
8548      M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8549 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
8550     V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
8551 
8552 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
8553 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
8554 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8555     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8556 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8557     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
8558      M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8559 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
8560     V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
8561 
8562 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
8563 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
8564 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8565     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8566 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8567     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
8568      M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8569 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
8570     V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
8571 
8572 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
8573 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
8574 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8575     ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8576 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8577     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
8578      M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8579 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
8580 
8581 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
8582 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
8583 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8584     ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8585 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8586     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
8587      M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8588 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
8589 
8590 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
8591 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
8592 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8593     ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8594 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8595     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
8596      M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8597 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
8598     V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
8599 
8600 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
8601 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
8602 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8603     ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8604 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8605     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
8606      M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8607 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
8608     V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
8609 
8610 struct fw_rss_vi_config_cmd {
8611 	__be32 op_to_viid;
8612 	__be32 retval_len16;
8613 	union fw_rss_vi_config {
8614 		struct fw_rss_vi_config_manual {
8615 			__be64 r3;
8616 			__be64 r4;
8617 			__be64 r5;
8618 		} manual;
8619 		struct fw_rss_vi_config_basicvirtual {
8620 			__be32 r6;
8621 			__be32 defaultq_to_udpen;
8622 			__be32 secretkeyidx_pkd;
8623 			__be32 secretkeyxor;
8624 			__be64 r10;
8625 		} basicvirtual;
8626 	} u;
8627 };
8628 
8629 #define S_FW_RSS_VI_CONFIG_CMD_VIID	0
8630 #define M_FW_RSS_VI_CONFIG_CMD_VIID	0xfff
8631 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
8632 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x)	\
8633     (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
8634 
8635 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ	16
8636 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ	0x3ff
8637 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8638     ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8639 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8640     (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
8641      M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8642 
8643 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
8644 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
8645 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8646     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8647 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8648     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
8649      M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8650 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
8651     V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
8652 
8653 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
8654 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
8655 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8656     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8657 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8658     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
8659      M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8660 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
8661     V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
8662 
8663 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
8664 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
8665 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8666     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8667 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8668     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
8669      M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8670 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
8671     V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
8672 
8673 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
8674 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
8675 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8676     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8677 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8678     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
8679      M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8680 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
8681     V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
8682 
8683 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN	0
8684 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN	0x1
8685 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
8686 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	\
8687     (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
8688 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
8689 
8690 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
8691 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
8692 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8693     ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8694 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8695     (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
8696      M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8697 
8698 enum fw_sched_sc {
8699 	FW_SCHED_SC_CONFIG		= 0,
8700 	FW_SCHED_SC_PARAMS		= 1,
8701 };
8702 
8703 enum fw_sched_type {
8704 	FW_SCHED_TYPE_PKTSCHED	        = 0,
8705 	FW_SCHED_TYPE_STREAMSCHED       = 1,
8706 };
8707 
8708 enum fw_sched_params_level {
8709 	FW_SCHED_PARAMS_LEVEL_CL_RL	= 0,
8710 	FW_SCHED_PARAMS_LEVEL_CL_WRR	= 1,
8711 	FW_SCHED_PARAMS_LEVEL_CH_RL	= 2,
8712 };
8713 
8714 enum fw_sched_params_mode {
8715 	FW_SCHED_PARAMS_MODE_CLASS	= 0,
8716 	FW_SCHED_PARAMS_MODE_FLOW	= 1,
8717 };
8718 
8719 enum fw_sched_params_unit {
8720 	FW_SCHED_PARAMS_UNIT_BITRATE	= 0,
8721 	FW_SCHED_PARAMS_UNIT_PKTRATE	= 1,
8722 };
8723 
8724 enum fw_sched_params_rate {
8725 	FW_SCHED_PARAMS_RATE_REL	= 0,
8726 	FW_SCHED_PARAMS_RATE_ABS	= 1,
8727 };
8728 
8729 struct fw_sched_cmd {
8730 	__be32 op_to_write;
8731 	__be32 retval_len16;
8732 	union fw_sched {
8733 		struct fw_sched_config {
8734 			__u8   sc;
8735 			__u8   type;
8736 			__u8   minmaxen;
8737 			__u8   r3[5];
8738 			__u8   nclasses[4];
8739 			__be32 r4;
8740 		} config;
8741 		struct fw_sched_params {
8742 			__u8   sc;
8743 			__u8   type;
8744 			__u8   level;
8745 			__u8   mode;
8746 			__u8   unit;
8747 			__u8   rate;
8748 			__u8   ch;
8749 			__u8   cl;
8750 			__be32 min;
8751 			__be32 max;
8752 			__be16 weight;
8753 			__be16 pktsize;
8754 			__be16 burstsize;
8755 			__be16 r4;
8756 		} params;
8757 	} u;
8758 };
8759 
8760 /*
8761  *	length of the formatting string
8762  */
8763 #define FW_DEVLOG_FMT_LEN	192
8764 
8765 /*
8766  *	maximum number of the formatting string parameters
8767  */
8768 #define FW_DEVLOG_FMT_PARAMS_NUM 8
8769 
8770 /*
8771  *	priority levels
8772  */
8773 enum fw_devlog_level {
8774 	FW_DEVLOG_LEVEL_EMERG	= 0x0,
8775 	FW_DEVLOG_LEVEL_CRIT	= 0x1,
8776 	FW_DEVLOG_LEVEL_ERR	= 0x2,
8777 	FW_DEVLOG_LEVEL_NOTICE	= 0x3,
8778 	FW_DEVLOG_LEVEL_INFO	= 0x4,
8779 	FW_DEVLOG_LEVEL_DEBUG	= 0x5,
8780 	FW_DEVLOG_LEVEL_MAX	= 0x5,
8781 };
8782 
8783 /*
8784  *	facilities that may send a log message
8785  */
8786 enum fw_devlog_facility {
8787 	FW_DEVLOG_FACILITY_CORE		= 0x00,
8788 	FW_DEVLOG_FACILITY_CF		= 0x01,
8789 	FW_DEVLOG_FACILITY_SCHED	= 0x02,
8790 	FW_DEVLOG_FACILITY_TIMER	= 0x04,
8791 	FW_DEVLOG_FACILITY_RES		= 0x06,
8792 	FW_DEVLOG_FACILITY_HW		= 0x08,
8793 	FW_DEVLOG_FACILITY_FLR		= 0x10,
8794 	FW_DEVLOG_FACILITY_DMAQ		= 0x12,
8795 	FW_DEVLOG_FACILITY_PHY		= 0x14,
8796 	FW_DEVLOG_FACILITY_MAC		= 0x16,
8797 	FW_DEVLOG_FACILITY_PORT		= 0x18,
8798 	FW_DEVLOG_FACILITY_VI		= 0x1A,
8799 	FW_DEVLOG_FACILITY_FILTER	= 0x1C,
8800 	FW_DEVLOG_FACILITY_ACL		= 0x1E,
8801 	FW_DEVLOG_FACILITY_TM		= 0x20,
8802 	FW_DEVLOG_FACILITY_QFC		= 0x22,
8803 	FW_DEVLOG_FACILITY_DCB		= 0x24,
8804 	FW_DEVLOG_FACILITY_ETH		= 0x26,
8805 	FW_DEVLOG_FACILITY_OFLD		= 0x28,
8806 	FW_DEVLOG_FACILITY_RI		= 0x2A,
8807 	FW_DEVLOG_FACILITY_ISCSI	= 0x2C,
8808 	FW_DEVLOG_FACILITY_FCOE		= 0x2E,
8809 	FW_DEVLOG_FACILITY_FOISCSI	= 0x30,
8810 	FW_DEVLOG_FACILITY_FOFCOE	= 0x32,
8811 	FW_DEVLOG_FACILITY_CHNET	= 0x34,
8812 	FW_DEVLOG_FACILITY_COISCSI	= 0x36,
8813 	FW_DEVLOG_FACILITY_MAX		= 0x38,
8814 };
8815 
8816 /*
8817  *	log message format
8818  */
8819 struct fw_devlog_e {
8820 	__be64	timestamp;
8821 	__be32	seqno;
8822 	__be16	reserved1;
8823 	__u8	level;
8824 	__u8	facility;
8825 	__u8	fmt[FW_DEVLOG_FMT_LEN];
8826 	__be32	params[FW_DEVLOG_FMT_PARAMS_NUM];
8827 	__be32	reserved3[4];
8828 };
8829 
8830 struct fw_devlog_cmd {
8831 	__be32 op_to_write;
8832 	__be32 retval_len16;
8833 	__u8   level;
8834 	__u8   r2[7];
8835 	__be32 memtype_devlog_memaddr16_devlog;
8836 	__be32 memsize_devlog;
8837 	__be32 r3[2];
8838 };
8839 
8840 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG	28
8841 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG	0xf
8842 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8843     ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8844 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8845     (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8846 
8847 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
8848 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
8849 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8850     ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8851 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8852     (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
8853      M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8854 
8855 enum fw_watchdog_actions {
8856 	FW_WATCHDOG_ACTION_SHUTDOWN = 0,
8857 	FW_WATCHDOG_ACTION_FLR = 1,
8858 	FW_WATCHDOG_ACTION_BYPASS = 2,
8859 	FW_WATCHDOG_ACTION_TMPCHK = 3,
8860 	FW_WATCHDOG_ACTION_PAUSEOFF = 4,
8861 
8862 	FW_WATCHDOG_ACTION_MAX = 5,
8863 };
8864 
8865 #define FW_WATCHDOG_MAX_TIMEOUT_SECS	60
8866 
8867 struct fw_watchdog_cmd {
8868 	__be32 op_to_vfn;
8869 	__be32 retval_len16;
8870 	__be32 timeout;
8871 	__be32 action;
8872 };
8873 
8874 #define S_FW_WATCHDOG_CMD_PFN		8
8875 #define M_FW_WATCHDOG_CMD_PFN		0x7
8876 #define V_FW_WATCHDOG_CMD_PFN(x)	((x) << S_FW_WATCHDOG_CMD_PFN)
8877 #define G_FW_WATCHDOG_CMD_PFN(x)	\
8878     (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
8879 
8880 #define S_FW_WATCHDOG_CMD_VFN		0
8881 #define M_FW_WATCHDOG_CMD_VFN		0xff
8882 #define V_FW_WATCHDOG_CMD_VFN(x)	((x) << S_FW_WATCHDOG_CMD_VFN)
8883 #define G_FW_WATCHDOG_CMD_VFN(x)	\
8884     (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
8885 
8886 struct fw_clip_cmd {
8887 	__be32 op_to_write;
8888 	__be32 alloc_to_len16;
8889 	__be64 ip_hi;
8890 	__be64 ip_lo;
8891 	__be32 r4[2];
8892 };
8893 
8894 #define S_FW_CLIP_CMD_ALLOC		31
8895 #define M_FW_CLIP_CMD_ALLOC		0x1
8896 #define V_FW_CLIP_CMD_ALLOC(x)		((x) << S_FW_CLIP_CMD_ALLOC)
8897 #define G_FW_CLIP_CMD_ALLOC(x)		\
8898     (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
8899 #define F_FW_CLIP_CMD_ALLOC		V_FW_CLIP_CMD_ALLOC(1U)
8900 
8901 #define S_FW_CLIP_CMD_FREE		30
8902 #define M_FW_CLIP_CMD_FREE		0x1
8903 #define V_FW_CLIP_CMD_FREE(x)		((x) << S_FW_CLIP_CMD_FREE)
8904 #define G_FW_CLIP_CMD_FREE(x)		\
8905     (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
8906 #define F_FW_CLIP_CMD_FREE		V_FW_CLIP_CMD_FREE(1U)
8907 
8908 #define S_FW_CLIP_CMD_INDEX	16
8909 #define M_FW_CLIP_CMD_INDEX	0x1fff
8910 #define V_FW_CLIP_CMD_INDEX(x)	((x) << S_FW_CLIP_CMD_INDEX)
8911 #define G_FW_CLIP_CMD_INDEX(x)	\
8912     (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
8913 
8914 /******************************************************************************
8915  *   F O i S C S I   C O M M A N D s
8916  **************************************/
8917 
8918 #define	FW_CHNET_IFACE_ADDR_MAX	3
8919 
8920 enum fw_chnet_iface_cmd_subop {
8921 	FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
8922 
8923 	FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
8924 	FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
8925 
8926 	FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
8927 	FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
8928 
8929 	FW_CHNET_IFACE_CMD_SUBOP_MAX,
8930 };
8931 
8932 struct fw_chnet_iface_cmd {
8933 	__be32 op_to_portid;
8934 	__be32 retval_len16;
8935 	__u8   subop;
8936 	__u8   r2[2];
8937 	__u8   flags;
8938 	__be32 ifid_ifstate;
8939 	__be16 mtu;
8940 	__be16 vlanid;
8941 	__be32 r3;
8942 	__be16 r4;
8943 	__u8   mac[6];
8944 };
8945 
8946 #define S_FW_CHNET_IFACE_CMD_PORTID	0
8947 #define M_FW_CHNET_IFACE_CMD_PORTID	0xf
8948 #define V_FW_CHNET_IFACE_CMD_PORTID(x)	((x) << S_FW_CHNET_IFACE_CMD_PORTID)
8949 #define G_FW_CHNET_IFACE_CMD_PORTID(x)	\
8950     (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
8951 
8952 #define S_FW_CHNET_IFACE_CMD_IFID	8
8953 #define M_FW_CHNET_IFACE_CMD_IFID	0xffffff
8954 #define V_FW_CHNET_IFACE_CMD_IFID(x)	((x) << S_FW_CHNET_IFACE_CMD_IFID)
8955 #define G_FW_CHNET_IFACE_CMD_IFID(x)	\
8956     (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
8957 
8958 #define S_FW_CHNET_IFACE_CMD_IFSTATE	0
8959 #define M_FW_CHNET_IFACE_CMD_IFSTATE	0xff
8960 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x)	((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
8961 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x)	\
8962     (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
8963 
8964 struct fw_fcoe_res_info_cmd {
8965 	__be32 op_to_read;
8966 	__be32 retval_len16;
8967 	__be16 e_d_tov;
8968 	__be16 r_a_tov_seq;
8969 	__be16 r_a_tov_els;
8970 	__be16 r_r_tov;
8971 	__be32 max_xchgs;
8972 	__be32 max_ssns;
8973 	__be32 used_xchgs;
8974 	__be32 used_ssns;
8975 	__be32 max_fcfs;
8976 	__be32 max_vnps;
8977 	__be32 used_fcfs;
8978 	__be32 used_vnps;
8979 };
8980 
8981 struct fw_fcoe_link_cmd {
8982 	__be32 op_to_portid;
8983 	__be32 retval_len16;
8984 	__be32 sub_opcode_fcfi;
8985 	__u8   r3;
8986 	__u8   lstatus;
8987 	__be16 flags;
8988 	__u8   r4;
8989 	__u8   set_vlan;
8990 	__be16 vlan_id;
8991 	__be32 vnpi_pkd;
8992 	__be16 r6;
8993 	__u8   phy_mac[6];
8994 	__u8   vnport_wwnn[8];
8995 	__u8   vnport_wwpn[8];
8996 };
8997 
8998 #define S_FW_FCOE_LINK_CMD_PORTID	0
8999 #define M_FW_FCOE_LINK_CMD_PORTID	0xf
9000 #define V_FW_FCOE_LINK_CMD_PORTID(x)	((x) << S_FW_FCOE_LINK_CMD_PORTID)
9001 #define G_FW_FCOE_LINK_CMD_PORTID(x)	\
9002     (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
9003 
9004 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE	24
9005 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE	0xff
9006 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
9007     ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
9008 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
9009     (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
9010 
9011 #define S_FW_FCOE_LINK_CMD_FCFI		0
9012 #define M_FW_FCOE_LINK_CMD_FCFI		0xffffff
9013 #define V_FW_FCOE_LINK_CMD_FCFI(x)	((x) << S_FW_FCOE_LINK_CMD_FCFI)
9014 #define G_FW_FCOE_LINK_CMD_FCFI(x)	\
9015     (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
9016 
9017 #define S_FW_FCOE_LINK_CMD_VNPI		0
9018 #define M_FW_FCOE_LINK_CMD_VNPI		0xfffff
9019 #define V_FW_FCOE_LINK_CMD_VNPI(x)	((x) << S_FW_FCOE_LINK_CMD_VNPI)
9020 #define G_FW_FCOE_LINK_CMD_VNPI(x)	\
9021     (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
9022 
9023 struct fw_fcoe_vnp_cmd {
9024 	__be32 op_to_fcfi;
9025 	__be32 alloc_to_len16;
9026 	__be32 gen_wwn_to_vnpi;
9027 	__be32 vf_id;
9028 	__be16 iqid;
9029 	__u8   vnport_mac[6];
9030 	__u8   vnport_wwnn[8];
9031 	__u8   vnport_wwpn[8];
9032 	__u8   cmn_srv_parms[16];
9033 	__u8   clsp_word_0_1[8];
9034 };
9035 
9036 #define S_FW_FCOE_VNP_CMD_FCFI		0
9037 #define M_FW_FCOE_VNP_CMD_FCFI		0xfffff
9038 #define V_FW_FCOE_VNP_CMD_FCFI(x)	((x) << S_FW_FCOE_VNP_CMD_FCFI)
9039 #define G_FW_FCOE_VNP_CMD_FCFI(x)	\
9040     (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
9041 
9042 #define S_FW_FCOE_VNP_CMD_ALLOC		31
9043 #define M_FW_FCOE_VNP_CMD_ALLOC		0x1
9044 #define V_FW_FCOE_VNP_CMD_ALLOC(x)	((x) << S_FW_FCOE_VNP_CMD_ALLOC)
9045 #define G_FW_FCOE_VNP_CMD_ALLOC(x)	\
9046     (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
9047 #define F_FW_FCOE_VNP_CMD_ALLOC		V_FW_FCOE_VNP_CMD_ALLOC(1U)
9048 
9049 #define S_FW_FCOE_VNP_CMD_FREE		30
9050 #define M_FW_FCOE_VNP_CMD_FREE		0x1
9051 #define V_FW_FCOE_VNP_CMD_FREE(x)	((x) << S_FW_FCOE_VNP_CMD_FREE)
9052 #define G_FW_FCOE_VNP_CMD_FREE(x)	\
9053     (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
9054 #define F_FW_FCOE_VNP_CMD_FREE		V_FW_FCOE_VNP_CMD_FREE(1U)
9055 
9056 #define S_FW_FCOE_VNP_CMD_MODIFY	29
9057 #define M_FW_FCOE_VNP_CMD_MODIFY	0x1
9058 #define V_FW_FCOE_VNP_CMD_MODIFY(x)	((x) << S_FW_FCOE_VNP_CMD_MODIFY)
9059 #define G_FW_FCOE_VNP_CMD_MODIFY(x)	\
9060     (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
9061 #define F_FW_FCOE_VNP_CMD_MODIFY	V_FW_FCOE_VNP_CMD_MODIFY(1U)
9062 
9063 #define S_FW_FCOE_VNP_CMD_GEN_WWN	22
9064 #define M_FW_FCOE_VNP_CMD_GEN_WWN	0x1
9065 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x)	((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
9066 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x)	\
9067     (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
9068 #define F_FW_FCOE_VNP_CMD_GEN_WWN	V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
9069 
9070 #define S_FW_FCOE_VNP_CMD_PERSIST	21
9071 #define M_FW_FCOE_VNP_CMD_PERSIST	0x1
9072 #define V_FW_FCOE_VNP_CMD_PERSIST(x)	((x) << S_FW_FCOE_VNP_CMD_PERSIST)
9073 #define G_FW_FCOE_VNP_CMD_PERSIST(x)	\
9074     (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
9075 #define F_FW_FCOE_VNP_CMD_PERSIST	V_FW_FCOE_VNP_CMD_PERSIST(1U)
9076 
9077 #define S_FW_FCOE_VNP_CMD_VFID_EN	20
9078 #define M_FW_FCOE_VNP_CMD_VFID_EN	0x1
9079 #define V_FW_FCOE_VNP_CMD_VFID_EN(x)	((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
9080 #define G_FW_FCOE_VNP_CMD_VFID_EN(x)	\
9081     (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
9082 #define F_FW_FCOE_VNP_CMD_VFID_EN	V_FW_FCOE_VNP_CMD_VFID_EN(1U)
9083 
9084 #define S_FW_FCOE_VNP_CMD_VNPI		0
9085 #define M_FW_FCOE_VNP_CMD_VNPI		0xfffff
9086 #define V_FW_FCOE_VNP_CMD_VNPI(x)	((x) << S_FW_FCOE_VNP_CMD_VNPI)
9087 #define G_FW_FCOE_VNP_CMD_VNPI(x)	\
9088     (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
9089 
9090 struct fw_fcoe_sparams_cmd {
9091 	__be32 op_to_portid;
9092 	__be32 retval_len16;
9093 	__u8   r3[7];
9094 	__u8   cos;
9095 	__u8   lport_wwnn[8];
9096 	__u8   lport_wwpn[8];
9097 	__u8   cmn_srv_parms[16];
9098 	__u8   cls_srv_parms[16];
9099 };
9100 
9101 #define S_FW_FCOE_SPARAMS_CMD_PORTID	0
9102 #define M_FW_FCOE_SPARAMS_CMD_PORTID	0xf
9103 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x)	((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
9104 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x)	\
9105     (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
9106 
9107 struct fw_fcoe_stats_cmd {
9108 	__be32 op_to_flowid;
9109 	__be32 free_to_len16;
9110 	union fw_fcoe_stats {
9111 		struct fw_fcoe_stats_ctl {
9112 			__u8   nstats_port;
9113 			__u8   port_valid_ix;
9114 			__be16 r6;
9115 			__be32 r7;
9116 			__be64 stat0;
9117 			__be64 stat1;
9118 			__be64 stat2;
9119 			__be64 stat3;
9120 			__be64 stat4;
9121 			__be64 stat5;
9122 		} ctl;
9123 		struct fw_fcoe_port_stats {
9124 			__be64 tx_bcast_bytes;
9125 			__be64 tx_bcast_frames;
9126 			__be64 tx_mcast_bytes;
9127 			__be64 tx_mcast_frames;
9128 			__be64 tx_ucast_bytes;
9129 			__be64 tx_ucast_frames;
9130 			__be64 tx_drop_frames;
9131 			__be64 tx_offload_bytes;
9132 			__be64 tx_offload_frames;
9133 			__be64 rx_bcast_bytes;
9134 			__be64 rx_bcast_frames;
9135 			__be64 rx_mcast_bytes;
9136 			__be64 rx_mcast_frames;
9137 			__be64 rx_ucast_bytes;
9138 			__be64 rx_ucast_frames;
9139 			__be64 rx_err_frames;
9140 		} port_stats;
9141 		struct fw_fcoe_fcf_stats {
9142 			__be32 fip_tx_bytes;
9143 			__be32 fip_tx_fr;
9144 			__be64 fcf_ka;
9145 			__be64 mcast_adv_rcvd;
9146 			__be16 ucast_adv_rcvd;
9147 			__be16 sol_sent;
9148 			__be16 vlan_req;
9149 			__be16 vlan_rpl;
9150 			__be16 clr_vlink;
9151 			__be16 link_down;
9152 			__be16 link_up;
9153 			__be16 logo;
9154 			__be16 flogi_req;
9155 			__be16 flogi_rpl;
9156 			__be16 fdisc_req;
9157 			__be16 fdisc_rpl;
9158 			__be16 fka_prd_chg;
9159 			__be16 fc_map_chg;
9160 			__be16 vfid_chg;
9161 			__u8   no_fka_req;
9162 			__u8   no_vnp;
9163 		} fcf_stats;
9164 		struct fw_fcoe_pcb_stats {
9165 			__be64 tx_bytes;
9166 			__be64 tx_frames;
9167 			__be64 rx_bytes;
9168 			__be64 rx_frames;
9169 			__be32 vnp_ka;
9170 			__be32 unsol_els_rcvd;
9171 			__be64 unsol_cmd_rcvd;
9172 			__be16 implicit_logo;
9173 			__be16 flogi_inv_sparm;
9174 			__be16 fdisc_inv_sparm;
9175 			__be16 flogi_rjt;
9176 			__be16 fdisc_rjt;
9177 			__be16 no_ssn;
9178 			__be16 mac_flt_fail;
9179 			__be16 inv_fr_rcvd;
9180 		} pcb_stats;
9181 		struct fw_fcoe_scb_stats {
9182 			__be64 tx_bytes;
9183 			__be64 tx_frames;
9184 			__be64 rx_bytes;
9185 			__be64 rx_frames;
9186 			__be32 host_abrt_req;
9187 			__be32 adap_auto_abrt;
9188 			__be32 adap_abrt_rsp;
9189 			__be32 host_ios_req;
9190 			__be16 ssn_offl_ios;
9191 			__be16 ssn_not_rdy_ios;
9192 			__u8   rx_data_ddp_err;
9193 			__u8   ddp_flt_set_err;
9194 			__be16 rx_data_fr_err;
9195 			__u8   bad_st_abrt_req;
9196 			__u8   no_io_abrt_req;
9197 			__u8   abort_tmo;
9198 			__u8   abort_tmo_2;
9199 			__be32 abort_req;
9200 			__u8   no_ppod_res_tmo;
9201 			__u8   bp_tmo;
9202 			__u8   adap_auto_cls;
9203 			__u8   no_io_cls_req;
9204 			__be32 host_cls_req;
9205 			__be64 unsol_cmd_rcvd;
9206 			__be32 plogi_req_rcvd;
9207 			__be32 prli_req_rcvd;
9208 			__be16 logo_req_rcvd;
9209 			__be16 prlo_req_rcvd;
9210 			__be16 plogi_rjt_rcvd;
9211 			__be16 prli_rjt_rcvd;
9212 			__be32 adisc_req_rcvd;
9213 			__be32 rscn_rcvd;
9214 			__be32 rrq_req_rcvd;
9215 			__be32 unsol_els_rcvd;
9216 			__u8   adisc_rjt_rcvd;
9217 			__u8   scr_rjt;
9218 			__u8   ct_rjt;
9219 			__u8   inval_bls_rcvd;
9220 			__be32 ba_rjt_rcvd;
9221 		} scb_stats;
9222 	} u;
9223 };
9224 
9225 #define S_FW_FCOE_STATS_CMD_FLOWID	0
9226 #define M_FW_FCOE_STATS_CMD_FLOWID	0xfffff
9227 #define V_FW_FCOE_STATS_CMD_FLOWID(x)	((x) << S_FW_FCOE_STATS_CMD_FLOWID)
9228 #define G_FW_FCOE_STATS_CMD_FLOWID(x)	\
9229     (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
9230 
9231 #define S_FW_FCOE_STATS_CMD_FREE	30
9232 #define M_FW_FCOE_STATS_CMD_FREE	0x1
9233 #define V_FW_FCOE_STATS_CMD_FREE(x)	((x) << S_FW_FCOE_STATS_CMD_FREE)
9234 #define G_FW_FCOE_STATS_CMD_FREE(x)	\
9235     (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
9236 #define F_FW_FCOE_STATS_CMD_FREE	V_FW_FCOE_STATS_CMD_FREE(1U)
9237 
9238 #define S_FW_FCOE_STATS_CMD_NSTATS	4
9239 #define M_FW_FCOE_STATS_CMD_NSTATS	0x7
9240 #define V_FW_FCOE_STATS_CMD_NSTATS(x)	((x) << S_FW_FCOE_STATS_CMD_NSTATS)
9241 #define G_FW_FCOE_STATS_CMD_NSTATS(x)	\
9242     (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
9243 
9244 #define S_FW_FCOE_STATS_CMD_PORT	0
9245 #define M_FW_FCOE_STATS_CMD_PORT	0x3
9246 #define V_FW_FCOE_STATS_CMD_PORT(x)	((x) << S_FW_FCOE_STATS_CMD_PORT)
9247 #define G_FW_FCOE_STATS_CMD_PORT(x)	\
9248     (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
9249 
9250 #define S_FW_FCOE_STATS_CMD_PORT_VALID	7
9251 #define M_FW_FCOE_STATS_CMD_PORT_VALID	0x1
9252 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
9253     ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
9254 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
9255     (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
9256 #define F_FW_FCOE_STATS_CMD_PORT_VALID	V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
9257 
9258 #define S_FW_FCOE_STATS_CMD_IX		0
9259 #define M_FW_FCOE_STATS_CMD_IX		0x3f
9260 #define V_FW_FCOE_STATS_CMD_IX(x)	((x) << S_FW_FCOE_STATS_CMD_IX)
9261 #define G_FW_FCOE_STATS_CMD_IX(x)	\
9262     (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
9263 
9264 struct fw_fcoe_fcf_cmd {
9265 	__be32 op_to_fcfi;
9266 	__be32 retval_len16;
9267 	__be16 priority_pkd;
9268 	__u8   mac[6];
9269 	__u8   name_id[8];
9270 	__u8   fabric[8];
9271 	__be16 vf_id;
9272 	__be16 max_fcoe_size;
9273 	__u8   vlan_id;
9274 	__u8   fc_map[3];
9275 	__be32 fka_adv;
9276 	__be32 r6;
9277 	__u8   r7_hi;
9278 	__u8   fpma_to_portid;
9279 	__u8   spma_mac[6];
9280 	__be64 r8;
9281 };
9282 
9283 #define S_FW_FCOE_FCF_CMD_FCFI		0
9284 #define M_FW_FCOE_FCF_CMD_FCFI		0xfffff
9285 #define V_FW_FCOE_FCF_CMD_FCFI(x)	((x) << S_FW_FCOE_FCF_CMD_FCFI)
9286 #define G_FW_FCOE_FCF_CMD_FCFI(x)	\
9287     (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
9288 
9289 #define S_FW_FCOE_FCF_CMD_PRIORITY	0
9290 #define M_FW_FCOE_FCF_CMD_PRIORITY	0xff
9291 #define V_FW_FCOE_FCF_CMD_PRIORITY(x)	((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
9292 #define G_FW_FCOE_FCF_CMD_PRIORITY(x)	\
9293     (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
9294 
9295 #define S_FW_FCOE_FCF_CMD_FPMA		6
9296 #define M_FW_FCOE_FCF_CMD_FPMA		0x1
9297 #define V_FW_FCOE_FCF_CMD_FPMA(x)	((x) << S_FW_FCOE_FCF_CMD_FPMA)
9298 #define G_FW_FCOE_FCF_CMD_FPMA(x)	\
9299     (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
9300 #define F_FW_FCOE_FCF_CMD_FPMA		V_FW_FCOE_FCF_CMD_FPMA(1U)
9301 
9302 #define S_FW_FCOE_FCF_CMD_SPMA		5
9303 #define M_FW_FCOE_FCF_CMD_SPMA		0x1
9304 #define V_FW_FCOE_FCF_CMD_SPMA(x)	((x) << S_FW_FCOE_FCF_CMD_SPMA)
9305 #define G_FW_FCOE_FCF_CMD_SPMA(x)	\
9306     (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
9307 #define F_FW_FCOE_FCF_CMD_SPMA		V_FW_FCOE_FCF_CMD_SPMA(1U)
9308 
9309 #define S_FW_FCOE_FCF_CMD_LOGIN		4
9310 #define M_FW_FCOE_FCF_CMD_LOGIN		0x1
9311 #define V_FW_FCOE_FCF_CMD_LOGIN(x)	((x) << S_FW_FCOE_FCF_CMD_LOGIN)
9312 #define G_FW_FCOE_FCF_CMD_LOGIN(x)	\
9313     (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
9314 #define F_FW_FCOE_FCF_CMD_LOGIN		V_FW_FCOE_FCF_CMD_LOGIN(1U)
9315 
9316 #define S_FW_FCOE_FCF_CMD_PORTID	0
9317 #define M_FW_FCOE_FCF_CMD_PORTID	0xf
9318 #define V_FW_FCOE_FCF_CMD_PORTID(x)	((x) << S_FW_FCOE_FCF_CMD_PORTID)
9319 #define G_FW_FCOE_FCF_CMD_PORTID(x)	\
9320     (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
9321 
9322 /******************************************************************************
9323  *   E R R O R   a n d   D E B U G   C O M M A N D s
9324  ******************************************************/
9325 
9326 enum fw_error_type {
9327 	FW_ERROR_TYPE_EXCEPTION		= 0x0,
9328 	FW_ERROR_TYPE_HWMODULE		= 0x1,
9329 	FW_ERROR_TYPE_WR		= 0x2,
9330 	FW_ERROR_TYPE_ACL		= 0x3,
9331 };
9332 
9333 enum fw_dcb_ieee_locations {
9334 	FW_IEEE_LOC_LOCAL,
9335 	FW_IEEE_LOC_PEER,
9336 	FW_IEEE_LOC_OPERATIONAL,
9337 };
9338 
9339 struct fw_dcb_ieee_cmd {
9340 	__be32 op_to_location;
9341 	__be32 changed_to_len16;
9342 	union fw_dcbx_stats {
9343 		struct fw_dcbx_pfc_stats_ieee {
9344 			__be32 pfc_mbc_pkd;
9345 			__be32 pfc_willing_to_pfc_en;
9346 		} dcbx_pfc_stats;
9347 		struct fw_dcbx_ets_stats_ieee {
9348 			__be32 cbs_to_ets_max_tc;
9349 			__be32 pg_table;
9350 			__u8   pg_percent[8];
9351 			__u8   tsa[8];
9352 		} dcbx_ets_stats;
9353 		struct fw_dcbx_app_stats_ieee {
9354 			__be32 num_apps_pkd;
9355 			__be32 r6;
9356 			__be32 app[4];
9357 		} dcbx_app_stats;
9358 		struct fw_dcbx_control {
9359 			__be32 multi_peer_invalidated;
9360 			__u8 version;
9361 			__u8 r6[3];
9362 		} dcbx_control;
9363 	} u;
9364 };
9365 
9366 #define S_FW_DCB_IEEE_CMD_PORT		8
9367 #define M_FW_DCB_IEEE_CMD_PORT		0x7
9368 #define V_FW_DCB_IEEE_CMD_PORT(x)	((x) << S_FW_DCB_IEEE_CMD_PORT)
9369 #define G_FW_DCB_IEEE_CMD_PORT(x)	\
9370     (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
9371 
9372 #define S_FW_DCB_IEEE_CMD_FEATURE	2
9373 #define M_FW_DCB_IEEE_CMD_FEATURE	0x7
9374 #define V_FW_DCB_IEEE_CMD_FEATURE(x)	((x) << S_FW_DCB_IEEE_CMD_FEATURE)
9375 #define G_FW_DCB_IEEE_CMD_FEATURE(x)	\
9376     (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
9377 
9378 #define S_FW_DCB_IEEE_CMD_LOCATION	0
9379 #define M_FW_DCB_IEEE_CMD_LOCATION	0x3
9380 #define V_FW_DCB_IEEE_CMD_LOCATION(x)	((x) << S_FW_DCB_IEEE_CMD_LOCATION)
9381 #define G_FW_DCB_IEEE_CMD_LOCATION(x)	\
9382     (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
9383 
9384 #define S_FW_DCB_IEEE_CMD_CHANGED	20
9385 #define M_FW_DCB_IEEE_CMD_CHANGED	0x1
9386 #define V_FW_DCB_IEEE_CMD_CHANGED(x)	((x) << S_FW_DCB_IEEE_CMD_CHANGED)
9387 #define G_FW_DCB_IEEE_CMD_CHANGED(x)	\
9388     (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
9389 #define F_FW_DCB_IEEE_CMD_CHANGED	V_FW_DCB_IEEE_CMD_CHANGED(1U)
9390 
9391 #define S_FW_DCB_IEEE_CMD_RECEIVED	19
9392 #define M_FW_DCB_IEEE_CMD_RECEIVED	0x1
9393 #define V_FW_DCB_IEEE_CMD_RECEIVED(x)	((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
9394 #define G_FW_DCB_IEEE_CMD_RECEIVED(x)	\
9395     (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
9396 #define F_FW_DCB_IEEE_CMD_RECEIVED	V_FW_DCB_IEEE_CMD_RECEIVED(1U)
9397 
9398 #define S_FW_DCB_IEEE_CMD_APPLY		18
9399 #define M_FW_DCB_IEEE_CMD_APPLY		0x1
9400 #define V_FW_DCB_IEEE_CMD_APPLY(x)	((x) << S_FW_DCB_IEEE_CMD_APPLY)
9401 #define G_FW_DCB_IEEE_CMD_APPLY(x)	\
9402     (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
9403 #define F_FW_DCB_IEEE_CMD_APPLY	V_FW_DCB_IEEE_CMD_APPLY(1U)
9404 
9405 #define S_FW_DCB_IEEE_CMD_DISABLED	17
9406 #define M_FW_DCB_IEEE_CMD_DISABLED	0x1
9407 #define V_FW_DCB_IEEE_CMD_DISABLED(x)	((x) << S_FW_DCB_IEEE_CMD_DISABLED)
9408 #define G_FW_DCB_IEEE_CMD_DISABLED(x)	\
9409     (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
9410 #define F_FW_DCB_IEEE_CMD_DISABLED	V_FW_DCB_IEEE_CMD_DISABLED(1U)
9411 
9412 #define S_FW_DCB_IEEE_CMD_MORE		16
9413 #define M_FW_DCB_IEEE_CMD_MORE		0x1
9414 #define V_FW_DCB_IEEE_CMD_MORE(x)	((x) << S_FW_DCB_IEEE_CMD_MORE)
9415 #define G_FW_DCB_IEEE_CMD_MORE(x)	\
9416     (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
9417 #define F_FW_DCB_IEEE_CMD_MORE	V_FW_DCB_IEEE_CMD_MORE(1U)
9418 
9419 #define S_FW_DCB_IEEE_CMD_PFC_MBC	0
9420 #define M_FW_DCB_IEEE_CMD_PFC_MBC	0x1
9421 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
9422 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x)	\
9423     (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
9424 #define F_FW_DCB_IEEE_CMD_PFC_MBC	V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
9425 
9426 #define S_FW_DCB_IEEE_CMD_PFC_WILLING		16
9427 #define M_FW_DCB_IEEE_CMD_PFC_WILLING		0x1
9428 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x)	\
9429     ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
9430 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x)	\
9431     (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
9432 #define F_FW_DCB_IEEE_CMD_PFC_WILLING	V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
9433 
9434 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC	8
9435 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC	0xff
9436 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
9437 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x)	\
9438     (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
9439 
9440 #define S_FW_DCB_IEEE_CMD_PFC_EN	0
9441 #define M_FW_DCB_IEEE_CMD_PFC_EN	0xff
9442 #define V_FW_DCB_IEEE_CMD_PFC_EN(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
9443 #define G_FW_DCB_IEEE_CMD_PFC_EN(x)	\
9444     (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
9445 
9446 #define S_FW_DCB_IEEE_CMD_CBS		16
9447 #define M_FW_DCB_IEEE_CMD_CBS		0x1
9448 #define V_FW_DCB_IEEE_CMD_CBS(x)	((x) << S_FW_DCB_IEEE_CMD_CBS)
9449 #define G_FW_DCB_IEEE_CMD_CBS(x)	\
9450     (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
9451 #define F_FW_DCB_IEEE_CMD_CBS	V_FW_DCB_IEEE_CMD_CBS(1U)
9452 
9453 #define S_FW_DCB_IEEE_CMD_ETS_WILLING		8
9454 #define M_FW_DCB_IEEE_CMD_ETS_WILLING		0x1
9455 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x)	\
9456     ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
9457 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x)	\
9458     (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
9459 #define F_FW_DCB_IEEE_CMD_ETS_WILLING	V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
9460 
9461 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC	0
9462 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC	0xff
9463 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x)	((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9464 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x)	\
9465     (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9466 
9467 #define S_FW_DCB_IEEE_CMD_NUM_APPS	0
9468 #define M_FW_DCB_IEEE_CMD_NUM_APPS	0x7
9469 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x)	((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
9470 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x)	\
9471     (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
9472 
9473 #define S_FW_DCB_IEEE_CMD_MULTI_PEER	31
9474 #define M_FW_DCB_IEEE_CMD_MULTI_PEER	0x1
9475 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x)	((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
9476 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x)	\
9477     (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
9478 #define F_FW_DCB_IEEE_CMD_MULTI_PEER	V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
9479 
9480 #define S_FW_DCB_IEEE_CMD_INVALIDATED		30
9481 #define M_FW_DCB_IEEE_CMD_INVALIDATED		0x1
9482 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x)	\
9483     ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
9484 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x)	\
9485     (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
9486 #define F_FW_DCB_IEEE_CMD_INVALIDATED	V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
9487 
9488 /* Hand-written */
9489 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL	16
9490 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL	0xffff
9491 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)	((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9492 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)	\
9493     (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9494 
9495 #define S_FW_DCB_IEEE_CMD_APP_SELECT	3
9496 #define M_FW_DCB_IEEE_CMD_APP_SELECT	0x7
9497 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x)	((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
9498 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x)	\
9499     (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
9500 
9501 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY	0
9502 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY	0x7
9503 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x)	((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
9504 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x)	\
9505     (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
9506 
9507 
9508 struct fw_error_cmd {
9509 	__be32 op_to_type;
9510 	__be32 len16_pkd;
9511 	union fw_error {
9512 		struct fw_error_exception {
9513 			__be32 info[6];
9514 		} exception;
9515 		struct fw_error_hwmodule {
9516 			__be32 regaddr;
9517 			__be32 regval;
9518 		} hwmodule;
9519 		struct fw_error_wr {
9520 			__be16 cidx;
9521 			__be16 pfn_vfn;
9522 			__be32 eqid;
9523 			__u8   wrhdr[16];
9524 		} wr;
9525 		struct fw_error_acl {
9526 			__be16 cidx;
9527 			__be16 pfn_vfn;
9528 			__be32 eqid;
9529 			__be16 mv_pkd;
9530 			__u8   val[6];
9531 			__be64 r4;
9532 		} acl;
9533 	} u;
9534 };
9535 
9536 #define S_FW_ERROR_CMD_FATAL		4
9537 #define M_FW_ERROR_CMD_FATAL		0x1
9538 #define V_FW_ERROR_CMD_FATAL(x)		((x) << S_FW_ERROR_CMD_FATAL)
9539 #define G_FW_ERROR_CMD_FATAL(x)		\
9540     (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
9541 #define F_FW_ERROR_CMD_FATAL		V_FW_ERROR_CMD_FATAL(1U)
9542 
9543 #define S_FW_ERROR_CMD_TYPE		0
9544 #define M_FW_ERROR_CMD_TYPE		0xf
9545 #define V_FW_ERROR_CMD_TYPE(x)		((x) << S_FW_ERROR_CMD_TYPE)
9546 #define G_FW_ERROR_CMD_TYPE(x)		\
9547     (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
9548 
9549 #define S_FW_ERROR_CMD_PFN		8
9550 #define M_FW_ERROR_CMD_PFN		0x7
9551 #define V_FW_ERROR_CMD_PFN(x)		((x) << S_FW_ERROR_CMD_PFN)
9552 #define G_FW_ERROR_CMD_PFN(x)		\
9553     (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9554 
9555 #define S_FW_ERROR_CMD_VFN		0
9556 #define M_FW_ERROR_CMD_VFN		0xff
9557 #define V_FW_ERROR_CMD_VFN(x)		((x) << S_FW_ERROR_CMD_VFN)
9558 #define G_FW_ERROR_CMD_VFN(x)		\
9559     (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9560 
9561 #define S_FW_ERROR_CMD_PFN		8
9562 #define M_FW_ERROR_CMD_PFN		0x7
9563 #define V_FW_ERROR_CMD_PFN(x)		((x) << S_FW_ERROR_CMD_PFN)
9564 #define G_FW_ERROR_CMD_PFN(x)		\
9565     (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9566 
9567 #define S_FW_ERROR_CMD_VFN		0
9568 #define M_FW_ERROR_CMD_VFN		0xff
9569 #define V_FW_ERROR_CMD_VFN(x)		((x) << S_FW_ERROR_CMD_VFN)
9570 #define G_FW_ERROR_CMD_VFN(x)		\
9571     (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9572 
9573 #define S_FW_ERROR_CMD_MV		15
9574 #define M_FW_ERROR_CMD_MV		0x1
9575 #define V_FW_ERROR_CMD_MV(x)		((x) << S_FW_ERROR_CMD_MV)
9576 #define G_FW_ERROR_CMD_MV(x)		\
9577     (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
9578 #define F_FW_ERROR_CMD_MV		V_FW_ERROR_CMD_MV(1U)
9579 
9580 struct fw_debug_cmd {
9581 	__be32 op_type;
9582 	__be32 len16_pkd;
9583 	union fw_debug {
9584 		struct fw_debug_assert {
9585 			__be32 fcid;
9586 			__be32 line;
9587 			__be32 x;
9588 			__be32 y;
9589 			__u8   filename_0_7[8];
9590 			__u8   filename_8_15[8];
9591 			__be64 r3;
9592 		} assert;
9593 		struct fw_debug_prt {
9594 			__be16 dprtstridx;
9595 			__be16 r3[3];
9596 			__be32 dprtstrparam0;
9597 			__be32 dprtstrparam1;
9598 			__be32 dprtstrparam2;
9599 			__be32 dprtstrparam3;
9600 		} prt;
9601 	} u;
9602 };
9603 
9604 #define S_FW_DEBUG_CMD_TYPE		0
9605 #define M_FW_DEBUG_CMD_TYPE		0xff
9606 #define V_FW_DEBUG_CMD_TYPE(x)		((x) << S_FW_DEBUG_CMD_TYPE)
9607 #define G_FW_DEBUG_CMD_TYPE(x)		\
9608     (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
9609 
9610 enum fw_diag_cmd_type {
9611 	FW_DIAG_CMD_TYPE_OFLDIAG = 0,
9612 };
9613 
9614 enum fw_diag_cmd_ofldiag_op {
9615 	FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
9616 	FW_DIAG_CMD_OFLDIAG_TEST_START,
9617 	FW_DIAG_CMD_OFLDIAG_TEST_STOP,
9618 	FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
9619 };
9620 
9621 enum fw_diag_cmd_ofldiag_status {
9622 	FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
9623 	FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
9624 	FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
9625 	FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
9626 };
9627 
9628 struct fw_diag_cmd {
9629 	__be32 op_type;
9630 	__be32 len16_pkd;
9631 	union fw_diag_test {
9632 		struct fw_diag_test_ofldiag {
9633 			__u8   test_op;
9634 			__u8   r3;
9635 			__be16 test_status;
9636 			__be32 duration;
9637 		} ofldiag;
9638 	} u;
9639 };
9640 
9641 #define S_FW_DIAG_CMD_TYPE		0
9642 #define M_FW_DIAG_CMD_TYPE		0xff
9643 #define V_FW_DIAG_CMD_TYPE(x)		((x) << S_FW_DIAG_CMD_TYPE)
9644 #define G_FW_DIAG_CMD_TYPE(x)		\
9645     (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
9646 
9647 struct fw_hma_cmd {
9648 	__be32 op_pkd;
9649 	__be32 retval_len16;
9650 	__be32 mode_to_pcie_params;
9651 	__be32 naddr_size;
9652 	__be32 addr_size_pkd;
9653 	__be32 r6;
9654 	__be64 phy_address[5];
9655 };
9656 
9657 #define S_FW_HMA_CMD_MODE	31
9658 #define M_FW_HMA_CMD_MODE	0x1
9659 #define V_FW_HMA_CMD_MODE(x)	((x) << S_FW_HMA_CMD_MODE)
9660 #define G_FW_HMA_CMD_MODE(x)	\
9661     (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)
9662 #define F_FW_HMA_CMD_MODE	V_FW_HMA_CMD_MODE(1U)
9663 
9664 #define S_FW_HMA_CMD_SOC	30
9665 #define M_FW_HMA_CMD_SOC	0x1
9666 #define V_FW_HMA_CMD_SOC(x)	((x) << S_FW_HMA_CMD_SOC)
9667 #define G_FW_HMA_CMD_SOC(x)	(((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)
9668 #define F_FW_HMA_CMD_SOC	V_FW_HMA_CMD_SOC(1U)
9669 
9670 #define S_FW_HMA_CMD_EOC	29
9671 #define M_FW_HMA_CMD_EOC	0x1
9672 #define V_FW_HMA_CMD_EOC(x)	((x) << S_FW_HMA_CMD_EOC)
9673 #define G_FW_HMA_CMD_EOC(x)	(((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)
9674 #define F_FW_HMA_CMD_EOC	V_FW_HMA_CMD_EOC(1U)
9675 
9676 #define S_FW_HMA_CMD_PCIE_PARAMS	0
9677 #define M_FW_HMA_CMD_PCIE_PARAMS	0x7ffffff
9678 #define V_FW_HMA_CMD_PCIE_PARAMS(x)	((x) << S_FW_HMA_CMD_PCIE_PARAMS)
9679 #define G_FW_HMA_CMD_PCIE_PARAMS(x)	\
9680     (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)
9681 
9682 #define S_FW_HMA_CMD_NADDR	12
9683 #define M_FW_HMA_CMD_NADDR	0x3f
9684 #define V_FW_HMA_CMD_NADDR(x)	((x) << S_FW_HMA_CMD_NADDR)
9685 #define G_FW_HMA_CMD_NADDR(x)	\
9686     (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)
9687 
9688 #define S_FW_HMA_CMD_SIZE	0
9689 #define M_FW_HMA_CMD_SIZE	0xfff
9690 #define V_FW_HMA_CMD_SIZE(x)	((x) << S_FW_HMA_CMD_SIZE)
9691 #define G_FW_HMA_CMD_SIZE(x)	\
9692     (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)
9693 
9694 #define S_FW_HMA_CMD_ADDR_SIZE		11
9695 #define M_FW_HMA_CMD_ADDR_SIZE		0x1fffff
9696 #define V_FW_HMA_CMD_ADDR_SIZE(x)	((x) << S_FW_HMA_CMD_ADDR_SIZE)
9697 #define G_FW_HMA_CMD_ADDR_SIZE(x)	\
9698     (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
9699 
9700 /******************************************************************************
9701  *   P C I E   F W   R E G I S T E R
9702  **************************************/
9703 
9704 enum pcie_fw_eval {
9705 	PCIE_FW_EVAL_CRASH		= 0,
9706 	PCIE_FW_EVAL_PREP		= 1,
9707 	PCIE_FW_EVAL_CONF		= 2,
9708 	PCIE_FW_EVAL_INIT		= 3,
9709 	PCIE_FW_EVAL_UNEXPECTEDEVENT	= 4,
9710 	PCIE_FW_EVAL_OVERHEAT		= 5,
9711 	PCIE_FW_EVAL_DEVICESHUTDOWN	= 6,
9712 };
9713 
9714 /**
9715  *	Register definitions for the PCIE_FW register which the firmware uses
9716  *	to retain status across RESETs.  This register should be considered
9717  *	as a READ-ONLY register for Host Software and only to be used to
9718  *	track firmware initialization/error state, etc.
9719  */
9720 #define S_PCIE_FW_ERR		31
9721 #define M_PCIE_FW_ERR		0x1
9722 #define V_PCIE_FW_ERR(x)	((x) << S_PCIE_FW_ERR)
9723 #define G_PCIE_FW_ERR(x)	(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
9724 #define F_PCIE_FW_ERR		V_PCIE_FW_ERR(1U)
9725 
9726 #define S_PCIE_FW_INIT		30
9727 #define M_PCIE_FW_INIT		0x1
9728 #define V_PCIE_FW_INIT(x)	((x) << S_PCIE_FW_INIT)
9729 #define G_PCIE_FW_INIT(x)	(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
9730 #define F_PCIE_FW_INIT		V_PCIE_FW_INIT(1U)
9731 
9732 #define S_PCIE_FW_HALT          29
9733 #define M_PCIE_FW_HALT          0x1
9734 #define V_PCIE_FW_HALT(x)       ((x) << S_PCIE_FW_HALT)
9735 #define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
9736 #define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)
9737 
9738 #define S_PCIE_FW_EVAL		24
9739 #define M_PCIE_FW_EVAL		0x7
9740 #define V_PCIE_FW_EVAL(x)	((x) << S_PCIE_FW_EVAL)
9741 #define G_PCIE_FW_EVAL(x)	(((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
9742 
9743 #define S_PCIE_FW_STAGE		21
9744 #define M_PCIE_FW_STAGE		0x7
9745 #define V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
9746 #define G_PCIE_FW_STAGE(x)	(((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
9747 
9748 #define S_PCIE_FW_ASYNCNOT_VLD	20
9749 #define M_PCIE_FW_ASYNCNOT_VLD	0x1
9750 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
9751     ((x) << S_PCIE_FW_ASYNCNOT_VLD)
9752 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
9753     (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
9754 #define F_PCIE_FW_ASYNCNOT_VLD	V_PCIE_FW_ASYNCNOT_VLD(1U)
9755 
9756 #define S_PCIE_FW_ASYNCNOTINT	19
9757 #define M_PCIE_FW_ASYNCNOTINT	0x1
9758 #define V_PCIE_FW_ASYNCNOTINT(x) \
9759     ((x) << S_PCIE_FW_ASYNCNOTINT)
9760 #define G_PCIE_FW_ASYNCNOTINT(x) \
9761     (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
9762 #define F_PCIE_FW_ASYNCNOTINT	V_PCIE_FW_ASYNCNOTINT(1U)
9763 
9764 #define S_PCIE_FW_ASYNCNOT	16
9765 #define M_PCIE_FW_ASYNCNOT	0x7
9766 #define V_PCIE_FW_ASYNCNOT(x)	((x) << S_PCIE_FW_ASYNCNOT)
9767 #define G_PCIE_FW_ASYNCNOT(x)	\
9768     (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
9769 
9770 #define S_PCIE_FW_MASTER_VLD	15
9771 #define M_PCIE_FW_MASTER_VLD	0x1
9772 #define V_PCIE_FW_MASTER_VLD(x)	((x) << S_PCIE_FW_MASTER_VLD)
9773 #define G_PCIE_FW_MASTER_VLD(x)	\
9774     (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
9775 #define F_PCIE_FW_MASTER_VLD	V_PCIE_FW_MASTER_VLD(1U)
9776 
9777 #define S_PCIE_FW_MASTER	12
9778 #define M_PCIE_FW_MASTER	0x7
9779 #define V_PCIE_FW_MASTER(x)	((x) << S_PCIE_FW_MASTER)
9780 #define G_PCIE_FW_MASTER(x)	(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
9781 
9782 #define S_PCIE_FW_RESET_VLD		11
9783 #define M_PCIE_FW_RESET_VLD		0x1
9784 #define V_PCIE_FW_RESET_VLD(x)	((x) << S_PCIE_FW_RESET_VLD)
9785 #define G_PCIE_FW_RESET_VLD(x)	\
9786     (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
9787 #define F_PCIE_FW_RESET_VLD	V_PCIE_FW_RESET_VLD(1U)
9788 
9789 #define S_PCIE_FW_RESET		8
9790 #define M_PCIE_FW_RESET		0x7
9791 #define V_PCIE_FW_RESET(x)	((x) << S_PCIE_FW_RESET)
9792 #define G_PCIE_FW_RESET(x)	\
9793     (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
9794 
9795 #define S_PCIE_FW_REGISTERED	0
9796 #define M_PCIE_FW_REGISTERED	0xff
9797 #define V_PCIE_FW_REGISTERED(x)	((x) << S_PCIE_FW_REGISTERED)
9798 #define G_PCIE_FW_REGISTERED(x)	\
9799     (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
9800 
9801 
9802 /******************************************************************************
9803  *   P C I E   F W   P F 0   R E G I S T E R
9804  **********************************************/
9805 
9806 /*
9807  *	this register is available as 32-bit of persistent storage (accross
9808  *	PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
9809  *	will not write it)
9810  */
9811 
9812 
9813 /******************************************************************************
9814  *   P C I E   F W   P F 7   R E G I S T E R
9815  **********************************************/
9816 
9817 /*
9818  * PF7 stores the Firmware Device Log parameters which allows Host Drivers to
9819  * access the "devlog" which needing to contact firmware.  The encoding is
9820  * mostly the same as that returned by the DEVLOG command except for the size
9821  * which is encoded as the number of entries in multiples-1 of 128 here rather
9822  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
9823  * and 15 means 2048.  This of course in turn constrains the allowed values
9824  * for the devlog size ...
9825  */
9826 #define PCIE_FW_PF_DEVLOG		7
9827 
9828 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128	28
9829 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128	0xf
9830 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9831 	((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
9832 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9833 	(((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
9834 	 M_PCIE_FW_PF_DEVLOG_NENTRIES128)
9835 
9836 #define S_PCIE_FW_PF_DEVLOG_ADDR16	4
9837 #define M_PCIE_FW_PF_DEVLOG_ADDR16	0xffffff
9838 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x)	((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
9839 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
9840 	(((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
9841 
9842 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE	0
9843 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE	0xf
9844 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x)	((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
9845 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
9846 	(((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
9847 
9848 
9849 /******************************************************************************
9850  *   B I N A R Y   H E A D E R   F O R M A T
9851  **********************************************/
9852 
9853 /*
9854  *	firmware binary header format
9855  */
9856 struct fw_hdr {
9857 	__u8	ver;
9858 	__u8	chip;			/* terminator chip family */
9859 	__be16	len512;			/* bin length in units of 512-bytes */
9860 	__be32	fw_ver;			/* firmware version */
9861 	__be32	tp_microcode_ver;	/* tcp processor microcode version */
9862 	__u8	intfver_nic;
9863 	__u8	intfver_vnic;
9864 	__u8	intfver_ofld;
9865 	__u8	intfver_ri;
9866 	__u8	intfver_iscsipdu;
9867 	__u8	intfver_iscsi;
9868 	__u8	intfver_fcoepdu;
9869 	__u8	intfver_fcoe;
9870 	__u32	reserved2;
9871 	__u32	reserved3;
9872 	__be32	magic;			/* runtime or bootstrap fw */
9873 	__be32	flags;
9874 	__be32	reserved6[23];
9875 };
9876 
9877 enum fw_hdr_chip {
9878 	FW_HDR_CHIP_T4,
9879 	FW_HDR_CHIP_T5,
9880 	FW_HDR_CHIP_T6
9881 };
9882 
9883 #define S_FW_HDR_FW_VER_MAJOR	24
9884 #define M_FW_HDR_FW_VER_MAJOR	0xff
9885 #define V_FW_HDR_FW_VER_MAJOR(x) \
9886     ((x) << S_FW_HDR_FW_VER_MAJOR)
9887 #define G_FW_HDR_FW_VER_MAJOR(x) \
9888     (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
9889 
9890 #define S_FW_HDR_FW_VER_MINOR	16
9891 #define M_FW_HDR_FW_VER_MINOR	0xff
9892 #define V_FW_HDR_FW_VER_MINOR(x) \
9893     ((x) << S_FW_HDR_FW_VER_MINOR)
9894 #define G_FW_HDR_FW_VER_MINOR(x) \
9895     (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
9896 
9897 #define S_FW_HDR_FW_VER_MICRO	8
9898 #define M_FW_HDR_FW_VER_MICRO	0xff
9899 #define V_FW_HDR_FW_VER_MICRO(x) \
9900     ((x) << S_FW_HDR_FW_VER_MICRO)
9901 #define G_FW_HDR_FW_VER_MICRO(x) \
9902     (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
9903 
9904 #define S_FW_HDR_FW_VER_BUILD	0
9905 #define M_FW_HDR_FW_VER_BUILD	0xff
9906 #define V_FW_HDR_FW_VER_BUILD(x) \
9907     ((x) << S_FW_HDR_FW_VER_BUILD)
9908 #define G_FW_HDR_FW_VER_BUILD(x) \
9909     (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
9910 
9911 enum {
9912 	/* T4
9913 	 */
9914 	FW_HDR_INTFVER_NIC	= 0x00,
9915 	FW_HDR_INTFVER_VNIC	= 0x00,
9916 	FW_HDR_INTFVER_OFLD	= 0x00,
9917 	FW_HDR_INTFVER_RI	= 0x00,
9918 	FW_HDR_INTFVER_ISCSIPDU	= 0x00,
9919 	FW_HDR_INTFVER_ISCSI	= 0x00,
9920 	FW_HDR_INTFVER_FCOEPDU  = 0x00,
9921 	FW_HDR_INTFVER_FCOE	= 0x00,
9922 
9923 	/* T5
9924 	 */
9925 	T5FW_HDR_INTFVER_NIC	= 0x00,
9926 	T5FW_HDR_INTFVER_VNIC	= 0x00,
9927 	T5FW_HDR_INTFVER_OFLD	= 0x00,
9928 	T5FW_HDR_INTFVER_RI	= 0x00,
9929 	T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
9930 	T5FW_HDR_INTFVER_ISCSI	= 0x00,
9931 	T5FW_HDR_INTFVER_FCOEPDU= 0x00,
9932 	T5FW_HDR_INTFVER_FCOE	= 0x00,
9933 
9934 	/* T6
9935 	 */
9936 	T6FW_HDR_INTFVER_NIC	= 0x00,
9937 	T6FW_HDR_INTFVER_VNIC	= 0x00,
9938 	T6FW_HDR_INTFVER_OFLD	= 0x00,
9939 	T6FW_HDR_INTFVER_RI	= 0x00,
9940 	T6FW_HDR_INTFVER_ISCSIPDU= 0x00,
9941 	T6FW_HDR_INTFVER_ISCSI	= 0x00,
9942 	T6FW_HDR_INTFVER_FCOEPDU= 0x00,
9943 	T6FW_HDR_INTFVER_FCOE	= 0x00,
9944 };
9945 
9946 enum {
9947 	FW_HDR_MAGIC_RUNTIME	= 0x00000000,
9948 	FW_HDR_MAGIC_BOOTSTRAP	= 0x626f6f74,
9949 };
9950 
9951 enum fw_hdr_flags {
9952 	FW_HDR_FLAGS_RESET_HALT	= 0x00000001,
9953 };
9954 
9955 /*
9956  *	External PHY firmware binary header format
9957  */
9958 struct fw_ephy_hdr {
9959 	__u8	ver;
9960 	__u8	reserved;
9961 	__be16	len512;			/* bin length in units of 512-bytes */
9962 	__be32	magic;
9963 
9964 	__be16	vendor_id;
9965 	__be16	device_id;
9966 	__be32	version;
9967 
9968 	__be32	reserved1[4];
9969 };
9970 
9971 enum {
9972 	FW_EPHY_HDR_MAGIC	= 0x65706879,
9973 };
9974 
9975 struct fw_ifconf_dhcp_info {
9976 	__be32		addr;
9977 	__be32		mask;
9978 	__be16		vlanid;
9979 	__be16		mtu;
9980 	__be32		gw;
9981 	__u8		op;
9982 	__u8		len;
9983 	__u8		data[270];
9984 };
9985 
9986 struct fw_ifconf_ping_info {
9987 	__be16		ping_pldsize;
9988 };
9989 
9990 #endif /* _T4FW_INTERFACE_H_ */
9991