156b2bdd1SGireesh Nagabhushana /* 256b2bdd1SGireesh Nagabhushana * This file and its contents are supplied under the terms of the 356b2bdd1SGireesh Nagabhushana * Common Development and Distribution License ("CDDL"), version 1.0. 456b2bdd1SGireesh Nagabhushana * You may only use this file in accordance with the terms of version 556b2bdd1SGireesh Nagabhushana * 1.0 of the CDDL. 656b2bdd1SGireesh Nagabhushana * 756b2bdd1SGireesh Nagabhushana * A full copy of the text of the CDDL should have accompanied this 856b2bdd1SGireesh Nagabhushana * source. A copy of the CDDL is also available via the Internet at 956b2bdd1SGireesh Nagabhushana * http://www.illumos.org/license/CDDL. 1056b2bdd1SGireesh Nagabhushana */ 1156b2bdd1SGireesh Nagabhushana 1256b2bdd1SGireesh Nagabhushana /* 1356b2bdd1SGireesh Nagabhushana * Chelsio Terminator 4 (T4) Firmware interface header file. 1456b2bdd1SGireesh Nagabhushana * 1556b2bdd1SGireesh Nagabhushana * Copyright (C) 2009-2013 Chelsio Communications. All rights reserved. 1656b2bdd1SGireesh Nagabhushana * 1756b2bdd1SGireesh Nagabhushana * Written by felix marti (felix@chelsio.com) 1856b2bdd1SGireesh Nagabhushana * 1956b2bdd1SGireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT 2056b2bdd1SGireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 2156b2bdd1SGireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 2256b2bdd1SGireesh Nagabhushana * release for licensing terms and conditions. 2356b2bdd1SGireesh Nagabhushana */ 2456b2bdd1SGireesh Nagabhushana #ifndef _T4FW_INTERFACE_H_ 2556b2bdd1SGireesh Nagabhushana #define _T4FW_INTERFACE_H_ 2656b2bdd1SGireesh Nagabhushana 2756b2bdd1SGireesh Nagabhushana /* 2856b2bdd1SGireesh Nagabhushana * ****************************** 2956b2bdd1SGireesh Nagabhushana * R E T U R N V A L U E S 3056b2bdd1SGireesh Nagabhushana * ****************************** 3156b2bdd1SGireesh Nagabhushana */ 3256b2bdd1SGireesh Nagabhushana 3356b2bdd1SGireesh Nagabhushana enum fw_retval { 3456b2bdd1SGireesh Nagabhushana FW_SUCCESS = 0, /* completed sucessfully */ 3556b2bdd1SGireesh Nagabhushana FW_EPERM = 1, /* operation not permitted */ 3656b2bdd1SGireesh Nagabhushana FW_ENOENT = 2, /* no such file or directory */ 3756b2bdd1SGireesh Nagabhushana FW_EIO = 5, /* input/output error; hw bad */ 3856b2bdd1SGireesh Nagabhushana FW_ENOEXEC = 8, /* exec format error; inv microcode */ 3956b2bdd1SGireesh Nagabhushana FW_EAGAIN = 11, /* try again */ 4056b2bdd1SGireesh Nagabhushana FW_ENOMEM = 12, /* out of memory */ 4156b2bdd1SGireesh Nagabhushana FW_EFAULT = 14, /* bad address; fw bad */ 4256b2bdd1SGireesh Nagabhushana FW_EBUSY = 16, /* resource busy */ 4356b2bdd1SGireesh Nagabhushana FW_EEXIST = 17, /* file exists */ 44*de483253SVishal Kulkarni FW_ENODEV = 19, /* no such device */ 4556b2bdd1SGireesh Nagabhushana FW_EINVAL = 22, /* invalid argument */ 4656b2bdd1SGireesh Nagabhushana FW_ENOSPC = 28, /* no space left on device */ 4756b2bdd1SGireesh Nagabhushana FW_ENOSYS = 38, /* functionality not implemented */ 48*de483253SVishal Kulkarni FW_ENODATA = 61, /* no data available */ 4956b2bdd1SGireesh Nagabhushana FW_EPROTO = 71, /* protocol error */ 5056b2bdd1SGireesh Nagabhushana FW_EADDRINUSE = 98, /* address already in use */ 5156b2bdd1SGireesh Nagabhushana FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 5256b2bdd1SGireesh Nagabhushana FW_ENETDOWN = 100, /* network is down */ 5356b2bdd1SGireesh Nagabhushana FW_ENETUNREACH = 101, /* network is unreachable */ 5456b2bdd1SGireesh Nagabhushana FW_ENOBUFS = 105, /* no buffer space available */ 5556b2bdd1SGireesh Nagabhushana FW_ETIMEDOUT = 110, /* timeout */ 5656b2bdd1SGireesh Nagabhushana FW_EINPROGRESS = 115, /* fw internal */ 5756b2bdd1SGireesh Nagabhushana FW_SCSI_ABORT_REQUESTED = 128, /* */ 5856b2bdd1SGireesh Nagabhushana FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 5956b2bdd1SGireesh Nagabhushana FW_SCSI_ABORTED = 130, /* */ 6056b2bdd1SGireesh Nagabhushana FW_SCSI_CLOSE_REQUESTED = 131, /* */ 6156b2bdd1SGireesh Nagabhushana FW_ERR_LINK_DOWN = 132, /* */ 6256b2bdd1SGireesh Nagabhushana FW_RDEV_NOT_READY = 133, /* */ 6356b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_LOST = 134, /* */ 6456b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_LOGO = 135, /* */ 6556b2bdd1SGireesh Nagabhushana FW_FCOE_NO_XCHG = 136, /* */ 6656b2bdd1SGireesh Nagabhushana FW_SCSI_RSP_ERR = 137, /* */ 6756b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 6856b2bdd1SGireesh Nagabhushana FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 6956b2bdd1SGireesh Nagabhushana FW_SCSI_OVER_FLOW_ERR = 140, /* */ 7056b2bdd1SGireesh Nagabhushana FW_SCSI_DDP_ERR = 141, /* DDP error */ 7156b2bdd1SGireesh Nagabhushana FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 7256b2bdd1SGireesh Nagabhushana }; 7356b2bdd1SGireesh Nagabhushana 7456b2bdd1SGireesh Nagabhushana /* 7556b2bdd1SGireesh Nagabhushana * ****************************** 7656b2bdd1SGireesh Nagabhushana * W O R K R E Q U E S T s 7756b2bdd1SGireesh Nagabhushana * ****************************** 7856b2bdd1SGireesh Nagabhushana */ 7956b2bdd1SGireesh Nagabhushana 8056b2bdd1SGireesh Nagabhushana enum fw_wr_opcodes { 81*de483253SVishal Kulkarni FW_FRAG_WR = 0x1d, 8256b2bdd1SGireesh Nagabhushana FW_FILTER_WR = 0x02, 8356b2bdd1SGireesh Nagabhushana FW_ULPTX_WR = 0x04, 8456b2bdd1SGireesh Nagabhushana FW_TP_WR = 0x05, 8556b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKT_WR = 0x08, 86*de483253SVishal Kulkarni FW_ETH_TX_PKT2_WR = 0x44, 8756b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKTS_WR = 0x09, 8856b2bdd1SGireesh Nagabhushana FW_ETH_TX_UO_WR = 0x1c, 8956b2bdd1SGireesh Nagabhushana FW_EQ_FLUSH_WR = 0x1b, 9056b2bdd1SGireesh Nagabhushana FW_OFLD_CONNECTION_WR = 0x2f, 9156b2bdd1SGireesh Nagabhushana FW_FLOWC_WR = 0x0a, 9256b2bdd1SGireesh Nagabhushana FW_OFLD_TX_DATA_WR = 0x0b, 9356b2bdd1SGireesh Nagabhushana FW_CMD_WR = 0x10, 9456b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKT_VM_WR = 0x11, 9556b2bdd1SGireesh Nagabhushana FW_RI_RES_WR = 0x0c, 9656b2bdd1SGireesh Nagabhushana FW_RI_RDMA_WRITE_WR = 0x14, 9756b2bdd1SGireesh Nagabhushana FW_RI_SEND_WR = 0x15, 9856b2bdd1SGireesh Nagabhushana FW_RI_RDMA_READ_WR = 0x16, 9956b2bdd1SGireesh Nagabhushana FW_RI_RECV_WR = 0x17, 10056b2bdd1SGireesh Nagabhushana FW_RI_BIND_MW_WR = 0x18, 10156b2bdd1SGireesh Nagabhushana FW_RI_FR_NSMR_WR = 0x19, 10256b2bdd1SGireesh Nagabhushana FW_RI_INV_LSTAG_WR = 0x1a, 10356b2bdd1SGireesh Nagabhushana FW_RI_SEND_IMMEDIATE_WR = 0x15, 10456b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_WR = 0x16, 10556b2bdd1SGireesh Nagabhushana FW_RI_WR = 0x0d, 10656b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR = 0x6b, 10756b2bdd1SGireesh Nagabhushana FW_RDEV_WR = 0x38, 10856b2bdd1SGireesh Nagabhushana FW_FOISCSI_NODE_WR = 0x60, 10956b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_WR = 0x6a, 11056b2bdd1SGireesh Nagabhushana FW_FOISCSI_CHAP_WR = 0x6c, 11156b2bdd1SGireesh Nagabhushana FW_FCOE_ELS_CT_WR = 0x30, 11256b2bdd1SGireesh Nagabhushana FW_SCSI_WRITE_WR = 0x31, 11356b2bdd1SGireesh Nagabhushana FW_SCSI_READ_WR = 0x32, 11456b2bdd1SGireesh Nagabhushana FW_SCSI_CMD_WR = 0x33, 11556b2bdd1SGireesh Nagabhushana FW_SCSI_ABRT_CLS_WR = 0x34, 11656b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_ACC_WR = 0x35, 11756b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_XMIT_WR = 0x36, 11856b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_RSP_WR = 0x37, 119*de483253SVishal Kulkarni FW_POFCOE_TCB_WR = 0x42, 120*de483253SVishal Kulkarni FW_POFCOE_ULPTX_WR = 0x43, 12156b2bdd1SGireesh Nagabhushana FW_LASTC2E_WR = 0x70 12256b2bdd1SGireesh Nagabhushana }; 12356b2bdd1SGireesh Nagabhushana 12456b2bdd1SGireesh Nagabhushana /* 12556b2bdd1SGireesh Nagabhushana * Generic work request header flit0 12656b2bdd1SGireesh Nagabhushana */ 12756b2bdd1SGireesh Nagabhushana struct fw_wr_hdr { 12856b2bdd1SGireesh Nagabhushana __be32 hi; 12956b2bdd1SGireesh Nagabhushana __be32 lo; 13056b2bdd1SGireesh Nagabhushana }; 13156b2bdd1SGireesh Nagabhushana 13256b2bdd1SGireesh Nagabhushana /* work request opcode (hi) */ 13356b2bdd1SGireesh Nagabhushana #define S_FW_WR_OP 24 13456b2bdd1SGireesh Nagabhushana #define M_FW_WR_OP 0xff 13556b2bdd1SGireesh Nagabhushana #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 13656b2bdd1SGireesh Nagabhushana #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 13756b2bdd1SGireesh Nagabhushana 13856b2bdd1SGireesh Nagabhushana /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 13956b2bdd1SGireesh Nagabhushana #define S_FW_WR_ATOMIC 23 14056b2bdd1SGireesh Nagabhushana #define M_FW_WR_ATOMIC 0x1 14156b2bdd1SGireesh Nagabhushana #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 14256b2bdd1SGireesh Nagabhushana #define G_FW_WR_ATOMIC(x) \ 14356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 14456b2bdd1SGireesh Nagabhushana #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 14556b2bdd1SGireesh Nagabhushana 14656b2bdd1SGireesh Nagabhushana /* 14756b2bdd1SGireesh Nagabhushana * flush flag (hi) - firmware flushes flushable work request buffered 14856b2bdd1SGireesh Nagabhushana * in the flow context. 14956b2bdd1SGireesh Nagabhushana */ 15056b2bdd1SGireesh Nagabhushana #define S_FW_WR_FLUSH 22 15156b2bdd1SGireesh Nagabhushana #define M_FW_WR_FLUSH 0x1 15256b2bdd1SGireesh Nagabhushana #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 15356b2bdd1SGireesh Nagabhushana #define G_FW_WR_FLUSH(x) \ 15456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 15556b2bdd1SGireesh Nagabhushana #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 15656b2bdd1SGireesh Nagabhushana 15756b2bdd1SGireesh Nagabhushana /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 15856b2bdd1SGireesh Nagabhushana #define S_FW_WR_COMPL 21 15956b2bdd1SGireesh Nagabhushana #define M_FW_WR_COMPL 0x1 16056b2bdd1SGireesh Nagabhushana #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 16156b2bdd1SGireesh Nagabhushana #define G_FW_WR_COMPL(x) \ 16256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 16356b2bdd1SGireesh Nagabhushana #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 16456b2bdd1SGireesh Nagabhushana 16556b2bdd1SGireesh Nagabhushana /* work request immediate data lengh (hi) */ 16656b2bdd1SGireesh Nagabhushana #define S_FW_WR_IMMDLEN 0 16756b2bdd1SGireesh Nagabhushana #define M_FW_WR_IMMDLEN 0xff 16856b2bdd1SGireesh Nagabhushana #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 16956b2bdd1SGireesh Nagabhushana #define G_FW_WR_IMMDLEN(x) \ 17056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 17156b2bdd1SGireesh Nagabhushana 17256b2bdd1SGireesh Nagabhushana /* egress queue status update to associated ingress queue entry (lo) */ 17356b2bdd1SGireesh Nagabhushana #define S_FW_WR_EQUIQ 31 17456b2bdd1SGireesh Nagabhushana #define M_FW_WR_EQUIQ 0x1 17556b2bdd1SGireesh Nagabhushana #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 17656b2bdd1SGireesh Nagabhushana #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 17756b2bdd1SGireesh Nagabhushana #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 17856b2bdd1SGireesh Nagabhushana 17956b2bdd1SGireesh Nagabhushana /* egress queue status update to egress queue status entry (lo) */ 18056b2bdd1SGireesh Nagabhushana #define S_FW_WR_EQUEQ 30 18156b2bdd1SGireesh Nagabhushana #define M_FW_WR_EQUEQ 0x1 18256b2bdd1SGireesh Nagabhushana #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 18356b2bdd1SGireesh Nagabhushana #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 18456b2bdd1SGireesh Nagabhushana #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 18556b2bdd1SGireesh Nagabhushana 18656b2bdd1SGireesh Nagabhushana /* flow context identifier (lo) */ 18756b2bdd1SGireesh Nagabhushana #define S_FW_WR_FLOWID 8 18856b2bdd1SGireesh Nagabhushana #define M_FW_WR_FLOWID 0xfffff 18956b2bdd1SGireesh Nagabhushana #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 19056b2bdd1SGireesh Nagabhushana #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 19156b2bdd1SGireesh Nagabhushana 19256b2bdd1SGireesh Nagabhushana /* length in units of 16-bytes (lo) */ 19356b2bdd1SGireesh Nagabhushana #define S_FW_WR_LEN16 0 19456b2bdd1SGireesh Nagabhushana #define M_FW_WR_LEN16 0xff 19556b2bdd1SGireesh Nagabhushana #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 19656b2bdd1SGireesh Nagabhushana #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 19756b2bdd1SGireesh Nagabhushana 198*de483253SVishal Kulkarni struct fw_frag_wr { 199*de483253SVishal Kulkarni __be32 op_to_fragoff16; 200*de483253SVishal Kulkarni __be32 flowid_len16; 201*de483253SVishal Kulkarni __be64 r4; 202*de483253SVishal Kulkarni }; 203*de483253SVishal Kulkarni 204*de483253SVishal Kulkarni #define S_FW_FRAG_WR_EOF 15 205*de483253SVishal Kulkarni #define M_FW_FRAG_WR_EOF 0x1 206*de483253SVishal Kulkarni #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 207*de483253SVishal Kulkarni #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 208*de483253SVishal Kulkarni #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 209*de483253SVishal Kulkarni 210*de483253SVishal Kulkarni #define S_FW_FRAG_WR_FRAGOFF16 8 211*de483253SVishal Kulkarni #define M_FW_FRAG_WR_FRAGOFF16 0x7f 212*de483253SVishal Kulkarni #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 213*de483253SVishal Kulkarni #define G_FW_FRAG_WR_FRAGOFF16(x) \ 214*de483253SVishal Kulkarni (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 215*de483253SVishal Kulkarni 21656b2bdd1SGireesh Nagabhushana /* 21756b2bdd1SGireesh Nagabhushana * valid filter configurations for compressed tuple 21856b2bdd1SGireesh Nagabhushana * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 21956b2bdd1SGireesh Nagabhushana * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 22056b2bdd1SGireesh Nagabhushana * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 22156b2bdd1SGireesh Nagabhushana * OV - Outer VLAN/VNIC_ID, 22256b2bdd1SGireesh Nagabhushana */ 22356b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 22456b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 22556b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 22656b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_M_OV_P_FC 0x387 22756b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_E_PR_T 0x370 22856b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_E_PR_P_FC 0X363 22956b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_E_T_P_FC 0X353 23056b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 23156b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 23256b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 23356b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_MT_T_OV_P_FC 0X317 23456b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_M_E_PR_FC 0X2E1 23556b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_M_E_T_FC 0X2D1 23656b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_M_PR_IV_FC 0X2A9 23756b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_M_PR_OV_FC 0X2A5 23856b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_M_T_IV_FC 0X299 23956b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_M_T_OV_FC 0X295 24056b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_E_PR_T_P 0X272 24156b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_E_PR_T_FC 0X271 24256b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_E_IV_FC 0X249 24356b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_E_OV_FC 0X245 24456b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_PR_T_IV_FC 0X239 24556b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_PR_T_OV_FC 0X235 24656b2bdd1SGireesh Nagabhushana #define HW_TPL_FR_IV_OV_FC 0X20D 24756b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_M_E_PR 0X1E0 24856b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_M_E_T 0X1D0 24956b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_E_PR_T_FC 0X171 25056b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_E_IV 0X148 25156b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_E_OV 0X144 25256b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_PR_T_IV 0X138 25356b2bdd1SGireesh Nagabhushana #define HW_TPL_MT_PR_T_OV 0X134 25456b2bdd1SGireesh Nagabhushana #define HW_TPL_M_E_PR_P 0X0E2 25556b2bdd1SGireesh Nagabhushana #define HW_TPL_M_E_T_P 0X0D2 25656b2bdd1SGireesh Nagabhushana #define HW_TPL_E_PR_T_P_FC 0X073 25756b2bdd1SGireesh Nagabhushana #define HW_TPL_E_IV_P 0X04A 25856b2bdd1SGireesh Nagabhushana #define HW_TPL_E_OV_P 0X046 25956b2bdd1SGireesh Nagabhushana #define HW_TPL_PR_T_IV_P 0X03A 26056b2bdd1SGireesh Nagabhushana #define HW_TPL_PR_T_OV_P 0X036 26156b2bdd1SGireesh Nagabhushana 26256b2bdd1SGireesh Nagabhushana /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 26356b2bdd1SGireesh Nagabhushana enum fw_filter_wr_cookie { 26456b2bdd1SGireesh Nagabhushana FW_FILTER_WR_SUCCESS, 26556b2bdd1SGireesh Nagabhushana FW_FILTER_WR_FLT_ADDED, 26656b2bdd1SGireesh Nagabhushana FW_FILTER_WR_FLT_DELETED, 26756b2bdd1SGireesh Nagabhushana FW_FILTER_WR_SMT_TBL_FULL, 26856b2bdd1SGireesh Nagabhushana FW_FILTER_WR_EINVAL, 26956b2bdd1SGireesh Nagabhushana }; 27056b2bdd1SGireesh Nagabhushana 27156b2bdd1SGireesh Nagabhushana struct fw_filter_wr { 27256b2bdd1SGireesh Nagabhushana __be32 op_pkd; 27356b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 27456b2bdd1SGireesh Nagabhushana __be64 r3; 27556b2bdd1SGireesh Nagabhushana __be32 tid_to_iq; 27656b2bdd1SGireesh Nagabhushana __be32 del_filter_to_l2tix; 27756b2bdd1SGireesh Nagabhushana __be16 ethtype; 27856b2bdd1SGireesh Nagabhushana __be16 ethtypem; 27956b2bdd1SGireesh Nagabhushana __u8 frag_to_ovlan_vldm; 28056b2bdd1SGireesh Nagabhushana __u8 smac_sel; 28156b2bdd1SGireesh Nagabhushana __be16 rx_chan_rx_rpl_iq; 28256b2bdd1SGireesh Nagabhushana __be32 maci_to_matchtypem; 28356b2bdd1SGireesh Nagabhushana __u8 ptcl; 28456b2bdd1SGireesh Nagabhushana __u8 ptclm; 28556b2bdd1SGireesh Nagabhushana __u8 ttyp; 28656b2bdd1SGireesh Nagabhushana __u8 ttypm; 28756b2bdd1SGireesh Nagabhushana __be16 ivlan; 28856b2bdd1SGireesh Nagabhushana __be16 ivlanm; 28956b2bdd1SGireesh Nagabhushana __be16 ovlan; 29056b2bdd1SGireesh Nagabhushana __be16 ovlanm; 29156b2bdd1SGireesh Nagabhushana __u8 lip[16]; 29256b2bdd1SGireesh Nagabhushana __u8 lipm[16]; 29356b2bdd1SGireesh Nagabhushana __u8 fip[16]; 29456b2bdd1SGireesh Nagabhushana __u8 fipm[16]; 29556b2bdd1SGireesh Nagabhushana __be16 lp; 29656b2bdd1SGireesh Nagabhushana __be16 lpm; 29756b2bdd1SGireesh Nagabhushana __be16 fp; 29856b2bdd1SGireesh Nagabhushana __be16 fpm; 29956b2bdd1SGireesh Nagabhushana __be16 r7; 30056b2bdd1SGireesh Nagabhushana __u8 sma[6]; 30156b2bdd1SGireesh Nagabhushana }; 30256b2bdd1SGireesh Nagabhushana 30356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_TID 12 30456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_TID 0xfffff 30556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 30656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_TID(x) \ 30756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 30856b2bdd1SGireesh Nagabhushana 30956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_RQTYPE 11 31056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_RQTYPE 0x1 31156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 31256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_RQTYPE(x) \ 31356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 31456b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 31556b2bdd1SGireesh Nagabhushana 31656b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_NOREPLY 10 31756b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_NOREPLY 0x1 31856b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 31956b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_NOREPLY(x) \ 32056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 32156b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 32256b2bdd1SGireesh Nagabhushana 32356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_IQ 0 32456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_IQ 0x3ff 32556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 32656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_IQ(x) \ 32756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 32856b2bdd1SGireesh Nagabhushana 32956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_DEL_FILTER 31 33056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_DEL_FILTER 0x1 33156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 33256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_DEL_FILTER(x) \ 33356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 33456b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 33556b2bdd1SGireesh Nagabhushana 33656b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_RPTTID 25 33756b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_RPTTID 0x1 33856b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 33956b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_RPTTID(x) \ 34056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 34156b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 34256b2bdd1SGireesh Nagabhushana 34356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_DROP 24 34456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_DROP 0x1 34556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 34656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_DROP(x) \ 34756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 34856b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 34956b2bdd1SGireesh Nagabhushana 35056b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_DIRSTEER 23 35156b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_DIRSTEER 0x1 35256b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 35356b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_DIRSTEER(x) \ 35456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 35556b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 35656b2bdd1SGireesh Nagabhushana 35756b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_MASKHASH 22 35856b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_MASKHASH 0x1 35956b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 36056b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_MASKHASH(x) \ 36156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 36256b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 36356b2bdd1SGireesh Nagabhushana 36456b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_DIRSTEERHASH 21 36556b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 36656b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 36756b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 36856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 36956b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 37056b2bdd1SGireesh Nagabhushana 37156b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_LPBK 20 37256b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_LPBK 0x1 37356b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 37456b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_LPBK(x) \ 37556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 37656b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 37756b2bdd1SGireesh Nagabhushana 37856b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_DMAC 19 37956b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_DMAC 0x1 38056b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 38156b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_DMAC(x) \ 38256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 38356b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 38456b2bdd1SGireesh Nagabhushana 38556b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_SMAC 18 38656b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_SMAC 0x1 38756b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 38856b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_SMAC(x) \ 38956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 39056b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 39156b2bdd1SGireesh Nagabhushana 39256b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_INSVLAN 17 39356b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_INSVLAN 0x1 39456b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 39556b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_INSVLAN(x) \ 39656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 39756b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 39856b2bdd1SGireesh Nagabhushana 39956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_RMVLAN 16 40056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_RMVLAN 0x1 40156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 40256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_RMVLAN(x) \ 40356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 40456b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 40556b2bdd1SGireesh Nagabhushana 40656b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_HITCNTS 15 40756b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_HITCNTS 0x1 40856b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 40956b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_HITCNTS(x) \ 41056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 41156b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 41256b2bdd1SGireesh Nagabhushana 41356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_TXCHAN 13 41456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_TXCHAN 0x3 41556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 41656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_TXCHAN(x) \ 41756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 41856b2bdd1SGireesh Nagabhushana 41956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_PRIO 12 42056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_PRIO 0x1 42156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 42256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_PRIO(x) \ 42356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 42456b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 42556b2bdd1SGireesh Nagabhushana 42656b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_L2TIX 0 42756b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_L2TIX 0xfff 42856b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 42956b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_L2TIX(x) \ 43056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 43156b2bdd1SGireesh Nagabhushana 43256b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_FRAG 7 43356b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_FRAG 0x1 43456b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 43556b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_FRAG(x) \ 43656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 43756b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 43856b2bdd1SGireesh Nagabhushana 43956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_FRAGM 6 44056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_FRAGM 0x1 44156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 44256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_FRAGM(x) \ 44356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 44456b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 44556b2bdd1SGireesh Nagabhushana 44656b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_IVLAN_VLD 5 44756b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_IVLAN_VLD 0x1 44856b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 44956b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 45056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 45156b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 45256b2bdd1SGireesh Nagabhushana 45356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_OVLAN_VLD 4 45456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_OVLAN_VLD 0x1 45556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 45656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 45756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 45856b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 45956b2bdd1SGireesh Nagabhushana 46056b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_IVLAN_VLDM 3 46156b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 46256b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 46356b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 46456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 46556b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 46656b2bdd1SGireesh Nagabhushana 46756b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_OVLAN_VLDM 2 46856b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 46956b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 47056b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 47156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 47256b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 47356b2bdd1SGireesh Nagabhushana 47456b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_RX_CHAN 15 47556b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_RX_CHAN 0x1 47656b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 47756b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_RX_CHAN(x) \ 47856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 47956b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 48056b2bdd1SGireesh Nagabhushana 48156b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_RX_RPL_IQ 0 48256b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 48356b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 48456b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 48556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 48656b2bdd1SGireesh Nagabhushana 48756b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_MACI 23 48856b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_MACI 0x1ff 48956b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 49056b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_MACI(x) \ 49156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 49256b2bdd1SGireesh Nagabhushana 49356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_MACIM 14 49456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_MACIM 0x1ff 49556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 49656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_MACIM(x) \ 49756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 49856b2bdd1SGireesh Nagabhushana 49956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_FCOE 13 50056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_FCOE 0x1 50156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 50256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_FCOE(x) \ 50356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 50456b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 50556b2bdd1SGireesh Nagabhushana 50656b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_FCOEM 12 50756b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_FCOEM 0x1 50856b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 50956b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_FCOEM(x) \ 51056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 51156b2bdd1SGireesh Nagabhushana #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 51256b2bdd1SGireesh Nagabhushana 51356b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_PORT 9 51456b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_PORT 0x7 51556b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 51656b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_PORT(x) \ 51756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 51856b2bdd1SGireesh Nagabhushana 51956b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_PORTM 6 52056b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_PORTM 0x7 52156b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 52256b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_PORTM(x) \ 52356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 52456b2bdd1SGireesh Nagabhushana 52556b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_MATCHTYPE 3 52656b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_MATCHTYPE 0x7 52756b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 52856b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_MATCHTYPE(x) \ 52956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 53056b2bdd1SGireesh Nagabhushana 53156b2bdd1SGireesh Nagabhushana #define S_FW_FILTER_WR_MATCHTYPEM 0 53256b2bdd1SGireesh Nagabhushana #define M_FW_FILTER_WR_MATCHTYPEM 0x7 53356b2bdd1SGireesh Nagabhushana #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 53456b2bdd1SGireesh Nagabhushana #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 53556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 53656b2bdd1SGireesh Nagabhushana 53756b2bdd1SGireesh Nagabhushana struct fw_ulptx_wr { 53856b2bdd1SGireesh Nagabhushana __be32 op_to_compl; 53956b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 54056b2bdd1SGireesh Nagabhushana __u64 cookie; 54156b2bdd1SGireesh Nagabhushana }; 54256b2bdd1SGireesh Nagabhushana 54356b2bdd1SGireesh Nagabhushana struct fw_tp_wr { 54456b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 54556b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 54656b2bdd1SGireesh Nagabhushana __u64 cookie; 54756b2bdd1SGireesh Nagabhushana }; 54856b2bdd1SGireesh Nagabhushana 54956b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_wr { 55056b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 55156b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 55256b2bdd1SGireesh Nagabhushana __be64 r3; 55356b2bdd1SGireesh Nagabhushana }; 55456b2bdd1SGireesh Nagabhushana 55556b2bdd1SGireesh Nagabhushana #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 55656b2bdd1SGireesh Nagabhushana #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 55756b2bdd1SGireesh Nagabhushana #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 55856b2bdd1SGireesh Nagabhushana #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 55956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 56056b2bdd1SGireesh Nagabhushana 561*de483253SVishal Kulkarni struct fw_eth_tx_pkt2_wr { 562*de483253SVishal Kulkarni __be32 op_immdlen; 563*de483253SVishal Kulkarni __be32 equiq_to_len16; 564*de483253SVishal Kulkarni __be32 r3; 565*de483253SVishal Kulkarni __be32 L4ChkDisable_to_IpHdrLen; 566*de483253SVishal Kulkarni }; 567*de483253SVishal Kulkarni 568*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 569*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 570*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 571*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 572*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 573*de483253SVishal Kulkarni 574*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 575*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 576*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 577*de483253SVishal Kulkarni ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 578*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 579*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 580*de483253SVishal Kulkarni M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 581*de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 582*de483253SVishal Kulkarni V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 583*de483253SVishal Kulkarni 584*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 585*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 586*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 587*de483253SVishal Kulkarni ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 588*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 589*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 590*de483253SVishal Kulkarni M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 591*de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 592*de483253SVishal Kulkarni V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 593*de483253SVishal Kulkarni 594*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 595*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 596*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 597*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 598*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 599*de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 600*de483253SVishal Kulkarni 601*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 602*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 603*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 604*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 605*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 606*de483253SVishal Kulkarni 607*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 608*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 609*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 610*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 611*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 612*de483253SVishal Kulkarni 613*de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 614*de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 615*de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 616*de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 617*de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 618*de483253SVishal Kulkarni 61956b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkts_wr { 62056b2bdd1SGireesh Nagabhushana __be32 op_pkd; 62156b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 62256b2bdd1SGireesh Nagabhushana __be32 r3; 62356b2bdd1SGireesh Nagabhushana __be16 plen; 62456b2bdd1SGireesh Nagabhushana __u8 npkt; 62556b2bdd1SGireesh Nagabhushana __u8 type; 62656b2bdd1SGireesh Nagabhushana }; 62756b2bdd1SGireesh Nagabhushana 62856b2bdd1SGireesh Nagabhushana struct fw_eth_tx_uo_wr { 62956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 63056b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 63156b2bdd1SGireesh Nagabhushana __be64 r3; 632*de483253SVishal Kulkarni __u8 r4; 633*de483253SVishal Kulkarni __u8 ethlen; 63456b2bdd1SGireesh Nagabhushana __be16 iplen; 635*de483253SVishal Kulkarni __u8 udplen; 636*de483253SVishal Kulkarni __u8 rtplen; 637*de483253SVishal Kulkarni __be16 r5; 63856b2bdd1SGireesh Nagabhushana __be16 mss; 639*de483253SVishal Kulkarni __be16 schedpktsize; 64056b2bdd1SGireesh Nagabhushana __be32 length; 64156b2bdd1SGireesh Nagabhushana }; 64256b2bdd1SGireesh Nagabhushana 64356b2bdd1SGireesh Nagabhushana struct fw_eq_flush_wr { 64456b2bdd1SGireesh Nagabhushana __u8 opcode; 64556b2bdd1SGireesh Nagabhushana __u8 r1[3]; 64656b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 64756b2bdd1SGireesh Nagabhushana __be64 r3; 64856b2bdd1SGireesh Nagabhushana }; 64956b2bdd1SGireesh Nagabhushana 65056b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_wr { 65156b2bdd1SGireesh Nagabhushana __be32 op_compl; 65256b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 65356b2bdd1SGireesh Nagabhushana __u64 cookie; 65456b2bdd1SGireesh Nagabhushana __be64 r2; 65556b2bdd1SGireesh Nagabhushana __be64 r3; 65656b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le { 65756b2bdd1SGireesh Nagabhushana __be32 version_cpl; 65856b2bdd1SGireesh Nagabhushana __be32 filter; 65956b2bdd1SGireesh Nagabhushana __be32 r1; 66056b2bdd1SGireesh Nagabhushana __be16 lport; 66156b2bdd1SGireesh Nagabhushana __be16 pport; 66256b2bdd1SGireesh Nagabhushana union fw_ofld_connection_leip { 66356b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le_ipv4 { 66456b2bdd1SGireesh Nagabhushana __be32 pip; 66556b2bdd1SGireesh Nagabhushana __be32 lip; 66656b2bdd1SGireesh Nagabhushana __be64 r0; 66756b2bdd1SGireesh Nagabhushana __be64 r1; 66856b2bdd1SGireesh Nagabhushana __be64 r2; 66956b2bdd1SGireesh Nagabhushana } ipv4; 67056b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le_ipv6 { 67156b2bdd1SGireesh Nagabhushana __be64 pip_hi; 67256b2bdd1SGireesh Nagabhushana __be64 pip_lo; 67356b2bdd1SGireesh Nagabhushana __be64 lip_hi; 67456b2bdd1SGireesh Nagabhushana __be64 lip_lo; 67556b2bdd1SGireesh Nagabhushana } ipv6; 67656b2bdd1SGireesh Nagabhushana } u; 67756b2bdd1SGireesh Nagabhushana } le; 67856b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_tcb { 67956b2bdd1SGireesh Nagabhushana __be32 t_state_to_astid; 68056b2bdd1SGireesh Nagabhushana __be16 cplrxdataack_cplpassacceptrpl; 68156b2bdd1SGireesh Nagabhushana __be16 rcv_adv; 68256b2bdd1SGireesh Nagabhushana __be32 rcv_nxt; 68356b2bdd1SGireesh Nagabhushana __be32 tx_max; 68456b2bdd1SGireesh Nagabhushana __be64 opt0; 68556b2bdd1SGireesh Nagabhushana __be32 opt2; 68656b2bdd1SGireesh Nagabhushana __be32 r1; 68756b2bdd1SGireesh Nagabhushana __be64 r2; 68856b2bdd1SGireesh Nagabhushana __be64 r3; 68956b2bdd1SGireesh Nagabhushana } tcb; 69056b2bdd1SGireesh Nagabhushana }; 69156b2bdd1SGireesh Nagabhushana 69256b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_VERSION 31 69356b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 69456b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 69556b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 69656b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 69756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 69856b2bdd1SGireesh Nagabhushana M_FW_OFLD_CONNECTION_WR_VERSION) 69956b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 70056b2bdd1SGireesh Nagabhushana 70156b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_CPL 30 70256b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 70356b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 70456b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 70556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 70656b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 70756b2bdd1SGireesh Nagabhushana 70856b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 70956b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 71056b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 71156b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 71256b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 71356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 71456b2bdd1SGireesh Nagabhushana M_FW_OFLD_CONNECTION_WR_T_STATE) 71556b2bdd1SGireesh Nagabhushana 71656b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 71756b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 71856b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 71956b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 72056b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 72156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 72256b2bdd1SGireesh Nagabhushana M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 72356b2bdd1SGireesh Nagabhushana 72456b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_ASTID 0 72556b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 72656b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 72756b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 72856b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 72956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 73056b2bdd1SGireesh Nagabhushana 73156b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 73256b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 73356b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 73456b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 73556b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 73656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 73756b2bdd1SGireesh Nagabhushana M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 73856b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 73956b2bdd1SGireesh Nagabhushana V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 74056b2bdd1SGireesh Nagabhushana 74156b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 74256b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 74356b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 74456b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 74556b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 74656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 74756b2bdd1SGireesh Nagabhushana M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 74856b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 74956b2bdd1SGireesh Nagabhushana V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 75056b2bdd1SGireesh Nagabhushana 75156b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem_tcpstate { 75256b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 75356b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 75456b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 75556b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 75656b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 75756b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 75856b2bdd1SGireesh Nagabhushana /* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */ 75956b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, 76056b2bdd1SGireesh Nagabhushana /* haven't gotten ACK for FIN & will resend FIN but have received FIN */ 76156b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, 76256b2bdd1SGireesh Nagabhushana /* haven't gotten ACK for FIN & will resend FIN but have received FIN */ 76356b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, 76456b2bdd1SGireesh Nagabhushana /* sent FIN and got FIN + ACK, waiting for FIN */ 76556b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, 76656b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 76756b2bdd1SGireesh Nagabhushana }; 76856b2bdd1SGireesh Nagabhushana 76956b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem_uostate { 77056b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 77156b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 77256b2bdd1SGireesh Nagabhushana /* graceful close, after sending outstanding payload */ 77356b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, 77456b2bdd1SGireesh Nagabhushana /* immediate close, after discarding outstanding payload */ 77556b2bdd1SGireesh Nagabhushana FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, 77656b2bdd1SGireesh Nagabhushana }; 77756b2bdd1SGireesh Nagabhushana 77856b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem { 779*de483253SVishal Kulkarni FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 780*de483253SVishal Kulkarni FW_FLOWC_MNEM_CH = 1, 781*de483253SVishal Kulkarni FW_FLOWC_MNEM_PORT = 2, 782*de483253SVishal Kulkarni FW_FLOWC_MNEM_IQID = 3, 783*de483253SVishal Kulkarni FW_FLOWC_MNEM_SNDNXT = 4, 784*de483253SVishal Kulkarni FW_FLOWC_MNEM_RCVNXT = 5, 785*de483253SVishal Kulkarni FW_FLOWC_MNEM_SNDBUF = 6, 786*de483253SVishal Kulkarni FW_FLOWC_MNEM_MSS = 7, 787*de483253SVishal Kulkarni FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 788*de483253SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE = 9, 789*de483253SVishal Kulkarni FW_FLOWC_MNEM_UOSTATE = 10, 790*de483253SVishal Kulkarni FW_FLOWC_MNEM_SCHEDCLASS = 11, 791*de483253SVishal Kulkarni FW_FLOWC_MNEM_DCBPRIO = 12, 79256b2bdd1SGireesh Nagabhushana }; 79356b2bdd1SGireesh Nagabhushana 79456b2bdd1SGireesh Nagabhushana struct fw_flowc_mnemval { 79556b2bdd1SGireesh Nagabhushana __u8 mnemonic; 79656b2bdd1SGireesh Nagabhushana __u8 r4[3]; 79756b2bdd1SGireesh Nagabhushana __be32 val; 79856b2bdd1SGireesh Nagabhushana }; 79956b2bdd1SGireesh Nagabhushana 80056b2bdd1SGireesh Nagabhushana struct fw_flowc_wr { 80156b2bdd1SGireesh Nagabhushana __be32 op_to_nparams; 80256b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 80356b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 80456b2bdd1SGireesh Nagabhushana struct fw_flowc_mnemval mnemval[]; 80556b2bdd1SGireesh Nagabhushana #endif 80656b2bdd1SGireesh Nagabhushana }; 80756b2bdd1SGireesh Nagabhushana 80856b2bdd1SGireesh Nagabhushana #define S_FW_FLOWC_WR_NPARAMS 0 80956b2bdd1SGireesh Nagabhushana #define M_FW_FLOWC_WR_NPARAMS 0xff 81056b2bdd1SGireesh Nagabhushana #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 81156b2bdd1SGireesh Nagabhushana #define G_FW_FLOWC_WR_NPARAMS(x) \ 81256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 81356b2bdd1SGireesh Nagabhushana 81456b2bdd1SGireesh Nagabhushana struct fw_ofld_tx_data_wr { 81556b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 81656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 81756b2bdd1SGireesh Nagabhushana __be32 plen; 81856b2bdd1SGireesh Nagabhushana __be32 tunnel_to_proxy; 81956b2bdd1SGireesh Nagabhushana }; 82056b2bdd1SGireesh Nagabhushana 82156b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 82256b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 82356b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 82456b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 82556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 82656b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 82756b2bdd1SGireesh Nagabhushana 82856b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_SAVE 18 82956b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 83056b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 83156b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 83256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 83356b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 83456b2bdd1SGireesh Nagabhushana 83556b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 83656b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 83756b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 83856b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 83956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 84056b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 84156b2bdd1SGireesh Nagabhushana 84256b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_URGENT 16 84356b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 84456b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 84556b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 84656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 84756b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 84856b2bdd1SGireesh Nagabhushana 84956b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_MORE 15 85056b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 85156b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 85256b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 85356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 85456b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 85556b2bdd1SGireesh Nagabhushana 85656b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 85756b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 85856b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 85956b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 86056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 86156b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 86256b2bdd1SGireesh Nagabhushana 86356b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 86456b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 86556b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 86656b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 86756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 86856b2bdd1SGireesh Nagabhushana 86956b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 87056b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 87156b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 87256b2bdd1SGireesh Nagabhushana ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 87356b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 87456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 87556b2bdd1SGireesh Nagabhushana M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 87656b2bdd1SGireesh Nagabhushana 87756b2bdd1SGireesh Nagabhushana #define S_FW_OFLD_TX_DATA_WR_PROXY 5 87856b2bdd1SGireesh Nagabhushana #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 87956b2bdd1SGireesh Nagabhushana #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 88056b2bdd1SGireesh Nagabhushana #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 88156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 88256b2bdd1SGireesh Nagabhushana #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 88356b2bdd1SGireesh Nagabhushana 88456b2bdd1SGireesh Nagabhushana struct fw_cmd_wr { 88556b2bdd1SGireesh Nagabhushana __be32 op_dma; 88656b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 88756b2bdd1SGireesh Nagabhushana __be64 cookie_daddr; 88856b2bdd1SGireesh Nagabhushana }; 88956b2bdd1SGireesh Nagabhushana 89056b2bdd1SGireesh Nagabhushana #define S_FW_CMD_WR_DMA 17 89156b2bdd1SGireesh Nagabhushana #define M_FW_CMD_WR_DMA 0x1 89256b2bdd1SGireesh Nagabhushana #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 89356b2bdd1SGireesh Nagabhushana #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 89456b2bdd1SGireesh Nagabhushana #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 89556b2bdd1SGireesh Nagabhushana 89656b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_vm_wr { 89756b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 89856b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 89956b2bdd1SGireesh Nagabhushana __be32 r3[2]; 90056b2bdd1SGireesh Nagabhushana __u8 ethmacdst[6]; 90156b2bdd1SGireesh Nagabhushana __u8 ethmacsrc[6]; 90256b2bdd1SGireesh Nagabhushana __be16 ethtype; 90356b2bdd1SGireesh Nagabhushana __be16 vlantci; 90456b2bdd1SGireesh Nagabhushana }; 90556b2bdd1SGireesh Nagabhushana 90656b2bdd1SGireesh Nagabhushana /* 90756b2bdd1SGireesh Nagabhushana * ************************************ 90856b2bdd1SGireesh Nagabhushana * R I W O R K R E Q U E S T s 90956b2bdd1SGireesh Nagabhushana * ************************************ 91056b2bdd1SGireesh Nagabhushana */ 91156b2bdd1SGireesh Nagabhushana 91256b2bdd1SGireesh Nagabhushana enum fw_ri_wr_opcode { 91356b2bdd1SGireesh Nagabhushana FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 91456b2bdd1SGireesh Nagabhushana FW_RI_READ_REQ = 0x1, 91556b2bdd1SGireesh Nagabhushana FW_RI_READ_RESP = 0x2, 91656b2bdd1SGireesh Nagabhushana FW_RI_SEND = 0x3, 91756b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_INV = 0x4, 91856b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_SE = 0x5, 91956b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_SE_INV = 0x6, 92056b2bdd1SGireesh Nagabhushana FW_RI_TERMINATE = 0x7, 92156b2bdd1SGireesh Nagabhushana FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 92256b2bdd1SGireesh Nagabhushana FW_RI_BIND_MW = 0x9, 92356b2bdd1SGireesh Nagabhushana FW_RI_FAST_REGISTER = 0xa, 92456b2bdd1SGireesh Nagabhushana FW_RI_LOCAL_INV = 0xb, 92556b2bdd1SGireesh Nagabhushana FW_RI_QP_MODIFY = 0xc, 92656b2bdd1SGireesh Nagabhushana FW_RI_BYPASS = 0xd, 92756b2bdd1SGireesh Nagabhushana FW_RI_RECEIVE = 0xe, 92856b2bdd1SGireesh Nagabhushana FW_RI_SGE_EC_CR_RETURN = 0xf 92956b2bdd1SGireesh Nagabhushana 93056b2bdd1SGireesh Nagabhushana }; 93156b2bdd1SGireesh Nagabhushana 93256b2bdd1SGireesh Nagabhushana enum fw_ri_wr_flags { 93356b2bdd1SGireesh Nagabhushana FW_RI_COMPLETION_FLAG = 0x01, 93456b2bdd1SGireesh Nagabhushana FW_RI_NOTIFICATION_FLAG = 0x02, 93556b2bdd1SGireesh Nagabhushana FW_RI_SOLICITED_EVENT_FLAG = 0x04, 93656b2bdd1SGireesh Nagabhushana FW_RI_READ_FENCE_FLAG = 0x08, 93756b2bdd1SGireesh Nagabhushana FW_RI_LOCAL_FENCE_FLAG = 0x10, 93856b2bdd1SGireesh Nagabhushana FW_RI_RDMA_READ_INVALIDATE = 0x20 93956b2bdd1SGireesh Nagabhushana }; 94056b2bdd1SGireesh Nagabhushana 94156b2bdd1SGireesh Nagabhushana enum fw_ri_mpa_attrs { 94256b2bdd1SGireesh Nagabhushana FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 94356b2bdd1SGireesh Nagabhushana FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 94456b2bdd1SGireesh Nagabhushana FW_RI_MPA_CRC_ENABLE = 0x04, 94556b2bdd1SGireesh Nagabhushana FW_RI_MPA_IETF_ENABLE = 0x08 94656b2bdd1SGireesh Nagabhushana }; 94756b2bdd1SGireesh Nagabhushana 94856b2bdd1SGireesh Nagabhushana enum fw_ri_qp_caps { 94956b2bdd1SGireesh Nagabhushana FW_RI_QP_RDMA_READ_ENABLE = 0x01, 95056b2bdd1SGireesh Nagabhushana FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 95156b2bdd1SGireesh Nagabhushana FW_RI_QP_BIND_ENABLE = 0x04, 95256b2bdd1SGireesh Nagabhushana FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 95356b2bdd1SGireesh Nagabhushana FW_RI_QP_STAG0_ENABLE = 0x10, 95456b2bdd1SGireesh Nagabhushana FW_RI_QP_RDMA_READ_REQ_0B_ENABLE = 0x80, 95556b2bdd1SGireesh Nagabhushana }; 95656b2bdd1SGireesh Nagabhushana 95756b2bdd1SGireesh Nagabhushana enum fw_ri_addr_type { 95856b2bdd1SGireesh Nagabhushana FW_RI_ZERO_BASED_TO = 0x00, 95956b2bdd1SGireesh Nagabhushana FW_RI_VA_BASED_TO = 0x01 96056b2bdd1SGireesh Nagabhushana }; 96156b2bdd1SGireesh Nagabhushana 96256b2bdd1SGireesh Nagabhushana enum fw_ri_mem_perms { 96356b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 96456b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM_READ = 0x02, 96556b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM = 0x03, 96656b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 96756b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 96856b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL = 0x0C 96956b2bdd1SGireesh Nagabhushana }; 97056b2bdd1SGireesh Nagabhushana 97156b2bdd1SGireesh Nagabhushana enum fw_ri_stag_type { 97256b2bdd1SGireesh Nagabhushana FW_RI_STAG_NSMR = 0x00, 97356b2bdd1SGireesh Nagabhushana FW_RI_STAG_SMR = 0x01, 97456b2bdd1SGireesh Nagabhushana FW_RI_STAG_MW = 0x02, 97556b2bdd1SGireesh Nagabhushana FW_RI_STAG_MW_RELAXED = 0x03 97656b2bdd1SGireesh Nagabhushana }; 97756b2bdd1SGireesh Nagabhushana 97856b2bdd1SGireesh Nagabhushana enum fw_ri_data_op { 97956b2bdd1SGireesh Nagabhushana FW_RI_DATA_IMMD = 0x81, 98056b2bdd1SGireesh Nagabhushana FW_RI_DATA_DSGL = 0x82, 98156b2bdd1SGireesh Nagabhushana FW_RI_DATA_ISGL = 0x83 98256b2bdd1SGireesh Nagabhushana }; 98356b2bdd1SGireesh Nagabhushana 98456b2bdd1SGireesh Nagabhushana enum fw_ri_sgl_depth { 98556b2bdd1SGireesh Nagabhushana FW_RI_SGL_DEPTH_MAX_SQ = 16, 98656b2bdd1SGireesh Nagabhushana FW_RI_SGL_DEPTH_MAX_RQ = 4 98756b2bdd1SGireesh Nagabhushana }; 98856b2bdd1SGireesh Nagabhushana 98956b2bdd1SGireesh Nagabhushana enum fw_ri_cqe_err { 99056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 99156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 99256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 99356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 99456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 99556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 99656b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 99756b2bdd1SGireesh Nagabhushana /* attempt to invalidate a SMR */ 99856b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, 99956b2bdd1SGireesh Nagabhushana /* attempt to invalidate a MR w MW */ 100056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, 100156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 100256b2bdd1SGireesh Nagabhushana /* ECC error detected when reading the PSTAG for a MW Invalidate */ 100356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, 100456b2bdd1SGireesh Nagabhushana /* pbl address out of bound : software error */ 100556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, 100656b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 100756b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 100856b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 100956b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 101056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 101156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 101256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 101356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 101456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 101556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 101656b2bdd1SGireesh Nagabhushana /* MO not zero for TERMINATE or READ_REQ */ 101756b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MO = 0x1A, 101856b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 101956b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 102056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 102156b2bdd1SGireesh Nagabhushana /* RQE address out of bound : software error */ 102256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, 102356b2bdd1SGireesh Nagabhushana /* internel error (opcode mismatch) */ 102456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F 102556b2bdd1SGireesh Nagabhushana 102656b2bdd1SGireesh Nagabhushana }; 102756b2bdd1SGireesh Nagabhushana 102856b2bdd1SGireesh Nagabhushana struct fw_ri_dsge_pair { 102956b2bdd1SGireesh Nagabhushana __be32 len[2]; 103056b2bdd1SGireesh Nagabhushana __be64 addr[2]; 103156b2bdd1SGireesh Nagabhushana }; 103256b2bdd1SGireesh Nagabhushana 103356b2bdd1SGireesh Nagabhushana struct fw_ri_dsgl { 103456b2bdd1SGireesh Nagabhushana __u8 op; 103556b2bdd1SGireesh Nagabhushana __u8 r1; 103656b2bdd1SGireesh Nagabhushana __be16 nsge; 103756b2bdd1SGireesh Nagabhushana __be32 len0; 103856b2bdd1SGireesh Nagabhushana __be64 addr0; 103956b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 104056b2bdd1SGireesh Nagabhushana struct fw_ri_dsge_pair sge[]; 104156b2bdd1SGireesh Nagabhushana #endif 104256b2bdd1SGireesh Nagabhushana }; 104356b2bdd1SGireesh Nagabhushana 104456b2bdd1SGireesh Nagabhushana struct fw_ri_sge { 104556b2bdd1SGireesh Nagabhushana __be32 stag; 104656b2bdd1SGireesh Nagabhushana __be32 len; 104756b2bdd1SGireesh Nagabhushana __be64 to; 104856b2bdd1SGireesh Nagabhushana }; 104956b2bdd1SGireesh Nagabhushana 105056b2bdd1SGireesh Nagabhushana struct fw_ri_isgl { 105156b2bdd1SGireesh Nagabhushana __u8 op; 105256b2bdd1SGireesh Nagabhushana __u8 r1; 105356b2bdd1SGireesh Nagabhushana __be16 nsge; 105456b2bdd1SGireesh Nagabhushana __be32 r2; 105556b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 105656b2bdd1SGireesh Nagabhushana struct fw_ri_sge sge[]; 105756b2bdd1SGireesh Nagabhushana #endif 105856b2bdd1SGireesh Nagabhushana }; 105956b2bdd1SGireesh Nagabhushana 106056b2bdd1SGireesh Nagabhushana struct fw_ri_immd { 106156b2bdd1SGireesh Nagabhushana __u8 op; 106256b2bdd1SGireesh Nagabhushana __u8 r1; 106356b2bdd1SGireesh Nagabhushana __be16 r2; 106456b2bdd1SGireesh Nagabhushana __be32 immdlen; 106556b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 106656b2bdd1SGireesh Nagabhushana __u8 data[]; 106756b2bdd1SGireesh Nagabhushana #endif 106856b2bdd1SGireesh Nagabhushana }; 106956b2bdd1SGireesh Nagabhushana 107056b2bdd1SGireesh Nagabhushana struct fw_ri_tpte { 107156b2bdd1SGireesh Nagabhushana __be32 valid_to_pdid; 107256b2bdd1SGireesh Nagabhushana __be32 locread_to_qpid; 107356b2bdd1SGireesh Nagabhushana __be32 nosnoop_pbladdr; 107456b2bdd1SGireesh Nagabhushana __be32 len_lo; 107556b2bdd1SGireesh Nagabhushana __be32 va_hi; 107656b2bdd1SGireesh Nagabhushana __be32 va_lo_fbo; 107756b2bdd1SGireesh Nagabhushana __be32 dca_mwbcnt_pstag; 107856b2bdd1SGireesh Nagabhushana __be32 len_hi; 107956b2bdd1SGireesh Nagabhushana }; 108056b2bdd1SGireesh Nagabhushana 108156b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_VALID 31 108256b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_VALID 0x1 108356b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 108456b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_VALID(x) \ 108556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 108656b2bdd1SGireesh Nagabhushana #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 108756b2bdd1SGireesh Nagabhushana 108856b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_STAGKEY 23 108956b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_STAGKEY 0xff 109056b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 109156b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_STAGKEY(x) \ 109256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 109356b2bdd1SGireesh Nagabhushana 109456b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_STAGSTATE 22 109556b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_STAGSTATE 0x1 109656b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 109756b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_STAGSTATE(x) \ 109856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 109956b2bdd1SGireesh Nagabhushana #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 110056b2bdd1SGireesh Nagabhushana 110156b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_STAGTYPE 20 110256b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_STAGTYPE 0x3 110356b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 110456b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_STAGTYPE(x) \ 110556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 110656b2bdd1SGireesh Nagabhushana 110756b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_PDID 0 110856b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_PDID 0xfffff 110956b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 111056b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_PDID(x) \ 111156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 111256b2bdd1SGireesh Nagabhushana 111356b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_PERM 28 111456b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_PERM 0xf 111556b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 111656b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_PERM(x) \ 111756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 111856b2bdd1SGireesh Nagabhushana 111956b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_REMINVDIS 27 112056b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_REMINVDIS 0x1 112156b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 112256b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_REMINVDIS(x) \ 112356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 112456b2bdd1SGireesh Nagabhushana #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 112556b2bdd1SGireesh Nagabhushana 112656b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_ADDRTYPE 26 112756b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_ADDRTYPE 1 112856b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 112956b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_ADDRTYPE(x) \ 113056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 113156b2bdd1SGireesh Nagabhushana #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 113256b2bdd1SGireesh Nagabhushana 113356b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_MWBINDEN 25 113456b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_MWBINDEN 0x1 113556b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 113656b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_MWBINDEN(x) \ 113756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 113856b2bdd1SGireesh Nagabhushana #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 113956b2bdd1SGireesh Nagabhushana 114056b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_PS 20 114156b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_PS 0x1f 114256b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 114356b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_PS(x) \ 114456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 114556b2bdd1SGireesh Nagabhushana 114656b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_QPID 0 114756b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_QPID 0xfffff 114856b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 114956b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_QPID(x) \ 115056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 115156b2bdd1SGireesh Nagabhushana 115256b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_NOSNOOP 31 115356b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_NOSNOOP 0x1 115456b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 115556b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_NOSNOOP(x) \ 115656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 115756b2bdd1SGireesh Nagabhushana #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 115856b2bdd1SGireesh Nagabhushana 115956b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_PBLADDR 0 116056b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 116156b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 116256b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_PBLADDR(x) \ 116356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 116456b2bdd1SGireesh Nagabhushana 116556b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_DCA 24 116656b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_DCA 0x1f 116756b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 116856b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_DCA(x) \ 116956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 117056b2bdd1SGireesh Nagabhushana 117156b2bdd1SGireesh Nagabhushana #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 117256b2bdd1SGireesh Nagabhushana #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 117356b2bdd1SGireesh Nagabhushana #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 117456b2bdd1SGireesh Nagabhushana ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 117556b2bdd1SGireesh Nagabhushana #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 117656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 117756b2bdd1SGireesh Nagabhushana 117856b2bdd1SGireesh Nagabhushana enum fw_ri_cqe_rxtx { 117956b2bdd1SGireesh Nagabhushana FW_RI_CQE_RXTX_RX = 0x0, 118056b2bdd1SGireesh Nagabhushana FW_RI_CQE_RXTX_TX = 0x1, 118156b2bdd1SGireesh Nagabhushana }; 118256b2bdd1SGireesh Nagabhushana 118356b2bdd1SGireesh Nagabhushana struct fw_ri_cqe { 118456b2bdd1SGireesh Nagabhushana union fw_ri_rxtx { 118556b2bdd1SGireesh Nagabhushana struct fw_ri_scqe { 118656b2bdd1SGireesh Nagabhushana __be32 qpid_n_stat_rxtx_type; 118756b2bdd1SGireesh Nagabhushana __be32 plen; 118856b2bdd1SGireesh Nagabhushana __be32 reserved; 118956b2bdd1SGireesh Nagabhushana __be32 wrid; 119056b2bdd1SGireesh Nagabhushana } scqe; 119156b2bdd1SGireesh Nagabhushana struct fw_ri_rcqe { 119256b2bdd1SGireesh Nagabhushana __be32 qpid_n_stat_rxtx_type; 119356b2bdd1SGireesh Nagabhushana __be32 plen; 119456b2bdd1SGireesh Nagabhushana __be32 stag; 119556b2bdd1SGireesh Nagabhushana __be32 msn; 119656b2bdd1SGireesh Nagabhushana } rcqe; 119756b2bdd1SGireesh Nagabhushana } u; 119856b2bdd1SGireesh Nagabhushana }; 119956b2bdd1SGireesh Nagabhushana 120056b2bdd1SGireesh Nagabhushana #define S_FW_RI_CQE_QPID 12 120156b2bdd1SGireesh Nagabhushana #define M_FW_RI_CQE_QPID 0xfffff 120256b2bdd1SGireesh Nagabhushana #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 120356b2bdd1SGireesh Nagabhushana #define G_FW_RI_CQE_QPID(x) \ 120456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 120556b2bdd1SGireesh Nagabhushana 120656b2bdd1SGireesh Nagabhushana #define S_FW_RI_CQE_NOTIFY 10 120756b2bdd1SGireesh Nagabhushana #define M_FW_RI_CQE_NOTIFY 0x1 120856b2bdd1SGireesh Nagabhushana #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 120956b2bdd1SGireesh Nagabhushana #define G_FW_RI_CQE_NOTIFY(x) \ 121056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 121156b2bdd1SGireesh Nagabhushana 121256b2bdd1SGireesh Nagabhushana #define S_FW_RI_CQE_STATUS 5 121356b2bdd1SGireesh Nagabhushana #define M_FW_RI_CQE_STATUS 0x1f 121456b2bdd1SGireesh Nagabhushana #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 121556b2bdd1SGireesh Nagabhushana #define G_FW_RI_CQE_STATUS(x) \ 121656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 121756b2bdd1SGireesh Nagabhushana 121856b2bdd1SGireesh Nagabhushana #define S_FW_RI_CQE_RXTX 4 121956b2bdd1SGireesh Nagabhushana #define M_FW_RI_CQE_RXTX 0x1 122056b2bdd1SGireesh Nagabhushana #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 122156b2bdd1SGireesh Nagabhushana #define G_FW_RI_CQE_RXTX(x) \ 122256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 122356b2bdd1SGireesh Nagabhushana 122456b2bdd1SGireesh Nagabhushana #define S_FW_RI_CQE_TYPE 0 122556b2bdd1SGireesh Nagabhushana #define M_FW_RI_CQE_TYPE 0xf 122656b2bdd1SGireesh Nagabhushana #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 122756b2bdd1SGireesh Nagabhushana #define G_FW_RI_CQE_TYPE(x) \ 122856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 122956b2bdd1SGireesh Nagabhushana 123056b2bdd1SGireesh Nagabhushana enum fw_ri_res_type { 123156b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_SQ, 123256b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_RQ, 123356b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_CQ, 123456b2bdd1SGireesh Nagabhushana }; 123556b2bdd1SGireesh Nagabhushana 123656b2bdd1SGireesh Nagabhushana enum fw_ri_res_op { 123756b2bdd1SGireesh Nagabhushana FW_RI_RES_OP_WRITE, 123856b2bdd1SGireesh Nagabhushana FW_RI_RES_OP_RESET, 123956b2bdd1SGireesh Nagabhushana }; 124056b2bdd1SGireesh Nagabhushana 124156b2bdd1SGireesh Nagabhushana struct fw_ri_res { 124256b2bdd1SGireesh Nagabhushana union fw_ri_restype { 124356b2bdd1SGireesh Nagabhushana struct fw_ri_res_sqrq { 124456b2bdd1SGireesh Nagabhushana __u8 restype; 124556b2bdd1SGireesh Nagabhushana __u8 op; 124656b2bdd1SGireesh Nagabhushana __be16 r3; 124756b2bdd1SGireesh Nagabhushana __be32 eqid; 124856b2bdd1SGireesh Nagabhushana __be32 r4[2]; 124956b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 125056b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 125156b2bdd1SGireesh Nagabhushana __be64 eqaddr; 125256b2bdd1SGireesh Nagabhushana } sqrq; 125356b2bdd1SGireesh Nagabhushana struct fw_ri_res_cq { 125456b2bdd1SGireesh Nagabhushana __u8 restype; 125556b2bdd1SGireesh Nagabhushana __u8 op; 125656b2bdd1SGireesh Nagabhushana __be16 r3; 125756b2bdd1SGireesh Nagabhushana __be32 iqid; 125856b2bdd1SGireesh Nagabhushana __be32 r4[2]; 125956b2bdd1SGireesh Nagabhushana __be32 iqandst_to_iqandstindex; 126056b2bdd1SGireesh Nagabhushana __be16 iqdroprss_to_iqesize; 126156b2bdd1SGireesh Nagabhushana __be16 iqsize; 126256b2bdd1SGireesh Nagabhushana __be64 iqaddr; 126356b2bdd1SGireesh Nagabhushana __be32 iqns_iqro; 126456b2bdd1SGireesh Nagabhushana __be32 r6_lo; 126556b2bdd1SGireesh Nagabhushana __be64 r7; 126656b2bdd1SGireesh Nagabhushana } cq; 126756b2bdd1SGireesh Nagabhushana } u; 126856b2bdd1SGireesh Nagabhushana }; 126956b2bdd1SGireesh Nagabhushana 127056b2bdd1SGireesh Nagabhushana struct fw_ri_res_wr { 127156b2bdd1SGireesh Nagabhushana __be32 op_nres; 127256b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 127356b2bdd1SGireesh Nagabhushana __u64 cookie; 127456b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 127556b2bdd1SGireesh Nagabhushana struct fw_ri_res res[]; 127656b2bdd1SGireesh Nagabhushana #endif 127756b2bdd1SGireesh Nagabhushana }; 127856b2bdd1SGireesh Nagabhushana 127956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_NRES 0 128056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_NRES 0xff 128156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 128256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_NRES(x) \ 128356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 128456b2bdd1SGireesh Nagabhushana 128556b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_FETCHSZM 26 128656b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_FETCHSZM 0x1 128756b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 128856b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_FETCHSZM(x) \ 128956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 129056b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 129156b2bdd1SGireesh Nagabhushana 129256b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_STATUSPGNS 25 129356b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_STATUSPGNS 0x1 129456b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 129556b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 129656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 129756b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 129856b2bdd1SGireesh Nagabhushana 129956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_STATUSPGRO 24 130056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_STATUSPGRO 0x1 130156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 130256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 130356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 130456b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 130556b2bdd1SGireesh Nagabhushana 130656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_FETCHNS 23 130756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_FETCHNS 0x1 130856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 130956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_FETCHNS(x) \ 131056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 131156b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 131256b2bdd1SGireesh Nagabhushana 131356b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_FETCHRO 22 131456b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_FETCHRO 0x1 131556b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 131656b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_FETCHRO(x) \ 131756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 131856b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 131956b2bdd1SGireesh Nagabhushana 132056b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_HOSTFCMODE 20 132156b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 132256b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 132356b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 132456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 132556b2bdd1SGireesh Nagabhushana 132656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_CPRIO 19 132756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_CPRIO 0x1 132856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 132956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_CPRIO(x) \ 133056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 133156b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 133256b2bdd1SGireesh Nagabhushana 133356b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_ONCHIP 18 133456b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_ONCHIP 0x1 133556b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 133656b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_ONCHIP(x) \ 133756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 133856b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 133956b2bdd1SGireesh Nagabhushana 134056b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_PCIECHN 16 134156b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_PCIECHN 0x3 134256b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 134356b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_PCIECHN(x) \ 134456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 134556b2bdd1SGireesh Nagabhushana 134656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQID 0 134756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQID 0xffff 134856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 134956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQID(x) \ 135056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 135156b2bdd1SGireesh Nagabhushana 135256b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_DCAEN 31 135356b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_DCAEN 0x1 135456b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 135556b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_DCAEN(x) \ 135656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 135756b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 135856b2bdd1SGireesh Nagabhushana 135956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_DCACPU 26 136056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_DCACPU 0x1f 136156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 136256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_DCACPU(x) \ 136356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 136456b2bdd1SGireesh Nagabhushana 136556b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_FBMIN 23 136656b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_FBMIN 0x7 136756b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 136856b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_FBMIN(x) \ 136956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 137056b2bdd1SGireesh Nagabhushana 137156b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_FBMAX 20 137256b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_FBMAX 0x7 137356b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 137456b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_FBMAX(x) \ 137556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 137656b2bdd1SGireesh Nagabhushana 137756b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 137856b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 137956b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 138056b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 138156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 138256b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 138356b2bdd1SGireesh Nagabhushana 138456b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_CIDXFTHRESH 16 138556b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 138656b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 138756b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 138856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 138956b2bdd1SGireesh Nagabhushana 139056b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_EQSIZE 0 139156b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_EQSIZE 0xffff 139256b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 139356b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_EQSIZE(x) \ 139456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 139556b2bdd1SGireesh Nagabhushana 139656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQANDST 15 139756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQANDST 0x1 139856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 139956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQANDST(x) \ 140056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 140156b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 140256b2bdd1SGireesh Nagabhushana 140356b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQANUS 14 140456b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQANUS 0x1 140556b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 140656b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQANUS(x) \ 140756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 140856b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 140956b2bdd1SGireesh Nagabhushana 141056b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQANUD 12 141156b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQANUD 0x3 141256b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 141356b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQANUD(x) \ 141456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 141556b2bdd1SGireesh Nagabhushana 141656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQANDSTINDEX 0 141756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 141856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 141956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 142056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 142156b2bdd1SGireesh Nagabhushana 142256b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQDROPRSS 15 142356b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQDROPRSS 0x1 142456b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 142556b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 142656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 142756b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 142856b2bdd1SGireesh Nagabhushana 142956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQGTSMODE 14 143056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQGTSMODE 0x1 143156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 143256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 143356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 143456b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 143556b2bdd1SGireesh Nagabhushana 143656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQPCIECH 12 143756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQPCIECH 0x3 143856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 143956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQPCIECH(x) \ 144056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 144156b2bdd1SGireesh Nagabhushana 144256b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQDCAEN 11 144356b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQDCAEN 0x1 144456b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 144556b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQDCAEN(x) \ 144656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 144756b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 144856b2bdd1SGireesh Nagabhushana 144956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQDCACPU 6 145056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQDCACPU 0x1f 145156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 145256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQDCACPU(x) \ 145356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 145456b2bdd1SGireesh Nagabhushana 145556b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 145656b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 145756b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 145856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 145956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 146056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 146156b2bdd1SGireesh Nagabhushana 146256b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQO 3 146356b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQO 0x1 146456b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 146556b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQO(x) \ 146656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 146756b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 146856b2bdd1SGireesh Nagabhushana 146956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQCPRIO 2 147056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQCPRIO 0x1 147156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 147256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQCPRIO(x) \ 147356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 147456b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 147556b2bdd1SGireesh Nagabhushana 147656b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQESIZE 0 147756b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQESIZE 0x3 147856b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 147956b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQESIZE(x) \ 148056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 148156b2bdd1SGireesh Nagabhushana 148256b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQNS 31 148356b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQNS 0x1 148456b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 148556b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQNS(x) \ 148656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 148756b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 148856b2bdd1SGireesh Nagabhushana 148956b2bdd1SGireesh Nagabhushana #define S_FW_RI_RES_WR_IQRO 30 149056b2bdd1SGireesh Nagabhushana #define M_FW_RI_RES_WR_IQRO 0x1 149156b2bdd1SGireesh Nagabhushana #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 149256b2bdd1SGireesh Nagabhushana #define G_FW_RI_RES_WR_IQRO(x) \ 149356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 149456b2bdd1SGireesh Nagabhushana #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 149556b2bdd1SGireesh Nagabhushana 149656b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_write_wr { 149756b2bdd1SGireesh Nagabhushana __u8 opcode; 149856b2bdd1SGireesh Nagabhushana __u8 flags; 149956b2bdd1SGireesh Nagabhushana __u16 wrid; 150056b2bdd1SGireesh Nagabhushana __u8 r1[3]; 150156b2bdd1SGireesh Nagabhushana __u8 len16; 150256b2bdd1SGireesh Nagabhushana __be64 r2; 150356b2bdd1SGireesh Nagabhushana __be32 plen; 150456b2bdd1SGireesh Nagabhushana __be32 stag_sink; 150556b2bdd1SGireesh Nagabhushana __be64 to_sink; 150656b2bdd1SGireesh Nagabhushana }; 150756b2bdd1SGireesh Nagabhushana 150856b2bdd1SGireesh Nagabhushana struct fw_ri_send_wr { 150956b2bdd1SGireesh Nagabhushana __u8 opcode; 151056b2bdd1SGireesh Nagabhushana __u8 flags; 151156b2bdd1SGireesh Nagabhushana __u16 wrid; 151256b2bdd1SGireesh Nagabhushana __u8 r1[3]; 151356b2bdd1SGireesh Nagabhushana __u8 len16; 151456b2bdd1SGireesh Nagabhushana __be32 sendop_pkd; 151556b2bdd1SGireesh Nagabhushana __be32 stag_inv; 151656b2bdd1SGireesh Nagabhushana __be32 plen; 151756b2bdd1SGireesh Nagabhushana __be32 r3; 151856b2bdd1SGireesh Nagabhushana __be64 r4; 151956b2bdd1SGireesh Nagabhushana }; 152056b2bdd1SGireesh Nagabhushana 152156b2bdd1SGireesh Nagabhushana #define S_FW_RI_SEND_WR_SENDOP 0 152256b2bdd1SGireesh Nagabhushana #define M_FW_RI_SEND_WR_SENDOP 0xf 152356b2bdd1SGireesh Nagabhushana #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 152456b2bdd1SGireesh Nagabhushana #define G_FW_RI_SEND_WR_SENDOP(x) \ 152556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 152656b2bdd1SGireesh Nagabhushana 152756b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_read_wr { 152856b2bdd1SGireesh Nagabhushana __u8 opcode; 152956b2bdd1SGireesh Nagabhushana __u8 flags; 153056b2bdd1SGireesh Nagabhushana __u16 wrid; 153156b2bdd1SGireesh Nagabhushana __u8 r1[3]; 153256b2bdd1SGireesh Nagabhushana __u8 len16; 153356b2bdd1SGireesh Nagabhushana __be64 r2; 153456b2bdd1SGireesh Nagabhushana __be32 stag_sink; 153556b2bdd1SGireesh Nagabhushana __be32 to_sink_hi; 153656b2bdd1SGireesh Nagabhushana __be32 to_sink_lo; 153756b2bdd1SGireesh Nagabhushana __be32 plen; 153856b2bdd1SGireesh Nagabhushana __be32 stag_src; 153956b2bdd1SGireesh Nagabhushana __be32 to_src_hi; 154056b2bdd1SGireesh Nagabhushana __be32 to_src_lo; 154156b2bdd1SGireesh Nagabhushana __be32 r5; 154256b2bdd1SGireesh Nagabhushana }; 154356b2bdd1SGireesh Nagabhushana 154456b2bdd1SGireesh Nagabhushana struct fw_ri_recv_wr { 154556b2bdd1SGireesh Nagabhushana __u8 opcode; 154656b2bdd1SGireesh Nagabhushana __u8 r1; 154756b2bdd1SGireesh Nagabhushana __u16 wrid; 154856b2bdd1SGireesh Nagabhushana __u8 r2[3]; 154956b2bdd1SGireesh Nagabhushana __u8 len16; 155056b2bdd1SGireesh Nagabhushana }; 155156b2bdd1SGireesh Nagabhushana 155256b2bdd1SGireesh Nagabhushana struct fw_ri_bind_mw_wr { 155356b2bdd1SGireesh Nagabhushana __u8 opcode; 155456b2bdd1SGireesh Nagabhushana __u8 flags; 155556b2bdd1SGireesh Nagabhushana __u16 wrid; 155656b2bdd1SGireesh Nagabhushana __u8 r1[3]; 155756b2bdd1SGireesh Nagabhushana __u8 len16; 155856b2bdd1SGireesh Nagabhushana __u8 qpbinde_to_dcacpu; 155956b2bdd1SGireesh Nagabhushana __u8 pgsz_shift; 156056b2bdd1SGireesh Nagabhushana __u8 addr_type; 156156b2bdd1SGireesh Nagabhushana __u8 mem_perms; 156256b2bdd1SGireesh Nagabhushana __be32 stag_mr; 156356b2bdd1SGireesh Nagabhushana __be32 stag_mw; 156456b2bdd1SGireesh Nagabhushana __be32 r3; 156556b2bdd1SGireesh Nagabhushana __be64 len_mw; 156656b2bdd1SGireesh Nagabhushana __be64 va_fbo; 156756b2bdd1SGireesh Nagabhushana __be64 r4; 156856b2bdd1SGireesh Nagabhushana }; 156956b2bdd1SGireesh Nagabhushana 157056b2bdd1SGireesh Nagabhushana #define S_FW_RI_BIND_MW_WR_QPBINDE 6 157156b2bdd1SGireesh Nagabhushana #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 157256b2bdd1SGireesh Nagabhushana #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 157356b2bdd1SGireesh Nagabhushana #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 157456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 157556b2bdd1SGireesh Nagabhushana #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 157656b2bdd1SGireesh Nagabhushana 157756b2bdd1SGireesh Nagabhushana #define S_FW_RI_BIND_MW_WR_NS 5 157856b2bdd1SGireesh Nagabhushana #define M_FW_RI_BIND_MW_WR_NS 0x1 157956b2bdd1SGireesh Nagabhushana #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 158056b2bdd1SGireesh Nagabhushana #define G_FW_RI_BIND_MW_WR_NS(x) \ 158156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 158256b2bdd1SGireesh Nagabhushana #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 158356b2bdd1SGireesh Nagabhushana 158456b2bdd1SGireesh Nagabhushana #define S_FW_RI_BIND_MW_WR_DCACPU 0 158556b2bdd1SGireesh Nagabhushana #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 158656b2bdd1SGireesh Nagabhushana #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 158756b2bdd1SGireesh Nagabhushana #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 158856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 158956b2bdd1SGireesh Nagabhushana 159056b2bdd1SGireesh Nagabhushana struct fw_ri_fr_nsmr_wr { 159156b2bdd1SGireesh Nagabhushana __u8 opcode; 159256b2bdd1SGireesh Nagabhushana __u8 flags; 159356b2bdd1SGireesh Nagabhushana __u16 wrid; 159456b2bdd1SGireesh Nagabhushana __u8 r1[3]; 159556b2bdd1SGireesh Nagabhushana __u8 len16; 159656b2bdd1SGireesh Nagabhushana __u8 qpbinde_to_dcacpu; 159756b2bdd1SGireesh Nagabhushana __u8 pgsz_shift; 159856b2bdd1SGireesh Nagabhushana __u8 addr_type; 159956b2bdd1SGireesh Nagabhushana __u8 mem_perms; 160056b2bdd1SGireesh Nagabhushana __be32 stag; 160156b2bdd1SGireesh Nagabhushana __be32 len_hi; 160256b2bdd1SGireesh Nagabhushana __be32 len_lo; 160356b2bdd1SGireesh Nagabhushana __be32 va_hi; 160456b2bdd1SGireesh Nagabhushana __be32 va_lo_fbo; 160556b2bdd1SGireesh Nagabhushana }; 160656b2bdd1SGireesh Nagabhushana 160756b2bdd1SGireesh Nagabhushana #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 160856b2bdd1SGireesh Nagabhushana #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 160956b2bdd1SGireesh Nagabhushana #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 161056b2bdd1SGireesh Nagabhushana #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 161156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 161256b2bdd1SGireesh Nagabhushana #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 161356b2bdd1SGireesh Nagabhushana 161456b2bdd1SGireesh Nagabhushana #define S_FW_RI_FR_NSMR_WR_NS 5 161556b2bdd1SGireesh Nagabhushana #define M_FW_RI_FR_NSMR_WR_NS 0x1 161656b2bdd1SGireesh Nagabhushana #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 161756b2bdd1SGireesh Nagabhushana #define G_FW_RI_FR_NSMR_WR_NS(x) \ 161856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 161956b2bdd1SGireesh Nagabhushana #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 162056b2bdd1SGireesh Nagabhushana 162156b2bdd1SGireesh Nagabhushana #define S_FW_RI_FR_NSMR_WR_DCACPU 0 162256b2bdd1SGireesh Nagabhushana #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 162356b2bdd1SGireesh Nagabhushana #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 162456b2bdd1SGireesh Nagabhushana #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 162556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 162656b2bdd1SGireesh Nagabhushana 162756b2bdd1SGireesh Nagabhushana struct fw_ri_inv_lstag_wr { 162856b2bdd1SGireesh Nagabhushana __u8 opcode; 162956b2bdd1SGireesh Nagabhushana __u8 flags; 163056b2bdd1SGireesh Nagabhushana __u16 wrid; 163156b2bdd1SGireesh Nagabhushana __u8 r1[3]; 163256b2bdd1SGireesh Nagabhushana __u8 len16; 163356b2bdd1SGireesh Nagabhushana __be32 r2; 163456b2bdd1SGireesh Nagabhushana __be32 stag_inv; 163556b2bdd1SGireesh Nagabhushana }; 163656b2bdd1SGireesh Nagabhushana 163756b2bdd1SGireesh Nagabhushana struct fw_ri_send_immediate_wr { 163856b2bdd1SGireesh Nagabhushana __u8 opcode; 163956b2bdd1SGireesh Nagabhushana __u8 flags; 164056b2bdd1SGireesh Nagabhushana __u16 wrid; 164156b2bdd1SGireesh Nagabhushana __u8 r1[3]; 164256b2bdd1SGireesh Nagabhushana __u8 len16; 164356b2bdd1SGireesh Nagabhushana __be32 sendimmop_pkd; 164456b2bdd1SGireesh Nagabhushana __be32 r3; 164556b2bdd1SGireesh Nagabhushana __be32 plen; 164656b2bdd1SGireesh Nagabhushana __be32 r4; 164756b2bdd1SGireesh Nagabhushana __be64 r5; 164856b2bdd1SGireesh Nagabhushana }; 164956b2bdd1SGireesh Nagabhushana 165056b2bdd1SGireesh Nagabhushana #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 165156b2bdd1SGireesh Nagabhushana #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 165256b2bdd1SGireesh Nagabhushana #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 165356b2bdd1SGireesh Nagabhushana ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 165456b2bdd1SGireesh Nagabhushana #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 165556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 165656b2bdd1SGireesh Nagabhushana M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 165756b2bdd1SGireesh Nagabhushana 165856b2bdd1SGireesh Nagabhushana enum fw_ri_atomic_op { 165956b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_FETCHADD, 166056b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_SWAP, 166156b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_CMDSWAP, 166256b2bdd1SGireesh Nagabhushana }; 166356b2bdd1SGireesh Nagabhushana 166456b2bdd1SGireesh Nagabhushana struct fw_ri_atomic_wr { 166556b2bdd1SGireesh Nagabhushana __u8 opcode; 166656b2bdd1SGireesh Nagabhushana __u8 flags; 166756b2bdd1SGireesh Nagabhushana __u16 wrid; 166856b2bdd1SGireesh Nagabhushana __u8 r1[3]; 166956b2bdd1SGireesh Nagabhushana __u8 len16; 167056b2bdd1SGireesh Nagabhushana __be32 atomicop_pkd; 167156b2bdd1SGireesh Nagabhushana __be64 r3; 167256b2bdd1SGireesh Nagabhushana __be32 aopcode_pkd; 167356b2bdd1SGireesh Nagabhushana __be32 reqid; 167456b2bdd1SGireesh Nagabhushana __be32 stag; 167556b2bdd1SGireesh Nagabhushana __be32 to_hi; 167656b2bdd1SGireesh Nagabhushana __be32 to_lo; 167756b2bdd1SGireesh Nagabhushana __be32 addswap_data_hi; 167856b2bdd1SGireesh Nagabhushana __be32 addswap_data_lo; 167956b2bdd1SGireesh Nagabhushana __be32 addswap_mask_hi; 168056b2bdd1SGireesh Nagabhushana __be32 addswap_mask_lo; 168156b2bdd1SGireesh Nagabhushana __be32 compare_data_hi; 168256b2bdd1SGireesh Nagabhushana __be32 compare_data_lo; 168356b2bdd1SGireesh Nagabhushana __be32 compare_mask_hi; 168456b2bdd1SGireesh Nagabhushana __be32 compare_mask_lo; 168556b2bdd1SGireesh Nagabhushana __be32 r5; 168656b2bdd1SGireesh Nagabhushana }; 168756b2bdd1SGireesh Nagabhushana 168856b2bdd1SGireesh Nagabhushana #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 168956b2bdd1SGireesh Nagabhushana #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 169056b2bdd1SGireesh Nagabhushana #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 169156b2bdd1SGireesh Nagabhushana #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 169256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 169356b2bdd1SGireesh Nagabhushana 169456b2bdd1SGireesh Nagabhushana #define S_FW_RI_ATOMIC_WR_AOPCODE 0 169556b2bdd1SGireesh Nagabhushana #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 169656b2bdd1SGireesh Nagabhushana #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 169756b2bdd1SGireesh Nagabhushana #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 169856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 169956b2bdd1SGireesh Nagabhushana 170056b2bdd1SGireesh Nagabhushana enum fw_ri_type { 170156b2bdd1SGireesh Nagabhushana FW_RI_TYPE_INIT, 170256b2bdd1SGireesh Nagabhushana FW_RI_TYPE_FINI, 170356b2bdd1SGireesh Nagabhushana FW_RI_TYPE_TERMINATE 170456b2bdd1SGireesh Nagabhushana }; 170556b2bdd1SGireesh Nagabhushana 170656b2bdd1SGireesh Nagabhushana enum fw_ri_init_p2ptype { 170756b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 170856b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 170956b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 171056b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 171156b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 171256b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 171356b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 171456b2bdd1SGireesh Nagabhushana }; 171556b2bdd1SGireesh Nagabhushana 171656b2bdd1SGireesh Nagabhushana struct fw_ri_wr { 171756b2bdd1SGireesh Nagabhushana __be32 op_compl; 171856b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 171956b2bdd1SGireesh Nagabhushana __u64 cookie; 172056b2bdd1SGireesh Nagabhushana union fw_ri { 172156b2bdd1SGireesh Nagabhushana struct fw_ri_init { 172256b2bdd1SGireesh Nagabhushana __u8 type; 172356b2bdd1SGireesh Nagabhushana __u8 mpareqbit_p2ptype; 172456b2bdd1SGireesh Nagabhushana __u8 r4[2]; 172556b2bdd1SGireesh Nagabhushana __u8 mpa_attrs; 172656b2bdd1SGireesh Nagabhushana __u8 qp_caps; 172756b2bdd1SGireesh Nagabhushana __be16 nrqe; 172856b2bdd1SGireesh Nagabhushana __be32 pdid; 172956b2bdd1SGireesh Nagabhushana __be32 qpid; 173056b2bdd1SGireesh Nagabhushana __be32 sq_eqid; 173156b2bdd1SGireesh Nagabhushana __be32 rq_eqid; 173256b2bdd1SGireesh Nagabhushana __be32 scqid; 173356b2bdd1SGireesh Nagabhushana __be32 rcqid; 173456b2bdd1SGireesh Nagabhushana __be32 ord_max; 173556b2bdd1SGireesh Nagabhushana __be32 ird_max; 173656b2bdd1SGireesh Nagabhushana __be32 iss; 173756b2bdd1SGireesh Nagabhushana __be32 irs; 173856b2bdd1SGireesh Nagabhushana __be32 hwrqsize; 173956b2bdd1SGireesh Nagabhushana __be32 hwrqaddr; 174056b2bdd1SGireesh Nagabhushana __be64 r5; 174156b2bdd1SGireesh Nagabhushana union fw_ri_init_p2p { 174256b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_write_wr write; 174356b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_read_wr read; 174456b2bdd1SGireesh Nagabhushana struct fw_ri_send_wr send; 174556b2bdd1SGireesh Nagabhushana } u; 174656b2bdd1SGireesh Nagabhushana } init; 174756b2bdd1SGireesh Nagabhushana struct fw_ri_fini { 174856b2bdd1SGireesh Nagabhushana __u8 type; 174956b2bdd1SGireesh Nagabhushana __u8 r3[7]; 175056b2bdd1SGireesh Nagabhushana __be64 r4; 175156b2bdd1SGireesh Nagabhushana } fini; 175256b2bdd1SGireesh Nagabhushana struct fw_ri_terminate { 175356b2bdd1SGireesh Nagabhushana __u8 type; 175456b2bdd1SGireesh Nagabhushana __u8 r3[3]; 175556b2bdd1SGireesh Nagabhushana __be32 immdlen; 175656b2bdd1SGireesh Nagabhushana __u8 termmsg[40]; 175756b2bdd1SGireesh Nagabhushana } terminate; 175856b2bdd1SGireesh Nagabhushana } u; 175956b2bdd1SGireesh Nagabhushana }; 176056b2bdd1SGireesh Nagabhushana 176156b2bdd1SGireesh Nagabhushana #define S_FW_RI_WR_MPAREQBIT 7 176256b2bdd1SGireesh Nagabhushana #define M_FW_RI_WR_MPAREQBIT 0x1 176356b2bdd1SGireesh Nagabhushana #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 176456b2bdd1SGireesh Nagabhushana #define G_FW_RI_WR_MPAREQBIT(x) \ 176556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 176656b2bdd1SGireesh Nagabhushana #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 176756b2bdd1SGireesh Nagabhushana 176856b2bdd1SGireesh Nagabhushana #define S_FW_RI_WR_0BRRBIT 6 176956b2bdd1SGireesh Nagabhushana #define M_FW_RI_WR_0BRRBIT 0x1 177056b2bdd1SGireesh Nagabhushana #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 177156b2bdd1SGireesh Nagabhushana #define G_FW_RI_WR_0BRRBIT(x) \ 177256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 177356b2bdd1SGireesh Nagabhushana #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 177456b2bdd1SGireesh Nagabhushana 177556b2bdd1SGireesh Nagabhushana #define S_FW_RI_WR_P2PTYPE 0 177656b2bdd1SGireesh Nagabhushana #define M_FW_RI_WR_P2PTYPE 0xf 177756b2bdd1SGireesh Nagabhushana #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 177856b2bdd1SGireesh Nagabhushana #define G_FW_RI_WR_P2PTYPE(x) \ 177956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 178056b2bdd1SGireesh Nagabhushana 178156b2bdd1SGireesh Nagabhushana /* 178256b2bdd1SGireesh Nagabhushana * ******************************************* 178356b2bdd1SGireesh Nagabhushana * F O i S C S I W O R K R E Q U E S T s 178456b2bdd1SGireesh Nagabhushana * ******************************************* 178556b2bdd1SGireesh Nagabhushana */ 178656b2bdd1SGireesh Nagabhushana 178756b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_NAME_MAX_LEN 224 178856b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_ALIAS_MAX_LEN 224 1789*de483253SVishal Kulkarni #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 179056b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_INIT_NODE_MAX 8 179156b2bdd1SGireesh Nagabhushana 179256b2bdd1SGireesh Nagabhushana enum fw_chnet_ifconf_wr_subop { 179356b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 179456b2bdd1SGireesh Nagabhushana 179556b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 179656b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 179756b2bdd1SGireesh Nagabhushana 179856b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 179956b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 180056b2bdd1SGireesh Nagabhushana 180156b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 180256b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 180356b2bdd1SGireesh Nagabhushana 180456b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 180556b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 180656b2bdd1SGireesh Nagabhushana 180756b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 180856b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 180956b2bdd1SGireesh Nagabhushana 181056b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 181156b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 181256b2bdd1SGireesh Nagabhushana 181356b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MAX, 181456b2bdd1SGireesh Nagabhushana }; 181556b2bdd1SGireesh Nagabhushana 181656b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_wr { 181756b2bdd1SGireesh Nagabhushana __be32 op_compl; 181856b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 181956b2bdd1SGireesh Nagabhushana __be64 cookie; 182056b2bdd1SGireesh Nagabhushana __be32 if_flowid; 182156b2bdd1SGireesh Nagabhushana __u8 idx; 182256b2bdd1SGireesh Nagabhushana __u8 subop; 182356b2bdd1SGireesh Nagabhushana __u8 retval; 182456b2bdd1SGireesh Nagabhushana __u8 r2; 182556b2bdd1SGireesh Nagabhushana __be64 r3; 182656b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_params { 182756b2bdd1SGireesh Nagabhushana __be32 r0; 182856b2bdd1SGireesh Nagabhushana __be16 vlanid; 182956b2bdd1SGireesh Nagabhushana __be16 mtu; 183056b2bdd1SGireesh Nagabhushana union fw_chnet_ifconf_addr_type { 183156b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_ipv4 { 183256b2bdd1SGireesh Nagabhushana __be32 addr; 183356b2bdd1SGireesh Nagabhushana __be32 mask; 183456b2bdd1SGireesh Nagabhushana __be32 router; 183556b2bdd1SGireesh Nagabhushana __be32 r0; 183656b2bdd1SGireesh Nagabhushana __be64 r1; 183756b2bdd1SGireesh Nagabhushana } ipv4; 183856b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_ipv6 { 183956b2bdd1SGireesh Nagabhushana __be64 linklocal_lo; 184056b2bdd1SGireesh Nagabhushana __be64 linklocal_hi; 184156b2bdd1SGireesh Nagabhushana __be64 router_hi; 184256b2bdd1SGireesh Nagabhushana __be64 router_lo; 184356b2bdd1SGireesh Nagabhushana __be64 aconf_hi; 184456b2bdd1SGireesh Nagabhushana __be64 aconf_lo; 184556b2bdd1SGireesh Nagabhushana __be64 linklocal_aconf_hi; 184656b2bdd1SGireesh Nagabhushana __be64 linklocal_aconf_lo; 184756b2bdd1SGireesh Nagabhushana __be64 router_aconf_hi; 184856b2bdd1SGireesh Nagabhushana __be64 router_aconf_lo; 184956b2bdd1SGireesh Nagabhushana __be64 r0; 185056b2bdd1SGireesh Nagabhushana } ipv6; 185156b2bdd1SGireesh Nagabhushana } in_attr; 185256b2bdd1SGireesh Nagabhushana } param; 185356b2bdd1SGireesh Nagabhushana }; 185456b2bdd1SGireesh Nagabhushana 1855*de483253SVishal Kulkarni enum fw_foiscsi_node_type { 1856*de483253SVishal Kulkarni FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1857*de483253SVishal Kulkarni FW_FOISCSI_NODE_TYPE_TARGET, 1858*de483253SVishal Kulkarni }; 1859*de483253SVishal Kulkarni 186056b2bdd1SGireesh Nagabhushana enum fw_foiscsi_session_type { 186156b2bdd1SGireesh Nagabhushana FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 186256b2bdd1SGireesh Nagabhushana FW_FOISCSI_SESSION_TYPE_NORMAL, 186356b2bdd1SGireesh Nagabhushana }; 186456b2bdd1SGireesh Nagabhushana 186556b2bdd1SGireesh Nagabhushana enum fw_foiscsi_auth_policy { 186656b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 186756b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_POLICY_MUTUAL, 186856b2bdd1SGireesh Nagabhushana }; 186956b2bdd1SGireesh Nagabhushana 187056b2bdd1SGireesh Nagabhushana enum fw_foiscsi_auth_method { 187156b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_NONE = 0, 187256b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP, 187356b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP_FST, 187456b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 187556b2bdd1SGireesh Nagabhushana }; 187656b2bdd1SGireesh Nagabhushana 187756b2bdd1SGireesh Nagabhushana enum fw_foiscsi_digest_type { 187856b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_NONE = 0, 187956b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32, 188056b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 188156b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 188256b2bdd1SGireesh Nagabhushana }; 188356b2bdd1SGireesh Nagabhushana 188456b2bdd1SGireesh Nagabhushana enum fw_foiscsi_wr_subop { 188556b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_ADD = 1, 188656b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_DEL = 2, 188756b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_MOD = 4, 188856b2bdd1SGireesh Nagabhushana }; 188956b2bdd1SGireesh Nagabhushana 189056b2bdd1SGireesh Nagabhushana enum fw_foiscsi_ctrl_state { 189156b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_FREE = 0, 189256b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_ONLINE = 1, 189356b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_FAILED, 189456b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 189556b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_REDIRECT, 189656b2bdd1SGireesh Nagabhushana }; 189756b2bdd1SGireesh Nagabhushana 189856b2bdd1SGireesh Nagabhushana struct fw_rdev_wr { 189956b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 190056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 190156b2bdd1SGireesh Nagabhushana __be64 cookie; 190256b2bdd1SGireesh Nagabhushana __u8 protocol; 190356b2bdd1SGireesh Nagabhushana __u8 event_cause; 190456b2bdd1SGireesh Nagabhushana __u8 cur_state; 190556b2bdd1SGireesh Nagabhushana __u8 prev_state; 190656b2bdd1SGireesh Nagabhushana __be32 flags_to_assoc_flowid; 190756b2bdd1SGireesh Nagabhushana union rdev_entry { 190856b2bdd1SGireesh Nagabhushana struct fcoe_rdev_entry { 190956b2bdd1SGireesh Nagabhushana __be32 flowid; 191056b2bdd1SGireesh Nagabhushana __u8 protocol; 191156b2bdd1SGireesh Nagabhushana __u8 event_cause; 191256b2bdd1SGireesh Nagabhushana __u8 flags; 191356b2bdd1SGireesh Nagabhushana __u8 rjt_reason; 191456b2bdd1SGireesh Nagabhushana __u8 cur_login_st; 191556b2bdd1SGireesh Nagabhushana __u8 prev_login_st; 191656b2bdd1SGireesh Nagabhushana __be16 rcv_fr_sz; 191756b2bdd1SGireesh Nagabhushana __u8 rd_xfer_rdy_to_rport_type; 191856b2bdd1SGireesh Nagabhushana __u8 vft_to_qos; 191956b2bdd1SGireesh Nagabhushana __u8 org_proc_assoc_to_acc_rsp_code; 192056b2bdd1SGireesh Nagabhushana __u8 enh_disc_to_tgt; 192156b2bdd1SGireesh Nagabhushana __u8 wwnn[8]; 192256b2bdd1SGireesh Nagabhushana __u8 wwpn[8]; 192356b2bdd1SGireesh Nagabhushana __be16 iqid; 192456b2bdd1SGireesh Nagabhushana __u8 fc_oui[3]; 192556b2bdd1SGireesh Nagabhushana __u8 r_id[3]; 192656b2bdd1SGireesh Nagabhushana } fcoe_rdev; 192756b2bdd1SGireesh Nagabhushana struct iscsi_rdev_entry { 192856b2bdd1SGireesh Nagabhushana __be32 flowid; 192956b2bdd1SGireesh Nagabhushana __u8 protocol; 193056b2bdd1SGireesh Nagabhushana __u8 event_cause; 193156b2bdd1SGireesh Nagabhushana __u8 flags; 193256b2bdd1SGireesh Nagabhushana __u8 r3; 193356b2bdd1SGireesh Nagabhushana __be16 iscsi_opts; 193456b2bdd1SGireesh Nagabhushana __be16 tcp_opts; 193556b2bdd1SGireesh Nagabhushana __be16 ip_opts; 193656b2bdd1SGireesh Nagabhushana __be16 max_rcv_len; 193756b2bdd1SGireesh Nagabhushana __be16 max_snd_len; 193856b2bdd1SGireesh Nagabhushana __be16 first_brst_len; 193956b2bdd1SGireesh Nagabhushana __be16 max_brst_len; 194056b2bdd1SGireesh Nagabhushana __be16 r4; 194156b2bdd1SGireesh Nagabhushana __be16 def_time2wait; 194256b2bdd1SGireesh Nagabhushana __be16 def_time2ret; 194356b2bdd1SGireesh Nagabhushana __be16 nop_out_intrvl; 194456b2bdd1SGireesh Nagabhushana __be16 non_scsi_to; 194556b2bdd1SGireesh Nagabhushana __be16 isid; 194656b2bdd1SGireesh Nagabhushana __be16 tsid; 194756b2bdd1SGireesh Nagabhushana __be16 port; 194856b2bdd1SGireesh Nagabhushana __be16 tpgt; 194956b2bdd1SGireesh Nagabhushana __u8 r5[6]; 195056b2bdd1SGireesh Nagabhushana __be16 iqid; 195156b2bdd1SGireesh Nagabhushana } iscsi_rdev; 195256b2bdd1SGireesh Nagabhushana } u; 195356b2bdd1SGireesh Nagabhushana }; 195456b2bdd1SGireesh Nagabhushana 195556b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_IMMDLEN 0 195656b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_IMMDLEN 0xff 195756b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 195856b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_IMMDLEN(x) \ 195956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 196056b2bdd1SGireesh Nagabhushana 196156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_ALLOC 31 196256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_ALLOC 0x1 196356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 196456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_ALLOC(x) \ 196556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 196656b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 196756b2bdd1SGireesh Nagabhushana 196856b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_FREE 30 196956b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_FREE 0x1 197056b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 197156b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_FREE(x) \ 197256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 197356b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 197456b2bdd1SGireesh Nagabhushana 197556b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_MODIFY 29 197656b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_MODIFY 0x1 197756b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 197856b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_MODIFY(x) \ 197956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 198056b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 198156b2bdd1SGireesh Nagabhushana 198256b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_FLOWID 8 198356b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_FLOWID 0xfffff 198456b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 198556b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_FLOWID(x) \ 198656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 198756b2bdd1SGireesh Nagabhushana 198856b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_LEN16 0 198956b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_LEN16 0xff 199056b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 199156b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_LEN16(x) \ 199256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 199356b2bdd1SGireesh Nagabhushana 199456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_FLAGS 24 199556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_FLAGS 0xff 199656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 199756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_FLAGS(x) \ 199856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 199956b2bdd1SGireesh Nagabhushana 200056b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_GET_NEXT 20 200156b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_GET_NEXT 0xf 200256b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 200356b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_GET_NEXT(x) \ 200456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 200556b2bdd1SGireesh Nagabhushana 200656b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_ASSOC_FLOWID 0 200756b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 200856b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 200956b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 201056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 201156b2bdd1SGireesh Nagabhushana 201256b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_RJT 7 201356b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_RJT 0x1 201456b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 201556b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 201656b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 201756b2bdd1SGireesh Nagabhushana 201856b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_REASON 0 201956b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_REASON 0x7f 202056b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 202156b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_REASON(x) \ 202256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 202356b2bdd1SGireesh Nagabhushana 202456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_RD_XFER_RDY 7 202556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 202656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 202756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 202856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 202956b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 203056b2bdd1SGireesh Nagabhushana 203156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_WR_XFER_RDY 6 203256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 203356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 203456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 203556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 203656b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 203756b2bdd1SGireesh Nagabhushana 203856b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_FC_SP 5 203956b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_FC_SP 0x1 204056b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 204156b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_FC_SP(x) \ 204256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 204356b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 204456b2bdd1SGireesh Nagabhushana 204556b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_RPORT_TYPE 0 204656b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 204756b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 204856b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 204956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 205056b2bdd1SGireesh Nagabhushana 205156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_VFT 7 205256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_VFT 0x1 205356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 205456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 205556b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 205656b2bdd1SGireesh Nagabhushana 205756b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_NPIV 6 205856b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_NPIV 0x1 205956b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 206056b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_NPIV(x) \ 206156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 206256b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 206356b2bdd1SGireesh Nagabhushana 206456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_CLASS 4 206556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_CLASS 0x3 206656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 206756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_CLASS(x) \ 206856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 206956b2bdd1SGireesh Nagabhushana 207056b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_SEQ_DEL 3 207156b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_SEQ_DEL 0x1 207256b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 207356b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_SEQ_DEL(x) \ 207456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 207556b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 207656b2bdd1SGireesh Nagabhushana 207756b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_PRIO_PREEMP 2 207856b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 207956b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 208056b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 208156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 208256b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 208356b2bdd1SGireesh Nagabhushana 208456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_PREF 1 208556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_PREF 0x1 208656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 208756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_PREF(x) \ 208856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 208956b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 209056b2bdd1SGireesh Nagabhushana 209156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_QOS 0 209256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_QOS 0x1 209356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 209456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 209556b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 209656b2bdd1SGireesh Nagabhushana 209756b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 209856b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 209956b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 210056b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 210156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 210256b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 210356b2bdd1SGireesh Nagabhushana 210456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 210556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 210656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 210756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 210856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 210956b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 211056b2bdd1SGireesh Nagabhushana 211156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_IMAGE_PAIR 5 211256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 211356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 211456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 211556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 211656b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 211756b2bdd1SGireesh Nagabhushana 211856b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_ACC_RSP_CODE 0 211956b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 212056b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 212156b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 212256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 212356b2bdd1SGireesh Nagabhushana 212456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_ENH_DISC 7 212556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_ENH_DISC 0x1 212656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 212756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_ENH_DISC(x) \ 212856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 212956b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 213056b2bdd1SGireesh Nagabhushana 213156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_REC 6 213256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_REC 0x1 213356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 213456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 213556b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 213656b2bdd1SGireesh Nagabhushana 213756b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_TASK_RETRY_ID 5 213856b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 213956b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 214056b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 214156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 214256b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 214356b2bdd1SGireesh Nagabhushana 214456b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_RETRY 4 214556b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_RETRY 0x1 214656b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 214756b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_RETRY(x) \ 214856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 214956b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 215056b2bdd1SGireesh Nagabhushana 215156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_CONF_CMPL 3 215256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_CONF_CMPL 0x1 215356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 215456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_CONF_CMPL(x) \ 215556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 215656b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 215756b2bdd1SGireesh Nagabhushana 215856b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_DATA_OVLY 2 215956b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_DATA_OVLY 0x1 216056b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 216156b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_DATA_OVLY(x) \ 216256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 216356b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 216456b2bdd1SGireesh Nagabhushana 216556b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_INI 1 216656b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_INI 0x1 216756b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 216856b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 216956b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 217056b2bdd1SGireesh Nagabhushana 217156b2bdd1SGireesh Nagabhushana #define S_FW_RDEV_WR_TGT 0 217256b2bdd1SGireesh Nagabhushana #define M_FW_RDEV_WR_TGT 0x1 217356b2bdd1SGireesh Nagabhushana #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 217456b2bdd1SGireesh Nagabhushana #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 217556b2bdd1SGireesh Nagabhushana #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 217656b2bdd1SGireesh Nagabhushana 217756b2bdd1SGireesh Nagabhushana struct fw_foiscsi_node_wr { 217856b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 217956b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 218056b2bdd1SGireesh Nagabhushana __u64 cookie; 218156b2bdd1SGireesh Nagabhushana __u8 subop; 218256b2bdd1SGireesh Nagabhushana __u8 status; 218356b2bdd1SGireesh Nagabhushana __u8 alias_len; 218456b2bdd1SGireesh Nagabhushana __u8 iqn_len; 218556b2bdd1SGireesh Nagabhushana __be32 node_flowid; 218656b2bdd1SGireesh Nagabhushana __be16 nodeid; 218756b2bdd1SGireesh Nagabhushana __be16 login_retry; 218856b2bdd1SGireesh Nagabhushana __be16 retry_timeout; 218956b2bdd1SGireesh Nagabhushana __be16 r3; 219056b2bdd1SGireesh Nagabhushana __u8 iqn[224]; 219156b2bdd1SGireesh Nagabhushana __u8 alias[224]; 219256b2bdd1SGireesh Nagabhushana }; 219356b2bdd1SGireesh Nagabhushana 219456b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 219556b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 219656b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 219756b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 219856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 219956b2bdd1SGireesh Nagabhushana 220056b2bdd1SGireesh Nagabhushana struct fw_foiscsi_ctrl_wr { 220156b2bdd1SGireesh Nagabhushana __be32 op_compl; 220256b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 220356b2bdd1SGireesh Nagabhushana __u64 cookie; 220456b2bdd1SGireesh Nagabhushana __u8 subop; 220556b2bdd1SGireesh Nagabhushana __u8 status; 220656b2bdd1SGireesh Nagabhushana __u8 ctrl_state; 220756b2bdd1SGireesh Nagabhushana __u8 io_state; 220856b2bdd1SGireesh Nagabhushana __be32 node_id; 220956b2bdd1SGireesh Nagabhushana __be32 ctrl_id; 221056b2bdd1SGireesh Nagabhushana __be32 io_id; 221156b2bdd1SGireesh Nagabhushana struct fw_foiscsi_sess_attr { 221256b2bdd1SGireesh Nagabhushana __be32 sess_type_to_erl; 221356b2bdd1SGireesh Nagabhushana __be16 max_conn; 221456b2bdd1SGireesh Nagabhushana __be16 max_r2t; 221556b2bdd1SGireesh Nagabhushana __be16 time2wait; 221656b2bdd1SGireesh Nagabhushana __be16 time2retain; 221756b2bdd1SGireesh Nagabhushana __be32 max_burst; 221856b2bdd1SGireesh Nagabhushana __be32 first_burst; 221956b2bdd1SGireesh Nagabhushana __be32 r1; 222056b2bdd1SGireesh Nagabhushana } sess_attr; 222156b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr { 2222*de483253SVishal Kulkarni __be32 hdigest_to_ddp_pgsz; 222356b2bdd1SGireesh Nagabhushana __be32 max_rcv_dsl; 222456b2bdd1SGireesh Nagabhushana __be32 ping_tmo; 222556b2bdd1SGireesh Nagabhushana __be16 dst_port; 222656b2bdd1SGireesh Nagabhushana __be16 src_port; 222756b2bdd1SGireesh Nagabhushana union fw_foiscsi_conn_attr_addr { 222856b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr_ipv6 { 222956b2bdd1SGireesh Nagabhushana __be64 dst_addr[2]; 223056b2bdd1SGireesh Nagabhushana __be64 src_addr[2]; 223156b2bdd1SGireesh Nagabhushana } ipv6_addr; 223256b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr_ipv4 { 223356b2bdd1SGireesh Nagabhushana __be32 dst_addr; 223456b2bdd1SGireesh Nagabhushana __be32 src_addr; 223556b2bdd1SGireesh Nagabhushana } ipv4_addr; 223656b2bdd1SGireesh Nagabhushana } u; 223756b2bdd1SGireesh Nagabhushana } conn_attr; 223856b2bdd1SGireesh Nagabhushana __u8 tgt_name_len; 223956b2bdd1SGireesh Nagabhushana __u8 r3[7]; 2240*de483253SVishal Kulkarni __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 224156b2bdd1SGireesh Nagabhushana }; 224256b2bdd1SGireesh Nagabhushana 224356b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 224456b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 224556b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 224656b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 224756b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 224856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \ 224956b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 225056b2bdd1SGireesh Nagabhushana 225156b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 225256b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 225356b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 225456b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 225556b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 225656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 225756b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 225856b2bdd1SGireesh Nagabhushana #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 225956b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 226056b2bdd1SGireesh Nagabhushana 226156b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 226256b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 226356b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 226456b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 226556b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 226656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 226756b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 226856b2bdd1SGireesh Nagabhushana #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 226956b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 227056b2bdd1SGireesh Nagabhushana 227156b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 227256b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 227356b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 227456b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 227556b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 227656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 227756b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 227856b2bdd1SGireesh Nagabhushana #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 227956b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 228056b2bdd1SGireesh Nagabhushana 228156b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 228256b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 228356b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 228456b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 228556b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 228656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 228756b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 228856b2bdd1SGireesh Nagabhushana #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 228956b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 229056b2bdd1SGireesh Nagabhushana 229156b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_ERL 24 229256b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 229356b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 229456b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 229556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 229656b2bdd1SGireesh Nagabhushana 229756b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 229856b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 229956b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 230056b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 230156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 230256b2bdd1SGireesh Nagabhushana 230356b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 230456b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 230556b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 230656b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 230756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 230856b2bdd1SGireesh Nagabhushana 230956b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 231056b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 231156b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 231256b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 231356b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 231456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 231556b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 231656b2bdd1SGireesh Nagabhushana 231756b2bdd1SGireesh Nagabhushana #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 231856b2bdd1SGireesh Nagabhushana #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 231956b2bdd1SGireesh Nagabhushana #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 232056b2bdd1SGireesh Nagabhushana ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 232156b2bdd1SGireesh Nagabhushana #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 232256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 232356b2bdd1SGireesh Nagabhushana M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 232456b2bdd1SGireesh Nagabhushana 2325*de483253SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2326*de483253SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2327*de483253SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2328*de483253SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2329*de483253SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2330*de483253SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2331*de483253SVishal Kulkarni 233256b2bdd1SGireesh Nagabhushana struct fw_foiscsi_chap_wr { 233356b2bdd1SGireesh Nagabhushana __be32 op_compl; 233456b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 233556b2bdd1SGireesh Nagabhushana __u64 cookie; 233656b2bdd1SGireesh Nagabhushana __u8 status; 233756b2bdd1SGireesh Nagabhushana __u8 id_len; 233856b2bdd1SGireesh Nagabhushana __u8 sec_len; 2339*de483253SVishal Kulkarni __u8 node_type; 234056b2bdd1SGireesh Nagabhushana __be16 node_id; 2341*de483253SVishal Kulkarni __u8 r3[2]; 2342*de483253SVishal Kulkarni __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2343*de483253SVishal Kulkarni __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 234456b2bdd1SGireesh Nagabhushana }; 234556b2bdd1SGireesh Nagabhushana 234656b2bdd1SGireesh Nagabhushana /* 234756b2bdd1SGireesh Nagabhushana * ***************************************** 234856b2bdd1SGireesh Nagabhushana * F O F C O E W O R K R E Q U E S T s 234956b2bdd1SGireesh Nagabhushana * ***************************************** 235056b2bdd1SGireesh Nagabhushana */ 235156b2bdd1SGireesh Nagabhushana 235256b2bdd1SGireesh Nagabhushana struct fw_fcoe_els_ct_wr { 235356b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 235456b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 235556b2bdd1SGireesh Nagabhushana __be64 cookie; 235656b2bdd1SGireesh Nagabhushana __be16 iqid; 235756b2bdd1SGireesh Nagabhushana __u8 tmo_val; 235856b2bdd1SGireesh Nagabhushana __u8 els_ct_type; 235956b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 236056b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 236156b2bdd1SGireesh Nagabhushana __be16 xfer_cnt; 236256b2bdd1SGireesh Nagabhushana __u8 fl_to_sp; 236356b2bdd1SGireesh Nagabhushana __u8 l_id[3]; 236456b2bdd1SGireesh Nagabhushana __u8 r5; 236556b2bdd1SGireesh Nagabhushana __u8 r_id[3]; 236656b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 236756b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 236856b2bdd1SGireesh Nagabhushana __be32 r6; 236956b2bdd1SGireesh Nagabhushana }; 237056b2bdd1SGireesh Nagabhushana 237156b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 237256b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 237356b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 237456b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 237556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 237656b2bdd1SGireesh Nagabhushana 237756b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 237856b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 237956b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 238056b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 238156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 238256b2bdd1SGireesh Nagabhushana 238356b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 238456b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 238556b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 238656b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 238756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 238856b2bdd1SGireesh Nagabhushana 238956b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_LEN16 0 239056b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 239156b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 239256b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 239356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 239456b2bdd1SGireesh Nagabhushana 239556b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 239656b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 239756b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 239856b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 239956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 240056b2bdd1SGireesh Nagabhushana 240156b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_CLASS 4 240256b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 240356b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 240456b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 240556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 240656b2bdd1SGireesh Nagabhushana 240756b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_FL 2 240856b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_FL 0x1 240956b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 241056b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 241156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 241256b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 241356b2bdd1SGireesh Nagabhushana 241456b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_NPIV 1 241556b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 241656b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 241756b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 241856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 241956b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 242056b2bdd1SGireesh Nagabhushana 242156b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_ELS_CT_WR_SP 0 242256b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_ELS_CT_WR_SP 0x1 242356b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 242456b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 242556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 242656b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 242756b2bdd1SGireesh Nagabhushana 242856b2bdd1SGireesh Nagabhushana /* 242956b2bdd1SGireesh Nagabhushana * **************************************** 243056b2bdd1SGireesh Nagabhushana * S C S I W O R K R E Q U E S T s 243156b2bdd1SGireesh Nagabhushana * (FOiSCSI and FCOE unified data path) 243256b2bdd1SGireesh Nagabhushana * **************************************** 243356b2bdd1SGireesh Nagabhushana */ 243456b2bdd1SGireesh Nagabhushana 243556b2bdd1SGireesh Nagabhushana struct fw_scsi_write_wr { 243656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 243756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 243856b2bdd1SGireesh Nagabhushana __be64 cookie; 243956b2bdd1SGireesh Nagabhushana __be16 iqid; 244056b2bdd1SGireesh Nagabhushana __u8 tmo_val; 244156b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 244256b2bdd1SGireesh Nagabhushana union fw_scsi_write_priv { 244356b2bdd1SGireesh Nagabhushana struct fcoe_write_priv { 244456b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 244556b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 244656b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 244756b2bdd1SGireesh Nagabhushana } fcoe; 244856b2bdd1SGireesh Nagabhushana struct iscsi_write_priv { 244956b2bdd1SGireesh Nagabhushana __u8 r3[4]; 245056b2bdd1SGireesh Nagabhushana } iscsi; 245156b2bdd1SGireesh Nagabhushana } u; 245256b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 245356b2bdd1SGireesh Nagabhushana __be32 ini_xfer_cnt; 245456b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 245556b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 245656b2bdd1SGireesh Nagabhushana __be32 r4; 245756b2bdd1SGireesh Nagabhushana }; 245856b2bdd1SGireesh Nagabhushana 245956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_WRITE_WR_OPCODE 24 246056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 246156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 246256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 246356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 246456b2bdd1SGireesh Nagabhushana 246556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 246656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 246756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 246856b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 246956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 247056b2bdd1SGireesh Nagabhushana 247156b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_WRITE_WR_FLOWID 8 247256b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 247356b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 247456b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 247556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 247656b2bdd1SGireesh Nagabhushana 247756b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_WRITE_WR_LEN16 0 247856b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_WRITE_WR_LEN16 0xff 247956b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 248056b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 248156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 248256b2bdd1SGireesh Nagabhushana 248356b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_WRITE_WR_CP_EN 6 248456b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 248556b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 248656b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 248756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 248856b2bdd1SGireesh Nagabhushana 248956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_WRITE_WR_CLASS 4 249056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_WRITE_WR_CLASS 0x3 249156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 249256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 249356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 249456b2bdd1SGireesh Nagabhushana 249556b2bdd1SGireesh Nagabhushana struct fw_scsi_read_wr { 249656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 249756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 249856b2bdd1SGireesh Nagabhushana __be64 cookie; 249956b2bdd1SGireesh Nagabhushana __be16 iqid; 250056b2bdd1SGireesh Nagabhushana __u8 tmo_val; 250156b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 250256b2bdd1SGireesh Nagabhushana union fw_scsi_read_priv { 250356b2bdd1SGireesh Nagabhushana struct fcoe_read_priv { 250456b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 250556b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 250656b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 250756b2bdd1SGireesh Nagabhushana } fcoe; 250856b2bdd1SGireesh Nagabhushana struct iscsi_read_priv { 250956b2bdd1SGireesh Nagabhushana __u8 r3[4]; 251056b2bdd1SGireesh Nagabhushana } iscsi; 251156b2bdd1SGireesh Nagabhushana } u; 251256b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 251356b2bdd1SGireesh Nagabhushana __be32 ini_xfer_cnt; 251456b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 251556b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 251656b2bdd1SGireesh Nagabhushana __be32 r4; 251756b2bdd1SGireesh Nagabhushana }; 251856b2bdd1SGireesh Nagabhushana 251956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_READ_WR_OPCODE 24 252056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_READ_WR_OPCODE 0xff 252156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 252256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_READ_WR_OPCODE(x) \ 252356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 252456b2bdd1SGireesh Nagabhushana 252556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_READ_WR_IMMDLEN 0 252656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 252756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 252856b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 252956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 253056b2bdd1SGireesh Nagabhushana 253156b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_READ_WR_FLOWID 8 253256b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 253356b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 253456b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_READ_WR_FLOWID(x) \ 253556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 253656b2bdd1SGireesh Nagabhushana 253756b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_READ_WR_LEN16 0 253856b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_READ_WR_LEN16 0xff 253956b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 254056b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_READ_WR_LEN16(x) \ 254156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 254256b2bdd1SGireesh Nagabhushana 254356b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_READ_WR_CP_EN 6 254456b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_READ_WR_CP_EN 0x3 254556b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 254656b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_READ_WR_CP_EN(x) \ 254756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 254856b2bdd1SGireesh Nagabhushana 254956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_READ_WR_CLASS 4 255056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_READ_WR_CLASS 0x3 255156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 255256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_READ_WR_CLASS(x) \ 255356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 255456b2bdd1SGireesh Nagabhushana 255556b2bdd1SGireesh Nagabhushana struct fw_scsi_cmd_wr { 255656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 255756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 255856b2bdd1SGireesh Nagabhushana __be64 cookie; 255956b2bdd1SGireesh Nagabhushana __be16 iqid; 256056b2bdd1SGireesh Nagabhushana __u8 tmo_val; 256156b2bdd1SGireesh Nagabhushana __u8 r3; 256256b2bdd1SGireesh Nagabhushana union fw_scsi_cmd_priv { 256356b2bdd1SGireesh Nagabhushana struct fcoe_cmd_priv { 256456b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 256556b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 256656b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 256756b2bdd1SGireesh Nagabhushana } fcoe; 256856b2bdd1SGireesh Nagabhushana struct iscsi_cmd_priv { 256956b2bdd1SGireesh Nagabhushana __u8 r4[4]; 257056b2bdd1SGireesh Nagabhushana } iscsi; 257156b2bdd1SGireesh Nagabhushana } u; 257256b2bdd1SGireesh Nagabhushana __u8 r5[8]; 257356b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 257456b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 257556b2bdd1SGireesh Nagabhushana __be32 r6; 257656b2bdd1SGireesh Nagabhushana }; 257756b2bdd1SGireesh Nagabhushana 257856b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_CMD_WR_OPCODE 24 257956b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_CMD_WR_OPCODE 0xff 258056b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 258156b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 258256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 258356b2bdd1SGireesh Nagabhushana 258456b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_CMD_WR_IMMDLEN 0 258556b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 258656b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 258756b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 258856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 258956b2bdd1SGireesh Nagabhushana 259056b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_CMD_WR_FLOWID 8 259156b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 259256b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 259356b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 259456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 259556b2bdd1SGireesh Nagabhushana 259656b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_CMD_WR_LEN16 0 259756b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_CMD_WR_LEN16 0xff 259856b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 259956b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_CMD_WR_LEN16(x) \ 260056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 260156b2bdd1SGireesh Nagabhushana 260256b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_CMD_WR_CP_EN 6 260356b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_CMD_WR_CP_EN 0x3 260456b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 260556b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 260656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 260756b2bdd1SGireesh Nagabhushana 260856b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_CMD_WR_CLASS 4 260956b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_CMD_WR_CLASS 0x3 261056b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 261156b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_CMD_WR_CLASS(x) \ 261256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 261356b2bdd1SGireesh Nagabhushana 261456b2bdd1SGireesh Nagabhushana struct fw_scsi_abrt_cls_wr { 261556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 261656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 261756b2bdd1SGireesh Nagabhushana __be64 cookie; 261856b2bdd1SGireesh Nagabhushana __be16 iqid; 261956b2bdd1SGireesh Nagabhushana __u8 tmo_val; 262056b2bdd1SGireesh Nagabhushana __u8 sub_opcode_to_chk_all_io; 262156b2bdd1SGireesh Nagabhushana __u8 r3[4]; 262256b2bdd1SGireesh Nagabhushana __be64 t_cookie; 262356b2bdd1SGireesh Nagabhushana }; 262456b2bdd1SGireesh Nagabhushana 262556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 262656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 262756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 262856b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 262956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 263056b2bdd1SGireesh Nagabhushana 263156b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 263256b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 263356b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 263456b2bdd1SGireesh Nagabhushana ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 263556b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 263656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 263756b2bdd1SGireesh Nagabhushana 263856b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 263956b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 264056b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 264156b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 264256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 264356b2bdd1SGireesh Nagabhushana 264456b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 264556b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 264656b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 264756b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 264856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 264956b2bdd1SGireesh Nagabhushana 265056b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 265156b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 265256b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 265356b2bdd1SGireesh Nagabhushana ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 265456b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 265556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 265656b2bdd1SGireesh Nagabhushana M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 265756b2bdd1SGireesh Nagabhushana 265856b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 265956b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 266056b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 266156b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 266256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 266356b2bdd1SGireesh Nagabhushana #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 266456b2bdd1SGireesh Nagabhushana 266556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 266656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 266756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 266856b2bdd1SGireesh Nagabhushana ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 266956b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 267056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 267156b2bdd1SGireesh Nagabhushana M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 267256b2bdd1SGireesh Nagabhushana #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 267356b2bdd1SGireesh Nagabhushana V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 267456b2bdd1SGireesh Nagabhushana 267556b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_acc_wr { 267656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 267756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 267856b2bdd1SGireesh Nagabhushana __be64 cookie; 267956b2bdd1SGireesh Nagabhushana __be16 iqid; 268056b2bdd1SGireesh Nagabhushana __u8 r3; 268156b2bdd1SGireesh Nagabhushana __u8 use_burst_len; 268256b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_acc_priv { 268356b2bdd1SGireesh Nagabhushana struct fcoe_tgt_acc_priv { 268456b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 268556b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 268656b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 268756b2bdd1SGireesh Nagabhushana } fcoe; 268856b2bdd1SGireesh Nagabhushana struct iscsi_tgt_acc_priv { 268956b2bdd1SGireesh Nagabhushana __u8 r4[4]; 269056b2bdd1SGireesh Nagabhushana } iscsi; 269156b2bdd1SGireesh Nagabhushana } u; 269256b2bdd1SGireesh Nagabhushana __be32 burst_len; 269356b2bdd1SGireesh Nagabhushana __be32 rel_off; 269456b2bdd1SGireesh Nagabhushana __be64 r5; 269556b2bdd1SGireesh Nagabhushana __be32 r6; 269656b2bdd1SGireesh Nagabhushana __be32 tot_xfer_len; 269756b2bdd1SGireesh Nagabhushana }; 269856b2bdd1SGireesh Nagabhushana 269956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 270056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 270156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 270256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 270356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 270456b2bdd1SGireesh Nagabhushana 270556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 270656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 270756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 270856b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 270956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 271056b2bdd1SGireesh Nagabhushana 271156b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 271256b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 271356b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 271456b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 271556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 271656b2bdd1SGireesh Nagabhushana 271756b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 271856b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 271956b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 272056b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 272156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 272256b2bdd1SGireesh Nagabhushana 272356b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 272456b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 272556b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 272656b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 272756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 272856b2bdd1SGireesh Nagabhushana 272956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 273056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 273156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 273256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 273356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 273456b2bdd1SGireesh Nagabhushana 273556b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_xmit_wr { 273656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 273756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 273856b2bdd1SGireesh Nagabhushana __be64 cookie; 273956b2bdd1SGireesh Nagabhushana __be16 iqid; 274056b2bdd1SGireesh Nagabhushana __u8 auto_rsp; 274156b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 274256b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_xmit_priv { 274356b2bdd1SGireesh Nagabhushana struct fcoe_tgt_xmit_priv { 274456b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 274556b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 274656b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 274756b2bdd1SGireesh Nagabhushana } fcoe; 274856b2bdd1SGireesh Nagabhushana struct iscsi_tgt_xmit_priv { 274956b2bdd1SGireesh Nagabhushana __u8 r3[4]; 275056b2bdd1SGireesh Nagabhushana } iscsi; 275156b2bdd1SGireesh Nagabhushana } u; 275256b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 275356b2bdd1SGireesh Nagabhushana __be32 r4; 275456b2bdd1SGireesh Nagabhushana __be64 r5; 275556b2bdd1SGireesh Nagabhushana __be32 r6; 275656b2bdd1SGireesh Nagabhushana __be32 tot_xfer_len; 275756b2bdd1SGireesh Nagabhushana }; 275856b2bdd1SGireesh Nagabhushana 275956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 276056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 276156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 276256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 276356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 276456b2bdd1SGireesh Nagabhushana 276556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 276656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 276756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 276856b2bdd1SGireesh Nagabhushana ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 276956b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 277056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 277156b2bdd1SGireesh Nagabhushana 277256b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 277356b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 277456b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 277556b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 277656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 277756b2bdd1SGireesh Nagabhushana 277856b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 277956b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 278056b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 278156b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 278256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 278356b2bdd1SGireesh Nagabhushana 278456b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 278556b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 278656b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 278756b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 278856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 278956b2bdd1SGireesh Nagabhushana 279056b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 279156b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 279256b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 279356b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 279456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 279556b2bdd1SGireesh Nagabhushana 279656b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_rsp_wr { 279756b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 279856b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 279956b2bdd1SGireesh Nagabhushana __be64 cookie; 280056b2bdd1SGireesh Nagabhushana __be16 iqid; 280156b2bdd1SGireesh Nagabhushana __u8 r3[2]; 280256b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_rsp_priv { 280356b2bdd1SGireesh Nagabhushana struct fcoe_tgt_rsp_priv { 280456b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 280556b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 280656b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 280756b2bdd1SGireesh Nagabhushana } fcoe; 280856b2bdd1SGireesh Nagabhushana struct iscsi_tgt_rsp_priv { 280956b2bdd1SGireesh Nagabhushana __u8 r4[4]; 281056b2bdd1SGireesh Nagabhushana } iscsi; 281156b2bdd1SGireesh Nagabhushana } u; 281256b2bdd1SGireesh Nagabhushana __u8 r5[8]; 281356b2bdd1SGireesh Nagabhushana }; 281456b2bdd1SGireesh Nagabhushana 281556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 281656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 281756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 281856b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 281956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 282056b2bdd1SGireesh Nagabhushana 282156b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 282256b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 282356b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 282456b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 282556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 282656b2bdd1SGireesh Nagabhushana 282756b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 282856b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 282956b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 283056b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 283156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 283256b2bdd1SGireesh Nagabhushana 283356b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 283456b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 283556b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 283656b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 283756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 283856b2bdd1SGireesh Nagabhushana 283956b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 284056b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 284156b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 284256b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 284356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 284456b2bdd1SGireesh Nagabhushana 284556b2bdd1SGireesh Nagabhushana #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 284656b2bdd1SGireesh Nagabhushana #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 284756b2bdd1SGireesh Nagabhushana #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 284856b2bdd1SGireesh Nagabhushana #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 284956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 285056b2bdd1SGireesh Nagabhushana 2851*de483253SVishal Kulkarni struct fw_pofcoe_tcb_wr { 2852*de483253SVishal Kulkarni __be32 op_compl; 2853*de483253SVishal Kulkarni __be32 equiq_to_len16; 2854*de483253SVishal Kulkarni __be64 cookie; 2855*de483253SVishal Kulkarni __be32 tid_to_port; 2856*de483253SVishal Kulkarni __be16 x_id; 2857*de483253SVishal Kulkarni __be16 vlan_id; 2858*de483253SVishal Kulkarni __be32 s_id; 2859*de483253SVishal Kulkarni __be32 d_id; 2860*de483253SVishal Kulkarni __be32 tag; 2861*de483253SVishal Kulkarni __be32 xfer_len; 2862*de483253SVishal Kulkarni __be32 r4; 2863*de483253SVishal Kulkarni __be16 r5; 2864*de483253SVishal Kulkarni __be16 iqid; 2865*de483253SVishal Kulkarni }; 2866*de483253SVishal Kulkarni 2867*de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_TID 12 2868*de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_TID 0xfffff 2869*de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2870*de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_TID(x) \ 2871*de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2872*de483253SVishal Kulkarni 2873*de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_ALLO 4 2874*de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2875*de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2876*de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2877*de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2878*de483253SVishal Kulkarni #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2879*de483253SVishal Kulkarni 2880*de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_FREE 3 2881*de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_FREE 0x1 2882*de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2883*de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_FREE(x) \ 2884*de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 2885*de483253SVishal Kulkarni #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 2886*de483253SVishal Kulkarni 2887*de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_PORT 0 2888*de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_PORT 0x7 2889*de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 2890*de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_PORT(x) \ 2891*de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 2892*de483253SVishal Kulkarni 2893*de483253SVishal Kulkarni struct fw_pofcoe_ulptx_wr { 2894*de483253SVishal Kulkarni __be32 op_pkd; 2895*de483253SVishal Kulkarni __be32 equiq_to_len16; 2896*de483253SVishal Kulkarni __u64 cookie; 2897*de483253SVishal Kulkarni }; 2898*de483253SVishal Kulkarni 2899*de483253SVishal Kulkarni 290056b2bdd1SGireesh Nagabhushana /* 290156b2bdd1SGireesh Nagabhushana * ******************* 290256b2bdd1SGireesh Nagabhushana * C O M M A N D s 290356b2bdd1SGireesh Nagabhushana * ******************* 290456b2bdd1SGireesh Nagabhushana */ 290556b2bdd1SGireesh Nagabhushana 290656b2bdd1SGireesh Nagabhushana /* 290756b2bdd1SGireesh Nagabhushana * The maximum length of time, in miliseconds, that we expect any firmware 290856b2bdd1SGireesh Nagabhushana * command to take to execute and return a reply to the host. The RESET 290956b2bdd1SGireesh Nagabhushana * and INITIALIZE commands can take a fair amount of time to execute but 291056b2bdd1SGireesh Nagabhushana * most execute in far less time than this maximum. This constant is used 291156b2bdd1SGireesh Nagabhushana * by host software to determine how long to wait for a firmware command 291256b2bdd1SGireesh Nagabhushana * reply before declaring the firmware as dead/unreachable ... 291356b2bdd1SGireesh Nagabhushana */ 291456b2bdd1SGireesh Nagabhushana #define FW_CMD_MAX_TIMEOUT 10000 291556b2bdd1SGireesh Nagabhushana 291656b2bdd1SGireesh Nagabhushana /* 291756b2bdd1SGireesh Nagabhushana * If a host driver does a HELLO and discovers that there's already a MASTER 291856b2bdd1SGireesh Nagabhushana * selected, we may have to wait for that MASTER to finish issuing RESET, 291956b2bdd1SGireesh Nagabhushana * configuration and INITIALIZE commands. Also, there's a possibility that 292056b2bdd1SGireesh Nagabhushana * our own HELLO may get lost if it happens right as the MASTER is issuign a 292156b2bdd1SGireesh Nagabhushana * RESET command, so we need to be willing to make a few retries of our HELLO. 292256b2bdd1SGireesh Nagabhushana */ 292356b2bdd1SGireesh Nagabhushana #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 292456b2bdd1SGireesh Nagabhushana #define FW_CMD_HELLO_RETRIES 3 292556b2bdd1SGireesh Nagabhushana 292656b2bdd1SGireesh Nagabhushana enum fw_cmd_opcodes { 292756b2bdd1SGireesh Nagabhushana FW_LDST_CMD = 0x01, 292856b2bdd1SGireesh Nagabhushana FW_RESET_CMD = 0x03, 292956b2bdd1SGireesh Nagabhushana FW_HELLO_CMD = 0x04, 293056b2bdd1SGireesh Nagabhushana FW_BYE_CMD = 0x05, 293156b2bdd1SGireesh Nagabhushana FW_INITIALIZE_CMD = 0x06, 293256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_CMD = 0x07, 293356b2bdd1SGireesh Nagabhushana FW_PARAMS_CMD = 0x08, 293456b2bdd1SGireesh Nagabhushana FW_PFVF_CMD = 0x09, 293556b2bdd1SGireesh Nagabhushana FW_IQ_CMD = 0x10, 293656b2bdd1SGireesh Nagabhushana FW_EQ_MNGT_CMD = 0x11, 293756b2bdd1SGireesh Nagabhushana FW_EQ_ETH_CMD = 0x12, 293856b2bdd1SGireesh Nagabhushana FW_EQ_CTRL_CMD = 0x13, 293956b2bdd1SGireesh Nagabhushana FW_EQ_OFLD_CMD = 0x21, 294056b2bdd1SGireesh Nagabhushana FW_VI_CMD = 0x14, 294156b2bdd1SGireesh Nagabhushana FW_VI_MAC_CMD = 0x15, 294256b2bdd1SGireesh Nagabhushana FW_VI_RXMODE_CMD = 0x16, 294356b2bdd1SGireesh Nagabhushana FW_VI_ENABLE_CMD = 0x17, 294456b2bdd1SGireesh Nagabhushana FW_VI_STATS_CMD = 0x1a, 294556b2bdd1SGireesh Nagabhushana FW_ACL_MAC_CMD = 0x18, 294656b2bdd1SGireesh Nagabhushana FW_ACL_VLAN_CMD = 0x19, 294756b2bdd1SGireesh Nagabhushana FW_PORT_CMD = 0x1b, 294856b2bdd1SGireesh Nagabhushana FW_PORT_STATS_CMD = 0x1c, 294956b2bdd1SGireesh Nagabhushana FW_PORT_LB_STATS_CMD = 0x1d, 295056b2bdd1SGireesh Nagabhushana FW_PORT_TRACE_CMD = 0x1e, 295156b2bdd1SGireesh Nagabhushana FW_PORT_TRACE_MMAP_CMD = 0x1f, 295256b2bdd1SGireesh Nagabhushana FW_RSS_IND_TBL_CMD = 0x20, 295356b2bdd1SGireesh Nagabhushana FW_RSS_GLB_CONFIG_CMD = 0x22, 295456b2bdd1SGireesh Nagabhushana FW_RSS_VI_CONFIG_CMD = 0x23, 295556b2bdd1SGireesh Nagabhushana FW_SCHED_CMD = 0x24, 295656b2bdd1SGireesh Nagabhushana FW_DEVLOG_CMD = 0x25, 295756b2bdd1SGireesh Nagabhushana FW_WATCHDOG_CMD = 0x27, 295856b2bdd1SGireesh Nagabhushana FW_CLIP_CMD = 0x28, 295956b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD = 0x26, 296056b2bdd1SGireesh Nagabhushana FW_FCOE_RES_INFO_CMD = 0x31, 296156b2bdd1SGireesh Nagabhushana FW_FCOE_LINK_CMD = 0x32, 296256b2bdd1SGireesh Nagabhushana FW_FCOE_VNP_CMD = 0x33, 296356b2bdd1SGireesh Nagabhushana FW_FCOE_SPARAMS_CMD = 0x35, 296456b2bdd1SGireesh Nagabhushana FW_FCOE_STATS_CMD = 0x37, 296556b2bdd1SGireesh Nagabhushana FW_FCOE_FCF_CMD = 0x38, 296656b2bdd1SGireesh Nagabhushana FW_LASTC2E_CMD = 0x40, 296756b2bdd1SGireesh Nagabhushana FW_ERROR_CMD = 0x80, 296856b2bdd1SGireesh Nagabhushana FW_DEBUG_CMD = 0x81, 296956b2bdd1SGireesh Nagabhushana }; 297056b2bdd1SGireesh Nagabhushana 297156b2bdd1SGireesh Nagabhushana enum fw_cmd_cap { 297256b2bdd1SGireesh Nagabhushana FW_CMD_CAP_PF = 0x01, 297356b2bdd1SGireesh Nagabhushana FW_CMD_CAP_DMAQ = 0x02, 297456b2bdd1SGireesh Nagabhushana FW_CMD_CAP_PORT = 0x04, 297556b2bdd1SGireesh Nagabhushana FW_CMD_CAP_PORTPROMISC = 0x08, 297656b2bdd1SGireesh Nagabhushana FW_CMD_CAP_PORTSTATS = 0x10, 297756b2bdd1SGireesh Nagabhushana FW_CMD_CAP_VF = 0x80, 297856b2bdd1SGireesh Nagabhushana }; 297956b2bdd1SGireesh Nagabhushana 298056b2bdd1SGireesh Nagabhushana /* 298156b2bdd1SGireesh Nagabhushana * Generic command header flit0 298256b2bdd1SGireesh Nagabhushana */ 298356b2bdd1SGireesh Nagabhushana struct fw_cmd_hdr { 298456b2bdd1SGireesh Nagabhushana __be32 hi; 298556b2bdd1SGireesh Nagabhushana __be32 lo; 298656b2bdd1SGireesh Nagabhushana }; 298756b2bdd1SGireesh Nagabhushana 298856b2bdd1SGireesh Nagabhushana #define S_FW_CMD_OP 24 298956b2bdd1SGireesh Nagabhushana #define M_FW_CMD_OP 0xff 299056b2bdd1SGireesh Nagabhushana #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 299156b2bdd1SGireesh Nagabhushana #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 299256b2bdd1SGireesh Nagabhushana 299356b2bdd1SGireesh Nagabhushana #define S_FW_CMD_REQUEST 23 299456b2bdd1SGireesh Nagabhushana #define M_FW_CMD_REQUEST 0x1 299556b2bdd1SGireesh Nagabhushana #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 299656b2bdd1SGireesh Nagabhushana #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 299756b2bdd1SGireesh Nagabhushana #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 299856b2bdd1SGireesh Nagabhushana 299956b2bdd1SGireesh Nagabhushana #define S_FW_CMD_READ 22 300056b2bdd1SGireesh Nagabhushana #define M_FW_CMD_READ 0x1 300156b2bdd1SGireesh Nagabhushana #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 300256b2bdd1SGireesh Nagabhushana #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 300356b2bdd1SGireesh Nagabhushana #define F_FW_CMD_READ V_FW_CMD_READ(1U) 300456b2bdd1SGireesh Nagabhushana 300556b2bdd1SGireesh Nagabhushana #define S_FW_CMD_WRITE 21 300656b2bdd1SGireesh Nagabhushana #define M_FW_CMD_WRITE 0x1 300756b2bdd1SGireesh Nagabhushana #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 300856b2bdd1SGireesh Nagabhushana #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 300956b2bdd1SGireesh Nagabhushana #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 301056b2bdd1SGireesh Nagabhushana 301156b2bdd1SGireesh Nagabhushana #define S_FW_CMD_EXEC 20 301256b2bdd1SGireesh Nagabhushana #define M_FW_CMD_EXEC 0x1 301356b2bdd1SGireesh Nagabhushana #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 301456b2bdd1SGireesh Nagabhushana #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 301556b2bdd1SGireesh Nagabhushana #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 301656b2bdd1SGireesh Nagabhushana 301756b2bdd1SGireesh Nagabhushana #define S_FW_CMD_RAMASK 20 301856b2bdd1SGireesh Nagabhushana #define M_FW_CMD_RAMASK 0xf 301956b2bdd1SGireesh Nagabhushana #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 302056b2bdd1SGireesh Nagabhushana #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 302156b2bdd1SGireesh Nagabhushana 302256b2bdd1SGireesh Nagabhushana #define S_FW_CMD_RETVAL 8 302356b2bdd1SGireesh Nagabhushana #define M_FW_CMD_RETVAL 0xff 302456b2bdd1SGireesh Nagabhushana #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 302556b2bdd1SGireesh Nagabhushana #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 302656b2bdd1SGireesh Nagabhushana 302756b2bdd1SGireesh Nagabhushana #define S_FW_CMD_LEN16 0 302856b2bdd1SGireesh Nagabhushana #define M_FW_CMD_LEN16 0xff 302956b2bdd1SGireesh Nagabhushana #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 303056b2bdd1SGireesh Nagabhushana #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 303156b2bdd1SGireesh Nagabhushana 303256b2bdd1SGireesh Nagabhushana #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof (fw_struct) / 16) 303356b2bdd1SGireesh Nagabhushana 303456b2bdd1SGireesh Nagabhushana /* 303556b2bdd1SGireesh Nagabhushana * address spaces 303656b2bdd1SGireesh Nagabhushana */ 303756b2bdd1SGireesh Nagabhushana enum fw_ldst_addrspc { 303856b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 303956b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 304056b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 304156b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 304256b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 304356b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_TP_PIO = 0x0010, 304456b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 304556b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_TP_MIB = 0x0012, 304656b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_MDIO = 0x0018, 304756b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_MPS = 0x0020, 304856b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FUNC = 0x0028, 304956b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3050*de483253SVishal Kulkarni FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 305156b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_LE = 0x0030, 3052*de483253SVishal Kulkarni FW_LDST_ADDRSPC_I2C = 0x0038, 3053*de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3054*de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3055*de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 305656b2bdd1SGireesh Nagabhushana }; 305756b2bdd1SGireesh Nagabhushana 305856b2bdd1SGireesh Nagabhushana /* 305956b2bdd1SGireesh Nagabhushana * MDIO VSC8634 register access control field 306056b2bdd1SGireesh Nagabhushana */ 306156b2bdd1SGireesh Nagabhushana enum fw_ldst_mdio_vsc8634_aid { 306256b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_STANDARD, 306356b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_EXTENDED, 306456b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_GPIO 306556b2bdd1SGireesh Nagabhushana }; 306656b2bdd1SGireesh Nagabhushana 306756b2bdd1SGireesh Nagabhushana enum fw_ldst_mps_fid { 306856b2bdd1SGireesh Nagabhushana FW_LDST_MPS_ATRB, 306956b2bdd1SGireesh Nagabhushana FW_LDST_MPS_RPLC 307056b2bdd1SGireesh Nagabhushana }; 307156b2bdd1SGireesh Nagabhushana 307256b2bdd1SGireesh Nagabhushana enum fw_ldst_func_access_ctl { 307356b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_ACC_CTL_VIID, 307456b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_ACC_CTL_FID 307556b2bdd1SGireesh Nagabhushana }; 307656b2bdd1SGireesh Nagabhushana 307756b2bdd1SGireesh Nagabhushana enum fw_ldst_func_mod_index { 307856b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_MPS 307956b2bdd1SGireesh Nagabhushana }; 308056b2bdd1SGireesh Nagabhushana 308156b2bdd1SGireesh Nagabhushana struct fw_ldst_cmd { 308256b2bdd1SGireesh Nagabhushana __be32 op_to_addrspace; 308356b2bdd1SGireesh Nagabhushana __be32 cycles_to_len16; 308456b2bdd1SGireesh Nagabhushana union fw_ldst { 308556b2bdd1SGireesh Nagabhushana struct fw_ldst_addrval { 308656b2bdd1SGireesh Nagabhushana __be32 addr; 308756b2bdd1SGireesh Nagabhushana __be32 val; 308856b2bdd1SGireesh Nagabhushana } addrval; 308956b2bdd1SGireesh Nagabhushana struct fw_ldst_idctxt { 309056b2bdd1SGireesh Nagabhushana __be32 physid; 309156b2bdd1SGireesh Nagabhushana __be32 msg_ctxtflush; 309256b2bdd1SGireesh Nagabhushana __be32 ctxt_data7; 309356b2bdd1SGireesh Nagabhushana __be32 ctxt_data6; 309456b2bdd1SGireesh Nagabhushana __be32 ctxt_data5; 309556b2bdd1SGireesh Nagabhushana __be32 ctxt_data4; 309656b2bdd1SGireesh Nagabhushana __be32 ctxt_data3; 309756b2bdd1SGireesh Nagabhushana __be32 ctxt_data2; 309856b2bdd1SGireesh Nagabhushana __be32 ctxt_data1; 309956b2bdd1SGireesh Nagabhushana __be32 ctxt_data0; 310056b2bdd1SGireesh Nagabhushana } idctxt; 310156b2bdd1SGireesh Nagabhushana struct fw_ldst_mdio { 310256b2bdd1SGireesh Nagabhushana __be16 paddr_mmd; 310356b2bdd1SGireesh Nagabhushana __be16 raddr; 310456b2bdd1SGireesh Nagabhushana __be16 vctl; 310556b2bdd1SGireesh Nagabhushana __be16 rval; 310656b2bdd1SGireesh Nagabhushana } mdio; 310756b2bdd1SGireesh Nagabhushana struct fw_ldst_mps { 310856b2bdd1SGireesh Nagabhushana __be16 fid_ctl; 310956b2bdd1SGireesh Nagabhushana __be16 rplcpf_pkd; 311056b2bdd1SGireesh Nagabhushana __be32 rplc127_96; 311156b2bdd1SGireesh Nagabhushana __be32 rplc95_64; 311256b2bdd1SGireesh Nagabhushana __be32 rplc63_32; 311356b2bdd1SGireesh Nagabhushana __be32 rplc31_0; 311456b2bdd1SGireesh Nagabhushana __be32 atrb; 311556b2bdd1SGireesh Nagabhushana __be16 vlan[16]; 311656b2bdd1SGireesh Nagabhushana } mps; 311756b2bdd1SGireesh Nagabhushana struct fw_ldst_func { 311856b2bdd1SGireesh Nagabhushana __u8 access_ctl; 311956b2bdd1SGireesh Nagabhushana __u8 mod_index; 312056b2bdd1SGireesh Nagabhushana __be16 ctl_id; 312156b2bdd1SGireesh Nagabhushana __be32 offset; 312256b2bdd1SGireesh Nagabhushana __be64 data0; 312356b2bdd1SGireesh Nagabhushana __be64 data1; 312456b2bdd1SGireesh Nagabhushana } func; 312556b2bdd1SGireesh Nagabhushana struct fw_ldst_pcie { 312656b2bdd1SGireesh Nagabhushana __u8 ctrl_to_fn; 312756b2bdd1SGireesh Nagabhushana __u8 bnum; 312856b2bdd1SGireesh Nagabhushana __u8 r; 312956b2bdd1SGireesh Nagabhushana __u8 ext_r; 313056b2bdd1SGireesh Nagabhushana __u8 select_naccess; 313156b2bdd1SGireesh Nagabhushana __u8 pcie_fn; 313256b2bdd1SGireesh Nagabhushana __be16 nset_pkd; 313356b2bdd1SGireesh Nagabhushana __be32 data[12]; 313456b2bdd1SGireesh Nagabhushana } pcie; 3135*de483253SVishal Kulkarni struct fw_ldst_i2c_deprecated { 313656b2bdd1SGireesh Nagabhushana __u8 pid_pkd; 313756b2bdd1SGireesh Nagabhushana __u8 base; 313856b2bdd1SGireesh Nagabhushana __u8 boffset; 313956b2bdd1SGireesh Nagabhushana __u8 data; 314056b2bdd1SGireesh Nagabhushana __be32 r9; 3141*de483253SVishal Kulkarni } i2c_deprecated; 3142*de483253SVishal Kulkarni struct fw_ldst_i2c { 3143*de483253SVishal Kulkarni __u8 pid; 3144*de483253SVishal Kulkarni __u8 did; 3145*de483253SVishal Kulkarni __u8 boffset; 3146*de483253SVishal Kulkarni __u8 blen; 3147*de483253SVishal Kulkarni __be32 r9; 3148*de483253SVishal Kulkarni __u8 data[48]; 3149*de483253SVishal Kulkarni } i2c; 315056b2bdd1SGireesh Nagabhushana struct fw_ldst_le { 3151*de483253SVishal Kulkarni __be32 index; 3152*de483253SVishal Kulkarni __be32 r9; 3153*de483253SVishal Kulkarni __u8 val[33]; 3154*de483253SVishal Kulkarni __u8 r11[7]; 315556b2bdd1SGireesh Nagabhushana } le; 315656b2bdd1SGireesh Nagabhushana } u; 315756b2bdd1SGireesh Nagabhushana }; 315856b2bdd1SGireesh Nagabhushana 315956b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_ADDRSPACE 0 316056b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_ADDRSPACE 0xff 316156b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 316256b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_ADDRSPACE(x) \ 316356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 316456b2bdd1SGireesh Nagabhushana 316556b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_CYCLES 16 316656b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_CYCLES 0xffff 316756b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 316856b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_CYCLES(x) \ 316956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 317056b2bdd1SGireesh Nagabhushana 317156b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_MSG 31 317256b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_MSG 0x1 317356b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 317456b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_MSG(x) \ 317556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 317656b2bdd1SGireesh Nagabhushana #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 317756b2bdd1SGireesh Nagabhushana 317856b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_CTXTFLUSH 30 317956b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_CTXTFLUSH 0x1 318056b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 318156b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 318256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 318356b2bdd1SGireesh Nagabhushana #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 318456b2bdd1SGireesh Nagabhushana 318556b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_PADDR 8 318656b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_PADDR 0x1f 318756b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 318856b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_PADDR(x) \ 318956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 319056b2bdd1SGireesh Nagabhushana 319156b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_MMD 0 319256b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_MMD 0x1f 319356b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 319456b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_MMD(x) \ 319556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 319656b2bdd1SGireesh Nagabhushana 319756b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_FID 15 319856b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_FID 0x1 319956b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 320056b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_FID(x) \ 320156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 320256b2bdd1SGireesh Nagabhushana #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 320356b2bdd1SGireesh Nagabhushana 320456b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_CTL 0 320556b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_CTL 0x7fff 320656b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 320756b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_CTL(x) \ 320856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 320956b2bdd1SGireesh Nagabhushana 321056b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_RPLCPF 0 321156b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_RPLCPF 0xff 321256b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 321356b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_RPLCPF(x) \ 321456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 321556b2bdd1SGireesh Nagabhushana 321656b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_CTRL 7 321756b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_CTRL 0x1 321856b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 321956b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_CTRL(x) \ 322056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 322156b2bdd1SGireesh Nagabhushana #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 322256b2bdd1SGireesh Nagabhushana 322356b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_LC 4 322456b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_LC 0x1 322556b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 322656b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 322756b2bdd1SGireesh Nagabhushana #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 322856b2bdd1SGireesh Nagabhushana 322956b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_AI 3 323056b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_AI 0x1 323156b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 323256b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 323356b2bdd1SGireesh Nagabhushana #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 323456b2bdd1SGireesh Nagabhushana 323556b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_FN 0 323656b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_FN 0x7 323756b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 323856b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 323956b2bdd1SGireesh Nagabhushana 324056b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_SELECT 4 324156b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_SELECT 0xf 324256b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 324356b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_SELECT(x) \ 324456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 324556b2bdd1SGireesh Nagabhushana 324656b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_NACCESS 0 324756b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_NACCESS 0xf 324856b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 324956b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_NACCESS(x) \ 325056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 325156b2bdd1SGireesh Nagabhushana 325256b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_NSET 14 325356b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_NSET 0x3 325456b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 325556b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_NSET(x) \ 325656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 325756b2bdd1SGireesh Nagabhushana 325856b2bdd1SGireesh Nagabhushana #define S_FW_LDST_CMD_PID 6 325956b2bdd1SGireesh Nagabhushana #define M_FW_LDST_CMD_PID 0x3 326056b2bdd1SGireesh Nagabhushana #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 326156b2bdd1SGireesh Nagabhushana #define G_FW_LDST_CMD_PID(x) \ 326256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 326356b2bdd1SGireesh Nagabhushana 326456b2bdd1SGireesh Nagabhushana struct fw_reset_cmd { 326556b2bdd1SGireesh Nagabhushana __be32 op_to_write; 326656b2bdd1SGireesh Nagabhushana __be32 retval_len16; 326756b2bdd1SGireesh Nagabhushana __be32 val; 326856b2bdd1SGireesh Nagabhushana __be32 halt_pkd; 326956b2bdd1SGireesh Nagabhushana }; 327056b2bdd1SGireesh Nagabhushana 327156b2bdd1SGireesh Nagabhushana #define S_FW_RESET_CMD_HALT 31 327256b2bdd1SGireesh Nagabhushana #define M_FW_RESET_CMD_HALT 0x1 327356b2bdd1SGireesh Nagabhushana #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 327456b2bdd1SGireesh Nagabhushana #define G_FW_RESET_CMD_HALT(x) \ 327556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 327656b2bdd1SGireesh Nagabhushana #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 327756b2bdd1SGireesh Nagabhushana 327856b2bdd1SGireesh Nagabhushana enum { 327956b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_OS = 0, 328056b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_PREOS0 = 1, 328156b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_PREOS1 = 2, 328256b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_POSTOS = 3, 328356b2bdd1SGireesh Nagabhushana }; 328456b2bdd1SGireesh Nagabhushana 328556b2bdd1SGireesh Nagabhushana struct fw_hello_cmd { 328656b2bdd1SGireesh Nagabhushana __be32 op_to_write; 328756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 328856b2bdd1SGireesh Nagabhushana __be32 err_to_clearinit; 328956b2bdd1SGireesh Nagabhushana __be32 fwrev; 329056b2bdd1SGireesh Nagabhushana }; 329156b2bdd1SGireesh Nagabhushana 329256b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_ERR 31 329356b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_ERR 0x1 329456b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 329556b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_ERR(x) \ 329656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 329756b2bdd1SGireesh Nagabhushana #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 329856b2bdd1SGireesh Nagabhushana 329956b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_INIT 30 330056b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_INIT 0x1 330156b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 330256b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_INIT(x) \ 330356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 330456b2bdd1SGireesh Nagabhushana #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 330556b2bdd1SGireesh Nagabhushana 330656b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_MASTERDIS 29 330756b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_MASTERDIS 0x1 330856b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 330956b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_MASTERDIS(x) \ 331056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 331156b2bdd1SGireesh Nagabhushana #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 331256b2bdd1SGireesh Nagabhushana 331356b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_MASTERFORCE 28 331456b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_MASTERFORCE 0x1 331556b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 331656b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 331756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 331856b2bdd1SGireesh Nagabhushana #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 331956b2bdd1SGireesh Nagabhushana 332056b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_MBMASTER 24 332156b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_MBMASTER 0xf 332256b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 332356b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_MBMASTER(x) \ 332456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 332556b2bdd1SGireesh Nagabhushana 332656b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 332756b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 332856b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 332956b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 333056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 333156b2bdd1SGireesh Nagabhushana #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 333256b2bdd1SGireesh Nagabhushana 333356b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_MBASYNCNOT 20 333456b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 333556b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 333656b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 333756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 333856b2bdd1SGireesh Nagabhushana 333956b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_STAGE 17 334056b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_STAGE 0x7 334156b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 334256b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_STAGE(x) \ 334356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 334456b2bdd1SGireesh Nagabhushana 334556b2bdd1SGireesh Nagabhushana #define S_FW_HELLO_CMD_CLEARINIT 16 334656b2bdd1SGireesh Nagabhushana #define M_FW_HELLO_CMD_CLEARINIT 0x1 334756b2bdd1SGireesh Nagabhushana #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 334856b2bdd1SGireesh Nagabhushana #define G_FW_HELLO_CMD_CLEARINIT(x) \ 334956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 335056b2bdd1SGireesh Nagabhushana #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 335156b2bdd1SGireesh Nagabhushana 335256b2bdd1SGireesh Nagabhushana struct fw_bye_cmd { 335356b2bdd1SGireesh Nagabhushana __be32 op_to_write; 335456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 335556b2bdd1SGireesh Nagabhushana __be64 r3; 335656b2bdd1SGireesh Nagabhushana }; 335756b2bdd1SGireesh Nagabhushana 335856b2bdd1SGireesh Nagabhushana struct fw_initialize_cmd { 335956b2bdd1SGireesh Nagabhushana __be32 op_to_write; 336056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 336156b2bdd1SGireesh Nagabhushana __be64 r3; 336256b2bdd1SGireesh Nagabhushana }; 336356b2bdd1SGireesh Nagabhushana 336456b2bdd1SGireesh Nagabhushana enum fw_caps_config_hm { 336556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 336656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PL = 0x00000002, 336756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SGE = 0x00000004, 336856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_CIM = 0x00000008, 336956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 337056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_TP = 0x00000020, 337156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 337256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 337356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 337456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MC = 0x00000200, 337556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_LE = 0x00000400, 337656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MPS = 0x00000800, 337756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 337856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 337956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 338056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MI = 0x00008000, 338156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 338256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 338356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SMB = 0x00040000, 338456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MA = 0x00080000, 338556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 338656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMU = 0x00200000, 338756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_UART = 0x00400000, 338856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SF = 0x00800000, 338956b2bdd1SGireesh Nagabhushana }; 339056b2bdd1SGireesh Nagabhushana 339156b2bdd1SGireesh Nagabhushana /* 339256b2bdd1SGireesh Nagabhushana * The VF Register Map. 339356b2bdd1SGireesh Nagabhushana * 339456b2bdd1SGireesh Nagabhushana * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 339556b2bdd1SGireesh Nagabhushana * bus module (PL) and CPU Interface Module (CIM) components are mapped via 339656b2bdd1SGireesh Nagabhushana * the Slice to Module Map Table (see below) in the Physical Function Register 339756b2bdd1SGireesh Nagabhushana * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 339856b2bdd1SGireesh Nagabhushana * and Offset registers in the PF Register Map. The MBDATA base address is 339956b2bdd1SGireesh Nagabhushana * quite constrained as it determines the Mailbox Data addresses for both PFs 340056b2bdd1SGireesh Nagabhushana * and VFs, and therefore must fit in both the VF and PF Register Maps without 340156b2bdd1SGireesh Nagabhushana * overlapping other registers. 340256b2bdd1SGireesh Nagabhushana */ 340356b2bdd1SGireesh Nagabhushana #define FW_T4VF_SGE_BASE_ADDR 0x0000 340456b2bdd1SGireesh Nagabhushana #define FW_T4VF_MPS_BASE_ADDR 0x0100 340556b2bdd1SGireesh Nagabhushana #define FW_T4VF_PL_BASE_ADDR 0x0200 340656b2bdd1SGireesh Nagabhushana #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 340756b2bdd1SGireesh Nagabhushana #define FW_T4VF_CIM_BASE_ADDR 0x0300 340856b2bdd1SGireesh Nagabhushana 340956b2bdd1SGireesh Nagabhushana #define FW_T4VF_REGMAP_START 0x0000 341056b2bdd1SGireesh Nagabhushana #define FW_T4VF_REGMAP_SIZE 0x0400 341156b2bdd1SGireesh Nagabhushana 341256b2bdd1SGireesh Nagabhushana enum fw_caps_config_nbm { 341356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 341456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 341556b2bdd1SGireesh Nagabhushana }; 341656b2bdd1SGireesh Nagabhushana 341756b2bdd1SGireesh Nagabhushana enum fw_caps_config_link { 341856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 341956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 342056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 342156b2bdd1SGireesh Nagabhushana }; 342256b2bdd1SGireesh Nagabhushana 342356b2bdd1SGireesh Nagabhushana enum fw_caps_config_switch { 342456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 342556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 342656b2bdd1SGireesh Nagabhushana }; 342756b2bdd1SGireesh Nagabhushana 342856b2bdd1SGireesh Nagabhushana enum fw_caps_config_nic { 342956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC = 0x00000001, 343056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_VM = 0x00000002, 343156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 343256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_UM = 0x00000008, 343356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 343456b2bdd1SGireesh Nagabhushana }; 343556b2bdd1SGireesh Nagabhushana 343656b2bdd1SGireesh Nagabhushana enum fw_caps_config_toe { 343756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_TOE = 0x00000001, 343856b2bdd1SGireesh Nagabhushana }; 343956b2bdd1SGireesh Nagabhushana 344056b2bdd1SGireesh Nagabhushana enum fw_caps_config_rdma { 344156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 344256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 344356b2bdd1SGireesh Nagabhushana }; 344456b2bdd1SGireesh Nagabhushana 344556b2bdd1SGireesh Nagabhushana enum fw_caps_config_iscsi { 344656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 344756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 344856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 344956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 345056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 345156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 345256b2bdd1SGireesh Nagabhushana 345356b2bdd1SGireesh Nagabhushana }; 345456b2bdd1SGireesh Nagabhushana 345556b2bdd1SGireesh Nagabhushana enum fw_caps_config_fcoe { 345656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 345756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 345856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3459*de483253SVishal Kulkarni FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3460*de483253SVishal Kulkarni FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 346156b2bdd1SGireesh Nagabhushana }; 346256b2bdd1SGireesh Nagabhushana 346356b2bdd1SGireesh Nagabhushana enum fw_memtype_cf { 346456b2bdd1SGireesh Nagabhushana FW_MEMTYPE_CF_EDC0 = 0x0, 346556b2bdd1SGireesh Nagabhushana FW_MEMTYPE_CF_EDC1 = 0x1, 346656b2bdd1SGireesh Nagabhushana FW_MEMTYPE_CF_EXTMEM = 0x2, 346756b2bdd1SGireesh Nagabhushana FW_MEMTYPE_CF_FLASH = 0x4, 346856b2bdd1SGireesh Nagabhushana FW_MEMTYPE_CF_INTERNAL = 0x5, 3469*de483253SVishal Kulkarni FW_MEMTYPE_CF_EXTMEM1 = 0x6, 347056b2bdd1SGireesh Nagabhushana }; 347156b2bdd1SGireesh Nagabhushana 347256b2bdd1SGireesh Nagabhushana struct fw_caps_config_cmd { 347356b2bdd1SGireesh Nagabhushana __be32 op_to_write; 347456b2bdd1SGireesh Nagabhushana __be32 cfvalid_to_len16; 347556b2bdd1SGireesh Nagabhushana __be32 r2; 347656b2bdd1SGireesh Nagabhushana __be32 hwmbitmap; 347756b2bdd1SGireesh Nagabhushana __be16 nbmcaps; 347856b2bdd1SGireesh Nagabhushana __be16 linkcaps; 347956b2bdd1SGireesh Nagabhushana __be16 switchcaps; 348056b2bdd1SGireesh Nagabhushana __be16 r3; 348156b2bdd1SGireesh Nagabhushana __be16 niccaps; 348256b2bdd1SGireesh Nagabhushana __be16 toecaps; 348356b2bdd1SGireesh Nagabhushana __be16 rdmacaps; 348456b2bdd1SGireesh Nagabhushana __be16 r4; 348556b2bdd1SGireesh Nagabhushana __be16 iscsicaps; 348656b2bdd1SGireesh Nagabhushana __be16 fcoecaps; 348756b2bdd1SGireesh Nagabhushana __be32 cfcsum; 348856b2bdd1SGireesh Nagabhushana __be32 finiver; 348956b2bdd1SGireesh Nagabhushana __be32 finicsum; 349056b2bdd1SGireesh Nagabhushana }; 349156b2bdd1SGireesh Nagabhushana 349256b2bdd1SGireesh Nagabhushana #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 349356b2bdd1SGireesh Nagabhushana #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 349456b2bdd1SGireesh Nagabhushana #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 349556b2bdd1SGireesh Nagabhushana #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 349656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 349756b2bdd1SGireesh Nagabhushana #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 349856b2bdd1SGireesh Nagabhushana 349956b2bdd1SGireesh Nagabhushana #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 350056b2bdd1SGireesh Nagabhushana #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 350156b2bdd1SGireesh Nagabhushana #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 350256b2bdd1SGireesh Nagabhushana ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 350356b2bdd1SGireesh Nagabhushana #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 350456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 350556b2bdd1SGireesh Nagabhushana M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 350656b2bdd1SGireesh Nagabhushana 350756b2bdd1SGireesh Nagabhushana #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 350856b2bdd1SGireesh Nagabhushana #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 350956b2bdd1SGireesh Nagabhushana #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 351056b2bdd1SGireesh Nagabhushana ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 351156b2bdd1SGireesh Nagabhushana #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 351256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 351356b2bdd1SGireesh Nagabhushana M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 351456b2bdd1SGireesh Nagabhushana 351556b2bdd1SGireesh Nagabhushana /* 351656b2bdd1SGireesh Nagabhushana * params command mnemonics 351756b2bdd1SGireesh Nagabhushana */ 351856b2bdd1SGireesh Nagabhushana enum fw_params_mnem { 351956b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_DEV = 1, /* device params */ 352056b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_PFVF = 2, /* function params */ 352156b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_REG = 3, /* limited register access */ 352256b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 352356b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_LAST 352456b2bdd1SGireesh Nagabhushana }; 352556b2bdd1SGireesh Nagabhushana 352656b2bdd1SGireesh Nagabhushana /* 352756b2bdd1SGireesh Nagabhushana * device parameters 352856b2bdd1SGireesh Nagabhushana */ 352956b2bdd1SGireesh Nagabhushana enum fw_params_param_dev { 353056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 353156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 353256b2bdd1SGireesh Nagabhushana /* reads the number of TIDs allocated by the device's Lookup Engine */ 353356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_NTID = 0x02, 353456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 353556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 353656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 353756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 353856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 353956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 354056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 354156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3542*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3543*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3544*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_CF = 0x0D, 3545*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3546*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3547*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3548*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3549*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 3550*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 3551*de483253SVishal Kulkarni */ 3552*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 3553*de483253SVishal Kulkarni */ 3554*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 3555*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 3556*de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 355756b2bdd1SGireesh Nagabhushana }; 355856b2bdd1SGireesh Nagabhushana 355956b2bdd1SGireesh Nagabhushana /* 356056b2bdd1SGireesh Nagabhushana * physical and virtual function parameters 356156b2bdd1SGireesh Nagabhushana */ 356256b2bdd1SGireesh Nagabhushana enum fw_params_param_pfvf { 356356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 356456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 356556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 356656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 356756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 356856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 356956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 357056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 357156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 357256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 357356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 357456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 357556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 357656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 357756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 357856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 357956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 358056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 358156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 358256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 358356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 358456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 358556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 358656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 358756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 358856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 358956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_VIID = 0x24, 359056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 359156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 359256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 359356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 359456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 359556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 359656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 359756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 359856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 359956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 360056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3601*de483253SVishal Kulkarni FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3602*de483253SVishal Kulkarni FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 360356b2bdd1SGireesh Nagabhushana }; 360456b2bdd1SGireesh Nagabhushana 360556b2bdd1SGireesh Nagabhushana /* 360656b2bdd1SGireesh Nagabhushana * dma queue parameters 360756b2bdd1SGireesh Nagabhushana */ 360856b2bdd1SGireesh Nagabhushana enum fw_params_param_dmaq { 360956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 361056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3611*de483253SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 361256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 361356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 361456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3615*de483253SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 3616*de483253SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 361756b2bdd1SGireesh Nagabhushana }; 361856b2bdd1SGireesh Nagabhushana 361956b2bdd1SGireesh Nagabhushana /* 362056b2bdd1SGireesh Nagabhushana * dev bypass parameters; actions and modes 362156b2bdd1SGireesh Nagabhushana */ 362256b2bdd1SGireesh Nagabhushana enum fw_params_param_dev_bypass { 362356b2bdd1SGireesh Nagabhushana 362456b2bdd1SGireesh Nagabhushana /* actions */ 362556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 362656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 362756b2bdd1SGireesh Nagabhushana 362856b2bdd1SGireesh Nagabhushana /* modes */ 362956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 363056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 363156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 363256b2bdd1SGireesh Nagabhushana }; 363356b2bdd1SGireesh Nagabhushana 3634*de483253SVishal Kulkarni enum fw_params_phyfw_actions { 3635*de483253SVishal Kulkarni FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, 3636*de483253SVishal Kulkarni FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, 3637*de483253SVishal Kulkarni }; 3638*de483253SVishal Kulkarni 3639*de483253SVishal Kulkarni enum fw_params_param_dev_diag { 3640*de483253SVishal Kulkarni FW_PARAM_DEV_DIAG_TMP = 0x00, 3641*de483253SVishal Kulkarni FW_PARAM_DEV_DIAG_VDD = 0x01, 3642*de483253SVishal Kulkarni }; 3643*de483253SVishal Kulkarni 364456b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_MNEM 24 364556b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_MNEM 0xff 364656b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 364756b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_MNEM(x) \ 364856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 364956b2bdd1SGireesh Nagabhushana 365056b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_PARAM_X 16 365156b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_PARAM_X 0xff 365256b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 365356b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_PARAM_X(x) \ 365456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 365556b2bdd1SGireesh Nagabhushana 365656b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_PARAM_Y 8 365756b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_PARAM_Y 0xff 365856b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 365956b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_PARAM_Y(x) \ 366056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 366156b2bdd1SGireesh Nagabhushana 366256b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_PARAM_Z 0 366356b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_PARAM_Z 0xff 366456b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 366556b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_PARAM_Z(x) \ 366656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 366756b2bdd1SGireesh Nagabhushana 366856b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_PARAM_XYZ 0 366956b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_PARAM_XYZ 0xffffff 367056b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 367156b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_PARAM_XYZ(x) \ 367256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 367356b2bdd1SGireesh Nagabhushana 367456b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_PARAM_YZ 0 367556b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_PARAM_YZ 0xffff 367656b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 367756b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_PARAM_YZ(x) \ 367856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 367956b2bdd1SGireesh Nagabhushana 368056b2bdd1SGireesh Nagabhushana struct fw_params_cmd { 368156b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 368256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 368356b2bdd1SGireesh Nagabhushana struct fw_params_param { 368456b2bdd1SGireesh Nagabhushana __be32 mnem; 368556b2bdd1SGireesh Nagabhushana __be32 val; 368656b2bdd1SGireesh Nagabhushana } param[7]; 368756b2bdd1SGireesh Nagabhushana }; 368856b2bdd1SGireesh Nagabhushana 368956b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_CMD_PFN 8 369056b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_CMD_PFN 0x7 369156b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 369256b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_CMD_PFN(x) \ 369356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 369456b2bdd1SGireesh Nagabhushana 369556b2bdd1SGireesh Nagabhushana #define S_FW_PARAMS_CMD_VFN 0 369656b2bdd1SGireesh Nagabhushana #define M_FW_PARAMS_CMD_VFN 0xff 369756b2bdd1SGireesh Nagabhushana #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 369856b2bdd1SGireesh Nagabhushana #define G_FW_PARAMS_CMD_VFN(x) \ 369956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 370056b2bdd1SGireesh Nagabhushana 370156b2bdd1SGireesh Nagabhushana struct fw_pfvf_cmd { 370256b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 370356b2bdd1SGireesh Nagabhushana __be32 retval_len16; 370456b2bdd1SGireesh Nagabhushana __be32 niqflint_niq; 370556b2bdd1SGireesh Nagabhushana __be32 type_to_neq; 370656b2bdd1SGireesh Nagabhushana __be32 tc_to_nexactf; 370756b2bdd1SGireesh Nagabhushana __be32 r_caps_to_nethctrl; 370856b2bdd1SGireesh Nagabhushana __be16 nricq; 370956b2bdd1SGireesh Nagabhushana __be16 nriqp; 371056b2bdd1SGireesh Nagabhushana __be32 r4; 371156b2bdd1SGireesh Nagabhushana }; 371256b2bdd1SGireesh Nagabhushana 371356b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_PFN 8 371456b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_PFN 0x7 371556b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 371656b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_PFN(x) \ 371756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 371856b2bdd1SGireesh Nagabhushana 371956b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_VFN 0 372056b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_VFN 0xff 372156b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 372256b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_VFN(x) \ 372356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 372456b2bdd1SGireesh Nagabhushana 372556b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_NIQFLINT 20 372656b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_NIQFLINT 0xfff 372756b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 372856b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_NIQFLINT(x) \ 372956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 373056b2bdd1SGireesh Nagabhushana 373156b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_NIQ 0 373256b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_NIQ 0xfffff 373356b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 373456b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_NIQ(x) \ 373556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 373656b2bdd1SGireesh Nagabhushana 373756b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_TYPE 31 373856b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_TYPE 0x1 373956b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 374056b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_TYPE(x) \ 374156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 374256b2bdd1SGireesh Nagabhushana #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 374356b2bdd1SGireesh Nagabhushana 374456b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_CMASK 24 374556b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_CMASK 0xf 374656b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 374756b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_CMASK(x) \ 374856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 374956b2bdd1SGireesh Nagabhushana 375056b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_PMASK 20 375156b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_PMASK 0xf 375256b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 375356b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_PMASK(x) \ 375456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 375556b2bdd1SGireesh Nagabhushana 375656b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_NEQ 0 375756b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_NEQ 0xfffff 375856b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 375956b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_NEQ(x) \ 376056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 376156b2bdd1SGireesh Nagabhushana 376256b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_TC 24 376356b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_TC 0xff 376456b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 376556b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 376656b2bdd1SGireesh Nagabhushana 376756b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_NVI 16 376856b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_NVI 0xff 376956b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 377056b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_NVI(x) \ 377156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 377256b2bdd1SGireesh Nagabhushana 377356b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_NEXACTF 0 377456b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_NEXACTF 0xffff 377556b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 377656b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_NEXACTF(x) \ 377756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 377856b2bdd1SGireesh Nagabhushana 377956b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_R_CAPS 24 378056b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_R_CAPS 0xff 378156b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 378256b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_R_CAPS(x) \ 378356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 378456b2bdd1SGireesh Nagabhushana 378556b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_WX_CAPS 16 378656b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_WX_CAPS 0xff 378756b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 378856b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_WX_CAPS(x) \ 378956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 379056b2bdd1SGireesh Nagabhushana 379156b2bdd1SGireesh Nagabhushana #define S_FW_PFVF_CMD_NETHCTRL 0 379256b2bdd1SGireesh Nagabhushana #define M_FW_PFVF_CMD_NETHCTRL 0xffff 379356b2bdd1SGireesh Nagabhushana #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 379456b2bdd1SGireesh Nagabhushana #define G_FW_PFVF_CMD_NETHCTRL(x) \ 379556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 379656b2bdd1SGireesh Nagabhushana 379756b2bdd1SGireesh Nagabhushana /* 379856b2bdd1SGireesh Nagabhushana * ingress queue type; the first 1K ingress queues can have associated 0, 379956b2bdd1SGireesh Nagabhushana * 1 or 2 free lists and an interrupt, all other ingress queues lack these 380056b2bdd1SGireesh Nagabhushana * capabilities 380156b2bdd1SGireesh Nagabhushana */ 380256b2bdd1SGireesh Nagabhushana enum fw_iq_type { 380356b2bdd1SGireesh Nagabhushana FW_IQ_TYPE_FL_INT_CAP, 380456b2bdd1SGireesh Nagabhushana FW_IQ_TYPE_NO_FL_INT_CAP 380556b2bdd1SGireesh Nagabhushana }; 380656b2bdd1SGireesh Nagabhushana 380756b2bdd1SGireesh Nagabhushana struct fw_iq_cmd { 380856b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 380956b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 381056b2bdd1SGireesh Nagabhushana __be16 physiqid; 381156b2bdd1SGireesh Nagabhushana __be16 iqid; 381256b2bdd1SGireesh Nagabhushana __be16 fl0id; 381356b2bdd1SGireesh Nagabhushana __be16 fl1id; 381456b2bdd1SGireesh Nagabhushana __be32 type_to_iqandstindex; 381556b2bdd1SGireesh Nagabhushana __be16 iqdroprss_to_iqesize; 381656b2bdd1SGireesh Nagabhushana __be16 iqsize; 381756b2bdd1SGireesh Nagabhushana __be64 iqaddr; 381856b2bdd1SGireesh Nagabhushana __be32 iqns_to_fl0congen; 381956b2bdd1SGireesh Nagabhushana __be16 fl0dcaen_to_fl0cidxfthresh; 382056b2bdd1SGireesh Nagabhushana __be16 fl0size; 382156b2bdd1SGireesh Nagabhushana __be64 fl0addr; 382256b2bdd1SGireesh Nagabhushana __be32 fl1cngchmap_to_fl1congen; 382356b2bdd1SGireesh Nagabhushana __be16 fl1dcaen_to_fl1cidxfthresh; 382456b2bdd1SGireesh Nagabhushana __be16 fl1size; 382556b2bdd1SGireesh Nagabhushana __be64 fl1addr; 382656b2bdd1SGireesh Nagabhushana }; 382756b2bdd1SGireesh Nagabhushana 382856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_PFN 8 382956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_PFN 0x7 383056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 383156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 383256b2bdd1SGireesh Nagabhushana 383356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_VFN 0 383456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_VFN 0xff 383556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 383656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 383756b2bdd1SGireesh Nagabhushana 383856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_ALLOC 31 383956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_ALLOC 0x1 384056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 384156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_ALLOC(x) \ 384256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 384356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 384456b2bdd1SGireesh Nagabhushana 384556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FREE 30 384656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FREE 0x1 384756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 384856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 384956b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 385056b2bdd1SGireesh Nagabhushana 385156b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_MODIFY 29 385256b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_MODIFY 0x1 385356b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 385456b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_MODIFY(x) \ 385556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 385656b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 385756b2bdd1SGireesh Nagabhushana 385856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQSTART 28 385956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQSTART 0x1 386056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 386156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQSTART(x) \ 386256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 386356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 386456b2bdd1SGireesh Nagabhushana 386556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQSTOP 27 386656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQSTOP 0x1 386756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 386856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQSTOP(x) \ 386956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 387056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 387156b2bdd1SGireesh Nagabhushana 387256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_TYPE 29 387356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_TYPE 0x7 387456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 387556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 387656b2bdd1SGireesh Nagabhushana 387756b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQASYNCH 28 387856b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQASYNCH 0x1 387956b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 388056b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQASYNCH(x) \ 388156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 388256b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 388356b2bdd1SGireesh Nagabhushana 388456b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_VIID 16 388556b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_VIID 0xfff 388656b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 388756b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 388856b2bdd1SGireesh Nagabhushana 388956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQANDST 15 389056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQANDST 0x1 389156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 389256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQANDST(x) \ 389356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 389456b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 389556b2bdd1SGireesh Nagabhushana 389656b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQANUS 14 389756b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQANUS 0x1 389856b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 389956b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQANUS(x) \ 390056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 390156b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 390256b2bdd1SGireesh Nagabhushana 390356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQANUD 12 390456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQANUD 0x3 390556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 390656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQANUD(x) \ 390756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 390856b2bdd1SGireesh Nagabhushana 390956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQANDSTINDEX 0 391056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 391156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 391256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 391356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 391456b2bdd1SGireesh Nagabhushana 391556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQDROPRSS 15 391656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQDROPRSS 0x1 391756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 391856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQDROPRSS(x) \ 391956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 392056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 392156b2bdd1SGireesh Nagabhushana 392256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQGTSMODE 14 392356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQGTSMODE 0x1 392456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 392556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQGTSMODE(x) \ 392656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 392756b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 392856b2bdd1SGireesh Nagabhushana 392956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQPCIECH 12 393056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQPCIECH 0x3 393156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 393256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQPCIECH(x) \ 393356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 393456b2bdd1SGireesh Nagabhushana 393556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQDCAEN 11 393656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQDCAEN 0x1 393756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 393856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQDCAEN(x) \ 393956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 394056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 394156b2bdd1SGireesh Nagabhushana 394256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQDCACPU 6 394356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQDCACPU 0x1f 394456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 394556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQDCACPU(x) \ 394656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 394756b2bdd1SGireesh Nagabhushana 394856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 394956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 395056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 395156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 395256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 395356b2bdd1SGireesh Nagabhushana 395456b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQO 3 395556b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQO 0x1 395656b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 395756b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 395856b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 395956b2bdd1SGireesh Nagabhushana 396056b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQCPRIO 2 396156b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQCPRIO 0x1 396256b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 396356b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQCPRIO(x) \ 396456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 396556b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 396656b2bdd1SGireesh Nagabhushana 396756b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQESIZE 0 396856b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQESIZE 0x3 396956b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 397056b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQESIZE(x) \ 397156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 397256b2bdd1SGireesh Nagabhushana 397356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQNS 31 397456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQNS 0x1 397556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 397656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 397756b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 397856b2bdd1SGireesh Nagabhushana 397956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQRO 30 398056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQRO 0x1 398156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 398256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 398356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 398456b2bdd1SGireesh Nagabhushana 398556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 398656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 398756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 398856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 398956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 399056b2bdd1SGireesh Nagabhushana 399156b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQFLINTCONGEN 27 399256b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 399356b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 399456b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 399556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 399656b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 399756b2bdd1SGireesh Nagabhushana 399856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_IQFLINTISCSIC 26 399956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 400056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 400156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 400256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 400356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 400456b2bdd1SGireesh Nagabhushana 400556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CNGCHMAP 20 400656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 400756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 400856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 400956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 401056b2bdd1SGireesh Nagabhushana 401156b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CACHELOCK 15 401256b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 401356b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 401456b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 401556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 401656b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 401756b2bdd1SGireesh Nagabhushana 401856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0DBP 14 401956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0DBP 0x1 402056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 402156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0DBP(x) \ 402256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 402356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 402456b2bdd1SGireesh Nagabhushana 402556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0DATANS 13 402656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0DATANS 0x1 402756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 402856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0DATANS(x) \ 402956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 403056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 403156b2bdd1SGireesh Nagabhushana 403256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0DATARO 12 403356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0DATARO 0x1 403456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 403556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0DATARO(x) \ 403656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 403756b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 403856b2bdd1SGireesh Nagabhushana 403956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CONGCIF 11 404056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CONGCIF 0x1 404156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 404256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 404356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 404456b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 404556b2bdd1SGireesh Nagabhushana 404656b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0ONCHIP 10 404756b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0ONCHIP 0x1 404856b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 404956b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 405056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 405156b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 405256b2bdd1SGireesh Nagabhushana 405356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0STATUSPGNS 9 405456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 405556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 405656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 405756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 405856b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 405956b2bdd1SGireesh Nagabhushana 406056b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0STATUSPGRO 8 406156b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 406256b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 406356b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 406456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 406556b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 406656b2bdd1SGireesh Nagabhushana 406756b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0FETCHNS 7 406856b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0FETCHNS 0x1 406956b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 407056b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 407156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 407256b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 407356b2bdd1SGireesh Nagabhushana 407456b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0FETCHRO 6 407556b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0FETCHRO 0x1 407656b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 407756b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 407856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 407956b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 408056b2bdd1SGireesh Nagabhushana 408156b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 408256b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 408356b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 408456b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 408556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 408656b2bdd1SGireesh Nagabhushana 408756b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CPRIO 3 408856b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CPRIO 0x1 408956b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 409056b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CPRIO(x) \ 409156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 409256b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 409356b2bdd1SGireesh Nagabhushana 409456b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0PADEN 2 409556b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0PADEN 0x1 409656b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 409756b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0PADEN(x) \ 409856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 409956b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 410056b2bdd1SGireesh Nagabhushana 410156b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0PACKEN 1 410256b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0PACKEN 0x1 410356b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 410456b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0PACKEN(x) \ 410556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 410656b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 410756b2bdd1SGireesh Nagabhushana 410856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CONGEN 0 410956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CONGEN 0x1 411056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 411156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CONGEN(x) \ 411256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 411356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 411456b2bdd1SGireesh Nagabhushana 411556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0DCAEN 15 411656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0DCAEN 0x1 411756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 411856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0DCAEN(x) \ 411956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 412056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 412156b2bdd1SGireesh Nagabhushana 412256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0DCACPU 10 412356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0DCACPU 0x1f 412456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 412556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0DCACPU(x) \ 412656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 412756b2bdd1SGireesh Nagabhushana 412856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0FBMIN 7 412956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0FBMIN 0x7 413056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 413156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0FBMIN(x) \ 413256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 413356b2bdd1SGireesh Nagabhushana 413456b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0FBMAX 4 413556b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0FBMAX 0x7 413656b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 413756b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0FBMAX(x) \ 413856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 413956b2bdd1SGireesh Nagabhushana 414056b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 414156b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 414256b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 414356b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 414456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 414556b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 414656b2bdd1SGireesh Nagabhushana 414756b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 414856b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 414956b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 415056b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 415156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 415256b2bdd1SGireesh Nagabhushana 415356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CNGCHMAP 20 415456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 415556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 415656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 415756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 415856b2bdd1SGireesh Nagabhushana 415956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CACHELOCK 15 416056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 416156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 416256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 416356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 416456b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 416556b2bdd1SGireesh Nagabhushana 416656b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1DBP 14 416756b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1DBP 0x1 416856b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 416956b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1DBP(x) \ 417056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 417156b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 417256b2bdd1SGireesh Nagabhushana 417356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1DATANS 13 417456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1DATANS 0x1 417556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 417656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1DATANS(x) \ 417756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 417856b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 417956b2bdd1SGireesh Nagabhushana 418056b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1DATARO 12 418156b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1DATARO 0x1 418256b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 418356b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1DATARO(x) \ 418456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 418556b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 418656b2bdd1SGireesh Nagabhushana 418756b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CONGCIF 11 418856b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CONGCIF 0x1 418956b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 419056b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 419156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 419256b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 419356b2bdd1SGireesh Nagabhushana 419456b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1ONCHIP 10 419556b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1ONCHIP 0x1 419656b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 419756b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 419856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 419956b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 420056b2bdd1SGireesh Nagabhushana 420156b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1STATUSPGNS 9 420256b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 420356b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 420456b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 420556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 420656b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 420756b2bdd1SGireesh Nagabhushana 420856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1STATUSPGRO 8 420956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 421056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 421156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 421256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 421356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 421456b2bdd1SGireesh Nagabhushana 421556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1FETCHNS 7 421656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1FETCHNS 0x1 421756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 421856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 421956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 422056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 422156b2bdd1SGireesh Nagabhushana 422256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1FETCHRO 6 422356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1FETCHRO 0x1 422456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 422556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 422656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 422756b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 422856b2bdd1SGireesh Nagabhushana 422956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 423056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 423156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 423256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 423356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 423456b2bdd1SGireesh Nagabhushana 423556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CPRIO 3 423656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CPRIO 0x1 423756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 423856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CPRIO(x) \ 423956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 424056b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 424156b2bdd1SGireesh Nagabhushana 424256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1PADEN 2 424356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1PADEN 0x1 424456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 424556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1PADEN(x) \ 424656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 424756b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 424856b2bdd1SGireesh Nagabhushana 424956b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1PACKEN 1 425056b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1PACKEN 0x1 425156b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 425256b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1PACKEN(x) \ 425356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 425456b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 425556b2bdd1SGireesh Nagabhushana 425656b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CONGEN 0 425756b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CONGEN 0x1 425856b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 425956b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CONGEN(x) \ 426056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 426156b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 426256b2bdd1SGireesh Nagabhushana 426356b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1DCAEN 15 426456b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1DCAEN 0x1 426556b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 426656b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1DCAEN(x) \ 426756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 426856b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 426956b2bdd1SGireesh Nagabhushana 427056b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1DCACPU 10 427156b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1DCACPU 0x1f 427256b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 427356b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1DCACPU(x) \ 427456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 427556b2bdd1SGireesh Nagabhushana 427656b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1FBMIN 7 427756b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1FBMIN 0x7 427856b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 427956b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1FBMIN(x) \ 428056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 428156b2bdd1SGireesh Nagabhushana 428256b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1FBMAX 4 428356b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1FBMAX 0x7 428456b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 428556b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1FBMAX(x) \ 428656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 428756b2bdd1SGireesh Nagabhushana 428856b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 428956b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 429056b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 429156b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 429256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 429356b2bdd1SGireesh Nagabhushana #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 429456b2bdd1SGireesh Nagabhushana 429556b2bdd1SGireesh Nagabhushana #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 429656b2bdd1SGireesh Nagabhushana #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 429756b2bdd1SGireesh Nagabhushana #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 429856b2bdd1SGireesh Nagabhushana #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 429956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 430056b2bdd1SGireesh Nagabhushana 430156b2bdd1SGireesh Nagabhushana struct fw_eq_mngt_cmd { 430256b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 430356b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 430456b2bdd1SGireesh Nagabhushana __be32 cmpliqid_eqid; 430556b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 430656b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 430756b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 430856b2bdd1SGireesh Nagabhushana __be64 eqaddr; 430956b2bdd1SGireesh Nagabhushana }; 431056b2bdd1SGireesh Nagabhushana 431156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_PFN 8 431256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_PFN 0x7 431356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 431456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_PFN(x) \ 431556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 431656b2bdd1SGireesh Nagabhushana 431756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_VFN 0 431856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_VFN 0xff 431956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 432056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_VFN(x) \ 432156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 432256b2bdd1SGireesh Nagabhushana 432356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_ALLOC 31 432456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 432556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 432656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 432756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 432856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 432956b2bdd1SGireesh Nagabhushana 433056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_FREE 30 433156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_FREE 0x1 433256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 433356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_FREE(x) \ 433456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 433556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 433656b2bdd1SGireesh Nagabhushana 433756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_MODIFY 29 433856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 433956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 434056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 434156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 434256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 434356b2bdd1SGireesh Nagabhushana 434456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_EQSTART 28 434556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 434656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 434756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 434856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 434956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 435056b2bdd1SGireesh Nagabhushana 435156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_EQSTOP 27 435256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 435356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 435456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 435556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 435656b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 435756b2bdd1SGireesh Nagabhushana 435856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 435956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 436056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 436156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 436256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 436356b2bdd1SGireesh Nagabhushana 436456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_EQID 0 436556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 436656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 436756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_EQID(x) \ 436856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 436956b2bdd1SGireesh Nagabhushana 437056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 437156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 437256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 437356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 437456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 437556b2bdd1SGireesh Nagabhushana 437656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 437756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 437856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 437956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 438056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 438156b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 438256b2bdd1SGireesh Nagabhushana 438356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 438456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 438556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 438656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 438756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 438856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 438956b2bdd1SGireesh Nagabhushana 439056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 439156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 439256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 439356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 439456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 439556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 439656b2bdd1SGireesh Nagabhushana 439756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_FETCHNS 23 439856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 439956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 440056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 440156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 440256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 440356b2bdd1SGireesh Nagabhushana 440456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_FETCHRO 22 440556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 440656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 440756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 440856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 440956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 441056b2bdd1SGireesh Nagabhushana 441156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 441256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 441356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 441456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 441556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 441656b2bdd1SGireesh Nagabhushana 441756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_CPRIO 19 441856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 441956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 442056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 442156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 442256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 442356b2bdd1SGireesh Nagabhushana 442456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_ONCHIP 18 442556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 442656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 442756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 442856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 442956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 443056b2bdd1SGireesh Nagabhushana 443156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_PCIECHN 16 443256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 443356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 443456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 443556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 443656b2bdd1SGireesh Nagabhushana 443756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_IQID 0 443856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_IQID 0xffff 443956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 444056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_IQID(x) \ 444156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 444256b2bdd1SGireesh Nagabhushana 444356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_DCAEN 31 444456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 444556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 444656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 444756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 444856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 444956b2bdd1SGireesh Nagabhushana 445056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_DCACPU 26 445156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 445256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 445356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 445456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 445556b2bdd1SGireesh Nagabhushana 445656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_FBMIN 23 445756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 445856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 445956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 446056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 446156b2bdd1SGireesh Nagabhushana 446256b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_FBMAX 20 446356b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 446456b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 446556b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 446656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 446756b2bdd1SGireesh Nagabhushana 446856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 446956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 447056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 447156b2bdd1SGireesh Nagabhushana ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 447256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 447356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 447456b2bdd1SGireesh Nagabhushana #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 447556b2bdd1SGireesh Nagabhushana 447656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 447756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 447856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 447956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 448056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 448156b2bdd1SGireesh Nagabhushana 448256b2bdd1SGireesh Nagabhushana #define S_FW_EQ_MNGT_CMD_EQSIZE 0 448356b2bdd1SGireesh Nagabhushana #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 448456b2bdd1SGireesh Nagabhushana #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 448556b2bdd1SGireesh Nagabhushana #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 448656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 448756b2bdd1SGireesh Nagabhushana 448856b2bdd1SGireesh Nagabhushana struct fw_eq_eth_cmd { 448956b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 449056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 449156b2bdd1SGireesh Nagabhushana __be32 eqid_pkd; 449256b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 449356b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 449456b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 449556b2bdd1SGireesh Nagabhushana __be64 eqaddr; 449656b2bdd1SGireesh Nagabhushana __be32 viid_pkd; 449756b2bdd1SGireesh Nagabhushana __be32 r8_lo; 449856b2bdd1SGireesh Nagabhushana __be64 r9; 449956b2bdd1SGireesh Nagabhushana }; 450056b2bdd1SGireesh Nagabhushana 450156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_PFN 8 450256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_PFN 0x7 450356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 450456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_PFN(x) \ 450556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 450656b2bdd1SGireesh Nagabhushana 450756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_VFN 0 450856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_VFN 0xff 450956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 451056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_VFN(x) \ 451156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 451256b2bdd1SGireesh Nagabhushana 451356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_ALLOC 31 451456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_ALLOC 0x1 451556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 451656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 451756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 451856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 451956b2bdd1SGireesh Nagabhushana 452056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_FREE 30 452156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_FREE 0x1 452256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 452356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_FREE(x) \ 452456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 452556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 452656b2bdd1SGireesh Nagabhushana 452756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_MODIFY 29 452856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_MODIFY 0x1 452956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 453056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 453156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 453256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 453356b2bdd1SGireesh Nagabhushana 453456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_EQSTART 28 453556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_EQSTART 0x1 453656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 453756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 453856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 453956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 454056b2bdd1SGireesh Nagabhushana 454156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_EQSTOP 27 454256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 454356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 454456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 454556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 454656b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 454756b2bdd1SGireesh Nagabhushana 454856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_EQID 0 454956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_EQID 0xfffff 455056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 455156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_EQID(x) \ 455256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 455356b2bdd1SGireesh Nagabhushana 455456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_PHYSEQID 0 455556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 455656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 455756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 455856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 455956b2bdd1SGireesh Nagabhushana 456056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_FETCHSZM 26 456156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 456256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 456356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 456456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 456556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 456656b2bdd1SGireesh Nagabhushana 456756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 456856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 456956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 457056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 457156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 457256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 457356b2bdd1SGireesh Nagabhushana 457456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 457556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 457656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 457756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 457856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 457956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 458056b2bdd1SGireesh Nagabhushana 458156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_FETCHNS 23 458256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 458356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 458456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 458556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 458656b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 458756b2bdd1SGireesh Nagabhushana 458856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_FETCHRO 22 458956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 459056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 459156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 459256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 459356b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 459456b2bdd1SGireesh Nagabhushana 459556b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 459656b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 459756b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 459856b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 459956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 460056b2bdd1SGireesh Nagabhushana 460156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_CPRIO 19 460256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_CPRIO 0x1 460356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 460456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 460556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 460656b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 460756b2bdd1SGireesh Nagabhushana 460856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_ONCHIP 18 460956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 461056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 461156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 461256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 461356b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 461456b2bdd1SGireesh Nagabhushana 461556b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_PCIECHN 16 461656b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 461756b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 461856b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 461956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 462056b2bdd1SGireesh Nagabhushana 462156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_IQID 0 462256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_IQID 0xffff 462356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 462456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_IQID(x) \ 462556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 462656b2bdd1SGireesh Nagabhushana 462756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_DCAEN 31 462856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_DCAEN 0x1 462956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 463056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 463156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 463256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 463356b2bdd1SGireesh Nagabhushana 463456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_DCACPU 26 463556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 463656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 463756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 463856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 463956b2bdd1SGireesh Nagabhushana 464056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_FBMIN 23 464156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_FBMIN 0x7 464256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 464356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 464456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 464556b2bdd1SGireesh Nagabhushana 464656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_FBMAX 20 464756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_FBMAX 0x7 464856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 464956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 465056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 465156b2bdd1SGireesh Nagabhushana 465256b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 465356b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 465456b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 465556b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 465656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 465756b2bdd1SGireesh Nagabhushana #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 465856b2bdd1SGireesh Nagabhushana 465956b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 466056b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 466156b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 466256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 466356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 466456b2bdd1SGireesh Nagabhushana 466556b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_EQSIZE 0 466656b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 466756b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 466856b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 466956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 467056b2bdd1SGireesh Nagabhushana 467156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_ETH_CMD_VIID 16 467256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_ETH_CMD_VIID 0xfff 467356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 467456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_ETH_CMD_VIID(x) \ 467556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 467656b2bdd1SGireesh Nagabhushana 467756b2bdd1SGireesh Nagabhushana struct fw_eq_ctrl_cmd { 467856b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 467956b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 468056b2bdd1SGireesh Nagabhushana __be32 cmpliqid_eqid; 468156b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 468256b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 468356b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 468456b2bdd1SGireesh Nagabhushana __be64 eqaddr; 468556b2bdd1SGireesh Nagabhushana }; 468656b2bdd1SGireesh Nagabhushana 468756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_PFN 8 468856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_PFN 0x7 468956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 469056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_PFN(x) \ 469156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 469256b2bdd1SGireesh Nagabhushana 469356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_VFN 0 469456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_VFN 0xff 469556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 469656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_VFN(x) \ 469756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 469856b2bdd1SGireesh Nagabhushana 469956b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_ALLOC 31 470056b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 470156b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 470256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 470356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 470456b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 470556b2bdd1SGireesh Nagabhushana 470656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_FREE 30 470756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_FREE 0x1 470856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 470956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_FREE(x) \ 471056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 471156b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 471256b2bdd1SGireesh Nagabhushana 471356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_MODIFY 29 471456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 471556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 471656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 471756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 471856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 471956b2bdd1SGireesh Nagabhushana 472056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_EQSTART 28 472156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 472256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 472356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 472456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 472556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 472656b2bdd1SGireesh Nagabhushana 472756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_EQSTOP 27 472856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 472956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 473056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 473156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 473256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 473356b2bdd1SGireesh Nagabhushana 473456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 473556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 473656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 473756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 473856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 473956b2bdd1SGireesh Nagabhushana 474056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_EQID 0 474156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 474256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 474356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_EQID(x) \ 474456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 474556b2bdd1SGireesh Nagabhushana 474656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 474756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 474856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 474956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 475056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 475156b2bdd1SGireesh Nagabhushana 475256b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 475356b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 475456b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 475556b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 475656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 475756b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 475856b2bdd1SGireesh Nagabhushana 475956b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 476056b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 476156b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 476256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 476356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 476456b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 476556b2bdd1SGireesh Nagabhushana 476656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 476756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 476856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 476956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 477056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 477156b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 477256b2bdd1SGireesh Nagabhushana 477356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_FETCHNS 23 477456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 477556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 477656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 477756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 477856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 477956b2bdd1SGireesh Nagabhushana 478056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_FETCHRO 22 478156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 478256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 478356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 478456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 478556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 478656b2bdd1SGireesh Nagabhushana 478756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 478856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 478956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 479056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 479156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 479256b2bdd1SGireesh Nagabhushana 479356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_CPRIO 19 479456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 479556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 479656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 479756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 479856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 479956b2bdd1SGireesh Nagabhushana 480056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_ONCHIP 18 480156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 480256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 480356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 480456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 480556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 480656b2bdd1SGireesh Nagabhushana 480756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_PCIECHN 16 480856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 480956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 481056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 481156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 481256b2bdd1SGireesh Nagabhushana 481356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_IQID 0 481456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_IQID 0xffff 481556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 481656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_IQID(x) \ 481756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 481856b2bdd1SGireesh Nagabhushana 481956b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_DCAEN 31 482056b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 482156b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 482256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 482356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 482456b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 482556b2bdd1SGireesh Nagabhushana 482656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_DCACPU 26 482756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 482856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 482956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 483056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 483156b2bdd1SGireesh Nagabhushana 483256b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_FBMIN 23 483356b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 483456b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 483556b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 483656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 483756b2bdd1SGireesh Nagabhushana 483856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_FBMAX 20 483956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 484056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 484156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 484256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 484356b2bdd1SGireesh Nagabhushana 484456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 484556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 484656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 484756b2bdd1SGireesh Nagabhushana ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 484856b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 484956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 485056b2bdd1SGireesh Nagabhushana #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 485156b2bdd1SGireesh Nagabhushana 485256b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 485356b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 485456b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 485556b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 485656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 485756b2bdd1SGireesh Nagabhushana 485856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_CTRL_CMD_EQSIZE 0 485956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 486056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 486156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 486256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 486356b2bdd1SGireesh Nagabhushana 486456b2bdd1SGireesh Nagabhushana struct fw_eq_ofld_cmd { 486556b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 486656b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 486756b2bdd1SGireesh Nagabhushana __be32 eqid_pkd; 486856b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 486956b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 487056b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 487156b2bdd1SGireesh Nagabhushana __be64 eqaddr; 487256b2bdd1SGireesh Nagabhushana }; 487356b2bdd1SGireesh Nagabhushana 487456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_PFN 8 487556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_PFN 0x7 487656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 487756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_PFN(x) \ 487856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 487956b2bdd1SGireesh Nagabhushana 488056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_VFN 0 488156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_VFN 0xff 488256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 488356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_VFN(x) \ 488456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 488556b2bdd1SGireesh Nagabhushana 488656b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_ALLOC 31 488756b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 488856b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 488956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 489056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 489156b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 489256b2bdd1SGireesh Nagabhushana 489356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_FREE 30 489456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_FREE 0x1 489556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 489656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_FREE(x) \ 489756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 489856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 489956b2bdd1SGireesh Nagabhushana 490056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_MODIFY 29 490156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 490256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 490356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 490456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 490556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 490656b2bdd1SGireesh Nagabhushana 490756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_EQSTART 28 490856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 490956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 491056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 491156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 491256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 491356b2bdd1SGireesh Nagabhushana 491456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_EQSTOP 27 491556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 491656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 491756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 491856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 491956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 492056b2bdd1SGireesh Nagabhushana 492156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_EQID 0 492256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 492356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 492456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_EQID(x) \ 492556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 492656b2bdd1SGireesh Nagabhushana 492756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 492856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 492956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 493056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 493156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 493256b2bdd1SGireesh Nagabhushana 493356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 493456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 493556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 493656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 493756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 493856b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 493956b2bdd1SGireesh Nagabhushana 494056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 494156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 494256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 494356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 494456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 494556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 494656b2bdd1SGireesh Nagabhushana 494756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 494856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 494956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 495056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 495156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 495256b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 495356b2bdd1SGireesh Nagabhushana 495456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_FETCHNS 23 495556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 495656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 495756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 495856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 495956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 496056b2bdd1SGireesh Nagabhushana 496156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_FETCHRO 22 496256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 496356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 496456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 496556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 496656b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 496756b2bdd1SGireesh Nagabhushana 496856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 496956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 497056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 497156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 497256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 497356b2bdd1SGireesh Nagabhushana 497456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_CPRIO 19 497556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 497656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 497756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 497856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 497956b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 498056b2bdd1SGireesh Nagabhushana 498156b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_ONCHIP 18 498256b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 498356b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 498456b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 498556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 498656b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 498756b2bdd1SGireesh Nagabhushana 498856b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_PCIECHN 16 498956b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 499056b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 499156b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 499256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 499356b2bdd1SGireesh Nagabhushana 499456b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_IQID 0 499556b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_IQID 0xffff 499656b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 499756b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_IQID(x) \ 499856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 499956b2bdd1SGireesh Nagabhushana 500056b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_DCAEN 31 500156b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 500256b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 500356b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 500456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 500556b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 500656b2bdd1SGireesh Nagabhushana 500756b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_DCACPU 26 500856b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 500956b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 501056b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 501156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 501256b2bdd1SGireesh Nagabhushana 501356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_FBMIN 23 501456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 501556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 501656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 501756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 501856b2bdd1SGireesh Nagabhushana 501956b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_FBMAX 20 502056b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 502156b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 502256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 502356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 502456b2bdd1SGireesh Nagabhushana 502556b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 502656b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 502756b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 502856b2bdd1SGireesh Nagabhushana ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 502956b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 503056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 503156b2bdd1SGireesh Nagabhushana #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 503256b2bdd1SGireesh Nagabhushana 503356b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 503456b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 503556b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 503656b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 503756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 503856b2bdd1SGireesh Nagabhushana 503956b2bdd1SGireesh Nagabhushana #define S_FW_EQ_OFLD_CMD_EQSIZE 0 504056b2bdd1SGireesh Nagabhushana #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 504156b2bdd1SGireesh Nagabhushana #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 504256b2bdd1SGireesh Nagabhushana #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 504356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 504456b2bdd1SGireesh Nagabhushana 504556b2bdd1SGireesh Nagabhushana /* 504656b2bdd1SGireesh Nagabhushana * Macros for VIID parsing: 504756b2bdd1SGireesh Nagabhushana * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 504856b2bdd1SGireesh Nagabhushana */ 504956b2bdd1SGireesh Nagabhushana #define S_FW_VIID_PFN 8 505056b2bdd1SGireesh Nagabhushana #define M_FW_VIID_PFN 0x7 505156b2bdd1SGireesh Nagabhushana #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 505256b2bdd1SGireesh Nagabhushana #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 505356b2bdd1SGireesh Nagabhushana 505456b2bdd1SGireesh Nagabhushana #define S_FW_VIID_VIVLD 7 505556b2bdd1SGireesh Nagabhushana #define M_FW_VIID_VIVLD 0x1 505656b2bdd1SGireesh Nagabhushana #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 505756b2bdd1SGireesh Nagabhushana #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 505856b2bdd1SGireesh Nagabhushana 505956b2bdd1SGireesh Nagabhushana #define S_FW_VIID_VIN 0 506056b2bdd1SGireesh Nagabhushana #define M_FW_VIID_VIN 0x7F 506156b2bdd1SGireesh Nagabhushana #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 506256b2bdd1SGireesh Nagabhushana #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 506356b2bdd1SGireesh Nagabhushana 506456b2bdd1SGireesh Nagabhushana enum fw_vi_func { 506556b2bdd1SGireesh Nagabhushana FW_VI_FUNC_ETH, 506656b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OFLD, 506756b2bdd1SGireesh Nagabhushana FW_VI_FUNC_IWARP, 506856b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OPENISCSI, 506956b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OPENFCOE, 507056b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FOISCSI, 507156b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FOFCOE, 507256b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FW, 507356b2bdd1SGireesh Nagabhushana }; 507456b2bdd1SGireesh Nagabhushana 507556b2bdd1SGireesh Nagabhushana struct fw_vi_cmd { 507656b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 507756b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 507856b2bdd1SGireesh Nagabhushana __be16 type_to_viid; 507956b2bdd1SGireesh Nagabhushana __u8 mac[6]; 508056b2bdd1SGireesh Nagabhushana __u8 portid_pkd; 508156b2bdd1SGireesh Nagabhushana __u8 nmac; 508256b2bdd1SGireesh Nagabhushana __u8 nmac0[6]; 5083*de483253SVishal Kulkarni __be16 norss_rsssize; 508456b2bdd1SGireesh Nagabhushana __u8 nmac1[6]; 508556b2bdd1SGireesh Nagabhushana __be16 idsiiq_pkd; 508656b2bdd1SGireesh Nagabhushana __u8 nmac2[6]; 508756b2bdd1SGireesh Nagabhushana __be16 idseiq_pkd; 508856b2bdd1SGireesh Nagabhushana __u8 nmac3[6]; 508956b2bdd1SGireesh Nagabhushana __be64 r9; 509056b2bdd1SGireesh Nagabhushana __be64 r10; 509156b2bdd1SGireesh Nagabhushana }; 509256b2bdd1SGireesh Nagabhushana 509356b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_PFN 8 509456b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_PFN 0x7 509556b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 509656b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 509756b2bdd1SGireesh Nagabhushana 509856b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_VFN 0 509956b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_VFN 0xff 510056b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 510156b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 510256b2bdd1SGireesh Nagabhushana 510356b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_ALLOC 31 510456b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_ALLOC 0x1 510556b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 510656b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_ALLOC(x) \ 510756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 510856b2bdd1SGireesh Nagabhushana #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 510956b2bdd1SGireesh Nagabhushana 511056b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_FREE 30 511156b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_FREE 0x1 511256b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 511356b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 511456b2bdd1SGireesh Nagabhushana #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 511556b2bdd1SGireesh Nagabhushana 511656b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_TYPE 15 511756b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_TYPE 0x1 511856b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 511956b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 512056b2bdd1SGireesh Nagabhushana #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 512156b2bdd1SGireesh Nagabhushana 512256b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_FUNC 12 512356b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_FUNC 0x7 512456b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 512556b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 512656b2bdd1SGireesh Nagabhushana 512756b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_VIID 0 512856b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_VIID 0xfff 512956b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 513056b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 513156b2bdd1SGireesh Nagabhushana 513256b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_PORTID 4 513356b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_PORTID 0xf 513456b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 513556b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_PORTID(x) \ 513656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 513756b2bdd1SGireesh Nagabhushana 5138*de483253SVishal Kulkarni #define S_FW_VI_CMD_NORSS 11 5139*de483253SVishal Kulkarni #define M_FW_VI_CMD_NORSS 0x1 5140*de483253SVishal Kulkarni #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5141*de483253SVishal Kulkarni #define G_FW_VI_CMD_NORSS(x) \ 5142*de483253SVishal Kulkarni (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5143*de483253SVishal Kulkarni #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5144*de483253SVishal Kulkarni 514556b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_RSSSIZE 0 514656b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_RSSSIZE 0x7ff 514756b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 514856b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_RSSSIZE(x) \ 514956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 515056b2bdd1SGireesh Nagabhushana 515156b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_IDSIIQ 0 515256b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_IDSIIQ 0x3ff 515356b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 515456b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_IDSIIQ(x) \ 515556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 515656b2bdd1SGireesh Nagabhushana 515756b2bdd1SGireesh Nagabhushana #define S_FW_VI_CMD_IDSEIQ 0 515856b2bdd1SGireesh Nagabhushana #define M_FW_VI_CMD_IDSEIQ 0x3ff 515956b2bdd1SGireesh Nagabhushana #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 516056b2bdd1SGireesh Nagabhushana #define G_FW_VI_CMD_IDSEIQ(x) \ 516156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 516256b2bdd1SGireesh Nagabhushana 516356b2bdd1SGireesh Nagabhushana /* Special VI_MAC command index ids */ 516456b2bdd1SGireesh Nagabhushana #define FW_VI_MAC_ADD_MAC 0x3FF 516556b2bdd1SGireesh Nagabhushana #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 516656b2bdd1SGireesh Nagabhushana #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 516756b2bdd1SGireesh Nagabhushana 516856b2bdd1SGireesh Nagabhushana enum fw_vi_mac_smac { 516956b2bdd1SGireesh Nagabhushana FW_VI_MAC_MPS_TCAM_ENTRY, 517056b2bdd1SGireesh Nagabhushana FW_VI_MAC_MPS_TCAM_ONLY, 517156b2bdd1SGireesh Nagabhushana FW_VI_MAC_SMT_ONLY, 517256b2bdd1SGireesh Nagabhushana FW_VI_MAC_SMT_AND_MPSTCAM 517356b2bdd1SGireesh Nagabhushana }; 517456b2bdd1SGireesh Nagabhushana 517556b2bdd1SGireesh Nagabhushana enum fw_vi_mac_result { 517656b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_SUCCESS, 517756b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 517856b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_SMAC_FAIL, 517956b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_F_ACL_CHECK 518056b2bdd1SGireesh Nagabhushana }; 518156b2bdd1SGireesh Nagabhushana 518256b2bdd1SGireesh Nagabhushana struct fw_vi_mac_cmd { 518356b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 518456b2bdd1SGireesh Nagabhushana __be32 freemacs_to_len16; 518556b2bdd1SGireesh Nagabhushana union fw_vi_mac { 518656b2bdd1SGireesh Nagabhushana struct fw_vi_mac_exact { 518756b2bdd1SGireesh Nagabhushana __be16 valid_to_idx; 518856b2bdd1SGireesh Nagabhushana __u8 macaddr[6]; 518956b2bdd1SGireesh Nagabhushana } exact[7]; 519056b2bdd1SGireesh Nagabhushana struct fw_vi_mac_hash { 519156b2bdd1SGireesh Nagabhushana __be64 hashvec; 519256b2bdd1SGireesh Nagabhushana } hash; 519356b2bdd1SGireesh Nagabhushana } u; 519456b2bdd1SGireesh Nagabhushana }; 519556b2bdd1SGireesh Nagabhushana 519656b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_VIID 0 519756b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_VIID 0xfff 519856b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 519956b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_VIID(x) \ 520056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 520156b2bdd1SGireesh Nagabhushana 520256b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_FREEMACS 31 520356b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_FREEMACS 0x1 520456b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 520556b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 520656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 520756b2bdd1SGireesh Nagabhushana #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 520856b2bdd1SGireesh Nagabhushana 520956b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_HASHVECEN 23 521056b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 521156b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 521256b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 521356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 521456b2bdd1SGireesh Nagabhushana #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 521556b2bdd1SGireesh Nagabhushana 521656b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_HASHUNIEN 22 521756b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 521856b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 521956b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 522056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 522156b2bdd1SGireesh Nagabhushana #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 522256b2bdd1SGireesh Nagabhushana 522356b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_VALID 15 522456b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_VALID 0x1 522556b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 522656b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_VALID(x) \ 522756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 522856b2bdd1SGireesh Nagabhushana #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 522956b2bdd1SGireesh Nagabhushana 523056b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_PRIO 12 523156b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_PRIO 0x7 523256b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 523356b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_PRIO(x) \ 523456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 523556b2bdd1SGireesh Nagabhushana 523656b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 523756b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 523856b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 523956b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 524056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 524156b2bdd1SGireesh Nagabhushana 524256b2bdd1SGireesh Nagabhushana #define S_FW_VI_MAC_CMD_IDX 0 524356b2bdd1SGireesh Nagabhushana #define M_FW_VI_MAC_CMD_IDX 0x3ff 524456b2bdd1SGireesh Nagabhushana #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 524556b2bdd1SGireesh Nagabhushana #define G_FW_VI_MAC_CMD_IDX(x) \ 524656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 524756b2bdd1SGireesh Nagabhushana 524856b2bdd1SGireesh Nagabhushana /* T4 max MTU supported */ 524956b2bdd1SGireesh Nagabhushana #define T4_MAX_MTU_SUPPORTED 9600 525056b2bdd1SGireesh Nagabhushana #define FW_RXMODE_MTU_NO_CHG 65535 525156b2bdd1SGireesh Nagabhushana 525256b2bdd1SGireesh Nagabhushana struct fw_vi_rxmode_cmd { 525356b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 525456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 525556b2bdd1SGireesh Nagabhushana __be32 mtu_to_vlanexen; 525656b2bdd1SGireesh Nagabhushana __be32 r4_lo; 525756b2bdd1SGireesh Nagabhushana }; 525856b2bdd1SGireesh Nagabhushana 525956b2bdd1SGireesh Nagabhushana #define S_FW_VI_RXMODE_CMD_VIID 0 526056b2bdd1SGireesh Nagabhushana #define M_FW_VI_RXMODE_CMD_VIID 0xfff 526156b2bdd1SGireesh Nagabhushana #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 526256b2bdd1SGireesh Nagabhushana #define G_FW_VI_RXMODE_CMD_VIID(x) \ 526356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 526456b2bdd1SGireesh Nagabhushana 526556b2bdd1SGireesh Nagabhushana #define S_FW_VI_RXMODE_CMD_MTU 16 526656b2bdd1SGireesh Nagabhushana #define M_FW_VI_RXMODE_CMD_MTU 0xffff 526756b2bdd1SGireesh Nagabhushana #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 526856b2bdd1SGireesh Nagabhushana #define G_FW_VI_RXMODE_CMD_MTU(x) \ 526956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 527056b2bdd1SGireesh Nagabhushana 527156b2bdd1SGireesh Nagabhushana #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 527256b2bdd1SGireesh Nagabhushana #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 527356b2bdd1SGireesh Nagabhushana #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 527456b2bdd1SGireesh Nagabhushana #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 527556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 527656b2bdd1SGireesh Nagabhushana 527756b2bdd1SGireesh Nagabhushana #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 527856b2bdd1SGireesh Nagabhushana #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 527956b2bdd1SGireesh Nagabhushana #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 528056b2bdd1SGireesh Nagabhushana ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 528156b2bdd1SGireesh Nagabhushana #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 528256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 528356b2bdd1SGireesh Nagabhushana 528456b2bdd1SGireesh Nagabhushana #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 528556b2bdd1SGireesh Nagabhushana #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 528656b2bdd1SGireesh Nagabhushana #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 528756b2bdd1SGireesh Nagabhushana ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 528856b2bdd1SGireesh Nagabhushana #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 528956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 529056b2bdd1SGireesh Nagabhushana M_FW_VI_RXMODE_CMD_BROADCASTEN) 529156b2bdd1SGireesh Nagabhushana 529256b2bdd1SGireesh Nagabhushana #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 529356b2bdd1SGireesh Nagabhushana #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 529456b2bdd1SGireesh Nagabhushana #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 529556b2bdd1SGireesh Nagabhushana #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 529656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 529756b2bdd1SGireesh Nagabhushana 529856b2bdd1SGireesh Nagabhushana struct fw_vi_enable_cmd { 529956b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 530056b2bdd1SGireesh Nagabhushana __be32 ien_to_len16; 530156b2bdd1SGireesh Nagabhushana __be16 blinkdur; 530256b2bdd1SGireesh Nagabhushana __be16 r3; 530356b2bdd1SGireesh Nagabhushana __be32 r4; 530456b2bdd1SGireesh Nagabhushana }; 530556b2bdd1SGireesh Nagabhushana 530656b2bdd1SGireesh Nagabhushana #define S_FW_VI_ENABLE_CMD_VIID 0 530756b2bdd1SGireesh Nagabhushana #define M_FW_VI_ENABLE_CMD_VIID 0xfff 530856b2bdd1SGireesh Nagabhushana #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 530956b2bdd1SGireesh Nagabhushana #define G_FW_VI_ENABLE_CMD_VIID(x) \ 531056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 531156b2bdd1SGireesh Nagabhushana 531256b2bdd1SGireesh Nagabhushana #define S_FW_VI_ENABLE_CMD_IEN 31 531356b2bdd1SGireesh Nagabhushana #define M_FW_VI_ENABLE_CMD_IEN 0x1 531456b2bdd1SGireesh Nagabhushana #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 531556b2bdd1SGireesh Nagabhushana #define G_FW_VI_ENABLE_CMD_IEN(x) \ 531656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 531756b2bdd1SGireesh Nagabhushana #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 531856b2bdd1SGireesh Nagabhushana 531956b2bdd1SGireesh Nagabhushana #define S_FW_VI_ENABLE_CMD_EEN 30 532056b2bdd1SGireesh Nagabhushana #define M_FW_VI_ENABLE_CMD_EEN 0x1 532156b2bdd1SGireesh Nagabhushana #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 532256b2bdd1SGireesh Nagabhushana #define G_FW_VI_ENABLE_CMD_EEN(x) \ 532356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 532456b2bdd1SGireesh Nagabhushana #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 532556b2bdd1SGireesh Nagabhushana 532656b2bdd1SGireesh Nagabhushana #define S_FW_VI_ENABLE_CMD_LED 29 532756b2bdd1SGireesh Nagabhushana #define M_FW_VI_ENABLE_CMD_LED 0x1 532856b2bdd1SGireesh Nagabhushana #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 532956b2bdd1SGireesh Nagabhushana #define G_FW_VI_ENABLE_CMD_LED(x) \ 533056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 533156b2bdd1SGireesh Nagabhushana #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 533256b2bdd1SGireesh Nagabhushana 5333*de483253SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5334*de483253SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5335*de483253SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5336*de483253SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5337*de483253SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5338*de483253SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5339*de483253SVishal Kulkarni 534056b2bdd1SGireesh Nagabhushana /* VI VF stats offset definitions */ 534156b2bdd1SGireesh Nagabhushana #define VI_VF_NUM_STATS 16 534256b2bdd1SGireesh Nagabhushana enum fw_vi_stats_vf_index { 534356b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 534456b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 534556b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 534656b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 534756b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 534856b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 534956b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 535056b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 535156b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 535256b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 535356b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 535456b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 535556b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 535656b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 535756b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 535856b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_ERR_FRAMES_IX 535956b2bdd1SGireesh Nagabhushana }; 536056b2bdd1SGireesh Nagabhushana 536156b2bdd1SGireesh Nagabhushana /* VI PF stats offset definitions */ 536256b2bdd1SGireesh Nagabhushana #define VI_PF_NUM_STATS 17 536356b2bdd1SGireesh Nagabhushana enum fw_vi_stats_pf_index { 536456b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 536556b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 536656b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 536756b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 536856b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 536956b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 537056b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 537156b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 537256b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BYTES_IX, 537356b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_FRAMES_IX, 537456b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 537556b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 537656b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 537756b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 537856b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 537956b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 538056b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_ERR_FRAMES_IX 538156b2bdd1SGireesh Nagabhushana }; 538256b2bdd1SGireesh Nagabhushana 538356b2bdd1SGireesh Nagabhushana struct fw_vi_stats_cmd { 538456b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 538556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 538656b2bdd1SGireesh Nagabhushana union fw_vi_stats { 538756b2bdd1SGireesh Nagabhushana struct fw_vi_stats_ctl { 538856b2bdd1SGireesh Nagabhushana __be16 nstats_ix; 538956b2bdd1SGireesh Nagabhushana __be16 r6; 539056b2bdd1SGireesh Nagabhushana __be32 r7; 539156b2bdd1SGireesh Nagabhushana __be64 stat0; 539256b2bdd1SGireesh Nagabhushana __be64 stat1; 539356b2bdd1SGireesh Nagabhushana __be64 stat2; 539456b2bdd1SGireesh Nagabhushana __be64 stat3; 539556b2bdd1SGireesh Nagabhushana __be64 stat4; 539656b2bdd1SGireesh Nagabhushana __be64 stat5; 539756b2bdd1SGireesh Nagabhushana } ctl; 539856b2bdd1SGireesh Nagabhushana struct fw_vi_stats_pf { 539956b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 540056b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 540156b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 540256b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 540356b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 540456b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 540556b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 540656b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 540756b2bdd1SGireesh Nagabhushana __be64 rx_pf_bytes; 540856b2bdd1SGireesh Nagabhushana __be64 rx_pf_frames; 540956b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 541056b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 541156b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 541256b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 541356b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 541456b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 541556b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 541656b2bdd1SGireesh Nagabhushana } pf; 541756b2bdd1SGireesh Nagabhushana struct fw_vi_stats_vf { 541856b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 541956b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 542056b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 542156b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 542256b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 542356b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 542456b2bdd1SGireesh Nagabhushana __be64 tx_drop_frames; 542556b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 542656b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 542756b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 542856b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 542956b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 543056b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 543156b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 543256b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 543356b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 543456b2bdd1SGireesh Nagabhushana } vf; 543556b2bdd1SGireesh Nagabhushana } u; 543656b2bdd1SGireesh Nagabhushana }; 543756b2bdd1SGireesh Nagabhushana 543856b2bdd1SGireesh Nagabhushana #define S_FW_VI_STATS_CMD_VIID 0 543956b2bdd1SGireesh Nagabhushana #define M_FW_VI_STATS_CMD_VIID 0xfff 544056b2bdd1SGireesh Nagabhushana #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 544156b2bdd1SGireesh Nagabhushana #define G_FW_VI_STATS_CMD_VIID(x) \ 544256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 544356b2bdd1SGireesh Nagabhushana 544456b2bdd1SGireesh Nagabhushana #define S_FW_VI_STATS_CMD_NSTATS 12 544556b2bdd1SGireesh Nagabhushana #define M_FW_VI_STATS_CMD_NSTATS 0x7 544656b2bdd1SGireesh Nagabhushana #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 544756b2bdd1SGireesh Nagabhushana #define G_FW_VI_STATS_CMD_NSTATS(x) \ 544856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 544956b2bdd1SGireesh Nagabhushana 545056b2bdd1SGireesh Nagabhushana #define S_FW_VI_STATS_CMD_IX 0 545156b2bdd1SGireesh Nagabhushana #define M_FW_VI_STATS_CMD_IX 0x1f 545256b2bdd1SGireesh Nagabhushana #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 545356b2bdd1SGireesh Nagabhushana #define G_FW_VI_STATS_CMD_IX(x) \ 545456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 545556b2bdd1SGireesh Nagabhushana 545656b2bdd1SGireesh Nagabhushana struct fw_acl_mac_cmd { 545756b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 545856b2bdd1SGireesh Nagabhushana __be32 en_to_len16; 545956b2bdd1SGireesh Nagabhushana __u8 nmac; 546056b2bdd1SGireesh Nagabhushana __u8 r3[7]; 546156b2bdd1SGireesh Nagabhushana __be16 r4; 546256b2bdd1SGireesh Nagabhushana __u8 macaddr0[6]; 546356b2bdd1SGireesh Nagabhushana __be16 r5; 546456b2bdd1SGireesh Nagabhushana __u8 macaddr1[6]; 546556b2bdd1SGireesh Nagabhushana __be16 r6; 546656b2bdd1SGireesh Nagabhushana __u8 macaddr2[6]; 546756b2bdd1SGireesh Nagabhushana __be16 r7; 546856b2bdd1SGireesh Nagabhushana __u8 macaddr3[6]; 546956b2bdd1SGireesh Nagabhushana }; 547056b2bdd1SGireesh Nagabhushana 547156b2bdd1SGireesh Nagabhushana #define S_FW_ACL_MAC_CMD_PFN 8 547256b2bdd1SGireesh Nagabhushana #define M_FW_ACL_MAC_CMD_PFN 0x7 547356b2bdd1SGireesh Nagabhushana #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 547456b2bdd1SGireesh Nagabhushana #define G_FW_ACL_MAC_CMD_PFN(x) \ 547556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 547656b2bdd1SGireesh Nagabhushana 547756b2bdd1SGireesh Nagabhushana #define S_FW_ACL_MAC_CMD_VFN 0 547856b2bdd1SGireesh Nagabhushana #define M_FW_ACL_MAC_CMD_VFN 0xff 547956b2bdd1SGireesh Nagabhushana #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 548056b2bdd1SGireesh Nagabhushana #define G_FW_ACL_MAC_CMD_VFN(x) \ 548156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 548256b2bdd1SGireesh Nagabhushana 548356b2bdd1SGireesh Nagabhushana #define S_FW_ACL_MAC_CMD_EN 31 548456b2bdd1SGireesh Nagabhushana #define M_FW_ACL_MAC_CMD_EN 0x1 548556b2bdd1SGireesh Nagabhushana #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 548656b2bdd1SGireesh Nagabhushana #define G_FW_ACL_MAC_CMD_EN(x) \ 548756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 548856b2bdd1SGireesh Nagabhushana #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 548956b2bdd1SGireesh Nagabhushana 549056b2bdd1SGireesh Nagabhushana struct fw_acl_vlan_cmd { 549156b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 549256b2bdd1SGireesh Nagabhushana __be32 en_to_len16; 549356b2bdd1SGireesh Nagabhushana __u8 nvlan; 549456b2bdd1SGireesh Nagabhushana __u8 dropnovlan_fm; 549556b2bdd1SGireesh Nagabhushana __u8 r3_lo[6]; 549656b2bdd1SGireesh Nagabhushana __be16 vlanid[16]; 549756b2bdd1SGireesh Nagabhushana }; 549856b2bdd1SGireesh Nagabhushana 549956b2bdd1SGireesh Nagabhushana #define S_FW_ACL_VLAN_CMD_PFN 8 550056b2bdd1SGireesh Nagabhushana #define M_FW_ACL_VLAN_CMD_PFN 0x7 550156b2bdd1SGireesh Nagabhushana #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 550256b2bdd1SGireesh Nagabhushana #define G_FW_ACL_VLAN_CMD_PFN(x) \ 550356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 550456b2bdd1SGireesh Nagabhushana 550556b2bdd1SGireesh Nagabhushana #define S_FW_ACL_VLAN_CMD_VFN 0 550656b2bdd1SGireesh Nagabhushana #define M_FW_ACL_VLAN_CMD_VFN 0xff 550756b2bdd1SGireesh Nagabhushana #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 550856b2bdd1SGireesh Nagabhushana #define G_FW_ACL_VLAN_CMD_VFN(x) \ 550956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 551056b2bdd1SGireesh Nagabhushana 551156b2bdd1SGireesh Nagabhushana #define S_FW_ACL_VLAN_CMD_EN 31 551256b2bdd1SGireesh Nagabhushana #define M_FW_ACL_VLAN_CMD_EN 0x1 551356b2bdd1SGireesh Nagabhushana #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 551456b2bdd1SGireesh Nagabhushana #define G_FW_ACL_VLAN_CMD_EN(x) \ 551556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 551656b2bdd1SGireesh Nagabhushana #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 551756b2bdd1SGireesh Nagabhushana 551856b2bdd1SGireesh Nagabhushana #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 551956b2bdd1SGireesh Nagabhushana #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 552056b2bdd1SGireesh Nagabhushana #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 552156b2bdd1SGireesh Nagabhushana #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 552256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 552356b2bdd1SGireesh Nagabhushana #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 552456b2bdd1SGireesh Nagabhushana 552556b2bdd1SGireesh Nagabhushana #define S_FW_ACL_VLAN_CMD_FM 6 552656b2bdd1SGireesh Nagabhushana #define M_FW_ACL_VLAN_CMD_FM 0x1 552756b2bdd1SGireesh Nagabhushana #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 552856b2bdd1SGireesh Nagabhushana #define G_FW_ACL_VLAN_CMD_FM(x) \ 552956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 553056b2bdd1SGireesh Nagabhushana #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 553156b2bdd1SGireesh Nagabhushana 553256b2bdd1SGireesh Nagabhushana /* port capabilities bitmap */ 553356b2bdd1SGireesh Nagabhushana enum fw_port_cap { 553456b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_100M = 0x0001, 553556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_1G = 0x0002, 553656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_2_5G = 0x0004, 553756b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_10G = 0x0008, 553856b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_40G = 0x0010, 553956b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_100G = 0x0020, 554056b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FC_RX = 0x0040, 554156b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FC_TX = 0x0080, 554256b2bdd1SGireesh Nagabhushana FW_PORT_CAP_ANEG = 0x0100, 554356b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDIX = 0x0200, 554456b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDIAUTO = 0x0400, 554556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FEC = 0x0800, 554656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_TECHKR = 0x1000, 554756b2bdd1SGireesh Nagabhushana FW_PORT_CAP_TECHKX4 = 0x2000, 554856b2bdd1SGireesh Nagabhushana }; 554956b2bdd1SGireesh Nagabhushana 555056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_AUXLINFO_MDI 3 555156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_AUXLINFO_MDI 0x3 555256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 555356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_AUXLINFO_MDI(x) \ 555456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 555556b2bdd1SGireesh Nagabhushana 555656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_AUXLINFO_KX4 2 555756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_AUXLINFO_KX4 0x1 555856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 555956b2bdd1SGireesh Nagabhushana #define G_FW_PORT_AUXLINFO_KX4(x) \ 556056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 556156b2bdd1SGireesh Nagabhushana #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 556256b2bdd1SGireesh Nagabhushana 556356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_AUXLINFO_KR 1 556456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_AUXLINFO_KR 0x1 556556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 556656b2bdd1SGireesh Nagabhushana #define G_FW_PORT_AUXLINFO_KR(x) \ 556756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 556856b2bdd1SGireesh Nagabhushana #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 556956b2bdd1SGireesh Nagabhushana 557056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_AUXLINFO_FEC 0 557156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_AUXLINFO_FEC 0x1 557256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 557356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_AUXLINFO_FEC(x) \ 557456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 557556b2bdd1SGireesh Nagabhushana #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 557656b2bdd1SGireesh Nagabhushana 557756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_RCAP_AUX 11 557856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_RCAP_AUX 0x7 557956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 558056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_RCAP_AUX(x) \ 558156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 558256b2bdd1SGireesh Nagabhushana 558356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CAP_SPEED 0 558456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CAP_SPEED 0x3f 558556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 558656b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CAP_SPEED(x) \ 558756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 558856b2bdd1SGireesh Nagabhushana 558956b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CAP_FC 6 559056b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CAP_FC 0x3 559156b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 559256b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CAP_FC(x) \ 559356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 559456b2bdd1SGireesh Nagabhushana 559556b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CAP_ANEG 8 559656b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CAP_ANEG 0x1 559756b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 559856b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CAP_ANEG(x) \ 559956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 560056b2bdd1SGireesh Nagabhushana 560156b2bdd1SGireesh Nagabhushana enum fw_port_mdi { 560256b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_UNCHANGED, 560356b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_AUTO, 560456b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_F_STRAIGHT, 560556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_F_CROSSOVER 560656b2bdd1SGireesh Nagabhushana }; 560756b2bdd1SGireesh Nagabhushana 560856b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CAP_MDI 9 560956b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CAP_MDI 3 561056b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 561156b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 561256b2bdd1SGireesh Nagabhushana 561356b2bdd1SGireesh Nagabhushana enum fw_port_action { 561456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_CFG = 0x0001, 561556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_CFG = 0x0002, 561656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 561756b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 561856b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5619*de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5620*de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5621*de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_DET = 0x0008, 562256b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 562356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 562456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 562556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 562656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, 562756b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_MAC_LPBK = 0x0022, 562856b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, 562956b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, 5630*de483253SVishal Kulkarni FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 563156b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PCS_LPBK = 0x0028, 563256b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PHY_RESET = 0x0040, 563356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PMA_RESET = 0x0041, 563456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PCS_RESET = 0x0042, 563556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PHYXS_RESET = 0x0043, 563656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5637*de483253SVishal Kulkarni FW_PORT_ACTION_AN_RESET = 0x0045, 563856b2bdd1SGireesh Nagabhushana }; 563956b2bdd1SGireesh Nagabhushana 564056b2bdd1SGireesh Nagabhushana enum fw_port_l2cfg_ctlbf { 564156b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 564256b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 564356b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 564456b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 564556b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_IVLAN = 0x10, 564656b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_TXIPG = 0x20, 564756b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_MTU = 0x40 564856b2bdd1SGireesh Nagabhushana }; 564956b2bdd1SGireesh Nagabhushana 565056b2bdd1SGireesh Nagabhushana enum fw_port_dcb_cfg { 565156b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_PG = 0x01, 565256b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_PFC = 0x02, 565356b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_APPL = 0x04 565456b2bdd1SGireesh Nagabhushana }; 565556b2bdd1SGireesh Nagabhushana 565656b2bdd1SGireesh Nagabhushana enum fw_port_dcb_cfg_rc { 565756b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_SUCCESS = 0x0, 565856b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_ERROR = 0x1 565956b2bdd1SGireesh Nagabhushana }; 566056b2bdd1SGireesh Nagabhushana 566156b2bdd1SGireesh Nagabhushana enum fw_port_dcb_type { 566256b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PGID = 0x00, 566356b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PGRATE = 0x01, 566456b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PRIORATE = 0x02, 566556b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PFC = 0x03, 566656b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_APP_ID = 0x04, 5667*de483253SVishal Kulkarni FW_PORT_DCB_TYPE_CONTROL = 0x04, 5668*de483253SVishal Kulkarni }; 5669*de483253SVishal Kulkarni 5670*de483253SVishal Kulkarni enum fw_port_diag_ops { 5671*de483253SVishal Kulkarni FW_PORT_DIAGS_TEMP = 0x00, 5672*de483253SVishal Kulkarni FW_PORT_DIAGS_TX_POWER = 0x01, 5673*de483253SVishal Kulkarni FW_PORT_DIAGS_RX_POWER = 0x02, 567456b2bdd1SGireesh Nagabhushana }; 567556b2bdd1SGireesh Nagabhushana 567656b2bdd1SGireesh Nagabhushana struct fw_port_cmd { 567756b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 567856b2bdd1SGireesh Nagabhushana __be32 action_to_len16; 567956b2bdd1SGireesh Nagabhushana union fw_port { 568056b2bdd1SGireesh Nagabhushana struct fw_port_l1cfg { 568156b2bdd1SGireesh Nagabhushana __be32 rcap; 568256b2bdd1SGireesh Nagabhushana __be32 r; 568356b2bdd1SGireesh Nagabhushana } l1cfg; 568456b2bdd1SGireesh Nagabhushana struct fw_port_l2cfg { 568556b2bdd1SGireesh Nagabhushana __u8 ctlbf; 568656b2bdd1SGireesh Nagabhushana __u8 ovlan3_to_ivlan0; 568756b2bdd1SGireesh Nagabhushana __be16 ivlantype; 568856b2bdd1SGireesh Nagabhushana __be16 txipg_force_pinfo; 568956b2bdd1SGireesh Nagabhushana __be16 mtu; 569056b2bdd1SGireesh Nagabhushana __be16 ovlan0mask; 569156b2bdd1SGireesh Nagabhushana __be16 ovlan0type; 569256b2bdd1SGireesh Nagabhushana __be16 ovlan1mask; 569356b2bdd1SGireesh Nagabhushana __be16 ovlan1type; 569456b2bdd1SGireesh Nagabhushana __be16 ovlan2mask; 569556b2bdd1SGireesh Nagabhushana __be16 ovlan2type; 569656b2bdd1SGireesh Nagabhushana __be16 ovlan3mask; 569756b2bdd1SGireesh Nagabhushana __be16 ovlan3type; 569856b2bdd1SGireesh Nagabhushana } l2cfg; 569956b2bdd1SGireesh Nagabhushana struct fw_port_info { 570056b2bdd1SGireesh Nagabhushana __be32 lstatus_to_modtype; 570156b2bdd1SGireesh Nagabhushana __be16 pcap; 570256b2bdd1SGireesh Nagabhushana __be16 acap; 570356b2bdd1SGireesh Nagabhushana __be16 mtu; 570456b2bdd1SGireesh Nagabhushana __u8 cbllen; 570556b2bdd1SGireesh Nagabhushana __u8 auxlinfo; 570656b2bdd1SGireesh Nagabhushana __be32 r8; 570756b2bdd1SGireesh Nagabhushana __be64 r9; 570856b2bdd1SGireesh Nagabhushana } info; 5709*de483253SVishal Kulkarni struct fw_port_diags { 5710*de483253SVishal Kulkarni __u8 diagop; 5711*de483253SVishal Kulkarni __u8 r[3]; 5712*de483253SVishal Kulkarni __be32 diagval; 5713*de483253SVishal Kulkarni } diags; 571456b2bdd1SGireesh Nagabhushana union fw_port_dcb { 571556b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pgid { 571656b2bdd1SGireesh Nagabhushana __u8 type; 571756b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 571856b2bdd1SGireesh Nagabhushana __u8 r10_lo[2]; 571956b2bdd1SGireesh Nagabhushana __be32 pgid; 572056b2bdd1SGireesh Nagabhushana __be64 r11; 572156b2bdd1SGireesh Nagabhushana } pgid; 572256b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pgrate { 572356b2bdd1SGireesh Nagabhushana __u8 type; 572456b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 572556b2bdd1SGireesh Nagabhushana __u8 r10_lo[5]; 572656b2bdd1SGireesh Nagabhushana __u8 num_tcs_supported; 572756b2bdd1SGireesh Nagabhushana __u8 pgrate[8]; 572856b2bdd1SGireesh Nagabhushana } pgrate; 572956b2bdd1SGireesh Nagabhushana struct fw_port_dcb_priorate { 573056b2bdd1SGireesh Nagabhushana __u8 type; 573156b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 573256b2bdd1SGireesh Nagabhushana __u8 r10_lo[6]; 573356b2bdd1SGireesh Nagabhushana __u8 strict_priorate[8]; 573456b2bdd1SGireesh Nagabhushana } priorate; 573556b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pfc { 573656b2bdd1SGireesh Nagabhushana __u8 type; 573756b2bdd1SGireesh Nagabhushana __u8 pfcen; 573856b2bdd1SGireesh Nagabhushana __be16 r10[3]; 573956b2bdd1SGireesh Nagabhushana __be64 r11; 574056b2bdd1SGireesh Nagabhushana } pfc; 574156b2bdd1SGireesh Nagabhushana struct fw_port_app_priority { 574256b2bdd1SGireesh Nagabhushana __u8 type; 574356b2bdd1SGireesh Nagabhushana __u8 r10[2]; 574456b2bdd1SGireesh Nagabhushana __u8 idx; 574556b2bdd1SGireesh Nagabhushana __u8 user_prio_map; 574656b2bdd1SGireesh Nagabhushana __u8 sel_field; 574756b2bdd1SGireesh Nagabhushana __be16 protocolid; 574856b2bdd1SGireesh Nagabhushana __be64 r12; 574956b2bdd1SGireesh Nagabhushana } app_priority; 5750*de483253SVishal Kulkarni struct fw_port_dcb_control { 5751*de483253SVishal Kulkarni __u8 type; 5752*de483253SVishal Kulkarni __u8 all_syncd_pkd; 5753*de483253SVishal Kulkarni __be16 r10_lo[3]; 5754*de483253SVishal Kulkarni __be64 r11; 5755*de483253SVishal Kulkarni } control; 575656b2bdd1SGireesh Nagabhushana } dcb; 575756b2bdd1SGireesh Nagabhushana } u; 575856b2bdd1SGireesh Nagabhushana }; 575956b2bdd1SGireesh Nagabhushana 576056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_READ 22 576156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_READ 0x1 576256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 576356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_READ(x) \ 576456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 576556b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 576656b2bdd1SGireesh Nagabhushana 576756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_PORTID 0 576856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_PORTID 0xf 576956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 577056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_PORTID(x) \ 577156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 577256b2bdd1SGireesh Nagabhushana 577356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_ACTION 16 577456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_ACTION 0xffff 577556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 577656b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_ACTION(x) \ 577756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 577856b2bdd1SGireesh Nagabhushana 577956b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_OVLAN3 7 578056b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_OVLAN3 0x1 578156b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 578256b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_OVLAN3(x) \ 578356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 578456b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 578556b2bdd1SGireesh Nagabhushana 578656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_OVLAN2 6 578756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_OVLAN2 0x1 578856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 578956b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_OVLAN2(x) \ 579056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 579156b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 579256b2bdd1SGireesh Nagabhushana 579356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_OVLAN1 5 579456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_OVLAN1 0x1 579556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 579656b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_OVLAN1(x) \ 579756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 579856b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 579956b2bdd1SGireesh Nagabhushana 580056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_OVLAN0 4 580156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_OVLAN0 0x1 580256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 580356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_OVLAN0(x) \ 580456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 580556b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 580656b2bdd1SGireesh Nagabhushana 580756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_IVLAN0 3 580856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_IVLAN0 0x1 580956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 581056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_IVLAN0(x) \ 581156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 581256b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 581356b2bdd1SGireesh Nagabhushana 581456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_TXIPG 3 581556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_TXIPG 0x1fff 581656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 581756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_TXIPG(x) \ 581856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 581956b2bdd1SGireesh Nagabhushana 582056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_FORCE_PINFO 0 582156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_FORCE_PINFO 0x1 582256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 582356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 582456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 582556b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 582656b2bdd1SGireesh Nagabhushana 582756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_LSTATUS 31 582856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_LSTATUS 0x1 582956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 583056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_LSTATUS(x) \ 583156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 583256b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 583356b2bdd1SGireesh Nagabhushana 583456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_LSPEED 24 583556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_LSPEED 0x3f 583656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 583756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_LSPEED(x) \ 583856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 583956b2bdd1SGireesh Nagabhushana 584056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_TXPAUSE 23 584156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_TXPAUSE 0x1 584256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 584356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_TXPAUSE(x) \ 584456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 584556b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 584656b2bdd1SGireesh Nagabhushana 584756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_RXPAUSE 22 584856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_RXPAUSE 0x1 584956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 585056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_RXPAUSE(x) \ 585156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 585256b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 585356b2bdd1SGireesh Nagabhushana 585456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_MDIOCAP 21 585556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_MDIOCAP 0x1 585656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 585756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_MDIOCAP(x) \ 585856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 585956b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 586056b2bdd1SGireesh Nagabhushana 586156b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_MDIOADDR 16 586256b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_MDIOADDR 0x1f 586356b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 586456b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_MDIOADDR(x) \ 586556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 586656b2bdd1SGireesh Nagabhushana 586756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_LPTXPAUSE 15 586856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_LPTXPAUSE 0x1 586956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 587056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 587156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 587256b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 587356b2bdd1SGireesh Nagabhushana 587456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_LPRXPAUSE 14 587556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_LPRXPAUSE 0x1 587656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 587756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 587856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 587956b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 588056b2bdd1SGireesh Nagabhushana 588156b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_PTYPE 8 588256b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_PTYPE 0x1f 588356b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 588456b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_PTYPE(x) \ 588556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 588656b2bdd1SGireesh Nagabhushana 588756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_LINKDNRC 5 588856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_LINKDNRC 0x7 588956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 589056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_LINKDNRC(x) \ 589156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 589256b2bdd1SGireesh Nagabhushana 589356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_MODTYPE 0 589456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_MODTYPE 0x1f 589556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 589656b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_MODTYPE(x) \ 589756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 589856b2bdd1SGireesh Nagabhushana 589956b2bdd1SGireesh Nagabhushana #define S_FW_PORT_CMD_APPLY 7 590056b2bdd1SGireesh Nagabhushana #define M_FW_PORT_CMD_APPLY 0x1 590156b2bdd1SGireesh Nagabhushana #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 590256b2bdd1SGireesh Nagabhushana #define G_FW_PORT_CMD_APPLY(x) \ 590356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 590456b2bdd1SGireesh Nagabhushana #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 590556b2bdd1SGireesh Nagabhushana 5906*de483253SVishal Kulkarni #define S_FW_PORT_CMD_ALL_SYNCD 7 5907*de483253SVishal Kulkarni #define M_FW_PORT_CMD_ALL_SYNCD 0x1 5908*de483253SVishal Kulkarni #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 5909*de483253SVishal Kulkarni #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 5910*de483253SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 5911*de483253SVishal Kulkarni #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 5912*de483253SVishal Kulkarni 591356b2bdd1SGireesh Nagabhushana /* 591456b2bdd1SGireesh Nagabhushana * These are configured into the VPD and hence tools that generate 591556b2bdd1SGireesh Nagabhushana * VPD may use this enumeration. 591656b2bdd1SGireesh Nagabhushana * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 591756b2bdd1SGireesh Nagabhushana */ 591856b2bdd1SGireesh Nagabhushana enum fw_port_type { 591956b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 592056b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 592156b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 592256b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 592356b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 592456b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 592556b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 592656b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 592756b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 592856b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 592956b2bdd1SGireesh Nagabhushana /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 593056b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BP_AP = 10, 593156b2bdd1SGireesh Nagabhushana /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 593256b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BP4_AP = 11, 5933*de483253SVishal Kulkarni FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 5934*de483253SVishal Kulkarni FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 5935*de483253SVishal Kulkarni /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 5936*de483253SVishal Kulkarni FW_PORT_TYPE_BP40_BA = 15, 593756b2bdd1SGireesh Nagabhushana 593856b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 593956b2bdd1SGireesh Nagabhushana }; 594056b2bdd1SGireesh Nagabhushana 594156b2bdd1SGireesh Nagabhushana /* 594256b2bdd1SGireesh Nagabhushana * These are read from module's EEPROM and determined once the module is 594356b2bdd1SGireesh Nagabhushana * inserted. 594456b2bdd1SGireesh Nagabhushana */ 594556b2bdd1SGireesh Nagabhushana enum fw_port_module_type { 594656b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NA = 0x0, 594756b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_LR = 0x1, 594856b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_SR = 0x2, 594956b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_ER = 0x3, 595056b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 595156b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 595256b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_LRM = 0x6, 595356b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 595456b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 595556b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 595656b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 595756b2bdd1SGireesh Nagabhushana }; 595856b2bdd1SGireesh Nagabhushana 595956b2bdd1SGireesh Nagabhushana /* used by FW and tools may use this to generate VPD */ 596056b2bdd1SGireesh Nagabhushana enum fw_port_mod_sub_type { 596156b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_NA, 596256b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 5963*de483253SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 5964*de483253SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 5965*de483253SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 5966*de483253SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 5967*de483253SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 596856b2bdd1SGireesh Nagabhushana 596956b2bdd1SGireesh Nagabhushana /* 597056b2bdd1SGireesh Nagabhushana * The following will never been in the VPD. They are TWINAX cable 597156b2bdd1SGireesh Nagabhushana * lengths decoded from SFP+ module i2c PROMs. These should almost 597256b2bdd1SGireesh Nagabhushana * certainly go somewhere else ... 597356b2bdd1SGireesh Nagabhushana */ 597456b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 597556b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 597656b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 597756b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 597856b2bdd1SGireesh Nagabhushana }; 597956b2bdd1SGireesh Nagabhushana 598056b2bdd1SGireesh Nagabhushana /* link down reason codes (3b) */ 598156b2bdd1SGireesh Nagabhushana enum fw_port_link_dn_rc { 598256b2bdd1SGireesh Nagabhushana FW_PORT_LINK_DN_RC_NONE, 5983*de483253SVishal Kulkarni FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 5984*de483253SVishal Kulkarni FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 5985*de483253SVishal Kulkarni FW_PORT_LINK_DN_RESERVED3, 5986*de483253SVishal Kulkarni FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 5987*de483253SVishal Kulkarni FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 5988*de483253SVishal Kulkarni FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 5989*de483253SVishal Kulkarni FW_PORT_LINK_DN_RESERVED7 599056b2bdd1SGireesh Nagabhushana }; 599156b2bdd1SGireesh Nagabhushana 599256b2bdd1SGireesh Nagabhushana /* port stats */ 599356b2bdd1SGireesh Nagabhushana #define FW_NUM_PORT_STATS 50 599456b2bdd1SGireesh Nagabhushana #define FW_NUM_PORT_TX_STATS 23 599556b2bdd1SGireesh Nagabhushana #define FW_NUM_PORT_RX_STATS 27 599656b2bdd1SGireesh Nagabhushana 599756b2bdd1SGireesh Nagabhushana enum fw_port_stats_tx_index { 599856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_BYTES_IX, 599956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_FRAMES_IX, 600056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_BCAST_IX, 600156b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_MCAST_IX, 600256b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_UCAST_IX, 600356b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_ERROR_IX, 600456b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_64B_IX, 600556b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_65B_127B_IX, 600656b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_128B_255B_IX, 600756b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_256B_511B_IX, 600856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_512B_1023B_IX, 600956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_1024B_1518B_IX, 601056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_1519B_MAX_IX, 601156b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_DROP_IX, 601256b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PAUSE_IX, 601356b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP0_IX, 601456b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP1_IX, 601556b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP2_IX, 601656b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP3_IX, 601756b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP4_IX, 601856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP5_IX, 601956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP6_IX, 602056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP7_IX 602156b2bdd1SGireesh Nagabhushana }; 602256b2bdd1SGireesh Nagabhushana 602356b2bdd1SGireesh Nagabhushana enum fw_port_stat_rx_index { 602456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_BYTES_IX, 602556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_FRAMES_IX, 602656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_BCAST_IX, 602756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MCAST_IX, 602856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_UCAST_IX, 602956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MTU_ERROR_IX, 603056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 603156b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_CRC_ERROR_IX, 603256b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_LEN_ERROR_IX, 603356b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_SYM_ERROR_IX, 603456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_64B_IX, 603556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_65B_127B_IX, 603656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_128B_255B_IX, 603756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_256B_511B_IX, 603856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_512B_1023B_IX, 603956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_1024B_1518B_IX, 604056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_1519B_MAX_IX, 604156b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PAUSE_IX, 604256b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP0_IX, 604356b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP1_IX, 604456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP2_IX, 604556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP3_IX, 604656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP4_IX, 604756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP5_IX, 604856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP6_IX, 604956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP7_IX, 605056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_LESS_64B_IX 605156b2bdd1SGireesh Nagabhushana }; 605256b2bdd1SGireesh Nagabhushana 605356b2bdd1SGireesh Nagabhushana struct fw_port_stats_cmd { 605456b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 605556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 605656b2bdd1SGireesh Nagabhushana union fw_port_stats { 605756b2bdd1SGireesh Nagabhushana struct fw_port_stats_ctl { 605856b2bdd1SGireesh Nagabhushana __u8 nstats_bg_bm; 605956b2bdd1SGireesh Nagabhushana __u8 tx_ix; 606056b2bdd1SGireesh Nagabhushana __be16 r6; 606156b2bdd1SGireesh Nagabhushana __be32 r7; 606256b2bdd1SGireesh Nagabhushana __be64 stat0; 606356b2bdd1SGireesh Nagabhushana __be64 stat1; 606456b2bdd1SGireesh Nagabhushana __be64 stat2; 606556b2bdd1SGireesh Nagabhushana __be64 stat3; 606656b2bdd1SGireesh Nagabhushana __be64 stat4; 606756b2bdd1SGireesh Nagabhushana __be64 stat5; 606856b2bdd1SGireesh Nagabhushana } ctl; 606956b2bdd1SGireesh Nagabhushana struct fw_port_stats_all { 607056b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 607156b2bdd1SGireesh Nagabhushana __be64 tx_frames; 607256b2bdd1SGireesh Nagabhushana __be64 tx_bcast; 607356b2bdd1SGireesh Nagabhushana __be64 tx_mcast; 607456b2bdd1SGireesh Nagabhushana __be64 tx_ucast; 607556b2bdd1SGireesh Nagabhushana __be64 tx_error; 607656b2bdd1SGireesh Nagabhushana __be64 tx_64b; 607756b2bdd1SGireesh Nagabhushana __be64 tx_65b_127b; 607856b2bdd1SGireesh Nagabhushana __be64 tx_128b_255b; 607956b2bdd1SGireesh Nagabhushana __be64 tx_256b_511b; 608056b2bdd1SGireesh Nagabhushana __be64 tx_512b_1023b; 608156b2bdd1SGireesh Nagabhushana __be64 tx_1024b_1518b; 608256b2bdd1SGireesh Nagabhushana __be64 tx_1519b_max; 608356b2bdd1SGireesh Nagabhushana __be64 tx_drop; 608456b2bdd1SGireesh Nagabhushana __be64 tx_pause; 608556b2bdd1SGireesh Nagabhushana __be64 tx_ppp0; 608656b2bdd1SGireesh Nagabhushana __be64 tx_ppp1; 608756b2bdd1SGireesh Nagabhushana __be64 tx_ppp2; 608856b2bdd1SGireesh Nagabhushana __be64 tx_ppp3; 608956b2bdd1SGireesh Nagabhushana __be64 tx_ppp4; 609056b2bdd1SGireesh Nagabhushana __be64 tx_ppp5; 609156b2bdd1SGireesh Nagabhushana __be64 tx_ppp6; 609256b2bdd1SGireesh Nagabhushana __be64 tx_ppp7; 609356b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 609456b2bdd1SGireesh Nagabhushana __be64 rx_frames; 609556b2bdd1SGireesh Nagabhushana __be64 rx_bcast; 609656b2bdd1SGireesh Nagabhushana __be64 rx_mcast; 609756b2bdd1SGireesh Nagabhushana __be64 rx_ucast; 609856b2bdd1SGireesh Nagabhushana __be64 rx_mtu_error; 609956b2bdd1SGireesh Nagabhushana __be64 rx_mtu_crc_error; 610056b2bdd1SGireesh Nagabhushana __be64 rx_crc_error; 610156b2bdd1SGireesh Nagabhushana __be64 rx_len_error; 610256b2bdd1SGireesh Nagabhushana __be64 rx_sym_error; 610356b2bdd1SGireesh Nagabhushana __be64 rx_64b; 610456b2bdd1SGireesh Nagabhushana __be64 rx_65b_127b; 610556b2bdd1SGireesh Nagabhushana __be64 rx_128b_255b; 610656b2bdd1SGireesh Nagabhushana __be64 rx_256b_511b; 610756b2bdd1SGireesh Nagabhushana __be64 rx_512b_1023b; 610856b2bdd1SGireesh Nagabhushana __be64 rx_1024b_1518b; 610956b2bdd1SGireesh Nagabhushana __be64 rx_1519b_max; 611056b2bdd1SGireesh Nagabhushana __be64 rx_pause; 611156b2bdd1SGireesh Nagabhushana __be64 rx_ppp0; 611256b2bdd1SGireesh Nagabhushana __be64 rx_ppp1; 611356b2bdd1SGireesh Nagabhushana __be64 rx_ppp2; 611456b2bdd1SGireesh Nagabhushana __be64 rx_ppp3; 611556b2bdd1SGireesh Nagabhushana __be64 rx_ppp4; 611656b2bdd1SGireesh Nagabhushana __be64 rx_ppp5; 611756b2bdd1SGireesh Nagabhushana __be64 rx_ppp6; 611856b2bdd1SGireesh Nagabhushana __be64 rx_ppp7; 611956b2bdd1SGireesh Nagabhushana __be64 rx_less_64b; 612056b2bdd1SGireesh Nagabhushana __be64 rx_bg_drop; 612156b2bdd1SGireesh Nagabhushana __be64 rx_bg_trunc; 612256b2bdd1SGireesh Nagabhushana } all; 612356b2bdd1SGireesh Nagabhushana } u; 612456b2bdd1SGireesh Nagabhushana }; 612556b2bdd1SGireesh Nagabhushana 612656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_STATS_CMD_NSTATS 4 612756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_STATS_CMD_NSTATS 0x7 612856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 612956b2bdd1SGireesh Nagabhushana #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 613056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 613156b2bdd1SGireesh Nagabhushana 613256b2bdd1SGireesh Nagabhushana #define S_FW_PORT_STATS_CMD_BG_BM 0 613356b2bdd1SGireesh Nagabhushana #define M_FW_PORT_STATS_CMD_BG_BM 0x3 613456b2bdd1SGireesh Nagabhushana #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 613556b2bdd1SGireesh Nagabhushana #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 613656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 613756b2bdd1SGireesh Nagabhushana 613856b2bdd1SGireesh Nagabhushana #define S_FW_PORT_STATS_CMD_TX 7 613956b2bdd1SGireesh Nagabhushana #define M_FW_PORT_STATS_CMD_TX 0x1 614056b2bdd1SGireesh Nagabhushana #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 614156b2bdd1SGireesh Nagabhushana #define G_FW_PORT_STATS_CMD_TX(x) \ 614256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 614356b2bdd1SGireesh Nagabhushana #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 614456b2bdd1SGireesh Nagabhushana 614556b2bdd1SGireesh Nagabhushana #define S_FW_PORT_STATS_CMD_IX 0 614656b2bdd1SGireesh Nagabhushana #define M_FW_PORT_STATS_CMD_IX 0x3f 614756b2bdd1SGireesh Nagabhushana #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 614856b2bdd1SGireesh Nagabhushana #define G_FW_PORT_STATS_CMD_IX(x) \ 614956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 615056b2bdd1SGireesh Nagabhushana 615156b2bdd1SGireesh Nagabhushana /* port loopback stats */ 615256b2bdd1SGireesh Nagabhushana #define FW_NUM_LB_STATS 14 615356b2bdd1SGireesh Nagabhushana enum fw_port_lb_stats_index { 615456b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_BYTES_IX, 615556b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_FRAMES_IX, 615656b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_BCAST_IX, 615756b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_MCAST_IX, 615856b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_UCAST_IX, 615956b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_ERROR_IX, 616056b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_64B_IX, 616156b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_65B_127B_IX, 616256b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_128B_255B_IX, 616356b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_256B_511B_IX, 616456b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_512B_1023B_IX, 616556b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_1024B_1518B_IX, 616656b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_1519B_MAX_IX, 616756b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_DROP_FRAMES_IX 616856b2bdd1SGireesh Nagabhushana }; 616956b2bdd1SGireesh Nagabhushana 617056b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_cmd { 617156b2bdd1SGireesh Nagabhushana __be32 op_to_lbport; 617256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 617356b2bdd1SGireesh Nagabhushana union fw_port_lb_stats { 617456b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_ctl { 617556b2bdd1SGireesh Nagabhushana __u8 nstats_bg_bm; 617656b2bdd1SGireesh Nagabhushana __u8 ix_pkd; 617756b2bdd1SGireesh Nagabhushana __be16 r6; 617856b2bdd1SGireesh Nagabhushana __be32 r7; 617956b2bdd1SGireesh Nagabhushana __be64 stat0; 618056b2bdd1SGireesh Nagabhushana __be64 stat1; 618156b2bdd1SGireesh Nagabhushana __be64 stat2; 618256b2bdd1SGireesh Nagabhushana __be64 stat3; 618356b2bdd1SGireesh Nagabhushana __be64 stat4; 618456b2bdd1SGireesh Nagabhushana __be64 stat5; 618556b2bdd1SGireesh Nagabhushana } ctl; 618656b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_all { 618756b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 618856b2bdd1SGireesh Nagabhushana __be64 tx_frames; 618956b2bdd1SGireesh Nagabhushana __be64 tx_bcast; 619056b2bdd1SGireesh Nagabhushana __be64 tx_mcast; 619156b2bdd1SGireesh Nagabhushana __be64 tx_ucast; 619256b2bdd1SGireesh Nagabhushana __be64 tx_error; 619356b2bdd1SGireesh Nagabhushana __be64 tx_64b; 619456b2bdd1SGireesh Nagabhushana __be64 tx_65b_127b; 619556b2bdd1SGireesh Nagabhushana __be64 tx_128b_255b; 619656b2bdd1SGireesh Nagabhushana __be64 tx_256b_511b; 619756b2bdd1SGireesh Nagabhushana __be64 tx_512b_1023b; 619856b2bdd1SGireesh Nagabhushana __be64 tx_1024b_1518b; 619956b2bdd1SGireesh Nagabhushana __be64 tx_1519b_max; 620056b2bdd1SGireesh Nagabhushana __be64 rx_lb_drop; 620156b2bdd1SGireesh Nagabhushana __be64 rx_lb_trunc; 620256b2bdd1SGireesh Nagabhushana } all; 620356b2bdd1SGireesh Nagabhushana } u; 620456b2bdd1SGireesh Nagabhushana }; 620556b2bdd1SGireesh Nagabhushana 620656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 620756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 620856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 620956b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 621056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 621156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 621256b2bdd1SGireesh Nagabhushana 621356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 621456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 621556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 621656b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 621756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 621856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 621956b2bdd1SGireesh Nagabhushana 622056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 622156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 622256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 622356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 622456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 622556b2bdd1SGireesh Nagabhushana 622656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_LB_STATS_CMD_IX 0 622756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_LB_STATS_CMD_IX 0xf 622856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 622956b2bdd1SGireesh Nagabhushana #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 623056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 623156b2bdd1SGireesh Nagabhushana 623256b2bdd1SGireesh Nagabhushana /* Trace related defines */ 623356b2bdd1SGireesh Nagabhushana #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 623456b2bdd1SGireesh Nagabhushana #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 623556b2bdd1SGireesh Nagabhushana 623656b2bdd1SGireesh Nagabhushana struct fw_port_trace_cmd { 623756b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 623856b2bdd1SGireesh Nagabhushana __be32 retval_len16; 623956b2bdd1SGireesh Nagabhushana __be16 traceen_to_pciech; 624056b2bdd1SGireesh Nagabhushana __be16 qnum; 624156b2bdd1SGireesh Nagabhushana __be32 r5; 624256b2bdd1SGireesh Nagabhushana }; 624356b2bdd1SGireesh Nagabhushana 624456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_CMD_PORTID 0 624556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_CMD_PORTID 0xf 624656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 624756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 624856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 624956b2bdd1SGireesh Nagabhushana 625056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_CMD_TRACEEN 15 625156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 625256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 625356b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 625456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 625556b2bdd1SGireesh Nagabhushana #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 625656b2bdd1SGireesh Nagabhushana 625756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_CMD_FLTMODE 14 625856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 625956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 626056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 626156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 626256b2bdd1SGireesh Nagabhushana #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 626356b2bdd1SGireesh Nagabhushana 626456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_CMD_DUPLEN 13 626556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 626656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 626756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 626856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 626956b2bdd1SGireesh Nagabhushana #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 627056b2bdd1SGireesh Nagabhushana 627156b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 627256b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 627356b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 627456b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 627556b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 627656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 627756b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 627856b2bdd1SGireesh Nagabhushana 627956b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_CMD_PCIECH 6 628056b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 628156b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 628256b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 628356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 628456b2bdd1SGireesh Nagabhushana 628556b2bdd1SGireesh Nagabhushana struct fw_port_trace_mmap_cmd { 628656b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 628756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 628856b2bdd1SGireesh Nagabhushana __be32 fid_to_skipoffset; 628956b2bdd1SGireesh Nagabhushana __be32 minpktsize_capturemax; 629056b2bdd1SGireesh Nagabhushana __u8 map[224]; 629156b2bdd1SGireesh Nagabhushana }; 629256b2bdd1SGireesh Nagabhushana 629356b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 629456b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 629556b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 629656b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 629756b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 629856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 629956b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_PORTID) 630056b2bdd1SGireesh Nagabhushana 630156b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 630256b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 630356b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 630456b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 630556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 630656b2bdd1SGireesh Nagabhushana 630756b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 630856b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 630956b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 631056b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 631156b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 631256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 631356b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 631456b2bdd1SGireesh Nagabhushana #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 631556b2bdd1SGireesh Nagabhushana 631656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 631756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 631856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 631956b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 632056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 632156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 632256b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 632356b2bdd1SGireesh Nagabhushana #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 632456b2bdd1SGireesh Nagabhushana V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 632556b2bdd1SGireesh Nagabhushana 632656b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 632756b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 632856b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 632956b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 633056b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 633156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 633256b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 633356b2bdd1SGireesh Nagabhushana 633456b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 633556b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 633656b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 633756b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 633856b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 633956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 634056b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 634156b2bdd1SGireesh Nagabhushana 634256b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 634356b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 634456b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 634556b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 634656b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 634756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 634856b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 634956b2bdd1SGireesh Nagabhushana 635056b2bdd1SGireesh Nagabhushana #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 635156b2bdd1SGireesh Nagabhushana #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 635256b2bdd1SGireesh Nagabhushana #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 635356b2bdd1SGireesh Nagabhushana ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 635456b2bdd1SGireesh Nagabhushana #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 635556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 635656b2bdd1SGireesh Nagabhushana M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 635756b2bdd1SGireesh Nagabhushana 635856b2bdd1SGireesh Nagabhushana struct fw_rss_ind_tbl_cmd { 635956b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 636056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 636156b2bdd1SGireesh Nagabhushana __be16 niqid; 636256b2bdd1SGireesh Nagabhushana __be16 startidx; 636356b2bdd1SGireesh Nagabhushana __be32 r3; 636456b2bdd1SGireesh Nagabhushana __be32 iq0_to_iq2; 636556b2bdd1SGireesh Nagabhushana __be32 iq3_to_iq5; 636656b2bdd1SGireesh Nagabhushana __be32 iq6_to_iq8; 636756b2bdd1SGireesh Nagabhushana __be32 iq9_to_iq11; 636856b2bdd1SGireesh Nagabhushana __be32 iq12_to_iq14; 636956b2bdd1SGireesh Nagabhushana __be32 iq15_to_iq17; 637056b2bdd1SGireesh Nagabhushana __be32 iq18_to_iq20; 637156b2bdd1SGireesh Nagabhushana __be32 iq21_to_iq23; 637256b2bdd1SGireesh Nagabhushana __be32 iq24_to_iq26; 637356b2bdd1SGireesh Nagabhushana __be32 iq27_to_iq29; 637456b2bdd1SGireesh Nagabhushana __be32 iq30_iq31; 637556b2bdd1SGireesh Nagabhushana __be32 r15_lo; 637656b2bdd1SGireesh Nagabhushana }; 637756b2bdd1SGireesh Nagabhushana 637856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_VIID 0 637956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 638056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 638156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 638256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 638356b2bdd1SGireesh Nagabhushana 638456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ0 20 638556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 638656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 638756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 638856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 638956b2bdd1SGireesh Nagabhushana 639056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ1 10 639156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 639256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 639356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 639456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 639556b2bdd1SGireesh Nagabhushana 639656b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ2 0 639756b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 639856b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 639956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 640056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 640156b2bdd1SGireesh Nagabhushana 640256b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ3 20 640356b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 640456b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 640556b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 640656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 640756b2bdd1SGireesh Nagabhushana 640856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ4 10 640956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 641056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 641156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 641256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 641356b2bdd1SGireesh Nagabhushana 641456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ5 0 641556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 641656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 641756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 641856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 641956b2bdd1SGireesh Nagabhushana 642056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ6 20 642156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 642256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 642356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 642456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 642556b2bdd1SGireesh Nagabhushana 642656b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ7 10 642756b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 642856b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 642956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 643056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 643156b2bdd1SGireesh Nagabhushana 643256b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ8 0 643356b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 643456b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 643556b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 643656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 643756b2bdd1SGireesh Nagabhushana 643856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ9 20 643956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 644056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 644156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 644256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 644356b2bdd1SGireesh Nagabhushana 644456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ10 10 644556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 644656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 644756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 644856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 644956b2bdd1SGireesh Nagabhushana 645056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ11 0 645156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 645256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 645356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 645456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 645556b2bdd1SGireesh Nagabhushana 645656b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ12 20 645756b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 645856b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 645956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 646056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 646156b2bdd1SGireesh Nagabhushana 646256b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ13 10 646356b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 646456b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 646556b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 646656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 646756b2bdd1SGireesh Nagabhushana 646856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ14 0 646956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 647056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 647156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 647256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 647356b2bdd1SGireesh Nagabhushana 647456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ15 20 647556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 647656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 647756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 647856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 647956b2bdd1SGireesh Nagabhushana 648056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ16 10 648156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 648256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 648356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 648456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 648556b2bdd1SGireesh Nagabhushana 648656b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ17 0 648756b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 648856b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 648956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 649056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 649156b2bdd1SGireesh Nagabhushana 649256b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ18 20 649356b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 649456b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 649556b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 649656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 649756b2bdd1SGireesh Nagabhushana 649856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ19 10 649956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 650056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 650156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 650256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 650356b2bdd1SGireesh Nagabhushana 650456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ20 0 650556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 650656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 650756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 650856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 650956b2bdd1SGireesh Nagabhushana 651056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ21 20 651156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 651256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 651356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 651456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 651556b2bdd1SGireesh Nagabhushana 651656b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ22 10 651756b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 651856b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 651956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 652056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 652156b2bdd1SGireesh Nagabhushana 652256b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ23 0 652356b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 652456b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 652556b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 652656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 652756b2bdd1SGireesh Nagabhushana 652856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ24 20 652956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 653056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 653156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 653256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 653356b2bdd1SGireesh Nagabhushana 653456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ25 10 653556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 653656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 653756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 653856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 653956b2bdd1SGireesh Nagabhushana 654056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ26 0 654156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 654256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 654356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 654456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 654556b2bdd1SGireesh Nagabhushana 654656b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ27 20 654756b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 654856b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 654956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 655056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 655156b2bdd1SGireesh Nagabhushana 655256b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ28 10 655356b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 655456b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 655556b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 655656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 655756b2bdd1SGireesh Nagabhushana 655856b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ29 0 655956b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 656056b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 656156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 656256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 656356b2bdd1SGireesh Nagabhushana 656456b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ30 20 656556b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 656656b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 656756b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 656856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 656956b2bdd1SGireesh Nagabhushana 657056b2bdd1SGireesh Nagabhushana #define S_FW_RSS_IND_TBL_CMD_IQ31 10 657156b2bdd1SGireesh Nagabhushana #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 657256b2bdd1SGireesh Nagabhushana #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 657356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 657456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 657556b2bdd1SGireesh Nagabhushana 657656b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_cmd { 657756b2bdd1SGireesh Nagabhushana __be32 op_to_write; 657856b2bdd1SGireesh Nagabhushana __be32 retval_len16; 657956b2bdd1SGireesh Nagabhushana union fw_rss_glb_config { 658056b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_manual { 658156b2bdd1SGireesh Nagabhushana __be32 mode_pkd; 658256b2bdd1SGireesh Nagabhushana __be32 r3; 658356b2bdd1SGireesh Nagabhushana __be64 r4; 658456b2bdd1SGireesh Nagabhushana __be64 r5; 658556b2bdd1SGireesh Nagabhushana } manual; 658656b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_basicvirtual { 658756b2bdd1SGireesh Nagabhushana __be32 mode_pkd; 658856b2bdd1SGireesh Nagabhushana __be32 synmapen_to_hashtoeplitz; 658956b2bdd1SGireesh Nagabhushana __be64 r8; 659056b2bdd1SGireesh Nagabhushana __be64 r9; 659156b2bdd1SGireesh Nagabhushana } basicvirtual; 659256b2bdd1SGireesh Nagabhushana } u; 659356b2bdd1SGireesh Nagabhushana }; 659456b2bdd1SGireesh Nagabhushana 659556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 659656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 659756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 659856b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 659956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 660056b2bdd1SGireesh Nagabhushana 660156b2bdd1SGireesh Nagabhushana #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 660256b2bdd1SGireesh Nagabhushana #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 660356b2bdd1SGireesh Nagabhushana #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 660456b2bdd1SGireesh Nagabhushana 660556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 660656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 660756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 660856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 660956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 661056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 661156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 661256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 661356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 661456b2bdd1SGireesh Nagabhushana 661556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 661656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 661756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 661856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 661956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 662056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 662156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 662256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 662356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 662456b2bdd1SGireesh Nagabhushana 662556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 662656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 662756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 662856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 662956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 663056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 663156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 663256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 663356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 663456b2bdd1SGireesh Nagabhushana 663556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 663656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 663756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 663856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 663956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 664056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 664156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 664256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 664356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 664456b2bdd1SGireesh Nagabhushana 664556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 664656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 664756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 664856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 664956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 665056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 665156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 665256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 665356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 665456b2bdd1SGireesh Nagabhushana 665556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 665656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 665756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 665856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 665956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 666056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 666156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 666256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 666356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 666456b2bdd1SGireesh Nagabhushana 666556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 666656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 666756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 666856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 666956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 667056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 667156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 667256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 667356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 667456b2bdd1SGireesh Nagabhushana 667556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 667656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 667756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 667856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 667956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 668056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 668156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 668256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 668356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 668456b2bdd1SGireesh Nagabhushana 668556b2bdd1SGireesh Nagabhushana #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 668656b2bdd1SGireesh Nagabhushana #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 668756b2bdd1SGireesh Nagabhushana #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 668856b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 668956b2bdd1SGireesh Nagabhushana #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 669056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 669156b2bdd1SGireesh Nagabhushana M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 669256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 669356b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 669456b2bdd1SGireesh Nagabhushana 669556b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_cmd { 669656b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 669756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 669856b2bdd1SGireesh Nagabhushana union fw_rss_vi_config { 669956b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_manual { 670056b2bdd1SGireesh Nagabhushana __be64 r3; 670156b2bdd1SGireesh Nagabhushana __be64 r4; 670256b2bdd1SGireesh Nagabhushana __be64 r5; 670356b2bdd1SGireesh Nagabhushana } manual; 670456b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_basicvirtual { 670556b2bdd1SGireesh Nagabhushana __be32 r6; 670656b2bdd1SGireesh Nagabhushana __be32 defaultq_to_udpen; 670756b2bdd1SGireesh Nagabhushana __be64 r9; 670856b2bdd1SGireesh Nagabhushana __be64 r10; 670956b2bdd1SGireesh Nagabhushana } basicvirtual; 671056b2bdd1SGireesh Nagabhushana } u; 671156b2bdd1SGireesh Nagabhushana }; 671256b2bdd1SGireesh Nagabhushana 671356b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 671456b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 671556b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 671656b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 671756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 671856b2bdd1SGireesh Nagabhushana 671956b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 672056b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 672156b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 672256b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 672356b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 672456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 672556b2bdd1SGireesh Nagabhushana M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 672656b2bdd1SGireesh Nagabhushana 672756b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 672856b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 672956b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 673056b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 673156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 673256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 673356b2bdd1SGireesh Nagabhushana M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 673456b2bdd1SGireesh Nagabhushana #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 673556b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 673656b2bdd1SGireesh Nagabhushana 673756b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 673856b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 673956b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 674056b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 674156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 674256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 674356b2bdd1SGireesh Nagabhushana M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 674456b2bdd1SGireesh Nagabhushana #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 674556b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 674656b2bdd1SGireesh Nagabhushana 674756b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 674856b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 674956b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 675056b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 675156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 675256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 675356b2bdd1SGireesh Nagabhushana M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 675456b2bdd1SGireesh Nagabhushana #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 675556b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 675656b2bdd1SGireesh Nagabhushana 675756b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 675856b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 675956b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 676056b2bdd1SGireesh Nagabhushana ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 676156b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 676256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 676356b2bdd1SGireesh Nagabhushana M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 676456b2bdd1SGireesh Nagabhushana #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 676556b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 676656b2bdd1SGireesh Nagabhushana 676756b2bdd1SGireesh Nagabhushana #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 676856b2bdd1SGireesh Nagabhushana #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 676956b2bdd1SGireesh Nagabhushana #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 677056b2bdd1SGireesh Nagabhushana #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 677156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 677256b2bdd1SGireesh Nagabhushana #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 677356b2bdd1SGireesh Nagabhushana 677456b2bdd1SGireesh Nagabhushana enum fw_sched_sc { 677556b2bdd1SGireesh Nagabhushana FW_SCHED_SC_CONFIG = 0, 677656b2bdd1SGireesh Nagabhushana FW_SCHED_SC_PARAMS = 1, 677756b2bdd1SGireesh Nagabhushana }; 677856b2bdd1SGireesh Nagabhushana 677956b2bdd1SGireesh Nagabhushana enum fw_sched_type { 678056b2bdd1SGireesh Nagabhushana FW_SCHED_TYPE_PKTSCHED = 0, 678156b2bdd1SGireesh Nagabhushana FW_SCHED_TYPE_STREAMSCHED = 1, 678256b2bdd1SGireesh Nagabhushana }; 678356b2bdd1SGireesh Nagabhushana 678456b2bdd1SGireesh Nagabhushana enum fw_sched_params_level { 678556b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 678656b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 678756b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 678856b2bdd1SGireesh Nagabhushana }; 678956b2bdd1SGireesh Nagabhushana 679056b2bdd1SGireesh Nagabhushana enum fw_sched_params_mode { 679156b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_MODE_CLASS = 0, 679256b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_MODE_FLOW = 1, 679356b2bdd1SGireesh Nagabhushana }; 679456b2bdd1SGireesh Nagabhushana 679556b2bdd1SGireesh Nagabhushana enum fw_sched_params_unit { 679656b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_UNIT_BITRATE = 0, 679756b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 679856b2bdd1SGireesh Nagabhushana }; 679956b2bdd1SGireesh Nagabhushana 680056b2bdd1SGireesh Nagabhushana enum fw_sched_params_rate { 680156b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_RATE_REL = 0, 680256b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_RATE_ABS = 1, 680356b2bdd1SGireesh Nagabhushana }; 680456b2bdd1SGireesh Nagabhushana 680556b2bdd1SGireesh Nagabhushana struct fw_sched_cmd { 680656b2bdd1SGireesh Nagabhushana __be32 op_to_write; 680756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 680856b2bdd1SGireesh Nagabhushana union fw_sched { 680956b2bdd1SGireesh Nagabhushana struct fw_sched_config { 681056b2bdd1SGireesh Nagabhushana __u8 sc; 681156b2bdd1SGireesh Nagabhushana __u8 type; 681256b2bdd1SGireesh Nagabhushana __u8 minmaxen; 681356b2bdd1SGireesh Nagabhushana __u8 r3[5]; 6814*de483253SVishal Kulkarni __u8 nclasses[4]; 6815*de483253SVishal Kulkarni __be32 r4; 681656b2bdd1SGireesh Nagabhushana } config; 681756b2bdd1SGireesh Nagabhushana struct fw_sched_params { 681856b2bdd1SGireesh Nagabhushana __u8 sc; 681956b2bdd1SGireesh Nagabhushana __u8 type; 682056b2bdd1SGireesh Nagabhushana __u8 level; 682156b2bdd1SGireesh Nagabhushana __u8 mode; 682256b2bdd1SGireesh Nagabhushana __u8 unit; 682356b2bdd1SGireesh Nagabhushana __u8 rate; 682456b2bdd1SGireesh Nagabhushana __u8 ch; 682556b2bdd1SGireesh Nagabhushana __u8 cl; 682656b2bdd1SGireesh Nagabhushana __be32 min; 682756b2bdd1SGireesh Nagabhushana __be32 max; 682856b2bdd1SGireesh Nagabhushana __be16 weight; 682956b2bdd1SGireesh Nagabhushana __be16 pktsize; 6830*de483253SVishal Kulkarni __be16 burstsize; 6831*de483253SVishal Kulkarni __be16 r4; 683256b2bdd1SGireesh Nagabhushana } params; 683356b2bdd1SGireesh Nagabhushana } u; 683456b2bdd1SGireesh Nagabhushana }; 683556b2bdd1SGireesh Nagabhushana 683656b2bdd1SGireesh Nagabhushana /* 683756b2bdd1SGireesh Nagabhushana * length of the formatting string 683856b2bdd1SGireesh Nagabhushana */ 683956b2bdd1SGireesh Nagabhushana #define FW_DEVLOG_FMT_LEN 192 684056b2bdd1SGireesh Nagabhushana 684156b2bdd1SGireesh Nagabhushana /* 684256b2bdd1SGireesh Nagabhushana * maximum number of the formatting string parameters 684356b2bdd1SGireesh Nagabhushana */ 684456b2bdd1SGireesh Nagabhushana #define FW_DEVLOG_FMT_PARAMS_NUM 8 684556b2bdd1SGireesh Nagabhushana 684656b2bdd1SGireesh Nagabhushana /* 684756b2bdd1SGireesh Nagabhushana * priority levels 684856b2bdd1SGireesh Nagabhushana */ 684956b2bdd1SGireesh Nagabhushana enum fw_devlog_level { 685056b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_EMERG = 0x0, 685156b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_CRIT = 0x1, 685256b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_ERR = 0x2, 685356b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_NOTICE = 0x3, 685456b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_INFO = 0x4, 685556b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_DEBUG = 0x5, 685656b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_MAX = 0x5, 685756b2bdd1SGireesh Nagabhushana }; 685856b2bdd1SGireesh Nagabhushana 685956b2bdd1SGireesh Nagabhushana /* 686056b2bdd1SGireesh Nagabhushana * facilities that may send a log message 686156b2bdd1SGireesh Nagabhushana */ 686256b2bdd1SGireesh Nagabhushana enum fw_devlog_facility { 686356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_CORE = 0x00, 6864*de483253SVishal Kulkarni FW_DEVLOG_FACILITY_CF = 0x01, 686556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_SCHED = 0x02, 686656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_TIMER = 0x04, 686756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_RES = 0x06, 686856b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_HW = 0x08, 686956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FLR = 0x10, 687056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_DMAQ = 0x12, 687156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_PHY = 0x14, 687256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_MAC = 0x16, 687356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_PORT = 0x18, 687456b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_VI = 0x1A, 687556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FILTER = 0x1C, 687656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ACL = 0x1E, 687756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_TM = 0x20, 687856b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_QFC = 0x22, 687956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_DCB = 0x24, 688056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ETH = 0x26, 688156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_OFLD = 0x28, 688256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_RI = 0x2A, 688356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ISCSI = 0x2C, 688456b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FCOE = 0x2E, 688556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FOISCSI = 0x30, 688656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FOFCOE = 0x32, 688756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_MAX = 0x32, 688856b2bdd1SGireesh Nagabhushana }; 688956b2bdd1SGireesh Nagabhushana 689056b2bdd1SGireesh Nagabhushana /* 689156b2bdd1SGireesh Nagabhushana * log message format 689256b2bdd1SGireesh Nagabhushana */ 689356b2bdd1SGireesh Nagabhushana struct fw_devlog_e { 689456b2bdd1SGireesh Nagabhushana __be64 timestamp; 689556b2bdd1SGireesh Nagabhushana __be32 seqno; 689656b2bdd1SGireesh Nagabhushana __be16 reserved1; 689756b2bdd1SGireesh Nagabhushana __u8 level; 689856b2bdd1SGireesh Nagabhushana __u8 facility; 689956b2bdd1SGireesh Nagabhushana __u8 fmt[FW_DEVLOG_FMT_LEN]; 690056b2bdd1SGireesh Nagabhushana __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 690156b2bdd1SGireesh Nagabhushana __be32 reserved3[4]; 690256b2bdd1SGireesh Nagabhushana }; 690356b2bdd1SGireesh Nagabhushana 690456b2bdd1SGireesh Nagabhushana struct fw_devlog_cmd { 690556b2bdd1SGireesh Nagabhushana __be32 op_to_write; 690656b2bdd1SGireesh Nagabhushana __be32 retval_len16; 690756b2bdd1SGireesh Nagabhushana __u8 level; 690856b2bdd1SGireesh Nagabhushana __u8 r2[7]; 690956b2bdd1SGireesh Nagabhushana __be32 memtype_devlog_memaddr16_devlog; 691056b2bdd1SGireesh Nagabhushana __be32 memsize_devlog; 691156b2bdd1SGireesh Nagabhushana __be32 r3[2]; 691256b2bdd1SGireesh Nagabhushana }; 691356b2bdd1SGireesh Nagabhushana 691456b2bdd1SGireesh Nagabhushana #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 691556b2bdd1SGireesh Nagabhushana #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 691656b2bdd1SGireesh Nagabhushana #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 691756b2bdd1SGireesh Nagabhushana ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 691856b2bdd1SGireesh Nagabhushana #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 691956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & \ 692056b2bdd1SGireesh Nagabhushana M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 692156b2bdd1SGireesh Nagabhushana 692256b2bdd1SGireesh Nagabhushana #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 692356b2bdd1SGireesh Nagabhushana #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 692456b2bdd1SGireesh Nagabhushana #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 692556b2bdd1SGireesh Nagabhushana ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 692656b2bdd1SGireesh Nagabhushana #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 692756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 692856b2bdd1SGireesh Nagabhushana M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 692956b2bdd1SGireesh Nagabhushana 693056b2bdd1SGireesh Nagabhushana enum fw_watchdog_actions { 6931*de483253SVishal Kulkarni FW_WATCHDOG_ACTION_SHUTDOWN = 0, 6932*de483253SVishal Kulkarni FW_WATCHDOG_ACTION_FLR = 1, 6933*de483253SVishal Kulkarni FW_WATCHDOG_ACTION_BYPASS = 2, 6934*de483253SVishal Kulkarni FW_WATCHDOG_ACTION_TMPCHK = 3, 6935*de483253SVishal Kulkarni 6936*de483253SVishal Kulkarni FW_WATCHDOG_ACTION_MAX = 4, 693756b2bdd1SGireesh Nagabhushana }; 693856b2bdd1SGireesh Nagabhushana 693956b2bdd1SGireesh Nagabhushana #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 694056b2bdd1SGireesh Nagabhushana 694156b2bdd1SGireesh Nagabhushana struct fw_watchdog_cmd { 6942*de483253SVishal Kulkarni __be32 op_to_vfn; 694356b2bdd1SGireesh Nagabhushana __be32 retval_len16; 694456b2bdd1SGireesh Nagabhushana __be32 timeout; 6945*de483253SVishal Kulkarni __be32 action; 694656b2bdd1SGireesh Nagabhushana }; 694756b2bdd1SGireesh Nagabhushana 6948*de483253SVishal Kulkarni #define S_FW_WATCHDOG_CMD_PFN 8 6949*de483253SVishal Kulkarni #define M_FW_WATCHDOG_CMD_PFN 0x7 6950*de483253SVishal Kulkarni #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 6951*de483253SVishal Kulkarni #define G_FW_WATCHDOG_CMD_PFN(x) \ 6952*de483253SVishal Kulkarni (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 6953*de483253SVishal Kulkarni 6954*de483253SVishal Kulkarni #define S_FW_WATCHDOG_CMD_VFN 0 6955*de483253SVishal Kulkarni #define M_FW_WATCHDOG_CMD_VFN 0xff 6956*de483253SVishal Kulkarni #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 6957*de483253SVishal Kulkarni #define G_FW_WATCHDOG_CMD_VFN(x) \ 6958*de483253SVishal Kulkarni (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 6959*de483253SVishal Kulkarni 696056b2bdd1SGireesh Nagabhushana struct fw_clip_cmd { 696156b2bdd1SGireesh Nagabhushana __be32 op_to_write; 696256b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 696356b2bdd1SGireesh Nagabhushana __be64 ip_hi; 696456b2bdd1SGireesh Nagabhushana __be64 ip_lo; 696556b2bdd1SGireesh Nagabhushana __be32 r4[2]; 696656b2bdd1SGireesh Nagabhushana }; 696756b2bdd1SGireesh Nagabhushana 696856b2bdd1SGireesh Nagabhushana #define S_FW_CLIP_CMD_ALLOC 31 696956b2bdd1SGireesh Nagabhushana #define M_FW_CLIP_CMD_ALLOC 0x1 697056b2bdd1SGireesh Nagabhushana #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 697156b2bdd1SGireesh Nagabhushana #define G_FW_CLIP_CMD_ALLOC(x) \ 697256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 697356b2bdd1SGireesh Nagabhushana #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 697456b2bdd1SGireesh Nagabhushana 697556b2bdd1SGireesh Nagabhushana #define S_FW_CLIP_CMD_FREE 30 697656b2bdd1SGireesh Nagabhushana #define M_FW_CLIP_CMD_FREE 0x1 697756b2bdd1SGireesh Nagabhushana #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 697856b2bdd1SGireesh Nagabhushana #define G_FW_CLIP_CMD_FREE(x) \ 697956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 698056b2bdd1SGireesh Nagabhushana #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 698156b2bdd1SGireesh Nagabhushana 698256b2bdd1SGireesh Nagabhushana /* 698356b2bdd1SGireesh Nagabhushana * ************************************ 698456b2bdd1SGireesh Nagabhushana * F O i S C S I C O M M A N D s 698556b2bdd1SGireesh Nagabhushana * ************************************ 698656b2bdd1SGireesh Nagabhushana */ 698756b2bdd1SGireesh Nagabhushana 698856b2bdd1SGireesh Nagabhushana #define FW_CHNET_IFACE_ADDR_MAX 3 698956b2bdd1SGireesh Nagabhushana 699056b2bdd1SGireesh Nagabhushana enum fw_chnet_iface_cmd_subop { 699156b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 699256b2bdd1SGireesh Nagabhushana 699356b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 699456b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 699556b2bdd1SGireesh Nagabhushana 699656b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 699756b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 699856b2bdd1SGireesh Nagabhushana 699956b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MAX, 700056b2bdd1SGireesh Nagabhushana }; 700156b2bdd1SGireesh Nagabhushana 700256b2bdd1SGireesh Nagabhushana struct fw_chnet_iface_cmd { 700356b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 700456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 700556b2bdd1SGireesh Nagabhushana __u8 subop; 700656b2bdd1SGireesh Nagabhushana __u8 r2[3]; 700756b2bdd1SGireesh Nagabhushana __be32 ifid_ifstate; 700856b2bdd1SGireesh Nagabhushana __be16 mtu; 700956b2bdd1SGireesh Nagabhushana __be16 vlanid; 701056b2bdd1SGireesh Nagabhushana __be32 r3; 701156b2bdd1SGireesh Nagabhushana __be16 r4; 701256b2bdd1SGireesh Nagabhushana __u8 mac[6]; 701356b2bdd1SGireesh Nagabhushana }; 701456b2bdd1SGireesh Nagabhushana 701556b2bdd1SGireesh Nagabhushana #define S_FW_CHNET_IFACE_CMD_PORTID 0 701656b2bdd1SGireesh Nagabhushana #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 701756b2bdd1SGireesh Nagabhushana #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 701856b2bdd1SGireesh Nagabhushana #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 701956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 702056b2bdd1SGireesh Nagabhushana 702156b2bdd1SGireesh Nagabhushana #define S_FW_CHNET_IFACE_CMD_IFID 8 702256b2bdd1SGireesh Nagabhushana #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 702356b2bdd1SGireesh Nagabhushana #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 702456b2bdd1SGireesh Nagabhushana #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 702556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 702656b2bdd1SGireesh Nagabhushana 702756b2bdd1SGireesh Nagabhushana #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 702856b2bdd1SGireesh Nagabhushana #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 702956b2bdd1SGireesh Nagabhushana #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 703056b2bdd1SGireesh Nagabhushana #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 703156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 703256b2bdd1SGireesh Nagabhushana 703356b2bdd1SGireesh Nagabhushana /* 703456b2bdd1SGireesh Nagabhushana * ********************************** 703556b2bdd1SGireesh Nagabhushana * F O F C O E C O M M A N D s 703656b2bdd1SGireesh Nagabhushana * ********************************** 703756b2bdd1SGireesh Nagabhushana */ 703856b2bdd1SGireesh Nagabhushana 703956b2bdd1SGireesh Nagabhushana struct fw_fcoe_res_info_cmd { 704056b2bdd1SGireesh Nagabhushana __be32 op_to_read; 704156b2bdd1SGireesh Nagabhushana __be32 retval_len16; 704256b2bdd1SGireesh Nagabhushana __be16 e_d_tov; 704356b2bdd1SGireesh Nagabhushana __be16 r_a_tov_seq; 704456b2bdd1SGireesh Nagabhushana __be16 r_a_tov_els; 704556b2bdd1SGireesh Nagabhushana __be16 r_r_tov; 704656b2bdd1SGireesh Nagabhushana __be32 max_xchgs; 704756b2bdd1SGireesh Nagabhushana __be32 max_ssns; 704856b2bdd1SGireesh Nagabhushana __be32 used_xchgs; 704956b2bdd1SGireesh Nagabhushana __be32 used_ssns; 705056b2bdd1SGireesh Nagabhushana __be32 max_fcfs; 705156b2bdd1SGireesh Nagabhushana __be32 max_vnps; 705256b2bdd1SGireesh Nagabhushana __be32 used_fcfs; 705356b2bdd1SGireesh Nagabhushana __be32 used_vnps; 705456b2bdd1SGireesh Nagabhushana }; 705556b2bdd1SGireesh Nagabhushana 705656b2bdd1SGireesh Nagabhushana struct fw_fcoe_link_cmd { 705756b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 705856b2bdd1SGireesh Nagabhushana __be32 retval_len16; 705956b2bdd1SGireesh Nagabhushana __be32 sub_opcode_fcfi; 706056b2bdd1SGireesh Nagabhushana __u8 r3; 706156b2bdd1SGireesh Nagabhushana __u8 lstatus; 706256b2bdd1SGireesh Nagabhushana __be16 flags; 706356b2bdd1SGireesh Nagabhushana __u8 r4; 706456b2bdd1SGireesh Nagabhushana __u8 set_vlan; 706556b2bdd1SGireesh Nagabhushana __be16 vlan_id; 706656b2bdd1SGireesh Nagabhushana __be32 vnpi_pkd; 706756b2bdd1SGireesh Nagabhushana __be16 r6; 706856b2bdd1SGireesh Nagabhushana __u8 phy_mac[6]; 706956b2bdd1SGireesh Nagabhushana __u8 vnport_wwnn[8]; 707056b2bdd1SGireesh Nagabhushana __u8 vnport_wwpn[8]; 707156b2bdd1SGireesh Nagabhushana }; 707256b2bdd1SGireesh Nagabhushana 707356b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_LINK_CMD_PORTID 0 707456b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_LINK_CMD_PORTID 0xf 707556b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 707656b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 707756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 707856b2bdd1SGireesh Nagabhushana 707956b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 708056b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 708156b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 708256b2bdd1SGireesh Nagabhushana ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 708356b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 708456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 708556b2bdd1SGireesh Nagabhushana 708656b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_LINK_CMD_FCFI 0 708756b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 708856b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 708956b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 709056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 709156b2bdd1SGireesh Nagabhushana 709256b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_LINK_CMD_VNPI 0 709356b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 709456b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 709556b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 709656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 709756b2bdd1SGireesh Nagabhushana 709856b2bdd1SGireesh Nagabhushana struct fw_fcoe_vnp_cmd { 709956b2bdd1SGireesh Nagabhushana __be32 op_to_fcfi; 710056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 710156b2bdd1SGireesh Nagabhushana __be32 gen_wwn_to_vnpi; 710256b2bdd1SGireesh Nagabhushana __be32 vf_id; 710356b2bdd1SGireesh Nagabhushana __be16 iqid; 710456b2bdd1SGireesh Nagabhushana __u8 vnport_mac[6]; 710556b2bdd1SGireesh Nagabhushana __u8 vnport_wwnn[8]; 710656b2bdd1SGireesh Nagabhushana __u8 vnport_wwpn[8]; 710756b2bdd1SGireesh Nagabhushana __u8 cmn_srv_parms[16]; 710856b2bdd1SGireesh Nagabhushana __u8 clsp_word_0_1[8]; 710956b2bdd1SGireesh Nagabhushana }; 711056b2bdd1SGireesh Nagabhushana 711156b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_FCFI 0 711256b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 711356b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 711456b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 711556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 711656b2bdd1SGireesh Nagabhushana 711756b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_ALLOC 31 711856b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 711956b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 712056b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 712156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 712256b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 712356b2bdd1SGireesh Nagabhushana 712456b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_FREE 30 712556b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_FREE 0x1 712656b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 712756b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_FREE(x) \ 712856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 712956b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 713056b2bdd1SGireesh Nagabhushana 713156b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_MODIFY 29 713256b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 713356b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 713456b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 713556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 713656b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 713756b2bdd1SGireesh Nagabhushana 713856b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 713956b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 714056b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 714156b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 714256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 714356b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 714456b2bdd1SGireesh Nagabhushana 714556b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_PERSIST 21 714656b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 714756b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 714856b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 714956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 715056b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 715156b2bdd1SGireesh Nagabhushana 715256b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_VFID_EN 20 715356b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 715456b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 715556b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 715656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 715756b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 715856b2bdd1SGireesh Nagabhushana 715956b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_VNP_CMD_VNPI 0 716056b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 716156b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 716256b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 716356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 716456b2bdd1SGireesh Nagabhushana 716556b2bdd1SGireesh Nagabhushana struct fw_fcoe_sparams_cmd { 716656b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 716756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 716856b2bdd1SGireesh Nagabhushana __u8 r3[7]; 716956b2bdd1SGireesh Nagabhushana __u8 cos; 717056b2bdd1SGireesh Nagabhushana __u8 lport_wwnn[8]; 717156b2bdd1SGireesh Nagabhushana __u8 lport_wwpn[8]; 717256b2bdd1SGireesh Nagabhushana __u8 cmn_srv_parms[16]; 717356b2bdd1SGireesh Nagabhushana __u8 cls_srv_parms[16]; 717456b2bdd1SGireesh Nagabhushana }; 717556b2bdd1SGireesh Nagabhushana 717656b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 717756b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 717856b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 717956b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 718056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 718156b2bdd1SGireesh Nagabhushana 718256b2bdd1SGireesh Nagabhushana struct fw_fcoe_stats_cmd { 718356b2bdd1SGireesh Nagabhushana __be32 op_to_flowid; 718456b2bdd1SGireesh Nagabhushana __be32 free_to_len16; 718556b2bdd1SGireesh Nagabhushana union fw_fcoe_stats { 718656b2bdd1SGireesh Nagabhushana struct fw_fcoe_stats_ctl { 718756b2bdd1SGireesh Nagabhushana __u8 nstats_port; 718856b2bdd1SGireesh Nagabhushana __u8 port_valid_ix; 718956b2bdd1SGireesh Nagabhushana __be16 r6; 719056b2bdd1SGireesh Nagabhushana __be32 r7; 719156b2bdd1SGireesh Nagabhushana __be64 stat0; 719256b2bdd1SGireesh Nagabhushana __be64 stat1; 719356b2bdd1SGireesh Nagabhushana __be64 stat2; 719456b2bdd1SGireesh Nagabhushana __be64 stat3; 719556b2bdd1SGireesh Nagabhushana __be64 stat4; 719656b2bdd1SGireesh Nagabhushana __be64 stat5; 719756b2bdd1SGireesh Nagabhushana } ctl; 719856b2bdd1SGireesh Nagabhushana struct fw_fcoe_port_stats { 719956b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 720056b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 720156b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 720256b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 720356b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 720456b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 720556b2bdd1SGireesh Nagabhushana __be64 tx_drop_frames; 720656b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 720756b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 720856b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 720956b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 721056b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 721156b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 721256b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 721356b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 721456b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 721556b2bdd1SGireesh Nagabhushana } port_stats; 721656b2bdd1SGireesh Nagabhushana struct fw_fcoe_fcf_stats { 721756b2bdd1SGireesh Nagabhushana __be32 fip_tx_bytes; 721856b2bdd1SGireesh Nagabhushana __be32 fip_tx_fr; 721956b2bdd1SGireesh Nagabhushana __be64 fcf_ka; 722056b2bdd1SGireesh Nagabhushana __be64 mcast_adv_rcvd; 722156b2bdd1SGireesh Nagabhushana __be16 ucast_adv_rcvd; 722256b2bdd1SGireesh Nagabhushana __be16 sol_sent; 722356b2bdd1SGireesh Nagabhushana __be16 vlan_req; 722456b2bdd1SGireesh Nagabhushana __be16 vlan_rpl; 722556b2bdd1SGireesh Nagabhushana __be16 clr_vlink; 722656b2bdd1SGireesh Nagabhushana __be16 link_down; 722756b2bdd1SGireesh Nagabhushana __be16 link_up; 722856b2bdd1SGireesh Nagabhushana __be16 logo; 722956b2bdd1SGireesh Nagabhushana __be16 flogi_req; 723056b2bdd1SGireesh Nagabhushana __be16 flogi_rpl; 723156b2bdd1SGireesh Nagabhushana __be16 fdisc_req; 723256b2bdd1SGireesh Nagabhushana __be16 fdisc_rpl; 723356b2bdd1SGireesh Nagabhushana __be16 fka_prd_chg; 723456b2bdd1SGireesh Nagabhushana __be16 fc_map_chg; 723556b2bdd1SGireesh Nagabhushana __be16 vfid_chg; 723656b2bdd1SGireesh Nagabhushana __u8 no_fka_req; 723756b2bdd1SGireesh Nagabhushana __u8 no_vnp; 723856b2bdd1SGireesh Nagabhushana } fcf_stats; 723956b2bdd1SGireesh Nagabhushana struct fw_fcoe_pcb_stats { 724056b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 724156b2bdd1SGireesh Nagabhushana __be64 tx_frames; 724256b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 724356b2bdd1SGireesh Nagabhushana __be64 rx_frames; 724456b2bdd1SGireesh Nagabhushana __be32 vnp_ka; 724556b2bdd1SGireesh Nagabhushana __be32 unsol_els_rcvd; 724656b2bdd1SGireesh Nagabhushana __be64 unsol_cmd_rcvd; 724756b2bdd1SGireesh Nagabhushana __be16 implicit_logo; 724856b2bdd1SGireesh Nagabhushana __be16 flogi_inv_sparm; 724956b2bdd1SGireesh Nagabhushana __be16 fdisc_inv_sparm; 725056b2bdd1SGireesh Nagabhushana __be16 flogi_rjt; 725156b2bdd1SGireesh Nagabhushana __be16 fdisc_rjt; 725256b2bdd1SGireesh Nagabhushana __be16 no_ssn; 725356b2bdd1SGireesh Nagabhushana __be16 mac_flt_fail; 725456b2bdd1SGireesh Nagabhushana __be16 inv_fr_rcvd; 725556b2bdd1SGireesh Nagabhushana } pcb_stats; 725656b2bdd1SGireesh Nagabhushana struct fw_fcoe_scb_stats { 725756b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 725856b2bdd1SGireesh Nagabhushana __be64 tx_frames; 725956b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 726056b2bdd1SGireesh Nagabhushana __be64 rx_frames; 726156b2bdd1SGireesh Nagabhushana __be32 host_abrt_req; 726256b2bdd1SGireesh Nagabhushana __be32 adap_auto_abrt; 726356b2bdd1SGireesh Nagabhushana __be32 adap_abrt_rsp; 726456b2bdd1SGireesh Nagabhushana __be32 host_ios_req; 726556b2bdd1SGireesh Nagabhushana __be16 ssn_offl_ios; 726656b2bdd1SGireesh Nagabhushana __be16 ssn_not_rdy_ios; 726756b2bdd1SGireesh Nagabhushana __u8 rx_data_ddp_err; 726856b2bdd1SGireesh Nagabhushana __u8 ddp_flt_set_err; 726956b2bdd1SGireesh Nagabhushana __be16 rx_data_fr_err; 727056b2bdd1SGireesh Nagabhushana __u8 bad_st_abrt_req; 727156b2bdd1SGireesh Nagabhushana __u8 no_io_abrt_req; 727256b2bdd1SGireesh Nagabhushana __u8 abort_tmo; 727356b2bdd1SGireesh Nagabhushana __u8 abort_tmo_2; 727456b2bdd1SGireesh Nagabhushana __be32 abort_req; 727556b2bdd1SGireesh Nagabhushana __u8 no_ppod_res_tmo; 727656b2bdd1SGireesh Nagabhushana __u8 bp_tmo; 727756b2bdd1SGireesh Nagabhushana __u8 adap_auto_cls; 727856b2bdd1SGireesh Nagabhushana __u8 no_io_cls_req; 727956b2bdd1SGireesh Nagabhushana __be32 host_cls_req; 728056b2bdd1SGireesh Nagabhushana __be64 unsol_cmd_rcvd; 728156b2bdd1SGireesh Nagabhushana __be32 plogi_req_rcvd; 728256b2bdd1SGireesh Nagabhushana __be32 prli_req_rcvd; 728356b2bdd1SGireesh Nagabhushana __be16 logo_req_rcvd; 728456b2bdd1SGireesh Nagabhushana __be16 prlo_req_rcvd; 728556b2bdd1SGireesh Nagabhushana __be16 plogi_rjt_rcvd; 728656b2bdd1SGireesh Nagabhushana __be16 prli_rjt_rcvd; 728756b2bdd1SGireesh Nagabhushana __be32 adisc_req_rcvd; 728856b2bdd1SGireesh Nagabhushana __be32 rscn_rcvd; 728956b2bdd1SGireesh Nagabhushana __be32 rrq_req_rcvd; 729056b2bdd1SGireesh Nagabhushana __be32 unsol_els_rcvd; 729156b2bdd1SGireesh Nagabhushana __u8 adisc_rjt_rcvd; 729256b2bdd1SGireesh Nagabhushana __u8 scr_rjt; 729356b2bdd1SGireesh Nagabhushana __u8 ct_rjt; 729456b2bdd1SGireesh Nagabhushana __u8 inval_bls_rcvd; 729556b2bdd1SGireesh Nagabhushana __be32 ba_rjt_rcvd; 729656b2bdd1SGireesh Nagabhushana } scb_stats; 729756b2bdd1SGireesh Nagabhushana } u; 729856b2bdd1SGireesh Nagabhushana }; 729956b2bdd1SGireesh Nagabhushana 730056b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_STATS_CMD_FLOWID 0 730156b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 730256b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 730356b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 730456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 730556b2bdd1SGireesh Nagabhushana 730656b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_STATS_CMD_FREE 30 730756b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_STATS_CMD_FREE 0x1 730856b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 730956b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_STATS_CMD_FREE(x) \ 731056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 731156b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 731256b2bdd1SGireesh Nagabhushana 731356b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_STATS_CMD_NSTATS 4 731456b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 731556b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 731656b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 731756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 731856b2bdd1SGireesh Nagabhushana 731956b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_STATS_CMD_PORT 0 732056b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_STATS_CMD_PORT 0x3 732156b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 732256b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_STATS_CMD_PORT(x) \ 732356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 732456b2bdd1SGireesh Nagabhushana 732556b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 732656b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 732756b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 732856b2bdd1SGireesh Nagabhushana ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 732956b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 733056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & \ 733156b2bdd1SGireesh Nagabhushana M_FW_FCOE_STATS_CMD_PORT_VALID) 733256b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 733356b2bdd1SGireesh Nagabhushana 733456b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_STATS_CMD_IX 0 733556b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_STATS_CMD_IX 0x3f 733656b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 733756b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_STATS_CMD_IX(x) \ 733856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 733956b2bdd1SGireesh Nagabhushana 734056b2bdd1SGireesh Nagabhushana struct fw_fcoe_fcf_cmd { 734156b2bdd1SGireesh Nagabhushana __be32 op_to_fcfi; 734256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 734356b2bdd1SGireesh Nagabhushana __be16 priority_pkd; 734456b2bdd1SGireesh Nagabhushana __u8 mac[6]; 734556b2bdd1SGireesh Nagabhushana __u8 name_id[8]; 734656b2bdd1SGireesh Nagabhushana __u8 fabric[8]; 734756b2bdd1SGireesh Nagabhushana __be16 vf_id; 734856b2bdd1SGireesh Nagabhushana __be16 max_fcoe_size; 734956b2bdd1SGireesh Nagabhushana __u8 vlan_id; 735056b2bdd1SGireesh Nagabhushana __u8 fc_map[3]; 735156b2bdd1SGireesh Nagabhushana __be32 fka_adv; 735256b2bdd1SGireesh Nagabhushana __be32 r6; 735356b2bdd1SGireesh Nagabhushana __u8 r7_hi; 735456b2bdd1SGireesh Nagabhushana __u8 fpma_to_portid; 735556b2bdd1SGireesh Nagabhushana __u8 spma_mac[6]; 735656b2bdd1SGireesh Nagabhushana __be64 r8; 735756b2bdd1SGireesh Nagabhushana }; 735856b2bdd1SGireesh Nagabhushana 735956b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_FCF_CMD_FCFI 0 736056b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 736156b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 736256b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 736356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 736456b2bdd1SGireesh Nagabhushana 736556b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_FCF_CMD_PRIORITY 0 736656b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 736756b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 736856b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 736956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 737056b2bdd1SGireesh Nagabhushana 737156b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_FCF_CMD_FPMA 6 737256b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_FCF_CMD_FPMA 0x1 737356b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 737456b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 737556b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 737656b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 737756b2bdd1SGireesh Nagabhushana 737856b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_FCF_CMD_SPMA 5 737956b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_FCF_CMD_SPMA 0x1 738056b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 738156b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 738256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 738356b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 738456b2bdd1SGireesh Nagabhushana 738556b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_FCF_CMD_LOGIN 4 738656b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 738756b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 738856b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 738956b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 739056b2bdd1SGireesh Nagabhushana #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 739156b2bdd1SGireesh Nagabhushana 739256b2bdd1SGireesh Nagabhushana #define S_FW_FCOE_FCF_CMD_PORTID 0 739356b2bdd1SGireesh Nagabhushana #define M_FW_FCOE_FCF_CMD_PORTID 0xf 739456b2bdd1SGireesh Nagabhushana #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 739556b2bdd1SGireesh Nagabhushana #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 739656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 739756b2bdd1SGireesh Nagabhushana 739856b2bdd1SGireesh Nagabhushana /* 739956b2bdd1SGireesh Nagabhushana * **************************************************** 740056b2bdd1SGireesh Nagabhushana * E R R O R a n d D E B U G C O M M A N D s 740156b2bdd1SGireesh Nagabhushana * **************************************************** 740256b2bdd1SGireesh Nagabhushana */ 740356b2bdd1SGireesh Nagabhushana 740456b2bdd1SGireesh Nagabhushana enum fw_error_type { 7405*de483253SVishal Kulkarni FW_ERROR_TYPE_EXCEPTION = 0x0, 7406*de483253SVishal Kulkarni FW_ERROR_TYPE_HWMODULE = 0x1, 7407*de483253SVishal Kulkarni FW_ERROR_TYPE_WR = 0x2, 7408*de483253SVishal Kulkarni FW_ERROR_TYPE_ACL = 0x3, 740956b2bdd1SGireesh Nagabhushana }; 741056b2bdd1SGireesh Nagabhushana 741156b2bdd1SGireesh Nagabhushana struct fw_error_cmd { 741256b2bdd1SGireesh Nagabhushana __be32 op_to_type; 741356b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 741456b2bdd1SGireesh Nagabhushana union fw_error { 741556b2bdd1SGireesh Nagabhushana struct fw_error_exception { 741656b2bdd1SGireesh Nagabhushana __be32 info[6]; 741756b2bdd1SGireesh Nagabhushana } exception; 741856b2bdd1SGireesh Nagabhushana struct fw_error_hwmodule { 741956b2bdd1SGireesh Nagabhushana __be32 regaddr; 742056b2bdd1SGireesh Nagabhushana __be32 regval; 742156b2bdd1SGireesh Nagabhushana } hwmodule; 742256b2bdd1SGireesh Nagabhushana struct fw_error_wr { 742356b2bdd1SGireesh Nagabhushana __be16 cidx; 742456b2bdd1SGireesh Nagabhushana __be16 pfn_vfn; 742556b2bdd1SGireesh Nagabhushana __be32 eqid; 742656b2bdd1SGireesh Nagabhushana __u8 wrhdr[16]; 742756b2bdd1SGireesh Nagabhushana } wr; 742856b2bdd1SGireesh Nagabhushana struct fw_error_acl { 742956b2bdd1SGireesh Nagabhushana __be16 cidx; 743056b2bdd1SGireesh Nagabhushana __be16 pfn_vfn; 743156b2bdd1SGireesh Nagabhushana __be32 eqid; 743256b2bdd1SGireesh Nagabhushana __be16 mv_pkd; 743356b2bdd1SGireesh Nagabhushana __u8 val[6]; 743456b2bdd1SGireesh Nagabhushana __be64 r4; 743556b2bdd1SGireesh Nagabhushana } acl; 743656b2bdd1SGireesh Nagabhushana } u; 743756b2bdd1SGireesh Nagabhushana }; 743856b2bdd1SGireesh Nagabhushana 743956b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_FATAL 4 744056b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_FATAL 0x1 744156b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 744256b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_FATAL(x) \ 744356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 744456b2bdd1SGireesh Nagabhushana #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 744556b2bdd1SGireesh Nagabhushana 744656b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_TYPE 0 744756b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_TYPE 0xf 744856b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 744956b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_TYPE(x) \ 745056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 745156b2bdd1SGireesh Nagabhushana 745256b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_PFN 8 745356b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_PFN 0x7 745456b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 745556b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_PFN(x) \ 745656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 745756b2bdd1SGireesh Nagabhushana 745856b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_VFN 0 745956b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_VFN 0xff 746056b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 746156b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_VFN(x) \ 746256b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 746356b2bdd1SGireesh Nagabhushana 746456b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_PFN 8 746556b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_PFN 0x7 746656b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 746756b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_PFN(x) \ 746856b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 746956b2bdd1SGireesh Nagabhushana 747056b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_VFN 0 747156b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_VFN 0xff 747256b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 747356b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_VFN(x) \ 747456b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 747556b2bdd1SGireesh Nagabhushana 747656b2bdd1SGireesh Nagabhushana #define S_FW_ERROR_CMD_MV 15 747756b2bdd1SGireesh Nagabhushana #define M_FW_ERROR_CMD_MV 0x1 747856b2bdd1SGireesh Nagabhushana #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 747956b2bdd1SGireesh Nagabhushana #define G_FW_ERROR_CMD_MV(x) \ 748056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 748156b2bdd1SGireesh Nagabhushana #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 748256b2bdd1SGireesh Nagabhushana 748356b2bdd1SGireesh Nagabhushana struct fw_debug_cmd { 748456b2bdd1SGireesh Nagabhushana __be32 op_type; 748556b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 748656b2bdd1SGireesh Nagabhushana union fw_debug { 748756b2bdd1SGireesh Nagabhushana struct fw_debug_assert { 748856b2bdd1SGireesh Nagabhushana __be32 fcid; 748956b2bdd1SGireesh Nagabhushana __be32 line; 749056b2bdd1SGireesh Nagabhushana __be32 x; 749156b2bdd1SGireesh Nagabhushana __be32 y; 749256b2bdd1SGireesh Nagabhushana __u8 filename_0_7[8]; 749356b2bdd1SGireesh Nagabhushana __u8 filename_8_15[8]; 749456b2bdd1SGireesh Nagabhushana __be64 r3; 749556b2bdd1SGireesh Nagabhushana } assert; 749656b2bdd1SGireesh Nagabhushana struct fw_debug_prt { 749756b2bdd1SGireesh Nagabhushana __be16 dprtstridx; 749856b2bdd1SGireesh Nagabhushana __be16 r3[3]; 749956b2bdd1SGireesh Nagabhushana __be32 dprtstrparam0; 750056b2bdd1SGireesh Nagabhushana __be32 dprtstrparam1; 750156b2bdd1SGireesh Nagabhushana __be32 dprtstrparam2; 750256b2bdd1SGireesh Nagabhushana __be32 dprtstrparam3; 750356b2bdd1SGireesh Nagabhushana } prt; 750456b2bdd1SGireesh Nagabhushana } u; 750556b2bdd1SGireesh Nagabhushana }; 750656b2bdd1SGireesh Nagabhushana 750756b2bdd1SGireesh Nagabhushana #define S_FW_DEBUG_CMD_TYPE 0 750856b2bdd1SGireesh Nagabhushana #define M_FW_DEBUG_CMD_TYPE 0xff 750956b2bdd1SGireesh Nagabhushana #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 751056b2bdd1SGireesh Nagabhushana #define G_FW_DEBUG_CMD_TYPE(x) \ 751156b2bdd1SGireesh Nagabhushana (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 751256b2bdd1SGireesh Nagabhushana 751356b2bdd1SGireesh Nagabhushana /* 751456b2bdd1SGireesh Nagabhushana * ************************************ 751556b2bdd1SGireesh Nagabhushana * P C I E F W R E G I S T E R 751656b2bdd1SGireesh Nagabhushana * ************************************ 751756b2bdd1SGireesh Nagabhushana */ 751856b2bdd1SGireesh Nagabhushana 7519*de483253SVishal Kulkarni enum pcie_fw_eval { 7520*de483253SVishal Kulkarni PCIE_FW_EVAL_CRASH = 0, 7521*de483253SVishal Kulkarni PCIE_FW_EVAL_PREP = 1, 7522*de483253SVishal Kulkarni PCIE_FW_EVAL_CONF = 2, 7523*de483253SVishal Kulkarni PCIE_FW_EVAL_INIT = 3, 7524*de483253SVishal Kulkarni PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7525*de483253SVishal Kulkarni PCIE_FW_EVAL_OVERHEAT = 5, 7526*de483253SVishal Kulkarni PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7527*de483253SVishal Kulkarni }; 7528*de483253SVishal Kulkarni 752956b2bdd1SGireesh Nagabhushana /* 753056b2bdd1SGireesh Nagabhushana * Register definitions for the PCIE_FW register which the firmware uses 7531*de483253SVishal Kulkarni * to retain status across RESETs. This register should be considered 753256b2bdd1SGireesh Nagabhushana * as a READ-ONLY register for Host Software and only to be used to 753356b2bdd1SGireesh Nagabhushana * track firmware initialization/error state, etc. 753456b2bdd1SGireesh Nagabhushana */ 753556b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_ERR 31 753656b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_ERR 0x1 753756b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 753856b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 753956b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 754056b2bdd1SGireesh Nagabhushana 754156b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_INIT 30 754256b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_INIT 0x1 754356b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 754456b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 754556b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 754656b2bdd1SGireesh Nagabhushana 754756b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_HALT 29 754856b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_HALT 0x1 754956b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 755056b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 755156b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 755256b2bdd1SGireesh Nagabhushana 7553*de483253SVishal Kulkarni #define S_PCIE_FW_EVAL 24 7554*de483253SVishal Kulkarni #define M_PCIE_FW_EVAL 0x7 7555*de483253SVishal Kulkarni #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7556*de483253SVishal Kulkarni #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7557*de483253SVishal Kulkarni 755856b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_STAGE 21 755956b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_STAGE 0x7 756056b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 756156b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 756256b2bdd1SGireesh Nagabhushana 756356b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_ASYNCNOT_VLD 20 756456b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_ASYNCNOT_VLD 0x1 756556b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 756656b2bdd1SGireesh Nagabhushana ((x) << S_PCIE_FW_ASYNCNOT_VLD) 756756b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 756856b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 756956b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 757056b2bdd1SGireesh Nagabhushana 757156b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_ASYNCNOTINT 19 757256b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_ASYNCNOTINT 0x1 757356b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_ASYNCNOTINT(x) \ 757456b2bdd1SGireesh Nagabhushana ((x) << S_PCIE_FW_ASYNCNOTINT) 757556b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_ASYNCNOTINT(x) \ 757656b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 757756b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 757856b2bdd1SGireesh Nagabhushana 757956b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_ASYNCNOT 16 758056b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_ASYNCNOT 0x7 758156b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 758256b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_ASYNCNOT(x) \ 758356b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 758456b2bdd1SGireesh Nagabhushana 758556b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_MASTER_VLD 15 758656b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_MASTER_VLD 0x1 758756b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 758856b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_MASTER_VLD(x) \ 758956b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 759056b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 759156b2bdd1SGireesh Nagabhushana 759256b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_MASTER 12 759356b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_MASTER 0x7 759456b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 759556b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 759656b2bdd1SGireesh Nagabhushana 759756b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_RESET_VLD 11 759856b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_RESET_VLD 0x1 759956b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 760056b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_RESET_VLD(x) \ 760156b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 760256b2bdd1SGireesh Nagabhushana #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 760356b2bdd1SGireesh Nagabhushana 760456b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_RESET 8 760556b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_RESET 0x7 760656b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 760756b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_RESET(x) \ 760856b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 760956b2bdd1SGireesh Nagabhushana 761056b2bdd1SGireesh Nagabhushana #define S_PCIE_FW_REGISTERED 0 761156b2bdd1SGireesh Nagabhushana #define M_PCIE_FW_REGISTERED 0xff 761256b2bdd1SGireesh Nagabhushana #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 761356b2bdd1SGireesh Nagabhushana #define G_PCIE_FW_REGISTERED(x) \ 761456b2bdd1SGireesh Nagabhushana (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 761556b2bdd1SGireesh Nagabhushana 761656b2bdd1SGireesh Nagabhushana /* 761756b2bdd1SGireesh Nagabhushana * ******************************************** 761856b2bdd1SGireesh Nagabhushana * B I N A R Y H E A D E R F O R M A T 761956b2bdd1SGireesh Nagabhushana * ******************************************** 762056b2bdd1SGireesh Nagabhushana */ 762156b2bdd1SGireesh Nagabhushana 762256b2bdd1SGireesh Nagabhushana /* 762356b2bdd1SGireesh Nagabhushana * firmware binary header format 762456b2bdd1SGireesh Nagabhushana */ 762556b2bdd1SGireesh Nagabhushana struct fw_hdr { 762656b2bdd1SGireesh Nagabhushana __u8 ver; 762756b2bdd1SGireesh Nagabhushana __u8 chip; /* terminator chip family */ 762856b2bdd1SGireesh Nagabhushana __be16 len512; /* bin length in units of 512-bytes */ 762956b2bdd1SGireesh Nagabhushana __be32 fw_ver; /* firmware version */ 763056b2bdd1SGireesh Nagabhushana __be32 tp_microcode_ver; /* tcp processor microcode version */ 763156b2bdd1SGireesh Nagabhushana __u8 intfver_nic; 763256b2bdd1SGireesh Nagabhushana __u8 intfver_vnic; 763356b2bdd1SGireesh Nagabhushana __u8 intfver_ofld; 763456b2bdd1SGireesh Nagabhushana __u8 intfver_ri; 763556b2bdd1SGireesh Nagabhushana __u8 intfver_iscsipdu; 763656b2bdd1SGireesh Nagabhushana __u8 intfver_iscsi; 7637*de483253SVishal Kulkarni __u8 intfver_fcoepdu; 763856b2bdd1SGireesh Nagabhushana __u8 intfver_fcoe; 7639*de483253SVishal Kulkarni __u32 reserved2; 764056b2bdd1SGireesh Nagabhushana __u32 reserved3; 7641*de483253SVishal Kulkarni __u32 magic; /* runtime or bootstrap fw */ 764256b2bdd1SGireesh Nagabhushana __be32 flags; 764356b2bdd1SGireesh Nagabhushana __be32 reserved6[23]; 764456b2bdd1SGireesh Nagabhushana }; 764556b2bdd1SGireesh Nagabhushana 764656b2bdd1SGireesh Nagabhushana enum fw_hdr_chip { 764756b2bdd1SGireesh Nagabhushana FW_HDR_CHIP_T4, 764856b2bdd1SGireesh Nagabhushana FW_HDR_CHIP_T5 764956b2bdd1SGireesh Nagabhushana }; 765056b2bdd1SGireesh Nagabhushana 765156b2bdd1SGireesh Nagabhushana #define S_FW_HDR_FW_VER_MAJOR 24 765256b2bdd1SGireesh Nagabhushana #define M_FW_HDR_FW_VER_MAJOR 0xff 765356b2bdd1SGireesh Nagabhushana #define V_FW_HDR_FW_VER_MAJOR(x) \ 765456b2bdd1SGireesh Nagabhushana ((x) << S_FW_HDR_FW_VER_MAJOR) 765556b2bdd1SGireesh Nagabhushana #define G_FW_HDR_FW_VER_MAJOR(x) \ 765656b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 765756b2bdd1SGireesh Nagabhushana 765856b2bdd1SGireesh Nagabhushana #define S_FW_HDR_FW_VER_MINOR 16 765956b2bdd1SGireesh Nagabhushana #define M_FW_HDR_FW_VER_MINOR 0xff 766056b2bdd1SGireesh Nagabhushana #define V_FW_HDR_FW_VER_MINOR(x) \ 766156b2bdd1SGireesh Nagabhushana ((x) << S_FW_HDR_FW_VER_MINOR) 766256b2bdd1SGireesh Nagabhushana #define G_FW_HDR_FW_VER_MINOR(x) \ 766356b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 766456b2bdd1SGireesh Nagabhushana 766556b2bdd1SGireesh Nagabhushana #define S_FW_HDR_FW_VER_MICRO 8 766656b2bdd1SGireesh Nagabhushana #define M_FW_HDR_FW_VER_MICRO 0xff 766756b2bdd1SGireesh Nagabhushana #define V_FW_HDR_FW_VER_MICRO(x) \ 766856b2bdd1SGireesh Nagabhushana ((x) << S_FW_HDR_FW_VER_MICRO) 766956b2bdd1SGireesh Nagabhushana #define G_FW_HDR_FW_VER_MICRO(x) \ 767056b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 767156b2bdd1SGireesh Nagabhushana 767256b2bdd1SGireesh Nagabhushana #define S_FW_HDR_FW_VER_BUILD 0 767356b2bdd1SGireesh Nagabhushana #define M_FW_HDR_FW_VER_BUILD 0xff 767456b2bdd1SGireesh Nagabhushana #define V_FW_HDR_FW_VER_BUILD(x) \ 767556b2bdd1SGireesh Nagabhushana ((x) << S_FW_HDR_FW_VER_BUILD) 767656b2bdd1SGireesh Nagabhushana #define G_FW_HDR_FW_VER_BUILD(x) \ 767756b2bdd1SGireesh Nagabhushana (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 767856b2bdd1SGireesh Nagabhushana 7679*de483253SVishal Kulkarni enum { 7680*de483253SVishal Kulkarni T4FW_VERSION_MAJOR = 0x01, 7681*de483253SVishal Kulkarni T4FW_VERSION_MINOR = 0x08, 7682*de483253SVishal Kulkarni T4FW_VERSION_MICRO = 0x18, 7683*de483253SVishal Kulkarni T4FW_VERSION_BUILD = 0x00, 7684*de483253SVishal Kulkarni 7685*de483253SVishal Kulkarni T5FW_VERSION_MAJOR = 0x01, 7686*de483253SVishal Kulkarni T5FW_VERSION_MINOR = 0x08, 7687*de483253SVishal Kulkarni T5FW_VERSION_MICRO = 0x1b, 7688*de483253SVishal Kulkarni T5FW_VERSION_BUILD = 0x00, 7689*de483253SVishal Kulkarni }; 7690*de483253SVishal Kulkarni 7691*de483253SVishal Kulkarni enum { 7692*de483253SVishal Kulkarni T4FW_HDR_INTFVER_NIC = 0x00, 7693*de483253SVishal Kulkarni T4FW_HDR_INTFVER_VNIC = 0x00, 7694*de483253SVishal Kulkarni T4FW_HDR_INTFVER_OFLD = 0x00, 7695*de483253SVishal Kulkarni T4FW_HDR_INTFVER_RI = 0x00, 7696*de483253SVishal Kulkarni T4FW_HDR_INTFVER_ISCSIPDU = 0x00, 7697*de483253SVishal Kulkarni T4FW_HDR_INTFVER_ISCSI = 0x00, 7698*de483253SVishal Kulkarni T4FW_HDR_INTFVER_FCOEPDU = 0x00, 7699*de483253SVishal Kulkarni T4FW_HDR_INTFVER_FCOE = 0x00, 7700*de483253SVishal Kulkarni 7701*de483253SVishal Kulkarni T5FW_HDR_INTFVER_NIC = 0x00, 7702*de483253SVishal Kulkarni T5FW_HDR_INTFVER_VNIC = 0x00, 7703*de483253SVishal Kulkarni T5FW_HDR_INTFVER_OFLD = 0x00, 7704*de483253SVishal Kulkarni T5FW_HDR_INTFVER_RI = 0x00, 7705*de483253SVishal Kulkarni T5FW_HDR_INTFVER_ISCSIPDU = 0x00, 7706*de483253SVishal Kulkarni T5FW_HDR_INTFVER_ISCSI = 0x00, 7707*de483253SVishal Kulkarni T5FW_HDR_INTFVER_FCOEPDU = 0x00, 7708*de483253SVishal Kulkarni T5FW_HDR_INTFVER_FCOE = 0x00, 770956b2bdd1SGireesh Nagabhushana }; 771056b2bdd1SGireesh Nagabhushana 7711*de483253SVishal Kulkarni enum { 7712*de483253SVishal Kulkarni FW_HDR_MAGIC_RUNTIME = 0x00000000, 7713*de483253SVishal Kulkarni FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 7714*de483253SVishal Kulkarni }; 7715*de483253SVishal Kulkarni 771656b2bdd1SGireesh Nagabhushana enum fw_hdr_flags { 771756b2bdd1SGireesh Nagabhushana FW_HDR_FLAGS_RESET_HALT = 0x00000001, 771856b2bdd1SGireesh Nagabhushana }; 771956b2bdd1SGireesh Nagabhushana 772056b2bdd1SGireesh Nagabhushana #endif /* _T4FW_INTERFACE_H_ */ 7721