156b2bdd1SGireesh Nagabhushana /* 256b2bdd1SGireesh Nagabhushana * Chelsio Terminator 4 (T4) Firmware interface header file. 356b2bdd1SGireesh Nagabhushana * 43dde7c95SVishal Kulkarni * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved. 556b2bdd1SGireesh Nagabhushana * 656b2bdd1SGireesh Nagabhushana * Written by felix marti (felix@chelsio.com) 756b2bdd1SGireesh Nagabhushana * 856b2bdd1SGireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT 956b2bdd1SGireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1056b2bdd1SGireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 1156b2bdd1SGireesh Nagabhushana * release for licensing terms and conditions. 1256b2bdd1SGireesh Nagabhushana */ 133dde7c95SVishal Kulkarni 1456b2bdd1SGireesh Nagabhushana #ifndef _T4FW_INTERFACE_H_ 153dde7c95SVishal Kulkarni #define _T4FW_INTERFACE_H_ 1656b2bdd1SGireesh Nagabhushana 173dde7c95SVishal Kulkarni /****************************************************************************** 183dde7c95SVishal Kulkarni * R E T U R N V A L U E S 193dde7c95SVishal Kulkarni ********************************/ 2056b2bdd1SGireesh Nagabhushana 2156b2bdd1SGireesh Nagabhushana enum fw_retval { 2256b2bdd1SGireesh Nagabhushana FW_SUCCESS = 0, /* completed sucessfully */ 2356b2bdd1SGireesh Nagabhushana FW_EPERM = 1, /* operation not permitted */ 2456b2bdd1SGireesh Nagabhushana FW_ENOENT = 2, /* no such file or directory */ 2556b2bdd1SGireesh Nagabhushana FW_EIO = 5, /* input/output error; hw bad */ 2656b2bdd1SGireesh Nagabhushana FW_ENOEXEC = 8, /* exec format error; inv microcode */ 2756b2bdd1SGireesh Nagabhushana FW_EAGAIN = 11, /* try again */ 2856b2bdd1SGireesh Nagabhushana FW_ENOMEM = 12, /* out of memory */ 2956b2bdd1SGireesh Nagabhushana FW_EFAULT = 14, /* bad address; fw bad */ 3056b2bdd1SGireesh Nagabhushana FW_EBUSY = 16, /* resource busy */ 3156b2bdd1SGireesh Nagabhushana FW_EEXIST = 17, /* file exists */ 32de483253SVishal Kulkarni FW_ENODEV = 19, /* no such device */ 3356b2bdd1SGireesh Nagabhushana FW_EINVAL = 22, /* invalid argument */ 3456b2bdd1SGireesh Nagabhushana FW_ENOSPC = 28, /* no space left on device */ 3556b2bdd1SGireesh Nagabhushana FW_ENOSYS = 38, /* functionality not implemented */ 36de483253SVishal Kulkarni FW_ENODATA = 61, /* no data available */ 3756b2bdd1SGireesh Nagabhushana FW_EPROTO = 71, /* protocol error */ 3856b2bdd1SGireesh Nagabhushana FW_EADDRINUSE = 98, /* address already in use */ 3956b2bdd1SGireesh Nagabhushana FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 4056b2bdd1SGireesh Nagabhushana FW_ENETDOWN = 100, /* network is down */ 4156b2bdd1SGireesh Nagabhushana FW_ENETUNREACH = 101, /* network is unreachable */ 4256b2bdd1SGireesh Nagabhushana FW_ENOBUFS = 105, /* no buffer space available */ 4356b2bdd1SGireesh Nagabhushana FW_ETIMEDOUT = 110, /* timeout */ 4456b2bdd1SGireesh Nagabhushana FW_EINPROGRESS = 115, /* fw internal */ 4556b2bdd1SGireesh Nagabhushana FW_SCSI_ABORT_REQUESTED = 128, /* */ 4656b2bdd1SGireesh Nagabhushana FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 4756b2bdd1SGireesh Nagabhushana FW_SCSI_ABORTED = 130, /* */ 4856b2bdd1SGireesh Nagabhushana FW_SCSI_CLOSE_REQUESTED = 131, /* */ 4956b2bdd1SGireesh Nagabhushana FW_ERR_LINK_DOWN = 132, /* */ 5056b2bdd1SGireesh Nagabhushana FW_RDEV_NOT_READY = 133, /* */ 5156b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_LOST = 134, /* */ 5256b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_LOGO = 135, /* */ 5356b2bdd1SGireesh Nagabhushana FW_FCOE_NO_XCHG = 136, /* */ 5456b2bdd1SGireesh Nagabhushana FW_SCSI_RSP_ERR = 137, /* */ 5556b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 5656b2bdd1SGireesh Nagabhushana FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 5756b2bdd1SGireesh Nagabhushana FW_SCSI_OVER_FLOW_ERR = 140, /* */ 583dde7c95SVishal Kulkarni FW_SCSI_DDP_ERR = 141, /* DDP error*/ 5956b2bdd1SGireesh Nagabhushana FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 6056b2bdd1SGireesh Nagabhushana }; 6156b2bdd1SGireesh Nagabhushana 623dde7c95SVishal Kulkarni /****************************************************************************** 633dde7c95SVishal Kulkarni * M E M O R Y T Y P E s 643dde7c95SVishal Kulkarni ******************************/ 653dde7c95SVishal Kulkarni 663dde7c95SVishal Kulkarni enum fw_memtype { 673dde7c95SVishal Kulkarni FW_MEMTYPE_EDC0 = 0x0, 683dde7c95SVishal Kulkarni FW_MEMTYPE_EDC1 = 0x1, 693dde7c95SVishal Kulkarni FW_MEMTYPE_EXTMEM = 0x2, 703dde7c95SVishal Kulkarni FW_MEMTYPE_FLASH = 0x4, 713dde7c95SVishal Kulkarni FW_MEMTYPE_INTERNAL = 0x5, 723dde7c95SVishal Kulkarni FW_MEMTYPE_EXTMEM1 = 0x6, 73*7e6ad469SVishal Kulkarni FW_MEMTYPE_HMA = 0x7, 743dde7c95SVishal Kulkarni }; 753dde7c95SVishal Kulkarni 763dde7c95SVishal Kulkarni /****************************************************************************** 773dde7c95SVishal Kulkarni * W O R K R E Q U E S T s 783dde7c95SVishal Kulkarni ********************************/ 7956b2bdd1SGireesh Nagabhushana 8056b2bdd1SGireesh Nagabhushana enum fw_wr_opcodes { 81de483253SVishal Kulkarni FW_FRAG_WR = 0x1d, 8256b2bdd1SGireesh Nagabhushana FW_FILTER_WR = 0x02, 8356b2bdd1SGireesh Nagabhushana FW_ULPTX_WR = 0x04, 8456b2bdd1SGireesh Nagabhushana FW_TP_WR = 0x05, 8556b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKT_WR = 0x08, 86de483253SVishal Kulkarni FW_ETH_TX_PKT2_WR = 0x44, 8756b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKTS_WR = 0x09, 883dde7c95SVishal Kulkarni FW_ETH_TX_PKTS2_WR = 0x78, 893dde7c95SVishal Kulkarni FW_ETH_TX_EO_WR = 0x1c, 9056b2bdd1SGireesh Nagabhushana FW_EQ_FLUSH_WR = 0x1b, 9156b2bdd1SGireesh Nagabhushana FW_OFLD_CONNECTION_WR = 0x2f, 9256b2bdd1SGireesh Nagabhushana FW_FLOWC_WR = 0x0a, 9356b2bdd1SGireesh Nagabhushana FW_OFLD_TX_DATA_WR = 0x0b, 9456b2bdd1SGireesh Nagabhushana FW_CMD_WR = 0x10, 9556b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKT_VM_WR = 0x11, 96*7e6ad469SVishal Kulkarni FW_ETH_TX_PKTS_VM_WR = 0x12, 9756b2bdd1SGireesh Nagabhushana FW_RI_RES_WR = 0x0c, 9856b2bdd1SGireesh Nagabhushana FW_RI_RDMA_WRITE_WR = 0x14, 9956b2bdd1SGireesh Nagabhushana FW_RI_SEND_WR = 0x15, 10056b2bdd1SGireesh Nagabhushana FW_RI_RDMA_READ_WR = 0x16, 10156b2bdd1SGireesh Nagabhushana FW_RI_RECV_WR = 0x17, 10256b2bdd1SGireesh Nagabhushana FW_RI_BIND_MW_WR = 0x18, 10356b2bdd1SGireesh Nagabhushana FW_RI_FR_NSMR_WR = 0x19, 1043dde7c95SVishal Kulkarni FW_RI_FR_NSMR_TPTE_WR = 0x20, 105*7e6ad469SVishal Kulkarni FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 10656b2bdd1SGireesh Nagabhushana FW_RI_INV_LSTAG_WR = 0x1a, 10756b2bdd1SGireesh Nagabhushana FW_RI_SEND_IMMEDIATE_WR = 0x15, 10856b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_WR = 0x16, 10956b2bdd1SGireesh Nagabhushana FW_RI_WR = 0x0d, 11056b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR = 0x6b, 11156b2bdd1SGireesh Nagabhushana FW_RDEV_WR = 0x38, 11256b2bdd1SGireesh Nagabhushana FW_FOISCSI_NODE_WR = 0x60, 11356b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_WR = 0x6a, 11456b2bdd1SGireesh Nagabhushana FW_FOISCSI_CHAP_WR = 0x6c, 11556b2bdd1SGireesh Nagabhushana FW_FCOE_ELS_CT_WR = 0x30, 11656b2bdd1SGireesh Nagabhushana FW_SCSI_WRITE_WR = 0x31, 11756b2bdd1SGireesh Nagabhushana FW_SCSI_READ_WR = 0x32, 11856b2bdd1SGireesh Nagabhushana FW_SCSI_CMD_WR = 0x33, 11956b2bdd1SGireesh Nagabhushana FW_SCSI_ABRT_CLS_WR = 0x34, 12056b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_ACC_WR = 0x35, 12156b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_XMIT_WR = 0x36, 12256b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_RSP_WR = 0x37, 123de483253SVishal Kulkarni FW_POFCOE_TCB_WR = 0x42, 124de483253SVishal Kulkarni FW_POFCOE_ULPTX_WR = 0x43, 1253dde7c95SVishal Kulkarni FW_ISCSI_TX_DATA_WR = 0x45, 1263dde7c95SVishal Kulkarni FW_PTP_TX_PKT_WR = 0x46, 1273dde7c95SVishal Kulkarni FW_TLSTX_DATA_WR = 0x68, 1283dde7c95SVishal Kulkarni FW_TLS_KEYCTX_TX_WR = 0x69, 1293dde7c95SVishal Kulkarni FW_CRYPTO_LOOKASIDE_WR = 0x6d, 1303dde7c95SVishal Kulkarni FW_COiSCSI_TGT_WR = 0x70, 1313dde7c95SVishal Kulkarni FW_COiSCSI_TGT_CONN_WR = 0x71, 1323dde7c95SVishal Kulkarni FW_COiSCSI_TGT_XMIT_WR = 0x72, 1333dde7c95SVishal Kulkarni FW_ISNS_WR = 0x75, 1343dde7c95SVishal Kulkarni FW_ISNS_XMIT_WR = 0x76, 1353dde7c95SVishal Kulkarni FW_FILTER2_WR = 0x77, 1363dde7c95SVishal Kulkarni FW_LASTC2E_WR = 0x80 13756b2bdd1SGireesh Nagabhushana }; 13856b2bdd1SGireesh Nagabhushana 13956b2bdd1SGireesh Nagabhushana /* 14056b2bdd1SGireesh Nagabhushana * Generic work request header flit0 14156b2bdd1SGireesh Nagabhushana */ 14256b2bdd1SGireesh Nagabhushana struct fw_wr_hdr { 14356b2bdd1SGireesh Nagabhushana __be32 hi; 14456b2bdd1SGireesh Nagabhushana __be32 lo; 14556b2bdd1SGireesh Nagabhushana }; 14656b2bdd1SGireesh Nagabhushana 1473dde7c95SVishal Kulkarni /* work request opcode (hi) 1483dde7c95SVishal Kulkarni */ 1493dde7c95SVishal Kulkarni #define S_FW_WR_OP 24 1503dde7c95SVishal Kulkarni #define M_FW_WR_OP 0xff 1513dde7c95SVishal Kulkarni #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 1523dde7c95SVishal Kulkarni #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 1533dde7c95SVishal Kulkarni 1543dde7c95SVishal Kulkarni /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 1553dde7c95SVishal Kulkarni */ 1563dde7c95SVishal Kulkarni #define S_FW_WR_ATOMIC 23 1573dde7c95SVishal Kulkarni #define M_FW_WR_ATOMIC 0x1 1583dde7c95SVishal Kulkarni #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 1593dde7c95SVishal Kulkarni #define G_FW_WR_ATOMIC(x) \ 1603dde7c95SVishal Kulkarni (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 1613dde7c95SVishal Kulkarni #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 1623dde7c95SVishal Kulkarni 1633dde7c95SVishal Kulkarni /* flush flag (hi) - firmware flushes flushable work request buffered 1643dde7c95SVishal Kulkarni * in the flow context. 1653dde7c95SVishal Kulkarni */ 1663dde7c95SVishal Kulkarni #define S_FW_WR_FLUSH 22 1673dde7c95SVishal Kulkarni #define M_FW_WR_FLUSH 0x1 1683dde7c95SVishal Kulkarni #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 1693dde7c95SVishal Kulkarni #define G_FW_WR_FLUSH(x) \ 1703dde7c95SVishal Kulkarni (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 1713dde7c95SVishal Kulkarni #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 1723dde7c95SVishal Kulkarni 1733dde7c95SVishal Kulkarni /* completion flag (hi) - firmware generates a cpl_fw6_ack 1743dde7c95SVishal Kulkarni */ 1753dde7c95SVishal Kulkarni #define S_FW_WR_COMPL 21 1763dde7c95SVishal Kulkarni #define M_FW_WR_COMPL 0x1 1773dde7c95SVishal Kulkarni #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 1783dde7c95SVishal Kulkarni #define G_FW_WR_COMPL(x) \ 1793dde7c95SVishal Kulkarni (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 1803dde7c95SVishal Kulkarni #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 1813dde7c95SVishal Kulkarni 18256b2bdd1SGireesh Nagabhushana 1833dde7c95SVishal Kulkarni /* work request immediate data lengh (hi) 1843dde7c95SVishal Kulkarni */ 1853dde7c95SVishal Kulkarni #define S_FW_WR_IMMDLEN 0 1863dde7c95SVishal Kulkarni #define M_FW_WR_IMMDLEN 0xff 1873dde7c95SVishal Kulkarni #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 1883dde7c95SVishal Kulkarni #define G_FW_WR_IMMDLEN(x) \ 1893dde7c95SVishal Kulkarni (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 19056b2bdd1SGireesh Nagabhushana 1913dde7c95SVishal Kulkarni /* egress queue status update to associated ingress queue entry (lo) 19256b2bdd1SGireesh Nagabhushana */ 1933dde7c95SVishal Kulkarni #define S_FW_WR_EQUIQ 31 1943dde7c95SVishal Kulkarni #define M_FW_WR_EQUIQ 0x1 1953dde7c95SVishal Kulkarni #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 1963dde7c95SVishal Kulkarni #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 1973dde7c95SVishal Kulkarni #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 1983dde7c95SVishal Kulkarni 1993dde7c95SVishal Kulkarni /* egress queue status update to egress queue status entry (lo) 2003dde7c95SVishal Kulkarni */ 2013dde7c95SVishal Kulkarni #define S_FW_WR_EQUEQ 30 2023dde7c95SVishal Kulkarni #define M_FW_WR_EQUEQ 0x1 2033dde7c95SVishal Kulkarni #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 2043dde7c95SVishal Kulkarni #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 2053dde7c95SVishal Kulkarni #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 2063dde7c95SVishal Kulkarni 2073dde7c95SVishal Kulkarni /* flow context identifier (lo) 2083dde7c95SVishal Kulkarni */ 2093dde7c95SVishal Kulkarni #define S_FW_WR_FLOWID 8 2103dde7c95SVishal Kulkarni #define M_FW_WR_FLOWID 0xfffff 2113dde7c95SVishal Kulkarni #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 2123dde7c95SVishal Kulkarni #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 2133dde7c95SVishal Kulkarni 2143dde7c95SVishal Kulkarni /* length in units of 16-bytes (lo) 2153dde7c95SVishal Kulkarni */ 2163dde7c95SVishal Kulkarni #define S_FW_WR_LEN16 0 2173dde7c95SVishal Kulkarni #define M_FW_WR_LEN16 0xff 2183dde7c95SVishal Kulkarni #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 2193dde7c95SVishal Kulkarni #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 22056b2bdd1SGireesh Nagabhushana 221de483253SVishal Kulkarni struct fw_frag_wr { 222de483253SVishal Kulkarni __be32 op_to_fragoff16; 223de483253SVishal Kulkarni __be32 flowid_len16; 224de483253SVishal Kulkarni __be64 r4; 225de483253SVishal Kulkarni }; 226de483253SVishal Kulkarni 227de483253SVishal Kulkarni #define S_FW_FRAG_WR_EOF 15 228de483253SVishal Kulkarni #define M_FW_FRAG_WR_EOF 0x1 229de483253SVishal Kulkarni #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 230de483253SVishal Kulkarni #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 231de483253SVishal Kulkarni #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 232de483253SVishal Kulkarni 233de483253SVishal Kulkarni #define S_FW_FRAG_WR_FRAGOFF16 8 234de483253SVishal Kulkarni #define M_FW_FRAG_WR_FRAGOFF16 0x7f 235de483253SVishal Kulkarni #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 236de483253SVishal Kulkarni #define G_FW_FRAG_WR_FRAGOFF16(x) \ 237de483253SVishal Kulkarni (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 238de483253SVishal Kulkarni 2393dde7c95SVishal Kulkarni /* valid filter configurations for compressed tuple 24056b2bdd1SGireesh Nagabhushana * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 24156b2bdd1SGireesh Nagabhushana * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 24256b2bdd1SGireesh Nagabhushana * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 24356b2bdd1SGireesh Nagabhushana * OV - Outer VLAN/VNIC_ID, 2443dde7c95SVishal Kulkarni */ 2453dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 2463dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 2473dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 2483dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_OV_P_FC 0x387 2493dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_PR_T 0x370 2503dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_PR_P_FC 0X363 2513dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_T_P_FC 0X353 2523dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 2533dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 2543dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 2553dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_T_OV_P_FC 0X317 2563dde7c95SVishal Kulkarni #define HW_TPL_FR_M_E_PR_FC 0X2E1 2573dde7c95SVishal Kulkarni #define HW_TPL_FR_M_E_T_FC 0X2D1 2583dde7c95SVishal Kulkarni #define HW_TPL_FR_M_PR_IV_FC 0X2A9 2593dde7c95SVishal Kulkarni #define HW_TPL_FR_M_PR_OV_FC 0X2A5 2603dde7c95SVishal Kulkarni #define HW_TPL_FR_M_T_IV_FC 0X299 2613dde7c95SVishal Kulkarni #define HW_TPL_FR_M_T_OV_FC 0X295 2623dde7c95SVishal Kulkarni #define HW_TPL_FR_E_PR_T_P 0X272 2633dde7c95SVishal Kulkarni #define HW_TPL_FR_E_PR_T_FC 0X271 2643dde7c95SVishal Kulkarni #define HW_TPL_FR_E_IV_FC 0X249 2653dde7c95SVishal Kulkarni #define HW_TPL_FR_E_OV_FC 0X245 2663dde7c95SVishal Kulkarni #define HW_TPL_FR_PR_T_IV_FC 0X239 2673dde7c95SVishal Kulkarni #define HW_TPL_FR_PR_T_OV_FC 0X235 2683dde7c95SVishal Kulkarni #define HW_TPL_FR_IV_OV_FC 0X20D 2693dde7c95SVishal Kulkarni #define HW_TPL_MT_M_E_PR 0X1E0 2703dde7c95SVishal Kulkarni #define HW_TPL_MT_M_E_T 0X1D0 2713dde7c95SVishal Kulkarni #define HW_TPL_MT_E_PR_T_FC 0X171 2723dde7c95SVishal Kulkarni #define HW_TPL_MT_E_IV 0X148 2733dde7c95SVishal Kulkarni #define HW_TPL_MT_E_OV 0X144 2743dde7c95SVishal Kulkarni #define HW_TPL_MT_PR_T_IV 0X138 2753dde7c95SVishal Kulkarni #define HW_TPL_MT_PR_T_OV 0X134 2763dde7c95SVishal Kulkarni #define HW_TPL_M_E_PR_P 0X0E2 2773dde7c95SVishal Kulkarni #define HW_TPL_M_E_T_P 0X0D2 2783dde7c95SVishal Kulkarni #define HW_TPL_E_PR_T_P_FC 0X073 2793dde7c95SVishal Kulkarni #define HW_TPL_E_IV_P 0X04A 2803dde7c95SVishal Kulkarni #define HW_TPL_E_OV_P 0X046 2813dde7c95SVishal Kulkarni #define HW_TPL_PR_T_IV_P 0X03A 2823dde7c95SVishal Kulkarni #define HW_TPL_PR_T_OV_P 0X036 28356b2bdd1SGireesh Nagabhushana 28456b2bdd1SGireesh Nagabhushana /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 28556b2bdd1SGireesh Nagabhushana enum fw_filter_wr_cookie { 28656b2bdd1SGireesh Nagabhushana FW_FILTER_WR_SUCCESS, 28756b2bdd1SGireesh Nagabhushana FW_FILTER_WR_FLT_ADDED, 28856b2bdd1SGireesh Nagabhushana FW_FILTER_WR_FLT_DELETED, 28956b2bdd1SGireesh Nagabhushana FW_FILTER_WR_SMT_TBL_FULL, 29056b2bdd1SGireesh Nagabhushana FW_FILTER_WR_EINVAL, 29156b2bdd1SGireesh Nagabhushana }; 29256b2bdd1SGireesh Nagabhushana 2933dde7c95SVishal Kulkarni enum fw_filter_wr_nat_mode { 2943dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_NONE = 0, 2953dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIP , 2963dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPDP, 2973dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPDPSIP, 2983dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPDPSP, 2993dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_SIPSP, 3003dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPSIPSP, 3013dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_FOURTUPLE, 3023dde7c95SVishal Kulkarni }; 3033dde7c95SVishal Kulkarni 30456b2bdd1SGireesh Nagabhushana struct fw_filter_wr { 30556b2bdd1SGireesh Nagabhushana __be32 op_pkd; 30656b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 30756b2bdd1SGireesh Nagabhushana __be64 r3; 30856b2bdd1SGireesh Nagabhushana __be32 tid_to_iq; 30956b2bdd1SGireesh Nagabhushana __be32 del_filter_to_l2tix; 31056b2bdd1SGireesh Nagabhushana __be16 ethtype; 31156b2bdd1SGireesh Nagabhushana __be16 ethtypem; 31256b2bdd1SGireesh Nagabhushana __u8 frag_to_ovlan_vldm; 31356b2bdd1SGireesh Nagabhushana __u8 smac_sel; 31456b2bdd1SGireesh Nagabhushana __be16 rx_chan_rx_rpl_iq; 31556b2bdd1SGireesh Nagabhushana __be32 maci_to_matchtypem; 31656b2bdd1SGireesh Nagabhushana __u8 ptcl; 31756b2bdd1SGireesh Nagabhushana __u8 ptclm; 31856b2bdd1SGireesh Nagabhushana __u8 ttyp; 31956b2bdd1SGireesh Nagabhushana __u8 ttypm; 32056b2bdd1SGireesh Nagabhushana __be16 ivlan; 32156b2bdd1SGireesh Nagabhushana __be16 ivlanm; 32256b2bdd1SGireesh Nagabhushana __be16 ovlan; 32356b2bdd1SGireesh Nagabhushana __be16 ovlanm; 32456b2bdd1SGireesh Nagabhushana __u8 lip[16]; 32556b2bdd1SGireesh Nagabhushana __u8 lipm[16]; 32656b2bdd1SGireesh Nagabhushana __u8 fip[16]; 32756b2bdd1SGireesh Nagabhushana __u8 fipm[16]; 32856b2bdd1SGireesh Nagabhushana __be16 lp; 32956b2bdd1SGireesh Nagabhushana __be16 lpm; 33056b2bdd1SGireesh Nagabhushana __be16 fp; 33156b2bdd1SGireesh Nagabhushana __be16 fpm; 33256b2bdd1SGireesh Nagabhushana __be16 r7; 33356b2bdd1SGireesh Nagabhushana __u8 sma[6]; 33456b2bdd1SGireesh Nagabhushana }; 33556b2bdd1SGireesh Nagabhushana 3363dde7c95SVishal Kulkarni struct fw_filter2_wr { 3373dde7c95SVishal Kulkarni __be32 op_pkd; 3383dde7c95SVishal Kulkarni __be32 len16_pkd; 3393dde7c95SVishal Kulkarni __be64 r3; 3403dde7c95SVishal Kulkarni __be32 tid_to_iq; 3413dde7c95SVishal Kulkarni __be32 del_filter_to_l2tix; 3423dde7c95SVishal Kulkarni __be16 ethtype; 3433dde7c95SVishal Kulkarni __be16 ethtypem; 3443dde7c95SVishal Kulkarni __u8 frag_to_ovlan_vldm; 3453dde7c95SVishal Kulkarni __u8 smac_sel; 3463dde7c95SVishal Kulkarni __be16 rx_chan_rx_rpl_iq; 3473dde7c95SVishal Kulkarni __be32 maci_to_matchtypem; 3483dde7c95SVishal Kulkarni __u8 ptcl; 3493dde7c95SVishal Kulkarni __u8 ptclm; 3503dde7c95SVishal Kulkarni __u8 ttyp; 3513dde7c95SVishal Kulkarni __u8 ttypm; 3523dde7c95SVishal Kulkarni __be16 ivlan; 3533dde7c95SVishal Kulkarni __be16 ivlanm; 3543dde7c95SVishal Kulkarni __be16 ovlan; 3553dde7c95SVishal Kulkarni __be16 ovlanm; 3563dde7c95SVishal Kulkarni __u8 lip[16]; 3573dde7c95SVishal Kulkarni __u8 lipm[16]; 3583dde7c95SVishal Kulkarni __u8 fip[16]; 3593dde7c95SVishal Kulkarni __u8 fipm[16]; 3603dde7c95SVishal Kulkarni __be16 lp; 3613dde7c95SVishal Kulkarni __be16 lpm; 3623dde7c95SVishal Kulkarni __be16 fp; 3633dde7c95SVishal Kulkarni __be16 fpm; 3643dde7c95SVishal Kulkarni __be16 r7; 3653dde7c95SVishal Kulkarni __u8 sma[6]; 366*7e6ad469SVishal Kulkarni __be16 r8; 3673dde7c95SVishal Kulkarni __u8 filter_type_swapmac; 3683dde7c95SVishal Kulkarni __u8 natmode_to_ulp_type; 3693dde7c95SVishal Kulkarni __be16 newlport; 3703dde7c95SVishal Kulkarni __be16 newfport; 3713dde7c95SVishal Kulkarni __u8 newlip[16]; 3723dde7c95SVishal Kulkarni __u8 newfip[16]; 3733dde7c95SVishal Kulkarni __be32 natseqcheck; 374*7e6ad469SVishal Kulkarni __be32 r9; 3753dde7c95SVishal Kulkarni __be64 r10; 3763dde7c95SVishal Kulkarni __be64 r11; 3773dde7c95SVishal Kulkarni __be64 r12; 3783dde7c95SVishal Kulkarni __be64 r13; 3793dde7c95SVishal Kulkarni }; 3803dde7c95SVishal Kulkarni 3813dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_TID 12 3823dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_TID 0xfffff 3833dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 3843dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_TID(x) \ 3853dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 3863dde7c95SVishal Kulkarni 3873dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RQTYPE 11 3883dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RQTYPE 0x1 3893dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 3903dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RQTYPE(x) \ 3913dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 3923dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 3933dde7c95SVishal Kulkarni 3943dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_NOREPLY 10 3953dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_NOREPLY 0x1 3963dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 3973dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_NOREPLY(x) \ 3983dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 3993dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 4003dde7c95SVishal Kulkarni 4013dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IQ 0 4023dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IQ 0x3ff 4033dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 4043dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IQ(x) \ 4053dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 4063dde7c95SVishal Kulkarni 4073dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DEL_FILTER 31 4083dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DEL_FILTER 0x1 4093dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 4103dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DEL_FILTER(x) \ 4113dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 4123dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 4133dde7c95SVishal Kulkarni 414*7e6ad469SVishal Kulkarni #define S_FW_FILTER2_WR_DROP_ENCAP 30 415*7e6ad469SVishal Kulkarni #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 416*7e6ad469SVishal Kulkarni #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 417*7e6ad469SVishal Kulkarni #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 418*7e6ad469SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 419*7e6ad469SVishal Kulkarni #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 420*7e6ad469SVishal Kulkarni 421*7e6ad469SVishal Kulkarni #define S_FW_FILTER2_WR_TX_LOOP 29 422*7e6ad469SVishal Kulkarni #define M_FW_FILTER2_WR_TX_LOOP 0x1 423*7e6ad469SVishal Kulkarni #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 424*7e6ad469SVishal Kulkarni #define G_FW_FILTER2_WR_TX_LOOP(x) \ 425*7e6ad469SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 426*7e6ad469SVishal Kulkarni #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 427*7e6ad469SVishal Kulkarni 4283dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RPTTID 25 4293dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RPTTID 0x1 4303dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 4313dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RPTTID(x) \ 4323dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 4333dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 4343dde7c95SVishal Kulkarni 4353dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DROP 24 4363dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DROP 0x1 4373dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 4383dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DROP(x) \ 4393dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 4403dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 4413dde7c95SVishal Kulkarni 4423dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DIRSTEER 23 4433dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DIRSTEER 0x1 4443dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 4453dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DIRSTEER(x) \ 4463dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 4473dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 4483dde7c95SVishal Kulkarni 4493dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MASKHASH 22 4503dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MASKHASH 0x1 4513dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 4523dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MASKHASH(x) \ 4533dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 4543dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 4553dde7c95SVishal Kulkarni 4563dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DIRSTEERHASH 21 4573dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 4583dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 4593dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 4603dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 4613dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 4623dde7c95SVishal Kulkarni 4633dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_LPBK 20 4643dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_LPBK 0x1 4653dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 4663dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_LPBK(x) \ 4673dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 4683dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 4693dde7c95SVishal Kulkarni 4703dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DMAC 19 4713dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DMAC 0x1 4723dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 4733dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DMAC(x) \ 4743dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 4753dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 4763dde7c95SVishal Kulkarni 4773dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_SMAC 18 4783dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_SMAC 0x1 4793dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 4803dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_SMAC(x) \ 4813dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 4823dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 4833dde7c95SVishal Kulkarni 4843dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_INSVLAN 17 4853dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_INSVLAN 0x1 4863dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 4873dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_INSVLAN(x) \ 4883dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 4893dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 4903dde7c95SVishal Kulkarni 4913dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RMVLAN 16 4923dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RMVLAN 0x1 4933dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 4943dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RMVLAN(x) \ 4953dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 4963dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 4973dde7c95SVishal Kulkarni 4983dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_HITCNTS 15 4993dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_HITCNTS 0x1 5003dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 5013dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_HITCNTS(x) \ 5023dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 5033dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 5043dde7c95SVishal Kulkarni 5053dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_TXCHAN 13 5063dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_TXCHAN 0x3 5073dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 5083dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_TXCHAN(x) \ 5093dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 5103dde7c95SVishal Kulkarni 5113dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PRIO 12 5123dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PRIO 0x1 5133dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 5143dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PRIO(x) \ 5153dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 5163dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 5173dde7c95SVishal Kulkarni 5183dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_L2TIX 0 5193dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_L2TIX 0xfff 5203dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 5213dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_L2TIX(x) \ 5223dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 5233dde7c95SVishal Kulkarni 5243dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FRAG 7 5253dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FRAG 0x1 5263dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 5273dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FRAG(x) \ 5283dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 5293dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 5303dde7c95SVishal Kulkarni 5313dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FRAGM 6 5323dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FRAGM 0x1 5333dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 5343dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FRAGM(x) \ 5353dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 5363dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 5373dde7c95SVishal Kulkarni 5383dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IVLAN_VLD 5 5393dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IVLAN_VLD 0x1 5403dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 5413dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 5423dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 5433dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 5443dde7c95SVishal Kulkarni 5453dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_OVLAN_VLD 4 5463dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_OVLAN_VLD 0x1 5473dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 5483dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 5493dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 5503dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 5513dde7c95SVishal Kulkarni 5523dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IVLAN_VLDM 3 5533dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 5543dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 5553dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 5563dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 5573dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 5583dde7c95SVishal Kulkarni 5593dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_OVLAN_VLDM 2 5603dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 5613dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 5623dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 5633dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 5643dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 5653dde7c95SVishal Kulkarni 5663dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RX_CHAN 15 5673dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RX_CHAN 0x1 5683dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 5693dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RX_CHAN(x) \ 5703dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 5713dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 5723dde7c95SVishal Kulkarni 5733dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RX_RPL_IQ 0 5743dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 5753dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 5763dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 5773dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 5783dde7c95SVishal Kulkarni 5793dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_FILTER_TYPE 1 5803dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 5813dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 5823dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 5833dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 5843dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 5853dde7c95SVishal Kulkarni 5863dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_SWAPMAC 0 5873dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_SWAPMAC 0x1 5883dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 5893dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_SWAPMAC(x) \ 5903dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 5913dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 5923dde7c95SVishal Kulkarni 5933dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_NATMODE 5 5943dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_NATMODE 0x7 5953dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 5963dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_NATMODE(x) \ 5973dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 5983dde7c95SVishal Kulkarni 5993dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_NATFLAGCHECK 4 6003dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 6013dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 6023dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 6033dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 6043dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 6053dde7c95SVishal Kulkarni 6063dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_ULP_TYPE 0 6073dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_ULP_TYPE 0xf 6083dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 6093dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 6103dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 6113dde7c95SVishal Kulkarni 6123dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MACI 23 6133dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MACI 0x1ff 6143dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 6153dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MACI(x) \ 6163dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 6173dde7c95SVishal Kulkarni 6183dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MACIM 14 6193dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MACIM 0x1ff 6203dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 6213dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MACIM(x) \ 6223dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 6233dde7c95SVishal Kulkarni 6243dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FCOE 13 6253dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FCOE 0x1 6263dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 6273dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FCOE(x) \ 6283dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 6293dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 6303dde7c95SVishal Kulkarni 6313dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FCOEM 12 6323dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FCOEM 0x1 6333dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 6343dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FCOEM(x) \ 6353dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 6363dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 6373dde7c95SVishal Kulkarni 6383dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PORT 9 6393dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PORT 0x7 6403dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 6413dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PORT(x) \ 6423dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 6433dde7c95SVishal Kulkarni 6443dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PORTM 6 6453dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PORTM 0x7 6463dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 6473dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PORTM(x) \ 6483dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 6493dde7c95SVishal Kulkarni 6503dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MATCHTYPE 3 6513dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MATCHTYPE 0x7 6523dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 6533dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MATCHTYPE(x) \ 6543dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 6553dde7c95SVishal Kulkarni 6563dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MATCHTYPEM 0 6573dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MATCHTYPEM 0x7 6583dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 6593dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 6603dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 66156b2bdd1SGireesh Nagabhushana 66256b2bdd1SGireesh Nagabhushana struct fw_ulptx_wr { 66356b2bdd1SGireesh Nagabhushana __be32 op_to_compl; 66456b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 66556b2bdd1SGireesh Nagabhushana __u64 cookie; 66656b2bdd1SGireesh Nagabhushana }; 66756b2bdd1SGireesh Nagabhushana 668*7e6ad469SVishal Kulkarni /* flag for packet type - control packet (0), data packet (1) 669*7e6ad469SVishal Kulkarni */ 670*7e6ad469SVishal Kulkarni #define S_FW_ULPTX_WR_DATA 28 671*7e6ad469SVishal Kulkarni #define M_FW_ULPTX_WR_DATA 0x1 672*7e6ad469SVishal Kulkarni #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 673*7e6ad469SVishal Kulkarni #define G_FW_ULPTX_WR_DATA(x) \ 674*7e6ad469SVishal Kulkarni (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 675*7e6ad469SVishal Kulkarni #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 676*7e6ad469SVishal Kulkarni 67756b2bdd1SGireesh Nagabhushana struct fw_tp_wr { 67856b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 67956b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 68056b2bdd1SGireesh Nagabhushana __u64 cookie; 68156b2bdd1SGireesh Nagabhushana }; 68256b2bdd1SGireesh Nagabhushana 68356b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_wr { 68456b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 68556b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 68656b2bdd1SGireesh Nagabhushana __be64 r3; 68756b2bdd1SGireesh Nagabhushana }; 68856b2bdd1SGireesh Nagabhushana 6893dde7c95SVishal Kulkarni #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 6903dde7c95SVishal Kulkarni #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 6913dde7c95SVishal Kulkarni #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 6923dde7c95SVishal Kulkarni #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 6933dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 69456b2bdd1SGireesh Nagabhushana 695de483253SVishal Kulkarni struct fw_eth_tx_pkt2_wr { 696de483253SVishal Kulkarni __be32 op_immdlen; 697de483253SVishal Kulkarni __be32 equiq_to_len16; 698de483253SVishal Kulkarni __be32 r3; 699de483253SVishal Kulkarni __be32 L4ChkDisable_to_IpHdrLen; 700de483253SVishal Kulkarni }; 701de483253SVishal Kulkarni 702de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 703de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 704de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 705de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 706de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 707de483253SVishal Kulkarni 708de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 709de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 710de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 711de483253SVishal Kulkarni ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 712de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 713de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 714de483253SVishal Kulkarni M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 715de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 716de483253SVishal Kulkarni V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 717de483253SVishal Kulkarni 718de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 719de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 720de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 721de483253SVishal Kulkarni ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 722de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 723de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 724de483253SVishal Kulkarni M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 725de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 726de483253SVishal Kulkarni V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 727de483253SVishal Kulkarni 728de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 729de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 730de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 731de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 732de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 733de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 734de483253SVishal Kulkarni 735de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 736de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 737de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 738de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 739de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 740de483253SVishal Kulkarni 741de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 742de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 743de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 744de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 745de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 746de483253SVishal Kulkarni 747de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 748de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 749de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 750de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 751de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 752de483253SVishal Kulkarni 75356b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkts_wr { 75456b2bdd1SGireesh Nagabhushana __be32 op_pkd; 75556b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 75656b2bdd1SGireesh Nagabhushana __be32 r3; 75756b2bdd1SGireesh Nagabhushana __be16 plen; 75856b2bdd1SGireesh Nagabhushana __u8 npkt; 75956b2bdd1SGireesh Nagabhushana __u8 type; 76056b2bdd1SGireesh Nagabhushana }; 76156b2bdd1SGireesh Nagabhushana 7623dde7c95SVishal Kulkarni #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 7633dde7c95SVishal Kulkarni #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 7643dde7c95SVishal Kulkarni #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 7653dde7c95SVishal Kulkarni #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 7663dde7c95SVishal Kulkarni (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 7673dde7c95SVishal Kulkarni 7683dde7c95SVishal Kulkarni struct fw_eth_tx_pkt_ptp_wr { 76956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 77056b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 77156b2bdd1SGireesh Nagabhushana __be64 r3; 77256b2bdd1SGireesh Nagabhushana }; 77356b2bdd1SGireesh Nagabhushana 7743dde7c95SVishal Kulkarni enum fw_eth_tx_eo_type { 7753dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_UDPSEG, 7763dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_TCPSEG, 7773dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_NVGRESEG, 7783dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_VXLANSEG, 7793dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_GENEVESEG, 7803dde7c95SVishal Kulkarni }; 7813dde7c95SVishal Kulkarni 7823dde7c95SVishal Kulkarni struct fw_eth_tx_eo_wr { 7833dde7c95SVishal Kulkarni __be32 op_immdlen; 7843dde7c95SVishal Kulkarni __be32 equiq_to_len16; 7853dde7c95SVishal Kulkarni __be64 r3; 7863dde7c95SVishal Kulkarni union fw_eth_tx_eo { 7873dde7c95SVishal Kulkarni struct fw_eth_tx_eo_udpseg { 7883dde7c95SVishal Kulkarni __u8 type; 7893dde7c95SVishal Kulkarni __u8 ethlen; 7903dde7c95SVishal Kulkarni __be16 iplen; 7913dde7c95SVishal Kulkarni __u8 udplen; 7923dde7c95SVishal Kulkarni __u8 rtplen; 7933dde7c95SVishal Kulkarni __be16 r4; 7943dde7c95SVishal Kulkarni __be16 mss; 7953dde7c95SVishal Kulkarni __be16 schedpktsize; 7963dde7c95SVishal Kulkarni __be32 plen; 7973dde7c95SVishal Kulkarni } udpseg; 7983dde7c95SVishal Kulkarni struct fw_eth_tx_eo_tcpseg { 7993dde7c95SVishal Kulkarni __u8 type; 8003dde7c95SVishal Kulkarni __u8 ethlen; 8013dde7c95SVishal Kulkarni __be16 iplen; 8023dde7c95SVishal Kulkarni __u8 tcplen; 8033dde7c95SVishal Kulkarni __u8 tsclk_tsoff; 8043dde7c95SVishal Kulkarni __be16 r4; 8053dde7c95SVishal Kulkarni __be16 mss; 8063dde7c95SVishal Kulkarni __be16 r5; 8073dde7c95SVishal Kulkarni __be32 plen; 8083dde7c95SVishal Kulkarni } tcpseg; 8093dde7c95SVishal Kulkarni struct fw_eth_tx_eo_nvgreseg { 8103dde7c95SVishal Kulkarni __u8 type; 8113dde7c95SVishal Kulkarni __u8 iphdroffout; 8123dde7c95SVishal Kulkarni __be16 grehdroff; 8133dde7c95SVishal Kulkarni __be16 iphdroffin; 8143dde7c95SVishal Kulkarni __be16 tcphdroffin; 8153dde7c95SVishal Kulkarni __be16 mss; 8163dde7c95SVishal Kulkarni __be16 r4; 8173dde7c95SVishal Kulkarni __be32 plen; 8183dde7c95SVishal Kulkarni } nvgreseg; 8193dde7c95SVishal Kulkarni struct fw_eth_tx_eo_vxlanseg { 8203dde7c95SVishal Kulkarni __u8 type; 8213dde7c95SVishal Kulkarni __u8 iphdroffout; 8223dde7c95SVishal Kulkarni __be16 vxlanhdroff; 8233dde7c95SVishal Kulkarni __be16 iphdroffin; 8243dde7c95SVishal Kulkarni __be16 tcphdroffin; 8253dde7c95SVishal Kulkarni __be16 mss; 8263dde7c95SVishal Kulkarni __be16 r4; 8273dde7c95SVishal Kulkarni __be32 plen; 8283dde7c95SVishal Kulkarni 8293dde7c95SVishal Kulkarni } vxlanseg; 8303dde7c95SVishal Kulkarni struct fw_eth_tx_eo_geneveseg { 8313dde7c95SVishal Kulkarni __u8 type; 8323dde7c95SVishal Kulkarni __u8 iphdroffout; 8333dde7c95SVishal Kulkarni __be16 genevehdroff; 8343dde7c95SVishal Kulkarni __be16 iphdroffin; 8353dde7c95SVishal Kulkarni __be16 tcphdroffin; 8363dde7c95SVishal Kulkarni __be16 mss; 8373dde7c95SVishal Kulkarni __be16 r4; 8383dde7c95SVishal Kulkarni __be32 plen; 8393dde7c95SVishal Kulkarni } geneveseg; 8403dde7c95SVishal Kulkarni } u; 8413dde7c95SVishal Kulkarni }; 8423dde7c95SVishal Kulkarni 8433dde7c95SVishal Kulkarni #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 8443dde7c95SVishal Kulkarni #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 8453dde7c95SVishal Kulkarni #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 8463dde7c95SVishal Kulkarni #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 8473dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 8483dde7c95SVishal Kulkarni 8493dde7c95SVishal Kulkarni #define S_FW_ETH_TX_EO_WR_TSCLK 6 8503dde7c95SVishal Kulkarni #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 8513dde7c95SVishal Kulkarni #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 8523dde7c95SVishal Kulkarni #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 8533dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 8543dde7c95SVishal Kulkarni 8553dde7c95SVishal Kulkarni #define S_FW_ETH_TX_EO_WR_TSOFF 0 8563dde7c95SVishal Kulkarni #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 8573dde7c95SVishal Kulkarni #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 8583dde7c95SVishal Kulkarni #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 8593dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 8603dde7c95SVishal Kulkarni 86156b2bdd1SGireesh Nagabhushana struct fw_eq_flush_wr { 86256b2bdd1SGireesh Nagabhushana __u8 opcode; 86356b2bdd1SGireesh Nagabhushana __u8 r1[3]; 86456b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 86556b2bdd1SGireesh Nagabhushana __be64 r3; 86656b2bdd1SGireesh Nagabhushana }; 86756b2bdd1SGireesh Nagabhushana 86856b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_wr { 86956b2bdd1SGireesh Nagabhushana __be32 op_compl; 87056b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 87156b2bdd1SGireesh Nagabhushana __u64 cookie; 87256b2bdd1SGireesh Nagabhushana __be64 r2; 87356b2bdd1SGireesh Nagabhushana __be64 r3; 87456b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le { 87556b2bdd1SGireesh Nagabhushana __be32 version_cpl; 87656b2bdd1SGireesh Nagabhushana __be32 filter; 87756b2bdd1SGireesh Nagabhushana __be32 r1; 87856b2bdd1SGireesh Nagabhushana __be16 lport; 87956b2bdd1SGireesh Nagabhushana __be16 pport; 88056b2bdd1SGireesh Nagabhushana union fw_ofld_connection_leip { 88156b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le_ipv4 { 88256b2bdd1SGireesh Nagabhushana __be32 pip; 88356b2bdd1SGireesh Nagabhushana __be32 lip; 88456b2bdd1SGireesh Nagabhushana __be64 r0; 88556b2bdd1SGireesh Nagabhushana __be64 r1; 88656b2bdd1SGireesh Nagabhushana __be64 r2; 88756b2bdd1SGireesh Nagabhushana } ipv4; 88856b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le_ipv6 { 88956b2bdd1SGireesh Nagabhushana __be64 pip_hi; 89056b2bdd1SGireesh Nagabhushana __be64 pip_lo; 89156b2bdd1SGireesh Nagabhushana __be64 lip_hi; 89256b2bdd1SGireesh Nagabhushana __be64 lip_lo; 89356b2bdd1SGireesh Nagabhushana } ipv6; 89456b2bdd1SGireesh Nagabhushana } u; 89556b2bdd1SGireesh Nagabhushana } le; 89656b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_tcb { 89756b2bdd1SGireesh Nagabhushana __be32 t_state_to_astid; 89856b2bdd1SGireesh Nagabhushana __be16 cplrxdataack_cplpassacceptrpl; 89956b2bdd1SGireesh Nagabhushana __be16 rcv_adv; 90056b2bdd1SGireesh Nagabhushana __be32 rcv_nxt; 90156b2bdd1SGireesh Nagabhushana __be32 tx_max; 90256b2bdd1SGireesh Nagabhushana __be64 opt0; 90356b2bdd1SGireesh Nagabhushana __be32 opt2; 90456b2bdd1SGireesh Nagabhushana __be32 r1; 90556b2bdd1SGireesh Nagabhushana __be64 r2; 90656b2bdd1SGireesh Nagabhushana __be64 r3; 90756b2bdd1SGireesh Nagabhushana } tcb; 90856b2bdd1SGireesh Nagabhushana }; 90956b2bdd1SGireesh Nagabhushana 9103dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_VERSION 31 9113dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 9123dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 9133dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 9143dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 9153dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 9163dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_VERSION) 9173dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 9183dde7c95SVishal Kulkarni 9193dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_CPL 30 9203dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 9213dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 9223dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 9233dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 9243dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 9253dde7c95SVishal Kulkarni 9263dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 9273dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 9283dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 9293dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 9303dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 9313dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 9323dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_T_STATE) 9333dde7c95SVishal Kulkarni 9343dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 9353dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 9363dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 9373dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 9383dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 9393dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 9403dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 9413dde7c95SVishal Kulkarni 9423dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_ASTID 0 9433dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 9443dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 9453dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 9463dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 9473dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 9483dde7c95SVishal Kulkarni 9493dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 9503dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 9513dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 9523dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 9533dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 9543dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 9553dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 9563dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 95756b2bdd1SGireesh Nagabhushana V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 95856b2bdd1SGireesh Nagabhushana 9593dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 9603dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 9613dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 9623dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 9633dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 9643dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 9653dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 9663dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 96756b2bdd1SGireesh Nagabhushana V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 96856b2bdd1SGireesh Nagabhushana 96956b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem_tcpstate { 9703dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 9713dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 9723dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 9733dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 9743dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 9753dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 9763dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 9773dde7c95SVishal Kulkarni * will resend FIN - equiv ESTAB 9783dde7c95SVishal Kulkarni */ 9793dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 9803dde7c95SVishal Kulkarni * will resend FIN but have 9813dde7c95SVishal Kulkarni * received FIN 9823dde7c95SVishal Kulkarni */ 9833dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 9843dde7c95SVishal Kulkarni * will resend FIN but have 9853dde7c95SVishal Kulkarni * received FIN 9863dde7c95SVishal Kulkarni */ 9873dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 9883dde7c95SVishal Kulkarni * waiting for FIN 9893dde7c95SVishal Kulkarni */ 9903dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 9913dde7c95SVishal Kulkarni }; 9923dde7c95SVishal Kulkarni 9933dde7c95SVishal Kulkarni enum fw_flowc_mnem_eostate { 9943dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 9953dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 9963dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 9973dde7c95SVishal Kulkarni * outstanding payload 9983dde7c95SVishal Kulkarni */ 9993dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 10003dde7c95SVishal Kulkarni * discarding outstanding payload 10013dde7c95SVishal Kulkarni */ 100256b2bdd1SGireesh Nagabhushana }; 100356b2bdd1SGireesh Nagabhushana 100456b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem { 1005de483253SVishal Kulkarni FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1006de483253SVishal Kulkarni FW_FLOWC_MNEM_CH = 1, 1007de483253SVishal Kulkarni FW_FLOWC_MNEM_PORT = 2, 1008de483253SVishal Kulkarni FW_FLOWC_MNEM_IQID = 3, 1009de483253SVishal Kulkarni FW_FLOWC_MNEM_SNDNXT = 4, 1010de483253SVishal Kulkarni FW_FLOWC_MNEM_RCVNXT = 5, 1011de483253SVishal Kulkarni FW_FLOWC_MNEM_SNDBUF = 6, 1012de483253SVishal Kulkarni FW_FLOWC_MNEM_MSS = 7, 1013de483253SVishal Kulkarni FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1014de483253SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE = 9, 10153dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE = 10, 1016de483253SVishal Kulkarni FW_FLOWC_MNEM_SCHEDCLASS = 11, 1017de483253SVishal Kulkarni FW_FLOWC_MNEM_DCBPRIO = 12, 10183dde7c95SVishal Kulkarni FW_FLOWC_MNEM_SND_SCALE = 13, 10193dde7c95SVishal Kulkarni FW_FLOWC_MNEM_RCV_SCALE = 14, 10203dde7c95SVishal Kulkarni FW_FLOWC_MNEM_ULP_MODE = 15, 10213dde7c95SVishal Kulkarni FW_FLOWC_MNEM_MAX = 16, 102256b2bdd1SGireesh Nagabhushana }; 102356b2bdd1SGireesh Nagabhushana 102456b2bdd1SGireesh Nagabhushana struct fw_flowc_mnemval { 102556b2bdd1SGireesh Nagabhushana __u8 mnemonic; 102656b2bdd1SGireesh Nagabhushana __u8 r4[3]; 102756b2bdd1SGireesh Nagabhushana __be32 val; 102856b2bdd1SGireesh Nagabhushana }; 102956b2bdd1SGireesh Nagabhushana 103056b2bdd1SGireesh Nagabhushana struct fw_flowc_wr { 103156b2bdd1SGireesh Nagabhushana __be32 op_to_nparams; 103256b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 103356b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 10343dde7c95SVishal Kulkarni struct fw_flowc_mnemval mnemval[0]; 103556b2bdd1SGireesh Nagabhushana #endif 103656b2bdd1SGireesh Nagabhushana }; 103756b2bdd1SGireesh Nagabhushana 10383dde7c95SVishal Kulkarni #define S_FW_FLOWC_WR_NPARAMS 0 10393dde7c95SVishal Kulkarni #define M_FW_FLOWC_WR_NPARAMS 0xff 10403dde7c95SVishal Kulkarni #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 10413dde7c95SVishal Kulkarni #define G_FW_FLOWC_WR_NPARAMS(x) \ 10423dde7c95SVishal Kulkarni (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 104356b2bdd1SGireesh Nagabhushana 104456b2bdd1SGireesh Nagabhushana struct fw_ofld_tx_data_wr { 104556b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 104656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 104756b2bdd1SGireesh Nagabhushana __be32 plen; 10483dde7c95SVishal Kulkarni __be32 lsodisable_to_flags; 10493dde7c95SVishal Kulkarni }; 10503dde7c95SVishal Kulkarni 10513dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 10523dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 10533dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 10543dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 10553dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 10563dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 10573dde7c95SVishal Kulkarni M_FW_OFLD_TX_DATA_WR_LSODISABLE) 10583dde7c95SVishal Kulkarni #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 10593dde7c95SVishal Kulkarni 10603dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 10613dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 10623dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 10633dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 10643dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 10653dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 10663dde7c95SVishal Kulkarni #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 10673dde7c95SVishal Kulkarni 10683dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 10693dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 10703dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 10713dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 10723dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 10733dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 10743dde7c95SVishal Kulkarni M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 10753dde7c95SVishal Kulkarni #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 10763dde7c95SVishal Kulkarni V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 10773dde7c95SVishal Kulkarni 10783dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 10793dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 10803dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 10813dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 10823dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 10833dde7c95SVishal Kulkarni 10843dde7c95SVishal Kulkarni 10853dde7c95SVishal Kulkarni /* Use fw_ofld_tx_data_wr structure */ 10863dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 10873dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 10883dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 10893dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 10903dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 10913dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 10923dde7c95SVishal Kulkarni 10933dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 10943dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 10953dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 10963dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 10973dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 10983dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 10993dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 11003dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 11013dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 11023dde7c95SVishal Kulkarni 11033dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 11043dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 11053dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 11063dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 11073dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 11083dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 11093dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 11103dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 11113dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 11123dde7c95SVishal Kulkarni 11133dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 11143dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 11153dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 11163dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 11173dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 11183dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 11193dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 11203dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 11213dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 11223dde7c95SVishal Kulkarni 11233dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 11243dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 11253dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 11263dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 11273dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 11283dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 11293dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 11303dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 11313dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 11323dde7c95SVishal Kulkarni 11333dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 11343dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 11353dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 11363dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 11373dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 11383dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 113956b2bdd1SGireesh Nagabhushana 114056b2bdd1SGireesh Nagabhushana struct fw_cmd_wr { 114156b2bdd1SGireesh Nagabhushana __be32 op_dma; 114256b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 114356b2bdd1SGireesh Nagabhushana __be64 cookie_daddr; 114456b2bdd1SGireesh Nagabhushana }; 114556b2bdd1SGireesh Nagabhushana 11463dde7c95SVishal Kulkarni #define S_FW_CMD_WR_DMA 17 11473dde7c95SVishal Kulkarni #define M_FW_CMD_WR_DMA 0x1 11483dde7c95SVishal Kulkarni #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 11493dde7c95SVishal Kulkarni #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 11503dde7c95SVishal Kulkarni #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 115156b2bdd1SGireesh Nagabhushana 115256b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_vm_wr { 115356b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 115456b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 115556b2bdd1SGireesh Nagabhushana __be32 r3[2]; 115656b2bdd1SGireesh Nagabhushana __u8 ethmacdst[6]; 115756b2bdd1SGireesh Nagabhushana __u8 ethmacsrc[6]; 115856b2bdd1SGireesh Nagabhushana __be16 ethtype; 115956b2bdd1SGireesh Nagabhushana __be16 vlantci; 116056b2bdd1SGireesh Nagabhushana }; 116156b2bdd1SGireesh Nagabhushana 1162*7e6ad469SVishal Kulkarni struct fw_eth_tx_pkts_vm_wr { 1163*7e6ad469SVishal Kulkarni __be32 op_pkd; 1164*7e6ad469SVishal Kulkarni __be32 equiq_to_len16; 1165*7e6ad469SVishal Kulkarni __be32 r3; 1166*7e6ad469SVishal Kulkarni __be16 plen; 1167*7e6ad469SVishal Kulkarni __u8 npkt; 1168*7e6ad469SVishal Kulkarni __u8 r4; 1169*7e6ad469SVishal Kulkarni __u8 ethmacdst[6]; 1170*7e6ad469SVishal Kulkarni __u8 ethmacsrc[6]; 1171*7e6ad469SVishal Kulkarni __be16 ethtype; 1172*7e6ad469SVishal Kulkarni __be16 vlantci; 1173*7e6ad469SVishal Kulkarni }; 1174*7e6ad469SVishal Kulkarni 11753dde7c95SVishal Kulkarni /****************************************************************************** 11763dde7c95SVishal Kulkarni * R I W O R K R E Q U E S T s 11773dde7c95SVishal Kulkarni **************************************/ 117856b2bdd1SGireesh Nagabhushana 117956b2bdd1SGireesh Nagabhushana enum fw_ri_wr_opcode { 118056b2bdd1SGireesh Nagabhushana FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 118156b2bdd1SGireesh Nagabhushana FW_RI_READ_REQ = 0x1, 118256b2bdd1SGireesh Nagabhushana FW_RI_READ_RESP = 0x2, 118356b2bdd1SGireesh Nagabhushana FW_RI_SEND = 0x3, 118456b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_INV = 0x4, 118556b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_SE = 0x5, 118656b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_SE_INV = 0x6, 118756b2bdd1SGireesh Nagabhushana FW_RI_TERMINATE = 0x7, 118856b2bdd1SGireesh Nagabhushana FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 118956b2bdd1SGireesh Nagabhushana FW_RI_BIND_MW = 0x9, 119056b2bdd1SGireesh Nagabhushana FW_RI_FAST_REGISTER = 0xa, 119156b2bdd1SGireesh Nagabhushana FW_RI_LOCAL_INV = 0xb, 119256b2bdd1SGireesh Nagabhushana FW_RI_QP_MODIFY = 0xc, 119356b2bdd1SGireesh Nagabhushana FW_RI_BYPASS = 0xd, 119456b2bdd1SGireesh Nagabhushana FW_RI_RECEIVE = 0xe, 11953dde7c95SVishal Kulkarni #if 0 11963dde7c95SVishal Kulkarni FW_RI_SEND_IMMEDIATE = 0x8, 11973dde7c95SVishal Kulkarni FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 11983dde7c95SVishal Kulkarni FW_RI_ATOMIC_REQUEST = 0xa, 11993dde7c95SVishal Kulkarni FW_RI_ATOMIC_RESPONSE = 0xb, 12003dde7c95SVishal Kulkarni 12013dde7c95SVishal Kulkarni FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 12023dde7c95SVishal Kulkarni FW_RI_FAST_REGISTER = 0xd, 12033dde7c95SVishal Kulkarni FW_RI_LOCAL_INV = 0xe, 12043dde7c95SVishal Kulkarni #endif 1205*7e6ad469SVishal Kulkarni FW_RI_SGE_EC_CR_RETURN = 0xf, 1206*7e6ad469SVishal Kulkarni FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 120756b2bdd1SGireesh Nagabhushana }; 120856b2bdd1SGireesh Nagabhushana 120956b2bdd1SGireesh Nagabhushana enum fw_ri_wr_flags { 121056b2bdd1SGireesh Nagabhushana FW_RI_COMPLETION_FLAG = 0x01, 121156b2bdd1SGireesh Nagabhushana FW_RI_NOTIFICATION_FLAG = 0x02, 121256b2bdd1SGireesh Nagabhushana FW_RI_SOLICITED_EVENT_FLAG = 0x04, 121356b2bdd1SGireesh Nagabhushana FW_RI_READ_FENCE_FLAG = 0x08, 121456b2bdd1SGireesh Nagabhushana FW_RI_LOCAL_FENCE_FLAG = 0x10, 1215*7e6ad469SVishal Kulkarni FW_RI_RDMA_READ_INVALIDATE = 0x20, 1216*7e6ad469SVishal Kulkarni FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 121756b2bdd1SGireesh Nagabhushana }; 121856b2bdd1SGireesh Nagabhushana 121956b2bdd1SGireesh Nagabhushana enum fw_ri_mpa_attrs { 122056b2bdd1SGireesh Nagabhushana FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 122156b2bdd1SGireesh Nagabhushana FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 122256b2bdd1SGireesh Nagabhushana FW_RI_MPA_CRC_ENABLE = 0x04, 122356b2bdd1SGireesh Nagabhushana FW_RI_MPA_IETF_ENABLE = 0x08 122456b2bdd1SGireesh Nagabhushana }; 122556b2bdd1SGireesh Nagabhushana 122656b2bdd1SGireesh Nagabhushana enum fw_ri_qp_caps { 12273dde7c95SVishal Kulkarni FW_RI_QP_RDMA_READ_ENABLE = 0x01, 12283dde7c95SVishal Kulkarni FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 12293dde7c95SVishal Kulkarni FW_RI_QP_BIND_ENABLE = 0x04, 12303dde7c95SVishal Kulkarni FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 12313dde7c95SVishal Kulkarni FW_RI_QP_STAG0_ENABLE = 0x10, 12323dde7c95SVishal Kulkarni FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 123356b2bdd1SGireesh Nagabhushana }; 123456b2bdd1SGireesh Nagabhushana 123556b2bdd1SGireesh Nagabhushana enum fw_ri_addr_type { 123656b2bdd1SGireesh Nagabhushana FW_RI_ZERO_BASED_TO = 0x00, 123756b2bdd1SGireesh Nagabhushana FW_RI_VA_BASED_TO = 0x01 123856b2bdd1SGireesh Nagabhushana }; 123956b2bdd1SGireesh Nagabhushana 124056b2bdd1SGireesh Nagabhushana enum fw_ri_mem_perms { 124156b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 124256b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM_READ = 0x02, 124356b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM = 0x03, 124456b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 124556b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 124656b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL = 0x0C 124756b2bdd1SGireesh Nagabhushana }; 124856b2bdd1SGireesh Nagabhushana 124956b2bdd1SGireesh Nagabhushana enum fw_ri_stag_type { 125056b2bdd1SGireesh Nagabhushana FW_RI_STAG_NSMR = 0x00, 125156b2bdd1SGireesh Nagabhushana FW_RI_STAG_SMR = 0x01, 125256b2bdd1SGireesh Nagabhushana FW_RI_STAG_MW = 0x02, 125356b2bdd1SGireesh Nagabhushana FW_RI_STAG_MW_RELAXED = 0x03 125456b2bdd1SGireesh Nagabhushana }; 125556b2bdd1SGireesh Nagabhushana 125656b2bdd1SGireesh Nagabhushana enum fw_ri_data_op { 125756b2bdd1SGireesh Nagabhushana FW_RI_DATA_IMMD = 0x81, 125856b2bdd1SGireesh Nagabhushana FW_RI_DATA_DSGL = 0x82, 125956b2bdd1SGireesh Nagabhushana FW_RI_DATA_ISGL = 0x83 126056b2bdd1SGireesh Nagabhushana }; 126156b2bdd1SGireesh Nagabhushana 126256b2bdd1SGireesh Nagabhushana enum fw_ri_sgl_depth { 126356b2bdd1SGireesh Nagabhushana FW_RI_SGL_DEPTH_MAX_SQ = 16, 126456b2bdd1SGireesh Nagabhushana FW_RI_SGL_DEPTH_MAX_RQ = 4 126556b2bdd1SGireesh Nagabhushana }; 126656b2bdd1SGireesh Nagabhushana 126756b2bdd1SGireesh Nagabhushana enum fw_ri_cqe_err { 126856b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 126956b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 127056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 127156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 127256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 127356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 127456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 12753dde7c95SVishal Kulkarni FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 12763dde7c95SVishal Kulkarni FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 127756b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 12783dde7c95SVishal Kulkarni FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 12793dde7c95SVishal Kulkarni FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 128056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 128156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 128256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 128356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 128456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 128556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 128656b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 128756b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 128856b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 128956b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 12903dde7c95SVishal Kulkarni FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 129156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 129256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 129356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 12943dde7c95SVishal Kulkarni FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 12953dde7c95SVishal Kulkarni FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 129656b2bdd1SGireesh Nagabhushana 129756b2bdd1SGireesh Nagabhushana }; 129856b2bdd1SGireesh Nagabhushana 129956b2bdd1SGireesh Nagabhushana struct fw_ri_dsge_pair { 130056b2bdd1SGireesh Nagabhushana __be32 len[2]; 130156b2bdd1SGireesh Nagabhushana __be64 addr[2]; 130256b2bdd1SGireesh Nagabhushana }; 130356b2bdd1SGireesh Nagabhushana 130456b2bdd1SGireesh Nagabhushana struct fw_ri_dsgl { 130556b2bdd1SGireesh Nagabhushana __u8 op; 130656b2bdd1SGireesh Nagabhushana __u8 r1; 130756b2bdd1SGireesh Nagabhushana __be16 nsge; 130856b2bdd1SGireesh Nagabhushana __be32 len0; 130956b2bdd1SGireesh Nagabhushana __be64 addr0; 131056b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 13113dde7c95SVishal Kulkarni struct fw_ri_dsge_pair sge[0]; 131256b2bdd1SGireesh Nagabhushana #endif 131356b2bdd1SGireesh Nagabhushana }; 131456b2bdd1SGireesh Nagabhushana 131556b2bdd1SGireesh Nagabhushana struct fw_ri_sge { 131656b2bdd1SGireesh Nagabhushana __be32 stag; 131756b2bdd1SGireesh Nagabhushana __be32 len; 131856b2bdd1SGireesh Nagabhushana __be64 to; 131956b2bdd1SGireesh Nagabhushana }; 132056b2bdd1SGireesh Nagabhushana 132156b2bdd1SGireesh Nagabhushana struct fw_ri_isgl { 132256b2bdd1SGireesh Nagabhushana __u8 op; 132356b2bdd1SGireesh Nagabhushana __u8 r1; 132456b2bdd1SGireesh Nagabhushana __be16 nsge; 132556b2bdd1SGireesh Nagabhushana __be32 r2; 132656b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 13273dde7c95SVishal Kulkarni struct fw_ri_sge sge[0]; 132856b2bdd1SGireesh Nagabhushana #endif 132956b2bdd1SGireesh Nagabhushana }; 133056b2bdd1SGireesh Nagabhushana 133156b2bdd1SGireesh Nagabhushana struct fw_ri_immd { 133256b2bdd1SGireesh Nagabhushana __u8 op; 133356b2bdd1SGireesh Nagabhushana __u8 r1; 133456b2bdd1SGireesh Nagabhushana __be16 r2; 133556b2bdd1SGireesh Nagabhushana __be32 immdlen; 133656b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 13373dde7c95SVishal Kulkarni __u8 data[0]; 133856b2bdd1SGireesh Nagabhushana #endif 133956b2bdd1SGireesh Nagabhushana }; 134056b2bdd1SGireesh Nagabhushana 134156b2bdd1SGireesh Nagabhushana struct fw_ri_tpte { 134256b2bdd1SGireesh Nagabhushana __be32 valid_to_pdid; 134356b2bdd1SGireesh Nagabhushana __be32 locread_to_qpid; 134456b2bdd1SGireesh Nagabhushana __be32 nosnoop_pbladdr; 134556b2bdd1SGireesh Nagabhushana __be32 len_lo; 134656b2bdd1SGireesh Nagabhushana __be32 va_hi; 134756b2bdd1SGireesh Nagabhushana __be32 va_lo_fbo; 134856b2bdd1SGireesh Nagabhushana __be32 dca_mwbcnt_pstag; 134956b2bdd1SGireesh Nagabhushana __be32 len_hi; 135056b2bdd1SGireesh Nagabhushana }; 135156b2bdd1SGireesh Nagabhushana 13523dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_VALID 31 13533dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_VALID 0x1 13543dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 13553dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_VALID(x) \ 13563dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 13573dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 13583dde7c95SVishal Kulkarni 13593dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_STAGKEY 23 13603dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_STAGKEY 0xff 13613dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 13623dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_STAGKEY(x) \ 13633dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 13643dde7c95SVishal Kulkarni 13653dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_STAGSTATE 22 13663dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_STAGSTATE 0x1 13673dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 13683dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_STAGSTATE(x) \ 13693dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 13703dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 13713dde7c95SVishal Kulkarni 13723dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_STAGTYPE 20 13733dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_STAGTYPE 0x3 13743dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 13753dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_STAGTYPE(x) \ 13763dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 13773dde7c95SVishal Kulkarni 13783dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PDID 0 13793dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PDID 0xfffff 13803dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 13813dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PDID(x) \ 13823dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 13833dde7c95SVishal Kulkarni 13843dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PERM 28 13853dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PERM 0xf 13863dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 13873dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PERM(x) \ 13883dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 13893dde7c95SVishal Kulkarni 13903dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_REMINVDIS 27 13913dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_REMINVDIS 0x1 13923dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 13933dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_REMINVDIS(x) \ 13943dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 13953dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 13963dde7c95SVishal Kulkarni 13973dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_ADDRTYPE 26 13983dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_ADDRTYPE 1 13993dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 14003dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_ADDRTYPE(x) \ 14013dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 14023dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 14033dde7c95SVishal Kulkarni 14043dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_MWBINDEN 25 14053dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_MWBINDEN 0x1 14063dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 14073dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_MWBINDEN(x) \ 14083dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 14093dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 14103dde7c95SVishal Kulkarni 14113dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PS 20 14123dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PS 0x1f 14133dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 14143dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PS(x) \ 14153dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 14163dde7c95SVishal Kulkarni 14173dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_QPID 0 14183dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_QPID 0xfffff 14193dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 14203dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_QPID(x) \ 14213dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 14223dde7c95SVishal Kulkarni 14233dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_NOSNOOP 31 14243dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_NOSNOOP 0x1 14253dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 14263dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_NOSNOOP(x) \ 14273dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 14283dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 14293dde7c95SVishal Kulkarni 14303dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PBLADDR 0 14313dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 14323dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 14333dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PBLADDR(x) \ 14343dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 14353dde7c95SVishal Kulkarni 14363dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_DCA 24 14373dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_DCA 0x1f 14383dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 14393dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_DCA(x) \ 14403dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 14413dde7c95SVishal Kulkarni 14423dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 14433dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 14443dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 14453dde7c95SVishal Kulkarni ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 14463dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 14473dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 144856b2bdd1SGireesh Nagabhushana 144956b2bdd1SGireesh Nagabhushana enum fw_ri_cqe_rxtx { 145056b2bdd1SGireesh Nagabhushana FW_RI_CQE_RXTX_RX = 0x0, 145156b2bdd1SGireesh Nagabhushana FW_RI_CQE_RXTX_TX = 0x1, 145256b2bdd1SGireesh Nagabhushana }; 145356b2bdd1SGireesh Nagabhushana 145456b2bdd1SGireesh Nagabhushana struct fw_ri_cqe { 145556b2bdd1SGireesh Nagabhushana union fw_ri_rxtx { 145656b2bdd1SGireesh Nagabhushana struct fw_ri_scqe { 145756b2bdd1SGireesh Nagabhushana __be32 qpid_n_stat_rxtx_type; 145856b2bdd1SGireesh Nagabhushana __be32 plen; 14593dde7c95SVishal Kulkarni __be32 stag; 146056b2bdd1SGireesh Nagabhushana __be32 wrid; 146156b2bdd1SGireesh Nagabhushana } scqe; 146256b2bdd1SGireesh Nagabhushana struct fw_ri_rcqe { 146356b2bdd1SGireesh Nagabhushana __be32 qpid_n_stat_rxtx_type; 146456b2bdd1SGireesh Nagabhushana __be32 plen; 146556b2bdd1SGireesh Nagabhushana __be32 stag; 146656b2bdd1SGireesh Nagabhushana __be32 msn; 146756b2bdd1SGireesh Nagabhushana } rcqe; 1468*7e6ad469SVishal Kulkarni struct fw_ri_rcqe_imm { 1469*7e6ad469SVishal Kulkarni __be32 qpid_n_stat_rxtx_type; 1470*7e6ad469SVishal Kulkarni __be32 plen; 1471*7e6ad469SVishal Kulkarni __be32 mo; 1472*7e6ad469SVishal Kulkarni __be32 msn; 1473*7e6ad469SVishal Kulkarni __u64 imm_data; 1474*7e6ad469SVishal Kulkarni } imm_data_rcqe; 147556b2bdd1SGireesh Nagabhushana } u; 147656b2bdd1SGireesh Nagabhushana }; 147756b2bdd1SGireesh Nagabhushana 14783dde7c95SVishal Kulkarni #define S_FW_RI_CQE_QPID 12 14793dde7c95SVishal Kulkarni #define M_FW_RI_CQE_QPID 0xfffff 14803dde7c95SVishal Kulkarni #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 14813dde7c95SVishal Kulkarni #define G_FW_RI_CQE_QPID(x) \ 14823dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 14833dde7c95SVishal Kulkarni 14843dde7c95SVishal Kulkarni #define S_FW_RI_CQE_NOTIFY 10 14853dde7c95SVishal Kulkarni #define M_FW_RI_CQE_NOTIFY 0x1 14863dde7c95SVishal Kulkarni #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 14873dde7c95SVishal Kulkarni #define G_FW_RI_CQE_NOTIFY(x) \ 14883dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 14893dde7c95SVishal Kulkarni 14903dde7c95SVishal Kulkarni #define S_FW_RI_CQE_STATUS 5 14913dde7c95SVishal Kulkarni #define M_FW_RI_CQE_STATUS 0x1f 14923dde7c95SVishal Kulkarni #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 14933dde7c95SVishal Kulkarni #define G_FW_RI_CQE_STATUS(x) \ 14943dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 14953dde7c95SVishal Kulkarni 14963dde7c95SVishal Kulkarni 14973dde7c95SVishal Kulkarni #define S_FW_RI_CQE_RXTX 4 14983dde7c95SVishal Kulkarni #define M_FW_RI_CQE_RXTX 0x1 14993dde7c95SVishal Kulkarni #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 15003dde7c95SVishal Kulkarni #define G_FW_RI_CQE_RXTX(x) \ 15013dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 15023dde7c95SVishal Kulkarni 15033dde7c95SVishal Kulkarni #define S_FW_RI_CQE_TYPE 0 15043dde7c95SVishal Kulkarni #define M_FW_RI_CQE_TYPE 0xf 15053dde7c95SVishal Kulkarni #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 15063dde7c95SVishal Kulkarni #define G_FW_RI_CQE_TYPE(x) \ 15073dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 150856b2bdd1SGireesh Nagabhushana 150956b2bdd1SGireesh Nagabhushana enum fw_ri_res_type { 151056b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_SQ, 151156b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_RQ, 151256b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_CQ, 15133dde7c95SVishal Kulkarni FW_RI_RES_TYPE_SRQ, 151456b2bdd1SGireesh Nagabhushana }; 151556b2bdd1SGireesh Nagabhushana 151656b2bdd1SGireesh Nagabhushana enum fw_ri_res_op { 151756b2bdd1SGireesh Nagabhushana FW_RI_RES_OP_WRITE, 151856b2bdd1SGireesh Nagabhushana FW_RI_RES_OP_RESET, 151956b2bdd1SGireesh Nagabhushana }; 152056b2bdd1SGireesh Nagabhushana 152156b2bdd1SGireesh Nagabhushana struct fw_ri_res { 152256b2bdd1SGireesh Nagabhushana union fw_ri_restype { 152356b2bdd1SGireesh Nagabhushana struct fw_ri_res_sqrq { 152456b2bdd1SGireesh Nagabhushana __u8 restype; 152556b2bdd1SGireesh Nagabhushana __u8 op; 152656b2bdd1SGireesh Nagabhushana __be16 r3; 152756b2bdd1SGireesh Nagabhushana __be32 eqid; 152856b2bdd1SGireesh Nagabhushana __be32 r4[2]; 152956b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 153056b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 153156b2bdd1SGireesh Nagabhushana __be64 eqaddr; 153256b2bdd1SGireesh Nagabhushana } sqrq; 153356b2bdd1SGireesh Nagabhushana struct fw_ri_res_cq { 153456b2bdd1SGireesh Nagabhushana __u8 restype; 153556b2bdd1SGireesh Nagabhushana __u8 op; 153656b2bdd1SGireesh Nagabhushana __be16 r3; 153756b2bdd1SGireesh Nagabhushana __be32 iqid; 153856b2bdd1SGireesh Nagabhushana __be32 r4[2]; 153956b2bdd1SGireesh Nagabhushana __be32 iqandst_to_iqandstindex; 154056b2bdd1SGireesh Nagabhushana __be16 iqdroprss_to_iqesize; 154156b2bdd1SGireesh Nagabhushana __be16 iqsize; 154256b2bdd1SGireesh Nagabhushana __be64 iqaddr; 154356b2bdd1SGireesh Nagabhushana __be32 iqns_iqro; 154456b2bdd1SGireesh Nagabhushana __be32 r6_lo; 154556b2bdd1SGireesh Nagabhushana __be64 r7; 154656b2bdd1SGireesh Nagabhushana } cq; 15473dde7c95SVishal Kulkarni struct fw_ri_res_srq { 15483dde7c95SVishal Kulkarni __u8 restype; 15493dde7c95SVishal Kulkarni __u8 op; 15503dde7c95SVishal Kulkarni __be16 r3; 15513dde7c95SVishal Kulkarni __be32 eqid; 15523dde7c95SVishal Kulkarni __be32 r4[2]; 15533dde7c95SVishal Kulkarni __be32 fetchszm_to_iqid; 15543dde7c95SVishal Kulkarni __be32 dcaen_to_eqsize; 15553dde7c95SVishal Kulkarni __be64 eqaddr; 15563dde7c95SVishal Kulkarni __be32 srqid; 15573dde7c95SVishal Kulkarni __be32 pdid; 15583dde7c95SVishal Kulkarni __be32 hwsrqsize; 15593dde7c95SVishal Kulkarni __be32 hwsrqaddr; 15603dde7c95SVishal Kulkarni } srq; 156156b2bdd1SGireesh Nagabhushana } u; 156256b2bdd1SGireesh Nagabhushana }; 156356b2bdd1SGireesh Nagabhushana 156456b2bdd1SGireesh Nagabhushana struct fw_ri_res_wr { 156556b2bdd1SGireesh Nagabhushana __be32 op_nres; 156656b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 156756b2bdd1SGireesh Nagabhushana __u64 cookie; 156856b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 15693dde7c95SVishal Kulkarni struct fw_ri_res res[0]; 157056b2bdd1SGireesh Nagabhushana #endif 157156b2bdd1SGireesh Nagabhushana }; 157256b2bdd1SGireesh Nagabhushana 15733dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_VFN 8 15743dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_VFN 0xff 15753dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 15763dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_VFN(x) \ 15773dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 15783dde7c95SVishal Kulkarni 15793dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_NRES 0 15803dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_NRES 0xff 15813dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 15823dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_NRES(x) \ 15833dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 15843dde7c95SVishal Kulkarni 15853dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FETCHSZM 26 15863dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FETCHSZM 0x1 15873dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 15883dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FETCHSZM(x) \ 15893dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 15903dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 15913dde7c95SVishal Kulkarni 15923dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_STATUSPGNS 25 15933dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_STATUSPGNS 0x1 15943dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 15953dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 15963dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 15973dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 15983dde7c95SVishal Kulkarni 15993dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_STATUSPGRO 24 16003dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_STATUSPGRO 0x1 16013dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 16023dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 16033dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 16043dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 16053dde7c95SVishal Kulkarni 16063dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FETCHNS 23 16073dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FETCHNS 0x1 16083dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 16093dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FETCHNS(x) \ 16103dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 16113dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 16123dde7c95SVishal Kulkarni 16133dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FETCHRO 22 16143dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FETCHRO 0x1 16153dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 16163dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FETCHRO(x) \ 16173dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 16183dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 16193dde7c95SVishal Kulkarni 16203dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_HOSTFCMODE 20 16213dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 16223dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 16233dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 16243dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 16253dde7c95SVishal Kulkarni 16263dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_CPRIO 19 16273dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_CPRIO 0x1 16283dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 16293dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_CPRIO(x) \ 16303dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 16313dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 16323dde7c95SVishal Kulkarni 16333dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_ONCHIP 18 16343dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_ONCHIP 0x1 16353dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 16363dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_ONCHIP(x) \ 16373dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 16383dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 16393dde7c95SVishal Kulkarni 16403dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_PCIECHN 16 16413dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_PCIECHN 0x3 16423dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 16433dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_PCIECHN(x) \ 16443dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 16453dde7c95SVishal Kulkarni 16463dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQID 0 16473dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQID 0xffff 16483dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 16493dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQID(x) \ 16503dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 16513dde7c95SVishal Kulkarni 16523dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_DCAEN 31 16533dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_DCAEN 0x1 16543dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 16553dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_DCAEN(x) \ 16563dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 16573dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 16583dde7c95SVishal Kulkarni 16593dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_DCACPU 26 16603dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_DCACPU 0x1f 16613dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 16623dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_DCACPU(x) \ 16633dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 16643dde7c95SVishal Kulkarni 16653dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FBMIN 23 16663dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FBMIN 0x7 16673dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 16683dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FBMIN(x) \ 16693dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 16703dde7c95SVishal Kulkarni 16713dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FBMAX 20 16723dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FBMAX 0x7 16733dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 16743dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FBMAX(x) \ 16753dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 16763dde7c95SVishal Kulkarni 16773dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 16783dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 16793dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 16803dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 16813dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 16823dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 16833dde7c95SVishal Kulkarni 16843dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_CIDXFTHRESH 16 16853dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 16863dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 16873dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 16883dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 16893dde7c95SVishal Kulkarni 16903dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_EQSIZE 0 16913dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_EQSIZE 0xffff 16923dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 16933dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_EQSIZE(x) \ 16943dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 16953dde7c95SVishal Kulkarni 16963dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANDST 15 16973dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANDST 0x1 16983dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 16993dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANDST(x) \ 17003dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 17013dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 17023dde7c95SVishal Kulkarni 17033dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANUS 14 17043dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANUS 0x1 17053dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 17063dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANUS(x) \ 17073dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 17083dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 17093dde7c95SVishal Kulkarni 17103dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANUD 12 17113dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANUD 0x3 17123dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 17133dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANUD(x) \ 17143dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 17153dde7c95SVishal Kulkarni 17163dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANDSTINDEX 0 17173dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 17183dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 17193dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 17203dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 17213dde7c95SVishal Kulkarni 17223dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQDROPRSS 15 17233dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQDROPRSS 0x1 17243dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 17253dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 17263dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 17273dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 17283dde7c95SVishal Kulkarni 17293dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQGTSMODE 14 17303dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQGTSMODE 0x1 17313dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 17323dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 17333dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 17343dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 17353dde7c95SVishal Kulkarni 17363dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQPCIECH 12 17373dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQPCIECH 0x3 17383dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 17393dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQPCIECH(x) \ 17403dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 17413dde7c95SVishal Kulkarni 17423dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQDCAEN 11 17433dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQDCAEN 0x1 17443dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 17453dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQDCAEN(x) \ 17463dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 17473dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 17483dde7c95SVishal Kulkarni 17493dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQDCACPU 6 17503dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQDCACPU 0x1f 17513dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 17523dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQDCACPU(x) \ 17533dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 17543dde7c95SVishal Kulkarni 17553dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 17563dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 17573dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 17583dde7c95SVishal Kulkarni ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 17593dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 17603dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 17613dde7c95SVishal Kulkarni 17623dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQO 3 17633dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQO 0x1 17643dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 17653dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQO(x) \ 17663dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 17673dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 17683dde7c95SVishal Kulkarni 17693dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQCPRIO 2 17703dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQCPRIO 0x1 17713dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 17723dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQCPRIO(x) \ 17733dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 17743dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 17753dde7c95SVishal Kulkarni 17763dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQESIZE 0 17773dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQESIZE 0x3 17783dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 17793dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQESIZE(x) \ 17803dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 17813dde7c95SVishal Kulkarni 17823dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQNS 31 17833dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQNS 0x1 17843dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 17853dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQNS(x) \ 17863dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 17873dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 17883dde7c95SVishal Kulkarni 17893dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQRO 30 17903dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQRO 0x1 17913dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 17923dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQRO(x) \ 17933dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 17943dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 179556b2bdd1SGireesh Nagabhushana 179656b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_write_wr { 179756b2bdd1SGireesh Nagabhushana __u8 opcode; 179856b2bdd1SGireesh Nagabhushana __u8 flags; 179956b2bdd1SGireesh Nagabhushana __u16 wrid; 180056b2bdd1SGireesh Nagabhushana __u8 r1[3]; 180156b2bdd1SGireesh Nagabhushana __u8 len16; 1802*7e6ad469SVishal Kulkarni __u64 immd_data; 180356b2bdd1SGireesh Nagabhushana __be32 plen; 180456b2bdd1SGireesh Nagabhushana __be32 stag_sink; 180556b2bdd1SGireesh Nagabhushana __be64 to_sink; 18063dde7c95SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 18073dde7c95SVishal Kulkarni union { 18083dde7c95SVishal Kulkarni struct fw_ri_immd immd_src[0]; 18093dde7c95SVishal Kulkarni struct fw_ri_isgl isgl_src[0]; 18103dde7c95SVishal Kulkarni } u; 18113dde7c95SVishal Kulkarni #endif 181256b2bdd1SGireesh Nagabhushana }; 181356b2bdd1SGireesh Nagabhushana 181456b2bdd1SGireesh Nagabhushana struct fw_ri_send_wr { 181556b2bdd1SGireesh Nagabhushana __u8 opcode; 181656b2bdd1SGireesh Nagabhushana __u8 flags; 181756b2bdd1SGireesh Nagabhushana __u16 wrid; 181856b2bdd1SGireesh Nagabhushana __u8 r1[3]; 181956b2bdd1SGireesh Nagabhushana __u8 len16; 182056b2bdd1SGireesh Nagabhushana __be32 sendop_pkd; 182156b2bdd1SGireesh Nagabhushana __be32 stag_inv; 182256b2bdd1SGireesh Nagabhushana __be32 plen; 182356b2bdd1SGireesh Nagabhushana __be32 r3; 182456b2bdd1SGireesh Nagabhushana __be64 r4; 18253dde7c95SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 18263dde7c95SVishal Kulkarni union { 18273dde7c95SVishal Kulkarni struct fw_ri_immd immd_src[0]; 18283dde7c95SVishal Kulkarni struct fw_ri_isgl isgl_src[0]; 18293dde7c95SVishal Kulkarni } u; 18303dde7c95SVishal Kulkarni #endif 183156b2bdd1SGireesh Nagabhushana }; 183256b2bdd1SGireesh Nagabhushana 18333dde7c95SVishal Kulkarni #define S_FW_RI_SEND_WR_SENDOP 0 18343dde7c95SVishal Kulkarni #define M_FW_RI_SEND_WR_SENDOP 0xf 18353dde7c95SVishal Kulkarni #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 18363dde7c95SVishal Kulkarni #define G_FW_RI_SEND_WR_SENDOP(x) \ 18373dde7c95SVishal Kulkarni (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 183856b2bdd1SGireesh Nagabhushana 1839*7e6ad469SVishal Kulkarni struct fw_ri_rdma_write_cmpl_wr { 1840*7e6ad469SVishal Kulkarni __u8 opcode; 1841*7e6ad469SVishal Kulkarni __u8 flags; 1842*7e6ad469SVishal Kulkarni __u16 wrid; 1843*7e6ad469SVishal Kulkarni __u8 r1[3]; 1844*7e6ad469SVishal Kulkarni __u8 len16; 1845*7e6ad469SVishal Kulkarni __u8 r2; 1846*7e6ad469SVishal Kulkarni __u8 flags_send; 1847*7e6ad469SVishal Kulkarni __u16 wrid_send; 1848*7e6ad469SVishal Kulkarni __be32 stag_inv; 1849*7e6ad469SVishal Kulkarni __be32 plen; 1850*7e6ad469SVishal Kulkarni __be32 stag_sink; 1851*7e6ad469SVishal Kulkarni __be64 to_sink; 1852*7e6ad469SVishal Kulkarni union fw_ri_cmpl { 1853*7e6ad469SVishal Kulkarni struct fw_ri_immd_cmpl { 1854*7e6ad469SVishal Kulkarni __u8 op; 1855*7e6ad469SVishal Kulkarni __u8 r1[6]; 1856*7e6ad469SVishal Kulkarni __u8 immdlen; 1857*7e6ad469SVishal Kulkarni __u8 data[16]; 1858*7e6ad469SVishal Kulkarni } immd_src; 1859*7e6ad469SVishal Kulkarni struct fw_ri_isgl isgl_src; 1860*7e6ad469SVishal Kulkarni } u_cmpl; 1861*7e6ad469SVishal Kulkarni __be64 r3; 1862*7e6ad469SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 1863*7e6ad469SVishal Kulkarni union fw_ri_write { 1864*7e6ad469SVishal Kulkarni struct fw_ri_immd immd_src[0]; 1865*7e6ad469SVishal Kulkarni struct fw_ri_isgl isgl_src[0]; 1866*7e6ad469SVishal Kulkarni } u; 1867*7e6ad469SVishal Kulkarni #endif 1868*7e6ad469SVishal Kulkarni }; 1869*7e6ad469SVishal Kulkarni 187056b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_read_wr { 187156b2bdd1SGireesh Nagabhushana __u8 opcode; 187256b2bdd1SGireesh Nagabhushana __u8 flags; 187356b2bdd1SGireesh Nagabhushana __u16 wrid; 187456b2bdd1SGireesh Nagabhushana __u8 r1[3]; 187556b2bdd1SGireesh Nagabhushana __u8 len16; 187656b2bdd1SGireesh Nagabhushana __be64 r2; 187756b2bdd1SGireesh Nagabhushana __be32 stag_sink; 187856b2bdd1SGireesh Nagabhushana __be32 to_sink_hi; 187956b2bdd1SGireesh Nagabhushana __be32 to_sink_lo; 188056b2bdd1SGireesh Nagabhushana __be32 plen; 188156b2bdd1SGireesh Nagabhushana __be32 stag_src; 188256b2bdd1SGireesh Nagabhushana __be32 to_src_hi; 188356b2bdd1SGireesh Nagabhushana __be32 to_src_lo; 188456b2bdd1SGireesh Nagabhushana __be32 r5; 188556b2bdd1SGireesh Nagabhushana }; 188656b2bdd1SGireesh Nagabhushana 188756b2bdd1SGireesh Nagabhushana struct fw_ri_recv_wr { 188856b2bdd1SGireesh Nagabhushana __u8 opcode; 188956b2bdd1SGireesh Nagabhushana __u8 r1; 189056b2bdd1SGireesh Nagabhushana __u16 wrid; 189156b2bdd1SGireesh Nagabhushana __u8 r2[3]; 189256b2bdd1SGireesh Nagabhushana __u8 len16; 18933dde7c95SVishal Kulkarni struct fw_ri_isgl isgl; 189456b2bdd1SGireesh Nagabhushana }; 189556b2bdd1SGireesh Nagabhushana 189656b2bdd1SGireesh Nagabhushana struct fw_ri_bind_mw_wr { 189756b2bdd1SGireesh Nagabhushana __u8 opcode; 189856b2bdd1SGireesh Nagabhushana __u8 flags; 189956b2bdd1SGireesh Nagabhushana __u16 wrid; 190056b2bdd1SGireesh Nagabhushana __u8 r1[3]; 190156b2bdd1SGireesh Nagabhushana __u8 len16; 190256b2bdd1SGireesh Nagabhushana __u8 qpbinde_to_dcacpu; 190356b2bdd1SGireesh Nagabhushana __u8 pgsz_shift; 190456b2bdd1SGireesh Nagabhushana __u8 addr_type; 190556b2bdd1SGireesh Nagabhushana __u8 mem_perms; 190656b2bdd1SGireesh Nagabhushana __be32 stag_mr; 190756b2bdd1SGireesh Nagabhushana __be32 stag_mw; 190856b2bdd1SGireesh Nagabhushana __be32 r3; 190956b2bdd1SGireesh Nagabhushana __be64 len_mw; 191056b2bdd1SGireesh Nagabhushana __be64 va_fbo; 191156b2bdd1SGireesh Nagabhushana __be64 r4; 191256b2bdd1SGireesh Nagabhushana }; 191356b2bdd1SGireesh Nagabhushana 19143dde7c95SVishal Kulkarni #define S_FW_RI_BIND_MW_WR_QPBINDE 6 19153dde7c95SVishal Kulkarni #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 19163dde7c95SVishal Kulkarni #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 19173dde7c95SVishal Kulkarni #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 19183dde7c95SVishal Kulkarni (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 19193dde7c95SVishal Kulkarni #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 192056b2bdd1SGireesh Nagabhushana 19213dde7c95SVishal Kulkarni #define S_FW_RI_BIND_MW_WR_NS 5 19223dde7c95SVishal Kulkarni #define M_FW_RI_BIND_MW_WR_NS 0x1 19233dde7c95SVishal Kulkarni #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 19243dde7c95SVishal Kulkarni #define G_FW_RI_BIND_MW_WR_NS(x) \ 19253dde7c95SVishal Kulkarni (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 19263dde7c95SVishal Kulkarni #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 192756b2bdd1SGireesh Nagabhushana 19283dde7c95SVishal Kulkarni #define S_FW_RI_BIND_MW_WR_DCACPU 0 19293dde7c95SVishal Kulkarni #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 19303dde7c95SVishal Kulkarni #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 19313dde7c95SVishal Kulkarni #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 19323dde7c95SVishal Kulkarni (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 193356b2bdd1SGireesh Nagabhushana 193456b2bdd1SGireesh Nagabhushana struct fw_ri_fr_nsmr_wr { 193556b2bdd1SGireesh Nagabhushana __u8 opcode; 193656b2bdd1SGireesh Nagabhushana __u8 flags; 193756b2bdd1SGireesh Nagabhushana __u16 wrid; 193856b2bdd1SGireesh Nagabhushana __u8 r1[3]; 193956b2bdd1SGireesh Nagabhushana __u8 len16; 194056b2bdd1SGireesh Nagabhushana __u8 qpbinde_to_dcacpu; 194156b2bdd1SGireesh Nagabhushana __u8 pgsz_shift; 194256b2bdd1SGireesh Nagabhushana __u8 addr_type; 194356b2bdd1SGireesh Nagabhushana __u8 mem_perms; 194456b2bdd1SGireesh Nagabhushana __be32 stag; 194556b2bdd1SGireesh Nagabhushana __be32 len_hi; 194656b2bdd1SGireesh Nagabhushana __be32 len_lo; 194756b2bdd1SGireesh Nagabhushana __be32 va_hi; 194856b2bdd1SGireesh Nagabhushana __be32 va_lo_fbo; 194956b2bdd1SGireesh Nagabhushana }; 195056b2bdd1SGireesh Nagabhushana 19513dde7c95SVishal Kulkarni #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 19523dde7c95SVishal Kulkarni #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 19533dde7c95SVishal Kulkarni #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 19543dde7c95SVishal Kulkarni #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 19553dde7c95SVishal Kulkarni (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 19563dde7c95SVishal Kulkarni #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 19573dde7c95SVishal Kulkarni 19583dde7c95SVishal Kulkarni #define S_FW_RI_FR_NSMR_WR_NS 5 19593dde7c95SVishal Kulkarni #define M_FW_RI_FR_NSMR_WR_NS 0x1 19603dde7c95SVishal Kulkarni #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 19613dde7c95SVishal Kulkarni #define G_FW_RI_FR_NSMR_WR_NS(x) \ 19623dde7c95SVishal Kulkarni (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 19633dde7c95SVishal Kulkarni #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 196456b2bdd1SGireesh Nagabhushana 19653dde7c95SVishal Kulkarni #define S_FW_RI_FR_NSMR_WR_DCACPU 0 19663dde7c95SVishal Kulkarni #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 19673dde7c95SVishal Kulkarni #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 19683dde7c95SVishal Kulkarni #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 19693dde7c95SVishal Kulkarni (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 197056b2bdd1SGireesh Nagabhushana 19713dde7c95SVishal Kulkarni struct fw_ri_fr_nsmr_tpte_wr { 19723dde7c95SVishal Kulkarni __u8 opcode; 19733dde7c95SVishal Kulkarni __u8 flags; 19743dde7c95SVishal Kulkarni __u16 wrid; 19753dde7c95SVishal Kulkarni __u8 r1[3]; 19763dde7c95SVishal Kulkarni __u8 len16; 19773dde7c95SVishal Kulkarni __be32 r2; 19783dde7c95SVishal Kulkarni __be32 stag; 19793dde7c95SVishal Kulkarni struct fw_ri_tpte tpte; 19803dde7c95SVishal Kulkarni __be64 pbl[2]; 19813dde7c95SVishal Kulkarni }; 198256b2bdd1SGireesh Nagabhushana 198356b2bdd1SGireesh Nagabhushana struct fw_ri_inv_lstag_wr { 198456b2bdd1SGireesh Nagabhushana __u8 opcode; 198556b2bdd1SGireesh Nagabhushana __u8 flags; 198656b2bdd1SGireesh Nagabhushana __u16 wrid; 198756b2bdd1SGireesh Nagabhushana __u8 r1[3]; 198856b2bdd1SGireesh Nagabhushana __u8 len16; 198956b2bdd1SGireesh Nagabhushana __be32 r2; 199056b2bdd1SGireesh Nagabhushana __be32 stag_inv; 199156b2bdd1SGireesh Nagabhushana }; 199256b2bdd1SGireesh Nagabhushana 199356b2bdd1SGireesh Nagabhushana struct fw_ri_send_immediate_wr { 199456b2bdd1SGireesh Nagabhushana __u8 opcode; 199556b2bdd1SGireesh Nagabhushana __u8 flags; 199656b2bdd1SGireesh Nagabhushana __u16 wrid; 199756b2bdd1SGireesh Nagabhushana __u8 r1[3]; 199856b2bdd1SGireesh Nagabhushana __u8 len16; 199956b2bdd1SGireesh Nagabhushana __be32 sendimmop_pkd; 200056b2bdd1SGireesh Nagabhushana __be32 r3; 200156b2bdd1SGireesh Nagabhushana __be32 plen; 200256b2bdd1SGireesh Nagabhushana __be32 r4; 200356b2bdd1SGireesh Nagabhushana __be64 r5; 20043dde7c95SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 20053dde7c95SVishal Kulkarni struct fw_ri_immd immd_src[0]; 20063dde7c95SVishal Kulkarni #endif 200756b2bdd1SGireesh Nagabhushana }; 200856b2bdd1SGireesh Nagabhushana 20093dde7c95SVishal Kulkarni #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 20103dde7c95SVishal Kulkarni #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 20113dde7c95SVishal Kulkarni #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 20123dde7c95SVishal Kulkarni ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 20133dde7c95SVishal Kulkarni #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 20143dde7c95SVishal Kulkarni (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 20153dde7c95SVishal Kulkarni M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 201656b2bdd1SGireesh Nagabhushana 201756b2bdd1SGireesh Nagabhushana enum fw_ri_atomic_op { 201856b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_FETCHADD, 201956b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_SWAP, 202056b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_CMDSWAP, 202156b2bdd1SGireesh Nagabhushana }; 202256b2bdd1SGireesh Nagabhushana 202356b2bdd1SGireesh Nagabhushana struct fw_ri_atomic_wr { 202456b2bdd1SGireesh Nagabhushana __u8 opcode; 202556b2bdd1SGireesh Nagabhushana __u8 flags; 202656b2bdd1SGireesh Nagabhushana __u16 wrid; 202756b2bdd1SGireesh Nagabhushana __u8 r1[3]; 202856b2bdd1SGireesh Nagabhushana __u8 len16; 202956b2bdd1SGireesh Nagabhushana __be32 atomicop_pkd; 203056b2bdd1SGireesh Nagabhushana __be64 r3; 203156b2bdd1SGireesh Nagabhushana __be32 aopcode_pkd; 203256b2bdd1SGireesh Nagabhushana __be32 reqid; 203356b2bdd1SGireesh Nagabhushana __be32 stag; 203456b2bdd1SGireesh Nagabhushana __be32 to_hi; 203556b2bdd1SGireesh Nagabhushana __be32 to_lo; 203656b2bdd1SGireesh Nagabhushana __be32 addswap_data_hi; 203756b2bdd1SGireesh Nagabhushana __be32 addswap_data_lo; 203856b2bdd1SGireesh Nagabhushana __be32 addswap_mask_hi; 203956b2bdd1SGireesh Nagabhushana __be32 addswap_mask_lo; 204056b2bdd1SGireesh Nagabhushana __be32 compare_data_hi; 204156b2bdd1SGireesh Nagabhushana __be32 compare_data_lo; 204256b2bdd1SGireesh Nagabhushana __be32 compare_mask_hi; 204356b2bdd1SGireesh Nagabhushana __be32 compare_mask_lo; 204456b2bdd1SGireesh Nagabhushana __be32 r5; 204556b2bdd1SGireesh Nagabhushana }; 204656b2bdd1SGireesh Nagabhushana 20473dde7c95SVishal Kulkarni #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 20483dde7c95SVishal Kulkarni #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 20493dde7c95SVishal Kulkarni #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 20503dde7c95SVishal Kulkarni #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 20513dde7c95SVishal Kulkarni (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 205256b2bdd1SGireesh Nagabhushana 20533dde7c95SVishal Kulkarni #define S_FW_RI_ATOMIC_WR_AOPCODE 0 20543dde7c95SVishal Kulkarni #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 20553dde7c95SVishal Kulkarni #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 20563dde7c95SVishal Kulkarni #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 20573dde7c95SVishal Kulkarni (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 205856b2bdd1SGireesh Nagabhushana 205956b2bdd1SGireesh Nagabhushana enum fw_ri_type { 206056b2bdd1SGireesh Nagabhushana FW_RI_TYPE_INIT, 206156b2bdd1SGireesh Nagabhushana FW_RI_TYPE_FINI, 206256b2bdd1SGireesh Nagabhushana FW_RI_TYPE_TERMINATE 206356b2bdd1SGireesh Nagabhushana }; 206456b2bdd1SGireesh Nagabhushana 206556b2bdd1SGireesh Nagabhushana enum fw_ri_init_p2ptype { 206656b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 206756b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 206856b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 206956b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 207056b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 207156b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 207256b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 207356b2bdd1SGireesh Nagabhushana }; 207456b2bdd1SGireesh Nagabhushana 20753dde7c95SVishal Kulkarni enum fw_ri_init_rqeqid_srq { 20763dde7c95SVishal Kulkarni FW_RI_INIT_RQEQID_SRQ = 1U << 31, 20773dde7c95SVishal Kulkarni }; 20783dde7c95SVishal Kulkarni 207956b2bdd1SGireesh Nagabhushana struct fw_ri_wr { 208056b2bdd1SGireesh Nagabhushana __be32 op_compl; 208156b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 208256b2bdd1SGireesh Nagabhushana __u64 cookie; 208356b2bdd1SGireesh Nagabhushana union fw_ri { 208456b2bdd1SGireesh Nagabhushana struct fw_ri_init { 208556b2bdd1SGireesh Nagabhushana __u8 type; 208656b2bdd1SGireesh Nagabhushana __u8 mpareqbit_p2ptype; 208756b2bdd1SGireesh Nagabhushana __u8 r4[2]; 208856b2bdd1SGireesh Nagabhushana __u8 mpa_attrs; 208956b2bdd1SGireesh Nagabhushana __u8 qp_caps; 209056b2bdd1SGireesh Nagabhushana __be16 nrqe; 209156b2bdd1SGireesh Nagabhushana __be32 pdid; 209256b2bdd1SGireesh Nagabhushana __be32 qpid; 209356b2bdd1SGireesh Nagabhushana __be32 sq_eqid; 209456b2bdd1SGireesh Nagabhushana __be32 rq_eqid; 209556b2bdd1SGireesh Nagabhushana __be32 scqid; 209656b2bdd1SGireesh Nagabhushana __be32 rcqid; 209756b2bdd1SGireesh Nagabhushana __be32 ord_max; 209856b2bdd1SGireesh Nagabhushana __be32 ird_max; 209956b2bdd1SGireesh Nagabhushana __be32 iss; 210056b2bdd1SGireesh Nagabhushana __be32 irs; 210156b2bdd1SGireesh Nagabhushana __be32 hwrqsize; 210256b2bdd1SGireesh Nagabhushana __be32 hwrqaddr; 210356b2bdd1SGireesh Nagabhushana __be64 r5; 210456b2bdd1SGireesh Nagabhushana union fw_ri_init_p2p { 210556b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_write_wr write; 210656b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_read_wr read; 210756b2bdd1SGireesh Nagabhushana struct fw_ri_send_wr send; 210856b2bdd1SGireesh Nagabhushana } u; 210956b2bdd1SGireesh Nagabhushana } init; 211056b2bdd1SGireesh Nagabhushana struct fw_ri_fini { 211156b2bdd1SGireesh Nagabhushana __u8 type; 211256b2bdd1SGireesh Nagabhushana __u8 r3[7]; 211356b2bdd1SGireesh Nagabhushana __be64 r4; 211456b2bdd1SGireesh Nagabhushana } fini; 211556b2bdd1SGireesh Nagabhushana struct fw_ri_terminate { 211656b2bdd1SGireesh Nagabhushana __u8 type; 211756b2bdd1SGireesh Nagabhushana __u8 r3[3]; 211856b2bdd1SGireesh Nagabhushana __be32 immdlen; 211956b2bdd1SGireesh Nagabhushana __u8 termmsg[40]; 212056b2bdd1SGireesh Nagabhushana } terminate; 212156b2bdd1SGireesh Nagabhushana } u; 212256b2bdd1SGireesh Nagabhushana }; 212356b2bdd1SGireesh Nagabhushana 21243dde7c95SVishal Kulkarni #define S_FW_RI_WR_MPAREQBIT 7 21253dde7c95SVishal Kulkarni #define M_FW_RI_WR_MPAREQBIT 0x1 21263dde7c95SVishal Kulkarni #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 21273dde7c95SVishal Kulkarni #define G_FW_RI_WR_MPAREQBIT(x) \ 21283dde7c95SVishal Kulkarni (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 21293dde7c95SVishal Kulkarni #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 213056b2bdd1SGireesh Nagabhushana 21313dde7c95SVishal Kulkarni #define S_FW_RI_WR_0BRRBIT 6 21323dde7c95SVishal Kulkarni #define M_FW_RI_WR_0BRRBIT 0x1 21333dde7c95SVishal Kulkarni #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 21343dde7c95SVishal Kulkarni #define G_FW_RI_WR_0BRRBIT(x) \ 21353dde7c95SVishal Kulkarni (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 21363dde7c95SVishal Kulkarni #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 213756b2bdd1SGireesh Nagabhushana 21383dde7c95SVishal Kulkarni #define S_FW_RI_WR_P2PTYPE 0 21393dde7c95SVishal Kulkarni #define M_FW_RI_WR_P2PTYPE 0xf 21403dde7c95SVishal Kulkarni #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 21413dde7c95SVishal Kulkarni #define G_FW_RI_WR_P2PTYPE(x) \ 21423dde7c95SVishal Kulkarni (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 214356b2bdd1SGireesh Nagabhushana 21443dde7c95SVishal Kulkarni /****************************************************************************** 21453dde7c95SVishal Kulkarni * F O i S C S I W O R K R E Q U E S T s 21463dde7c95SVishal Kulkarni *********************************************/ 214756b2bdd1SGireesh Nagabhushana 214856b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_NAME_MAX_LEN 224 214956b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_ALIAS_MAX_LEN 224 21503dde7c95SVishal Kulkarni #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 215156b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_INIT_NODE_MAX 8 215256b2bdd1SGireesh Nagabhushana 215356b2bdd1SGireesh Nagabhushana enum fw_chnet_ifconf_wr_subop { 215456b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 215556b2bdd1SGireesh Nagabhushana 215656b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 215756b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 215856b2bdd1SGireesh Nagabhushana 215956b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 216056b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 216156b2bdd1SGireesh Nagabhushana 216256b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 216356b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 216456b2bdd1SGireesh Nagabhushana 216556b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 216656b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 216756b2bdd1SGireesh Nagabhushana 216856b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 216956b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 217056b2bdd1SGireesh Nagabhushana 217156b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 217256b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 217356b2bdd1SGireesh Nagabhushana 21743dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 21753dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 21763dde7c95SVishal Kulkarni 21773dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 21783dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 21793dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 21803dde7c95SVishal Kulkarni 218156b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MAX, 218256b2bdd1SGireesh Nagabhushana }; 218356b2bdd1SGireesh Nagabhushana 218456b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_wr { 218556b2bdd1SGireesh Nagabhushana __be32 op_compl; 218656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 218756b2bdd1SGireesh Nagabhushana __be64 cookie; 218856b2bdd1SGireesh Nagabhushana __be32 if_flowid; 218956b2bdd1SGireesh Nagabhushana __u8 idx; 219056b2bdd1SGireesh Nagabhushana __u8 subop; 219156b2bdd1SGireesh Nagabhushana __u8 retval; 219256b2bdd1SGireesh Nagabhushana __u8 r2; 219356b2bdd1SGireesh Nagabhushana __be64 r3; 219456b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_params { 219556b2bdd1SGireesh Nagabhushana __be32 r0; 219656b2bdd1SGireesh Nagabhushana __be16 vlanid; 219756b2bdd1SGireesh Nagabhushana __be16 mtu; 219856b2bdd1SGireesh Nagabhushana union fw_chnet_ifconf_addr_type { 219956b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_ipv4 { 220056b2bdd1SGireesh Nagabhushana __be32 addr; 220156b2bdd1SGireesh Nagabhushana __be32 mask; 220256b2bdd1SGireesh Nagabhushana __be32 router; 220356b2bdd1SGireesh Nagabhushana __be32 r0; 220456b2bdd1SGireesh Nagabhushana __be64 r1; 220556b2bdd1SGireesh Nagabhushana } ipv4; 220656b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_ipv6 { 22073dde7c95SVishal Kulkarni __u8 prefix_len; 22083dde7c95SVishal Kulkarni __u8 r0; 22093dde7c95SVishal Kulkarni __be16 r1; 22103dde7c95SVishal Kulkarni __be32 r2; 22113dde7c95SVishal Kulkarni __be64 addr_hi; 22123dde7c95SVishal Kulkarni __be64 addr_lo; 221356b2bdd1SGireesh Nagabhushana __be64 router_hi; 221456b2bdd1SGireesh Nagabhushana __be64 router_lo; 221556b2bdd1SGireesh Nagabhushana } ipv6; 221656b2bdd1SGireesh Nagabhushana } in_attr; 221756b2bdd1SGireesh Nagabhushana } param; 221856b2bdd1SGireesh Nagabhushana }; 221956b2bdd1SGireesh Nagabhushana 2220de483253SVishal Kulkarni enum fw_foiscsi_node_type { 2221de483253SVishal Kulkarni FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2222de483253SVishal Kulkarni FW_FOISCSI_NODE_TYPE_TARGET, 2223de483253SVishal Kulkarni }; 2224de483253SVishal Kulkarni 222556b2bdd1SGireesh Nagabhushana enum fw_foiscsi_session_type { 222656b2bdd1SGireesh Nagabhushana FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 222756b2bdd1SGireesh Nagabhushana FW_FOISCSI_SESSION_TYPE_NORMAL, 222856b2bdd1SGireesh Nagabhushana }; 222956b2bdd1SGireesh Nagabhushana 223056b2bdd1SGireesh Nagabhushana enum fw_foiscsi_auth_policy { 223156b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 223256b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_POLICY_MUTUAL, 223356b2bdd1SGireesh Nagabhushana }; 223456b2bdd1SGireesh Nagabhushana 223556b2bdd1SGireesh Nagabhushana enum fw_foiscsi_auth_method { 223656b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_NONE = 0, 223756b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP, 223856b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP_FST, 223956b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 224056b2bdd1SGireesh Nagabhushana }; 224156b2bdd1SGireesh Nagabhushana 224256b2bdd1SGireesh Nagabhushana enum fw_foiscsi_digest_type { 224356b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_NONE = 0, 224456b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32, 224556b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 224656b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 224756b2bdd1SGireesh Nagabhushana }; 224856b2bdd1SGireesh Nagabhushana 224956b2bdd1SGireesh Nagabhushana enum fw_foiscsi_wr_subop { 225056b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_ADD = 1, 225156b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_DEL = 2, 225256b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_MOD = 4, 225356b2bdd1SGireesh Nagabhushana }; 225456b2bdd1SGireesh Nagabhushana 225556b2bdd1SGireesh Nagabhushana enum fw_foiscsi_ctrl_state { 225656b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_FREE = 0, 225756b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_ONLINE = 1, 225856b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_FAILED, 225956b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 226056b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_REDIRECT, 226156b2bdd1SGireesh Nagabhushana }; 226256b2bdd1SGireesh Nagabhushana 226356b2bdd1SGireesh Nagabhushana struct fw_rdev_wr { 226456b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 226556b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 226656b2bdd1SGireesh Nagabhushana __be64 cookie; 226756b2bdd1SGireesh Nagabhushana __u8 protocol; 226856b2bdd1SGireesh Nagabhushana __u8 event_cause; 226956b2bdd1SGireesh Nagabhushana __u8 cur_state; 227056b2bdd1SGireesh Nagabhushana __u8 prev_state; 227156b2bdd1SGireesh Nagabhushana __be32 flags_to_assoc_flowid; 227256b2bdd1SGireesh Nagabhushana union rdev_entry { 227356b2bdd1SGireesh Nagabhushana struct fcoe_rdev_entry { 227456b2bdd1SGireesh Nagabhushana __be32 flowid; 227556b2bdd1SGireesh Nagabhushana __u8 protocol; 227656b2bdd1SGireesh Nagabhushana __u8 event_cause; 227756b2bdd1SGireesh Nagabhushana __u8 flags; 227856b2bdd1SGireesh Nagabhushana __u8 rjt_reason; 227956b2bdd1SGireesh Nagabhushana __u8 cur_login_st; 228056b2bdd1SGireesh Nagabhushana __u8 prev_login_st; 228156b2bdd1SGireesh Nagabhushana __be16 rcv_fr_sz; 228256b2bdd1SGireesh Nagabhushana __u8 rd_xfer_rdy_to_rport_type; 228356b2bdd1SGireesh Nagabhushana __u8 vft_to_qos; 228456b2bdd1SGireesh Nagabhushana __u8 org_proc_assoc_to_acc_rsp_code; 228556b2bdd1SGireesh Nagabhushana __u8 enh_disc_to_tgt; 228656b2bdd1SGireesh Nagabhushana __u8 wwnn[8]; 228756b2bdd1SGireesh Nagabhushana __u8 wwpn[8]; 228856b2bdd1SGireesh Nagabhushana __be16 iqid; 228956b2bdd1SGireesh Nagabhushana __u8 fc_oui[3]; 229056b2bdd1SGireesh Nagabhushana __u8 r_id[3]; 229156b2bdd1SGireesh Nagabhushana } fcoe_rdev; 229256b2bdd1SGireesh Nagabhushana struct iscsi_rdev_entry { 229356b2bdd1SGireesh Nagabhushana __be32 flowid; 229456b2bdd1SGireesh Nagabhushana __u8 protocol; 229556b2bdd1SGireesh Nagabhushana __u8 event_cause; 229656b2bdd1SGireesh Nagabhushana __u8 flags; 229756b2bdd1SGireesh Nagabhushana __u8 r3; 229856b2bdd1SGireesh Nagabhushana __be16 iscsi_opts; 229956b2bdd1SGireesh Nagabhushana __be16 tcp_opts; 230056b2bdd1SGireesh Nagabhushana __be16 ip_opts; 230156b2bdd1SGireesh Nagabhushana __be16 max_rcv_len; 230256b2bdd1SGireesh Nagabhushana __be16 max_snd_len; 230356b2bdd1SGireesh Nagabhushana __be16 first_brst_len; 230456b2bdd1SGireesh Nagabhushana __be16 max_brst_len; 230556b2bdd1SGireesh Nagabhushana __be16 r4; 230656b2bdd1SGireesh Nagabhushana __be16 def_time2wait; 230756b2bdd1SGireesh Nagabhushana __be16 def_time2ret; 230856b2bdd1SGireesh Nagabhushana __be16 nop_out_intrvl; 230956b2bdd1SGireesh Nagabhushana __be16 non_scsi_to; 231056b2bdd1SGireesh Nagabhushana __be16 isid; 231156b2bdd1SGireesh Nagabhushana __be16 tsid; 231256b2bdd1SGireesh Nagabhushana __be16 port; 231356b2bdd1SGireesh Nagabhushana __be16 tpgt; 231456b2bdd1SGireesh Nagabhushana __u8 r5[6]; 231556b2bdd1SGireesh Nagabhushana __be16 iqid; 231656b2bdd1SGireesh Nagabhushana } iscsi_rdev; 231756b2bdd1SGireesh Nagabhushana } u; 231856b2bdd1SGireesh Nagabhushana }; 231956b2bdd1SGireesh Nagabhushana 23203dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_IMMDLEN 0 23213dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_IMMDLEN 0xff 23223dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 23233dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_IMMDLEN(x) \ 23243dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 23253dde7c95SVishal Kulkarni 23263dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ALLOC 31 23273dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ALLOC 0x1 23283dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 23293dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ALLOC(x) \ 23303dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 23313dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 23323dde7c95SVishal Kulkarni 23333dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FREE 30 23343dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FREE 0x1 23353dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 23363dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FREE(x) \ 23373dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 23383dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 23393dde7c95SVishal Kulkarni 23403dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_MODIFY 29 23413dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_MODIFY 0x1 23423dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 23433dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_MODIFY(x) \ 23443dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 23453dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 23463dde7c95SVishal Kulkarni 23473dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FLOWID 8 23483dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FLOWID 0xfffff 23493dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 23503dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FLOWID(x) \ 23513dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 23523dde7c95SVishal Kulkarni 23533dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_LEN16 0 23543dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_LEN16 0xff 23553dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 23563dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_LEN16(x) \ 23573dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 23583dde7c95SVishal Kulkarni 23593dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FLAGS 24 23603dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FLAGS 0xff 23613dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 23623dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FLAGS(x) \ 23633dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 23643dde7c95SVishal Kulkarni 23653dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_GET_NEXT 20 23663dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_GET_NEXT 0xf 23673dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 23683dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_GET_NEXT(x) \ 23693dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 23703dde7c95SVishal Kulkarni 23713dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ASSOC_FLOWID 0 23723dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 23733dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 23743dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 23753dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 23763dde7c95SVishal Kulkarni 23773dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RJT 7 23783dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RJT 0x1 23793dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 23803dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 23813dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 23823dde7c95SVishal Kulkarni 23833dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_REASON 0 23843dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_REASON 0x7f 23853dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 23863dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_REASON(x) \ 23873dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 23883dde7c95SVishal Kulkarni 23893dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RD_XFER_RDY 7 23903dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 23913dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 23923dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 23933dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 23943dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 23953dde7c95SVishal Kulkarni 23963dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_WR_XFER_RDY 6 23973dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 23983dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 23993dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 24003dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 24013dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 24023dde7c95SVishal Kulkarni 24033dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FC_SP 5 24043dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FC_SP 0x1 24053dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 24063dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FC_SP(x) \ 24073dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 24083dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 24093dde7c95SVishal Kulkarni 24103dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RPORT_TYPE 0 24113dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 24123dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 24133dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 24143dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 24153dde7c95SVishal Kulkarni 24163dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_VFT 7 24173dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_VFT 0x1 24183dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 24193dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 24203dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 24213dde7c95SVishal Kulkarni 24223dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_NPIV 6 24233dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_NPIV 0x1 24243dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 24253dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_NPIV(x) \ 24263dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 24273dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 24283dde7c95SVishal Kulkarni 24293dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_CLASS 4 24303dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_CLASS 0x3 24313dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 24323dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_CLASS(x) \ 24333dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 24343dde7c95SVishal Kulkarni 24353dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_SEQ_DEL 3 24363dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_SEQ_DEL 0x1 24373dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 24383dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_SEQ_DEL(x) \ 24393dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 24403dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 24413dde7c95SVishal Kulkarni 24423dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_PRIO_PREEMP 2 24433dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 24443dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 24453dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 24463dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 24473dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 24483dde7c95SVishal Kulkarni 24493dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_PREF 1 24503dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_PREF 0x1 24513dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 24523dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_PREF(x) \ 24533dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 24543dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 24553dde7c95SVishal Kulkarni 24563dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_QOS 0 24573dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_QOS 0x1 24583dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 24593dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 24603dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 24613dde7c95SVishal Kulkarni 24623dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 24633dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 24643dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 24653dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 24663dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 24673dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 24683dde7c95SVishal Kulkarni 24693dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 24703dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 24713dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 24723dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 24733dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 24743dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 24753dde7c95SVishal Kulkarni 24763dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_IMAGE_PAIR 5 24773dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 24783dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 24793dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 24803dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 24813dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 24823dde7c95SVishal Kulkarni 24833dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ACC_RSP_CODE 0 24843dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 24853dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 24863dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 24873dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 24883dde7c95SVishal Kulkarni 24893dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ENH_DISC 7 24903dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ENH_DISC 0x1 24913dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 24923dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ENH_DISC(x) \ 24933dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 24943dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 24953dde7c95SVishal Kulkarni 24963dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_REC 6 24973dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_REC 0x1 24983dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 24993dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 25003dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 25013dde7c95SVishal Kulkarni 25023dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_TASK_RETRY_ID 5 25033dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 25043dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 25053dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 25063dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 25073dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 25083dde7c95SVishal Kulkarni 25093dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RETRY 4 25103dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RETRY 0x1 25113dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 25123dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RETRY(x) \ 25133dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 25143dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 25153dde7c95SVishal Kulkarni 25163dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_CONF_CMPL 3 25173dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_CONF_CMPL 0x1 25183dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 25193dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_CONF_CMPL(x) \ 25203dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 25213dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 25223dde7c95SVishal Kulkarni 25233dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_DATA_OVLY 2 25243dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_DATA_OVLY 0x1 25253dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 25263dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_DATA_OVLY(x) \ 25273dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 25283dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 25293dde7c95SVishal Kulkarni 25303dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_INI 1 25313dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_INI 0x1 25323dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 25333dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 25343dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 25353dde7c95SVishal Kulkarni 25363dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_TGT 0 25373dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_TGT 0x1 25383dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 25393dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 25403dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 254156b2bdd1SGireesh Nagabhushana 254256b2bdd1SGireesh Nagabhushana struct fw_foiscsi_node_wr { 254356b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 254456b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 254556b2bdd1SGireesh Nagabhushana __u64 cookie; 254656b2bdd1SGireesh Nagabhushana __u8 subop; 254756b2bdd1SGireesh Nagabhushana __u8 status; 254856b2bdd1SGireesh Nagabhushana __u8 alias_len; 254956b2bdd1SGireesh Nagabhushana __u8 iqn_len; 255056b2bdd1SGireesh Nagabhushana __be32 node_flowid; 255156b2bdd1SGireesh Nagabhushana __be16 nodeid; 255256b2bdd1SGireesh Nagabhushana __be16 login_retry; 255356b2bdd1SGireesh Nagabhushana __be16 retry_timeout; 255456b2bdd1SGireesh Nagabhushana __be16 r3; 255556b2bdd1SGireesh Nagabhushana __u8 iqn[224]; 255656b2bdd1SGireesh Nagabhushana __u8 alias[224]; 255756b2bdd1SGireesh Nagabhushana }; 255856b2bdd1SGireesh Nagabhushana 25593dde7c95SVishal Kulkarni #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 25603dde7c95SVishal Kulkarni #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 25613dde7c95SVishal Kulkarni #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 25623dde7c95SVishal Kulkarni #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 25633dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 256456b2bdd1SGireesh Nagabhushana 256556b2bdd1SGireesh Nagabhushana struct fw_foiscsi_ctrl_wr { 256656b2bdd1SGireesh Nagabhushana __be32 op_compl; 256756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 256856b2bdd1SGireesh Nagabhushana __u64 cookie; 256956b2bdd1SGireesh Nagabhushana __u8 subop; 257056b2bdd1SGireesh Nagabhushana __u8 status; 257156b2bdd1SGireesh Nagabhushana __u8 ctrl_state; 257256b2bdd1SGireesh Nagabhushana __u8 io_state; 257356b2bdd1SGireesh Nagabhushana __be32 node_id; 257456b2bdd1SGireesh Nagabhushana __be32 ctrl_id; 257556b2bdd1SGireesh Nagabhushana __be32 io_id; 257656b2bdd1SGireesh Nagabhushana struct fw_foiscsi_sess_attr { 257756b2bdd1SGireesh Nagabhushana __be32 sess_type_to_erl; 257856b2bdd1SGireesh Nagabhushana __be16 max_conn; 257956b2bdd1SGireesh Nagabhushana __be16 max_r2t; 258056b2bdd1SGireesh Nagabhushana __be16 time2wait; 258156b2bdd1SGireesh Nagabhushana __be16 time2retain; 258256b2bdd1SGireesh Nagabhushana __be32 max_burst; 258356b2bdd1SGireesh Nagabhushana __be32 first_burst; 258456b2bdd1SGireesh Nagabhushana __be32 r1; 258556b2bdd1SGireesh Nagabhushana } sess_attr; 258656b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr { 2587de483253SVishal Kulkarni __be32 hdigest_to_ddp_pgsz; 258856b2bdd1SGireesh Nagabhushana __be32 max_rcv_dsl; 258956b2bdd1SGireesh Nagabhushana __be32 ping_tmo; 259056b2bdd1SGireesh Nagabhushana __be16 dst_port; 259156b2bdd1SGireesh Nagabhushana __be16 src_port; 259256b2bdd1SGireesh Nagabhushana union fw_foiscsi_conn_attr_addr { 259356b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr_ipv6 { 259456b2bdd1SGireesh Nagabhushana __be64 dst_addr[2]; 259556b2bdd1SGireesh Nagabhushana __be64 src_addr[2]; 259656b2bdd1SGireesh Nagabhushana } ipv6_addr; 259756b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr_ipv4 { 259856b2bdd1SGireesh Nagabhushana __be32 dst_addr; 259956b2bdd1SGireesh Nagabhushana __be32 src_addr; 260056b2bdd1SGireesh Nagabhushana } ipv4_addr; 260156b2bdd1SGireesh Nagabhushana } u; 260256b2bdd1SGireesh Nagabhushana } conn_attr; 260356b2bdd1SGireesh Nagabhushana __u8 tgt_name_len; 260456b2bdd1SGireesh Nagabhushana __u8 r3[7]; 2605de483253SVishal Kulkarni __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 260656b2bdd1SGireesh Nagabhushana }; 260756b2bdd1SGireesh Nagabhushana 26083dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 26093dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 26103dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 26113dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 26123dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 26133dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 26143dde7c95SVishal Kulkarni 26153dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 26163dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 26173dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 26183dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 26193dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 26203dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 26213dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 26223dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 262356b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 262456b2bdd1SGireesh Nagabhushana 26253dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 26263dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 26273dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 26283dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 26293dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 26303dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 26313dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 26323dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 263356b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 263456b2bdd1SGireesh Nagabhushana 26353dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 26363dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 26373dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 26383dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 26393dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 26403dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 26413dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 26423dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 264356b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 264456b2bdd1SGireesh Nagabhushana 26453dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 26463dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 26473dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 26483dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 26493dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 26503dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 26513dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 26523dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 265356b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 265456b2bdd1SGireesh Nagabhushana 26553dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_ERL 24 26563dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 26573dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 26583dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 26593dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 26603dde7c95SVishal Kulkarni 26613dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 26623dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 26633dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 26643dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 26653dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 26663dde7c95SVishal Kulkarni 26673dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 26683dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 26693dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 26703dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 26713dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 26723dde7c95SVishal Kulkarni 26733dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 26743dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 26753dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 26763dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 26773dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 26783dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 26793dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 26803dde7c95SVishal Kulkarni 26813dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 26823dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 26833dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 26843dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 26853dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 26863dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 26873dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 268856b2bdd1SGireesh Nagabhushana 2689de483253SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2690de483253SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2691de483253SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2692de483253SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2693de483253SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2694de483253SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2695de483253SVishal Kulkarni 26963dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_IPV6 20 26973dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 26983dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 26993dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 27003dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 27013dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 27023dde7c95SVishal Kulkarni 270356b2bdd1SGireesh Nagabhushana struct fw_foiscsi_chap_wr { 270456b2bdd1SGireesh Nagabhushana __be32 op_compl; 270556b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 270656b2bdd1SGireesh Nagabhushana __u64 cookie; 270756b2bdd1SGireesh Nagabhushana __u8 status; 270856b2bdd1SGireesh Nagabhushana __u8 id_len; 270956b2bdd1SGireesh Nagabhushana __u8 sec_len; 2710de483253SVishal Kulkarni __u8 node_type; 271156b2bdd1SGireesh Nagabhushana __be16 node_id; 2712de483253SVishal Kulkarni __u8 r3[2]; 2713de483253SVishal Kulkarni __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2714de483253SVishal Kulkarni __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 271556b2bdd1SGireesh Nagabhushana }; 271656b2bdd1SGireesh Nagabhushana 27173dde7c95SVishal Kulkarni /****************************************************************************** 27183dde7c95SVishal Kulkarni * C O i S C S I W O R K R E Q U E S T S 27193dde7c95SVishal Kulkarni ********************************************/ 27203dde7c95SVishal Kulkarni 27213dde7c95SVishal Kulkarni enum fw_chnet_addr_type { 27223dde7c95SVishal Kulkarni FW_CHNET_ADDD_TYPE_NONE = 0, 27233dde7c95SVishal Kulkarni FW_CHNET_ADDR_TYPE_IPV4, 27243dde7c95SVishal Kulkarni FW_CHNET_ADDR_TYPE_IPV6, 27253dde7c95SVishal Kulkarni }; 27263dde7c95SVishal Kulkarni 27273dde7c95SVishal Kulkarni enum fw_msg_wr_type { 27283dde7c95SVishal Kulkarni FW_MSG_WR_TYPE_RPL = 0, 27293dde7c95SVishal Kulkarni FW_MSG_WR_TYPE_ERR, 27303dde7c95SVishal Kulkarni FW_MSG_WR_TYPE_PLD, 27313dde7c95SVishal Kulkarni }; 27323dde7c95SVishal Kulkarni 27333dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_wr { 27343dde7c95SVishal Kulkarni __be32 op_compl; 27353dde7c95SVishal Kulkarni __be32 flowid_len16; 27363dde7c95SVishal Kulkarni __u64 cookie; 27373dde7c95SVishal Kulkarni __u8 subop; 27383dde7c95SVishal Kulkarni __u8 status; 27393dde7c95SVishal Kulkarni __be16 r4; 27403dde7c95SVishal Kulkarni __be32 flags; 27413dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_conn_attr { 27423dde7c95SVishal Kulkarni __be32 in_tid; 27433dde7c95SVishal Kulkarni __be16 in_port; 27443dde7c95SVishal Kulkarni __u8 in_type; 27453dde7c95SVishal Kulkarni __u8 r6; 27463dde7c95SVishal Kulkarni union fw_coiscsi_tgt_conn_attr_addr { 27473dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_conn_attr_in_addr { 27483dde7c95SVishal Kulkarni __be32 addr; 27493dde7c95SVishal Kulkarni __be32 r7; 27503dde7c95SVishal Kulkarni __be32 r8[2]; 27513dde7c95SVishal Kulkarni } in_addr; 27523dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_conn_attr_in_addr6 { 27533dde7c95SVishal Kulkarni __be64 addr[2]; 27543dde7c95SVishal Kulkarni } in_addr6; 27553dde7c95SVishal Kulkarni } u; 27563dde7c95SVishal Kulkarni } conn_attr; 27573dde7c95SVishal Kulkarni }; 27583dde7c95SVishal Kulkarni 27593dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_xmit_wr { 27603dde7c95SVishal Kulkarni __be32 op_to_immdlen; 27613dde7c95SVishal Kulkarni __be32 flowid_len16; 27623dde7c95SVishal Kulkarni __be64 cookie; 27633dde7c95SVishal Kulkarni __be16 iq_id; 27643dde7c95SVishal Kulkarni __be16 r4; 27653dde7c95SVishal Kulkarni __be32 datasn; 27663dde7c95SVishal Kulkarni __be32 t_xfer_len; 27673dde7c95SVishal Kulkarni __be32 flags; 27683dde7c95SVishal Kulkarni __be32 tag; 27693dde7c95SVishal Kulkarni __be32 tidx; 27703dde7c95SVishal Kulkarni __be32 r5[2]; 27713dde7c95SVishal Kulkarni }; 27723dde7c95SVishal Kulkarni 27733dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 27743dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 27753dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 27763dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 27773dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 27783dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 27793dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 27803dde7c95SVishal Kulkarni 27813dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 27823dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 27833dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 27843dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 27853dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 27863dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 27873dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 27883dde7c95SVishal Kulkarni 27893dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 27903dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 27913dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 27923dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 27933dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 27943dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 27953dde7c95SVishal Kulkarni 27963dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 27973dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 27983dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 27993dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 28003dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 28013dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 28023dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 28033dde7c95SVishal Kulkarni 28043dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 28053dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 28063dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 28073dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 28083dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 28093dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 28103dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 28113dde7c95SVishal Kulkarni 28123dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 28133dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 28143dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 28153dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 28163dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 28173dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 28183dde7c95SVishal Kulkarni M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 28193dde7c95SVishal Kulkarni 28203dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 28213dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 28223dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 28233dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 28243dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 28253dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 28263dde7c95SVishal Kulkarni M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 28273dde7c95SVishal Kulkarni 28283dde7c95SVishal Kulkarni struct fw_isns_wr { 28293dde7c95SVishal Kulkarni __be32 op_compl; 28303dde7c95SVishal Kulkarni __be32 flowid_len16; 28313dde7c95SVishal Kulkarni __u64 cookie; 28323dde7c95SVishal Kulkarni __u8 subop; 28333dde7c95SVishal Kulkarni __u8 status; 28343dde7c95SVishal Kulkarni __be16 iq_id; 28353dde7c95SVishal Kulkarni __be32 r4; 28363dde7c95SVishal Kulkarni struct fw_tcp_conn_attr { 28373dde7c95SVishal Kulkarni __be32 in_tid; 28383dde7c95SVishal Kulkarni __be16 in_port; 28393dde7c95SVishal Kulkarni __u8 in_type; 28403dde7c95SVishal Kulkarni __u8 r6; 28413dde7c95SVishal Kulkarni union fw_tcp_conn_attr_addr { 28423dde7c95SVishal Kulkarni struct fw_tcp_conn_attr_in_addr { 28433dde7c95SVishal Kulkarni __be32 addr; 28443dde7c95SVishal Kulkarni __be32 r7; 28453dde7c95SVishal Kulkarni __be32 r8[2]; 28463dde7c95SVishal Kulkarni } in_addr; 28473dde7c95SVishal Kulkarni struct fw_tcp_conn_attr_in_addr6 { 28483dde7c95SVishal Kulkarni __be64 addr[2]; 28493dde7c95SVishal Kulkarni } in_addr6; 28503dde7c95SVishal Kulkarni } u; 28513dde7c95SVishal Kulkarni } conn_attr; 28523dde7c95SVishal Kulkarni }; 28533dde7c95SVishal Kulkarni 28543dde7c95SVishal Kulkarni struct fw_isns_xmit_wr { 28553dde7c95SVishal Kulkarni __be32 op_to_immdlen; 28563dde7c95SVishal Kulkarni __be32 flowid_len16; 28573dde7c95SVishal Kulkarni __be64 cookie; 28583dde7c95SVishal Kulkarni __be16 iq_id; 28593dde7c95SVishal Kulkarni __be16 r4; 28603dde7c95SVishal Kulkarni __be32 xfer_len; 28613dde7c95SVishal Kulkarni __be64 r5; 28623dde7c95SVishal Kulkarni }; 28633dde7c95SVishal Kulkarni 28643dde7c95SVishal Kulkarni #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 28653dde7c95SVishal Kulkarni #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 28663dde7c95SVishal Kulkarni #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 28673dde7c95SVishal Kulkarni #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 28683dde7c95SVishal Kulkarni (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 28693dde7c95SVishal Kulkarni 28703dde7c95SVishal Kulkarni /****************************************************************************** 28713dde7c95SVishal Kulkarni * F O F C O E W O R K R E Q U E S T s 28723dde7c95SVishal Kulkarni *******************************************/ 287356b2bdd1SGireesh Nagabhushana 287456b2bdd1SGireesh Nagabhushana struct fw_fcoe_els_ct_wr { 287556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 287656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 287756b2bdd1SGireesh Nagabhushana __be64 cookie; 287856b2bdd1SGireesh Nagabhushana __be16 iqid; 287956b2bdd1SGireesh Nagabhushana __u8 tmo_val; 288056b2bdd1SGireesh Nagabhushana __u8 els_ct_type; 288156b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 288256b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 288356b2bdd1SGireesh Nagabhushana __be16 xfer_cnt; 288456b2bdd1SGireesh Nagabhushana __u8 fl_to_sp; 288556b2bdd1SGireesh Nagabhushana __u8 l_id[3]; 288656b2bdd1SGireesh Nagabhushana __u8 r5; 288756b2bdd1SGireesh Nagabhushana __u8 r_id[3]; 288856b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 288956b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 289056b2bdd1SGireesh Nagabhushana __be32 r6; 289156b2bdd1SGireesh Nagabhushana }; 289256b2bdd1SGireesh Nagabhushana 28933dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 28943dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 28953dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 28963dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 28973dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 28983dde7c95SVishal Kulkarni 28993dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 29003dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 29013dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 29023dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 29033dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 29043dde7c95SVishal Kulkarni 29053dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 29063dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 29073dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 29083dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 29093dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 29103dde7c95SVishal Kulkarni 29113dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_LEN16 0 29123dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 29133dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 29143dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 29153dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 29163dde7c95SVishal Kulkarni 29173dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 29183dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 29193dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 29203dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 29213dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 29223dde7c95SVishal Kulkarni 29233dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_CLASS 4 29243dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 29253dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 29263dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 29273dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 29283dde7c95SVishal Kulkarni 29293dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_FL 2 29303dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_FL 0x1 29313dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 29323dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 29333dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 29343dde7c95SVishal Kulkarni #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 29353dde7c95SVishal Kulkarni 29363dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_NPIV 1 29373dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 29383dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 29393dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 29403dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 29413dde7c95SVishal Kulkarni #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 29423dde7c95SVishal Kulkarni 29433dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_SP 0 29443dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_SP 0x1 29453dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 29463dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 29473dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 29483dde7c95SVishal Kulkarni #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 29493dde7c95SVishal Kulkarni 29503dde7c95SVishal Kulkarni /****************************************************************************** 29513dde7c95SVishal Kulkarni * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 29523dde7c95SVishal Kulkarni *****************************************************************************/ 295356b2bdd1SGireesh Nagabhushana 295456b2bdd1SGireesh Nagabhushana struct fw_scsi_write_wr { 295556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 295656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 295756b2bdd1SGireesh Nagabhushana __be64 cookie; 295856b2bdd1SGireesh Nagabhushana __be16 iqid; 295956b2bdd1SGireesh Nagabhushana __u8 tmo_val; 296056b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 296156b2bdd1SGireesh Nagabhushana union fw_scsi_write_priv { 296256b2bdd1SGireesh Nagabhushana struct fcoe_write_priv { 296356b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 296456b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 296556b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 296656b2bdd1SGireesh Nagabhushana } fcoe; 296756b2bdd1SGireesh Nagabhushana struct iscsi_write_priv { 296856b2bdd1SGireesh Nagabhushana __u8 r3[4]; 296956b2bdd1SGireesh Nagabhushana } iscsi; 297056b2bdd1SGireesh Nagabhushana } u; 297156b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 297256b2bdd1SGireesh Nagabhushana __be32 ini_xfer_cnt; 297356b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 297456b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 297556b2bdd1SGireesh Nagabhushana __be32 r4; 297656b2bdd1SGireesh Nagabhushana }; 297756b2bdd1SGireesh Nagabhushana 29783dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_OPCODE 24 29793dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 29803dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 29813dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 29823dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 29833dde7c95SVishal Kulkarni 29843dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 29853dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 29863dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 29873dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 29883dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 29893dde7c95SVishal Kulkarni 29903dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_FLOWID 8 29913dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 29923dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 29933dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 29943dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 29953dde7c95SVishal Kulkarni 29963dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_LEN16 0 29973dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_LEN16 0xff 29983dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 29993dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 30003dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 30013dde7c95SVishal Kulkarni 30023dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_CP_EN 6 30033dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 30043dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 30053dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 30063dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 30073dde7c95SVishal Kulkarni 30083dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_CLASS 4 30093dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_CLASS 0x3 30103dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 30113dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 30123dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 301356b2bdd1SGireesh Nagabhushana 301456b2bdd1SGireesh Nagabhushana struct fw_scsi_read_wr { 301556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 301656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 301756b2bdd1SGireesh Nagabhushana __be64 cookie; 301856b2bdd1SGireesh Nagabhushana __be16 iqid; 301956b2bdd1SGireesh Nagabhushana __u8 tmo_val; 302056b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 302156b2bdd1SGireesh Nagabhushana union fw_scsi_read_priv { 302256b2bdd1SGireesh Nagabhushana struct fcoe_read_priv { 302356b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 302456b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 302556b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 302656b2bdd1SGireesh Nagabhushana } fcoe; 302756b2bdd1SGireesh Nagabhushana struct iscsi_read_priv { 302856b2bdd1SGireesh Nagabhushana __u8 r3[4]; 302956b2bdd1SGireesh Nagabhushana } iscsi; 303056b2bdd1SGireesh Nagabhushana } u; 303156b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 303256b2bdd1SGireesh Nagabhushana __be32 ini_xfer_cnt; 303356b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 303456b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 303556b2bdd1SGireesh Nagabhushana __be32 r4; 303656b2bdd1SGireesh Nagabhushana }; 303756b2bdd1SGireesh Nagabhushana 30383dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_OPCODE 24 30393dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_OPCODE 0xff 30403dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 30413dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_OPCODE(x) \ 30423dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 30433dde7c95SVishal Kulkarni 30443dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_IMMDLEN 0 30453dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 30463dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 30473dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 30483dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 30493dde7c95SVishal Kulkarni 30503dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_FLOWID 8 30513dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 30523dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 30533dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_FLOWID(x) \ 30543dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 30553dde7c95SVishal Kulkarni 30563dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_LEN16 0 30573dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_LEN16 0xff 30583dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 30593dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_LEN16(x) \ 30603dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 30613dde7c95SVishal Kulkarni 30623dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_CP_EN 6 30633dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_CP_EN 0x3 30643dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 30653dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_CP_EN(x) \ 30663dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 30673dde7c95SVishal Kulkarni 30683dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_CLASS 4 30693dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_CLASS 0x3 30703dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 30713dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_CLASS(x) \ 30723dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 307356b2bdd1SGireesh Nagabhushana 307456b2bdd1SGireesh Nagabhushana struct fw_scsi_cmd_wr { 307556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 307656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 307756b2bdd1SGireesh Nagabhushana __be64 cookie; 307856b2bdd1SGireesh Nagabhushana __be16 iqid; 307956b2bdd1SGireesh Nagabhushana __u8 tmo_val; 308056b2bdd1SGireesh Nagabhushana __u8 r3; 308156b2bdd1SGireesh Nagabhushana union fw_scsi_cmd_priv { 308256b2bdd1SGireesh Nagabhushana struct fcoe_cmd_priv { 308356b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 308456b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 308556b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 308656b2bdd1SGireesh Nagabhushana } fcoe; 308756b2bdd1SGireesh Nagabhushana struct iscsi_cmd_priv { 308856b2bdd1SGireesh Nagabhushana __u8 r4[4]; 308956b2bdd1SGireesh Nagabhushana } iscsi; 309056b2bdd1SGireesh Nagabhushana } u; 309156b2bdd1SGireesh Nagabhushana __u8 r5[8]; 309256b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 309356b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 309456b2bdd1SGireesh Nagabhushana __be32 r6; 309556b2bdd1SGireesh Nagabhushana }; 309656b2bdd1SGireesh Nagabhushana 30973dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_OPCODE 24 30983dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_OPCODE 0xff 30993dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 31003dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 31013dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 31023dde7c95SVishal Kulkarni 31033dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_IMMDLEN 0 31043dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 31053dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 31063dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 31073dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 31083dde7c95SVishal Kulkarni 31093dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_FLOWID 8 31103dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 31113dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 31123dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 31133dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 31143dde7c95SVishal Kulkarni 31153dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_LEN16 0 31163dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_LEN16 0xff 31173dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 31183dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_LEN16(x) \ 31193dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 31203dde7c95SVishal Kulkarni 31213dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_CP_EN 6 31223dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_CP_EN 0x3 31233dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 31243dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 31253dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 31263dde7c95SVishal Kulkarni 31273dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_CLASS 4 31283dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_CLASS 0x3 31293dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 31303dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_CLASS(x) \ 31313dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 313256b2bdd1SGireesh Nagabhushana 313356b2bdd1SGireesh Nagabhushana struct fw_scsi_abrt_cls_wr { 313456b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 313556b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 313656b2bdd1SGireesh Nagabhushana __be64 cookie; 313756b2bdd1SGireesh Nagabhushana __be16 iqid; 313856b2bdd1SGireesh Nagabhushana __u8 tmo_val; 313956b2bdd1SGireesh Nagabhushana __u8 sub_opcode_to_chk_all_io; 314056b2bdd1SGireesh Nagabhushana __u8 r3[4]; 314156b2bdd1SGireesh Nagabhushana __be64 t_cookie; 314256b2bdd1SGireesh Nagabhushana }; 314356b2bdd1SGireesh Nagabhushana 31443dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 31453dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 31463dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 31473dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 31483dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 31493dde7c95SVishal Kulkarni 31503dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 31513dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 31523dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 31533dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 31543dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 31553dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 31563dde7c95SVishal Kulkarni 31573dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 31583dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 31593dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 31603dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 31613dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 31623dde7c95SVishal Kulkarni 31633dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 31643dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 31653dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 31663dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 31673dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 31683dde7c95SVishal Kulkarni 31693dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 31703dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 31713dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 31723dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 31733dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 31743dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 31753dde7c95SVishal Kulkarni M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 31763dde7c95SVishal Kulkarni 31773dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 31783dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 31793dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 31803dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 31813dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 31823dde7c95SVishal Kulkarni #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 31833dde7c95SVishal Kulkarni 31843dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 31853dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 31863dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 31873dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 31883dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 31893dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 31903dde7c95SVishal Kulkarni M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 31913dde7c95SVishal Kulkarni #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 319256b2bdd1SGireesh Nagabhushana V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 319356b2bdd1SGireesh Nagabhushana 319456b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_acc_wr { 319556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 319656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 319756b2bdd1SGireesh Nagabhushana __be64 cookie; 319856b2bdd1SGireesh Nagabhushana __be16 iqid; 319956b2bdd1SGireesh Nagabhushana __u8 r3; 320056b2bdd1SGireesh Nagabhushana __u8 use_burst_len; 320156b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_acc_priv { 320256b2bdd1SGireesh Nagabhushana struct fcoe_tgt_acc_priv { 320356b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 320456b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 320556b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 320656b2bdd1SGireesh Nagabhushana } fcoe; 320756b2bdd1SGireesh Nagabhushana struct iscsi_tgt_acc_priv { 320856b2bdd1SGireesh Nagabhushana __u8 r4[4]; 320956b2bdd1SGireesh Nagabhushana } iscsi; 321056b2bdd1SGireesh Nagabhushana } u; 321156b2bdd1SGireesh Nagabhushana __be32 burst_len; 321256b2bdd1SGireesh Nagabhushana __be32 rel_off; 321356b2bdd1SGireesh Nagabhushana __be64 r5; 321456b2bdd1SGireesh Nagabhushana __be32 r6; 321556b2bdd1SGireesh Nagabhushana __be32 tot_xfer_len; 321656b2bdd1SGireesh Nagabhushana }; 321756b2bdd1SGireesh Nagabhushana 32183dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 32193dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 32203dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 32213dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 32223dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 32233dde7c95SVishal Kulkarni 32243dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 32253dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 32263dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 32273dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 32283dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 32293dde7c95SVishal Kulkarni 32303dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 32313dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 32323dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 32333dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 32343dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 32353dde7c95SVishal Kulkarni 32363dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 32373dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 32383dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 32393dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 32403dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 32413dde7c95SVishal Kulkarni 32423dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 32433dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 32443dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 32453dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 32463dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 32473dde7c95SVishal Kulkarni 32483dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 32493dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 32503dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 32513dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 32523dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 325356b2bdd1SGireesh Nagabhushana 325456b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_xmit_wr { 325556b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 325656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 325756b2bdd1SGireesh Nagabhushana __be64 cookie; 325856b2bdd1SGireesh Nagabhushana __be16 iqid; 325956b2bdd1SGireesh Nagabhushana __u8 auto_rsp; 326056b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 326156b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_xmit_priv { 326256b2bdd1SGireesh Nagabhushana struct fcoe_tgt_xmit_priv { 326356b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 326456b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 326556b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 326656b2bdd1SGireesh Nagabhushana } fcoe; 326756b2bdd1SGireesh Nagabhushana struct iscsi_tgt_xmit_priv { 326856b2bdd1SGireesh Nagabhushana __u8 r3[4]; 326956b2bdd1SGireesh Nagabhushana } iscsi; 327056b2bdd1SGireesh Nagabhushana } u; 327156b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 327256b2bdd1SGireesh Nagabhushana __be32 r4; 327356b2bdd1SGireesh Nagabhushana __be64 r5; 327456b2bdd1SGireesh Nagabhushana __be32 r6; 327556b2bdd1SGireesh Nagabhushana __be32 tot_xfer_len; 327656b2bdd1SGireesh Nagabhushana }; 327756b2bdd1SGireesh Nagabhushana 32783dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 32793dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 32803dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 32813dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 32823dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 32833dde7c95SVishal Kulkarni 32843dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 32853dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 32863dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 32873dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 32883dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 32893dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 32903dde7c95SVishal Kulkarni 32913dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 32923dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 32933dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 32943dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 32953dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 32963dde7c95SVishal Kulkarni 32973dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 32983dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 32993dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 33003dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 33013dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 33023dde7c95SVishal Kulkarni 33033dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 33043dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 33053dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 33063dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 33073dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 33083dde7c95SVishal Kulkarni 33093dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 33103dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 33113dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 33123dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 33133dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 331456b2bdd1SGireesh Nagabhushana 331556b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_rsp_wr { 331656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 331756b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 331856b2bdd1SGireesh Nagabhushana __be64 cookie; 331956b2bdd1SGireesh Nagabhushana __be16 iqid; 332056b2bdd1SGireesh Nagabhushana __u8 r3[2]; 332156b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_rsp_priv { 332256b2bdd1SGireesh Nagabhushana struct fcoe_tgt_rsp_priv { 332356b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 332456b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 332556b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 332656b2bdd1SGireesh Nagabhushana } fcoe; 332756b2bdd1SGireesh Nagabhushana struct iscsi_tgt_rsp_priv { 332856b2bdd1SGireesh Nagabhushana __u8 r4[4]; 332956b2bdd1SGireesh Nagabhushana } iscsi; 333056b2bdd1SGireesh Nagabhushana } u; 333156b2bdd1SGireesh Nagabhushana __u8 r5[8]; 333256b2bdd1SGireesh Nagabhushana }; 333356b2bdd1SGireesh Nagabhushana 33343dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 33353dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 33363dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 33373dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 33383dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 33393dde7c95SVishal Kulkarni 33403dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 33413dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 33423dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 33433dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 33443dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 33453dde7c95SVishal Kulkarni 33463dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 33473dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 33483dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 33493dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 33503dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 33513dde7c95SVishal Kulkarni 33523dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 33533dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 33543dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 33553dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 33563dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 33573dde7c95SVishal Kulkarni 33583dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 33593dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 33603dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 33613dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 33623dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 33633dde7c95SVishal Kulkarni 33643dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 33653dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 33663dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 33673dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 33683dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 336956b2bdd1SGireesh Nagabhushana 3370de483253SVishal Kulkarni struct fw_pofcoe_tcb_wr { 3371de483253SVishal Kulkarni __be32 op_compl; 3372de483253SVishal Kulkarni __be32 equiq_to_len16; 33733dde7c95SVishal Kulkarni __be32 r4; 33743dde7c95SVishal Kulkarni __be32 xfer_len; 3375de483253SVishal Kulkarni __be32 tid_to_port; 3376de483253SVishal Kulkarni __be16 x_id; 3377de483253SVishal Kulkarni __be16 vlan_id; 33783dde7c95SVishal Kulkarni __be64 cookie; 3379de483253SVishal Kulkarni __be32 s_id; 3380de483253SVishal Kulkarni __be32 d_id; 3381de483253SVishal Kulkarni __be32 tag; 33823dde7c95SVishal Kulkarni __be16 r6; 3383de483253SVishal Kulkarni __be16 iqid; 3384de483253SVishal Kulkarni }; 3385de483253SVishal Kulkarni 3386de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_TID 12 3387de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3388de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3389de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_TID(x) \ 3390de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3391de483253SVishal Kulkarni 33923dde7c95SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_ALLOC 4 3393de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3394de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3395de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3396de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3397de483253SVishal Kulkarni #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3398de483253SVishal Kulkarni 3399de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_FREE 3 3400de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_FREE 0x1 3401de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3402de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3403de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3404de483253SVishal Kulkarni #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3405de483253SVishal Kulkarni 3406de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_PORT 0 3407de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_PORT 0x7 3408de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3409de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3410de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3411de483253SVishal Kulkarni 3412de483253SVishal Kulkarni struct fw_pofcoe_ulptx_wr { 3413de483253SVishal Kulkarni __be32 op_pkd; 3414de483253SVishal Kulkarni __be32 equiq_to_len16; 3415de483253SVishal Kulkarni __u64 cookie; 3416de483253SVishal Kulkarni }; 3417de483253SVishal Kulkarni 34183dde7c95SVishal Kulkarni /******************************************************************* 34193dde7c95SVishal Kulkarni * T10 DIF related definition 34203dde7c95SVishal Kulkarni *******************************************************************/ 34213dde7c95SVishal Kulkarni struct fw_tx_pi_header { 34223dde7c95SVishal Kulkarni __be16 op_to_inline; 34233dde7c95SVishal Kulkarni __u8 pi_interval_tag_type; 34243dde7c95SVishal Kulkarni __u8 num_pi; 34253dde7c95SVishal Kulkarni __be32 pi_start4_pi_end4; 34263dde7c95SVishal Kulkarni __u8 tag_gen_enabled_pkd; 34273dde7c95SVishal Kulkarni __u8 num_pi_dsg; 34283dde7c95SVishal Kulkarni __be16 app_tag; 34293dde7c95SVishal Kulkarni __be32 ref_tag; 34303dde7c95SVishal Kulkarni }; 34313dde7c95SVishal Kulkarni 34323dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_OP 8 34333dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_OP 0xff 34343dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 34353dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_OP(x) \ 34363dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 34373dde7c95SVishal Kulkarni 34383dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_ULPTXMORE 7 34393dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 34403dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 34413dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 34423dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 34433dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 34443dde7c95SVishal Kulkarni 34453dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_CONTROL 4 34463dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 34473dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 34483dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 34493dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 34503dde7c95SVishal Kulkarni 34513dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 34523dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 34533dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 34543dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 34553dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 34563dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 34573dde7c95SVishal Kulkarni 34583dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_VALIDATE 1 34593dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_VALIDATE 0x1 34603dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 34613dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 34623dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 34633dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 34643dde7c95SVishal Kulkarni 34653dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_INLINE 0 34663dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_INLINE 0x1 34673dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 34683dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_INLINE(x) \ 34693dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 34703dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 34713dde7c95SVishal Kulkarni 34723dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 34733dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 34743dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 34753dde7c95SVishal Kulkarni ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 34763dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 34773dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 34783dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 34793dde7c95SVishal Kulkarni 34803dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_TAG_TYPE 5 34813dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 34823dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 34833dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 34843dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 34853dde7c95SVishal Kulkarni 34863dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_START4 22 34873dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 34883dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 34893dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_START4(x) \ 34903dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 34913dde7c95SVishal Kulkarni 34923dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_END4 0 34933dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 34943dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 34953dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_END4(x) \ 34963dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 34973dde7c95SVishal Kulkarni 34983dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 34993dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 35003dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 35013dde7c95SVishal Kulkarni ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 35023dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 35033dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 35043dde7c95SVishal Kulkarni M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 35053dde7c95SVishal Kulkarni 35063dde7c95SVishal Kulkarni enum fw_pi_error_type { 35073dde7c95SVishal Kulkarni FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 35083dde7c95SVishal Kulkarni }; 35093dde7c95SVishal Kulkarni 35103dde7c95SVishal Kulkarni struct fw_pi_error { 35113dde7c95SVishal Kulkarni __be32 err_type_pkd; 35123dde7c95SVishal Kulkarni __be32 flowid_len16; 35133dde7c95SVishal Kulkarni __be16 r2; 35143dde7c95SVishal Kulkarni __be16 app_tag; 35153dde7c95SVishal Kulkarni __be32 ref_tag; 35163dde7c95SVishal Kulkarni __be32 pisc[4]; 35173dde7c95SVishal Kulkarni }; 35183dde7c95SVishal Kulkarni 35193dde7c95SVishal Kulkarni #define S_FW_PI_ERROR_ERR_TYPE 24 35203dde7c95SVishal Kulkarni #define M_FW_PI_ERROR_ERR_TYPE 0xff 35213dde7c95SVishal Kulkarni #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 35223dde7c95SVishal Kulkarni #define G_FW_PI_ERROR_ERR_TYPE(x) \ 35233dde7c95SVishal Kulkarni (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 35243dde7c95SVishal Kulkarni 35253dde7c95SVishal Kulkarni struct fw_tlstx_data_wr { 35263dde7c95SVishal Kulkarni __be32 op_to_immdlen; 35273dde7c95SVishal Kulkarni __be32 flowid_len16; 35283dde7c95SVishal Kulkarni __be32 plen; 35293dde7c95SVishal Kulkarni __be32 lsodisable_to_flags; 35303dde7c95SVishal Kulkarni __be32 r5; 35313dde7c95SVishal Kulkarni __be32 ctxloc_to_exp; 35323dde7c95SVishal Kulkarni __be16 mfs; 35333dde7c95SVishal Kulkarni __be16 adjustedplen_pkd; 35343dde7c95SVishal Kulkarni __be16 expinplenmax_pkd; 35353dde7c95SVishal Kulkarni __u8 pdusinplenmax_pkd; 35363dde7c95SVishal Kulkarni __u8 r10; 35373dde7c95SVishal Kulkarni }; 35383dde7c95SVishal Kulkarni 35393dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_OPCODE 24 35403dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 35413dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 35423dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 35433dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 35443dde7c95SVishal Kulkarni 35453dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_COMPL 21 35463dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_COMPL 0x1 35473dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 35483dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 35493dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 35503dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 35513dde7c95SVishal Kulkarni 35523dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 35533dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 35543dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 35553dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 35563dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 35573dde7c95SVishal Kulkarni 35583dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_FLOWID 8 35593dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 35603dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 35613dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 35623dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 35633dde7c95SVishal Kulkarni 35643dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_LEN16 0 35653dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_LEN16 0xff 35663dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 35673dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 35683dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 35693dde7c95SVishal Kulkarni 35703dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 35713dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 35723dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 35733dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 35743dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 35753dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 35763dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 35773dde7c95SVishal Kulkarni 35783dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 35793dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 35803dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 35813dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 35823dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 35833dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 35843dde7c95SVishal Kulkarni 35853dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 35863dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 35873dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 35883dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 35893dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 35903dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 35913dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 35923dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 35933dde7c95SVishal Kulkarni 35943dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_FLAGS 0 35953dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 35963dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 35973dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 35983dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 35993dde7c95SVishal Kulkarni 36003dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_CTXLOC 30 36013dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 36023dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 36033dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 36043dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 36053dde7c95SVishal Kulkarni 36063dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_IVDSGL 29 36073dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 36083dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 36093dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 36103dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 36113dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 36123dde7c95SVishal Kulkarni 36133dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 36143dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 36153dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 36163dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 36173dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 36183dde7c95SVishal Kulkarni 36193dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_NUMIVS 14 36203dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 36213dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 36223dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 36233dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 36243dde7c95SVishal Kulkarni 36253dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_EXP 0 36263dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 36273dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 36283dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_EXP(x) \ 36293dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 36303dde7c95SVishal Kulkarni 36313dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 36323dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 36333dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 36343dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 36353dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 36363dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 36373dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 36383dde7c95SVishal Kulkarni 36393dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 36403dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 36413dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 36423dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 36433dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 36443dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 36453dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 36463dde7c95SVishal Kulkarni 36473dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 36483dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 36493dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 36503dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 36513dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 36523dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 36533dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 36543dde7c95SVishal Kulkarni 36553dde7c95SVishal Kulkarni struct fw_tls_keyctx_tx_wr { 36563dde7c95SVishal Kulkarni __be32 op_to_compl; 36573dde7c95SVishal Kulkarni __be32 flowid_len16; 36583dde7c95SVishal Kulkarni union fw_key_ctx { 36593dde7c95SVishal Kulkarni struct fw_tx_keyctx_hdr { 36603dde7c95SVishal Kulkarni __u8 ctxlen; 36613dde7c95SVishal Kulkarni __u8 r2; 36623dde7c95SVishal Kulkarni __be16 dualck_to_txvalid; 36633dde7c95SVishal Kulkarni __u8 txsalt[4]; 36643dde7c95SVishal Kulkarni __be64 r5; 36653dde7c95SVishal Kulkarni } txhdr; 36663dde7c95SVishal Kulkarni struct fw_rx_keyctx_hdr { 36673dde7c95SVishal Kulkarni __u8 flitcnt_hmacctrl; 36683dde7c95SVishal Kulkarni __u8 protover_ciphmode; 36693dde7c95SVishal Kulkarni __u8 authmode_to_rxvalid; 36703dde7c95SVishal Kulkarni __u8 ivpresent_to_rxmk_size; 36713dde7c95SVishal Kulkarni __u8 rxsalt[4]; 36723dde7c95SVishal Kulkarni __be64 ivinsert_to_authinsrt; 36733dde7c95SVishal Kulkarni } rxhdr; 36743dde7c95SVishal Kulkarni struct fw_keyctx_clear { 36753dde7c95SVishal Kulkarni __be32 tx_key; 36763dde7c95SVishal Kulkarni __be32 rx_key; 36773dde7c95SVishal Kulkarni } kctx_clr; 36783dde7c95SVishal Kulkarni } u; 36793dde7c95SVishal Kulkarni struct keys { 36803dde7c95SVishal Kulkarni __u8 edkey[32]; 36813dde7c95SVishal Kulkarni __u8 ipad[64]; 36823dde7c95SVishal Kulkarni __u8 opad[64]; 36833dde7c95SVishal Kulkarni } keys; 36843dde7c95SVishal Kulkarni __u8 reneg_to_write_rx; 36853dde7c95SVishal Kulkarni __u8 protocol; 36863dde7c95SVishal Kulkarni __be16 mfs; 36873dde7c95SVishal Kulkarni __be32 ftid; 36883dde7c95SVishal Kulkarni }; 36893dde7c95SVishal Kulkarni 36903dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24 36913dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff 36923dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE) 36933dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \ 36943dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE) 36953dde7c95SVishal Kulkarni 36963dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23 36973dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1 36983dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC) 36993dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \ 37003dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC) 37013dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U) 37023dde7c95SVishal Kulkarni 37033dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22 37043dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1 37053dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH) 37063dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \ 37073dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH) 37083dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U) 37093dde7c95SVishal Kulkarni 37103dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_COMPL 21 37113dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1 37123dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL) 37133dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \ 37143dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL) 37153dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U) 37163dde7c95SVishal Kulkarni 37173dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8 37183dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff 37193dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID) 37203dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \ 37213dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID) 37223dde7c95SVishal Kulkarni 37233dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_LEN16 0 37243dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff 37253dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16) 37263dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \ 37273dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16) 37283dde7c95SVishal Kulkarni 37293dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12 37303dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1 37313dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK) 37323dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \ 37333dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK) 37343dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U) 37353dde7c95SVishal Kulkarni 37363dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11 37373dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1 37383dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 37393dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 37403dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 37413dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \ 37423dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 37433dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \ 37443dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U) 37453dde7c95SVishal Kulkarni 37463dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10 37473dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1 37483dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 37493dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 37503dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 37513dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \ 37523dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 37533dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \ 37543dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U) 37553dde7c95SVishal Kulkarni 37563dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6 37573dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf 37583dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 37593dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 37603dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 37613dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \ 37623dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 37633dde7c95SVishal Kulkarni 37643dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2 37653dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf 37663dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 37673dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 37683dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 37693dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \ 37703dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 37713dde7c95SVishal Kulkarni 37723dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0 37733dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1 37743dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 37753dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID) 37763dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 37773dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID) 37783dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U) 37793dde7c95SVishal Kulkarni 37803dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3 37813dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f 37823dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 37833dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT) 37843dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 37853dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT) 37863dde7c95SVishal Kulkarni 37873dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0 37883dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7 37893dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 37903dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 37913dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 37923dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 37933dde7c95SVishal Kulkarni 37943dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4 37953dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf 37963dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 37973dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER) 37983dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 37993dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER) 38003dde7c95SVishal Kulkarni 38013dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0 38023dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf 38033dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 38043dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 38053dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 38063dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 38073dde7c95SVishal Kulkarni 38083dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4 38093dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf 38103dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 38113dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 38123dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 38133dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 38143dde7c95SVishal Kulkarni 38153dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3 38163dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1 38173dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 38183dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 38193dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 38203dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \ 38213dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 38223dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \ 38233dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U) 38243dde7c95SVishal Kulkarni 38253dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1 38263dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3 38273dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 38283dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 38293dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 38303dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \ 38313dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 38323dde7c95SVishal Kulkarni 38333dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0 38343dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1 38353dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 38363dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID) 38373dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 38383dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID) 38393dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U) 38403dde7c95SVishal Kulkarni 38413dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7 38423dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1 38433dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 38443dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 38453dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 38463dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \ 38473dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 38483dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U) 38493dde7c95SVishal Kulkarni 38503dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6 38513dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1 38523dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 38533dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 38543dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 38553dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \ 38563dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 38573dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \ 38583dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U) 38593dde7c95SVishal Kulkarni 38603dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3 38613dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7 38623dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 38633dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 38643dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 38653dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \ 38663dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 38673dde7c95SVishal Kulkarni 38683dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0 38693dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7 38703dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 38713dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 38723dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 38733dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \ 38743dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 38753dde7c95SVishal Kulkarni 38763dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55 38773dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL 38783dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 38793dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT) 38803dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 38813dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT) 38823dde7c95SVishal Kulkarni 38833dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47 38843dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL 38853dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 38863dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 38873dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 38883dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \ 38893dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 38903dde7c95SVishal Kulkarni 38913dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39 38923dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL 38933dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 38943dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 38953dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 38963dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \ 38973dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 38983dde7c95SVishal Kulkarni 38993dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30 39003dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL 39013dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 39023dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 39033dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 39043dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \ 39053dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 39063dde7c95SVishal Kulkarni 39073dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23 39083dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f 39093dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 39103dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 39113dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 39123dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \ 39133dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 39143dde7c95SVishal Kulkarni 39153dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14 39163dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff 39173dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 39183dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 39193dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 39203dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \ 39213dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 39223dde7c95SVishal Kulkarni 39233dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7 39243dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f 39253dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 39263dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 39273dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 39283dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \ 39293dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 39303dde7c95SVishal Kulkarni 39313dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0 39323dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f 39333dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 39343dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 39353dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 39363dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \ 39373dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 39383dde7c95SVishal Kulkarni 39393dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RENEG 4 39403dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1 39413dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG) 39423dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \ 39433dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG) 39443dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U) 39453dde7c95SVishal Kulkarni 39463dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3 39473dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1 39483dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 39493dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 39503dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 39513dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \ 39523dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 39533dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U) 39543dde7c95SVishal Kulkarni 39553dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2 39563dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1 39573dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 39583dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 39593dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 39603dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \ 39613dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 39623dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U) 39633dde7c95SVishal Kulkarni 39643dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1 39653dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1 39663dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 39673dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 39683dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 39693dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 39703dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U) 39713dde7c95SVishal Kulkarni 39723dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0 39733dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1 39743dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 39753dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 39763dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 39773dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 39783dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U) 39793dde7c95SVishal Kulkarni 39803dde7c95SVishal Kulkarni struct fw_crypto_lookaside_wr { 39813dde7c95SVishal Kulkarni __be32 op_to_cctx_size; 39823dde7c95SVishal Kulkarni __be32 len16_pkd; 39833dde7c95SVishal Kulkarni __be32 session_id; 39843dde7c95SVishal Kulkarni __be32 rx_chid_to_rx_q_id; 39853dde7c95SVishal Kulkarni __be32 key_addr; 39863dde7c95SVishal Kulkarni __be32 pld_size_hash_size; 39873dde7c95SVishal Kulkarni __be64 cookie; 39883dde7c95SVishal Kulkarni }; 39893dde7c95SVishal Kulkarni 39903dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 39913dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 39923dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 39933dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 39943dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 39953dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 39963dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 39973dde7c95SVishal Kulkarni 39983dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 39993dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 40003dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 40013dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 40023dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 40033dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 40043dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 40053dde7c95SVishal Kulkarni #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 40063dde7c95SVishal Kulkarni 40073dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 40083dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 40093dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 40103dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 40113dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 40123dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 40133dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 40143dde7c95SVishal Kulkarni 40153dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 40163dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 40173dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 40183dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 40193dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 40203dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 40213dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 40223dde7c95SVishal Kulkarni 40233dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 40243dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 40253dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 40263dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 40273dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 40283dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 40293dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 40303dde7c95SVishal Kulkarni 40313dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 40323dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 40333dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 40343dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 40353dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 40363dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 40373dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 40383dde7c95SVishal Kulkarni 40393dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 40403dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 40413dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 40423dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 40433dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 40443dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 40453dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 40463dde7c95SVishal Kulkarni 40473dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 40483dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 40493dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 40503dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 40513dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 40523dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 40533dde7c95SVishal Kulkarni 40543dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 40553dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 40563dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 40573dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 40583dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 40593dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 40603dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 40613dde7c95SVishal Kulkarni 40623dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 40633dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 40643dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 40653dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 40663dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 40673dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 40683dde7c95SVishal Kulkarni 40693dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 40703dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 40713dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 40723dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 40733dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 40743dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 40753dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 40763dde7c95SVishal Kulkarni 40773dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 40783dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 40793dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 40803dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 40813dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 40823dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 40833dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 40843dde7c95SVishal Kulkarni 40853dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 40863dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 40873dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 40883dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 40893dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 40903dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 40913dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 40923dde7c95SVishal Kulkarni 40933dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 40943dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 40953dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 40963dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 40973dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 40983dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 40993dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 41003dde7c95SVishal Kulkarni 41013dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 41023dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 41033dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 41043dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 41053dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 41063dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 41073dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 41083dde7c95SVishal Kulkarni 41093dde7c95SVishal Kulkarni /****************************************************************************** 41103dde7c95SVishal Kulkarni * C O M M A N D s 41113dde7c95SVishal Kulkarni *********************/ 411256b2bdd1SGireesh Nagabhushana 411356b2bdd1SGireesh Nagabhushana /* 411456b2bdd1SGireesh Nagabhushana * The maximum length of time, in miliseconds, that we expect any firmware 411556b2bdd1SGireesh Nagabhushana * command to take to execute and return a reply to the host. The RESET 411656b2bdd1SGireesh Nagabhushana * and INITIALIZE commands can take a fair amount of time to execute but 411756b2bdd1SGireesh Nagabhushana * most execute in far less time than this maximum. This constant is used 411856b2bdd1SGireesh Nagabhushana * by host software to determine how long to wait for a firmware command 411956b2bdd1SGireesh Nagabhushana * reply before declaring the firmware as dead/unreachable ... 412056b2bdd1SGireesh Nagabhushana */ 41213dde7c95SVishal Kulkarni #define FW_CMD_MAX_TIMEOUT 10000 412256b2bdd1SGireesh Nagabhushana 412356b2bdd1SGireesh Nagabhushana /* 412456b2bdd1SGireesh Nagabhushana * If a host driver does a HELLO and discovers that there's already a MASTER 412556b2bdd1SGireesh Nagabhushana * selected, we may have to wait for that MASTER to finish issuing RESET, 412656b2bdd1SGireesh Nagabhushana * configuration and INITIALIZE commands. Also, there's a possibility that 412756b2bdd1SGireesh Nagabhushana * our own HELLO may get lost if it happens right as the MASTER is issuign a 412856b2bdd1SGireesh Nagabhushana * RESET command, so we need to be willing to make a few retries of our HELLO. 412956b2bdd1SGireesh Nagabhushana */ 41303dde7c95SVishal Kulkarni #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 41313dde7c95SVishal Kulkarni #define FW_CMD_HELLO_RETRIES 3 413256b2bdd1SGireesh Nagabhushana 413356b2bdd1SGireesh Nagabhushana enum fw_cmd_opcodes { 41343dde7c95SVishal Kulkarni FW_LDST_CMD = 0x01, 41353dde7c95SVishal Kulkarni FW_RESET_CMD = 0x03, 41363dde7c95SVishal Kulkarni FW_HELLO_CMD = 0x04, 41373dde7c95SVishal Kulkarni FW_BYE_CMD = 0x05, 41383dde7c95SVishal Kulkarni FW_INITIALIZE_CMD = 0x06, 41393dde7c95SVishal Kulkarni FW_CAPS_CONFIG_CMD = 0x07, 41403dde7c95SVishal Kulkarni FW_PARAMS_CMD = 0x08, 41413dde7c95SVishal Kulkarni FW_PFVF_CMD = 0x09, 41423dde7c95SVishal Kulkarni FW_IQ_CMD = 0x10, 41433dde7c95SVishal Kulkarni FW_EQ_MNGT_CMD = 0x11, 41443dde7c95SVishal Kulkarni FW_EQ_ETH_CMD = 0x12, 41453dde7c95SVishal Kulkarni FW_EQ_CTRL_CMD = 0x13, 41463dde7c95SVishal Kulkarni FW_EQ_OFLD_CMD = 0x21, 41473dde7c95SVishal Kulkarni FW_VI_CMD = 0x14, 41483dde7c95SVishal Kulkarni FW_VI_MAC_CMD = 0x15, 41493dde7c95SVishal Kulkarni FW_VI_RXMODE_CMD = 0x16, 41503dde7c95SVishal Kulkarni FW_VI_ENABLE_CMD = 0x17, 41513dde7c95SVishal Kulkarni FW_VI_STATS_CMD = 0x1a, 41523dde7c95SVishal Kulkarni FW_ACL_MAC_CMD = 0x18, 41533dde7c95SVishal Kulkarni FW_ACL_VLAN_CMD = 0x19, 41543dde7c95SVishal Kulkarni FW_PORT_CMD = 0x1b, 41553dde7c95SVishal Kulkarni FW_PORT_STATS_CMD = 0x1c, 41563dde7c95SVishal Kulkarni FW_PORT_LB_STATS_CMD = 0x1d, 41573dde7c95SVishal Kulkarni FW_PORT_TRACE_CMD = 0x1e, 41583dde7c95SVishal Kulkarni FW_PORT_TRACE_MMAP_CMD = 0x1f, 41593dde7c95SVishal Kulkarni FW_RSS_IND_TBL_CMD = 0x20, 41603dde7c95SVishal Kulkarni FW_RSS_GLB_CONFIG_CMD = 0x22, 41613dde7c95SVishal Kulkarni FW_RSS_VI_CONFIG_CMD = 0x23, 41623dde7c95SVishal Kulkarni FW_SCHED_CMD = 0x24, 41633dde7c95SVishal Kulkarni FW_DEVLOG_CMD = 0x25, 41643dde7c95SVishal Kulkarni FW_WATCHDOG_CMD = 0x27, 41653dde7c95SVishal Kulkarni FW_CLIP_CMD = 0x28, 41663dde7c95SVishal Kulkarni FW_CHNET_IFACE_CMD = 0x26, 41673dde7c95SVishal Kulkarni FW_FCOE_RES_INFO_CMD = 0x31, 41683dde7c95SVishal Kulkarni FW_FCOE_LINK_CMD = 0x32, 41693dde7c95SVishal Kulkarni FW_FCOE_VNP_CMD = 0x33, 41703dde7c95SVishal Kulkarni FW_FCOE_SPARAMS_CMD = 0x35, 41713dde7c95SVishal Kulkarni FW_FCOE_STATS_CMD = 0x37, 41723dde7c95SVishal Kulkarni FW_FCOE_FCF_CMD = 0x38, 41733dde7c95SVishal Kulkarni FW_DCB_IEEE_CMD = 0x3a, 41743dde7c95SVishal Kulkarni FW_DIAG_CMD = 0x3d, 41753dde7c95SVishal Kulkarni FW_PTP_CMD = 0x3e, 4176*7e6ad469SVishal Kulkarni FW_HMA_CMD = 0x3f, 41773dde7c95SVishal Kulkarni FW_LASTC2E_CMD = 0x40, 41783dde7c95SVishal Kulkarni FW_ERROR_CMD = 0x80, 41793dde7c95SVishal Kulkarni FW_DEBUG_CMD = 0x81, 418056b2bdd1SGireesh Nagabhushana }; 418156b2bdd1SGireesh Nagabhushana 418256b2bdd1SGireesh Nagabhushana enum fw_cmd_cap { 41833dde7c95SVishal Kulkarni FW_CMD_CAP_PF = 0x01, 41843dde7c95SVishal Kulkarni FW_CMD_CAP_DMAQ = 0x02, 41853dde7c95SVishal Kulkarni FW_CMD_CAP_PORT = 0x04, 41863dde7c95SVishal Kulkarni FW_CMD_CAP_PORTPROMISC = 0x08, 41873dde7c95SVishal Kulkarni FW_CMD_CAP_PORTSTATS = 0x10, 41883dde7c95SVishal Kulkarni FW_CMD_CAP_VF = 0x80, 418956b2bdd1SGireesh Nagabhushana }; 419056b2bdd1SGireesh Nagabhushana 419156b2bdd1SGireesh Nagabhushana /* 419256b2bdd1SGireesh Nagabhushana * Generic command header flit0 419356b2bdd1SGireesh Nagabhushana */ 419456b2bdd1SGireesh Nagabhushana struct fw_cmd_hdr { 419556b2bdd1SGireesh Nagabhushana __be32 hi; 419656b2bdd1SGireesh Nagabhushana __be32 lo; 419756b2bdd1SGireesh Nagabhushana }; 419856b2bdd1SGireesh Nagabhushana 41993dde7c95SVishal Kulkarni #define S_FW_CMD_OP 24 42003dde7c95SVishal Kulkarni #define M_FW_CMD_OP 0xff 42013dde7c95SVishal Kulkarni #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 42023dde7c95SVishal Kulkarni #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 42033dde7c95SVishal Kulkarni 42043dde7c95SVishal Kulkarni #define S_FW_CMD_REQUEST 23 42053dde7c95SVishal Kulkarni #define M_FW_CMD_REQUEST 0x1 42063dde7c95SVishal Kulkarni #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 42073dde7c95SVishal Kulkarni #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 42083dde7c95SVishal Kulkarni #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 42093dde7c95SVishal Kulkarni 42103dde7c95SVishal Kulkarni #define S_FW_CMD_READ 22 42113dde7c95SVishal Kulkarni #define M_FW_CMD_READ 0x1 42123dde7c95SVishal Kulkarni #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 42133dde7c95SVishal Kulkarni #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 42143dde7c95SVishal Kulkarni #define F_FW_CMD_READ V_FW_CMD_READ(1U) 42153dde7c95SVishal Kulkarni 42163dde7c95SVishal Kulkarni #define S_FW_CMD_WRITE 21 42173dde7c95SVishal Kulkarni #define M_FW_CMD_WRITE 0x1 42183dde7c95SVishal Kulkarni #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 42193dde7c95SVishal Kulkarni #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 42203dde7c95SVishal Kulkarni #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 42213dde7c95SVishal Kulkarni 42223dde7c95SVishal Kulkarni #define S_FW_CMD_EXEC 20 42233dde7c95SVishal Kulkarni #define M_FW_CMD_EXEC 0x1 42243dde7c95SVishal Kulkarni #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 42253dde7c95SVishal Kulkarni #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 42263dde7c95SVishal Kulkarni #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 42273dde7c95SVishal Kulkarni 42283dde7c95SVishal Kulkarni #define S_FW_CMD_RAMASK 20 42293dde7c95SVishal Kulkarni #define M_FW_CMD_RAMASK 0xf 42303dde7c95SVishal Kulkarni #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 42313dde7c95SVishal Kulkarni #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 42323dde7c95SVishal Kulkarni 42333dde7c95SVishal Kulkarni #define S_FW_CMD_RETVAL 8 42343dde7c95SVishal Kulkarni #define M_FW_CMD_RETVAL 0xff 42353dde7c95SVishal Kulkarni #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 42363dde7c95SVishal Kulkarni #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 42373dde7c95SVishal Kulkarni 42383dde7c95SVishal Kulkarni #define S_FW_CMD_LEN16 0 42393dde7c95SVishal Kulkarni #define M_FW_CMD_LEN16 0xff 42403dde7c95SVishal Kulkarni #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 42413dde7c95SVishal Kulkarni #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 42423dde7c95SVishal Kulkarni 42433dde7c95SVishal Kulkarni #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 424456b2bdd1SGireesh Nagabhushana 424556b2bdd1SGireesh Nagabhushana /* 424656b2bdd1SGireesh Nagabhushana * address spaces 424756b2bdd1SGireesh Nagabhushana */ 424856b2bdd1SGireesh Nagabhushana enum fw_ldst_addrspc { 424956b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 425056b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 425156b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 425256b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 425356b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 42543dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_TP_PIO = 0x0010, 425556b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 42563dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_TP_MIB = 0x0012, 42573dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_MDIO = 0x0018, 42583dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_MPS = 0x0020, 42593dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_FUNC = 0x0028, 426056b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4261de483253SVishal Kulkarni FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 426256b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_LE = 0x0030, 4263de483253SVishal Kulkarni FW_LDST_ADDRSPC_I2C = 0x0038, 4264de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4265de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4266de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 42673dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_CIM_Q = 0x0048, 426856b2bdd1SGireesh Nagabhushana }; 426956b2bdd1SGireesh Nagabhushana 427056b2bdd1SGireesh Nagabhushana /* 427156b2bdd1SGireesh Nagabhushana * MDIO VSC8634 register access control field 427256b2bdd1SGireesh Nagabhushana */ 427356b2bdd1SGireesh Nagabhushana enum fw_ldst_mdio_vsc8634_aid { 427456b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_STANDARD, 427556b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_EXTENDED, 427656b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_GPIO 427756b2bdd1SGireesh Nagabhushana }; 427856b2bdd1SGireesh Nagabhushana 427956b2bdd1SGireesh Nagabhushana enum fw_ldst_mps_fid { 428056b2bdd1SGireesh Nagabhushana FW_LDST_MPS_ATRB, 428156b2bdd1SGireesh Nagabhushana FW_LDST_MPS_RPLC 428256b2bdd1SGireesh Nagabhushana }; 428356b2bdd1SGireesh Nagabhushana 428456b2bdd1SGireesh Nagabhushana enum fw_ldst_func_access_ctl { 428556b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_ACC_CTL_VIID, 428656b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_ACC_CTL_FID 428756b2bdd1SGireesh Nagabhushana }; 428856b2bdd1SGireesh Nagabhushana 428956b2bdd1SGireesh Nagabhushana enum fw_ldst_func_mod_index { 429056b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_MPS 429156b2bdd1SGireesh Nagabhushana }; 429256b2bdd1SGireesh Nagabhushana 429356b2bdd1SGireesh Nagabhushana struct fw_ldst_cmd { 429456b2bdd1SGireesh Nagabhushana __be32 op_to_addrspace; 429556b2bdd1SGireesh Nagabhushana __be32 cycles_to_len16; 429656b2bdd1SGireesh Nagabhushana union fw_ldst { 429756b2bdd1SGireesh Nagabhushana struct fw_ldst_addrval { 429856b2bdd1SGireesh Nagabhushana __be32 addr; 429956b2bdd1SGireesh Nagabhushana __be32 val; 430056b2bdd1SGireesh Nagabhushana } addrval; 430156b2bdd1SGireesh Nagabhushana struct fw_ldst_idctxt { 430256b2bdd1SGireesh Nagabhushana __be32 physid; 430356b2bdd1SGireesh Nagabhushana __be32 msg_ctxtflush; 430456b2bdd1SGireesh Nagabhushana __be32 ctxt_data7; 430556b2bdd1SGireesh Nagabhushana __be32 ctxt_data6; 430656b2bdd1SGireesh Nagabhushana __be32 ctxt_data5; 430756b2bdd1SGireesh Nagabhushana __be32 ctxt_data4; 430856b2bdd1SGireesh Nagabhushana __be32 ctxt_data3; 430956b2bdd1SGireesh Nagabhushana __be32 ctxt_data2; 431056b2bdd1SGireesh Nagabhushana __be32 ctxt_data1; 431156b2bdd1SGireesh Nagabhushana __be32 ctxt_data0; 431256b2bdd1SGireesh Nagabhushana } idctxt; 431356b2bdd1SGireesh Nagabhushana struct fw_ldst_mdio { 431456b2bdd1SGireesh Nagabhushana __be16 paddr_mmd; 431556b2bdd1SGireesh Nagabhushana __be16 raddr; 431656b2bdd1SGireesh Nagabhushana __be16 vctl; 431756b2bdd1SGireesh Nagabhushana __be16 rval; 431856b2bdd1SGireesh Nagabhushana } mdio; 43193dde7c95SVishal Kulkarni struct fw_ldst_cim_rq { 43203dde7c95SVishal Kulkarni __u8 req_first64[8]; 43213dde7c95SVishal Kulkarni __u8 req_second64[8]; 43223dde7c95SVishal Kulkarni __u8 resp_first64[8]; 43233dde7c95SVishal Kulkarni __u8 resp_second64[8]; 43243dde7c95SVishal Kulkarni __be32 r3[2]; 43253dde7c95SVishal Kulkarni } cim_rq; 43263dde7c95SVishal Kulkarni union fw_ldst_mps { 43273dde7c95SVishal Kulkarni struct fw_ldst_mps_rplc { 43283dde7c95SVishal Kulkarni __be16 fid_idx; 43293dde7c95SVishal Kulkarni __be16 rplcpf_pkd; 43303dde7c95SVishal Kulkarni __be32 rplc255_224; 43313dde7c95SVishal Kulkarni __be32 rplc223_192; 43323dde7c95SVishal Kulkarni __be32 rplc191_160; 43333dde7c95SVishal Kulkarni __be32 rplc159_128; 43343dde7c95SVishal Kulkarni __be32 rplc127_96; 43353dde7c95SVishal Kulkarni __be32 rplc95_64; 43363dde7c95SVishal Kulkarni __be32 rplc63_32; 43373dde7c95SVishal Kulkarni __be32 rplc31_0; 43383dde7c95SVishal Kulkarni } rplc; 43393dde7c95SVishal Kulkarni struct fw_ldst_mps_atrb { 43403dde7c95SVishal Kulkarni __be16 fid_mpsid; 43413dde7c95SVishal Kulkarni __be16 r2[3]; 43423dde7c95SVishal Kulkarni __be32 r3[2]; 43433dde7c95SVishal Kulkarni __be32 r4; 43443dde7c95SVishal Kulkarni __be32 atrb; 43453dde7c95SVishal Kulkarni __be16 vlan[16]; 43463dde7c95SVishal Kulkarni } atrb; 434756b2bdd1SGireesh Nagabhushana } mps; 434856b2bdd1SGireesh Nagabhushana struct fw_ldst_func { 434956b2bdd1SGireesh Nagabhushana __u8 access_ctl; 435056b2bdd1SGireesh Nagabhushana __u8 mod_index; 435156b2bdd1SGireesh Nagabhushana __be16 ctl_id; 435256b2bdd1SGireesh Nagabhushana __be32 offset; 435356b2bdd1SGireesh Nagabhushana __be64 data0; 435456b2bdd1SGireesh Nagabhushana __be64 data1; 435556b2bdd1SGireesh Nagabhushana } func; 435656b2bdd1SGireesh Nagabhushana struct fw_ldst_pcie { 435756b2bdd1SGireesh Nagabhushana __u8 ctrl_to_fn; 435856b2bdd1SGireesh Nagabhushana __u8 bnum; 435956b2bdd1SGireesh Nagabhushana __u8 r; 436056b2bdd1SGireesh Nagabhushana __u8 ext_r; 436156b2bdd1SGireesh Nagabhushana __u8 select_naccess; 436256b2bdd1SGireesh Nagabhushana __u8 pcie_fn; 436356b2bdd1SGireesh Nagabhushana __be16 nset_pkd; 436456b2bdd1SGireesh Nagabhushana __be32 data[12]; 436556b2bdd1SGireesh Nagabhushana } pcie; 4366de483253SVishal Kulkarni struct fw_ldst_i2c_deprecated { 436756b2bdd1SGireesh Nagabhushana __u8 pid_pkd; 436856b2bdd1SGireesh Nagabhushana __u8 base; 436956b2bdd1SGireesh Nagabhushana __u8 boffset; 437056b2bdd1SGireesh Nagabhushana __u8 data; 437156b2bdd1SGireesh Nagabhushana __be32 r9; 4372de483253SVishal Kulkarni } i2c_deprecated; 4373de483253SVishal Kulkarni struct fw_ldst_i2c { 4374de483253SVishal Kulkarni __u8 pid; 4375de483253SVishal Kulkarni __u8 did; 4376de483253SVishal Kulkarni __u8 boffset; 4377de483253SVishal Kulkarni __u8 blen; 4378de483253SVishal Kulkarni __be32 r9; 4379de483253SVishal Kulkarni __u8 data[48]; 43803dde7c95SVishal Kulkarni } i2c; 438156b2bdd1SGireesh Nagabhushana struct fw_ldst_le { 4382de483253SVishal Kulkarni __be32 index; 4383de483253SVishal Kulkarni __be32 r9; 4384de483253SVishal Kulkarni __u8 val[33]; 4385de483253SVishal Kulkarni __u8 r11[7]; 438656b2bdd1SGireesh Nagabhushana } le; 438756b2bdd1SGireesh Nagabhushana } u; 438856b2bdd1SGireesh Nagabhushana }; 438956b2bdd1SGireesh Nagabhushana 43903dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_ADDRSPACE 0 43913dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_ADDRSPACE 0xff 43923dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 43933dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_ADDRSPACE(x) \ 43943dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 43953dde7c95SVishal Kulkarni 43963dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_CYCLES 16 43973dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_CYCLES 0xffff 43983dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 43993dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_CYCLES(x) \ 44003dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 44013dde7c95SVishal Kulkarni 44023dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_MSG 31 44033dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_MSG 0x1 44043dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 44053dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_MSG(x) \ 44063dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 44073dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 44083dde7c95SVishal Kulkarni 44093dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_CTXTFLUSH 30 44103dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_CTXTFLUSH 0x1 44113dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 44123dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 44133dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 44143dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 44153dde7c95SVishal Kulkarni 44163dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_PADDR 8 44173dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_PADDR 0x1f 44183dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 44193dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_PADDR(x) \ 44203dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 44213dde7c95SVishal Kulkarni 44223dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_MMD 0 44233dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_MMD 0x1f 44243dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 44253dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_MMD(x) \ 44263dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 44273dde7c95SVishal Kulkarni 44283dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_FID 15 44293dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_FID 0x1 44303dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 44313dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_FID(x) \ 44323dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 44333dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 44343dde7c95SVishal Kulkarni 44353dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_IDX 0 44363dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_IDX 0x7fff 44373dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 44383dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_IDX(x) \ 44393dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 44403dde7c95SVishal Kulkarni 44413dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_RPLCPF 0 44423dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_RPLCPF 0xff 44433dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 44443dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_RPLCPF(x) \ 44453dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 44463dde7c95SVishal Kulkarni 44473dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_MPSID 0 44483dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_MPSID 0x7fff 44493dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 44503dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_MPSID(x) \ 44513dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 44523dde7c95SVishal Kulkarni 44533dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_CTRL 7 44543dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_CTRL 0x1 44553dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 44563dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_CTRL(x) \ 44573dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 44583dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 44593dde7c95SVishal Kulkarni 44603dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_LC 4 44613dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_LC 0x1 44623dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 44633dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_LC(x) \ 44643dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 44653dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 44663dde7c95SVishal Kulkarni 44673dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_AI 3 44683dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_AI 0x1 44693dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 44703dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_AI(x) \ 44713dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 44723dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 44733dde7c95SVishal Kulkarni 44743dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_FN 0 44753dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_FN 0x7 44763dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 44773dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_FN(x) \ 44783dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 44793dde7c95SVishal Kulkarni 44803dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_SELECT 4 44813dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_SELECT 0xf 44823dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 44833dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_SELECT(x) \ 44843dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 44853dde7c95SVishal Kulkarni 44863dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_NACCESS 0 44873dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_NACCESS 0xf 44883dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 44893dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_NACCESS(x) \ 44903dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 44913dde7c95SVishal Kulkarni 44923dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_NSET 14 44933dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_NSET 0x3 44943dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 44953dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_NSET(x) \ 44963dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 44973dde7c95SVishal Kulkarni 44983dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_PID 6 44993dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_PID 0x3 45003dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 45013dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_PID(x) \ 45023dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 450356b2bdd1SGireesh Nagabhushana 450456b2bdd1SGireesh Nagabhushana struct fw_reset_cmd { 450556b2bdd1SGireesh Nagabhushana __be32 op_to_write; 450656b2bdd1SGireesh Nagabhushana __be32 retval_len16; 450756b2bdd1SGireesh Nagabhushana __be32 val; 450856b2bdd1SGireesh Nagabhushana __be32 halt_pkd; 450956b2bdd1SGireesh Nagabhushana }; 451056b2bdd1SGireesh Nagabhushana 45113dde7c95SVishal Kulkarni #define S_FW_RESET_CMD_HALT 31 45123dde7c95SVishal Kulkarni #define M_FW_RESET_CMD_HALT 0x1 45133dde7c95SVishal Kulkarni #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 45143dde7c95SVishal Kulkarni #define G_FW_RESET_CMD_HALT(x) \ 45153dde7c95SVishal Kulkarni (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 45163dde7c95SVishal Kulkarni #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 451756b2bdd1SGireesh Nagabhushana 451856b2bdd1SGireesh Nagabhushana enum { 451956b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_OS = 0, 452056b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_PREOS0 = 1, 452156b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_PREOS1 = 2, 452256b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_POSTOS = 3, 452356b2bdd1SGireesh Nagabhushana }; 452456b2bdd1SGireesh Nagabhushana 452556b2bdd1SGireesh Nagabhushana struct fw_hello_cmd { 452656b2bdd1SGireesh Nagabhushana __be32 op_to_write; 452756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 452856b2bdd1SGireesh Nagabhushana __be32 err_to_clearinit; 452956b2bdd1SGireesh Nagabhushana __be32 fwrev; 453056b2bdd1SGireesh Nagabhushana }; 453156b2bdd1SGireesh Nagabhushana 45323dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_ERR 31 45333dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_ERR 0x1 45343dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 45353dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_ERR(x) \ 45363dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 45373dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 45383dde7c95SVishal Kulkarni 45393dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_INIT 30 45403dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_INIT 0x1 45413dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 45423dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_INIT(x) \ 45433dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 45443dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 45453dde7c95SVishal Kulkarni 45463dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MASTERDIS 29 45473dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MASTERDIS 0x1 45483dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 45493dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MASTERDIS(x) \ 45503dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 45513dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 45523dde7c95SVishal Kulkarni 45533dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MASTERFORCE 28 45543dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MASTERFORCE 0x1 45553dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 45563dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 45573dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 45583dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 45593dde7c95SVishal Kulkarni 45603dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MBMASTER 24 45613dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MBMASTER 0xf 45623dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 45633dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MBMASTER(x) \ 45643dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 45653dde7c95SVishal Kulkarni 45663dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 45673dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 45683dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 45693dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 45703dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 45713dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 45723dde7c95SVishal Kulkarni 45733dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MBASYNCNOT 20 45743dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 45753dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 45763dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 45773dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 45783dde7c95SVishal Kulkarni 45793dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_STAGE 17 45803dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_STAGE 0x7 45813dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 45823dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_STAGE(x) \ 45833dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 45843dde7c95SVishal Kulkarni 45853dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_CLEARINIT 16 45863dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_CLEARINIT 0x1 45873dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 45883dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_CLEARINIT(x) \ 45893dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 45903dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 459156b2bdd1SGireesh Nagabhushana 459256b2bdd1SGireesh Nagabhushana struct fw_bye_cmd { 459356b2bdd1SGireesh Nagabhushana __be32 op_to_write; 459456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 459556b2bdd1SGireesh Nagabhushana __be64 r3; 459656b2bdd1SGireesh Nagabhushana }; 459756b2bdd1SGireesh Nagabhushana 459856b2bdd1SGireesh Nagabhushana struct fw_initialize_cmd { 459956b2bdd1SGireesh Nagabhushana __be32 op_to_write; 460056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 460156b2bdd1SGireesh Nagabhushana __be64 r3; 460256b2bdd1SGireesh Nagabhushana }; 460356b2bdd1SGireesh Nagabhushana 460456b2bdd1SGireesh Nagabhushana enum fw_caps_config_hm { 460556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 460656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PL = 0x00000002, 460756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SGE = 0x00000004, 460856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_CIM = 0x00000008, 460956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 461056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_TP = 0x00000020, 461156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 461256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 461356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 461456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MC = 0x00000200, 461556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_LE = 0x00000400, 461656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MPS = 0x00000800, 461756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 461856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 461956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 462056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MI = 0x00008000, 462156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 462256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 462356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SMB = 0x00040000, 462456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MA = 0x00080000, 462556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 462656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMU = 0x00200000, 462756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_UART = 0x00400000, 462856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SF = 0x00800000, 462956b2bdd1SGireesh Nagabhushana }; 463056b2bdd1SGireesh Nagabhushana 463156b2bdd1SGireesh Nagabhushana /* 463256b2bdd1SGireesh Nagabhushana * The VF Register Map. 463356b2bdd1SGireesh Nagabhushana * 463456b2bdd1SGireesh Nagabhushana * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 463556b2bdd1SGireesh Nagabhushana * bus module (PL) and CPU Interface Module (CIM) components are mapped via 463656b2bdd1SGireesh Nagabhushana * the Slice to Module Map Table (see below) in the Physical Function Register 463756b2bdd1SGireesh Nagabhushana * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 463856b2bdd1SGireesh Nagabhushana * and Offset registers in the PF Register Map. The MBDATA base address is 463956b2bdd1SGireesh Nagabhushana * quite constrained as it determines the Mailbox Data addresses for both PFs 464056b2bdd1SGireesh Nagabhushana * and VFs, and therefore must fit in both the VF and PF Register Maps without 464156b2bdd1SGireesh Nagabhushana * overlapping other registers. 464256b2bdd1SGireesh Nagabhushana */ 46433dde7c95SVishal Kulkarni #define FW_T4VF_SGE_BASE_ADDR 0x0000 46443dde7c95SVishal Kulkarni #define FW_T4VF_MPS_BASE_ADDR 0x0100 46453dde7c95SVishal Kulkarni #define FW_T4VF_PL_BASE_ADDR 0x0200 46463dde7c95SVishal Kulkarni #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 46473dde7c95SVishal Kulkarni #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 46483dde7c95SVishal Kulkarni #define FW_T4VF_CIM_BASE_ADDR 0x0300 464956b2bdd1SGireesh Nagabhushana 46503dde7c95SVishal Kulkarni #define FW_T4VF_REGMAP_START 0x0000 46513dde7c95SVishal Kulkarni #define FW_T4VF_REGMAP_SIZE 0x0400 465256b2bdd1SGireesh Nagabhushana 465356b2bdd1SGireesh Nagabhushana enum fw_caps_config_nbm { 465456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 465556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 465656b2bdd1SGireesh Nagabhushana }; 465756b2bdd1SGireesh Nagabhushana 465856b2bdd1SGireesh Nagabhushana enum fw_caps_config_link { 465956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 466056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 466156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 466256b2bdd1SGireesh Nagabhushana }; 466356b2bdd1SGireesh Nagabhushana 466456b2bdd1SGireesh Nagabhushana enum fw_caps_config_switch { 466556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 466656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 466756b2bdd1SGireesh Nagabhushana }; 466856b2bdd1SGireesh Nagabhushana 466956b2bdd1SGireesh Nagabhushana enum fw_caps_config_nic { 467056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC = 0x00000001, 467156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_VM = 0x00000002, 467256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 467356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_UM = 0x00000008, 467456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 46753dde7c95SVishal Kulkarni FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 46763dde7c95SVishal Kulkarni FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 467756b2bdd1SGireesh Nagabhushana }; 467856b2bdd1SGireesh Nagabhushana 467956b2bdd1SGireesh Nagabhushana enum fw_caps_config_toe { 468056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_TOE = 0x00000001, 468156b2bdd1SGireesh Nagabhushana }; 468256b2bdd1SGireesh Nagabhushana 468356b2bdd1SGireesh Nagabhushana enum fw_caps_config_rdma { 468456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 468556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 468656b2bdd1SGireesh Nagabhushana }; 468756b2bdd1SGireesh Nagabhushana 468856b2bdd1SGireesh Nagabhushana enum fw_caps_config_iscsi { 468956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 469056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 469156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 469256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 469356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 469456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 46953dde7c95SVishal Kulkarni FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 46963dde7c95SVishal Kulkarni FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 46973dde7c95SVishal Kulkarni FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 46983dde7c95SVishal Kulkarni }; 469956b2bdd1SGireesh Nagabhushana 47003dde7c95SVishal Kulkarni enum fw_caps_config_crypto { 47013dde7c95SVishal Kulkarni FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 47023dde7c95SVishal Kulkarni FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 470356b2bdd1SGireesh Nagabhushana }; 470456b2bdd1SGireesh Nagabhushana 470556b2bdd1SGireesh Nagabhushana enum fw_caps_config_fcoe { 470656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 470756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 470856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4709de483253SVishal Kulkarni FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4710de483253SVishal Kulkarni FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 471156b2bdd1SGireesh Nagabhushana }; 471256b2bdd1SGireesh Nagabhushana 471356b2bdd1SGireesh Nagabhushana enum fw_memtype_cf { 47143dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 47153dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 47163dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 47173dde7c95SVishal Kulkarni FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 47183dde7c95SVishal Kulkarni FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 47193dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 472056b2bdd1SGireesh Nagabhushana }; 472156b2bdd1SGireesh Nagabhushana 472256b2bdd1SGireesh Nagabhushana struct fw_caps_config_cmd { 472356b2bdd1SGireesh Nagabhushana __be32 op_to_write; 472456b2bdd1SGireesh Nagabhushana __be32 cfvalid_to_len16; 472556b2bdd1SGireesh Nagabhushana __be32 r2; 472656b2bdd1SGireesh Nagabhushana __be32 hwmbitmap; 472756b2bdd1SGireesh Nagabhushana __be16 nbmcaps; 472856b2bdd1SGireesh Nagabhushana __be16 linkcaps; 472956b2bdd1SGireesh Nagabhushana __be16 switchcaps; 473056b2bdd1SGireesh Nagabhushana __be16 r3; 473156b2bdd1SGireesh Nagabhushana __be16 niccaps; 473256b2bdd1SGireesh Nagabhushana __be16 toecaps; 473356b2bdd1SGireesh Nagabhushana __be16 rdmacaps; 47343dde7c95SVishal Kulkarni __be16 cryptocaps; 473556b2bdd1SGireesh Nagabhushana __be16 iscsicaps; 473656b2bdd1SGireesh Nagabhushana __be16 fcoecaps; 473756b2bdd1SGireesh Nagabhushana __be32 cfcsum; 473856b2bdd1SGireesh Nagabhushana __be32 finiver; 473956b2bdd1SGireesh Nagabhushana __be32 finicsum; 474056b2bdd1SGireesh Nagabhushana }; 474156b2bdd1SGireesh Nagabhushana 47423dde7c95SVishal Kulkarni #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 47433dde7c95SVishal Kulkarni #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 47443dde7c95SVishal Kulkarni #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 47453dde7c95SVishal Kulkarni #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 47463dde7c95SVishal Kulkarni (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 47473dde7c95SVishal Kulkarni #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 47483dde7c95SVishal Kulkarni 47493dde7c95SVishal Kulkarni #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 47503dde7c95SVishal Kulkarni #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 47513dde7c95SVishal Kulkarni #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 47523dde7c95SVishal Kulkarni ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 47533dde7c95SVishal Kulkarni #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 47543dde7c95SVishal Kulkarni (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 47553dde7c95SVishal Kulkarni M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 47563dde7c95SVishal Kulkarni 47573dde7c95SVishal Kulkarni #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 47583dde7c95SVishal Kulkarni #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 47593dde7c95SVishal Kulkarni #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 47603dde7c95SVishal Kulkarni ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 47613dde7c95SVishal Kulkarni #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 47623dde7c95SVishal Kulkarni (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 47633dde7c95SVishal Kulkarni M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 476456b2bdd1SGireesh Nagabhushana 476556b2bdd1SGireesh Nagabhushana /* 476656b2bdd1SGireesh Nagabhushana * params command mnemonics 476756b2bdd1SGireesh Nagabhushana */ 476856b2bdd1SGireesh Nagabhushana enum fw_params_mnem { 476956b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_DEV = 1, /* device params */ 477056b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_PFVF = 2, /* function params */ 477156b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_REG = 3, /* limited register access */ 477256b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 47733dde7c95SVishal Kulkarni FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 477456b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_LAST 477556b2bdd1SGireesh Nagabhushana }; 477656b2bdd1SGireesh Nagabhushana 477756b2bdd1SGireesh Nagabhushana /* 477856b2bdd1SGireesh Nagabhushana * device parameters 477956b2bdd1SGireesh Nagabhushana */ 4780*7e6ad469SVishal Kulkarni #define S_FW_PARAMS_PARAM_FILTER_MODE 16 4781*7e6ad469SVishal Kulkarni #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 4782*7e6ad469SVishal Kulkarni #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 4783*7e6ad469SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 4784*7e6ad469SVishal Kulkarni #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 4785*7e6ad469SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 4786*7e6ad469SVishal Kulkarni M_FW_PARAMS_PARAM_FILTER_MODE) 4787*7e6ad469SVishal Kulkarni 4788*7e6ad469SVishal Kulkarni #define S_FW_PARAMS_PARAM_FILTER_MASK 0 4789*7e6ad469SVishal Kulkarni #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 4790*7e6ad469SVishal Kulkarni #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 4791*7e6ad469SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 4792*7e6ad469SVishal Kulkarni #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 4793*7e6ad469SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 4794*7e6ad469SVishal Kulkarni M_FW_PARAMS_PARAM_FILTER_MASK) 4795*7e6ad469SVishal Kulkarni 479656b2bdd1SGireesh Nagabhushana enum fw_params_param_dev { 479756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 479856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 47993dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 48003dde7c95SVishal Kulkarni * allocated by the device's 48013dde7c95SVishal Kulkarni * Lookup Engine 48023dde7c95SVishal Kulkarni */ 480356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 480456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 480556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 480656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 480756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 480856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 480956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 481056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4811de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4812de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4813de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_CF = 0x0D, 4814de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4815de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4816de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4817de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4818de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4819de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4820de483253SVishal Kulkarni */ 4821de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4822de483253SVishal Kulkarni */ 4823de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4824de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4825de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 48263dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 48273dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 48283dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 48293dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 48303dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 48313dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 48323dde7c95SVishal Kulkarni 48333dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 48343dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4835*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4836*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4837*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4838*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4839*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 4840*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 4841*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 4842*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 4843*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 4844*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 4845*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 4846*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 4847*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C, 4848*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D, 4849*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 48503dde7c95SVishal Kulkarni }; 48513dde7c95SVishal Kulkarni 48523dde7c95SVishal Kulkarni /* 48533dde7c95SVishal Kulkarni * dev bypass parameters; actions and modes 48543dde7c95SVishal Kulkarni */ 48553dde7c95SVishal Kulkarni enum fw_params_param_dev_bypass { 48563dde7c95SVishal Kulkarni 48573dde7c95SVishal Kulkarni /* actions 48583dde7c95SVishal Kulkarni */ 48593dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 48603dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 48613dde7c95SVishal Kulkarni 48623dde7c95SVishal Kulkarni /* modes 48633dde7c95SVishal Kulkarni */ 48643dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 48653dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 48663dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 48673dde7c95SVishal Kulkarni }; 48683dde7c95SVishal Kulkarni 48693dde7c95SVishal Kulkarni enum fw_params_param_dev_phyfw { 48703dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 48713dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 48723dde7c95SVishal Kulkarni }; 48733dde7c95SVishal Kulkarni 48743dde7c95SVishal Kulkarni enum fw_params_param_dev_diag { 48753dde7c95SVishal Kulkarni FW_PARAM_DEV_DIAG_TMP = 0x00, 48763dde7c95SVishal Kulkarni FW_PARAM_DEV_DIAG_VDD = 0x01, 4877*7e6ad469SVishal Kulkarni FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 4878*7e6ad469SVishal Kulkarni }; 4879*7e6ad469SVishal Kulkarni 4880*7e6ad469SVishal Kulkarni enum fw_params_param_dev_filter{ 4881*7e6ad469SVishal Kulkarni FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 4882*7e6ad469SVishal Kulkarni FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 48833dde7c95SVishal Kulkarni }; 48843dde7c95SVishal Kulkarni 48853dde7c95SVishal Kulkarni enum fw_params_param_dev_fwcache { 48863dde7c95SVishal Kulkarni FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 48873dde7c95SVishal Kulkarni FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 488856b2bdd1SGireesh Nagabhushana }; 488956b2bdd1SGireesh Nagabhushana 489056b2bdd1SGireesh Nagabhushana /* 489156b2bdd1SGireesh Nagabhushana * physical and virtual function parameters 489256b2bdd1SGireesh Nagabhushana */ 489356b2bdd1SGireesh Nagabhushana enum fw_params_param_pfvf { 489456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 489556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 489656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 489756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 489856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 489956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 490056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 490156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 490256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 490356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 490456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 490556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 490656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 490756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 490856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 490956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 491056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 491156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 491256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 491356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 491456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 491556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 491656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 491756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 491856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 49193dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 49203dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 492156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 492256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_VIID = 0x24, 492356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 492456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 492556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 492656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 492756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 492856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 492956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 493056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 493156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 493256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 493356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4934de483253SVishal Kulkarni FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 49353dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 49363dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 49373dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 49383dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 49393dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 49403dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 49413dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 49423dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 49433dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4944*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4945*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4946*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4947*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 4948*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 4949*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 4950*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 4951*7e6ad469SVishal Kulkarni }; 4952*7e6ad469SVishal Kulkarni 4953*7e6ad469SVishal Kulkarni /* 4954*7e6ad469SVishal Kulkarni * virtual link state as seen by the specified VF 4955*7e6ad469SVishal Kulkarni */ 4956*7e6ad469SVishal Kulkarni enum vf_link_states { 4957*7e6ad469SVishal Kulkarni VF_LINK_STATE_AUTO = 0x00, 4958*7e6ad469SVishal Kulkarni VF_LINK_STATE_ENABLE = 0x01, 4959*7e6ad469SVishal Kulkarni VF_LINK_STATE_DISABLE = 0x02, 496056b2bdd1SGireesh Nagabhushana }; 496156b2bdd1SGireesh Nagabhushana 496256b2bdd1SGireesh Nagabhushana /* 496356b2bdd1SGireesh Nagabhushana * dma queue parameters 496456b2bdd1SGireesh Nagabhushana */ 496556b2bdd1SGireesh Nagabhushana enum fw_params_param_dmaq { 496656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 496756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 49683dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 49693dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 497056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 497156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 497256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4973de483253SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 49743dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4975*7e6ad469SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 49763dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 49773dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 497856b2bdd1SGireesh Nagabhushana }; 497956b2bdd1SGireesh Nagabhushana 498056b2bdd1SGireesh Nagabhushana /* 49813dde7c95SVishal Kulkarni * chnet parameters 498256b2bdd1SGireesh Nagabhushana */ 49833dde7c95SVishal Kulkarni enum fw_params_param_chnet { 49843dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 49853dde7c95SVishal Kulkarni }; 49863dde7c95SVishal Kulkarni 49873dde7c95SVishal Kulkarni enum fw_params_param_chnet_flags { 49883dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 49893dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 49903dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 49913dde7c95SVishal Kulkarni }; 49923dde7c95SVishal Kulkarni 49933dde7c95SVishal Kulkarni #define S_FW_PARAMS_MNEM 24 49943dde7c95SVishal Kulkarni #define M_FW_PARAMS_MNEM 0xff 49953dde7c95SVishal Kulkarni #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 49963dde7c95SVishal Kulkarni #define G_FW_PARAMS_MNEM(x) \ 49973dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 49983dde7c95SVishal Kulkarni 49993dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_X 16 50003dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_X 0xff 50013dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 50023dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_X(x) \ 50033dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 50043dde7c95SVishal Kulkarni 50053dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_Y 8 50063dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_Y 0xff 50073dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 50083dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_Y(x) \ 50093dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 50103dde7c95SVishal Kulkarni 50113dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_Z 0 50123dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_Z 0xff 50133dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 50143dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_Z(x) \ 50153dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 50163dde7c95SVishal Kulkarni 50173dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_XYZ 0 50183dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_XYZ 0xffffff 50193dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 50203dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_XYZ(x) \ 50213dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 50223dde7c95SVishal Kulkarni 50233dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_YZ 0 50243dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_YZ 0xffff 50253dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 50263dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_YZ(x) \ 50273dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 50283dde7c95SVishal Kulkarni 50293dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 50303dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 50313dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 50323dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 50333dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 50343dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 50353dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 50363dde7c95SVishal Kulkarni 50373dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 50383dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 50393dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 50403dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 50413dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 50423dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 50433dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 50443dde7c95SVishal Kulkarni 50453dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 50463dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 50473dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 50483dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 50493dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 50503dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 50513dde7c95SVishal Kulkarni 50523dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 50533dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 50543dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 50553dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 50563dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 50573dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 50583dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 50593dde7c95SVishal Kulkarni 50603dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 50613dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 50623dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 50633dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 50643dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 50653dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 50663dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 506756b2bdd1SGireesh Nagabhushana 506856b2bdd1SGireesh Nagabhushana struct fw_params_cmd { 506956b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 507056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 507156b2bdd1SGireesh Nagabhushana struct fw_params_param { 507256b2bdd1SGireesh Nagabhushana __be32 mnem; 507356b2bdd1SGireesh Nagabhushana __be32 val; 507456b2bdd1SGireesh Nagabhushana } param[7]; 507556b2bdd1SGireesh Nagabhushana }; 507656b2bdd1SGireesh Nagabhushana 50773dde7c95SVishal Kulkarni #define S_FW_PARAMS_CMD_PFN 8 50783dde7c95SVishal Kulkarni #define M_FW_PARAMS_CMD_PFN 0x7 50793dde7c95SVishal Kulkarni #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 50803dde7c95SVishal Kulkarni #define G_FW_PARAMS_CMD_PFN(x) \ 50813dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 508256b2bdd1SGireesh Nagabhushana 50833dde7c95SVishal Kulkarni #define S_FW_PARAMS_CMD_VFN 0 50843dde7c95SVishal Kulkarni #define M_FW_PARAMS_CMD_VFN 0xff 50853dde7c95SVishal Kulkarni #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 50863dde7c95SVishal Kulkarni #define G_FW_PARAMS_CMD_VFN(x) \ 50873dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 508856b2bdd1SGireesh Nagabhushana 508956b2bdd1SGireesh Nagabhushana struct fw_pfvf_cmd { 509056b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 509156b2bdd1SGireesh Nagabhushana __be32 retval_len16; 509256b2bdd1SGireesh Nagabhushana __be32 niqflint_niq; 509356b2bdd1SGireesh Nagabhushana __be32 type_to_neq; 509456b2bdd1SGireesh Nagabhushana __be32 tc_to_nexactf; 509556b2bdd1SGireesh Nagabhushana __be32 r_caps_to_nethctrl; 509656b2bdd1SGireesh Nagabhushana __be16 nricq; 509756b2bdd1SGireesh Nagabhushana __be16 nriqp; 509856b2bdd1SGireesh Nagabhushana __be32 r4; 509956b2bdd1SGireesh Nagabhushana }; 510056b2bdd1SGireesh Nagabhushana 51013dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_PFN 8 51023dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_PFN 0x7 51033dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 51043dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_PFN(x) \ 51053dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 51063dde7c95SVishal Kulkarni 51073dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_VFN 0 51083dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_VFN 0xff 51093dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 51103dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_VFN(x) \ 51113dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 51123dde7c95SVishal Kulkarni 51133dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NIQFLINT 20 51143dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NIQFLINT 0xfff 51153dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 51163dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NIQFLINT(x) \ 51173dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 51183dde7c95SVishal Kulkarni 51193dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NIQ 0 51203dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NIQ 0xfffff 51213dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 51223dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NIQ(x) \ 51233dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 51243dde7c95SVishal Kulkarni 51253dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_TYPE 31 51263dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_TYPE 0x1 51273dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 51283dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_TYPE(x) \ 51293dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 51303dde7c95SVishal Kulkarni #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 51313dde7c95SVishal Kulkarni 51323dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_CMASK 24 51333dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_CMASK 0xf 51343dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 51353dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_CMASK(x) \ 51363dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 51373dde7c95SVishal Kulkarni 51383dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_PMASK 20 51393dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_PMASK 0xf 51403dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 51413dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_PMASK(x) \ 51423dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 51433dde7c95SVishal Kulkarni 51443dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NEQ 0 51453dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NEQ 0xfffff 51463dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 51473dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NEQ(x) \ 51483dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 51493dde7c95SVishal Kulkarni 51503dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_TC 24 51513dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_TC 0xff 51523dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 51533dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_TC(x) \ 51543dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 51553dde7c95SVishal Kulkarni 51563dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NVI 16 51573dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NVI 0xff 51583dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 51593dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NVI(x) \ 51603dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 51613dde7c95SVishal Kulkarni 51623dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NEXACTF 0 51633dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NEXACTF 0xffff 51643dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 51653dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NEXACTF(x) \ 51663dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 51673dde7c95SVishal Kulkarni 51683dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_R_CAPS 24 51693dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_R_CAPS 0xff 51703dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 51713dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_R_CAPS(x) \ 51723dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 51733dde7c95SVishal Kulkarni 51743dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_WX_CAPS 16 51753dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_WX_CAPS 0xff 51763dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 51773dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_WX_CAPS(x) \ 51783dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 51793dde7c95SVishal Kulkarni 51803dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NETHCTRL 0 51813dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NETHCTRL 0xffff 51823dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 51833dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NETHCTRL(x) \ 51843dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 518556b2bdd1SGireesh Nagabhushana 518656b2bdd1SGireesh Nagabhushana /* 518756b2bdd1SGireesh Nagabhushana * ingress queue type; the first 1K ingress queues can have associated 0, 518856b2bdd1SGireesh Nagabhushana * 1 or 2 free lists and an interrupt, all other ingress queues lack these 518956b2bdd1SGireesh Nagabhushana * capabilities 519056b2bdd1SGireesh Nagabhushana */ 519156b2bdd1SGireesh Nagabhushana enum fw_iq_type { 519256b2bdd1SGireesh Nagabhushana FW_IQ_TYPE_FL_INT_CAP, 51933dde7c95SVishal Kulkarni FW_IQ_TYPE_NO_FL_INT_CAP, 51943dde7c95SVishal Kulkarni FW_IQ_TYPE_VF_CQ 519556b2bdd1SGireesh Nagabhushana }; 519656b2bdd1SGireesh Nagabhushana 5197*7e6ad469SVishal Kulkarni enum fw_iq_iqtype { 5198*7e6ad469SVishal Kulkarni FW_IQ_IQTYPE_OTHER, 5199*7e6ad469SVishal Kulkarni FW_IQ_IQTYPE_NIC, 5200*7e6ad469SVishal Kulkarni FW_IQ_IQTYPE_OFLD, 5201*7e6ad469SVishal Kulkarni }; 5202*7e6ad469SVishal Kulkarni 520356b2bdd1SGireesh Nagabhushana struct fw_iq_cmd { 520456b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 520556b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 520656b2bdd1SGireesh Nagabhushana __be16 physiqid; 520756b2bdd1SGireesh Nagabhushana __be16 iqid; 520856b2bdd1SGireesh Nagabhushana __be16 fl0id; 520956b2bdd1SGireesh Nagabhushana __be16 fl1id; 521056b2bdd1SGireesh Nagabhushana __be32 type_to_iqandstindex; 521156b2bdd1SGireesh Nagabhushana __be16 iqdroprss_to_iqesize; 521256b2bdd1SGireesh Nagabhushana __be16 iqsize; 521356b2bdd1SGireesh Nagabhushana __be64 iqaddr; 521456b2bdd1SGireesh Nagabhushana __be32 iqns_to_fl0congen; 521556b2bdd1SGireesh Nagabhushana __be16 fl0dcaen_to_fl0cidxfthresh; 521656b2bdd1SGireesh Nagabhushana __be16 fl0size; 521756b2bdd1SGireesh Nagabhushana __be64 fl0addr; 521856b2bdd1SGireesh Nagabhushana __be32 fl1cngchmap_to_fl1congen; 521956b2bdd1SGireesh Nagabhushana __be16 fl1dcaen_to_fl1cidxfthresh; 522056b2bdd1SGireesh Nagabhushana __be16 fl1size; 522156b2bdd1SGireesh Nagabhushana __be64 fl1addr; 522256b2bdd1SGireesh Nagabhushana }; 522356b2bdd1SGireesh Nagabhushana 52243dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_PFN 8 52253dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_PFN 0x7 52263dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 52273dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_PFN(x) \ 52283dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 52293dde7c95SVishal Kulkarni 52303dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_VFN 0 52313dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_VFN 0xff 52323dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 52333dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_VFN(x) \ 52343dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 52353dde7c95SVishal Kulkarni 52363dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_ALLOC 31 52373dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_ALLOC 0x1 52383dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 52393dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_ALLOC(x) \ 52403dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 52413dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 52423dde7c95SVishal Kulkarni 52433dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FREE 30 52443dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FREE 0x1 52453dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 52463dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FREE(x) \ 52473dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 52483dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 52493dde7c95SVishal Kulkarni 52503dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_MODIFY 29 52513dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_MODIFY 0x1 52523dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 52533dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_MODIFY(x) \ 52543dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 52553dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 52563dde7c95SVishal Kulkarni 52573dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQSTART 28 52583dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQSTART 0x1 52593dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 52603dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQSTART(x) \ 52613dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 52623dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 52633dde7c95SVishal Kulkarni 52643dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQSTOP 27 52653dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQSTOP 0x1 52663dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 52673dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQSTOP(x) \ 52683dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 52693dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 52703dde7c95SVishal Kulkarni 52713dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_TYPE 29 52723dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_TYPE 0x7 52733dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 52743dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_TYPE(x) \ 52753dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 52763dde7c95SVishal Kulkarni 52773dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQASYNCH 28 52783dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQASYNCH 0x1 52793dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 52803dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQASYNCH(x) \ 52813dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 52823dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 52833dde7c95SVishal Kulkarni 52843dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_VIID 16 52853dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_VIID 0xfff 52863dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 52873dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_VIID(x) \ 52883dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 52893dde7c95SVishal Kulkarni 52903dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANDST 15 52913dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANDST 0x1 52923dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 52933dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANDST(x) \ 52943dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 52953dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 52963dde7c95SVishal Kulkarni 52973dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANUS 14 52983dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANUS 0x1 52993dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 53003dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANUS(x) \ 53013dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 53023dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 53033dde7c95SVishal Kulkarni 53043dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANUD 12 53053dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANUD 0x3 53063dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 53073dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANUD(x) \ 53083dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 53093dde7c95SVishal Kulkarni 53103dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANDSTINDEX 0 53113dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 53123dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 53133dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 53143dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 53153dde7c95SVishal Kulkarni 53163dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQDROPRSS 15 53173dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQDROPRSS 0x1 53183dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 53193dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQDROPRSS(x) \ 53203dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 53213dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 53223dde7c95SVishal Kulkarni 53233dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQGTSMODE 14 53243dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQGTSMODE 0x1 53253dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 53263dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQGTSMODE(x) \ 53273dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 53283dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 53293dde7c95SVishal Kulkarni 53303dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQPCIECH 12 53313dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQPCIECH 0x3 53323dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 53333dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQPCIECH(x) \ 53343dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 53353dde7c95SVishal Kulkarni 53363dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQDCAEN 11 53373dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQDCAEN 0x1 53383dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 53393dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQDCAEN(x) \ 53403dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 53413dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 53423dde7c95SVishal Kulkarni 53433dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQDCACPU 6 53443dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQDCACPU 0x1f 53453dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 53463dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQDCACPU(x) \ 53473dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 53483dde7c95SVishal Kulkarni 53493dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 53503dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 53513dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 53523dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 53533dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 53543dde7c95SVishal Kulkarni 53553dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQO 3 53563dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQO 0x1 53573dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 53583dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQO(x) \ 53593dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 53603dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 53613dde7c95SVishal Kulkarni 53623dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQCPRIO 2 53633dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQCPRIO 0x1 53643dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 53653dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQCPRIO(x) \ 53663dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 53673dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 53683dde7c95SVishal Kulkarni 53693dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQESIZE 0 53703dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQESIZE 0x3 53713dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 53723dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQESIZE(x) \ 53733dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 53743dde7c95SVishal Kulkarni 53753dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQNS 31 53763dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQNS 0x1 53773dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 53783dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQNS(x) \ 53793dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 53803dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 53813dde7c95SVishal Kulkarni 53823dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQRO 30 53833dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQRO 0x1 53843dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 53853dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQRO(x) \ 53863dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 53873dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 53883dde7c95SVishal Kulkarni 53893dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 53903dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 53913dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 53923dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 53933dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 53943dde7c95SVishal Kulkarni 53953dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQFLINTCONGEN 27 53963dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 53973dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 53983dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 53993dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 54003dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 54013dde7c95SVishal Kulkarni 54023dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQFLINTISCSIC 26 54033dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 54043dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 54053dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 54063dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 54073dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 54083dde7c95SVishal Kulkarni 5409*7e6ad469SVishal Kulkarni #define S_FW_IQ_CMD_IQTYPE 24 5410*7e6ad469SVishal Kulkarni #define M_FW_IQ_CMD_IQTYPE 0x3 5411*7e6ad469SVishal Kulkarni #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 5412*7e6ad469SVishal Kulkarni #define G_FW_IQ_CMD_IQTYPE(x) \ 5413*7e6ad469SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 5414*7e6ad469SVishal Kulkarni 54153dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CNGCHMAP 20 54163dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 54173dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 54183dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 54193dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 54203dde7c95SVishal Kulkarni 54213dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CONGDROP 16 54223dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CONGDROP 0x1 54233dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 54243dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 54253dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 54263dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 54273dde7c95SVishal Kulkarni 54283dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CACHELOCK 15 54293dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 54303dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 54313dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 54323dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 54333dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 54343dde7c95SVishal Kulkarni 54353dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DBP 14 54363dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DBP 0x1 54373dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 54383dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DBP(x) \ 54393dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 54403dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 54413dde7c95SVishal Kulkarni 54423dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DATANS 13 54433dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DATANS 0x1 54443dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 54453dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DATANS(x) \ 54463dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 54473dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 54483dde7c95SVishal Kulkarni 54493dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DATARO 12 54503dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DATARO 0x1 54513dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 54523dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DATARO(x) \ 54533dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 54543dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 54553dde7c95SVishal Kulkarni 54563dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CONGCIF 11 54573dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CONGCIF 0x1 54583dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 54593dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 54603dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 54613dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 54623dde7c95SVishal Kulkarni 54633dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0ONCHIP 10 54643dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0ONCHIP 0x1 54653dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 54663dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 54673dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 54683dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 54693dde7c95SVishal Kulkarni 54703dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0STATUSPGNS 9 54713dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 54723dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 54733dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 54743dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 54753dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 54763dde7c95SVishal Kulkarni 54773dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0STATUSPGRO 8 54783dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 54793dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 54803dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 54813dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 54823dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 54833dde7c95SVishal Kulkarni 54843dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FETCHNS 7 54853dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FETCHNS 0x1 54863dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 54873dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 54883dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 54893dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 54903dde7c95SVishal Kulkarni 54913dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FETCHRO 6 54923dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FETCHRO 0x1 54933dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 54943dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 54953dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 54963dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 54973dde7c95SVishal Kulkarni 54983dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 54993dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 55003dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 55013dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 55023dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 55033dde7c95SVishal Kulkarni 55043dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CPRIO 3 55053dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CPRIO 0x1 55063dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 55073dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CPRIO(x) \ 55083dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 55093dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 55103dde7c95SVishal Kulkarni 55113dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0PADEN 2 55123dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0PADEN 0x1 55133dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 55143dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0PADEN(x) \ 55153dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 55163dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 55173dde7c95SVishal Kulkarni 55183dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0PACKEN 1 55193dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0PACKEN 0x1 55203dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 55213dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0PACKEN(x) \ 55223dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 55233dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 55243dde7c95SVishal Kulkarni 55253dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CONGEN 0 55263dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CONGEN 0x1 55273dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 55283dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CONGEN(x) \ 55293dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 55303dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 55313dde7c95SVishal Kulkarni 55323dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DCAEN 15 55333dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DCAEN 0x1 55343dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 55353dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DCAEN(x) \ 55363dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 55373dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 55383dde7c95SVishal Kulkarni 55393dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DCACPU 10 55403dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DCACPU 0x1f 55413dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 55423dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DCACPU(x) \ 55433dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 55443dde7c95SVishal Kulkarni 55453dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FBMIN 7 55463dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FBMIN 0x7 55473dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 55483dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FBMIN(x) \ 55493dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 55503dde7c95SVishal Kulkarni 55513dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FBMAX 4 55523dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FBMAX 0x7 55533dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 55543dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FBMAX(x) \ 55553dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 55563dde7c95SVishal Kulkarni 55573dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 55583dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 55593dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 55603dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 55613dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 55623dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 55633dde7c95SVishal Kulkarni 55643dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 55653dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 55663dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 55673dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 55683dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 55693dde7c95SVishal Kulkarni 55703dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CNGCHMAP 20 55713dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 55723dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 55733dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 55743dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 55753dde7c95SVishal Kulkarni 55763dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CONGDROP 16 55773dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CONGDROP 0x1 55783dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 55793dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 55803dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 55813dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 55823dde7c95SVishal Kulkarni 55833dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CACHELOCK 15 55843dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 55853dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 55863dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 55873dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 55883dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 55893dde7c95SVishal Kulkarni 55903dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DBP 14 55913dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DBP 0x1 55923dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 55933dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DBP(x) \ 55943dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 55953dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 55963dde7c95SVishal Kulkarni 55973dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DATANS 13 55983dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DATANS 0x1 55993dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 56003dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DATANS(x) \ 56013dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 56023dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 56033dde7c95SVishal Kulkarni 56043dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DATARO 12 56053dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DATARO 0x1 56063dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 56073dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DATARO(x) \ 56083dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 56093dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 56103dde7c95SVishal Kulkarni 56113dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CONGCIF 11 56123dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CONGCIF 0x1 56133dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 56143dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 56153dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 56163dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 56173dde7c95SVishal Kulkarni 56183dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1ONCHIP 10 56193dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1ONCHIP 0x1 56203dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 56213dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 56223dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 56233dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 56243dde7c95SVishal Kulkarni 56253dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1STATUSPGNS 9 56263dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 56273dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 56283dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 56293dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 56303dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 56313dde7c95SVishal Kulkarni 56323dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1STATUSPGRO 8 56333dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 56343dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 56353dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 56363dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 56373dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 56383dde7c95SVishal Kulkarni 56393dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FETCHNS 7 56403dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FETCHNS 0x1 56413dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 56423dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 56433dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 56443dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 56453dde7c95SVishal Kulkarni 56463dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FETCHRO 6 56473dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FETCHRO 0x1 56483dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 56493dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 56503dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 56513dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 56523dde7c95SVishal Kulkarni 56533dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 56543dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 56553dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 56563dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 56573dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 56583dde7c95SVishal Kulkarni 56593dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CPRIO 3 56603dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CPRIO 0x1 56613dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 56623dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CPRIO(x) \ 56633dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 56643dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 56653dde7c95SVishal Kulkarni 56663dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1PADEN 2 56673dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1PADEN 0x1 56683dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 56693dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1PADEN(x) \ 56703dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 56713dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 56723dde7c95SVishal Kulkarni 56733dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1PACKEN 1 56743dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1PACKEN 0x1 56753dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 56763dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1PACKEN(x) \ 56773dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 56783dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 56793dde7c95SVishal Kulkarni 56803dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CONGEN 0 56813dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CONGEN 0x1 56823dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 56833dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CONGEN(x) \ 56843dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 56853dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 56863dde7c95SVishal Kulkarni 56873dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DCAEN 15 56883dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DCAEN 0x1 56893dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 56903dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DCAEN(x) \ 56913dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 56923dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 56933dde7c95SVishal Kulkarni 56943dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DCACPU 10 56953dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DCACPU 0x1f 56963dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 56973dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DCACPU(x) \ 56983dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 56993dde7c95SVishal Kulkarni 57003dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FBMIN 7 57013dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FBMIN 0x7 57023dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 57033dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FBMIN(x) \ 57043dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 57053dde7c95SVishal Kulkarni 57063dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FBMAX 4 57073dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FBMAX 0x7 57083dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 57093dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FBMAX(x) \ 57103dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 57113dde7c95SVishal Kulkarni 57123dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 57133dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 57143dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 57153dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 57163dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 57173dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 57183dde7c95SVishal Kulkarni 57193dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 57203dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 57213dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 57223dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 57233dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 572456b2bdd1SGireesh Nagabhushana 572556b2bdd1SGireesh Nagabhushana struct fw_eq_mngt_cmd { 572656b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 572756b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 572856b2bdd1SGireesh Nagabhushana __be32 cmpliqid_eqid; 572956b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 573056b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 573156b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 573256b2bdd1SGireesh Nagabhushana __be64 eqaddr; 573356b2bdd1SGireesh Nagabhushana }; 573456b2bdd1SGireesh Nagabhushana 57353dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_PFN 8 57363dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_PFN 0x7 57373dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 57383dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_PFN(x) \ 57393dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 57403dde7c95SVishal Kulkarni 57413dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_VFN 0 57423dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_VFN 0xff 57433dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 57443dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_VFN(x) \ 57453dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 57463dde7c95SVishal Kulkarni 57473dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_ALLOC 31 57483dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 57493dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 57503dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 57513dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 57523dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 57533dde7c95SVishal Kulkarni 57543dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FREE 30 57553dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FREE 0x1 57563dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 57573dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FREE(x) \ 57583dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 57593dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 57603dde7c95SVishal Kulkarni 57613dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_MODIFY 29 57623dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 57633dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 57643dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 57653dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 57663dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 57673dde7c95SVishal Kulkarni 57683dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQSTART 28 57693dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 57703dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 57713dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 57723dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 57733dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 57743dde7c95SVishal Kulkarni 57753dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQSTOP 27 57763dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 57773dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 57783dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 57793dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 57803dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 57813dde7c95SVishal Kulkarni 57823dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 57833dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 57843dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 57853dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 57863dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 57873dde7c95SVishal Kulkarni 57883dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQID 0 57893dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 57903dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 57913dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQID(x) \ 57923dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 57933dde7c95SVishal Kulkarni 57943dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 57953dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 57963dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 57973dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 57983dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 57993dde7c95SVishal Kulkarni 58003dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 58013dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 58023dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 58033dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 58043dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 58053dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 58063dde7c95SVishal Kulkarni 58073dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 58083dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 58093dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 58103dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 58113dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 58123dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 58133dde7c95SVishal Kulkarni 58143dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 58153dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 58163dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 58173dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 58183dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 58193dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 58203dde7c95SVishal Kulkarni 58213dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FETCHNS 23 58223dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 58233dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 58243dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 58253dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 58263dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 58273dde7c95SVishal Kulkarni 58283dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FETCHRO 22 58293dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 58303dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 58313dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 58323dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 58333dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 58343dde7c95SVishal Kulkarni 58353dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 58363dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 58373dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 58383dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 58393dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 58403dde7c95SVishal Kulkarni 58413dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CPRIO 19 58423dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 58433dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 58443dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 58453dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 58463dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 58473dde7c95SVishal Kulkarni 58483dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_ONCHIP 18 58493dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 58503dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 58513dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 58523dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 58533dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 58543dde7c95SVishal Kulkarni 58553dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_PCIECHN 16 58563dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 58573dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 58583dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 58593dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 58603dde7c95SVishal Kulkarni 58613dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_IQID 0 58623dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_IQID 0xffff 58633dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 58643dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_IQID(x) \ 58653dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 58663dde7c95SVishal Kulkarni 58673dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_DCAEN 31 58683dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 58693dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 58703dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 58713dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 58723dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 58733dde7c95SVishal Kulkarni 58743dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_DCACPU 26 58753dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 58763dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 58773dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 58783dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 58793dde7c95SVishal Kulkarni 58803dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FBMIN 23 58813dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 58823dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 58833dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 58843dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 58853dde7c95SVishal Kulkarni 58863dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FBMAX 20 58873dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 58883dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 58893dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 58903dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 58913dde7c95SVishal Kulkarni 58923dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 58933dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 58943dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 58953dde7c95SVishal Kulkarni ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 58963dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 58973dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 58983dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 58993dde7c95SVishal Kulkarni 59003dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 59013dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 59023dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 59033dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 59043dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 59053dde7c95SVishal Kulkarni 59063dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQSIZE 0 59073dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 59083dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 59093dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 59103dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 591156b2bdd1SGireesh Nagabhushana 591256b2bdd1SGireesh Nagabhushana struct fw_eq_eth_cmd { 591356b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 591456b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 591556b2bdd1SGireesh Nagabhushana __be32 eqid_pkd; 591656b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 591756b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 591856b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 591956b2bdd1SGireesh Nagabhushana __be64 eqaddr; 59203dde7c95SVishal Kulkarni __be32 autoequiqe_to_viid; 5921*7e6ad469SVishal Kulkarni __be32 timeren_timerix; 592256b2bdd1SGireesh Nagabhushana __be64 r9; 592356b2bdd1SGireesh Nagabhushana }; 592456b2bdd1SGireesh Nagabhushana 59253dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_PFN 8 59263dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_PFN 0x7 59273dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 59283dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_PFN(x) \ 59293dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 59303dde7c95SVishal Kulkarni 59313dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_VFN 0 59323dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_VFN 0xff 59333dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 59343dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_VFN(x) \ 59353dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 59363dde7c95SVishal Kulkarni 59373dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_ALLOC 31 59383dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_ALLOC 0x1 59393dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 59403dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 59413dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 59423dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 59433dde7c95SVishal Kulkarni 59443dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FREE 30 59453dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FREE 0x1 59463dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 59473dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FREE(x) \ 59483dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 59493dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 59503dde7c95SVishal Kulkarni 59513dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_MODIFY 29 59523dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_MODIFY 0x1 59533dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 59543dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 59553dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 59563dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 59573dde7c95SVishal Kulkarni 59583dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQSTART 28 59593dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQSTART 0x1 59603dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 59613dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 59623dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 59633dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 59643dde7c95SVishal Kulkarni 59653dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQSTOP 27 59663dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 59673dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 59683dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 59693dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 59703dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 59713dde7c95SVishal Kulkarni 59723dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQID 0 59733dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQID 0xfffff 59743dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 59753dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQID(x) \ 59763dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 59773dde7c95SVishal Kulkarni 59783dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_PHYSEQID 0 59793dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 59803dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 59813dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 59823dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 59833dde7c95SVishal Kulkarni 59843dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FETCHSZM 26 59853dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 59863dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 59873dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 59883dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 59893dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 59903dde7c95SVishal Kulkarni 59913dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 59923dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 59933dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 59943dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 59953dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 59963dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 59973dde7c95SVishal Kulkarni 59983dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 59993dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 60003dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 60013dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 60023dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 60033dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 60043dde7c95SVishal Kulkarni 60053dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FETCHNS 23 60063dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 60073dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 60083dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 60093dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 60103dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 60113dde7c95SVishal Kulkarni 60123dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FETCHRO 22 60133dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 60143dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 60153dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 60163dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 60173dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 60183dde7c95SVishal Kulkarni 60193dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 60203dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 60213dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 60223dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 60233dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 60243dde7c95SVishal Kulkarni 60253dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_CPRIO 19 60263dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_CPRIO 0x1 60273dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 60283dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 60293dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 60303dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 60313dde7c95SVishal Kulkarni 60323dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_ONCHIP 18 60333dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 60343dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 60353dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 60363dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 60373dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 60383dde7c95SVishal Kulkarni 60393dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_PCIECHN 16 60403dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 60413dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 60423dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 60433dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 60443dde7c95SVishal Kulkarni 60453dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_IQID 0 60463dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_IQID 0xffff 60473dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 60483dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_IQID(x) \ 60493dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 60503dde7c95SVishal Kulkarni 60513dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_DCAEN 31 60523dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_DCAEN 0x1 60533dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 60543dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 60553dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 60563dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 60573dde7c95SVishal Kulkarni 60583dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_DCACPU 26 60593dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 60603dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 60613dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 60623dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 60633dde7c95SVishal Kulkarni 60643dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FBMIN 23 60653dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FBMIN 0x7 60663dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 60673dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 60683dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 60693dde7c95SVishal Kulkarni 60703dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FBMAX 20 60713dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FBMAX 0x7 60723dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 60733dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 60743dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 60753dde7c95SVishal Kulkarni 60763dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 60773dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 60783dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 60793dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 60803dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 60813dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 60823dde7c95SVishal Kulkarni 60833dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 60843dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 60853dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 60863dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 60873dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 60883dde7c95SVishal Kulkarni 60893dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQSIZE 0 60903dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 60913dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 60923dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 60933dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 60943dde7c95SVishal Kulkarni 60953dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 60963dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 60973dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 60983dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 60993dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 61003dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 61013dde7c95SVishal Kulkarni 61023dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 61033dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 61043dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 61053dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 61063dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 61073dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 61083dde7c95SVishal Kulkarni 61093dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_VIID 16 61103dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_VIID 0xfff 61113dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 61123dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_VIID(x) \ 61133dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 611456b2bdd1SGireesh Nagabhushana 6115*7e6ad469SVishal Kulkarni #define S_FW_EQ_ETH_CMD_TIMEREN 3 6116*7e6ad469SVishal Kulkarni #define M_FW_EQ_ETH_CMD_TIMEREN 0x1 6117*7e6ad469SVishal Kulkarni #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN) 6118*7e6ad469SVishal Kulkarni #define G_FW_EQ_ETH_CMD_TIMEREN(x) \ 6119*7e6ad469SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN) 6120*7e6ad469SVishal Kulkarni #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U) 6121*7e6ad469SVishal Kulkarni 6122*7e6ad469SVishal Kulkarni #define S_FW_EQ_ETH_CMD_TIMERIX 0 6123*7e6ad469SVishal Kulkarni #define M_FW_EQ_ETH_CMD_TIMERIX 0x7 6124*7e6ad469SVishal Kulkarni #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX) 6125*7e6ad469SVishal Kulkarni #define G_FW_EQ_ETH_CMD_TIMERIX(x) \ 6126*7e6ad469SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX) 6127*7e6ad469SVishal Kulkarni 612856b2bdd1SGireesh Nagabhushana struct fw_eq_ctrl_cmd { 612956b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 613056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 613156b2bdd1SGireesh Nagabhushana __be32 cmpliqid_eqid; 613256b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 613356b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 613456b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 613556b2bdd1SGireesh Nagabhushana __be64 eqaddr; 613656b2bdd1SGireesh Nagabhushana }; 613756b2bdd1SGireesh Nagabhushana 61383dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_PFN 8 61393dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_PFN 0x7 61403dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 61413dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_PFN(x) \ 61423dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 61433dde7c95SVishal Kulkarni 61443dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_VFN 0 61453dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_VFN 0xff 61463dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 61473dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_VFN(x) \ 61483dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 61493dde7c95SVishal Kulkarni 61503dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_ALLOC 31 61513dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 61523dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 61533dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 61543dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 61553dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 61563dde7c95SVishal Kulkarni 61573dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FREE 30 61583dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FREE 0x1 61593dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 61603dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FREE(x) \ 61613dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 61623dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 61633dde7c95SVishal Kulkarni 61643dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_MODIFY 29 61653dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 61663dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 61673dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 61683dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 61693dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 61703dde7c95SVishal Kulkarni 61713dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQSTART 28 61723dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 61733dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 61743dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 61753dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 61763dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 61773dde7c95SVishal Kulkarni 61783dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQSTOP 27 61793dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 61803dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 61813dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 61823dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 61833dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 61843dde7c95SVishal Kulkarni 61853dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 61863dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 61873dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 61883dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 61893dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 61903dde7c95SVishal Kulkarni 61913dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQID 0 61923dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 61933dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 61943dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQID(x) \ 61953dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 61963dde7c95SVishal Kulkarni 61973dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 61983dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 61993dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 62003dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 62013dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 62023dde7c95SVishal Kulkarni 62033dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 62043dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 62053dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 62063dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 62073dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 62083dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 62093dde7c95SVishal Kulkarni 62103dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 62113dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 62123dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 62133dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 62143dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 62153dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 62163dde7c95SVishal Kulkarni 62173dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 62183dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 62193dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 62203dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 62213dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 62223dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 62233dde7c95SVishal Kulkarni 62243dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FETCHNS 23 62253dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 62263dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 62273dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 62283dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 62293dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 62303dde7c95SVishal Kulkarni 62313dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FETCHRO 22 62323dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 62333dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 62343dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 62353dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 62363dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 62373dde7c95SVishal Kulkarni 62383dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 62393dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 62403dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 62413dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 62423dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 62433dde7c95SVishal Kulkarni 62443dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CPRIO 19 62453dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 62463dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 62473dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 62483dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 62493dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 62503dde7c95SVishal Kulkarni 62513dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_ONCHIP 18 62523dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 62533dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 62543dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 62553dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 62563dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 62573dde7c95SVishal Kulkarni 62583dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_PCIECHN 16 62593dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 62603dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 62613dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 62623dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 62633dde7c95SVishal Kulkarni 62643dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_IQID 0 62653dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_IQID 0xffff 62663dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 62673dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_IQID(x) \ 62683dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 62693dde7c95SVishal Kulkarni 62703dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_DCAEN 31 62713dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 62723dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 62733dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 62743dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 62753dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 62763dde7c95SVishal Kulkarni 62773dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_DCACPU 26 62783dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 62793dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 62803dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 62813dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 62823dde7c95SVishal Kulkarni 62833dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FBMIN 23 62843dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 62853dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 62863dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 62873dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 62883dde7c95SVishal Kulkarni 62893dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FBMAX 20 62903dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 62913dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 62923dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 62933dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 62943dde7c95SVishal Kulkarni 62953dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 62963dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 62973dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 62983dde7c95SVishal Kulkarni ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 62993dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 63003dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 63013dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 63023dde7c95SVishal Kulkarni 63033dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 63043dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 63053dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 63063dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 63073dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 63083dde7c95SVishal Kulkarni 63093dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQSIZE 0 63103dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 63113dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 63123dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 63133dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 631456b2bdd1SGireesh Nagabhushana 631556b2bdd1SGireesh Nagabhushana struct fw_eq_ofld_cmd { 631656b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 631756b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 631856b2bdd1SGireesh Nagabhushana __be32 eqid_pkd; 631956b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 632056b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 632156b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 632256b2bdd1SGireesh Nagabhushana __be64 eqaddr; 632356b2bdd1SGireesh Nagabhushana }; 632456b2bdd1SGireesh Nagabhushana 63253dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_PFN 8 63263dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_PFN 0x7 63273dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 63283dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_PFN(x) \ 63293dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 63303dde7c95SVishal Kulkarni 63313dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_VFN 0 63323dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_VFN 0xff 63333dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 63343dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_VFN(x) \ 63353dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 63363dde7c95SVishal Kulkarni 63373dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_ALLOC 31 63383dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 63393dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 63403dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 63413dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 63423dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 63433dde7c95SVishal Kulkarni 63443dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FREE 30 63453dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FREE 0x1 63463dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 63473dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FREE(x) \ 63483dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 63493dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 63503dde7c95SVishal Kulkarni 63513dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_MODIFY 29 63523dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 63533dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 63543dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 63553dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 63563dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 63573dde7c95SVishal Kulkarni 63583dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQSTART 28 63593dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 63603dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 63613dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 63623dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 63633dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 63643dde7c95SVishal Kulkarni 63653dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQSTOP 27 63663dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 63673dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 63683dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 63693dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 63703dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 63713dde7c95SVishal Kulkarni 63723dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQID 0 63733dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 63743dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 63753dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQID(x) \ 63763dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 63773dde7c95SVishal Kulkarni 63783dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 63793dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 63803dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 63813dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 63823dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 63833dde7c95SVishal Kulkarni 63843dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 63853dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 63863dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 63873dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 63883dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 63893dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 63903dde7c95SVishal Kulkarni 63913dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 63923dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 63933dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 63943dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 63953dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 63963dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 63973dde7c95SVishal Kulkarni 63983dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 63993dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 64003dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 64013dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 64023dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 64033dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 64043dde7c95SVishal Kulkarni 64053dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FETCHNS 23 64063dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 64073dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 64083dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 64093dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 64103dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 64113dde7c95SVishal Kulkarni 64123dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FETCHRO 22 64133dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 64143dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 64153dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 64163dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 64173dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 64183dde7c95SVishal Kulkarni 64193dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 64203dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 64213dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 64223dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 64233dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 64243dde7c95SVishal Kulkarni 64253dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_CPRIO 19 64263dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 64273dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 64283dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 64293dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 64303dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 64313dde7c95SVishal Kulkarni 64323dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_ONCHIP 18 64333dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 64343dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 64353dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 64363dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 64373dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 64383dde7c95SVishal Kulkarni 64393dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_PCIECHN 16 64403dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 64413dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 64423dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 64433dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 64443dde7c95SVishal Kulkarni 64453dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_IQID 0 64463dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_IQID 0xffff 64473dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 64483dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_IQID(x) \ 64493dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 64503dde7c95SVishal Kulkarni 64513dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_DCAEN 31 64523dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 64533dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 64543dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 64553dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 64563dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 64573dde7c95SVishal Kulkarni 64583dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_DCACPU 26 64593dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 64603dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 64613dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 64623dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 64633dde7c95SVishal Kulkarni 64643dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FBMIN 23 64653dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 64663dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 64673dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 64683dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 64693dde7c95SVishal Kulkarni 64703dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FBMAX 20 64713dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 64723dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 64733dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 64743dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 64753dde7c95SVishal Kulkarni 64763dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 64773dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 64783dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 64793dde7c95SVishal Kulkarni ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 64803dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 64813dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 64823dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 64833dde7c95SVishal Kulkarni 64843dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 64853dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 64863dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 64873dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 64883dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 64893dde7c95SVishal Kulkarni 64903dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQSIZE 0 64913dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 64923dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 64933dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 64943dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 64953dde7c95SVishal Kulkarni 64963dde7c95SVishal Kulkarni /* Macros for VIID parsing: 64973dde7c95SVishal Kulkarni VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 64983dde7c95SVishal Kulkarni #define S_FW_VIID_PFN 8 64993dde7c95SVishal Kulkarni #define M_FW_VIID_PFN 0x7 65003dde7c95SVishal Kulkarni #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 65013dde7c95SVishal Kulkarni #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 65023dde7c95SVishal Kulkarni 65033dde7c95SVishal Kulkarni #define S_FW_VIID_VIVLD 7 65043dde7c95SVishal Kulkarni #define M_FW_VIID_VIVLD 0x1 65053dde7c95SVishal Kulkarni #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 65063dde7c95SVishal Kulkarni #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 65073dde7c95SVishal Kulkarni 65083dde7c95SVishal Kulkarni #define S_FW_VIID_VIN 0 65093dde7c95SVishal Kulkarni #define M_FW_VIID_VIN 0x7F 65103dde7c95SVishal Kulkarni #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 65113dde7c95SVishal Kulkarni #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 651256b2bdd1SGireesh Nagabhushana 6513*7e6ad469SVishal Kulkarni /* Macros for VIID parsing: 6514*7e6ad469SVishal Kulkarni VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 6515*7e6ad469SVishal Kulkarni #define S_FW_256VIID_PFN 9 6516*7e6ad469SVishal Kulkarni #define M_FW_256VIID_PFN 0x7 6517*7e6ad469SVishal Kulkarni #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 6518*7e6ad469SVishal Kulkarni #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 6519*7e6ad469SVishal Kulkarni 6520*7e6ad469SVishal Kulkarni #define S_FW_256VIID_VIVLD 8 6521*7e6ad469SVishal Kulkarni #define M_FW_256VIID_VIVLD 0x1 6522*7e6ad469SVishal Kulkarni #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 6523*7e6ad469SVishal Kulkarni #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 6524*7e6ad469SVishal Kulkarni 6525*7e6ad469SVishal Kulkarni #define S_FW_256VIID_VIN 0 6526*7e6ad469SVishal Kulkarni #define M_FW_256VIID_VIN 0xFF 6527*7e6ad469SVishal Kulkarni #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 6528*7e6ad469SVishal Kulkarni #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 6529*7e6ad469SVishal Kulkarni 653056b2bdd1SGireesh Nagabhushana enum fw_vi_func { 653156b2bdd1SGireesh Nagabhushana FW_VI_FUNC_ETH, 653256b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OFLD, 653356b2bdd1SGireesh Nagabhushana FW_VI_FUNC_IWARP, 653456b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OPENISCSI, 653556b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OPENFCOE, 653656b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FOISCSI, 653756b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FOFCOE, 653856b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FW, 653956b2bdd1SGireesh Nagabhushana }; 654056b2bdd1SGireesh Nagabhushana 654156b2bdd1SGireesh Nagabhushana struct fw_vi_cmd { 654256b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 654356b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 654456b2bdd1SGireesh Nagabhushana __be16 type_to_viid; 654556b2bdd1SGireesh Nagabhushana __u8 mac[6]; 654656b2bdd1SGireesh Nagabhushana __u8 portid_pkd; 654756b2bdd1SGireesh Nagabhushana __u8 nmac; 654856b2bdd1SGireesh Nagabhushana __u8 nmac0[6]; 6549de483253SVishal Kulkarni __be16 norss_rsssize; 655056b2bdd1SGireesh Nagabhushana __u8 nmac1[6]; 655156b2bdd1SGireesh Nagabhushana __be16 idsiiq_pkd; 655256b2bdd1SGireesh Nagabhushana __u8 nmac2[6]; 655356b2bdd1SGireesh Nagabhushana __be16 idseiq_pkd; 655456b2bdd1SGireesh Nagabhushana __u8 nmac3[6]; 655556b2bdd1SGireesh Nagabhushana __be64 r9; 655656b2bdd1SGireesh Nagabhushana __be64 r10; 655756b2bdd1SGireesh Nagabhushana }; 655856b2bdd1SGireesh Nagabhushana 65593dde7c95SVishal Kulkarni #define S_FW_VI_CMD_PFN 8 65603dde7c95SVishal Kulkarni #define M_FW_VI_CMD_PFN 0x7 65613dde7c95SVishal Kulkarni #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 65623dde7c95SVishal Kulkarni #define G_FW_VI_CMD_PFN(x) \ 65633dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 65643dde7c95SVishal Kulkarni 65653dde7c95SVishal Kulkarni #define S_FW_VI_CMD_VFN 0 65663dde7c95SVishal Kulkarni #define M_FW_VI_CMD_VFN 0xff 65673dde7c95SVishal Kulkarni #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 65683dde7c95SVishal Kulkarni #define G_FW_VI_CMD_VFN(x) \ 65693dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 65703dde7c95SVishal Kulkarni 65713dde7c95SVishal Kulkarni #define S_FW_VI_CMD_ALLOC 31 65723dde7c95SVishal Kulkarni #define M_FW_VI_CMD_ALLOC 0x1 65733dde7c95SVishal Kulkarni #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 65743dde7c95SVishal Kulkarni #define G_FW_VI_CMD_ALLOC(x) \ 65753dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 65763dde7c95SVishal Kulkarni #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 65773dde7c95SVishal Kulkarni 65783dde7c95SVishal Kulkarni #define S_FW_VI_CMD_FREE 30 65793dde7c95SVishal Kulkarni #define M_FW_VI_CMD_FREE 0x1 65803dde7c95SVishal Kulkarni #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 65813dde7c95SVishal Kulkarni #define G_FW_VI_CMD_FREE(x) \ 65823dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 65833dde7c95SVishal Kulkarni #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 65843dde7c95SVishal Kulkarni 6585*7e6ad469SVishal Kulkarni #define S_FW_VI_CMD_VFVLD 24 6586*7e6ad469SVishal Kulkarni #define M_FW_VI_CMD_VFVLD 0x1 6587*7e6ad469SVishal Kulkarni #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD) 6588*7e6ad469SVishal Kulkarni #define G_FW_VI_CMD_VFVLD(x) \ 6589*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 6590*7e6ad469SVishal Kulkarni #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U) 6591*7e6ad469SVishal Kulkarni 6592*7e6ad469SVishal Kulkarni #define S_FW_VI_CMD_VIN 16 6593*7e6ad469SVishal Kulkarni #define M_FW_VI_CMD_VIN 0xff 6594*7e6ad469SVishal Kulkarni #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN) 6595*7e6ad469SVishal Kulkarni #define G_FW_VI_CMD_VIN(x) \ 6596*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 6597*7e6ad469SVishal Kulkarni 65983dde7c95SVishal Kulkarni #define S_FW_VI_CMD_TYPE 15 65993dde7c95SVishal Kulkarni #define M_FW_VI_CMD_TYPE 0x1 66003dde7c95SVishal Kulkarni #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 66013dde7c95SVishal Kulkarni #define G_FW_VI_CMD_TYPE(x) \ 66023dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 66033dde7c95SVishal Kulkarni #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 66043dde7c95SVishal Kulkarni 66053dde7c95SVishal Kulkarni #define S_FW_VI_CMD_FUNC 12 66063dde7c95SVishal Kulkarni #define M_FW_VI_CMD_FUNC 0x7 66073dde7c95SVishal Kulkarni #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 66083dde7c95SVishal Kulkarni #define G_FW_VI_CMD_FUNC(x) \ 66093dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 66103dde7c95SVishal Kulkarni 66113dde7c95SVishal Kulkarni #define S_FW_VI_CMD_VIID 0 66123dde7c95SVishal Kulkarni #define M_FW_VI_CMD_VIID 0xfff 66133dde7c95SVishal Kulkarni #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 66143dde7c95SVishal Kulkarni #define G_FW_VI_CMD_VIID(x) \ 66153dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 66163dde7c95SVishal Kulkarni 66173dde7c95SVishal Kulkarni #define S_FW_VI_CMD_PORTID 4 66183dde7c95SVishal Kulkarni #define M_FW_VI_CMD_PORTID 0xf 66193dde7c95SVishal Kulkarni #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 66203dde7c95SVishal Kulkarni #define G_FW_VI_CMD_PORTID(x) \ 66213dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 66223dde7c95SVishal Kulkarni 66233dde7c95SVishal Kulkarni #define S_FW_VI_CMD_NORSS 11 66243dde7c95SVishal Kulkarni #define M_FW_VI_CMD_NORSS 0x1 66253dde7c95SVishal Kulkarni #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 66263dde7c95SVishal Kulkarni #define G_FW_VI_CMD_NORSS(x) \ 6627de483253SVishal Kulkarni (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 66283dde7c95SVishal Kulkarni #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 66293dde7c95SVishal Kulkarni 66303dde7c95SVishal Kulkarni #define S_FW_VI_CMD_RSSSIZE 0 66313dde7c95SVishal Kulkarni #define M_FW_VI_CMD_RSSSIZE 0x7ff 66323dde7c95SVishal Kulkarni #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 66333dde7c95SVishal Kulkarni #define G_FW_VI_CMD_RSSSIZE(x) \ 66343dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 66353dde7c95SVishal Kulkarni 66363dde7c95SVishal Kulkarni #define S_FW_VI_CMD_IDSIIQ 0 66373dde7c95SVishal Kulkarni #define M_FW_VI_CMD_IDSIIQ 0x3ff 66383dde7c95SVishal Kulkarni #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 66393dde7c95SVishal Kulkarni #define G_FW_VI_CMD_IDSIIQ(x) \ 66403dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 66413dde7c95SVishal Kulkarni 66423dde7c95SVishal Kulkarni #define S_FW_VI_CMD_IDSEIQ 0 66433dde7c95SVishal Kulkarni #define M_FW_VI_CMD_IDSEIQ 0x3ff 66443dde7c95SVishal Kulkarni #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 66453dde7c95SVishal Kulkarni #define G_FW_VI_CMD_IDSEIQ(x) \ 66463dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 664756b2bdd1SGireesh Nagabhushana 664856b2bdd1SGireesh Nagabhushana /* Special VI_MAC command index ids */ 66493dde7c95SVishal Kulkarni #define FW_VI_MAC_ADD_MAC 0x3FF 66503dde7c95SVishal Kulkarni #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 66513dde7c95SVishal Kulkarni #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6652*7e6ad469SVishal Kulkarni #define FW_VI_MAC_ID_BASED_FREE 0x3FC 665356b2bdd1SGireesh Nagabhushana 665456b2bdd1SGireesh Nagabhushana enum fw_vi_mac_smac { 665556b2bdd1SGireesh Nagabhushana FW_VI_MAC_MPS_TCAM_ENTRY, 665656b2bdd1SGireesh Nagabhushana FW_VI_MAC_MPS_TCAM_ONLY, 665756b2bdd1SGireesh Nagabhushana FW_VI_MAC_SMT_ONLY, 665856b2bdd1SGireesh Nagabhushana FW_VI_MAC_SMT_AND_MPSTCAM 665956b2bdd1SGireesh Nagabhushana }; 666056b2bdd1SGireesh Nagabhushana 666156b2bdd1SGireesh Nagabhushana enum fw_vi_mac_result { 666256b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_SUCCESS, 666356b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 666456b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_SMAC_FAIL, 666556b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_F_ACL_CHECK 666656b2bdd1SGireesh Nagabhushana }; 666756b2bdd1SGireesh Nagabhushana 66683dde7c95SVishal Kulkarni enum fw_vi_mac_entry_types { 66693dde7c95SVishal Kulkarni FW_VI_MAC_TYPE_EXACTMAC, 66703dde7c95SVishal Kulkarni FW_VI_MAC_TYPE_HASHVEC, 66713dde7c95SVishal Kulkarni FW_VI_MAC_TYPE_RAW, 6672*7e6ad469SVishal Kulkarni FW_VI_MAC_TYPE_EXACTMAC_VNI, 66733dde7c95SVishal Kulkarni }; 66743dde7c95SVishal Kulkarni 667556b2bdd1SGireesh Nagabhushana struct fw_vi_mac_cmd { 667656b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 667756b2bdd1SGireesh Nagabhushana __be32 freemacs_to_len16; 667856b2bdd1SGireesh Nagabhushana union fw_vi_mac { 667956b2bdd1SGireesh Nagabhushana struct fw_vi_mac_exact { 668056b2bdd1SGireesh Nagabhushana __be16 valid_to_idx; 668156b2bdd1SGireesh Nagabhushana __u8 macaddr[6]; 668256b2bdd1SGireesh Nagabhushana } exact[7]; 668356b2bdd1SGireesh Nagabhushana struct fw_vi_mac_hash { 668456b2bdd1SGireesh Nagabhushana __be64 hashvec; 668556b2bdd1SGireesh Nagabhushana } hash; 66863dde7c95SVishal Kulkarni struct fw_vi_mac_raw { 66873dde7c95SVishal Kulkarni __be32 raw_idx_pkd; 66883dde7c95SVishal Kulkarni __be32 data0_pkd; 66893dde7c95SVishal Kulkarni __be32 data1[2]; 66903dde7c95SVishal Kulkarni __be64 data0m_pkd; 66913dde7c95SVishal Kulkarni __be32 data1m[2]; 66923dde7c95SVishal Kulkarni } raw; 6693*7e6ad469SVishal Kulkarni struct fw_vi_mac_vni { 6694*7e6ad469SVishal Kulkarni __be16 valid_to_idx; 6695*7e6ad469SVishal Kulkarni __u8 macaddr[6]; 6696*7e6ad469SVishal Kulkarni __be16 r7; 6697*7e6ad469SVishal Kulkarni __u8 macaddr_mask[6]; 6698*7e6ad469SVishal Kulkarni __be32 lookup_type_to_vni; 6699*7e6ad469SVishal Kulkarni __be32 vni_mask_pkd; 6700*7e6ad469SVishal Kulkarni } exact_vni[2]; 670156b2bdd1SGireesh Nagabhushana } u; 670256b2bdd1SGireesh Nagabhushana }; 670356b2bdd1SGireesh Nagabhushana 6704*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_SMTID 12 6705*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_SMTID 0xff 6706*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID) 6707*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_SMTID(x) \ 6708*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID) 6709*7e6ad469SVishal Kulkarni 67103dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_VIID 0 67113dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_VIID 0xfff 67123dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 67133dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_VIID(x) \ 67143dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 67153dde7c95SVishal Kulkarni 67163dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_FREEMACS 31 67173dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_FREEMACS 0x1 67183dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 67193dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 67203dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 67213dde7c95SVishal Kulkarni #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 67223dde7c95SVishal Kulkarni 6723*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_IS_SMAC 30 6724*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_IS_SMAC 0x1 6725*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 6726*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 6727*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 6728*7e6ad469SVishal Kulkarni #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 6729*7e6ad469SVishal Kulkarni 67303dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 67313dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 67323dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 67333dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 67343dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 67353dde7c95SVishal Kulkarni 67363dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_HASHUNIEN 22 67373dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 67383dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 67393dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 67403dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 67413dde7c95SVishal Kulkarni #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 67423dde7c95SVishal Kulkarni 67433dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_VALID 15 67443dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_VALID 0x1 67453dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 67463dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_VALID(x) \ 67473dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 67483dde7c95SVishal Kulkarni #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 67493dde7c95SVishal Kulkarni 67503dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_PRIO 12 67513dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_PRIO 0x7 67523dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 67533dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_PRIO(x) \ 67543dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 67553dde7c95SVishal Kulkarni 67563dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 67573dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 67583dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 67593dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 67603dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 67613dde7c95SVishal Kulkarni 67623dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_IDX 0 67633dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_IDX 0x3ff 67643dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 67653dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_IDX(x) \ 67663dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 67673dde7c95SVishal Kulkarni 67683dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_RAW_IDX 16 67693dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 67703dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 67713dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 67723dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 67733dde7c95SVishal Kulkarni 67743dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_DATA0 0 67753dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_DATA0 0xffff 67763dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 67773dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_DATA0(x) \ 67783dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 677956b2bdd1SGireesh Nagabhushana 6780*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6781*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6782*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6783*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6784*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6785*7e6ad469SVishal Kulkarni #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6786*7e6ad469SVishal Kulkarni 6787*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_DIP_HIT 30 6788*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6789*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6790*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6791*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6792*7e6ad469SVishal Kulkarni #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6793*7e6ad469SVishal Kulkarni 6794*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_VNI 0 6795*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_VNI 0xffffff 6796*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6797*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_VNI(x) \ 6798*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6799*7e6ad469SVishal Kulkarni 6800*7e6ad469SVishal Kulkarni /* Extracting loopback port number passed from driver. 6801*7e6ad469SVishal Kulkarni * as a part of fw_vi_mac_vni For non loopback entries 6802*7e6ad469SVishal Kulkarni * ignore the field and update port number from flowc. 6803*7e6ad469SVishal Kulkarni * Fw will ignore if physical port number received. 6804*7e6ad469SVishal Kulkarni * expected range (4-7). 6805*7e6ad469SVishal Kulkarni */ 6806*7e6ad469SVishal Kulkarni 6807*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_PORT 24 6808*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_PORT 0x7 6809*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 6810*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_PORT(x) \ 6811*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 6812*7e6ad469SVishal Kulkarni 6813*7e6ad469SVishal Kulkarni #define S_FW_VI_MAC_CMD_VNI_MASK 0 6814*7e6ad469SVishal Kulkarni #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6815*7e6ad469SVishal Kulkarni #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6816*7e6ad469SVishal Kulkarni #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6817*7e6ad469SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6818*7e6ad469SVishal Kulkarni 681956b2bdd1SGireesh Nagabhushana /* T4 max MTU supported */ 68203dde7c95SVishal Kulkarni #define T4_MAX_MTU_SUPPORTED 9600 68213dde7c95SVishal Kulkarni #define FW_RXMODE_MTU_NO_CHG 65535 682256b2bdd1SGireesh Nagabhushana 682356b2bdd1SGireesh Nagabhushana struct fw_vi_rxmode_cmd { 682456b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 682556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 682656b2bdd1SGireesh Nagabhushana __be32 mtu_to_vlanexen; 682756b2bdd1SGireesh Nagabhushana __be32 r4_lo; 682856b2bdd1SGireesh Nagabhushana }; 682956b2bdd1SGireesh Nagabhushana 68303dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_VIID 0 68313dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_VIID 0xfff 68323dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 68333dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_VIID(x) \ 68343dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 68353dde7c95SVishal Kulkarni 68363dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_MTU 16 68373dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_MTU 0xffff 68383dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 68393dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_MTU(x) \ 68403dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 68413dde7c95SVishal Kulkarni 68423dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 68433dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 68443dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 68453dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 68463dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 68473dde7c95SVishal Kulkarni 68483dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 68493dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 68503dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 68513dde7c95SVishal Kulkarni ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 68523dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 68533dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 68543dde7c95SVishal Kulkarni 68553dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 68563dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 68573dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 68583dde7c95SVishal Kulkarni ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 68593dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 68603dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 68613dde7c95SVishal Kulkarni 68623dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 68633dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 68643dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 68653dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 68663dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 686756b2bdd1SGireesh Nagabhushana 686856b2bdd1SGireesh Nagabhushana struct fw_vi_enable_cmd { 686956b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 687056b2bdd1SGireesh Nagabhushana __be32 ien_to_len16; 687156b2bdd1SGireesh Nagabhushana __be16 blinkdur; 687256b2bdd1SGireesh Nagabhushana __be16 r3; 687356b2bdd1SGireesh Nagabhushana __be32 r4; 687456b2bdd1SGireesh Nagabhushana }; 687556b2bdd1SGireesh Nagabhushana 68763dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_VIID 0 68773dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_VIID 0xfff 68783dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 68793dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_VIID(x) \ 68803dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 68813dde7c95SVishal Kulkarni 68823dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_IEN 31 68833dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_IEN 0x1 68843dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 68853dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_IEN(x) \ 68863dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 68873dde7c95SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 68883dde7c95SVishal Kulkarni 68893dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_EEN 30 68903dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_EEN 0x1 68913dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 68923dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_EEN(x) \ 68933dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 68943dde7c95SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 68953dde7c95SVishal Kulkarni 68963dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_LED 29 68973dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_LED 0x1 68983dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 68993dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_LED(x) \ 69003dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 69013dde7c95SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 690256b2bdd1SGireesh Nagabhushana 6903de483253SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6904de483253SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6905de483253SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6906de483253SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6907de483253SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6908de483253SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6909de483253SVishal Kulkarni 691056b2bdd1SGireesh Nagabhushana /* VI VF stats offset definitions */ 69113dde7c95SVishal Kulkarni #define VI_VF_NUM_STATS 16 691256b2bdd1SGireesh Nagabhushana enum fw_vi_stats_vf_index { 691356b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 691456b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 691556b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 691656b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 691756b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 691856b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 691956b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 692056b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 692156b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 692256b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 692356b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 692456b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 692556b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 692656b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 692756b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 692856b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_ERR_FRAMES_IX 692956b2bdd1SGireesh Nagabhushana }; 693056b2bdd1SGireesh Nagabhushana 693156b2bdd1SGireesh Nagabhushana /* VI PF stats offset definitions */ 69323dde7c95SVishal Kulkarni #define VI_PF_NUM_STATS 17 693356b2bdd1SGireesh Nagabhushana enum fw_vi_stats_pf_index { 693456b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 693556b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 693656b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 693756b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 693856b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 693956b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 694056b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 694156b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 694256b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BYTES_IX, 694356b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_FRAMES_IX, 694456b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 694556b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 694656b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 694756b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 694856b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 694956b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 695056b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_ERR_FRAMES_IX 695156b2bdd1SGireesh Nagabhushana }; 695256b2bdd1SGireesh Nagabhushana 695356b2bdd1SGireesh Nagabhushana struct fw_vi_stats_cmd { 695456b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 695556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 695656b2bdd1SGireesh Nagabhushana union fw_vi_stats { 695756b2bdd1SGireesh Nagabhushana struct fw_vi_stats_ctl { 695856b2bdd1SGireesh Nagabhushana __be16 nstats_ix; 695956b2bdd1SGireesh Nagabhushana __be16 r6; 696056b2bdd1SGireesh Nagabhushana __be32 r7; 696156b2bdd1SGireesh Nagabhushana __be64 stat0; 696256b2bdd1SGireesh Nagabhushana __be64 stat1; 696356b2bdd1SGireesh Nagabhushana __be64 stat2; 696456b2bdd1SGireesh Nagabhushana __be64 stat3; 696556b2bdd1SGireesh Nagabhushana __be64 stat4; 696656b2bdd1SGireesh Nagabhushana __be64 stat5; 696756b2bdd1SGireesh Nagabhushana } ctl; 696856b2bdd1SGireesh Nagabhushana struct fw_vi_stats_pf { 696956b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 697056b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 697156b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 697256b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 697356b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 697456b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 697556b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 697656b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 697756b2bdd1SGireesh Nagabhushana __be64 rx_pf_bytes; 697856b2bdd1SGireesh Nagabhushana __be64 rx_pf_frames; 697956b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 698056b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 698156b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 698256b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 698356b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 698456b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 698556b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 698656b2bdd1SGireesh Nagabhushana } pf; 698756b2bdd1SGireesh Nagabhushana struct fw_vi_stats_vf { 698856b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 698956b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 699056b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 699156b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 699256b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 699356b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 699456b2bdd1SGireesh Nagabhushana __be64 tx_drop_frames; 699556b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 699656b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 699756b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 699856b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 699956b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 700056b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 700156b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 700256b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 700356b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 700456b2bdd1SGireesh Nagabhushana } vf; 700556b2bdd1SGireesh Nagabhushana } u; 700656b2bdd1SGireesh Nagabhushana }; 700756b2bdd1SGireesh Nagabhushana 70083dde7c95SVishal Kulkarni #define S_FW_VI_STATS_CMD_VIID 0 70093dde7c95SVishal Kulkarni #define M_FW_VI_STATS_CMD_VIID 0xfff 70103dde7c95SVishal Kulkarni #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 70113dde7c95SVishal Kulkarni #define G_FW_VI_STATS_CMD_VIID(x) \ 70123dde7c95SVishal Kulkarni (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 701356b2bdd1SGireesh Nagabhushana 70143dde7c95SVishal Kulkarni #define S_FW_VI_STATS_CMD_NSTATS 12 70153dde7c95SVishal Kulkarni #define M_FW_VI_STATS_CMD_NSTATS 0x7 70163dde7c95SVishal Kulkarni #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 70173dde7c95SVishal Kulkarni #define G_FW_VI_STATS_CMD_NSTATS(x) \ 70183dde7c95SVishal Kulkarni (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 701956b2bdd1SGireesh Nagabhushana 70203dde7c95SVishal Kulkarni #define S_FW_VI_STATS_CMD_IX 0 70213dde7c95SVishal Kulkarni #define M_FW_VI_STATS_CMD_IX 0x1f 70223dde7c95SVishal Kulkarni #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 70233dde7c95SVishal Kulkarni #define G_FW_VI_STATS_CMD_IX(x) \ 70243dde7c95SVishal Kulkarni (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 702556b2bdd1SGireesh Nagabhushana 702656b2bdd1SGireesh Nagabhushana struct fw_acl_mac_cmd { 702756b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 702856b2bdd1SGireesh Nagabhushana __be32 en_to_len16; 702956b2bdd1SGireesh Nagabhushana __u8 nmac; 703056b2bdd1SGireesh Nagabhushana __u8 r3[7]; 703156b2bdd1SGireesh Nagabhushana __be16 r4; 703256b2bdd1SGireesh Nagabhushana __u8 macaddr0[6]; 703356b2bdd1SGireesh Nagabhushana __be16 r5; 703456b2bdd1SGireesh Nagabhushana __u8 macaddr1[6]; 703556b2bdd1SGireesh Nagabhushana __be16 r6; 703656b2bdd1SGireesh Nagabhushana __u8 macaddr2[6]; 703756b2bdd1SGireesh Nagabhushana __be16 r7; 703856b2bdd1SGireesh Nagabhushana __u8 macaddr3[6]; 703956b2bdd1SGireesh Nagabhushana }; 704056b2bdd1SGireesh Nagabhushana 70413dde7c95SVishal Kulkarni #define S_FW_ACL_MAC_CMD_PFN 8 70423dde7c95SVishal Kulkarni #define M_FW_ACL_MAC_CMD_PFN 0x7 70433dde7c95SVishal Kulkarni #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 70443dde7c95SVishal Kulkarni #define G_FW_ACL_MAC_CMD_PFN(x) \ 70453dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 704656b2bdd1SGireesh Nagabhushana 70473dde7c95SVishal Kulkarni #define S_FW_ACL_MAC_CMD_VFN 0 70483dde7c95SVishal Kulkarni #define M_FW_ACL_MAC_CMD_VFN 0xff 70493dde7c95SVishal Kulkarni #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 70503dde7c95SVishal Kulkarni #define G_FW_ACL_MAC_CMD_VFN(x) \ 70513dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 705256b2bdd1SGireesh Nagabhushana 70533dde7c95SVishal Kulkarni #define S_FW_ACL_MAC_CMD_EN 31 70543dde7c95SVishal Kulkarni #define M_FW_ACL_MAC_CMD_EN 0x1 70553dde7c95SVishal Kulkarni #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 70563dde7c95SVishal Kulkarni #define G_FW_ACL_MAC_CMD_EN(x) \ 70573dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 70583dde7c95SVishal Kulkarni #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 705956b2bdd1SGireesh Nagabhushana 706056b2bdd1SGireesh Nagabhushana struct fw_acl_vlan_cmd { 706156b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 706256b2bdd1SGireesh Nagabhushana __be32 en_to_len16; 706356b2bdd1SGireesh Nagabhushana __u8 nvlan; 706456b2bdd1SGireesh Nagabhushana __u8 dropnovlan_fm; 706556b2bdd1SGireesh Nagabhushana __u8 r3_lo[6]; 706656b2bdd1SGireesh Nagabhushana __be16 vlanid[16]; 706756b2bdd1SGireesh Nagabhushana }; 706856b2bdd1SGireesh Nagabhushana 70693dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_PFN 8 70703dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_PFN 0x7 70713dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 70723dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_PFN(x) \ 70733dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 70743dde7c95SVishal Kulkarni 70753dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_VFN 0 70763dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_VFN 0xff 70773dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 70783dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_VFN(x) \ 70793dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 70803dde7c95SVishal Kulkarni 70813dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_EN 31 70823dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_EN 0x1 70833dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 70843dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_EN(x) \ 70853dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 70863dde7c95SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 70873dde7c95SVishal Kulkarni 7088*7e6ad469SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 7089*7e6ad469SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 7090*7e6ad469SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7091*7e6ad469SVishal Kulkarni ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 7092*7e6ad469SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7093*7e6ad469SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 7094*7e6ad469SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 7095*7e6ad469SVishal Kulkarni 7096*7e6ad469SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_PMASK 16 7097*7e6ad469SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_PMASK 0xf 7098*7e6ad469SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 7099*7e6ad469SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_PMASK(x) \ 7100*7e6ad469SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 7101*7e6ad469SVishal Kulkarni 71023dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 71033dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 71043dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 71053dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 71063dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 71073dde7c95SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 71083dde7c95SVishal Kulkarni 71093dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_FM 6 71103dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_FM 0x1 71113dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 71123dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_FM(x) \ 71133dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 71143dde7c95SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 711556b2bdd1SGireesh Nagabhushana 7116*7e6ad469SVishal Kulkarni /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 711756b2bdd1SGireesh Nagabhushana enum fw_port_cap { 711856b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_100M = 0x0001, 711956b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_1G = 0x0002, 71203dde7c95SVishal Kulkarni FW_PORT_CAP_SPEED_25G = 0x0004, 712156b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_10G = 0x0008, 712256b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_40G = 0x0010, 712356b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_100G = 0x0020, 712456b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FC_RX = 0x0040, 712556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FC_TX = 0x0080, 712656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_ANEG = 0x0100, 7127*7e6ad469SVishal Kulkarni FW_PORT_CAP_MDIAUTO = 0x0200, 7128*7e6ad469SVishal Kulkarni FW_PORT_CAP_MDISTRAIGHT = 0x0400, 71293dde7c95SVishal Kulkarni FW_PORT_CAP_FEC_RS = 0x0800, 71303dde7c95SVishal Kulkarni FW_PORT_CAP_FEC_BASER_RS = 0x1000, 7131*7e6ad469SVishal Kulkarni FW_PORT_CAP_FORCE_PAUSE = 0x2000, 71323dde7c95SVishal Kulkarni FW_PORT_CAP_802_3_PAUSE = 0x4000, 71333dde7c95SVishal Kulkarni FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 71343dde7c95SVishal Kulkarni }; 71353dde7c95SVishal Kulkarni 71363dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_SPEED 0 71373dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_SPEED 0x3f 71383dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 71393dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_SPEED(x) \ 71403dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 71413dde7c95SVishal Kulkarni 71423dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_FC 6 71433dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_FC 0x3 71443dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 71453dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_FC(x) \ 71463dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 71473dde7c95SVishal Kulkarni 71483dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_ANEG 8 71493dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_ANEG 0x1 71503dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 71513dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_ANEG(x) \ 71523dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 71533dde7c95SVishal Kulkarni 71543dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_FEC 11 7155*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP_FEC 0x3 71563dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 71573dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_FEC(x) \ 71583dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 71593dde7c95SVishal Kulkarni 7160*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP_FORCE_PAUSE 13 7161*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 7162*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 7163*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 7164*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 7165*7e6ad469SVishal Kulkarni 71663dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_802_3 14 71673dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_802_3 0x3 71683dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 71693dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_802_3(x) \ 71703dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 717156b2bdd1SGireesh Nagabhushana 717256b2bdd1SGireesh Nagabhushana enum fw_port_mdi { 717356b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_UNCHANGED, 717456b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_AUTO, 717556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_F_STRAIGHT, 717656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_F_CROSSOVER 717756b2bdd1SGireesh Nagabhushana }; 717856b2bdd1SGireesh Nagabhushana 71793dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_MDI 9 71803dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_MDI 3 71813dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 71823dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 71833dde7c95SVishal Kulkarni 7184*7e6ad469SVishal Kulkarni /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 7185*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 7186*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 7187*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 7188*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 7189*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 7190*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 7191*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 7192*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 7193*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 7194*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 7195*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 7196*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 7197*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 7198*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FC_RX 0x00010000UL 7199*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FC_TX 0x00020000UL 7200*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 7201*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 7202*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_ANEG 0x00100000UL 7203*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 7204*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 7205*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FEC_RS 0x00800000UL 7206*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 7207*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 7208*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 7209*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 7210*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 7211*7e6ad469SVishal Kulkarni #define FW_PORT_CAP32_RESERVED2 0xe0000000UL 7212*7e6ad469SVishal Kulkarni 7213*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_SPEED 0 7214*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_SPEED 0xfff 7215*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 7216*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_SPEED(x) \ 7217*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 7218*7e6ad469SVishal Kulkarni 7219*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_FC 16 7220*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_FC 0x3 7221*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 7222*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_FC(x) \ 7223*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 7224*7e6ad469SVishal Kulkarni 7225*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_802_3 18 7226*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_802_3 0x3 7227*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 7228*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_802_3(x) \ 7229*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 7230*7e6ad469SVishal Kulkarni 7231*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_ANEG 20 7232*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_ANEG 0x1 7233*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 7234*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_ANEG(x) \ 7235*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 7236*7e6ad469SVishal Kulkarni 7237*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_FORCE_PAUSE 28 7238*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 7239*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 7240*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 7241*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 7242*7e6ad469SVishal Kulkarni 7243*7e6ad469SVishal Kulkarni enum fw_port_mdi32 { 7244*7e6ad469SVishal Kulkarni FW_PORT_CAP32_MDI_UNCHANGED, 7245*7e6ad469SVishal Kulkarni FW_PORT_CAP32_MDI_AUTO, 7246*7e6ad469SVishal Kulkarni FW_PORT_CAP32_MDI_F_STRAIGHT, 7247*7e6ad469SVishal Kulkarni FW_PORT_CAP32_MDI_F_CROSSOVER 7248*7e6ad469SVishal Kulkarni }; 7249*7e6ad469SVishal Kulkarni 7250*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_MDI 21 7251*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_MDI 3 7252*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 7253*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_MDI(x) \ 7254*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 7255*7e6ad469SVishal Kulkarni 7256*7e6ad469SVishal Kulkarni #define S_FW_PORT_CAP32_FEC 23 7257*7e6ad469SVishal Kulkarni #define M_FW_PORT_CAP32_FEC 0x1f 7258*7e6ad469SVishal Kulkarni #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 7259*7e6ad469SVishal Kulkarni #define G_FW_PORT_CAP32_FEC(x) \ 7260*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 7261*7e6ad469SVishal Kulkarni 7262*7e6ad469SVishal Kulkarni /* macros to isolate various 32-bit Port Capabilities sub-fields */ 7263*7e6ad469SVishal Kulkarni #define CAP32_SPEED(__cap32) \ 7264*7e6ad469SVishal Kulkarni (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 7265*7e6ad469SVishal Kulkarni 7266*7e6ad469SVishal Kulkarni #define CAP32_FEC(__cap32) \ 7267*7e6ad469SVishal Kulkarni (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 7268*7e6ad469SVishal Kulkarni 7269*7e6ad469SVishal Kulkarni #define CAP32_FC(__cap32) \ 7270*7e6ad469SVishal Kulkarni (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 727156b2bdd1SGireesh Nagabhushana 727256b2bdd1SGireesh Nagabhushana enum fw_port_action { 727356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_CFG = 0x0001, 727456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_CFG = 0x0002, 727556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 727656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 727756b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7278de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7279de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7280de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7281*7e6ad469SVishal Kulkarni FW_PORT_ACTION_L1_CFG32 = 0x0009, 7282*7e6ad469SVishal Kulkarni FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 728356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 728456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 728556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 728656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 72873dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 72883dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 72893dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 72903dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7291de483253SVishal Kulkarni FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 72923dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 729356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PHY_RESET = 0x0040, 729456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PMA_RESET = 0x0041, 729556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PCS_RESET = 0x0042, 729656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PHYXS_RESET = 0x0043, 729756b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7298de483253SVishal Kulkarni FW_PORT_ACTION_AN_RESET = 0x0045, 72993dde7c95SVishal Kulkarni 730056b2bdd1SGireesh Nagabhushana }; 730156b2bdd1SGireesh Nagabhushana 730256b2bdd1SGireesh Nagabhushana enum fw_port_l2cfg_ctlbf { 730356b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 730456b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 730556b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 730656b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 730756b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_IVLAN = 0x10, 730856b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_TXIPG = 0x20, 7309*7e6ad469SVishal Kulkarni FW_PORT_L2_CTLBF_MTU = 0x40, 7310*7e6ad469SVishal Kulkarni FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80, 731156b2bdd1SGireesh Nagabhushana }; 731256b2bdd1SGireesh Nagabhushana 73133dde7c95SVishal Kulkarni enum fw_dcb_app_tlv_sf { 73143dde7c95SVishal Kulkarni FW_DCB_APP_SF_ETHERTYPE, 73153dde7c95SVishal Kulkarni FW_DCB_APP_SF_SOCKET_TCP, 73163dde7c95SVishal Kulkarni FW_DCB_APP_SF_SOCKET_UDP, 73173dde7c95SVishal Kulkarni FW_DCB_APP_SF_SOCKET_ALL, 73183dde7c95SVishal Kulkarni }; 73193dde7c95SVishal Kulkarni 73203dde7c95SVishal Kulkarni enum fw_port_dcb_versions { 73213dde7c95SVishal Kulkarni FW_PORT_DCB_VER_UNKNOWN, 73223dde7c95SVishal Kulkarni FW_PORT_DCB_VER_CEE1D0, 73233dde7c95SVishal Kulkarni FW_PORT_DCB_VER_CEE1D01, 73243dde7c95SVishal Kulkarni FW_PORT_DCB_VER_IEEE, 73253dde7c95SVishal Kulkarni FW_PORT_DCB_VER_AUTO=7 73263dde7c95SVishal Kulkarni }; 73273dde7c95SVishal Kulkarni 732856b2bdd1SGireesh Nagabhushana enum fw_port_dcb_cfg { 732956b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_PG = 0x01, 733056b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_PFC = 0x02, 733156b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_APPL = 0x04 733256b2bdd1SGireesh Nagabhushana }; 733356b2bdd1SGireesh Nagabhushana 733456b2bdd1SGireesh Nagabhushana enum fw_port_dcb_cfg_rc { 733556b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_SUCCESS = 0x0, 733656b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_ERROR = 0x1 733756b2bdd1SGireesh Nagabhushana }; 733856b2bdd1SGireesh Nagabhushana 733956b2bdd1SGireesh Nagabhushana enum fw_port_dcb_type { 734056b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PGID = 0x00, 734156b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PGRATE = 0x01, 734256b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PRIORATE = 0x02, 734356b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PFC = 0x03, 734456b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_APP_ID = 0x04, 73453dde7c95SVishal Kulkarni FW_PORT_DCB_TYPE_CONTROL = 0x05, 73463dde7c95SVishal Kulkarni }; 73473dde7c95SVishal Kulkarni 73483dde7c95SVishal Kulkarni enum fw_port_dcb_feature_state { 73493dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 73503dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 73513dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 73523dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7353de483253SVishal Kulkarni }; 7354de483253SVishal Kulkarni 7355de483253SVishal Kulkarni enum fw_port_diag_ops { 7356de483253SVishal Kulkarni FW_PORT_DIAGS_TEMP = 0x00, 7357de483253SVishal Kulkarni FW_PORT_DIAGS_TX_POWER = 0x01, 7358de483253SVishal Kulkarni FW_PORT_DIAGS_RX_POWER = 0x02, 73593dde7c95SVishal Kulkarni FW_PORT_DIAGS_TX_DIS = 0x03, 736056b2bdd1SGireesh Nagabhushana }; 736156b2bdd1SGireesh Nagabhushana 736256b2bdd1SGireesh Nagabhushana struct fw_port_cmd { 736356b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 736456b2bdd1SGireesh Nagabhushana __be32 action_to_len16; 736556b2bdd1SGireesh Nagabhushana union fw_port { 736656b2bdd1SGireesh Nagabhushana struct fw_port_l1cfg { 736756b2bdd1SGireesh Nagabhushana __be32 rcap; 736856b2bdd1SGireesh Nagabhushana __be32 r; 736956b2bdd1SGireesh Nagabhushana } l1cfg; 737056b2bdd1SGireesh Nagabhushana struct fw_port_l2cfg { 737156b2bdd1SGireesh Nagabhushana __u8 ctlbf; 737256b2bdd1SGireesh Nagabhushana __u8 ovlan3_to_ivlan0; 737356b2bdd1SGireesh Nagabhushana __be16 ivlantype; 737456b2bdd1SGireesh Nagabhushana __be16 txipg_force_pinfo; 737556b2bdd1SGireesh Nagabhushana __be16 mtu; 737656b2bdd1SGireesh Nagabhushana __be16 ovlan0mask; 737756b2bdd1SGireesh Nagabhushana __be16 ovlan0type; 737856b2bdd1SGireesh Nagabhushana __be16 ovlan1mask; 737956b2bdd1SGireesh Nagabhushana __be16 ovlan1type; 738056b2bdd1SGireesh Nagabhushana __be16 ovlan2mask; 738156b2bdd1SGireesh Nagabhushana __be16 ovlan2type; 738256b2bdd1SGireesh Nagabhushana __be16 ovlan3mask; 738356b2bdd1SGireesh Nagabhushana __be16 ovlan3type; 738456b2bdd1SGireesh Nagabhushana } l2cfg; 738556b2bdd1SGireesh Nagabhushana struct fw_port_info { 738656b2bdd1SGireesh Nagabhushana __be32 lstatus_to_modtype; 738756b2bdd1SGireesh Nagabhushana __be16 pcap; 738856b2bdd1SGireesh Nagabhushana __be16 acap; 738956b2bdd1SGireesh Nagabhushana __be16 mtu; 739056b2bdd1SGireesh Nagabhushana __u8 cbllen; 739156b2bdd1SGireesh Nagabhushana __u8 auxlinfo; 73923dde7c95SVishal Kulkarni __u8 dcbxdis_pkd; 73933dde7c95SVishal Kulkarni __u8 r8_lo; 73943dde7c95SVishal Kulkarni __be16 lpacap; 739556b2bdd1SGireesh Nagabhushana __be64 r9; 739656b2bdd1SGireesh Nagabhushana } info; 7397de483253SVishal Kulkarni struct fw_port_diags { 7398de483253SVishal Kulkarni __u8 diagop; 7399de483253SVishal Kulkarni __u8 r[3]; 7400de483253SVishal Kulkarni __be32 diagval; 7401de483253SVishal Kulkarni } diags; 740256b2bdd1SGireesh Nagabhushana union fw_port_dcb { 740356b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pgid { 740456b2bdd1SGireesh Nagabhushana __u8 type; 740556b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 740656b2bdd1SGireesh Nagabhushana __u8 r10_lo[2]; 740756b2bdd1SGireesh Nagabhushana __be32 pgid; 740856b2bdd1SGireesh Nagabhushana __be64 r11; 740956b2bdd1SGireesh Nagabhushana } pgid; 741056b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pgrate { 741156b2bdd1SGireesh Nagabhushana __u8 type; 741256b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 741356b2bdd1SGireesh Nagabhushana __u8 r10_lo[5]; 741456b2bdd1SGireesh Nagabhushana __u8 num_tcs_supported; 741556b2bdd1SGireesh Nagabhushana __u8 pgrate[8]; 74163dde7c95SVishal Kulkarni __u8 tsa[8]; 741756b2bdd1SGireesh Nagabhushana } pgrate; 741856b2bdd1SGireesh Nagabhushana struct fw_port_dcb_priorate { 741956b2bdd1SGireesh Nagabhushana __u8 type; 742056b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 742156b2bdd1SGireesh Nagabhushana __u8 r10_lo[6]; 742256b2bdd1SGireesh Nagabhushana __u8 strict_priorate[8]; 742356b2bdd1SGireesh Nagabhushana } priorate; 742456b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pfc { 742556b2bdd1SGireesh Nagabhushana __u8 type; 742656b2bdd1SGireesh Nagabhushana __u8 pfcen; 7427*7e6ad469SVishal Kulkarni __u8 apply_pkd; 7428*7e6ad469SVishal Kulkarni __u8 r10_lo[4]; 74293dde7c95SVishal Kulkarni __u8 max_pfc_tcs; 743056b2bdd1SGireesh Nagabhushana __be64 r11; 743156b2bdd1SGireesh Nagabhushana } pfc; 743256b2bdd1SGireesh Nagabhushana struct fw_port_app_priority { 743356b2bdd1SGireesh Nagabhushana __u8 type; 7434*7e6ad469SVishal Kulkarni __u8 apply_pkd; 7435*7e6ad469SVishal Kulkarni __u8 r10_lo; 743656b2bdd1SGireesh Nagabhushana __u8 idx; 743756b2bdd1SGireesh Nagabhushana __u8 user_prio_map; 743856b2bdd1SGireesh Nagabhushana __u8 sel_field; 743956b2bdd1SGireesh Nagabhushana __be16 protocolid; 744056b2bdd1SGireesh Nagabhushana __be64 r12; 744156b2bdd1SGireesh Nagabhushana } app_priority; 7442de483253SVishal Kulkarni struct fw_port_dcb_control { 7443de483253SVishal Kulkarni __u8 type; 7444de483253SVishal Kulkarni __u8 all_syncd_pkd; 74453dde7c95SVishal Kulkarni __be16 dcb_version_to_app_state; 74463dde7c95SVishal Kulkarni __be32 r11; 74473dde7c95SVishal Kulkarni __be64 r12; 7448de483253SVishal Kulkarni } control; 744956b2bdd1SGireesh Nagabhushana } dcb; 7450*7e6ad469SVishal Kulkarni struct fw_port_l1cfg32 { 7451*7e6ad469SVishal Kulkarni __be32 rcap32; 7452*7e6ad469SVishal Kulkarni __be32 r; 7453*7e6ad469SVishal Kulkarni } l1cfg32; 7454*7e6ad469SVishal Kulkarni struct fw_port_info32 { 7455*7e6ad469SVishal Kulkarni __be32 lstatus32_to_cbllen32; 7456*7e6ad469SVishal Kulkarni __be32 auxlinfo32_mtu32; 7457*7e6ad469SVishal Kulkarni __be32 linkattr32; 7458*7e6ad469SVishal Kulkarni __be32 pcaps32; 7459*7e6ad469SVishal Kulkarni __be32 acaps32; 7460*7e6ad469SVishal Kulkarni __be32 lpacaps32; 7461*7e6ad469SVishal Kulkarni } info32; 746256b2bdd1SGireesh Nagabhushana } u; 746356b2bdd1SGireesh Nagabhushana }; 746456b2bdd1SGireesh Nagabhushana 74653dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_READ 22 74663dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_READ 0x1 74673dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 74683dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_READ(x) \ 74693dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 74703dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 74713dde7c95SVishal Kulkarni 74723dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_PORTID 0 74733dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_PORTID 0xf 74743dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 74753dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_PORTID(x) \ 74763dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 74773dde7c95SVishal Kulkarni 74783dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_ACTION 16 74793dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_ACTION 0xffff 74803dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 74813dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_ACTION(x) \ 74823dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 74833dde7c95SVishal Kulkarni 74843dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN3 7 74853dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN3 0x1 74863dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 74873dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN3(x) \ 74883dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 74893dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 74903dde7c95SVishal Kulkarni 74913dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN2 6 74923dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN2 0x1 74933dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 74943dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN2(x) \ 74953dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 74963dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 74973dde7c95SVishal Kulkarni 74983dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN1 5 74993dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN1 0x1 75003dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 75013dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN1(x) \ 75023dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 75033dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 75043dde7c95SVishal Kulkarni 75053dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN0 4 75063dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN0 0x1 75073dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 75083dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN0(x) \ 75093dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 75103dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 75113dde7c95SVishal Kulkarni 75123dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_IVLAN0 3 75133dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_IVLAN0 0x1 75143dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 75153dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_IVLAN0(x) \ 75163dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 75173dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 75183dde7c95SVishal Kulkarni 7519*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN_FILT 2 7520*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN_FILT 0x1 7521*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT) 7522*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN_FILT(x) \ 7523*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT) 7524*7e6ad469SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U) 7525*7e6ad469SVishal Kulkarni 75263dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_TXIPG 3 75273dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_TXIPG 0x1fff 75283dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 75293dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_TXIPG(x) \ 75303dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 75313dde7c95SVishal Kulkarni 75323dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_FORCE_PINFO 0 75333dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_FORCE_PINFO 0x1 75343dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 75353dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 75363dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 75373dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 75383dde7c95SVishal Kulkarni 75393dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LSTATUS 31 75403dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LSTATUS 0x1 75413dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 75423dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LSTATUS(x) \ 75433dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 75443dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 75453dde7c95SVishal Kulkarni 75463dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LSPEED 24 75473dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LSPEED 0x3f 75483dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 75493dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LSPEED(x) \ 75503dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 75513dde7c95SVishal Kulkarni 75523dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_TXPAUSE 23 75533dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_TXPAUSE 0x1 75543dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 75553dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_TXPAUSE(x) \ 75563dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 75573dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 75583dde7c95SVishal Kulkarni 75593dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_RXPAUSE 22 75603dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_RXPAUSE 0x1 75613dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 75623dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_RXPAUSE(x) \ 75633dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 75643dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 75653dde7c95SVishal Kulkarni 75663dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_MDIOCAP 21 75673dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_MDIOCAP 0x1 75683dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 75693dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_MDIOCAP(x) \ 75703dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 75713dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 75723dde7c95SVishal Kulkarni 75733dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_MDIOADDR 16 75743dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_MDIOADDR 0x1f 75753dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 75763dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_MDIOADDR(x) \ 75773dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 75783dde7c95SVishal Kulkarni 75793dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LPTXPAUSE 15 75803dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LPTXPAUSE 0x1 75813dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 75823dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 75833dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 75843dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 75853dde7c95SVishal Kulkarni 75863dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LPRXPAUSE 14 75873dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LPRXPAUSE 0x1 75883dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 75893dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 75903dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 75913dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 75923dde7c95SVishal Kulkarni 75933dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_PTYPE 8 75943dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_PTYPE 0x1f 75953dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 75963dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_PTYPE(x) \ 75973dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 75983dde7c95SVishal Kulkarni 75993dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LINKDNRC 5 76003dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LINKDNRC 0x7 76013dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 76023dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LINKDNRC(x) \ 76033dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 76043dde7c95SVishal Kulkarni 76053dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_MODTYPE 0 76063dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_MODTYPE 0x1f 76073dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 76083dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_MODTYPE(x) \ 76093dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 76103dde7c95SVishal Kulkarni 7611*7e6ad469SVishal Kulkarni #define S_FW_PORT_AUXLINFO_KX4 2 7612*7e6ad469SVishal Kulkarni #define M_FW_PORT_AUXLINFO_KX4 0x1 7613*7e6ad469SVishal Kulkarni #define V_FW_PORT_AUXLINFO_KX4(x) \ 7614*7e6ad469SVishal Kulkarni ((x) << S_FW_PORT_AUXLINFO_KX4) 7615*7e6ad469SVishal Kulkarni #define G_FW_PORT_AUXLINFO_KX4(x) \ 7616*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7617*7e6ad469SVishal Kulkarni #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7618*7e6ad469SVishal Kulkarni 7619*7e6ad469SVishal Kulkarni #define S_FW_PORT_AUXLINFO_KR 1 7620*7e6ad469SVishal Kulkarni #define M_FW_PORT_AUXLINFO_KR 0x1 7621*7e6ad469SVishal Kulkarni #define V_FW_PORT_AUXLINFO_KR(x) \ 7622*7e6ad469SVishal Kulkarni ((x) << S_FW_PORT_AUXLINFO_KR) 7623*7e6ad469SVishal Kulkarni #define G_FW_PORT_AUXLINFO_KR(x) \ 7624*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7625*7e6ad469SVishal Kulkarni #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7626*7e6ad469SVishal Kulkarni 76273dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_DCBXDIS 7 76283dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_DCBXDIS 0x1 76293dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 76303dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_DCBXDIS(x) \ 76313dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 76323dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 76333dde7c95SVishal Kulkarni 76343dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_APPLY 7 76353dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_APPLY 0x1 76363dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 76373dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_APPLY(x) \ 76383dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 76393dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 764056b2bdd1SGireesh Nagabhushana 7641de483253SVishal Kulkarni #define S_FW_PORT_CMD_ALL_SYNCD 7 7642de483253SVishal Kulkarni #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7643de483253SVishal Kulkarni #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7644de483253SVishal Kulkarni #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7645de483253SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 76463dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 76473dde7c95SVishal Kulkarni 76483dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_DCB_VERSION 12 76493dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_DCB_VERSION 0x7 76503dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 76513dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_DCB_VERSION(x) \ 76523dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 76533dde7c95SVishal Kulkarni 76543dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_PFC_STATE 8 76553dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_PFC_STATE 0xf 76563dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 76573dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_PFC_STATE(x) \ 76583dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 76593dde7c95SVishal Kulkarni 76603dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_ETS_STATE 4 76613dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_ETS_STATE 0xf 76623dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 76633dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_ETS_STATE(x) \ 76643dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 76653dde7c95SVishal Kulkarni 76663dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_APP_STATE 0 76673dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_APP_STATE 0xf 76683dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 76693dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_APP_STATE(x) \ 76703dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7671de483253SVishal Kulkarni 7672*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_LSTATUS32 31 7673*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_LSTATUS32 0x1 7674*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7675*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_LSTATUS32(x) \ 7676*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7677*7e6ad469SVishal Kulkarni #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7678*7e6ad469SVishal Kulkarni 7679*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_LINKDNRC32 28 7680*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_LINKDNRC32 0x7 7681*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7682*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_LINKDNRC32(x) \ 7683*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7684*7e6ad469SVishal Kulkarni 7685*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_DCBXDIS32 27 7686*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_DCBXDIS32 0x1 7687*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7688*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_DCBXDIS32(x) \ 7689*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7690*7e6ad469SVishal Kulkarni #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7691*7e6ad469SVishal Kulkarni 7692*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_MDIOCAP32 26 7693*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_MDIOCAP32 0x1 7694*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7695*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_MDIOCAP32(x) \ 7696*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7697*7e6ad469SVishal Kulkarni #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7698*7e6ad469SVishal Kulkarni 7699*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_MDIOADDR32 21 7700*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_MDIOADDR32 0x1f 7701*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7702*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_MDIOADDR32(x) \ 7703*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7704*7e6ad469SVishal Kulkarni 7705*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_PORTTYPE32 13 7706*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_PORTTYPE32 0xff 7707*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7708*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_PORTTYPE32(x) \ 7709*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7710*7e6ad469SVishal Kulkarni 7711*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_MODTYPE32 8 7712*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_MODTYPE32 0x1f 7713*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7714*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_MODTYPE32(x) \ 7715*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7716*7e6ad469SVishal Kulkarni 7717*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_CBLLEN32 0 7718*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_CBLLEN32 0xff 7719*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7720*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_CBLLEN32(x) \ 7721*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7722*7e6ad469SVishal Kulkarni 7723*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_AUXLINFO32 24 7724*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_AUXLINFO32 0xff 7725*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7726*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_AUXLINFO32(x) \ 7727*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7728*7e6ad469SVishal Kulkarni 7729*7e6ad469SVishal Kulkarni #define S_FW_PORT_AUXLINFO32_KX4 2 7730*7e6ad469SVishal Kulkarni #define M_FW_PORT_AUXLINFO32_KX4 0x1 7731*7e6ad469SVishal Kulkarni #define V_FW_PORT_AUXLINFO32_KX4(x) \ 7732*7e6ad469SVishal Kulkarni ((x) << S_FW_PORT_AUXLINFO32_KX4) 7733*7e6ad469SVishal Kulkarni #define G_FW_PORT_AUXLINFO32_KX4(x) \ 7734*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7735*7e6ad469SVishal Kulkarni #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7736*7e6ad469SVishal Kulkarni 7737*7e6ad469SVishal Kulkarni #define S_FW_PORT_AUXLINFO32_KR 1 7738*7e6ad469SVishal Kulkarni #define M_FW_PORT_AUXLINFO32_KR 0x1 7739*7e6ad469SVishal Kulkarni #define V_FW_PORT_AUXLINFO32_KR(x) \ 7740*7e6ad469SVishal Kulkarni ((x) << S_FW_PORT_AUXLINFO32_KR) 7741*7e6ad469SVishal Kulkarni #define G_FW_PORT_AUXLINFO32_KR(x) \ 7742*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7743*7e6ad469SVishal Kulkarni #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7744*7e6ad469SVishal Kulkarni 7745*7e6ad469SVishal Kulkarni #define S_FW_PORT_CMD_MTU32 0 7746*7e6ad469SVishal Kulkarni #define M_FW_PORT_CMD_MTU32 0xffff 7747*7e6ad469SVishal Kulkarni #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7748*7e6ad469SVishal Kulkarni #define G_FW_PORT_CMD_MTU32(x) \ 7749*7e6ad469SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7750*7e6ad469SVishal Kulkarni 775156b2bdd1SGireesh Nagabhushana /* 775256b2bdd1SGireesh Nagabhushana * These are configured into the VPD and hence tools that generate 775356b2bdd1SGireesh Nagabhushana * VPD may use this enumeration. 775456b2bdd1SGireesh Nagabhushana * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 77553dde7c95SVishal Kulkarni * 77563dde7c95SVishal Kulkarni * REMEMBER: 77573dde7c95SVishal Kulkarni * Update the Common Code t4_hw.c:t4_get_port_type_description() 77583dde7c95SVishal Kulkarni * with any new Firmware Port Technology Types! 775956b2bdd1SGireesh Nagabhushana */ 776056b2bdd1SGireesh Nagabhushana enum fw_port_type { 776156b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 776256b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 776356b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 77643dde7c95SVishal Kulkarni FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 77653dde7c95SVishal Kulkarni FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 776656b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 776756b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 776856b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 776956b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 777056b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 77713dde7c95SVishal Kulkarni FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 77723dde7c95SVishal Kulkarni FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7773de483253SVishal Kulkarni FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 77743dde7c95SVishal Kulkarni FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7775de483253SVishal Kulkarni FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 77763dde7c95SVishal Kulkarni FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 77773dde7c95SVishal Kulkarni FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 77783dde7c95SVishal Kulkarni FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 77793dde7c95SVishal Kulkarni FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 77803dde7c95SVishal Kulkarni FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 77813dde7c95SVishal Kulkarni FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 77823dde7c95SVishal Kulkarni FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7783*7e6ad469SVishal Kulkarni FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 778456b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 778556b2bdd1SGireesh Nagabhushana }; 778656b2bdd1SGireesh Nagabhushana 77873dde7c95SVishal Kulkarni /* These are read from module's EEPROM and determined once the 77883dde7c95SVishal Kulkarni module is inserted. */ 778956b2bdd1SGireesh Nagabhushana enum fw_port_module_type { 779056b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NA = 0x0, 779156b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_LR = 0x1, 779256b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_SR = 0x2, 779356b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_ER = 0x3, 779456b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 779556b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 779656b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_LRM = 0x6, 779756b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 779856b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 779956b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 780056b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 780156b2bdd1SGireesh Nagabhushana }; 780256b2bdd1SGireesh Nagabhushana 780356b2bdd1SGireesh Nagabhushana /* used by FW and tools may use this to generate VPD */ 780456b2bdd1SGireesh Nagabhushana enum fw_port_mod_sub_type { 780556b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_NA, 78063dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 78073dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 78083dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 78093dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 78103dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 78113dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 78123dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 78133dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 781456b2bdd1SGireesh Nagabhushana 781556b2bdd1SGireesh Nagabhushana /* 781656b2bdd1SGireesh Nagabhushana * The following will never been in the VPD. They are TWINAX cable 781756b2bdd1SGireesh Nagabhushana * lengths decoded from SFP+ module i2c PROMs. These should almost 781856b2bdd1SGireesh Nagabhushana * certainly go somewhere else ... 781956b2bdd1SGireesh Nagabhushana */ 78203dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 78213dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 78223dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 78233dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 782456b2bdd1SGireesh Nagabhushana }; 782556b2bdd1SGireesh Nagabhushana 782656b2bdd1SGireesh Nagabhushana /* link down reason codes (3b) */ 782756b2bdd1SGireesh Nagabhushana enum fw_port_link_dn_rc { 782856b2bdd1SGireesh Nagabhushana FW_PORT_LINK_DN_RC_NONE, 7829de483253SVishal Kulkarni FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7830de483253SVishal Kulkarni FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7831de483253SVishal Kulkarni FW_PORT_LINK_DN_RESERVED3, 7832de483253SVishal Kulkarni FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7833de483253SVishal Kulkarni FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7834de483253SVishal Kulkarni FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7835de483253SVishal Kulkarni FW_PORT_LINK_DN_RESERVED7 783656b2bdd1SGireesh Nagabhushana }; 783756b2bdd1SGireesh Nagabhushana enum fw_port_stats_tx_index { 78383dde7c95SVishal Kulkarni FW_STAT_TX_PORT_BYTES_IX = 0, 783956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_FRAMES_IX, 784056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_BCAST_IX, 784156b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_MCAST_IX, 784256b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_UCAST_IX, 784356b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_ERROR_IX, 784456b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_64B_IX, 784556b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_65B_127B_IX, 784656b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_128B_255B_IX, 784756b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_256B_511B_IX, 784856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_512B_1023B_IX, 784956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_1024B_1518B_IX, 785056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_1519B_MAX_IX, 785156b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_DROP_IX, 785256b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PAUSE_IX, 785356b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP0_IX, 785456b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP1_IX, 785556b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP2_IX, 785656b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP3_IX, 785756b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP4_IX, 785856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP5_IX, 785956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP6_IX, 78603dde7c95SVishal Kulkarni FW_STAT_TX_PORT_PPP7_IX, 78613dde7c95SVishal Kulkarni FW_NUM_PORT_TX_STATS 786256b2bdd1SGireesh Nagabhushana }; 786356b2bdd1SGireesh Nagabhushana 786456b2bdd1SGireesh Nagabhushana enum fw_port_stat_rx_index { 78653dde7c95SVishal Kulkarni FW_STAT_RX_PORT_BYTES_IX = 0, 786656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_FRAMES_IX, 786756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_BCAST_IX, 786856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MCAST_IX, 786956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_UCAST_IX, 787056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MTU_ERROR_IX, 787156b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 787256b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_CRC_ERROR_IX, 787356b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_LEN_ERROR_IX, 787456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_SYM_ERROR_IX, 787556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_64B_IX, 787656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_65B_127B_IX, 787756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_128B_255B_IX, 787856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_256B_511B_IX, 787956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_512B_1023B_IX, 788056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_1024B_1518B_IX, 788156b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_1519B_MAX_IX, 788256b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PAUSE_IX, 788356b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP0_IX, 788456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP1_IX, 788556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP2_IX, 788656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP3_IX, 788756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP4_IX, 788856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP5_IX, 788956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP6_IX, 789056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP7_IX, 78913dde7c95SVishal Kulkarni FW_STAT_RX_PORT_LESS_64B_IX, 78923dde7c95SVishal Kulkarni FW_STAT_RX_PORT_MAC_ERROR_IX, 78933dde7c95SVishal Kulkarni FW_NUM_PORT_RX_STATS 789456b2bdd1SGireesh Nagabhushana }; 78953dde7c95SVishal Kulkarni /* port stats */ 78963dde7c95SVishal Kulkarni #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 78973dde7c95SVishal Kulkarni FW_NUM_PORT_RX_STATS) 78983dde7c95SVishal Kulkarni 789956b2bdd1SGireesh Nagabhushana 790056b2bdd1SGireesh Nagabhushana struct fw_port_stats_cmd { 790156b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 790256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 790356b2bdd1SGireesh Nagabhushana union fw_port_stats { 790456b2bdd1SGireesh Nagabhushana struct fw_port_stats_ctl { 790556b2bdd1SGireesh Nagabhushana __u8 nstats_bg_bm; 790656b2bdd1SGireesh Nagabhushana __u8 tx_ix; 790756b2bdd1SGireesh Nagabhushana __be16 r6; 790856b2bdd1SGireesh Nagabhushana __be32 r7; 790956b2bdd1SGireesh Nagabhushana __be64 stat0; 791056b2bdd1SGireesh Nagabhushana __be64 stat1; 791156b2bdd1SGireesh Nagabhushana __be64 stat2; 791256b2bdd1SGireesh Nagabhushana __be64 stat3; 791356b2bdd1SGireesh Nagabhushana __be64 stat4; 791456b2bdd1SGireesh Nagabhushana __be64 stat5; 791556b2bdd1SGireesh Nagabhushana } ctl; 791656b2bdd1SGireesh Nagabhushana struct fw_port_stats_all { 791756b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 791856b2bdd1SGireesh Nagabhushana __be64 tx_frames; 791956b2bdd1SGireesh Nagabhushana __be64 tx_bcast; 792056b2bdd1SGireesh Nagabhushana __be64 tx_mcast; 792156b2bdd1SGireesh Nagabhushana __be64 tx_ucast; 792256b2bdd1SGireesh Nagabhushana __be64 tx_error; 792356b2bdd1SGireesh Nagabhushana __be64 tx_64b; 792456b2bdd1SGireesh Nagabhushana __be64 tx_65b_127b; 792556b2bdd1SGireesh Nagabhushana __be64 tx_128b_255b; 792656b2bdd1SGireesh Nagabhushana __be64 tx_256b_511b; 792756b2bdd1SGireesh Nagabhushana __be64 tx_512b_1023b; 792856b2bdd1SGireesh Nagabhushana __be64 tx_1024b_1518b; 792956b2bdd1SGireesh Nagabhushana __be64 tx_1519b_max; 793056b2bdd1SGireesh Nagabhushana __be64 tx_drop; 793156b2bdd1SGireesh Nagabhushana __be64 tx_pause; 793256b2bdd1SGireesh Nagabhushana __be64 tx_ppp0; 793356b2bdd1SGireesh Nagabhushana __be64 tx_ppp1; 793456b2bdd1SGireesh Nagabhushana __be64 tx_ppp2; 793556b2bdd1SGireesh Nagabhushana __be64 tx_ppp3; 793656b2bdd1SGireesh Nagabhushana __be64 tx_ppp4; 793756b2bdd1SGireesh Nagabhushana __be64 tx_ppp5; 793856b2bdd1SGireesh Nagabhushana __be64 tx_ppp6; 793956b2bdd1SGireesh Nagabhushana __be64 tx_ppp7; 794056b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 794156b2bdd1SGireesh Nagabhushana __be64 rx_frames; 794256b2bdd1SGireesh Nagabhushana __be64 rx_bcast; 794356b2bdd1SGireesh Nagabhushana __be64 rx_mcast; 794456b2bdd1SGireesh Nagabhushana __be64 rx_ucast; 794556b2bdd1SGireesh Nagabhushana __be64 rx_mtu_error; 794656b2bdd1SGireesh Nagabhushana __be64 rx_mtu_crc_error; 794756b2bdd1SGireesh Nagabhushana __be64 rx_crc_error; 794856b2bdd1SGireesh Nagabhushana __be64 rx_len_error; 794956b2bdd1SGireesh Nagabhushana __be64 rx_sym_error; 795056b2bdd1SGireesh Nagabhushana __be64 rx_64b; 795156b2bdd1SGireesh Nagabhushana __be64 rx_65b_127b; 795256b2bdd1SGireesh Nagabhushana __be64 rx_128b_255b; 795356b2bdd1SGireesh Nagabhushana __be64 rx_256b_511b; 795456b2bdd1SGireesh Nagabhushana __be64 rx_512b_1023b; 795556b2bdd1SGireesh Nagabhushana __be64 rx_1024b_1518b; 795656b2bdd1SGireesh Nagabhushana __be64 rx_1519b_max; 795756b2bdd1SGireesh Nagabhushana __be64 rx_pause; 795856b2bdd1SGireesh Nagabhushana __be64 rx_ppp0; 795956b2bdd1SGireesh Nagabhushana __be64 rx_ppp1; 796056b2bdd1SGireesh Nagabhushana __be64 rx_ppp2; 796156b2bdd1SGireesh Nagabhushana __be64 rx_ppp3; 796256b2bdd1SGireesh Nagabhushana __be64 rx_ppp4; 796356b2bdd1SGireesh Nagabhushana __be64 rx_ppp5; 796456b2bdd1SGireesh Nagabhushana __be64 rx_ppp6; 796556b2bdd1SGireesh Nagabhushana __be64 rx_ppp7; 796656b2bdd1SGireesh Nagabhushana __be64 rx_less_64b; 796756b2bdd1SGireesh Nagabhushana __be64 rx_bg_drop; 796856b2bdd1SGireesh Nagabhushana __be64 rx_bg_trunc; 796956b2bdd1SGireesh Nagabhushana } all; 797056b2bdd1SGireesh Nagabhushana } u; 797156b2bdd1SGireesh Nagabhushana }; 797256b2bdd1SGireesh Nagabhushana 79733dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_NSTATS 4 79743dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_NSTATS 0x7 79753dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 79763dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 79773dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 797856b2bdd1SGireesh Nagabhushana 79793dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_BG_BM 0 79803dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_BG_BM 0x3 79813dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 79823dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 79833dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 798456b2bdd1SGireesh Nagabhushana 79853dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_TX 7 79863dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_TX 0x1 79873dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 79883dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_TX(x) \ 79893dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 79903dde7c95SVishal Kulkarni #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 799156b2bdd1SGireesh Nagabhushana 79923dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_IX 0 79933dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_IX 0x3f 79943dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 79953dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_IX(x) \ 79963dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 799756b2bdd1SGireesh Nagabhushana 799856b2bdd1SGireesh Nagabhushana /* port loopback stats */ 79993dde7c95SVishal Kulkarni #define FW_NUM_LB_STATS 14 800056b2bdd1SGireesh Nagabhushana enum fw_port_lb_stats_index { 800156b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_BYTES_IX, 800256b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_FRAMES_IX, 800356b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_BCAST_IX, 800456b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_MCAST_IX, 800556b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_UCAST_IX, 800656b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_ERROR_IX, 800756b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_64B_IX, 800856b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_65B_127B_IX, 800956b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_128B_255B_IX, 801056b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_256B_511B_IX, 801156b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_512B_1023B_IX, 801256b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_1024B_1518B_IX, 801356b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_1519B_MAX_IX, 801456b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_DROP_FRAMES_IX 801556b2bdd1SGireesh Nagabhushana }; 801656b2bdd1SGireesh Nagabhushana 801756b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_cmd { 801856b2bdd1SGireesh Nagabhushana __be32 op_to_lbport; 801956b2bdd1SGireesh Nagabhushana __be32 retval_len16; 802056b2bdd1SGireesh Nagabhushana union fw_port_lb_stats { 802156b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_ctl { 802256b2bdd1SGireesh Nagabhushana __u8 nstats_bg_bm; 802356b2bdd1SGireesh Nagabhushana __u8 ix_pkd; 802456b2bdd1SGireesh Nagabhushana __be16 r6; 802556b2bdd1SGireesh Nagabhushana __be32 r7; 802656b2bdd1SGireesh Nagabhushana __be64 stat0; 802756b2bdd1SGireesh Nagabhushana __be64 stat1; 802856b2bdd1SGireesh Nagabhushana __be64 stat2; 802956b2bdd1SGireesh Nagabhushana __be64 stat3; 803056b2bdd1SGireesh Nagabhushana __be64 stat4; 803156b2bdd1SGireesh Nagabhushana __be64 stat5; 803256b2bdd1SGireesh Nagabhushana } ctl; 803356b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_all { 803456b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 803556b2bdd1SGireesh Nagabhushana __be64 tx_frames; 803656b2bdd1SGireesh Nagabhushana __be64 tx_bcast; 803756b2bdd1SGireesh Nagabhushana __be64 tx_mcast; 803856b2bdd1SGireesh Nagabhushana __be64 tx_ucast; 803956b2bdd1SGireesh Nagabhushana __be64 tx_error; 804056b2bdd1SGireesh Nagabhushana __be64 tx_64b; 804156b2bdd1SGireesh Nagabhushana __be64 tx_65b_127b; 804256b2bdd1SGireesh Nagabhushana __be64 tx_128b_255b; 804356b2bdd1SGireesh Nagabhushana __be64 tx_256b_511b; 804456b2bdd1SGireesh Nagabhushana __be64 tx_512b_1023b; 804556b2bdd1SGireesh Nagabhushana __be64 tx_1024b_1518b; 804656b2bdd1SGireesh Nagabhushana __be64 tx_1519b_max; 804756b2bdd1SGireesh Nagabhushana __be64 rx_lb_drop; 804856b2bdd1SGireesh Nagabhushana __be64 rx_lb_trunc; 804956b2bdd1SGireesh Nagabhushana } all; 805056b2bdd1SGireesh Nagabhushana } u; 805156b2bdd1SGireesh Nagabhushana }; 805256b2bdd1SGireesh Nagabhushana 80533dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 80543dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 80553dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 80563dde7c95SVishal Kulkarni ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 80573dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 80583dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 80593dde7c95SVishal Kulkarni 80603dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 80613dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 80623dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 80633dde7c95SVishal Kulkarni ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 80643dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 80653dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 80663dde7c95SVishal Kulkarni 80673dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 80683dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 80693dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 80703dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 80713dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 80723dde7c95SVishal Kulkarni 80733dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_IX 0 80743dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_IX 0xf 80753dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 80763dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 80773dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 807856b2bdd1SGireesh Nagabhushana 807956b2bdd1SGireesh Nagabhushana /* Trace related defines */ 80803dde7c95SVishal Kulkarni #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 80813dde7c95SVishal Kulkarni #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 808256b2bdd1SGireesh Nagabhushana 808356b2bdd1SGireesh Nagabhushana struct fw_port_trace_cmd { 808456b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 808556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 808656b2bdd1SGireesh Nagabhushana __be16 traceen_to_pciech; 808756b2bdd1SGireesh Nagabhushana __be16 qnum; 808856b2bdd1SGireesh Nagabhushana __be32 r5; 808956b2bdd1SGireesh Nagabhushana }; 809056b2bdd1SGireesh Nagabhushana 80913dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_PORTID 0 80923dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_PORTID 0xf 80933dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 80943dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 80953dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 80963dde7c95SVishal Kulkarni 80973dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_TRACEEN 15 80983dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 80993dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 81003dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 81013dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 81023dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 81033dde7c95SVishal Kulkarni 81043dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_FLTMODE 14 81053dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 81063dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 81073dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 81083dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 81093dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 81103dde7c95SVishal Kulkarni 81113dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_DUPLEN 13 81123dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 81133dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 81143dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 81153dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 81163dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 81173dde7c95SVishal Kulkarni 81183dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 81193dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 81203dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 81213dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 81223dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 81233dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 81243dde7c95SVishal Kulkarni M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 81253dde7c95SVishal Kulkarni 81263dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_PCIECH 6 81273dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 81283dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 81293dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 81303dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 813156b2bdd1SGireesh Nagabhushana 813256b2bdd1SGireesh Nagabhushana struct fw_port_trace_mmap_cmd { 813356b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 813456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 813556b2bdd1SGireesh Nagabhushana __be32 fid_to_skipoffset; 813656b2bdd1SGireesh Nagabhushana __be32 minpktsize_capturemax; 813756b2bdd1SGireesh Nagabhushana __u8 map[224]; 813856b2bdd1SGireesh Nagabhushana }; 813956b2bdd1SGireesh Nagabhushana 81403dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 81413dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 81423dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 81433dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 81443dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 81453dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 81463dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_PORTID) 81473dde7c95SVishal Kulkarni 81483dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 81493dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 81503dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 81513dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 81523dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 81533dde7c95SVishal Kulkarni 81543dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 81553dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 81563dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 81573dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 81583dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 81593dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 81603dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 81613dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 81623dde7c95SVishal Kulkarni 81633dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 81643dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 81653dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 81663dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 81673dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 81683dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 81693dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 81703dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 81713dde7c95SVishal Kulkarni 81723dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 81733dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 81743dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 81753dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 81763dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 81773dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 81783dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 81793dde7c95SVishal Kulkarni 81803dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 81813dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 81823dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 81833dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 81843dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 81853dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 81863dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 81873dde7c95SVishal Kulkarni 81883dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 81893dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 81903dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 81913dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 81923dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 81933dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 81943dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 81953dde7c95SVishal Kulkarni 81963dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 81973dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 81983dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 81993dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 82003dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 82013dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 82023dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 82033dde7c95SVishal Kulkarni 82043dde7c95SVishal Kulkarni enum fw_ptp_subop { 82053dde7c95SVishal Kulkarni 82063dde7c95SVishal Kulkarni /* none */ 82073dde7c95SVishal Kulkarni FW_PTP_SC_INIT_TIMER = 0x00, 82083dde7c95SVishal Kulkarni FW_PTP_SC_TX_TYPE = 0x01, 82093dde7c95SVishal Kulkarni 82103dde7c95SVishal Kulkarni /* init */ 82113dde7c95SVishal Kulkarni FW_PTP_SC_RXTIME_STAMP = 0x08, 82123dde7c95SVishal Kulkarni FW_PTP_SC_RDRX_TYPE = 0x09, 82133dde7c95SVishal Kulkarni 82143dde7c95SVishal Kulkarni /* ts */ 82153dde7c95SVishal Kulkarni FW_PTP_SC_ADJ_FREQ = 0x10, 82163dde7c95SVishal Kulkarni FW_PTP_SC_ADJ_TIME = 0x11, 82173dde7c95SVishal Kulkarni FW_PTP_SC_ADJ_FTIME = 0x12, 82183dde7c95SVishal Kulkarni FW_PTP_SC_WALL_CLOCK = 0x13, 82193dde7c95SVishal Kulkarni FW_PTP_SC_GET_TIME = 0x14, 82203dde7c95SVishal Kulkarni FW_PTP_SC_SET_TIME = 0x15, 82213dde7c95SVishal Kulkarni }; 82223dde7c95SVishal Kulkarni 82233dde7c95SVishal Kulkarni struct fw_ptp_cmd { 82243dde7c95SVishal Kulkarni __be32 op_to_portid; 82253dde7c95SVishal Kulkarni __be32 retval_len16; 82263dde7c95SVishal Kulkarni union fw_ptp { 82273dde7c95SVishal Kulkarni struct fw_ptp_sc { 82283dde7c95SVishal Kulkarni __u8 sc; 82293dde7c95SVishal Kulkarni __u8 r3[7]; 82303dde7c95SVishal Kulkarni } scmd; 82313dde7c95SVishal Kulkarni struct fw_ptp_init { 82323dde7c95SVishal Kulkarni __u8 sc; 82333dde7c95SVishal Kulkarni __u8 txchan; 82343dde7c95SVishal Kulkarni __be16 absid; 82353dde7c95SVishal Kulkarni __be16 mode; 8236*7e6ad469SVishal Kulkarni __be16 ptp_rx_ctrl_pkd; 82373dde7c95SVishal Kulkarni } init; 82383dde7c95SVishal Kulkarni struct fw_ptp_ts { 82393dde7c95SVishal Kulkarni __u8 sc; 82403dde7c95SVishal Kulkarni __u8 sign; 82413dde7c95SVishal Kulkarni __be16 r3; 82423dde7c95SVishal Kulkarni __be32 ppb; 82433dde7c95SVishal Kulkarni __be64 tm; 82443dde7c95SVishal Kulkarni } ts; 82453dde7c95SVishal Kulkarni } u; 82463dde7c95SVishal Kulkarni __be64 r3; 82473dde7c95SVishal Kulkarni }; 82483dde7c95SVishal Kulkarni 82493dde7c95SVishal Kulkarni #define S_FW_PTP_CMD_PORTID 0 82503dde7c95SVishal Kulkarni #define M_FW_PTP_CMD_PORTID 0xf 82513dde7c95SVishal Kulkarni #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 82523dde7c95SVishal Kulkarni #define G_FW_PTP_CMD_PORTID(x) \ 82533dde7c95SVishal Kulkarni (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 825456b2bdd1SGireesh Nagabhushana 8255*7e6ad469SVishal Kulkarni #define S_FW_PTP_CMD_PTP_RX_CTRL 15 8256*7e6ad469SVishal Kulkarni #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1 8257*7e6ad469SVishal Kulkarni #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL) 8258*7e6ad469SVishal Kulkarni #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \ 8259*7e6ad469SVishal Kulkarni (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL) 8260*7e6ad469SVishal Kulkarni #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U) 8261*7e6ad469SVishal Kulkarni 8262*7e6ad469SVishal Kulkarni 826356b2bdd1SGireesh Nagabhushana struct fw_rss_ind_tbl_cmd { 826456b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 826556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 826656b2bdd1SGireesh Nagabhushana __be16 niqid; 826756b2bdd1SGireesh Nagabhushana __be16 startidx; 826856b2bdd1SGireesh Nagabhushana __be32 r3; 826956b2bdd1SGireesh Nagabhushana __be32 iq0_to_iq2; 827056b2bdd1SGireesh Nagabhushana __be32 iq3_to_iq5; 827156b2bdd1SGireesh Nagabhushana __be32 iq6_to_iq8; 827256b2bdd1SGireesh Nagabhushana __be32 iq9_to_iq11; 827356b2bdd1SGireesh Nagabhushana __be32 iq12_to_iq14; 827456b2bdd1SGireesh Nagabhushana __be32 iq15_to_iq17; 827556b2bdd1SGireesh Nagabhushana __be32 iq18_to_iq20; 827656b2bdd1SGireesh Nagabhushana __be32 iq21_to_iq23; 827756b2bdd1SGireesh Nagabhushana __be32 iq24_to_iq26; 827856b2bdd1SGireesh Nagabhushana __be32 iq27_to_iq29; 827956b2bdd1SGireesh Nagabhushana __be32 iq30_iq31; 828056b2bdd1SGireesh Nagabhushana __be32 r15_lo; 828156b2bdd1SGireesh Nagabhushana }; 828256b2bdd1SGireesh Nagabhushana 82833dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_VIID 0 82843dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 82853dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 82863dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 82873dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 82883dde7c95SVishal Kulkarni 82893dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ0 20 82903dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 82913dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 82923dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 82933dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 82943dde7c95SVishal Kulkarni 82953dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ1 10 82963dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 82973dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 82983dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 82993dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 83003dde7c95SVishal Kulkarni 83013dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ2 0 83023dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 83033dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 83043dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 83053dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 83063dde7c95SVishal Kulkarni 83073dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ3 20 83083dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 83093dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 83103dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 83113dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 83123dde7c95SVishal Kulkarni 83133dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ4 10 83143dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 83153dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 83163dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 83173dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 83183dde7c95SVishal Kulkarni 83193dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ5 0 83203dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 83213dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 83223dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 83233dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 83243dde7c95SVishal Kulkarni 83253dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ6 20 83263dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 83273dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 83283dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 83293dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 83303dde7c95SVishal Kulkarni 83313dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ7 10 83323dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 83333dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 83343dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 83353dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 83363dde7c95SVishal Kulkarni 83373dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ8 0 83383dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 83393dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 83403dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 83413dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 83423dde7c95SVishal Kulkarni 83433dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ9 20 83443dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 83453dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 83463dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 83473dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 83483dde7c95SVishal Kulkarni 83493dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ10 10 83503dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 83513dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 83523dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 83533dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 83543dde7c95SVishal Kulkarni 83553dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ11 0 83563dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 83573dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 83583dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 83593dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 83603dde7c95SVishal Kulkarni 83613dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ12 20 83623dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 83633dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 83643dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 83653dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 83663dde7c95SVishal Kulkarni 83673dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ13 10 83683dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 83693dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 83703dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 83713dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 83723dde7c95SVishal Kulkarni 83733dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ14 0 83743dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 83753dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 83763dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 83773dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 83783dde7c95SVishal Kulkarni 83793dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ15 20 83803dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 83813dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 83823dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 83833dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 83843dde7c95SVishal Kulkarni 83853dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ16 10 83863dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 83873dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 83883dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 83893dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 83903dde7c95SVishal Kulkarni 83913dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ17 0 83923dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 83933dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 83943dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 83953dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 83963dde7c95SVishal Kulkarni 83973dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ18 20 83983dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 83993dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 84003dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 84013dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 84023dde7c95SVishal Kulkarni 84033dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ19 10 84043dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 84053dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 84063dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 84073dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 84083dde7c95SVishal Kulkarni 84093dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ20 0 84103dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 84113dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 84123dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 84133dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 84143dde7c95SVishal Kulkarni 84153dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ21 20 84163dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 84173dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 84183dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 84193dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 84203dde7c95SVishal Kulkarni 84213dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ22 10 84223dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 84233dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 84243dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 84253dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 84263dde7c95SVishal Kulkarni 84273dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ23 0 84283dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 84293dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 84303dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 84313dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 84323dde7c95SVishal Kulkarni 84333dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ24 20 84343dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 84353dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 84363dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 84373dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 84383dde7c95SVishal Kulkarni 84393dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ25 10 84403dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 84413dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 84423dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 84433dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 84443dde7c95SVishal Kulkarni 84453dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ26 0 84463dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 84473dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 84483dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 84493dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 84503dde7c95SVishal Kulkarni 84513dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ27 20 84523dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 84533dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 84543dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 84553dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 84563dde7c95SVishal Kulkarni 84573dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ28 10 84583dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 84593dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 84603dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 84613dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 84623dde7c95SVishal Kulkarni 84633dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ29 0 84643dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 84653dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 84663dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 84673dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 84683dde7c95SVishal Kulkarni 84693dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ30 20 84703dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 84713dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 84723dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 84733dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 84743dde7c95SVishal Kulkarni 84753dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ31 10 84763dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 84773dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 84783dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 84793dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 848056b2bdd1SGireesh Nagabhushana 848156b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_cmd { 848256b2bdd1SGireesh Nagabhushana __be32 op_to_write; 848356b2bdd1SGireesh Nagabhushana __be32 retval_len16; 848456b2bdd1SGireesh Nagabhushana union fw_rss_glb_config { 848556b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_manual { 848656b2bdd1SGireesh Nagabhushana __be32 mode_pkd; 848756b2bdd1SGireesh Nagabhushana __be32 r3; 848856b2bdd1SGireesh Nagabhushana __be64 r4; 848956b2bdd1SGireesh Nagabhushana __be64 r5; 849056b2bdd1SGireesh Nagabhushana } manual; 849156b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_basicvirtual { 84923dde7c95SVishal Kulkarni __be32 mode_keymode; 849356b2bdd1SGireesh Nagabhushana __be32 synmapen_to_hashtoeplitz; 849456b2bdd1SGireesh Nagabhushana __be64 r8; 849556b2bdd1SGireesh Nagabhushana __be64 r9; 849656b2bdd1SGireesh Nagabhushana } basicvirtual; 849756b2bdd1SGireesh Nagabhushana } u; 849856b2bdd1SGireesh Nagabhushana }; 849956b2bdd1SGireesh Nagabhushana 85003dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 85013dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 85023dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 85033dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 85043dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 85053dde7c95SVishal Kulkarni 85063dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 85073dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 85083dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 85093dde7c95SVishal Kulkarni 85103dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 85113dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 85123dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 85133dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 85143dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 85153dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 85163dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 85173dde7c95SVishal Kulkarni 85183dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 85193dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 85203dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 85213dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 85223dde7c95SVishal Kulkarni 85233dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 85243dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 85253dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 85263dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 85273dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 85283dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 85293dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 85303dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 85313dde7c95SVishal Kulkarni 85323dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 85333dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 85343dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 85353dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 85363dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 85373dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 85383dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 85393dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 854056b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 854156b2bdd1SGireesh Nagabhushana 85423dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 85433dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 85443dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 85453dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 85463dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 85473dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 85483dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 85493dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 855056b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 855156b2bdd1SGireesh Nagabhushana 85523dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 85533dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 85543dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 85553dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 85563dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 85573dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 85583dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 85593dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 856056b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 856156b2bdd1SGireesh Nagabhushana 85623dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 85633dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 85643dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 85653dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 85663dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 85673dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 85683dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 85693dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 857056b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 857156b2bdd1SGireesh Nagabhushana 85723dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 85733dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 85743dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 85753dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 85763dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 85773dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 85783dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 85793dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 85803dde7c95SVishal Kulkarni 85813dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 85823dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 85833dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 85843dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 85853dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 85863dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 85873dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 85883dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 85893dde7c95SVishal Kulkarni 85903dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 85913dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 85923dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 85933dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 85943dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 85953dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 85963dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 85973dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 859856b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 859956b2bdd1SGireesh Nagabhushana 86003dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 86013dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 86023dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 86033dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 86043dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 86053dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 86063dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 86073dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 860856b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 860956b2bdd1SGireesh Nagabhushana 861056b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_cmd { 861156b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 861256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 861356b2bdd1SGireesh Nagabhushana union fw_rss_vi_config { 861456b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_manual { 861556b2bdd1SGireesh Nagabhushana __be64 r3; 861656b2bdd1SGireesh Nagabhushana __be64 r4; 861756b2bdd1SGireesh Nagabhushana __be64 r5; 861856b2bdd1SGireesh Nagabhushana } manual; 861956b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_basicvirtual { 862056b2bdd1SGireesh Nagabhushana __be32 r6; 862156b2bdd1SGireesh Nagabhushana __be32 defaultq_to_udpen; 86223dde7c95SVishal Kulkarni __be32 secretkeyidx_pkd; 86233dde7c95SVishal Kulkarni __be32 secretkeyxor; 862456b2bdd1SGireesh Nagabhushana __be64 r10; 862556b2bdd1SGireesh Nagabhushana } basicvirtual; 862656b2bdd1SGireesh Nagabhushana } u; 862756b2bdd1SGireesh Nagabhushana }; 862856b2bdd1SGireesh Nagabhushana 86293dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 86303dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 86313dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 86323dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 86333dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 86343dde7c95SVishal Kulkarni 86353dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 86363dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 86373dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 86383dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 86393dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 86403dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 86413dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 86423dde7c95SVishal Kulkarni 86433dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 86443dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 86453dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 86463dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 86473dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 86483dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 86493dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 86503dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 865156b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 865256b2bdd1SGireesh Nagabhushana 86533dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 86543dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 86553dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 86563dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 86573dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 86583dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 86593dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 86603dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 866156b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 866256b2bdd1SGireesh Nagabhushana 86633dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 86643dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 86653dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 86663dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 86673dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 86683dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 86693dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 86703dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 867156b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 867256b2bdd1SGireesh Nagabhushana 86733dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 86743dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 86753dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 86763dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 86773dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 86783dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 86793dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 86803dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 868156b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 868256b2bdd1SGireesh Nagabhushana 86833dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 86843dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 86853dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 86863dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 86873dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 86883dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 86893dde7c95SVishal Kulkarni 86903dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 86913dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 86923dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 86933dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 86943dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 86953dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 86963dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 869756b2bdd1SGireesh Nagabhushana 869856b2bdd1SGireesh Nagabhushana enum fw_sched_sc { 869956b2bdd1SGireesh Nagabhushana FW_SCHED_SC_CONFIG = 0, 870056b2bdd1SGireesh Nagabhushana FW_SCHED_SC_PARAMS = 1, 870156b2bdd1SGireesh Nagabhushana }; 870256b2bdd1SGireesh Nagabhushana 870356b2bdd1SGireesh Nagabhushana enum fw_sched_type { 87043dde7c95SVishal Kulkarni FW_SCHED_TYPE_PKTSCHED = 0, 87053dde7c95SVishal Kulkarni FW_SCHED_TYPE_STREAMSCHED = 1, 870656b2bdd1SGireesh Nagabhushana }; 870756b2bdd1SGireesh Nagabhushana 870856b2bdd1SGireesh Nagabhushana enum fw_sched_params_level { 870956b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 871056b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 871156b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 871256b2bdd1SGireesh Nagabhushana }; 871356b2bdd1SGireesh Nagabhushana 871456b2bdd1SGireesh Nagabhushana enum fw_sched_params_mode { 871556b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_MODE_CLASS = 0, 871656b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_MODE_FLOW = 1, 871756b2bdd1SGireesh Nagabhushana }; 871856b2bdd1SGireesh Nagabhushana 871956b2bdd1SGireesh Nagabhushana enum fw_sched_params_unit { 872056b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_UNIT_BITRATE = 0, 872156b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 872256b2bdd1SGireesh Nagabhushana }; 872356b2bdd1SGireesh Nagabhushana 872456b2bdd1SGireesh Nagabhushana enum fw_sched_params_rate { 872556b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_RATE_REL = 0, 872656b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_RATE_ABS = 1, 872756b2bdd1SGireesh Nagabhushana }; 872856b2bdd1SGireesh Nagabhushana 872956b2bdd1SGireesh Nagabhushana struct fw_sched_cmd { 873056b2bdd1SGireesh Nagabhushana __be32 op_to_write; 873156b2bdd1SGireesh Nagabhushana __be32 retval_len16; 873256b2bdd1SGireesh Nagabhushana union fw_sched { 873356b2bdd1SGireesh Nagabhushana struct fw_sched_config { 873456b2bdd1SGireesh Nagabhushana __u8 sc; 873556b2bdd1SGireesh Nagabhushana __u8 type; 873656b2bdd1SGireesh Nagabhushana __u8 minmaxen; 873756b2bdd1SGireesh Nagabhushana __u8 r3[5]; 8738de483253SVishal Kulkarni __u8 nclasses[4]; 8739de483253SVishal Kulkarni __be32 r4; 874056b2bdd1SGireesh Nagabhushana } config; 874156b2bdd1SGireesh Nagabhushana struct fw_sched_params { 874256b2bdd1SGireesh Nagabhushana __u8 sc; 874356b2bdd1SGireesh Nagabhushana __u8 type; 874456b2bdd1SGireesh Nagabhushana __u8 level; 874556b2bdd1SGireesh Nagabhushana __u8 mode; 874656b2bdd1SGireesh Nagabhushana __u8 unit; 874756b2bdd1SGireesh Nagabhushana __u8 rate; 874856b2bdd1SGireesh Nagabhushana __u8 ch; 874956b2bdd1SGireesh Nagabhushana __u8 cl; 875056b2bdd1SGireesh Nagabhushana __be32 min; 875156b2bdd1SGireesh Nagabhushana __be32 max; 875256b2bdd1SGireesh Nagabhushana __be16 weight; 875356b2bdd1SGireesh Nagabhushana __be16 pktsize; 8754de483253SVishal Kulkarni __be16 burstsize; 8755de483253SVishal Kulkarni __be16 r4; 875656b2bdd1SGireesh Nagabhushana } params; 875756b2bdd1SGireesh Nagabhushana } u; 875856b2bdd1SGireesh Nagabhushana }; 875956b2bdd1SGireesh Nagabhushana 876056b2bdd1SGireesh Nagabhushana /* 876156b2bdd1SGireesh Nagabhushana * length of the formatting string 876256b2bdd1SGireesh Nagabhushana */ 87633dde7c95SVishal Kulkarni #define FW_DEVLOG_FMT_LEN 192 876456b2bdd1SGireesh Nagabhushana 876556b2bdd1SGireesh Nagabhushana /* 876656b2bdd1SGireesh Nagabhushana * maximum number of the formatting string parameters 876756b2bdd1SGireesh Nagabhushana */ 87683dde7c95SVishal Kulkarni #define FW_DEVLOG_FMT_PARAMS_NUM 8 876956b2bdd1SGireesh Nagabhushana 877056b2bdd1SGireesh Nagabhushana /* 877156b2bdd1SGireesh Nagabhushana * priority levels 877256b2bdd1SGireesh Nagabhushana */ 877356b2bdd1SGireesh Nagabhushana enum fw_devlog_level { 877456b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_EMERG = 0x0, 877556b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_CRIT = 0x1, 877656b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_ERR = 0x2, 877756b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_NOTICE = 0x3, 877856b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_INFO = 0x4, 877956b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_DEBUG = 0x5, 878056b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_MAX = 0x5, 878156b2bdd1SGireesh Nagabhushana }; 878256b2bdd1SGireesh Nagabhushana 878356b2bdd1SGireesh Nagabhushana /* 878456b2bdd1SGireesh Nagabhushana * facilities that may send a log message 878556b2bdd1SGireesh Nagabhushana */ 878656b2bdd1SGireesh Nagabhushana enum fw_devlog_facility { 878756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_CORE = 0x00, 8788de483253SVishal Kulkarni FW_DEVLOG_FACILITY_CF = 0x01, 878956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_SCHED = 0x02, 879056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_TIMER = 0x04, 879156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_RES = 0x06, 879256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_HW = 0x08, 879356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FLR = 0x10, 879456b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_DMAQ = 0x12, 879556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_PHY = 0x14, 879656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_MAC = 0x16, 879756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_PORT = 0x18, 879856b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_VI = 0x1A, 879956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FILTER = 0x1C, 880056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ACL = 0x1E, 880156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_TM = 0x20, 880256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_QFC = 0x22, 880356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_DCB = 0x24, 880456b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ETH = 0x26, 880556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_OFLD = 0x28, 880656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_RI = 0x2A, 880756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ISCSI = 0x2C, 880856b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FCOE = 0x2E, 880956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FOISCSI = 0x30, 881056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FOFCOE = 0x32, 88113dde7c95SVishal Kulkarni FW_DEVLOG_FACILITY_CHNET = 0x34, 8812*7e6ad469SVishal Kulkarni FW_DEVLOG_FACILITY_COISCSI = 0x36, 88133dde7c95SVishal Kulkarni FW_DEVLOG_FACILITY_MAX = 0x38, 881456b2bdd1SGireesh Nagabhushana }; 881556b2bdd1SGireesh Nagabhushana 881656b2bdd1SGireesh Nagabhushana /* 881756b2bdd1SGireesh Nagabhushana * log message format 881856b2bdd1SGireesh Nagabhushana */ 881956b2bdd1SGireesh Nagabhushana struct fw_devlog_e { 882056b2bdd1SGireesh Nagabhushana __be64 timestamp; 882156b2bdd1SGireesh Nagabhushana __be32 seqno; 882256b2bdd1SGireesh Nagabhushana __be16 reserved1; 882356b2bdd1SGireesh Nagabhushana __u8 level; 882456b2bdd1SGireesh Nagabhushana __u8 facility; 882556b2bdd1SGireesh Nagabhushana __u8 fmt[FW_DEVLOG_FMT_LEN]; 882656b2bdd1SGireesh Nagabhushana __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 882756b2bdd1SGireesh Nagabhushana __be32 reserved3[4]; 882856b2bdd1SGireesh Nagabhushana }; 882956b2bdd1SGireesh Nagabhushana 883056b2bdd1SGireesh Nagabhushana struct fw_devlog_cmd { 883156b2bdd1SGireesh Nagabhushana __be32 op_to_write; 883256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 883356b2bdd1SGireesh Nagabhushana __u8 level; 883456b2bdd1SGireesh Nagabhushana __u8 r2[7]; 883556b2bdd1SGireesh Nagabhushana __be32 memtype_devlog_memaddr16_devlog; 883656b2bdd1SGireesh Nagabhushana __be32 memsize_devlog; 883756b2bdd1SGireesh Nagabhushana __be32 r3[2]; 883856b2bdd1SGireesh Nagabhushana }; 883956b2bdd1SGireesh Nagabhushana 88403dde7c95SVishal Kulkarni #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 88413dde7c95SVishal Kulkarni #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 88423dde7c95SVishal Kulkarni #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 88433dde7c95SVishal Kulkarni ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 88443dde7c95SVishal Kulkarni #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 88453dde7c95SVishal Kulkarni (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 884656b2bdd1SGireesh Nagabhushana 88473dde7c95SVishal Kulkarni #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 88483dde7c95SVishal Kulkarni #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 88493dde7c95SVishal Kulkarni #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 88503dde7c95SVishal Kulkarni ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 88513dde7c95SVishal Kulkarni #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 88523dde7c95SVishal Kulkarni (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 88533dde7c95SVishal Kulkarni M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 885456b2bdd1SGireesh Nagabhushana 885556b2bdd1SGireesh Nagabhushana enum fw_watchdog_actions { 8856de483253SVishal Kulkarni FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8857de483253SVishal Kulkarni FW_WATCHDOG_ACTION_FLR = 1, 8858de483253SVishal Kulkarni FW_WATCHDOG_ACTION_BYPASS = 2, 8859de483253SVishal Kulkarni FW_WATCHDOG_ACTION_TMPCHK = 3, 88603dde7c95SVishal Kulkarni FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8861de483253SVishal Kulkarni 88623dde7c95SVishal Kulkarni FW_WATCHDOG_ACTION_MAX = 5, 886356b2bdd1SGireesh Nagabhushana }; 886456b2bdd1SGireesh Nagabhushana 88653dde7c95SVishal Kulkarni #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 886656b2bdd1SGireesh Nagabhushana 886756b2bdd1SGireesh Nagabhushana struct fw_watchdog_cmd { 8868de483253SVishal Kulkarni __be32 op_to_vfn; 886956b2bdd1SGireesh Nagabhushana __be32 retval_len16; 887056b2bdd1SGireesh Nagabhushana __be32 timeout; 8871de483253SVishal Kulkarni __be32 action; 887256b2bdd1SGireesh Nagabhushana }; 887356b2bdd1SGireesh Nagabhushana 8874de483253SVishal Kulkarni #define S_FW_WATCHDOG_CMD_PFN 8 8875de483253SVishal Kulkarni #define M_FW_WATCHDOG_CMD_PFN 0x7 8876de483253SVishal Kulkarni #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8877de483253SVishal Kulkarni #define G_FW_WATCHDOG_CMD_PFN(x) \ 8878de483253SVishal Kulkarni (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8879de483253SVishal Kulkarni 8880de483253SVishal Kulkarni #define S_FW_WATCHDOG_CMD_VFN 0 8881de483253SVishal Kulkarni #define M_FW_WATCHDOG_CMD_VFN 0xff 8882de483253SVishal Kulkarni #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8883de483253SVishal Kulkarni #define G_FW_WATCHDOG_CMD_VFN(x) \ 8884de483253SVishal Kulkarni (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 88853dde7c95SVishal Kulkarni 888656b2bdd1SGireesh Nagabhushana struct fw_clip_cmd { 888756b2bdd1SGireesh Nagabhushana __be32 op_to_write; 888856b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 888956b2bdd1SGireesh Nagabhushana __be64 ip_hi; 889056b2bdd1SGireesh Nagabhushana __be64 ip_lo; 889156b2bdd1SGireesh Nagabhushana __be32 r4[2]; 889256b2bdd1SGireesh Nagabhushana }; 889356b2bdd1SGireesh Nagabhushana 88943dde7c95SVishal Kulkarni #define S_FW_CLIP_CMD_ALLOC 31 88953dde7c95SVishal Kulkarni #define M_FW_CLIP_CMD_ALLOC 0x1 88963dde7c95SVishal Kulkarni #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 88973dde7c95SVishal Kulkarni #define G_FW_CLIP_CMD_ALLOC(x) \ 88983dde7c95SVishal Kulkarni (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 88993dde7c95SVishal Kulkarni #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 890056b2bdd1SGireesh Nagabhushana 89013dde7c95SVishal Kulkarni #define S_FW_CLIP_CMD_FREE 30 89023dde7c95SVishal Kulkarni #define M_FW_CLIP_CMD_FREE 0x1 89033dde7c95SVishal Kulkarni #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 89043dde7c95SVishal Kulkarni #define G_FW_CLIP_CMD_FREE(x) \ 89053dde7c95SVishal Kulkarni (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 89063dde7c95SVishal Kulkarni #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 890756b2bdd1SGireesh Nagabhushana 8908*7e6ad469SVishal Kulkarni #define S_FW_CLIP_CMD_INDEX 16 8909*7e6ad469SVishal Kulkarni #define M_FW_CLIP_CMD_INDEX 0x1fff 8910*7e6ad469SVishal Kulkarni #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 8911*7e6ad469SVishal Kulkarni #define G_FW_CLIP_CMD_INDEX(x) \ 8912*7e6ad469SVishal Kulkarni (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 8913*7e6ad469SVishal Kulkarni 89143dde7c95SVishal Kulkarni /****************************************************************************** 89153dde7c95SVishal Kulkarni * F O i S C S I C O M M A N D s 89163dde7c95SVishal Kulkarni **************************************/ 891756b2bdd1SGireesh Nagabhushana 891856b2bdd1SGireesh Nagabhushana #define FW_CHNET_IFACE_ADDR_MAX 3 891956b2bdd1SGireesh Nagabhushana 892056b2bdd1SGireesh Nagabhushana enum fw_chnet_iface_cmd_subop { 892156b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 892256b2bdd1SGireesh Nagabhushana 892356b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 892456b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 892556b2bdd1SGireesh Nagabhushana 892656b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 892756b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 892856b2bdd1SGireesh Nagabhushana 892956b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MAX, 893056b2bdd1SGireesh Nagabhushana }; 893156b2bdd1SGireesh Nagabhushana 893256b2bdd1SGireesh Nagabhushana struct fw_chnet_iface_cmd { 893356b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 893456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 893556b2bdd1SGireesh Nagabhushana __u8 subop; 8936*7e6ad469SVishal Kulkarni __u8 r2[2]; 8937*7e6ad469SVishal Kulkarni __u8 flags; 893856b2bdd1SGireesh Nagabhushana __be32 ifid_ifstate; 893956b2bdd1SGireesh Nagabhushana __be16 mtu; 894056b2bdd1SGireesh Nagabhushana __be16 vlanid; 894156b2bdd1SGireesh Nagabhushana __be32 r3; 894256b2bdd1SGireesh Nagabhushana __be16 r4; 894356b2bdd1SGireesh Nagabhushana __u8 mac[6]; 894456b2bdd1SGireesh Nagabhushana }; 894556b2bdd1SGireesh Nagabhushana 89463dde7c95SVishal Kulkarni #define S_FW_CHNET_IFACE_CMD_PORTID 0 89473dde7c95SVishal Kulkarni #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 89483dde7c95SVishal Kulkarni #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 89493dde7c95SVishal Kulkarni #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 89503dde7c95SVishal Kulkarni (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 895156b2bdd1SGireesh Nagabhushana 89523dde7c95SVishal Kulkarni #define S_FW_CHNET_IFACE_CMD_IFID 8 89533dde7c95SVishal Kulkarni #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 89543dde7c95SVishal Kulkarni #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 89553dde7c95SVishal Kulkarni #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 89563dde7c95SVishal Kulkarni (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 895756b2bdd1SGireesh Nagabhushana 89583dde7c95SVishal Kulkarni #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 89593dde7c95SVishal Kulkarni #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 89603dde7c95SVishal Kulkarni #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 89613dde7c95SVishal Kulkarni #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 89623dde7c95SVishal Kulkarni (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 896356b2bdd1SGireesh Nagabhushana 896456b2bdd1SGireesh Nagabhushana struct fw_fcoe_res_info_cmd { 896556b2bdd1SGireesh Nagabhushana __be32 op_to_read; 896656b2bdd1SGireesh Nagabhushana __be32 retval_len16; 896756b2bdd1SGireesh Nagabhushana __be16 e_d_tov; 896856b2bdd1SGireesh Nagabhushana __be16 r_a_tov_seq; 896956b2bdd1SGireesh Nagabhushana __be16 r_a_tov_els; 897056b2bdd1SGireesh Nagabhushana __be16 r_r_tov; 897156b2bdd1SGireesh Nagabhushana __be32 max_xchgs; 897256b2bdd1SGireesh Nagabhushana __be32 max_ssns; 897356b2bdd1SGireesh Nagabhushana __be32 used_xchgs; 897456b2bdd1SGireesh Nagabhushana __be32 used_ssns; 897556b2bdd1SGireesh Nagabhushana __be32 max_fcfs; 897656b2bdd1SGireesh Nagabhushana __be32 max_vnps; 897756b2bdd1SGireesh Nagabhushana __be32 used_fcfs; 897856b2bdd1SGireesh Nagabhushana __be32 used_vnps; 897956b2bdd1SGireesh Nagabhushana }; 898056b2bdd1SGireesh Nagabhushana 898156b2bdd1SGireesh Nagabhushana struct fw_fcoe_link_cmd { 898256b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 898356b2bdd1SGireesh Nagabhushana __be32 retval_len16; 898456b2bdd1SGireesh Nagabhushana __be32 sub_opcode_fcfi; 898556b2bdd1SGireesh Nagabhushana __u8 r3; 898656b2bdd1SGireesh Nagabhushana __u8 lstatus; 898756b2bdd1SGireesh Nagabhushana __be16 flags; 898856b2bdd1SGireesh Nagabhushana __u8 r4; 898956b2bdd1SGireesh Nagabhushana __u8 set_vlan; 899056b2bdd1SGireesh Nagabhushana __be16 vlan_id; 899156b2bdd1SGireesh Nagabhushana __be32 vnpi_pkd; 899256b2bdd1SGireesh Nagabhushana __be16 r6; 899356b2bdd1SGireesh Nagabhushana __u8 phy_mac[6]; 899456b2bdd1SGireesh Nagabhushana __u8 vnport_wwnn[8]; 899556b2bdd1SGireesh Nagabhushana __u8 vnport_wwpn[8]; 899656b2bdd1SGireesh Nagabhushana }; 899756b2bdd1SGireesh Nagabhushana 89983dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_PORTID 0 89993dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_PORTID 0xf 90003dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 90013dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 90023dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 900356b2bdd1SGireesh Nagabhushana 90043dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 90053dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 90063dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 90073dde7c95SVishal Kulkarni ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 90083dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 90093dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 901056b2bdd1SGireesh Nagabhushana 90113dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_FCFI 0 90123dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 90133dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 90143dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 90153dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 901656b2bdd1SGireesh Nagabhushana 90173dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_VNPI 0 90183dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 90193dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 90203dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 90213dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 902256b2bdd1SGireesh Nagabhushana 902356b2bdd1SGireesh Nagabhushana struct fw_fcoe_vnp_cmd { 902456b2bdd1SGireesh Nagabhushana __be32 op_to_fcfi; 902556b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 902656b2bdd1SGireesh Nagabhushana __be32 gen_wwn_to_vnpi; 902756b2bdd1SGireesh Nagabhushana __be32 vf_id; 902856b2bdd1SGireesh Nagabhushana __be16 iqid; 902956b2bdd1SGireesh Nagabhushana __u8 vnport_mac[6]; 903056b2bdd1SGireesh Nagabhushana __u8 vnport_wwnn[8]; 903156b2bdd1SGireesh Nagabhushana __u8 vnport_wwpn[8]; 903256b2bdd1SGireesh Nagabhushana __u8 cmn_srv_parms[16]; 903356b2bdd1SGireesh Nagabhushana __u8 clsp_word_0_1[8]; 903456b2bdd1SGireesh Nagabhushana }; 903556b2bdd1SGireesh Nagabhushana 90363dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_FCFI 0 90373dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 90383dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 90393dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 90403dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 90413dde7c95SVishal Kulkarni 90423dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_ALLOC 31 90433dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 90443dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 90453dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 90463dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 90473dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 90483dde7c95SVishal Kulkarni 90493dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_FREE 30 90503dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_FREE 0x1 90513dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 90523dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_FREE(x) \ 90533dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 90543dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 90553dde7c95SVishal Kulkarni 90563dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_MODIFY 29 90573dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 90583dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 90593dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 90603dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 90613dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 90623dde7c95SVishal Kulkarni 90633dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 90643dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 90653dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 90663dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 90673dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 90683dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 90693dde7c95SVishal Kulkarni 90703dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_PERSIST 21 90713dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 90723dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 90733dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 90743dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 90753dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 90763dde7c95SVishal Kulkarni 90773dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_VFID_EN 20 90783dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 90793dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 90803dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 90813dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 90823dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 90833dde7c95SVishal Kulkarni 90843dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_VNPI 0 90853dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 90863dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 90873dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 90883dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 908956b2bdd1SGireesh Nagabhushana 909056b2bdd1SGireesh Nagabhushana struct fw_fcoe_sparams_cmd { 909156b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 909256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 909356b2bdd1SGireesh Nagabhushana __u8 r3[7]; 909456b2bdd1SGireesh Nagabhushana __u8 cos; 909556b2bdd1SGireesh Nagabhushana __u8 lport_wwnn[8]; 909656b2bdd1SGireesh Nagabhushana __u8 lport_wwpn[8]; 909756b2bdd1SGireesh Nagabhushana __u8 cmn_srv_parms[16]; 909856b2bdd1SGireesh Nagabhushana __u8 cls_srv_parms[16]; 909956b2bdd1SGireesh Nagabhushana }; 910056b2bdd1SGireesh Nagabhushana 91013dde7c95SVishal Kulkarni #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 91023dde7c95SVishal Kulkarni #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 91033dde7c95SVishal Kulkarni #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 91043dde7c95SVishal Kulkarni #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 91053dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 910656b2bdd1SGireesh Nagabhushana 910756b2bdd1SGireesh Nagabhushana struct fw_fcoe_stats_cmd { 910856b2bdd1SGireesh Nagabhushana __be32 op_to_flowid; 910956b2bdd1SGireesh Nagabhushana __be32 free_to_len16; 911056b2bdd1SGireesh Nagabhushana union fw_fcoe_stats { 911156b2bdd1SGireesh Nagabhushana struct fw_fcoe_stats_ctl { 911256b2bdd1SGireesh Nagabhushana __u8 nstats_port; 911356b2bdd1SGireesh Nagabhushana __u8 port_valid_ix; 911456b2bdd1SGireesh Nagabhushana __be16 r6; 911556b2bdd1SGireesh Nagabhushana __be32 r7; 911656b2bdd1SGireesh Nagabhushana __be64 stat0; 911756b2bdd1SGireesh Nagabhushana __be64 stat1; 911856b2bdd1SGireesh Nagabhushana __be64 stat2; 911956b2bdd1SGireesh Nagabhushana __be64 stat3; 912056b2bdd1SGireesh Nagabhushana __be64 stat4; 912156b2bdd1SGireesh Nagabhushana __be64 stat5; 912256b2bdd1SGireesh Nagabhushana } ctl; 912356b2bdd1SGireesh Nagabhushana struct fw_fcoe_port_stats { 912456b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 912556b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 912656b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 912756b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 912856b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 912956b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 913056b2bdd1SGireesh Nagabhushana __be64 tx_drop_frames; 913156b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 913256b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 913356b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 913456b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 913556b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 913656b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 913756b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 913856b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 913956b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 914056b2bdd1SGireesh Nagabhushana } port_stats; 914156b2bdd1SGireesh Nagabhushana struct fw_fcoe_fcf_stats { 914256b2bdd1SGireesh Nagabhushana __be32 fip_tx_bytes; 914356b2bdd1SGireesh Nagabhushana __be32 fip_tx_fr; 914456b2bdd1SGireesh Nagabhushana __be64 fcf_ka; 914556b2bdd1SGireesh Nagabhushana __be64 mcast_adv_rcvd; 914656b2bdd1SGireesh Nagabhushana __be16 ucast_adv_rcvd; 914756b2bdd1SGireesh Nagabhushana __be16 sol_sent; 914856b2bdd1SGireesh Nagabhushana __be16 vlan_req; 914956b2bdd1SGireesh Nagabhushana __be16 vlan_rpl; 915056b2bdd1SGireesh Nagabhushana __be16 clr_vlink; 915156b2bdd1SGireesh Nagabhushana __be16 link_down; 915256b2bdd1SGireesh Nagabhushana __be16 link_up; 915356b2bdd1SGireesh Nagabhushana __be16 logo; 915456b2bdd1SGireesh Nagabhushana __be16 flogi_req; 915556b2bdd1SGireesh Nagabhushana __be16 flogi_rpl; 915656b2bdd1SGireesh Nagabhushana __be16 fdisc_req; 915756b2bdd1SGireesh Nagabhushana __be16 fdisc_rpl; 915856b2bdd1SGireesh Nagabhushana __be16 fka_prd_chg; 915956b2bdd1SGireesh Nagabhushana __be16 fc_map_chg; 916056b2bdd1SGireesh Nagabhushana __be16 vfid_chg; 916156b2bdd1SGireesh Nagabhushana __u8 no_fka_req; 916256b2bdd1SGireesh Nagabhushana __u8 no_vnp; 916356b2bdd1SGireesh Nagabhushana } fcf_stats; 916456b2bdd1SGireesh Nagabhushana struct fw_fcoe_pcb_stats { 916556b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 916656b2bdd1SGireesh Nagabhushana __be64 tx_frames; 916756b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 916856b2bdd1SGireesh Nagabhushana __be64 rx_frames; 916956b2bdd1SGireesh Nagabhushana __be32 vnp_ka; 917056b2bdd1SGireesh Nagabhushana __be32 unsol_els_rcvd; 917156b2bdd1SGireesh Nagabhushana __be64 unsol_cmd_rcvd; 917256b2bdd1SGireesh Nagabhushana __be16 implicit_logo; 917356b2bdd1SGireesh Nagabhushana __be16 flogi_inv_sparm; 917456b2bdd1SGireesh Nagabhushana __be16 fdisc_inv_sparm; 917556b2bdd1SGireesh Nagabhushana __be16 flogi_rjt; 917656b2bdd1SGireesh Nagabhushana __be16 fdisc_rjt; 917756b2bdd1SGireesh Nagabhushana __be16 no_ssn; 917856b2bdd1SGireesh Nagabhushana __be16 mac_flt_fail; 917956b2bdd1SGireesh Nagabhushana __be16 inv_fr_rcvd; 918056b2bdd1SGireesh Nagabhushana } pcb_stats; 918156b2bdd1SGireesh Nagabhushana struct fw_fcoe_scb_stats { 918256b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 918356b2bdd1SGireesh Nagabhushana __be64 tx_frames; 918456b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 918556b2bdd1SGireesh Nagabhushana __be64 rx_frames; 918656b2bdd1SGireesh Nagabhushana __be32 host_abrt_req; 918756b2bdd1SGireesh Nagabhushana __be32 adap_auto_abrt; 918856b2bdd1SGireesh Nagabhushana __be32 adap_abrt_rsp; 918956b2bdd1SGireesh Nagabhushana __be32 host_ios_req; 919056b2bdd1SGireesh Nagabhushana __be16 ssn_offl_ios; 919156b2bdd1SGireesh Nagabhushana __be16 ssn_not_rdy_ios; 919256b2bdd1SGireesh Nagabhushana __u8 rx_data_ddp_err; 919356b2bdd1SGireesh Nagabhushana __u8 ddp_flt_set_err; 919456b2bdd1SGireesh Nagabhushana __be16 rx_data_fr_err; 919556b2bdd1SGireesh Nagabhushana __u8 bad_st_abrt_req; 919656b2bdd1SGireesh Nagabhushana __u8 no_io_abrt_req; 919756b2bdd1SGireesh Nagabhushana __u8 abort_tmo; 919856b2bdd1SGireesh Nagabhushana __u8 abort_tmo_2; 919956b2bdd1SGireesh Nagabhushana __be32 abort_req; 920056b2bdd1SGireesh Nagabhushana __u8 no_ppod_res_tmo; 920156b2bdd1SGireesh Nagabhushana __u8 bp_tmo; 920256b2bdd1SGireesh Nagabhushana __u8 adap_auto_cls; 920356b2bdd1SGireesh Nagabhushana __u8 no_io_cls_req; 920456b2bdd1SGireesh Nagabhushana __be32 host_cls_req; 920556b2bdd1SGireesh Nagabhushana __be64 unsol_cmd_rcvd; 920656b2bdd1SGireesh Nagabhushana __be32 plogi_req_rcvd; 920756b2bdd1SGireesh Nagabhushana __be32 prli_req_rcvd; 920856b2bdd1SGireesh Nagabhushana __be16 logo_req_rcvd; 920956b2bdd1SGireesh Nagabhushana __be16 prlo_req_rcvd; 921056b2bdd1SGireesh Nagabhushana __be16 plogi_rjt_rcvd; 921156b2bdd1SGireesh Nagabhushana __be16 prli_rjt_rcvd; 921256b2bdd1SGireesh Nagabhushana __be32 adisc_req_rcvd; 921356b2bdd1SGireesh Nagabhushana __be32 rscn_rcvd; 921456b2bdd1SGireesh Nagabhushana __be32 rrq_req_rcvd; 921556b2bdd1SGireesh Nagabhushana __be32 unsol_els_rcvd; 921656b2bdd1SGireesh Nagabhushana __u8 adisc_rjt_rcvd; 921756b2bdd1SGireesh Nagabhushana __u8 scr_rjt; 921856b2bdd1SGireesh Nagabhushana __u8 ct_rjt; 921956b2bdd1SGireesh Nagabhushana __u8 inval_bls_rcvd; 922056b2bdd1SGireesh Nagabhushana __be32 ba_rjt_rcvd; 922156b2bdd1SGireesh Nagabhushana } scb_stats; 922256b2bdd1SGireesh Nagabhushana } u; 922356b2bdd1SGireesh Nagabhushana }; 922456b2bdd1SGireesh Nagabhushana 92253dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_FLOWID 0 92263dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 92273dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 92283dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 92293dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 92303dde7c95SVishal Kulkarni 92313dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_FREE 30 92323dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_FREE 0x1 92333dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 92343dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_FREE(x) \ 92353dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 92363dde7c95SVishal Kulkarni #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 92373dde7c95SVishal Kulkarni 92383dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_NSTATS 4 92393dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 92403dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 92413dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 92423dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 92433dde7c95SVishal Kulkarni 92443dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_PORT 0 92453dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_PORT 0x3 92463dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 92473dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_PORT(x) \ 92483dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 92493dde7c95SVishal Kulkarni 92503dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 92513dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 92523dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 92533dde7c95SVishal Kulkarni ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 92543dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 92553dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 92563dde7c95SVishal Kulkarni #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 92573dde7c95SVishal Kulkarni 92583dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_IX 0 92593dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_IX 0x3f 92603dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 92613dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_IX(x) \ 92623dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 926356b2bdd1SGireesh Nagabhushana 926456b2bdd1SGireesh Nagabhushana struct fw_fcoe_fcf_cmd { 926556b2bdd1SGireesh Nagabhushana __be32 op_to_fcfi; 926656b2bdd1SGireesh Nagabhushana __be32 retval_len16; 926756b2bdd1SGireesh Nagabhushana __be16 priority_pkd; 926856b2bdd1SGireesh Nagabhushana __u8 mac[6]; 926956b2bdd1SGireesh Nagabhushana __u8 name_id[8]; 927056b2bdd1SGireesh Nagabhushana __u8 fabric[8]; 927156b2bdd1SGireesh Nagabhushana __be16 vf_id; 927256b2bdd1SGireesh Nagabhushana __be16 max_fcoe_size; 927356b2bdd1SGireesh Nagabhushana __u8 vlan_id; 927456b2bdd1SGireesh Nagabhushana __u8 fc_map[3]; 927556b2bdd1SGireesh Nagabhushana __be32 fka_adv; 927656b2bdd1SGireesh Nagabhushana __be32 r6; 927756b2bdd1SGireesh Nagabhushana __u8 r7_hi; 927856b2bdd1SGireesh Nagabhushana __u8 fpma_to_portid; 927956b2bdd1SGireesh Nagabhushana __u8 spma_mac[6]; 928056b2bdd1SGireesh Nagabhushana __be64 r8; 928156b2bdd1SGireesh Nagabhushana }; 928256b2bdd1SGireesh Nagabhushana 92833dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_FCFI 0 92843dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 92853dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 92863dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 92873dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 92883dde7c95SVishal Kulkarni 92893dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_PRIORITY 0 92903dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 92913dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 92923dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 92933dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 92943dde7c95SVishal Kulkarni 92953dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_FPMA 6 92963dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_FPMA 0x1 92973dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 92983dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 92993dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 93003dde7c95SVishal Kulkarni #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 93013dde7c95SVishal Kulkarni 93023dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_SPMA 5 93033dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_SPMA 0x1 93043dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 93053dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 93063dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 93073dde7c95SVishal Kulkarni #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 93083dde7c95SVishal Kulkarni 93093dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_LOGIN 4 93103dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 93113dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 93123dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 93133dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 93143dde7c95SVishal Kulkarni #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 93153dde7c95SVishal Kulkarni 93163dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_PORTID 0 93173dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_PORTID 0xf 93183dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 93193dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 93203dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 93213dde7c95SVishal Kulkarni 93223dde7c95SVishal Kulkarni /****************************************************************************** 93233dde7c95SVishal Kulkarni * E R R O R a n d D E B U G C O M M A N D s 93243dde7c95SVishal Kulkarni ******************************************************/ 932556b2bdd1SGireesh Nagabhushana 932656b2bdd1SGireesh Nagabhushana enum fw_error_type { 9327de483253SVishal Kulkarni FW_ERROR_TYPE_EXCEPTION = 0x0, 9328de483253SVishal Kulkarni FW_ERROR_TYPE_HWMODULE = 0x1, 9329de483253SVishal Kulkarni FW_ERROR_TYPE_WR = 0x2, 9330de483253SVishal Kulkarni FW_ERROR_TYPE_ACL = 0x3, 933156b2bdd1SGireesh Nagabhushana }; 933256b2bdd1SGireesh Nagabhushana 93333dde7c95SVishal Kulkarni enum fw_dcb_ieee_locations { 93343dde7c95SVishal Kulkarni FW_IEEE_LOC_LOCAL, 93353dde7c95SVishal Kulkarni FW_IEEE_LOC_PEER, 93363dde7c95SVishal Kulkarni FW_IEEE_LOC_OPERATIONAL, 93373dde7c95SVishal Kulkarni }; 93383dde7c95SVishal Kulkarni 93393dde7c95SVishal Kulkarni struct fw_dcb_ieee_cmd { 93403dde7c95SVishal Kulkarni __be32 op_to_location; 93413dde7c95SVishal Kulkarni __be32 changed_to_len16; 93423dde7c95SVishal Kulkarni union fw_dcbx_stats { 93433dde7c95SVishal Kulkarni struct fw_dcbx_pfc_stats_ieee { 93443dde7c95SVishal Kulkarni __be32 pfc_mbc_pkd; 93453dde7c95SVishal Kulkarni __be32 pfc_willing_to_pfc_en; 93463dde7c95SVishal Kulkarni } dcbx_pfc_stats; 93473dde7c95SVishal Kulkarni struct fw_dcbx_ets_stats_ieee { 93483dde7c95SVishal Kulkarni __be32 cbs_to_ets_max_tc; 93493dde7c95SVishal Kulkarni __be32 pg_table; 93503dde7c95SVishal Kulkarni __u8 pg_percent[8]; 93513dde7c95SVishal Kulkarni __u8 tsa[8]; 93523dde7c95SVishal Kulkarni } dcbx_ets_stats; 93533dde7c95SVishal Kulkarni struct fw_dcbx_app_stats_ieee { 93543dde7c95SVishal Kulkarni __be32 num_apps_pkd; 93553dde7c95SVishal Kulkarni __be32 r6; 93563dde7c95SVishal Kulkarni __be32 app[4]; 93573dde7c95SVishal Kulkarni } dcbx_app_stats; 93583dde7c95SVishal Kulkarni struct fw_dcbx_control { 93593dde7c95SVishal Kulkarni __be32 multi_peer_invalidated; 9360*7e6ad469SVishal Kulkarni __u8 version; 9361*7e6ad469SVishal Kulkarni __u8 r6[3]; 93623dde7c95SVishal Kulkarni } dcbx_control; 93633dde7c95SVishal Kulkarni } u; 93643dde7c95SVishal Kulkarni }; 93653dde7c95SVishal Kulkarni 93663dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PORT 8 93673dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PORT 0x7 93683dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 93693dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PORT(x) \ 93703dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 93713dde7c95SVishal Kulkarni 93723dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_FEATURE 2 93733dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 93743dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 93753dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 93763dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 93773dde7c95SVishal Kulkarni 93783dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_LOCATION 0 93793dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 93803dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 93813dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 93823dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 93833dde7c95SVishal Kulkarni 93843dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_CHANGED 20 93853dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 93863dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 93873dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 93883dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 93893dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 93903dde7c95SVishal Kulkarni 93913dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_RECEIVED 19 93923dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 93933dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 93943dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 93953dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 93963dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 93973dde7c95SVishal Kulkarni 93983dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APPLY 18 93993dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APPLY 0x1 94003dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 94013dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 94023dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 94033dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 94043dde7c95SVishal Kulkarni 94053dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_DISABLED 17 94063dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 94073dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 94083dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 94093dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 94103dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 94113dde7c95SVishal Kulkarni 94123dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_MORE 16 94133dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_MORE 0x1 94143dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 94153dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_MORE(x) \ 94163dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 94173dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 94183dde7c95SVishal Kulkarni 94193dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 94203dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 94213dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 94223dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 94233dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 94243dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 94253dde7c95SVishal Kulkarni 94263dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 94273dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 94283dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 94293dde7c95SVishal Kulkarni ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 94303dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 94313dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 94323dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 94333dde7c95SVishal Kulkarni 94343dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 94353dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 94363dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 94373dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 94383dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 94393dde7c95SVishal Kulkarni 94403dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_EN 0 94413dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 94423dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 94433dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 94443dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 94453dde7c95SVishal Kulkarni 94463dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_CBS 16 94473dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_CBS 0x1 94483dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 94493dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_CBS(x) \ 94503dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 94513dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 94523dde7c95SVishal Kulkarni 94533dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 94543dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 94553dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 94563dde7c95SVishal Kulkarni ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 94573dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 94583dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 94593dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 94603dde7c95SVishal Kulkarni 94613dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 94623dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 94633dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 94643dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 94653dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 94663dde7c95SVishal Kulkarni 94673dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 94683dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 94693dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 94703dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 94713dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 94723dde7c95SVishal Kulkarni 94733dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 94743dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 94753dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 94763dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 94773dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 94783dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 94793dde7c95SVishal Kulkarni 94803dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 94813dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 94823dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 94833dde7c95SVishal Kulkarni ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 94843dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 94853dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 94863dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 94873dde7c95SVishal Kulkarni 94883dde7c95SVishal Kulkarni /* Hand-written */ 94893dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 94903dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 94913dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 94923dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 94933dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 94943dde7c95SVishal Kulkarni 94953dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 94963dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 94973dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 94983dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 94993dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 95003dde7c95SVishal Kulkarni 95013dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 95023dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 95033dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 95043dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 95053dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 95063dde7c95SVishal Kulkarni 95073dde7c95SVishal Kulkarni 950856b2bdd1SGireesh Nagabhushana struct fw_error_cmd { 950956b2bdd1SGireesh Nagabhushana __be32 op_to_type; 951056b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 951156b2bdd1SGireesh Nagabhushana union fw_error { 951256b2bdd1SGireesh Nagabhushana struct fw_error_exception { 951356b2bdd1SGireesh Nagabhushana __be32 info[6]; 951456b2bdd1SGireesh Nagabhushana } exception; 951556b2bdd1SGireesh Nagabhushana struct fw_error_hwmodule { 951656b2bdd1SGireesh Nagabhushana __be32 regaddr; 951756b2bdd1SGireesh Nagabhushana __be32 regval; 951856b2bdd1SGireesh Nagabhushana } hwmodule; 951956b2bdd1SGireesh Nagabhushana struct fw_error_wr { 952056b2bdd1SGireesh Nagabhushana __be16 cidx; 952156b2bdd1SGireesh Nagabhushana __be16 pfn_vfn; 952256b2bdd1SGireesh Nagabhushana __be32 eqid; 952356b2bdd1SGireesh Nagabhushana __u8 wrhdr[16]; 952456b2bdd1SGireesh Nagabhushana } wr; 952556b2bdd1SGireesh Nagabhushana struct fw_error_acl { 952656b2bdd1SGireesh Nagabhushana __be16 cidx; 952756b2bdd1SGireesh Nagabhushana __be16 pfn_vfn; 952856b2bdd1SGireesh Nagabhushana __be32 eqid; 952956b2bdd1SGireesh Nagabhushana __be16 mv_pkd; 953056b2bdd1SGireesh Nagabhushana __u8 val[6]; 953156b2bdd1SGireesh Nagabhushana __be64 r4; 953256b2bdd1SGireesh Nagabhushana } acl; 953356b2bdd1SGireesh Nagabhushana } u; 953456b2bdd1SGireesh Nagabhushana }; 953556b2bdd1SGireesh Nagabhushana 95363dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_FATAL 4 95373dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_FATAL 0x1 95383dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 95393dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_FATAL(x) \ 95403dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 95413dde7c95SVishal Kulkarni #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 95423dde7c95SVishal Kulkarni 95433dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_TYPE 0 95443dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_TYPE 0xf 95453dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 95463dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_TYPE(x) \ 95473dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 95483dde7c95SVishal Kulkarni 95493dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_PFN 8 95503dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_PFN 0x7 95513dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 95523dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_PFN(x) \ 95533dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 95543dde7c95SVishal Kulkarni 95553dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_VFN 0 95563dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_VFN 0xff 95573dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 95583dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_VFN(x) \ 95593dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 95603dde7c95SVishal Kulkarni 95613dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_PFN 8 95623dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_PFN 0x7 95633dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 95643dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_PFN(x) \ 95653dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 95663dde7c95SVishal Kulkarni 95673dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_VFN 0 95683dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_VFN 0xff 95693dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 95703dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_VFN(x) \ 95713dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 95723dde7c95SVishal Kulkarni 95733dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_MV 15 95743dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_MV 0x1 95753dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 95763dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_MV(x) \ 95773dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 95783dde7c95SVishal Kulkarni #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 957956b2bdd1SGireesh Nagabhushana 958056b2bdd1SGireesh Nagabhushana struct fw_debug_cmd { 958156b2bdd1SGireesh Nagabhushana __be32 op_type; 958256b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 958356b2bdd1SGireesh Nagabhushana union fw_debug { 958456b2bdd1SGireesh Nagabhushana struct fw_debug_assert { 958556b2bdd1SGireesh Nagabhushana __be32 fcid; 958656b2bdd1SGireesh Nagabhushana __be32 line; 958756b2bdd1SGireesh Nagabhushana __be32 x; 958856b2bdd1SGireesh Nagabhushana __be32 y; 958956b2bdd1SGireesh Nagabhushana __u8 filename_0_7[8]; 959056b2bdd1SGireesh Nagabhushana __u8 filename_8_15[8]; 959156b2bdd1SGireesh Nagabhushana __be64 r3; 959256b2bdd1SGireesh Nagabhushana } assert; 959356b2bdd1SGireesh Nagabhushana struct fw_debug_prt { 959456b2bdd1SGireesh Nagabhushana __be16 dprtstridx; 959556b2bdd1SGireesh Nagabhushana __be16 r3[3]; 959656b2bdd1SGireesh Nagabhushana __be32 dprtstrparam0; 959756b2bdd1SGireesh Nagabhushana __be32 dprtstrparam1; 959856b2bdd1SGireesh Nagabhushana __be32 dprtstrparam2; 959956b2bdd1SGireesh Nagabhushana __be32 dprtstrparam3; 960056b2bdd1SGireesh Nagabhushana } prt; 960156b2bdd1SGireesh Nagabhushana } u; 960256b2bdd1SGireesh Nagabhushana }; 960356b2bdd1SGireesh Nagabhushana 96043dde7c95SVishal Kulkarni #define S_FW_DEBUG_CMD_TYPE 0 96053dde7c95SVishal Kulkarni #define M_FW_DEBUG_CMD_TYPE 0xff 96063dde7c95SVishal Kulkarni #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 96073dde7c95SVishal Kulkarni #define G_FW_DEBUG_CMD_TYPE(x) \ 96083dde7c95SVishal Kulkarni (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 960956b2bdd1SGireesh Nagabhushana 96103dde7c95SVishal Kulkarni enum fw_diag_cmd_type { 96113dde7c95SVishal Kulkarni FW_DIAG_CMD_TYPE_OFLDIAG = 0, 96123dde7c95SVishal Kulkarni }; 96133dde7c95SVishal Kulkarni 96143dde7c95SVishal Kulkarni enum fw_diag_cmd_ofldiag_op { 96153dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 96163dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_START, 96173dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_STOP, 96183dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 96193dde7c95SVishal Kulkarni }; 96203dde7c95SVishal Kulkarni 96213dde7c95SVishal Kulkarni enum fw_diag_cmd_ofldiag_status { 96223dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 96233dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 96243dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 96253dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 96263dde7c95SVishal Kulkarni }; 96273dde7c95SVishal Kulkarni 96283dde7c95SVishal Kulkarni struct fw_diag_cmd { 96293dde7c95SVishal Kulkarni __be32 op_type; 96303dde7c95SVishal Kulkarni __be32 len16_pkd; 96313dde7c95SVishal Kulkarni union fw_diag_test { 96323dde7c95SVishal Kulkarni struct fw_diag_test_ofldiag { 96333dde7c95SVishal Kulkarni __u8 test_op; 96343dde7c95SVishal Kulkarni __u8 r3; 96353dde7c95SVishal Kulkarni __be16 test_status; 96363dde7c95SVishal Kulkarni __be32 duration; 96373dde7c95SVishal Kulkarni } ofldiag; 96383dde7c95SVishal Kulkarni } u; 96393dde7c95SVishal Kulkarni }; 96403dde7c95SVishal Kulkarni 96413dde7c95SVishal Kulkarni #define S_FW_DIAG_CMD_TYPE 0 96423dde7c95SVishal Kulkarni #define M_FW_DIAG_CMD_TYPE 0xff 96433dde7c95SVishal Kulkarni #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 96443dde7c95SVishal Kulkarni #define G_FW_DIAG_CMD_TYPE(x) \ 96453dde7c95SVishal Kulkarni (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 96463dde7c95SVishal Kulkarni 9647*7e6ad469SVishal Kulkarni struct fw_hma_cmd { 9648*7e6ad469SVishal Kulkarni __be32 op_pkd; 9649*7e6ad469SVishal Kulkarni __be32 retval_len16; 9650*7e6ad469SVishal Kulkarni __be32 mode_to_pcie_params; 9651*7e6ad469SVishal Kulkarni __be32 naddr_size; 9652*7e6ad469SVishal Kulkarni __be32 addr_size_pkd; 9653*7e6ad469SVishal Kulkarni __be32 r6; 9654*7e6ad469SVishal Kulkarni __be64 phy_address[5]; 9655*7e6ad469SVishal Kulkarni }; 9656*7e6ad469SVishal Kulkarni 9657*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_MODE 31 9658*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_MODE 0x1 9659*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9660*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_MODE(x) \ 9661*7e6ad469SVishal Kulkarni (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9662*7e6ad469SVishal Kulkarni #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9663*7e6ad469SVishal Kulkarni 9664*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_SOC 30 9665*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_SOC 0x1 9666*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9667*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9668*7e6ad469SVishal Kulkarni #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9669*7e6ad469SVishal Kulkarni 9670*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_EOC 29 9671*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_EOC 0x1 9672*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9673*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9674*7e6ad469SVishal Kulkarni #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9675*7e6ad469SVishal Kulkarni 9676*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_PCIE_PARAMS 0 9677*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9678*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9679*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9680*7e6ad469SVishal Kulkarni (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9681*7e6ad469SVishal Kulkarni 9682*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_NADDR 12 9683*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_NADDR 0x3f 9684*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9685*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_NADDR(x) \ 9686*7e6ad469SVishal Kulkarni (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9687*7e6ad469SVishal Kulkarni 9688*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_SIZE 0 9689*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_SIZE 0xfff 9690*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9691*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_SIZE(x) \ 9692*7e6ad469SVishal Kulkarni (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9693*7e6ad469SVishal Kulkarni 9694*7e6ad469SVishal Kulkarni #define S_FW_HMA_CMD_ADDR_SIZE 11 9695*7e6ad469SVishal Kulkarni #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9696*7e6ad469SVishal Kulkarni #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9697*7e6ad469SVishal Kulkarni #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9698*7e6ad469SVishal Kulkarni (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9699*7e6ad469SVishal Kulkarni 97003dde7c95SVishal Kulkarni /****************************************************************************** 97013dde7c95SVishal Kulkarni * P C I E F W R E G I S T E R 97023dde7c95SVishal Kulkarni **************************************/ 970356b2bdd1SGireesh Nagabhushana 9704de483253SVishal Kulkarni enum pcie_fw_eval { 9705de483253SVishal Kulkarni PCIE_FW_EVAL_CRASH = 0, 9706de483253SVishal Kulkarni PCIE_FW_EVAL_PREP = 1, 9707de483253SVishal Kulkarni PCIE_FW_EVAL_CONF = 2, 9708de483253SVishal Kulkarni PCIE_FW_EVAL_INIT = 3, 9709de483253SVishal Kulkarni PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9710de483253SVishal Kulkarni PCIE_FW_EVAL_OVERHEAT = 5, 9711de483253SVishal Kulkarni PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9712de483253SVishal Kulkarni }; 9713de483253SVishal Kulkarni 97143dde7c95SVishal Kulkarni /** 971556b2bdd1SGireesh Nagabhushana * Register definitions for the PCIE_FW register which the firmware uses 9716de483253SVishal Kulkarni * to retain status across RESETs. This register should be considered 971756b2bdd1SGireesh Nagabhushana * as a READ-ONLY register for Host Software and only to be used to 971856b2bdd1SGireesh Nagabhushana * track firmware initialization/error state, etc. 971956b2bdd1SGireesh Nagabhushana */ 97203dde7c95SVishal Kulkarni #define S_PCIE_FW_ERR 31 97213dde7c95SVishal Kulkarni #define M_PCIE_FW_ERR 0x1 97223dde7c95SVishal Kulkarni #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 97233dde7c95SVishal Kulkarni #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 97243dde7c95SVishal Kulkarni #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 97253dde7c95SVishal Kulkarni 97263dde7c95SVishal Kulkarni #define S_PCIE_FW_INIT 30 97273dde7c95SVishal Kulkarni #define M_PCIE_FW_INIT 0x1 97283dde7c95SVishal Kulkarni #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 97293dde7c95SVishal Kulkarni #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 97303dde7c95SVishal Kulkarni #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 97313dde7c95SVishal Kulkarni 97323dde7c95SVishal Kulkarni #define S_PCIE_FW_HALT 29 97333dde7c95SVishal Kulkarni #define M_PCIE_FW_HALT 0x1 97343dde7c95SVishal Kulkarni #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 97353dde7c95SVishal Kulkarni #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 97363dde7c95SVishal Kulkarni #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 973756b2bdd1SGireesh Nagabhushana 9738de483253SVishal Kulkarni #define S_PCIE_FW_EVAL 24 9739de483253SVishal Kulkarni #define M_PCIE_FW_EVAL 0x7 9740de483253SVishal Kulkarni #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9741de483253SVishal Kulkarni #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9742de483253SVishal Kulkarni 97433dde7c95SVishal Kulkarni #define S_PCIE_FW_STAGE 21 97443dde7c95SVishal Kulkarni #define M_PCIE_FW_STAGE 0x7 97453dde7c95SVishal Kulkarni #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 97463dde7c95SVishal Kulkarni #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 97473dde7c95SVishal Kulkarni 97483dde7c95SVishal Kulkarni #define S_PCIE_FW_ASYNCNOT_VLD 20 97493dde7c95SVishal Kulkarni #define M_PCIE_FW_ASYNCNOT_VLD 0x1 97503dde7c95SVishal Kulkarni #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 97513dde7c95SVishal Kulkarni ((x) << S_PCIE_FW_ASYNCNOT_VLD) 97523dde7c95SVishal Kulkarni #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 97533dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 97543dde7c95SVishal Kulkarni #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 97553dde7c95SVishal Kulkarni 97563dde7c95SVishal Kulkarni #define S_PCIE_FW_ASYNCNOTINT 19 97573dde7c95SVishal Kulkarni #define M_PCIE_FW_ASYNCNOTINT 0x1 97583dde7c95SVishal Kulkarni #define V_PCIE_FW_ASYNCNOTINT(x) \ 97593dde7c95SVishal Kulkarni ((x) << S_PCIE_FW_ASYNCNOTINT) 97603dde7c95SVishal Kulkarni #define G_PCIE_FW_ASYNCNOTINT(x) \ 97613dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 97623dde7c95SVishal Kulkarni #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 97633dde7c95SVishal Kulkarni 97643dde7c95SVishal Kulkarni #define S_PCIE_FW_ASYNCNOT 16 97653dde7c95SVishal Kulkarni #define M_PCIE_FW_ASYNCNOT 0x7 97663dde7c95SVishal Kulkarni #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 97673dde7c95SVishal Kulkarni #define G_PCIE_FW_ASYNCNOT(x) \ 97683dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 97693dde7c95SVishal Kulkarni 97703dde7c95SVishal Kulkarni #define S_PCIE_FW_MASTER_VLD 15 97713dde7c95SVishal Kulkarni #define M_PCIE_FW_MASTER_VLD 0x1 97723dde7c95SVishal Kulkarni #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 97733dde7c95SVishal Kulkarni #define G_PCIE_FW_MASTER_VLD(x) \ 97743dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 97753dde7c95SVishal Kulkarni #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 97763dde7c95SVishal Kulkarni 97773dde7c95SVishal Kulkarni #define S_PCIE_FW_MASTER 12 97783dde7c95SVishal Kulkarni #define M_PCIE_FW_MASTER 0x7 97793dde7c95SVishal Kulkarni #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 97803dde7c95SVishal Kulkarni #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 97813dde7c95SVishal Kulkarni 97823dde7c95SVishal Kulkarni #define S_PCIE_FW_RESET_VLD 11 97833dde7c95SVishal Kulkarni #define M_PCIE_FW_RESET_VLD 0x1 97843dde7c95SVishal Kulkarni #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 97853dde7c95SVishal Kulkarni #define G_PCIE_FW_RESET_VLD(x) \ 97863dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 97873dde7c95SVishal Kulkarni #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 97883dde7c95SVishal Kulkarni 97893dde7c95SVishal Kulkarni #define S_PCIE_FW_RESET 8 97903dde7c95SVishal Kulkarni #define M_PCIE_FW_RESET 0x7 97913dde7c95SVishal Kulkarni #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 97923dde7c95SVishal Kulkarni #define G_PCIE_FW_RESET(x) \ 97933dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 97943dde7c95SVishal Kulkarni 97953dde7c95SVishal Kulkarni #define S_PCIE_FW_REGISTERED 0 97963dde7c95SVishal Kulkarni #define M_PCIE_FW_REGISTERED 0xff 97973dde7c95SVishal Kulkarni #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 97983dde7c95SVishal Kulkarni #define G_PCIE_FW_REGISTERED(x) \ 97993dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 98003dde7c95SVishal Kulkarni 98013dde7c95SVishal Kulkarni 98023dde7c95SVishal Kulkarni /****************************************************************************** 98033dde7c95SVishal Kulkarni * P C I E F W P F 0 R E G I S T E R 98043dde7c95SVishal Kulkarni **********************************************/ 980556b2bdd1SGireesh Nagabhushana 980656b2bdd1SGireesh Nagabhushana /* 98073dde7c95SVishal Kulkarni * this register is available as 32-bit of persistent storage (accross 98083dde7c95SVishal Kulkarni * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 98093dde7c95SVishal Kulkarni * will not write it) 981056b2bdd1SGireesh Nagabhushana */ 981156b2bdd1SGireesh Nagabhushana 98123dde7c95SVishal Kulkarni 98133dde7c95SVishal Kulkarni /****************************************************************************** 98143dde7c95SVishal Kulkarni * P C I E F W P F 7 R E G I S T E R 98153dde7c95SVishal Kulkarni **********************************************/ 98163dde7c95SVishal Kulkarni 98173dde7c95SVishal Kulkarni /* 98183dde7c95SVishal Kulkarni * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 98193dde7c95SVishal Kulkarni * access the "devlog" which needing to contact firmware. The encoding is 98203dde7c95SVishal Kulkarni * mostly the same as that returned by the DEVLOG command except for the size 98213dde7c95SVishal Kulkarni * which is encoded as the number of entries in multiples-1 of 128 here rather 98223dde7c95SVishal Kulkarni * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 98233dde7c95SVishal Kulkarni * and 15 means 2048. This of course in turn constrains the allowed values 98243dde7c95SVishal Kulkarni * for the devlog size ... 98253dde7c95SVishal Kulkarni */ 98263dde7c95SVishal Kulkarni #define PCIE_FW_PF_DEVLOG 7 98273dde7c95SVishal Kulkarni 98283dde7c95SVishal Kulkarni #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 98293dde7c95SVishal Kulkarni #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 98303dde7c95SVishal Kulkarni #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 98313dde7c95SVishal Kulkarni ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 98323dde7c95SVishal Kulkarni #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 98333dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 98343dde7c95SVishal Kulkarni M_PCIE_FW_PF_DEVLOG_NENTRIES128) 98353dde7c95SVishal Kulkarni 98363dde7c95SVishal Kulkarni #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 98373dde7c95SVishal Kulkarni #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 98383dde7c95SVishal Kulkarni #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 98393dde7c95SVishal Kulkarni #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 98403dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 98413dde7c95SVishal Kulkarni 98423dde7c95SVishal Kulkarni #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 98433dde7c95SVishal Kulkarni #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 98443dde7c95SVishal Kulkarni #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 98453dde7c95SVishal Kulkarni #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 98463dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 98473dde7c95SVishal Kulkarni 98483dde7c95SVishal Kulkarni 98493dde7c95SVishal Kulkarni /****************************************************************************** 98503dde7c95SVishal Kulkarni * B I N A R Y H E A D E R F O R M A T 98513dde7c95SVishal Kulkarni **********************************************/ 98523dde7c95SVishal Kulkarni 985356b2bdd1SGireesh Nagabhushana /* 985456b2bdd1SGireesh Nagabhushana * firmware binary header format 985556b2bdd1SGireesh Nagabhushana */ 985656b2bdd1SGireesh Nagabhushana struct fw_hdr { 985756b2bdd1SGireesh Nagabhushana __u8 ver; 985856b2bdd1SGireesh Nagabhushana __u8 chip; /* terminator chip family */ 985956b2bdd1SGireesh Nagabhushana __be16 len512; /* bin length in units of 512-bytes */ 986056b2bdd1SGireesh Nagabhushana __be32 fw_ver; /* firmware version */ 986156b2bdd1SGireesh Nagabhushana __be32 tp_microcode_ver; /* tcp processor microcode version */ 986256b2bdd1SGireesh Nagabhushana __u8 intfver_nic; 986356b2bdd1SGireesh Nagabhushana __u8 intfver_vnic; 986456b2bdd1SGireesh Nagabhushana __u8 intfver_ofld; 986556b2bdd1SGireesh Nagabhushana __u8 intfver_ri; 986656b2bdd1SGireesh Nagabhushana __u8 intfver_iscsipdu; 986756b2bdd1SGireesh Nagabhushana __u8 intfver_iscsi; 9868de483253SVishal Kulkarni __u8 intfver_fcoepdu; 986956b2bdd1SGireesh Nagabhushana __u8 intfver_fcoe; 9870de483253SVishal Kulkarni __u32 reserved2; 987156b2bdd1SGireesh Nagabhushana __u32 reserved3; 98723dde7c95SVishal Kulkarni __be32 magic; /* runtime or bootstrap fw */ 987356b2bdd1SGireesh Nagabhushana __be32 flags; 987456b2bdd1SGireesh Nagabhushana __be32 reserved6[23]; 987556b2bdd1SGireesh Nagabhushana }; 987656b2bdd1SGireesh Nagabhushana 987756b2bdd1SGireesh Nagabhushana enum fw_hdr_chip { 987856b2bdd1SGireesh Nagabhushana FW_HDR_CHIP_T4, 98793dde7c95SVishal Kulkarni FW_HDR_CHIP_T5, 98803dde7c95SVishal Kulkarni FW_HDR_CHIP_T6 98813dde7c95SVishal Kulkarni }; 98823dde7c95SVishal Kulkarni 98833dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_MAJOR 24 98843dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_MAJOR 0xff 98853dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_MAJOR(x) \ 98863dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_MAJOR) 98873dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_MAJOR(x) \ 98883dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 98893dde7c95SVishal Kulkarni 98903dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_MINOR 16 98913dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_MINOR 0xff 98923dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_MINOR(x) \ 98933dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_MINOR) 98943dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_MINOR(x) \ 98953dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 98963dde7c95SVishal Kulkarni 98973dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_MICRO 8 98983dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_MICRO 0xff 98993dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_MICRO(x) \ 99003dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_MICRO) 99013dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_MICRO(x) \ 99023dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 99033dde7c95SVishal Kulkarni 99043dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_BUILD 0 99053dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_BUILD 0xff 99063dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_BUILD(x) \ 99073dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_BUILD) 99083dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_BUILD(x) \ 99093dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9910de483253SVishal Kulkarni 9911de483253SVishal Kulkarni enum { 99123dde7c95SVishal Kulkarni /* T4 99133dde7c95SVishal Kulkarni */ 99143dde7c95SVishal Kulkarni FW_HDR_INTFVER_NIC = 0x00, 99153dde7c95SVishal Kulkarni FW_HDR_INTFVER_VNIC = 0x00, 99163dde7c95SVishal Kulkarni FW_HDR_INTFVER_OFLD = 0x00, 99173dde7c95SVishal Kulkarni FW_HDR_INTFVER_RI = 0x00, 99183dde7c95SVishal Kulkarni FW_HDR_INTFVER_ISCSIPDU = 0x00, 99193dde7c95SVishal Kulkarni FW_HDR_INTFVER_ISCSI = 0x00, 99203dde7c95SVishal Kulkarni FW_HDR_INTFVER_FCOEPDU = 0x00, 99213dde7c95SVishal Kulkarni FW_HDR_INTFVER_FCOE = 0x00, 99223dde7c95SVishal Kulkarni 99233dde7c95SVishal Kulkarni /* T5 99243dde7c95SVishal Kulkarni */ 99253dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_NIC = 0x00, 99263dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_VNIC = 0x00, 99273dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_OFLD = 0x00, 99283dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_RI = 0x00, 99293dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 99303dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_ISCSI = 0x00, 99313dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_FCOEPDU= 0x00, 99323dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_FCOE = 0x00, 99333dde7c95SVishal Kulkarni 99343dde7c95SVishal Kulkarni /* T6 99353dde7c95SVishal Kulkarni */ 99363dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_NIC = 0x00, 99373dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_VNIC = 0x00, 99383dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_OFLD = 0x00, 99393dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_RI = 0x00, 99403dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 99413dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_ISCSI = 0x00, 99423dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_FCOEPDU= 0x00, 99433dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_FCOE = 0x00, 994456b2bdd1SGireesh Nagabhushana }; 994556b2bdd1SGireesh Nagabhushana 9946de483253SVishal Kulkarni enum { 9947de483253SVishal Kulkarni FW_HDR_MAGIC_RUNTIME = 0x00000000, 9948de483253SVishal Kulkarni FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9949de483253SVishal Kulkarni }; 99503dde7c95SVishal Kulkarni 995156b2bdd1SGireesh Nagabhushana enum fw_hdr_flags { 995256b2bdd1SGireesh Nagabhushana FW_HDR_FLAGS_RESET_HALT = 0x00000001, 995356b2bdd1SGireesh Nagabhushana }; 995456b2bdd1SGireesh Nagabhushana 99553dde7c95SVishal Kulkarni /* 99563dde7c95SVishal Kulkarni * External PHY firmware binary header format 99573dde7c95SVishal Kulkarni */ 99583dde7c95SVishal Kulkarni struct fw_ephy_hdr { 99593dde7c95SVishal Kulkarni __u8 ver; 99603dde7c95SVishal Kulkarni __u8 reserved; 99613dde7c95SVishal Kulkarni __be16 len512; /* bin length in units of 512-bytes */ 99623dde7c95SVishal Kulkarni __be32 magic; 99633dde7c95SVishal Kulkarni 99643dde7c95SVishal Kulkarni __be16 vendor_id; 99653dde7c95SVishal Kulkarni __be16 device_id; 99663dde7c95SVishal Kulkarni __be32 version; 99673dde7c95SVishal Kulkarni 99683dde7c95SVishal Kulkarni __be32 reserved1[4]; 99693dde7c95SVishal Kulkarni }; 99703dde7c95SVishal Kulkarni 99713dde7c95SVishal Kulkarni enum { 99723dde7c95SVishal Kulkarni FW_EPHY_HDR_MAGIC = 0x65706879, 99733dde7c95SVishal Kulkarni }; 99743dde7c95SVishal Kulkarni 9975*7e6ad469SVishal Kulkarni struct fw_ifconf_dhcp_info { 9976*7e6ad469SVishal Kulkarni __be32 addr; 9977*7e6ad469SVishal Kulkarni __be32 mask; 9978*7e6ad469SVishal Kulkarni __be16 vlanid; 9979*7e6ad469SVishal Kulkarni __be16 mtu; 9980*7e6ad469SVishal Kulkarni __be32 gw; 9981*7e6ad469SVishal Kulkarni __u8 op; 9982*7e6ad469SVishal Kulkarni __u8 len; 9983*7e6ad469SVishal Kulkarni __u8 data[270]; 9984*7e6ad469SVishal Kulkarni }; 9985*7e6ad469SVishal Kulkarni 9986*7e6ad469SVishal Kulkarni struct fw_ifconf_ping_info { 9987*7e6ad469SVishal Kulkarni __be16 ping_pldsize; 9988*7e6ad469SVishal Kulkarni }; 9989*7e6ad469SVishal Kulkarni 999056b2bdd1SGireesh Nagabhushana #endif /* _T4FW_INTERFACE_H_ */ 9991