156b2bdd1SGireesh Nagabhushana /* 256b2bdd1SGireesh Nagabhushana * Chelsio Terminator 4 (T4) Firmware interface header file. 356b2bdd1SGireesh Nagabhushana * 4*3dde7c95SVishal Kulkarni * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved. 556b2bdd1SGireesh Nagabhushana * 656b2bdd1SGireesh Nagabhushana * Written by felix marti (felix@chelsio.com) 756b2bdd1SGireesh Nagabhushana * 856b2bdd1SGireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT 956b2bdd1SGireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1056b2bdd1SGireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 1156b2bdd1SGireesh Nagabhushana * release for licensing terms and conditions. 1256b2bdd1SGireesh Nagabhushana */ 13*3dde7c95SVishal Kulkarni 1456b2bdd1SGireesh Nagabhushana #ifndef _T4FW_INTERFACE_H_ 15*3dde7c95SVishal Kulkarni #define _T4FW_INTERFACE_H_ 1656b2bdd1SGireesh Nagabhushana 17*3dde7c95SVishal Kulkarni /****************************************************************************** 18*3dde7c95SVishal Kulkarni * R E T U R N V A L U E S 19*3dde7c95SVishal Kulkarni ********************************/ 2056b2bdd1SGireesh Nagabhushana 2156b2bdd1SGireesh Nagabhushana enum fw_retval { 2256b2bdd1SGireesh Nagabhushana FW_SUCCESS = 0, /* completed sucessfully */ 2356b2bdd1SGireesh Nagabhushana FW_EPERM = 1, /* operation not permitted */ 2456b2bdd1SGireesh Nagabhushana FW_ENOENT = 2, /* no such file or directory */ 2556b2bdd1SGireesh Nagabhushana FW_EIO = 5, /* input/output error; hw bad */ 2656b2bdd1SGireesh Nagabhushana FW_ENOEXEC = 8, /* exec format error; inv microcode */ 2756b2bdd1SGireesh Nagabhushana FW_EAGAIN = 11, /* try again */ 2856b2bdd1SGireesh Nagabhushana FW_ENOMEM = 12, /* out of memory */ 2956b2bdd1SGireesh Nagabhushana FW_EFAULT = 14, /* bad address; fw bad */ 3056b2bdd1SGireesh Nagabhushana FW_EBUSY = 16, /* resource busy */ 3156b2bdd1SGireesh Nagabhushana FW_EEXIST = 17, /* file exists */ 32de483253SVishal Kulkarni FW_ENODEV = 19, /* no such device */ 3356b2bdd1SGireesh Nagabhushana FW_EINVAL = 22, /* invalid argument */ 3456b2bdd1SGireesh Nagabhushana FW_ENOSPC = 28, /* no space left on device */ 3556b2bdd1SGireesh Nagabhushana FW_ENOSYS = 38, /* functionality not implemented */ 36de483253SVishal Kulkarni FW_ENODATA = 61, /* no data available */ 3756b2bdd1SGireesh Nagabhushana FW_EPROTO = 71, /* protocol error */ 3856b2bdd1SGireesh Nagabhushana FW_EADDRINUSE = 98, /* address already in use */ 3956b2bdd1SGireesh Nagabhushana FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 4056b2bdd1SGireesh Nagabhushana FW_ENETDOWN = 100, /* network is down */ 4156b2bdd1SGireesh Nagabhushana FW_ENETUNREACH = 101, /* network is unreachable */ 4256b2bdd1SGireesh Nagabhushana FW_ENOBUFS = 105, /* no buffer space available */ 4356b2bdd1SGireesh Nagabhushana FW_ETIMEDOUT = 110, /* timeout */ 4456b2bdd1SGireesh Nagabhushana FW_EINPROGRESS = 115, /* fw internal */ 4556b2bdd1SGireesh Nagabhushana FW_SCSI_ABORT_REQUESTED = 128, /* */ 4656b2bdd1SGireesh Nagabhushana FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 4756b2bdd1SGireesh Nagabhushana FW_SCSI_ABORTED = 130, /* */ 4856b2bdd1SGireesh Nagabhushana FW_SCSI_CLOSE_REQUESTED = 131, /* */ 4956b2bdd1SGireesh Nagabhushana FW_ERR_LINK_DOWN = 132, /* */ 5056b2bdd1SGireesh Nagabhushana FW_RDEV_NOT_READY = 133, /* */ 5156b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_LOST = 134, /* */ 5256b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_LOGO = 135, /* */ 5356b2bdd1SGireesh Nagabhushana FW_FCOE_NO_XCHG = 136, /* */ 5456b2bdd1SGireesh Nagabhushana FW_SCSI_RSP_ERR = 137, /* */ 5556b2bdd1SGireesh Nagabhushana FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 5656b2bdd1SGireesh Nagabhushana FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 5756b2bdd1SGireesh Nagabhushana FW_SCSI_OVER_FLOW_ERR = 140, /* */ 58*3dde7c95SVishal Kulkarni FW_SCSI_DDP_ERR = 141, /* DDP error*/ 5956b2bdd1SGireesh Nagabhushana FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 6056b2bdd1SGireesh Nagabhushana }; 6156b2bdd1SGireesh Nagabhushana 62*3dde7c95SVishal Kulkarni /****************************************************************************** 63*3dde7c95SVishal Kulkarni * M E M O R Y T Y P E s 64*3dde7c95SVishal Kulkarni ******************************/ 65*3dde7c95SVishal Kulkarni 66*3dde7c95SVishal Kulkarni enum fw_memtype { 67*3dde7c95SVishal Kulkarni FW_MEMTYPE_EDC0 = 0x0, 68*3dde7c95SVishal Kulkarni FW_MEMTYPE_EDC1 = 0x1, 69*3dde7c95SVishal Kulkarni FW_MEMTYPE_EXTMEM = 0x2, 70*3dde7c95SVishal Kulkarni FW_MEMTYPE_FLASH = 0x4, 71*3dde7c95SVishal Kulkarni FW_MEMTYPE_INTERNAL = 0x5, 72*3dde7c95SVishal Kulkarni FW_MEMTYPE_EXTMEM1 = 0x6, 73*3dde7c95SVishal Kulkarni }; 74*3dde7c95SVishal Kulkarni 75*3dde7c95SVishal Kulkarni /****************************************************************************** 76*3dde7c95SVishal Kulkarni * W O R K R E Q U E S T s 77*3dde7c95SVishal Kulkarni ********************************/ 7856b2bdd1SGireesh Nagabhushana 7956b2bdd1SGireesh Nagabhushana enum fw_wr_opcodes { 80de483253SVishal Kulkarni FW_FRAG_WR = 0x1d, 8156b2bdd1SGireesh Nagabhushana FW_FILTER_WR = 0x02, 8256b2bdd1SGireesh Nagabhushana FW_ULPTX_WR = 0x04, 8356b2bdd1SGireesh Nagabhushana FW_TP_WR = 0x05, 8456b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKT_WR = 0x08, 85de483253SVishal Kulkarni FW_ETH_TX_PKT2_WR = 0x44, 8656b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKTS_WR = 0x09, 87*3dde7c95SVishal Kulkarni FW_ETH_TX_PKTS2_WR = 0x78, 88*3dde7c95SVishal Kulkarni FW_ETH_TX_EO_WR = 0x1c, 8956b2bdd1SGireesh Nagabhushana FW_EQ_FLUSH_WR = 0x1b, 9056b2bdd1SGireesh Nagabhushana FW_OFLD_CONNECTION_WR = 0x2f, 9156b2bdd1SGireesh Nagabhushana FW_FLOWC_WR = 0x0a, 9256b2bdd1SGireesh Nagabhushana FW_OFLD_TX_DATA_WR = 0x0b, 9356b2bdd1SGireesh Nagabhushana FW_CMD_WR = 0x10, 9456b2bdd1SGireesh Nagabhushana FW_ETH_TX_PKT_VM_WR = 0x11, 9556b2bdd1SGireesh Nagabhushana FW_RI_RES_WR = 0x0c, 9656b2bdd1SGireesh Nagabhushana FW_RI_RDMA_WRITE_WR = 0x14, 9756b2bdd1SGireesh Nagabhushana FW_RI_SEND_WR = 0x15, 9856b2bdd1SGireesh Nagabhushana FW_RI_RDMA_READ_WR = 0x16, 9956b2bdd1SGireesh Nagabhushana FW_RI_RECV_WR = 0x17, 10056b2bdd1SGireesh Nagabhushana FW_RI_BIND_MW_WR = 0x18, 10156b2bdd1SGireesh Nagabhushana FW_RI_FR_NSMR_WR = 0x19, 102*3dde7c95SVishal Kulkarni FW_RI_FR_NSMR_TPTE_WR = 0x20, 10356b2bdd1SGireesh Nagabhushana FW_RI_INV_LSTAG_WR = 0x1a, 10456b2bdd1SGireesh Nagabhushana FW_RI_SEND_IMMEDIATE_WR = 0x15, 10556b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_WR = 0x16, 10656b2bdd1SGireesh Nagabhushana FW_RI_WR = 0x0d, 10756b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR = 0x6b, 10856b2bdd1SGireesh Nagabhushana FW_RDEV_WR = 0x38, 10956b2bdd1SGireesh Nagabhushana FW_FOISCSI_NODE_WR = 0x60, 11056b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_WR = 0x6a, 11156b2bdd1SGireesh Nagabhushana FW_FOISCSI_CHAP_WR = 0x6c, 11256b2bdd1SGireesh Nagabhushana FW_FCOE_ELS_CT_WR = 0x30, 11356b2bdd1SGireesh Nagabhushana FW_SCSI_WRITE_WR = 0x31, 11456b2bdd1SGireesh Nagabhushana FW_SCSI_READ_WR = 0x32, 11556b2bdd1SGireesh Nagabhushana FW_SCSI_CMD_WR = 0x33, 11656b2bdd1SGireesh Nagabhushana FW_SCSI_ABRT_CLS_WR = 0x34, 11756b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_ACC_WR = 0x35, 11856b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_XMIT_WR = 0x36, 11956b2bdd1SGireesh Nagabhushana FW_SCSI_TGT_RSP_WR = 0x37, 120de483253SVishal Kulkarni FW_POFCOE_TCB_WR = 0x42, 121de483253SVishal Kulkarni FW_POFCOE_ULPTX_WR = 0x43, 122*3dde7c95SVishal Kulkarni FW_ISCSI_TX_DATA_WR = 0x45, 123*3dde7c95SVishal Kulkarni FW_PTP_TX_PKT_WR = 0x46, 124*3dde7c95SVishal Kulkarni FW_TLSTX_DATA_WR = 0x68, 125*3dde7c95SVishal Kulkarni FW_TLS_KEYCTX_TX_WR = 0x69, 126*3dde7c95SVishal Kulkarni FW_CRYPTO_LOOKASIDE_WR = 0x6d, 127*3dde7c95SVishal Kulkarni FW_COiSCSI_TGT_WR = 0x70, 128*3dde7c95SVishal Kulkarni FW_COiSCSI_TGT_CONN_WR = 0x71, 129*3dde7c95SVishal Kulkarni FW_COiSCSI_TGT_XMIT_WR = 0x72, 130*3dde7c95SVishal Kulkarni FW_ISNS_WR = 0x75, 131*3dde7c95SVishal Kulkarni FW_ISNS_XMIT_WR = 0x76, 132*3dde7c95SVishal Kulkarni FW_FILTER2_WR = 0x77, 133*3dde7c95SVishal Kulkarni FW_LASTC2E_WR = 0x80 13456b2bdd1SGireesh Nagabhushana }; 13556b2bdd1SGireesh Nagabhushana 13656b2bdd1SGireesh Nagabhushana /* 13756b2bdd1SGireesh Nagabhushana * Generic work request header flit0 13856b2bdd1SGireesh Nagabhushana */ 13956b2bdd1SGireesh Nagabhushana struct fw_wr_hdr { 14056b2bdd1SGireesh Nagabhushana __be32 hi; 14156b2bdd1SGireesh Nagabhushana __be32 lo; 14256b2bdd1SGireesh Nagabhushana }; 14356b2bdd1SGireesh Nagabhushana 144*3dde7c95SVishal Kulkarni /* work request opcode (hi) 145*3dde7c95SVishal Kulkarni */ 146*3dde7c95SVishal Kulkarni #define S_FW_WR_OP 24 147*3dde7c95SVishal Kulkarni #define M_FW_WR_OP 0xff 148*3dde7c95SVishal Kulkarni #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 149*3dde7c95SVishal Kulkarni #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 150*3dde7c95SVishal Kulkarni 151*3dde7c95SVishal Kulkarni /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 152*3dde7c95SVishal Kulkarni */ 153*3dde7c95SVishal Kulkarni #define S_FW_WR_ATOMIC 23 154*3dde7c95SVishal Kulkarni #define M_FW_WR_ATOMIC 0x1 155*3dde7c95SVishal Kulkarni #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 156*3dde7c95SVishal Kulkarni #define G_FW_WR_ATOMIC(x) \ 157*3dde7c95SVishal Kulkarni (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 158*3dde7c95SVishal Kulkarni #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 159*3dde7c95SVishal Kulkarni 160*3dde7c95SVishal Kulkarni /* flush flag (hi) - firmware flushes flushable work request buffered 161*3dde7c95SVishal Kulkarni * in the flow context. 162*3dde7c95SVishal Kulkarni */ 163*3dde7c95SVishal Kulkarni #define S_FW_WR_FLUSH 22 164*3dde7c95SVishal Kulkarni #define M_FW_WR_FLUSH 0x1 165*3dde7c95SVishal Kulkarni #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 166*3dde7c95SVishal Kulkarni #define G_FW_WR_FLUSH(x) \ 167*3dde7c95SVishal Kulkarni (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 168*3dde7c95SVishal Kulkarni #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 169*3dde7c95SVishal Kulkarni 170*3dde7c95SVishal Kulkarni /* completion flag (hi) - firmware generates a cpl_fw6_ack 171*3dde7c95SVishal Kulkarni */ 172*3dde7c95SVishal Kulkarni #define S_FW_WR_COMPL 21 173*3dde7c95SVishal Kulkarni #define M_FW_WR_COMPL 0x1 174*3dde7c95SVishal Kulkarni #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 175*3dde7c95SVishal Kulkarni #define G_FW_WR_COMPL(x) \ 176*3dde7c95SVishal Kulkarni (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 177*3dde7c95SVishal Kulkarni #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 178*3dde7c95SVishal Kulkarni 17956b2bdd1SGireesh Nagabhushana 180*3dde7c95SVishal Kulkarni /* work request immediate data lengh (hi) 181*3dde7c95SVishal Kulkarni */ 182*3dde7c95SVishal Kulkarni #define S_FW_WR_IMMDLEN 0 183*3dde7c95SVishal Kulkarni #define M_FW_WR_IMMDLEN 0xff 184*3dde7c95SVishal Kulkarni #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 185*3dde7c95SVishal Kulkarni #define G_FW_WR_IMMDLEN(x) \ 186*3dde7c95SVishal Kulkarni (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 18756b2bdd1SGireesh Nagabhushana 188*3dde7c95SVishal Kulkarni /* egress queue status update to associated ingress queue entry (lo) 18956b2bdd1SGireesh Nagabhushana */ 190*3dde7c95SVishal Kulkarni #define S_FW_WR_EQUIQ 31 191*3dde7c95SVishal Kulkarni #define M_FW_WR_EQUIQ 0x1 192*3dde7c95SVishal Kulkarni #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 193*3dde7c95SVishal Kulkarni #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 194*3dde7c95SVishal Kulkarni #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 195*3dde7c95SVishal Kulkarni 196*3dde7c95SVishal Kulkarni /* egress queue status update to egress queue status entry (lo) 197*3dde7c95SVishal Kulkarni */ 198*3dde7c95SVishal Kulkarni #define S_FW_WR_EQUEQ 30 199*3dde7c95SVishal Kulkarni #define M_FW_WR_EQUEQ 0x1 200*3dde7c95SVishal Kulkarni #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 201*3dde7c95SVishal Kulkarni #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 202*3dde7c95SVishal Kulkarni #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 203*3dde7c95SVishal Kulkarni 204*3dde7c95SVishal Kulkarni /* flow context identifier (lo) 205*3dde7c95SVishal Kulkarni */ 206*3dde7c95SVishal Kulkarni #define S_FW_WR_FLOWID 8 207*3dde7c95SVishal Kulkarni #define M_FW_WR_FLOWID 0xfffff 208*3dde7c95SVishal Kulkarni #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 209*3dde7c95SVishal Kulkarni #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 210*3dde7c95SVishal Kulkarni 211*3dde7c95SVishal Kulkarni /* length in units of 16-bytes (lo) 212*3dde7c95SVishal Kulkarni */ 213*3dde7c95SVishal Kulkarni #define S_FW_WR_LEN16 0 214*3dde7c95SVishal Kulkarni #define M_FW_WR_LEN16 0xff 215*3dde7c95SVishal Kulkarni #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 216*3dde7c95SVishal Kulkarni #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 21756b2bdd1SGireesh Nagabhushana 218de483253SVishal Kulkarni struct fw_frag_wr { 219de483253SVishal Kulkarni __be32 op_to_fragoff16; 220de483253SVishal Kulkarni __be32 flowid_len16; 221de483253SVishal Kulkarni __be64 r4; 222de483253SVishal Kulkarni }; 223de483253SVishal Kulkarni 224de483253SVishal Kulkarni #define S_FW_FRAG_WR_EOF 15 225de483253SVishal Kulkarni #define M_FW_FRAG_WR_EOF 0x1 226de483253SVishal Kulkarni #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 227de483253SVishal Kulkarni #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 228de483253SVishal Kulkarni #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 229de483253SVishal Kulkarni 230de483253SVishal Kulkarni #define S_FW_FRAG_WR_FRAGOFF16 8 231de483253SVishal Kulkarni #define M_FW_FRAG_WR_FRAGOFF16 0x7f 232de483253SVishal Kulkarni #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 233de483253SVishal Kulkarni #define G_FW_FRAG_WR_FRAGOFF16(x) \ 234de483253SVishal Kulkarni (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 235de483253SVishal Kulkarni 236*3dde7c95SVishal Kulkarni /* valid filter configurations for compressed tuple 23756b2bdd1SGireesh Nagabhushana * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 23856b2bdd1SGireesh Nagabhushana * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 23956b2bdd1SGireesh Nagabhushana * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 24056b2bdd1SGireesh Nagabhushana * OV - Outer VLAN/VNIC_ID, 241*3dde7c95SVishal Kulkarni */ 242*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 243*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 244*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 245*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_M_OV_P_FC 0x387 246*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_PR_T 0x370 247*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_PR_P_FC 0X363 248*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_E_T_P_FC 0X353 249*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 250*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 251*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 252*3dde7c95SVishal Kulkarni #define HW_TPL_FR_MT_T_OV_P_FC 0X317 253*3dde7c95SVishal Kulkarni #define HW_TPL_FR_M_E_PR_FC 0X2E1 254*3dde7c95SVishal Kulkarni #define HW_TPL_FR_M_E_T_FC 0X2D1 255*3dde7c95SVishal Kulkarni #define HW_TPL_FR_M_PR_IV_FC 0X2A9 256*3dde7c95SVishal Kulkarni #define HW_TPL_FR_M_PR_OV_FC 0X2A5 257*3dde7c95SVishal Kulkarni #define HW_TPL_FR_M_T_IV_FC 0X299 258*3dde7c95SVishal Kulkarni #define HW_TPL_FR_M_T_OV_FC 0X295 259*3dde7c95SVishal Kulkarni #define HW_TPL_FR_E_PR_T_P 0X272 260*3dde7c95SVishal Kulkarni #define HW_TPL_FR_E_PR_T_FC 0X271 261*3dde7c95SVishal Kulkarni #define HW_TPL_FR_E_IV_FC 0X249 262*3dde7c95SVishal Kulkarni #define HW_TPL_FR_E_OV_FC 0X245 263*3dde7c95SVishal Kulkarni #define HW_TPL_FR_PR_T_IV_FC 0X239 264*3dde7c95SVishal Kulkarni #define HW_TPL_FR_PR_T_OV_FC 0X235 265*3dde7c95SVishal Kulkarni #define HW_TPL_FR_IV_OV_FC 0X20D 266*3dde7c95SVishal Kulkarni #define HW_TPL_MT_M_E_PR 0X1E0 267*3dde7c95SVishal Kulkarni #define HW_TPL_MT_M_E_T 0X1D0 268*3dde7c95SVishal Kulkarni #define HW_TPL_MT_E_PR_T_FC 0X171 269*3dde7c95SVishal Kulkarni #define HW_TPL_MT_E_IV 0X148 270*3dde7c95SVishal Kulkarni #define HW_TPL_MT_E_OV 0X144 271*3dde7c95SVishal Kulkarni #define HW_TPL_MT_PR_T_IV 0X138 272*3dde7c95SVishal Kulkarni #define HW_TPL_MT_PR_T_OV 0X134 273*3dde7c95SVishal Kulkarni #define HW_TPL_M_E_PR_P 0X0E2 274*3dde7c95SVishal Kulkarni #define HW_TPL_M_E_T_P 0X0D2 275*3dde7c95SVishal Kulkarni #define HW_TPL_E_PR_T_P_FC 0X073 276*3dde7c95SVishal Kulkarni #define HW_TPL_E_IV_P 0X04A 277*3dde7c95SVishal Kulkarni #define HW_TPL_E_OV_P 0X046 278*3dde7c95SVishal Kulkarni #define HW_TPL_PR_T_IV_P 0X03A 279*3dde7c95SVishal Kulkarni #define HW_TPL_PR_T_OV_P 0X036 28056b2bdd1SGireesh Nagabhushana 28156b2bdd1SGireesh Nagabhushana /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 28256b2bdd1SGireesh Nagabhushana enum fw_filter_wr_cookie { 28356b2bdd1SGireesh Nagabhushana FW_FILTER_WR_SUCCESS, 28456b2bdd1SGireesh Nagabhushana FW_FILTER_WR_FLT_ADDED, 28556b2bdd1SGireesh Nagabhushana FW_FILTER_WR_FLT_DELETED, 28656b2bdd1SGireesh Nagabhushana FW_FILTER_WR_SMT_TBL_FULL, 28756b2bdd1SGireesh Nagabhushana FW_FILTER_WR_EINVAL, 28856b2bdd1SGireesh Nagabhushana }; 28956b2bdd1SGireesh Nagabhushana 290*3dde7c95SVishal Kulkarni enum fw_filter_wr_nat_mode { 291*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_NONE = 0, 292*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIP , 293*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPDP, 294*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPDPSIP, 295*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPDPSP, 296*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_SIPSP, 297*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_DIPSIPSP, 298*3dde7c95SVishal Kulkarni FW_FILTER_WR_NATMODE_FOURTUPLE, 299*3dde7c95SVishal Kulkarni }; 300*3dde7c95SVishal Kulkarni 30156b2bdd1SGireesh Nagabhushana struct fw_filter_wr { 30256b2bdd1SGireesh Nagabhushana __be32 op_pkd; 30356b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 30456b2bdd1SGireesh Nagabhushana __be64 r3; 30556b2bdd1SGireesh Nagabhushana __be32 tid_to_iq; 30656b2bdd1SGireesh Nagabhushana __be32 del_filter_to_l2tix; 30756b2bdd1SGireesh Nagabhushana __be16 ethtype; 30856b2bdd1SGireesh Nagabhushana __be16 ethtypem; 30956b2bdd1SGireesh Nagabhushana __u8 frag_to_ovlan_vldm; 31056b2bdd1SGireesh Nagabhushana __u8 smac_sel; 31156b2bdd1SGireesh Nagabhushana __be16 rx_chan_rx_rpl_iq; 31256b2bdd1SGireesh Nagabhushana __be32 maci_to_matchtypem; 31356b2bdd1SGireesh Nagabhushana __u8 ptcl; 31456b2bdd1SGireesh Nagabhushana __u8 ptclm; 31556b2bdd1SGireesh Nagabhushana __u8 ttyp; 31656b2bdd1SGireesh Nagabhushana __u8 ttypm; 31756b2bdd1SGireesh Nagabhushana __be16 ivlan; 31856b2bdd1SGireesh Nagabhushana __be16 ivlanm; 31956b2bdd1SGireesh Nagabhushana __be16 ovlan; 32056b2bdd1SGireesh Nagabhushana __be16 ovlanm; 32156b2bdd1SGireesh Nagabhushana __u8 lip[16]; 32256b2bdd1SGireesh Nagabhushana __u8 lipm[16]; 32356b2bdd1SGireesh Nagabhushana __u8 fip[16]; 32456b2bdd1SGireesh Nagabhushana __u8 fipm[16]; 32556b2bdd1SGireesh Nagabhushana __be16 lp; 32656b2bdd1SGireesh Nagabhushana __be16 lpm; 32756b2bdd1SGireesh Nagabhushana __be16 fp; 32856b2bdd1SGireesh Nagabhushana __be16 fpm; 32956b2bdd1SGireesh Nagabhushana __be16 r7; 33056b2bdd1SGireesh Nagabhushana __u8 sma[6]; 33156b2bdd1SGireesh Nagabhushana }; 33256b2bdd1SGireesh Nagabhushana 333*3dde7c95SVishal Kulkarni struct fw_filter2_wr { 334*3dde7c95SVishal Kulkarni __be32 op_pkd; 335*3dde7c95SVishal Kulkarni __be32 len16_pkd; 336*3dde7c95SVishal Kulkarni __be64 r3; 337*3dde7c95SVishal Kulkarni __be32 tid_to_iq; 338*3dde7c95SVishal Kulkarni __be32 del_filter_to_l2tix; 339*3dde7c95SVishal Kulkarni __be16 ethtype; 340*3dde7c95SVishal Kulkarni __be16 ethtypem; 341*3dde7c95SVishal Kulkarni __u8 frag_to_ovlan_vldm; 342*3dde7c95SVishal Kulkarni __u8 smac_sel; 343*3dde7c95SVishal Kulkarni __be16 rx_chan_rx_rpl_iq; 344*3dde7c95SVishal Kulkarni __be32 maci_to_matchtypem; 345*3dde7c95SVishal Kulkarni __u8 ptcl; 346*3dde7c95SVishal Kulkarni __u8 ptclm; 347*3dde7c95SVishal Kulkarni __u8 ttyp; 348*3dde7c95SVishal Kulkarni __u8 ttypm; 349*3dde7c95SVishal Kulkarni __be16 ivlan; 350*3dde7c95SVishal Kulkarni __be16 ivlanm; 351*3dde7c95SVishal Kulkarni __be16 ovlan; 352*3dde7c95SVishal Kulkarni __be16 ovlanm; 353*3dde7c95SVishal Kulkarni __u8 lip[16]; 354*3dde7c95SVishal Kulkarni __u8 lipm[16]; 355*3dde7c95SVishal Kulkarni __u8 fip[16]; 356*3dde7c95SVishal Kulkarni __u8 fipm[16]; 357*3dde7c95SVishal Kulkarni __be16 lp; 358*3dde7c95SVishal Kulkarni __be16 lpm; 359*3dde7c95SVishal Kulkarni __be16 fp; 360*3dde7c95SVishal Kulkarni __be16 fpm; 361*3dde7c95SVishal Kulkarni __be16 r7; 362*3dde7c95SVishal Kulkarni __u8 sma[6]; 363*3dde7c95SVishal Kulkarni __u8 r8_hi[2]; 364*3dde7c95SVishal Kulkarni __u8 filter_type_swapmac; 365*3dde7c95SVishal Kulkarni __u8 natmode_to_ulp_type; 366*3dde7c95SVishal Kulkarni __be16 newlport; 367*3dde7c95SVishal Kulkarni __be16 newfport; 368*3dde7c95SVishal Kulkarni __u8 newlip[16]; 369*3dde7c95SVishal Kulkarni __u8 newfip[16]; 370*3dde7c95SVishal Kulkarni __be32 natseqcheck; 371*3dde7c95SVishal Kulkarni __be32 dip_hit_vni; 372*3dde7c95SVishal Kulkarni __be64 r10; 373*3dde7c95SVishal Kulkarni __be64 r11; 374*3dde7c95SVishal Kulkarni __be64 r12; 375*3dde7c95SVishal Kulkarni __be64 r13; 376*3dde7c95SVishal Kulkarni }; 377*3dde7c95SVishal Kulkarni 378*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_TID 12 379*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_TID 0xfffff 380*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 381*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_TID(x) \ 382*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 383*3dde7c95SVishal Kulkarni 384*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RQTYPE 11 385*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RQTYPE 0x1 386*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 387*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RQTYPE(x) \ 388*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 389*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 390*3dde7c95SVishal Kulkarni 391*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_NOREPLY 10 392*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_NOREPLY 0x1 393*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 394*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_NOREPLY(x) \ 395*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 396*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 397*3dde7c95SVishal Kulkarni 398*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IQ 0 399*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IQ 0x3ff 400*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 401*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IQ(x) \ 402*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 403*3dde7c95SVishal Kulkarni 404*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DEL_FILTER 31 405*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DEL_FILTER 0x1 406*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 407*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DEL_FILTER(x) \ 408*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 409*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 410*3dde7c95SVishal Kulkarni 411*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RPTTID 25 412*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RPTTID 0x1 413*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 414*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RPTTID(x) \ 415*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 416*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 417*3dde7c95SVishal Kulkarni 418*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DROP 24 419*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DROP 0x1 420*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 421*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DROP(x) \ 422*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 423*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 424*3dde7c95SVishal Kulkarni 425*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DIRSTEER 23 426*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DIRSTEER 0x1 427*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 428*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DIRSTEER(x) \ 429*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 430*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 431*3dde7c95SVishal Kulkarni 432*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MASKHASH 22 433*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MASKHASH 0x1 434*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 435*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MASKHASH(x) \ 436*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 437*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 438*3dde7c95SVishal Kulkarni 439*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DIRSTEERHASH 21 440*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 441*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 442*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 443*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 444*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 445*3dde7c95SVishal Kulkarni 446*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_LPBK 20 447*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_LPBK 0x1 448*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 449*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_LPBK(x) \ 450*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 451*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 452*3dde7c95SVishal Kulkarni 453*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_DMAC 19 454*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_DMAC 0x1 455*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 456*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_DMAC(x) \ 457*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 458*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 459*3dde7c95SVishal Kulkarni 460*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_SMAC 18 461*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_SMAC 0x1 462*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 463*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_SMAC(x) \ 464*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 465*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 466*3dde7c95SVishal Kulkarni 467*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_INSVLAN 17 468*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_INSVLAN 0x1 469*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 470*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_INSVLAN(x) \ 471*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 472*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 473*3dde7c95SVishal Kulkarni 474*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RMVLAN 16 475*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RMVLAN 0x1 476*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 477*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RMVLAN(x) \ 478*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 479*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 480*3dde7c95SVishal Kulkarni 481*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_HITCNTS 15 482*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_HITCNTS 0x1 483*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 484*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_HITCNTS(x) \ 485*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 486*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 487*3dde7c95SVishal Kulkarni 488*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_TXCHAN 13 489*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_TXCHAN 0x3 490*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 491*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_TXCHAN(x) \ 492*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 493*3dde7c95SVishal Kulkarni 494*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PRIO 12 495*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PRIO 0x1 496*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 497*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PRIO(x) \ 498*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 499*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 500*3dde7c95SVishal Kulkarni 501*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_L2TIX 0 502*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_L2TIX 0xfff 503*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 504*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_L2TIX(x) \ 505*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 506*3dde7c95SVishal Kulkarni 507*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FRAG 7 508*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FRAG 0x1 509*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 510*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FRAG(x) \ 511*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 512*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 513*3dde7c95SVishal Kulkarni 514*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FRAGM 6 515*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FRAGM 0x1 516*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 517*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FRAGM(x) \ 518*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 519*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 520*3dde7c95SVishal Kulkarni 521*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IVLAN_VLD 5 522*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IVLAN_VLD 0x1 523*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 524*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 525*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 526*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 527*3dde7c95SVishal Kulkarni 528*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_OVLAN_VLD 4 529*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_OVLAN_VLD 0x1 530*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 531*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 532*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 533*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 534*3dde7c95SVishal Kulkarni 535*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_IVLAN_VLDM 3 536*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 537*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 538*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 539*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 540*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 541*3dde7c95SVishal Kulkarni 542*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_OVLAN_VLDM 2 543*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 544*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 545*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 546*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 547*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 548*3dde7c95SVishal Kulkarni 549*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RX_CHAN 15 550*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RX_CHAN 0x1 551*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 552*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RX_CHAN(x) \ 553*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 554*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 555*3dde7c95SVishal Kulkarni 556*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_RX_RPL_IQ 0 557*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 558*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 559*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 560*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 561*3dde7c95SVishal Kulkarni 562*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_FILTER_TYPE 1 563*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 564*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 565*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 566*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 567*3dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 568*3dde7c95SVishal Kulkarni 569*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_SWAPMAC 0 570*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_SWAPMAC 0x1 571*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 572*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_SWAPMAC(x) \ 573*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 574*3dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 575*3dde7c95SVishal Kulkarni 576*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_NATMODE 5 577*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_NATMODE 0x7 578*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 579*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_NATMODE(x) \ 580*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 581*3dde7c95SVishal Kulkarni 582*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_NATFLAGCHECK 4 583*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 584*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 585*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 586*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 587*3dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 588*3dde7c95SVishal Kulkarni 589*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_ULP_TYPE 0 590*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_ULP_TYPE 0xf 591*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 592*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 593*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 594*3dde7c95SVishal Kulkarni 595*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_DIP_HIT 24 596*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_DIP_HIT 0x1 597*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_DIP_HIT(x) ((x) << S_FW_FILTER2_WR_DIP_HIT) 598*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_DIP_HIT(x) \ 599*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_DIP_HIT) & M_FW_FILTER2_WR_DIP_HIT) 600*3dde7c95SVishal Kulkarni #define F_FW_FILTER2_WR_DIP_HIT V_FW_FILTER2_WR_DIP_HIT(1U) 601*3dde7c95SVishal Kulkarni 602*3dde7c95SVishal Kulkarni #define S_FW_FILTER2_WR_VNI 0 603*3dde7c95SVishal Kulkarni #define M_FW_FILTER2_WR_VNI 0xffffff 604*3dde7c95SVishal Kulkarni #define V_FW_FILTER2_WR_VNI(x) ((x) << S_FW_FILTER2_WR_VNI) 605*3dde7c95SVishal Kulkarni #define G_FW_FILTER2_WR_VNI(x) \ 606*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER2_WR_VNI) & M_FW_FILTER2_WR_VNI) 607*3dde7c95SVishal Kulkarni 608*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MACI 23 609*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MACI 0x1ff 610*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 611*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MACI(x) \ 612*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 613*3dde7c95SVishal Kulkarni 614*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MACIM 14 615*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MACIM 0x1ff 616*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 617*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MACIM(x) \ 618*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 619*3dde7c95SVishal Kulkarni 620*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FCOE 13 621*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FCOE 0x1 622*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 623*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FCOE(x) \ 624*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 625*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 626*3dde7c95SVishal Kulkarni 627*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_FCOEM 12 628*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_FCOEM 0x1 629*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 630*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_FCOEM(x) \ 631*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 632*3dde7c95SVishal Kulkarni #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 633*3dde7c95SVishal Kulkarni 634*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PORT 9 635*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PORT 0x7 636*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 637*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PORT(x) \ 638*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 639*3dde7c95SVishal Kulkarni 640*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_PORTM 6 641*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_PORTM 0x7 642*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 643*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_PORTM(x) \ 644*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 645*3dde7c95SVishal Kulkarni 646*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MATCHTYPE 3 647*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MATCHTYPE 0x7 648*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 649*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MATCHTYPE(x) \ 650*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 651*3dde7c95SVishal Kulkarni 652*3dde7c95SVishal Kulkarni #define S_FW_FILTER_WR_MATCHTYPEM 0 653*3dde7c95SVishal Kulkarni #define M_FW_FILTER_WR_MATCHTYPEM 0x7 654*3dde7c95SVishal Kulkarni #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 655*3dde7c95SVishal Kulkarni #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 656*3dde7c95SVishal Kulkarni (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 65756b2bdd1SGireesh Nagabhushana 65856b2bdd1SGireesh Nagabhushana struct fw_ulptx_wr { 65956b2bdd1SGireesh Nagabhushana __be32 op_to_compl; 66056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 66156b2bdd1SGireesh Nagabhushana __u64 cookie; 66256b2bdd1SGireesh Nagabhushana }; 66356b2bdd1SGireesh Nagabhushana 66456b2bdd1SGireesh Nagabhushana struct fw_tp_wr { 66556b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 66656b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 66756b2bdd1SGireesh Nagabhushana __u64 cookie; 66856b2bdd1SGireesh Nagabhushana }; 66956b2bdd1SGireesh Nagabhushana 67056b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_wr { 67156b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 67256b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 67356b2bdd1SGireesh Nagabhushana __be64 r3; 67456b2bdd1SGireesh Nagabhushana }; 67556b2bdd1SGireesh Nagabhushana 676*3dde7c95SVishal Kulkarni #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 677*3dde7c95SVishal Kulkarni #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 678*3dde7c95SVishal Kulkarni #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 679*3dde7c95SVishal Kulkarni #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 680*3dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 68156b2bdd1SGireesh Nagabhushana 682de483253SVishal Kulkarni struct fw_eth_tx_pkt2_wr { 683de483253SVishal Kulkarni __be32 op_immdlen; 684de483253SVishal Kulkarni __be32 equiq_to_len16; 685de483253SVishal Kulkarni __be32 r3; 686de483253SVishal Kulkarni __be32 L4ChkDisable_to_IpHdrLen; 687de483253SVishal Kulkarni }; 688de483253SVishal Kulkarni 689de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 690de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 691de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 692de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 693de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 694de483253SVishal Kulkarni 695de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 696de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 697de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 698de483253SVishal Kulkarni ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 699de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 700de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 701de483253SVishal Kulkarni M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 702de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 703de483253SVishal Kulkarni V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 704de483253SVishal Kulkarni 705de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 706de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 707de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 708de483253SVishal Kulkarni ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 709de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 710de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 711de483253SVishal Kulkarni M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 712de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 713de483253SVishal Kulkarni V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 714de483253SVishal Kulkarni 715de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 716de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 717de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 718de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 719de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 720de483253SVishal Kulkarni #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 721de483253SVishal Kulkarni 722de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 723de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 724de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 725de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 726de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 727de483253SVishal Kulkarni 728de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 729de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 730de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 731de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 732de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 733de483253SVishal Kulkarni 734de483253SVishal Kulkarni #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 735de483253SVishal Kulkarni #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 736de483253SVishal Kulkarni #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 737de483253SVishal Kulkarni #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 738de483253SVishal Kulkarni (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 739de483253SVishal Kulkarni 74056b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkts_wr { 74156b2bdd1SGireesh Nagabhushana __be32 op_pkd; 74256b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 74356b2bdd1SGireesh Nagabhushana __be32 r3; 74456b2bdd1SGireesh Nagabhushana __be16 plen; 74556b2bdd1SGireesh Nagabhushana __u8 npkt; 74656b2bdd1SGireesh Nagabhushana __u8 type; 74756b2bdd1SGireesh Nagabhushana }; 74856b2bdd1SGireesh Nagabhushana 749*3dde7c95SVishal Kulkarni #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 750*3dde7c95SVishal Kulkarni #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 751*3dde7c95SVishal Kulkarni #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 752*3dde7c95SVishal Kulkarni #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 753*3dde7c95SVishal Kulkarni (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 754*3dde7c95SVishal Kulkarni 755*3dde7c95SVishal Kulkarni struct fw_eth_tx_pkt_ptp_wr { 75656b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 75756b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 75856b2bdd1SGireesh Nagabhushana __be64 r3; 75956b2bdd1SGireesh Nagabhushana }; 76056b2bdd1SGireesh Nagabhushana 761*3dde7c95SVishal Kulkarni enum fw_eth_tx_eo_type { 762*3dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_UDPSEG, 763*3dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_TCPSEG, 764*3dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_NVGRESEG, 765*3dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_VXLANSEG, 766*3dde7c95SVishal Kulkarni FW_ETH_TX_EO_TYPE_GENEVESEG, 767*3dde7c95SVishal Kulkarni }; 768*3dde7c95SVishal Kulkarni 769*3dde7c95SVishal Kulkarni struct fw_eth_tx_eo_wr { 770*3dde7c95SVishal Kulkarni __be32 op_immdlen; 771*3dde7c95SVishal Kulkarni __be32 equiq_to_len16; 772*3dde7c95SVishal Kulkarni __be64 r3; 773*3dde7c95SVishal Kulkarni union fw_eth_tx_eo { 774*3dde7c95SVishal Kulkarni struct fw_eth_tx_eo_udpseg { 775*3dde7c95SVishal Kulkarni __u8 type; 776*3dde7c95SVishal Kulkarni __u8 ethlen; 777*3dde7c95SVishal Kulkarni __be16 iplen; 778*3dde7c95SVishal Kulkarni __u8 udplen; 779*3dde7c95SVishal Kulkarni __u8 rtplen; 780*3dde7c95SVishal Kulkarni __be16 r4; 781*3dde7c95SVishal Kulkarni __be16 mss; 782*3dde7c95SVishal Kulkarni __be16 schedpktsize; 783*3dde7c95SVishal Kulkarni __be32 plen; 784*3dde7c95SVishal Kulkarni } udpseg; 785*3dde7c95SVishal Kulkarni struct fw_eth_tx_eo_tcpseg { 786*3dde7c95SVishal Kulkarni __u8 type; 787*3dde7c95SVishal Kulkarni __u8 ethlen; 788*3dde7c95SVishal Kulkarni __be16 iplen; 789*3dde7c95SVishal Kulkarni __u8 tcplen; 790*3dde7c95SVishal Kulkarni __u8 tsclk_tsoff; 791*3dde7c95SVishal Kulkarni __be16 r4; 792*3dde7c95SVishal Kulkarni __be16 mss; 793*3dde7c95SVishal Kulkarni __be16 r5; 794*3dde7c95SVishal Kulkarni __be32 plen; 795*3dde7c95SVishal Kulkarni } tcpseg; 796*3dde7c95SVishal Kulkarni struct fw_eth_tx_eo_nvgreseg { 797*3dde7c95SVishal Kulkarni __u8 type; 798*3dde7c95SVishal Kulkarni __u8 iphdroffout; 799*3dde7c95SVishal Kulkarni __be16 grehdroff; 800*3dde7c95SVishal Kulkarni __be16 iphdroffin; 801*3dde7c95SVishal Kulkarni __be16 tcphdroffin; 802*3dde7c95SVishal Kulkarni __be16 mss; 803*3dde7c95SVishal Kulkarni __be16 r4; 804*3dde7c95SVishal Kulkarni __be32 plen; 805*3dde7c95SVishal Kulkarni } nvgreseg; 806*3dde7c95SVishal Kulkarni struct fw_eth_tx_eo_vxlanseg { 807*3dde7c95SVishal Kulkarni __u8 type; 808*3dde7c95SVishal Kulkarni __u8 iphdroffout; 809*3dde7c95SVishal Kulkarni __be16 vxlanhdroff; 810*3dde7c95SVishal Kulkarni __be16 iphdroffin; 811*3dde7c95SVishal Kulkarni __be16 tcphdroffin; 812*3dde7c95SVishal Kulkarni __be16 mss; 813*3dde7c95SVishal Kulkarni __be16 r4; 814*3dde7c95SVishal Kulkarni __be32 plen; 815*3dde7c95SVishal Kulkarni 816*3dde7c95SVishal Kulkarni } vxlanseg; 817*3dde7c95SVishal Kulkarni struct fw_eth_tx_eo_geneveseg { 818*3dde7c95SVishal Kulkarni __u8 type; 819*3dde7c95SVishal Kulkarni __u8 iphdroffout; 820*3dde7c95SVishal Kulkarni __be16 genevehdroff; 821*3dde7c95SVishal Kulkarni __be16 iphdroffin; 822*3dde7c95SVishal Kulkarni __be16 tcphdroffin; 823*3dde7c95SVishal Kulkarni __be16 mss; 824*3dde7c95SVishal Kulkarni __be16 r4; 825*3dde7c95SVishal Kulkarni __be32 plen; 826*3dde7c95SVishal Kulkarni } geneveseg; 827*3dde7c95SVishal Kulkarni } u; 828*3dde7c95SVishal Kulkarni }; 829*3dde7c95SVishal Kulkarni 830*3dde7c95SVishal Kulkarni #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 831*3dde7c95SVishal Kulkarni #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 832*3dde7c95SVishal Kulkarni #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 833*3dde7c95SVishal Kulkarni #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 834*3dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 835*3dde7c95SVishal Kulkarni 836*3dde7c95SVishal Kulkarni #define S_FW_ETH_TX_EO_WR_TSCLK 6 837*3dde7c95SVishal Kulkarni #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 838*3dde7c95SVishal Kulkarni #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 839*3dde7c95SVishal Kulkarni #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 840*3dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 841*3dde7c95SVishal Kulkarni 842*3dde7c95SVishal Kulkarni #define S_FW_ETH_TX_EO_WR_TSOFF 0 843*3dde7c95SVishal Kulkarni #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 844*3dde7c95SVishal Kulkarni #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 845*3dde7c95SVishal Kulkarni #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 846*3dde7c95SVishal Kulkarni (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 847*3dde7c95SVishal Kulkarni 84856b2bdd1SGireesh Nagabhushana struct fw_eq_flush_wr { 84956b2bdd1SGireesh Nagabhushana __u8 opcode; 85056b2bdd1SGireesh Nagabhushana __u8 r1[3]; 85156b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 85256b2bdd1SGireesh Nagabhushana __be64 r3; 85356b2bdd1SGireesh Nagabhushana }; 85456b2bdd1SGireesh Nagabhushana 85556b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_wr { 85656b2bdd1SGireesh Nagabhushana __be32 op_compl; 85756b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 85856b2bdd1SGireesh Nagabhushana __u64 cookie; 85956b2bdd1SGireesh Nagabhushana __be64 r2; 86056b2bdd1SGireesh Nagabhushana __be64 r3; 86156b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le { 86256b2bdd1SGireesh Nagabhushana __be32 version_cpl; 86356b2bdd1SGireesh Nagabhushana __be32 filter; 86456b2bdd1SGireesh Nagabhushana __be32 r1; 86556b2bdd1SGireesh Nagabhushana __be16 lport; 86656b2bdd1SGireesh Nagabhushana __be16 pport; 86756b2bdd1SGireesh Nagabhushana union fw_ofld_connection_leip { 86856b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le_ipv4 { 86956b2bdd1SGireesh Nagabhushana __be32 pip; 87056b2bdd1SGireesh Nagabhushana __be32 lip; 87156b2bdd1SGireesh Nagabhushana __be64 r0; 87256b2bdd1SGireesh Nagabhushana __be64 r1; 87356b2bdd1SGireesh Nagabhushana __be64 r2; 87456b2bdd1SGireesh Nagabhushana } ipv4; 87556b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_le_ipv6 { 87656b2bdd1SGireesh Nagabhushana __be64 pip_hi; 87756b2bdd1SGireesh Nagabhushana __be64 pip_lo; 87856b2bdd1SGireesh Nagabhushana __be64 lip_hi; 87956b2bdd1SGireesh Nagabhushana __be64 lip_lo; 88056b2bdd1SGireesh Nagabhushana } ipv6; 88156b2bdd1SGireesh Nagabhushana } u; 88256b2bdd1SGireesh Nagabhushana } le; 88356b2bdd1SGireesh Nagabhushana struct fw_ofld_connection_tcb { 88456b2bdd1SGireesh Nagabhushana __be32 t_state_to_astid; 88556b2bdd1SGireesh Nagabhushana __be16 cplrxdataack_cplpassacceptrpl; 88656b2bdd1SGireesh Nagabhushana __be16 rcv_adv; 88756b2bdd1SGireesh Nagabhushana __be32 rcv_nxt; 88856b2bdd1SGireesh Nagabhushana __be32 tx_max; 88956b2bdd1SGireesh Nagabhushana __be64 opt0; 89056b2bdd1SGireesh Nagabhushana __be32 opt2; 89156b2bdd1SGireesh Nagabhushana __be32 r1; 89256b2bdd1SGireesh Nagabhushana __be64 r2; 89356b2bdd1SGireesh Nagabhushana __be64 r3; 89456b2bdd1SGireesh Nagabhushana } tcb; 89556b2bdd1SGireesh Nagabhushana }; 89656b2bdd1SGireesh Nagabhushana 897*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_VERSION 31 898*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 899*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 900*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 901*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 902*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 903*3dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_VERSION) 904*3dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 905*3dde7c95SVishal Kulkarni 906*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_CPL 30 907*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 908*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 909*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 910*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 911*3dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 912*3dde7c95SVishal Kulkarni 913*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 914*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 915*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 916*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 917*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 918*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 919*3dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_T_STATE) 920*3dde7c95SVishal Kulkarni 921*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 922*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 923*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 924*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 925*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 926*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 927*3dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 928*3dde7c95SVishal Kulkarni 929*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_ASTID 0 930*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 931*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 932*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 933*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 934*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 935*3dde7c95SVishal Kulkarni 936*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 937*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 938*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 939*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 940*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 941*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 942*3dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 943*3dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 94456b2bdd1SGireesh Nagabhushana V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 94556b2bdd1SGireesh Nagabhushana 946*3dde7c95SVishal Kulkarni #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 947*3dde7c95SVishal Kulkarni #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 948*3dde7c95SVishal Kulkarni #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 949*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 950*3dde7c95SVishal Kulkarni #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 951*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 952*3dde7c95SVishal Kulkarni M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 953*3dde7c95SVishal Kulkarni #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 95456b2bdd1SGireesh Nagabhushana V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 95556b2bdd1SGireesh Nagabhushana 95656b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem_tcpstate { 957*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 958*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 959*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 960*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 961*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 962*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 963*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 964*3dde7c95SVishal Kulkarni * will resend FIN - equiv ESTAB 965*3dde7c95SVishal Kulkarni */ 966*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 967*3dde7c95SVishal Kulkarni * will resend FIN but have 968*3dde7c95SVishal Kulkarni * received FIN 969*3dde7c95SVishal Kulkarni */ 970*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 971*3dde7c95SVishal Kulkarni * will resend FIN but have 972*3dde7c95SVishal Kulkarni * received FIN 973*3dde7c95SVishal Kulkarni */ 974*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 975*3dde7c95SVishal Kulkarni * waiting for FIN 976*3dde7c95SVishal Kulkarni */ 977*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 978*3dde7c95SVishal Kulkarni }; 979*3dde7c95SVishal Kulkarni 980*3dde7c95SVishal Kulkarni enum fw_flowc_mnem_eostate { 981*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 982*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 983*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 984*3dde7c95SVishal Kulkarni * outstanding payload 985*3dde7c95SVishal Kulkarni */ 986*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 987*3dde7c95SVishal Kulkarni * discarding outstanding payload 988*3dde7c95SVishal Kulkarni */ 98956b2bdd1SGireesh Nagabhushana }; 99056b2bdd1SGireesh Nagabhushana 99156b2bdd1SGireesh Nagabhushana enum fw_flowc_mnem { 992de483253SVishal Kulkarni FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 993de483253SVishal Kulkarni FW_FLOWC_MNEM_CH = 1, 994de483253SVishal Kulkarni FW_FLOWC_MNEM_PORT = 2, 995de483253SVishal Kulkarni FW_FLOWC_MNEM_IQID = 3, 996de483253SVishal Kulkarni FW_FLOWC_MNEM_SNDNXT = 4, 997de483253SVishal Kulkarni FW_FLOWC_MNEM_RCVNXT = 5, 998de483253SVishal Kulkarni FW_FLOWC_MNEM_SNDBUF = 6, 999de483253SVishal Kulkarni FW_FLOWC_MNEM_MSS = 7, 1000de483253SVishal Kulkarni FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1001de483253SVishal Kulkarni FW_FLOWC_MNEM_TCPSTATE = 9, 1002*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_EOSTATE = 10, 1003de483253SVishal Kulkarni FW_FLOWC_MNEM_SCHEDCLASS = 11, 1004de483253SVishal Kulkarni FW_FLOWC_MNEM_DCBPRIO = 12, 1005*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_SND_SCALE = 13, 1006*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_RCV_SCALE = 14, 1007*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_ULP_MODE = 15, 1008*3dde7c95SVishal Kulkarni FW_FLOWC_MNEM_MAX = 16, 100956b2bdd1SGireesh Nagabhushana }; 101056b2bdd1SGireesh Nagabhushana 101156b2bdd1SGireesh Nagabhushana struct fw_flowc_mnemval { 101256b2bdd1SGireesh Nagabhushana __u8 mnemonic; 101356b2bdd1SGireesh Nagabhushana __u8 r4[3]; 101456b2bdd1SGireesh Nagabhushana __be32 val; 101556b2bdd1SGireesh Nagabhushana }; 101656b2bdd1SGireesh Nagabhushana 101756b2bdd1SGireesh Nagabhushana struct fw_flowc_wr { 101856b2bdd1SGireesh Nagabhushana __be32 op_to_nparams; 101956b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 102056b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 1021*3dde7c95SVishal Kulkarni struct fw_flowc_mnemval mnemval[0]; 102256b2bdd1SGireesh Nagabhushana #endif 102356b2bdd1SGireesh Nagabhushana }; 102456b2bdd1SGireesh Nagabhushana 1025*3dde7c95SVishal Kulkarni #define S_FW_FLOWC_WR_NPARAMS 0 1026*3dde7c95SVishal Kulkarni #define M_FW_FLOWC_WR_NPARAMS 0xff 1027*3dde7c95SVishal Kulkarni #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1028*3dde7c95SVishal Kulkarni #define G_FW_FLOWC_WR_NPARAMS(x) \ 1029*3dde7c95SVishal Kulkarni (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 103056b2bdd1SGireesh Nagabhushana 103156b2bdd1SGireesh Nagabhushana struct fw_ofld_tx_data_wr { 103256b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 103356b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 103456b2bdd1SGireesh Nagabhushana __be32 plen; 1035*3dde7c95SVishal Kulkarni __be32 lsodisable_to_flags; 1036*3dde7c95SVishal Kulkarni }; 1037*3dde7c95SVishal Kulkarni 1038*3dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1039*3dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1040*3dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1041*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1042*3dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1043*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1044*3dde7c95SVishal Kulkarni M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1045*3dde7c95SVishal Kulkarni #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1046*3dde7c95SVishal Kulkarni 1047*3dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1048*3dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1049*3dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1050*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1051*3dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1052*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1053*3dde7c95SVishal Kulkarni #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1054*3dde7c95SVishal Kulkarni 1055*3dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1056*3dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1057*3dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1058*3dde7c95SVishal Kulkarni ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1059*3dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1060*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1061*3dde7c95SVishal Kulkarni M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1062*3dde7c95SVishal Kulkarni #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1063*3dde7c95SVishal Kulkarni V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1064*3dde7c95SVishal Kulkarni 1065*3dde7c95SVishal Kulkarni #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1066*3dde7c95SVishal Kulkarni #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1067*3dde7c95SVishal Kulkarni #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1068*3dde7c95SVishal Kulkarni #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1069*3dde7c95SVishal Kulkarni (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1070*3dde7c95SVishal Kulkarni 1071*3dde7c95SVishal Kulkarni 1072*3dde7c95SVishal Kulkarni /* Use fw_ofld_tx_data_wr structure */ 1073*3dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1074*3dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1075*3dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1076*3dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1077*3dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1078*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1079*3dde7c95SVishal Kulkarni 1080*3dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1081*3dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1082*3dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1083*3dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1084*3dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1085*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1086*3dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1087*3dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1088*3dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1089*3dde7c95SVishal Kulkarni 1090*3dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1091*3dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1092*3dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1093*3dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1094*3dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1095*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1096*3dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1097*3dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1098*3dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1099*3dde7c95SVishal Kulkarni 1100*3dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1101*3dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1102*3dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1103*3dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1104*3dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1105*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1106*3dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1107*3dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1108*3dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1109*3dde7c95SVishal Kulkarni 1110*3dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1111*3dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1112*3dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1113*3dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1114*3dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1115*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1116*3dde7c95SVishal Kulkarni M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1117*3dde7c95SVishal Kulkarni #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1118*3dde7c95SVishal Kulkarni V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1119*3dde7c95SVishal Kulkarni 1120*3dde7c95SVishal Kulkarni #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1121*3dde7c95SVishal Kulkarni #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1122*3dde7c95SVishal Kulkarni #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1123*3dde7c95SVishal Kulkarni ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1124*3dde7c95SVishal Kulkarni #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1125*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 112656b2bdd1SGireesh Nagabhushana 112756b2bdd1SGireesh Nagabhushana struct fw_cmd_wr { 112856b2bdd1SGireesh Nagabhushana __be32 op_dma; 112956b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 113056b2bdd1SGireesh Nagabhushana __be64 cookie_daddr; 113156b2bdd1SGireesh Nagabhushana }; 113256b2bdd1SGireesh Nagabhushana 1133*3dde7c95SVishal Kulkarni #define S_FW_CMD_WR_DMA 17 1134*3dde7c95SVishal Kulkarni #define M_FW_CMD_WR_DMA 0x1 1135*3dde7c95SVishal Kulkarni #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1136*3dde7c95SVishal Kulkarni #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1137*3dde7c95SVishal Kulkarni #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 113856b2bdd1SGireesh Nagabhushana 113956b2bdd1SGireesh Nagabhushana struct fw_eth_tx_pkt_vm_wr { 114056b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 114156b2bdd1SGireesh Nagabhushana __be32 equiq_to_len16; 114256b2bdd1SGireesh Nagabhushana __be32 r3[2]; 114356b2bdd1SGireesh Nagabhushana __u8 ethmacdst[6]; 114456b2bdd1SGireesh Nagabhushana __u8 ethmacsrc[6]; 114556b2bdd1SGireesh Nagabhushana __be16 ethtype; 114656b2bdd1SGireesh Nagabhushana __be16 vlantci; 114756b2bdd1SGireesh Nagabhushana }; 114856b2bdd1SGireesh Nagabhushana 1149*3dde7c95SVishal Kulkarni /****************************************************************************** 1150*3dde7c95SVishal Kulkarni * R I W O R K R E Q U E S T s 1151*3dde7c95SVishal Kulkarni **************************************/ 115256b2bdd1SGireesh Nagabhushana 115356b2bdd1SGireesh Nagabhushana enum fw_ri_wr_opcode { 115456b2bdd1SGireesh Nagabhushana FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 115556b2bdd1SGireesh Nagabhushana FW_RI_READ_REQ = 0x1, 115656b2bdd1SGireesh Nagabhushana FW_RI_READ_RESP = 0x2, 115756b2bdd1SGireesh Nagabhushana FW_RI_SEND = 0x3, 115856b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_INV = 0x4, 115956b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_SE = 0x5, 116056b2bdd1SGireesh Nagabhushana FW_RI_SEND_WITH_SE_INV = 0x6, 116156b2bdd1SGireesh Nagabhushana FW_RI_TERMINATE = 0x7, 116256b2bdd1SGireesh Nagabhushana FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 116356b2bdd1SGireesh Nagabhushana FW_RI_BIND_MW = 0x9, 116456b2bdd1SGireesh Nagabhushana FW_RI_FAST_REGISTER = 0xa, 116556b2bdd1SGireesh Nagabhushana FW_RI_LOCAL_INV = 0xb, 116656b2bdd1SGireesh Nagabhushana FW_RI_QP_MODIFY = 0xc, 116756b2bdd1SGireesh Nagabhushana FW_RI_BYPASS = 0xd, 116856b2bdd1SGireesh Nagabhushana FW_RI_RECEIVE = 0xe, 1169*3dde7c95SVishal Kulkarni #if 0 1170*3dde7c95SVishal Kulkarni FW_RI_SEND_IMMEDIATE = 0x8, 1171*3dde7c95SVishal Kulkarni FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1172*3dde7c95SVishal Kulkarni FW_RI_ATOMIC_REQUEST = 0xa, 1173*3dde7c95SVishal Kulkarni FW_RI_ATOMIC_RESPONSE = 0xb, 1174*3dde7c95SVishal Kulkarni 1175*3dde7c95SVishal Kulkarni FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1176*3dde7c95SVishal Kulkarni FW_RI_FAST_REGISTER = 0xd, 1177*3dde7c95SVishal Kulkarni FW_RI_LOCAL_INV = 0xe, 1178*3dde7c95SVishal Kulkarni #endif 117956b2bdd1SGireesh Nagabhushana FW_RI_SGE_EC_CR_RETURN = 0xf 118056b2bdd1SGireesh Nagabhushana }; 118156b2bdd1SGireesh Nagabhushana 118256b2bdd1SGireesh Nagabhushana enum fw_ri_wr_flags { 118356b2bdd1SGireesh Nagabhushana FW_RI_COMPLETION_FLAG = 0x01, 118456b2bdd1SGireesh Nagabhushana FW_RI_NOTIFICATION_FLAG = 0x02, 118556b2bdd1SGireesh Nagabhushana FW_RI_SOLICITED_EVENT_FLAG = 0x04, 118656b2bdd1SGireesh Nagabhushana FW_RI_READ_FENCE_FLAG = 0x08, 118756b2bdd1SGireesh Nagabhushana FW_RI_LOCAL_FENCE_FLAG = 0x10, 118856b2bdd1SGireesh Nagabhushana FW_RI_RDMA_READ_INVALIDATE = 0x20 118956b2bdd1SGireesh Nagabhushana }; 119056b2bdd1SGireesh Nagabhushana 119156b2bdd1SGireesh Nagabhushana enum fw_ri_mpa_attrs { 119256b2bdd1SGireesh Nagabhushana FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 119356b2bdd1SGireesh Nagabhushana FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 119456b2bdd1SGireesh Nagabhushana FW_RI_MPA_CRC_ENABLE = 0x04, 119556b2bdd1SGireesh Nagabhushana FW_RI_MPA_IETF_ENABLE = 0x08 119656b2bdd1SGireesh Nagabhushana }; 119756b2bdd1SGireesh Nagabhushana 119856b2bdd1SGireesh Nagabhushana enum fw_ri_qp_caps { 1199*3dde7c95SVishal Kulkarni FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1200*3dde7c95SVishal Kulkarni FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1201*3dde7c95SVishal Kulkarni FW_RI_QP_BIND_ENABLE = 0x04, 1202*3dde7c95SVishal Kulkarni FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1203*3dde7c95SVishal Kulkarni FW_RI_QP_STAG0_ENABLE = 0x10, 1204*3dde7c95SVishal Kulkarni FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 120556b2bdd1SGireesh Nagabhushana }; 120656b2bdd1SGireesh Nagabhushana 120756b2bdd1SGireesh Nagabhushana enum fw_ri_addr_type { 120856b2bdd1SGireesh Nagabhushana FW_RI_ZERO_BASED_TO = 0x00, 120956b2bdd1SGireesh Nagabhushana FW_RI_VA_BASED_TO = 0x01 121056b2bdd1SGireesh Nagabhushana }; 121156b2bdd1SGireesh Nagabhushana 121256b2bdd1SGireesh Nagabhushana enum fw_ri_mem_perms { 121356b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 121456b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM_READ = 0x02, 121556b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_REM = 0x03, 121656b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 121756b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 121856b2bdd1SGireesh Nagabhushana FW_RI_MEM_ACCESS_LOCAL = 0x0C 121956b2bdd1SGireesh Nagabhushana }; 122056b2bdd1SGireesh Nagabhushana 122156b2bdd1SGireesh Nagabhushana enum fw_ri_stag_type { 122256b2bdd1SGireesh Nagabhushana FW_RI_STAG_NSMR = 0x00, 122356b2bdd1SGireesh Nagabhushana FW_RI_STAG_SMR = 0x01, 122456b2bdd1SGireesh Nagabhushana FW_RI_STAG_MW = 0x02, 122556b2bdd1SGireesh Nagabhushana FW_RI_STAG_MW_RELAXED = 0x03 122656b2bdd1SGireesh Nagabhushana }; 122756b2bdd1SGireesh Nagabhushana 122856b2bdd1SGireesh Nagabhushana enum fw_ri_data_op { 122956b2bdd1SGireesh Nagabhushana FW_RI_DATA_IMMD = 0x81, 123056b2bdd1SGireesh Nagabhushana FW_RI_DATA_DSGL = 0x82, 123156b2bdd1SGireesh Nagabhushana FW_RI_DATA_ISGL = 0x83 123256b2bdd1SGireesh Nagabhushana }; 123356b2bdd1SGireesh Nagabhushana 123456b2bdd1SGireesh Nagabhushana enum fw_ri_sgl_depth { 123556b2bdd1SGireesh Nagabhushana FW_RI_SGL_DEPTH_MAX_SQ = 16, 123656b2bdd1SGireesh Nagabhushana FW_RI_SGL_DEPTH_MAX_RQ = 4 123756b2bdd1SGireesh Nagabhushana }; 123856b2bdd1SGireesh Nagabhushana 123956b2bdd1SGireesh Nagabhushana enum fw_ri_cqe_err { 124056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 124156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 124256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 124356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 124456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 124556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 124656b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1247*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1248*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 124956b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1250*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1251*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 125256b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 125356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 125456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 125556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 125656b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 125756b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 125856b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 125956b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 126056b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 126156b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1262*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 126356b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 126456b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 126556b2bdd1SGireesh Nagabhushana FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1266*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1267*3dde7c95SVishal Kulkarni FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 126856b2bdd1SGireesh Nagabhushana 126956b2bdd1SGireesh Nagabhushana }; 127056b2bdd1SGireesh Nagabhushana 127156b2bdd1SGireesh Nagabhushana struct fw_ri_dsge_pair { 127256b2bdd1SGireesh Nagabhushana __be32 len[2]; 127356b2bdd1SGireesh Nagabhushana __be64 addr[2]; 127456b2bdd1SGireesh Nagabhushana }; 127556b2bdd1SGireesh Nagabhushana 127656b2bdd1SGireesh Nagabhushana struct fw_ri_dsgl { 127756b2bdd1SGireesh Nagabhushana __u8 op; 127856b2bdd1SGireesh Nagabhushana __u8 r1; 127956b2bdd1SGireesh Nagabhushana __be16 nsge; 128056b2bdd1SGireesh Nagabhushana __be32 len0; 128156b2bdd1SGireesh Nagabhushana __be64 addr0; 128256b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 1283*3dde7c95SVishal Kulkarni struct fw_ri_dsge_pair sge[0]; 128456b2bdd1SGireesh Nagabhushana #endif 128556b2bdd1SGireesh Nagabhushana }; 128656b2bdd1SGireesh Nagabhushana 128756b2bdd1SGireesh Nagabhushana struct fw_ri_sge { 128856b2bdd1SGireesh Nagabhushana __be32 stag; 128956b2bdd1SGireesh Nagabhushana __be32 len; 129056b2bdd1SGireesh Nagabhushana __be64 to; 129156b2bdd1SGireesh Nagabhushana }; 129256b2bdd1SGireesh Nagabhushana 129356b2bdd1SGireesh Nagabhushana struct fw_ri_isgl { 129456b2bdd1SGireesh Nagabhushana __u8 op; 129556b2bdd1SGireesh Nagabhushana __u8 r1; 129656b2bdd1SGireesh Nagabhushana __be16 nsge; 129756b2bdd1SGireesh Nagabhushana __be32 r2; 129856b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 1299*3dde7c95SVishal Kulkarni struct fw_ri_sge sge[0]; 130056b2bdd1SGireesh Nagabhushana #endif 130156b2bdd1SGireesh Nagabhushana }; 130256b2bdd1SGireesh Nagabhushana 130356b2bdd1SGireesh Nagabhushana struct fw_ri_immd { 130456b2bdd1SGireesh Nagabhushana __u8 op; 130556b2bdd1SGireesh Nagabhushana __u8 r1; 130656b2bdd1SGireesh Nagabhushana __be16 r2; 130756b2bdd1SGireesh Nagabhushana __be32 immdlen; 130856b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 1309*3dde7c95SVishal Kulkarni __u8 data[0]; 131056b2bdd1SGireesh Nagabhushana #endif 131156b2bdd1SGireesh Nagabhushana }; 131256b2bdd1SGireesh Nagabhushana 131356b2bdd1SGireesh Nagabhushana struct fw_ri_tpte { 131456b2bdd1SGireesh Nagabhushana __be32 valid_to_pdid; 131556b2bdd1SGireesh Nagabhushana __be32 locread_to_qpid; 131656b2bdd1SGireesh Nagabhushana __be32 nosnoop_pbladdr; 131756b2bdd1SGireesh Nagabhushana __be32 len_lo; 131856b2bdd1SGireesh Nagabhushana __be32 va_hi; 131956b2bdd1SGireesh Nagabhushana __be32 va_lo_fbo; 132056b2bdd1SGireesh Nagabhushana __be32 dca_mwbcnt_pstag; 132156b2bdd1SGireesh Nagabhushana __be32 len_hi; 132256b2bdd1SGireesh Nagabhushana }; 132356b2bdd1SGireesh Nagabhushana 1324*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_VALID 31 1325*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_VALID 0x1 1326*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1327*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_VALID(x) \ 1328*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1329*3dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1330*3dde7c95SVishal Kulkarni 1331*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_STAGKEY 23 1332*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_STAGKEY 0xff 1333*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1334*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_STAGKEY(x) \ 1335*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1336*3dde7c95SVishal Kulkarni 1337*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_STAGSTATE 22 1338*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_STAGSTATE 0x1 1339*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1340*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_STAGSTATE(x) \ 1341*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1342*3dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1343*3dde7c95SVishal Kulkarni 1344*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_STAGTYPE 20 1345*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_STAGTYPE 0x3 1346*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1347*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_STAGTYPE(x) \ 1348*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1349*3dde7c95SVishal Kulkarni 1350*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PDID 0 1351*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PDID 0xfffff 1352*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1353*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PDID(x) \ 1354*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1355*3dde7c95SVishal Kulkarni 1356*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PERM 28 1357*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PERM 0xf 1358*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1359*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PERM(x) \ 1360*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1361*3dde7c95SVishal Kulkarni 1362*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_REMINVDIS 27 1363*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_REMINVDIS 0x1 1364*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1365*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_REMINVDIS(x) \ 1366*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1367*3dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1368*3dde7c95SVishal Kulkarni 1369*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_ADDRTYPE 26 1370*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_ADDRTYPE 1 1371*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1372*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1373*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1374*3dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1375*3dde7c95SVishal Kulkarni 1376*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_MWBINDEN 25 1377*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_MWBINDEN 0x1 1378*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1379*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_MWBINDEN(x) \ 1380*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1381*3dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1382*3dde7c95SVishal Kulkarni 1383*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PS 20 1384*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PS 0x1f 1385*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1386*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PS(x) \ 1387*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1388*3dde7c95SVishal Kulkarni 1389*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_QPID 0 1390*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_QPID 0xfffff 1391*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1392*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_QPID(x) \ 1393*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1394*3dde7c95SVishal Kulkarni 1395*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_NOSNOOP 31 1396*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_NOSNOOP 0x1 1397*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1398*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_NOSNOOP(x) \ 1399*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1400*3dde7c95SVishal Kulkarni #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1401*3dde7c95SVishal Kulkarni 1402*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_PBLADDR 0 1403*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1404*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1405*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_PBLADDR(x) \ 1406*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1407*3dde7c95SVishal Kulkarni 1408*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_DCA 24 1409*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_DCA 0x1f 1410*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1411*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_DCA(x) \ 1412*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1413*3dde7c95SVishal Kulkarni 1414*3dde7c95SVishal Kulkarni #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1415*3dde7c95SVishal Kulkarni #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1416*3dde7c95SVishal Kulkarni #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1417*3dde7c95SVishal Kulkarni ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1418*3dde7c95SVishal Kulkarni #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1419*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 142056b2bdd1SGireesh Nagabhushana 142156b2bdd1SGireesh Nagabhushana enum fw_ri_cqe_rxtx { 142256b2bdd1SGireesh Nagabhushana FW_RI_CQE_RXTX_RX = 0x0, 142356b2bdd1SGireesh Nagabhushana FW_RI_CQE_RXTX_TX = 0x1, 142456b2bdd1SGireesh Nagabhushana }; 142556b2bdd1SGireesh Nagabhushana 142656b2bdd1SGireesh Nagabhushana struct fw_ri_cqe { 142756b2bdd1SGireesh Nagabhushana union fw_ri_rxtx { 142856b2bdd1SGireesh Nagabhushana struct fw_ri_scqe { 142956b2bdd1SGireesh Nagabhushana __be32 qpid_n_stat_rxtx_type; 143056b2bdd1SGireesh Nagabhushana __be32 plen; 1431*3dde7c95SVishal Kulkarni __be32 stag; 143256b2bdd1SGireesh Nagabhushana __be32 wrid; 143356b2bdd1SGireesh Nagabhushana } scqe; 143456b2bdd1SGireesh Nagabhushana struct fw_ri_rcqe { 143556b2bdd1SGireesh Nagabhushana __be32 qpid_n_stat_rxtx_type; 143656b2bdd1SGireesh Nagabhushana __be32 plen; 143756b2bdd1SGireesh Nagabhushana __be32 stag; 143856b2bdd1SGireesh Nagabhushana __be32 msn; 143956b2bdd1SGireesh Nagabhushana } rcqe; 144056b2bdd1SGireesh Nagabhushana } u; 144156b2bdd1SGireesh Nagabhushana }; 144256b2bdd1SGireesh Nagabhushana 1443*3dde7c95SVishal Kulkarni #define S_FW_RI_CQE_QPID 12 1444*3dde7c95SVishal Kulkarni #define M_FW_RI_CQE_QPID 0xfffff 1445*3dde7c95SVishal Kulkarni #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1446*3dde7c95SVishal Kulkarni #define G_FW_RI_CQE_QPID(x) \ 1447*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1448*3dde7c95SVishal Kulkarni 1449*3dde7c95SVishal Kulkarni #define S_FW_RI_CQE_NOTIFY 10 1450*3dde7c95SVishal Kulkarni #define M_FW_RI_CQE_NOTIFY 0x1 1451*3dde7c95SVishal Kulkarni #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1452*3dde7c95SVishal Kulkarni #define G_FW_RI_CQE_NOTIFY(x) \ 1453*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1454*3dde7c95SVishal Kulkarni 1455*3dde7c95SVishal Kulkarni #define S_FW_RI_CQE_STATUS 5 1456*3dde7c95SVishal Kulkarni #define M_FW_RI_CQE_STATUS 0x1f 1457*3dde7c95SVishal Kulkarni #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1458*3dde7c95SVishal Kulkarni #define G_FW_RI_CQE_STATUS(x) \ 1459*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1460*3dde7c95SVishal Kulkarni 1461*3dde7c95SVishal Kulkarni 1462*3dde7c95SVishal Kulkarni #define S_FW_RI_CQE_RXTX 4 1463*3dde7c95SVishal Kulkarni #define M_FW_RI_CQE_RXTX 0x1 1464*3dde7c95SVishal Kulkarni #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1465*3dde7c95SVishal Kulkarni #define G_FW_RI_CQE_RXTX(x) \ 1466*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1467*3dde7c95SVishal Kulkarni 1468*3dde7c95SVishal Kulkarni #define S_FW_RI_CQE_TYPE 0 1469*3dde7c95SVishal Kulkarni #define M_FW_RI_CQE_TYPE 0xf 1470*3dde7c95SVishal Kulkarni #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1471*3dde7c95SVishal Kulkarni #define G_FW_RI_CQE_TYPE(x) \ 1472*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 147356b2bdd1SGireesh Nagabhushana 147456b2bdd1SGireesh Nagabhushana enum fw_ri_res_type { 147556b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_SQ, 147656b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_RQ, 147756b2bdd1SGireesh Nagabhushana FW_RI_RES_TYPE_CQ, 1478*3dde7c95SVishal Kulkarni FW_RI_RES_TYPE_SRQ, 147956b2bdd1SGireesh Nagabhushana }; 148056b2bdd1SGireesh Nagabhushana 148156b2bdd1SGireesh Nagabhushana enum fw_ri_res_op { 148256b2bdd1SGireesh Nagabhushana FW_RI_RES_OP_WRITE, 148356b2bdd1SGireesh Nagabhushana FW_RI_RES_OP_RESET, 148456b2bdd1SGireesh Nagabhushana }; 148556b2bdd1SGireesh Nagabhushana 148656b2bdd1SGireesh Nagabhushana struct fw_ri_res { 148756b2bdd1SGireesh Nagabhushana union fw_ri_restype { 148856b2bdd1SGireesh Nagabhushana struct fw_ri_res_sqrq { 148956b2bdd1SGireesh Nagabhushana __u8 restype; 149056b2bdd1SGireesh Nagabhushana __u8 op; 149156b2bdd1SGireesh Nagabhushana __be16 r3; 149256b2bdd1SGireesh Nagabhushana __be32 eqid; 149356b2bdd1SGireesh Nagabhushana __be32 r4[2]; 149456b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 149556b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 149656b2bdd1SGireesh Nagabhushana __be64 eqaddr; 149756b2bdd1SGireesh Nagabhushana } sqrq; 149856b2bdd1SGireesh Nagabhushana struct fw_ri_res_cq { 149956b2bdd1SGireesh Nagabhushana __u8 restype; 150056b2bdd1SGireesh Nagabhushana __u8 op; 150156b2bdd1SGireesh Nagabhushana __be16 r3; 150256b2bdd1SGireesh Nagabhushana __be32 iqid; 150356b2bdd1SGireesh Nagabhushana __be32 r4[2]; 150456b2bdd1SGireesh Nagabhushana __be32 iqandst_to_iqandstindex; 150556b2bdd1SGireesh Nagabhushana __be16 iqdroprss_to_iqesize; 150656b2bdd1SGireesh Nagabhushana __be16 iqsize; 150756b2bdd1SGireesh Nagabhushana __be64 iqaddr; 150856b2bdd1SGireesh Nagabhushana __be32 iqns_iqro; 150956b2bdd1SGireesh Nagabhushana __be32 r6_lo; 151056b2bdd1SGireesh Nagabhushana __be64 r7; 151156b2bdd1SGireesh Nagabhushana } cq; 1512*3dde7c95SVishal Kulkarni struct fw_ri_res_srq { 1513*3dde7c95SVishal Kulkarni __u8 restype; 1514*3dde7c95SVishal Kulkarni __u8 op; 1515*3dde7c95SVishal Kulkarni __be16 r3; 1516*3dde7c95SVishal Kulkarni __be32 eqid; 1517*3dde7c95SVishal Kulkarni __be32 r4[2]; 1518*3dde7c95SVishal Kulkarni __be32 fetchszm_to_iqid; 1519*3dde7c95SVishal Kulkarni __be32 dcaen_to_eqsize; 1520*3dde7c95SVishal Kulkarni __be64 eqaddr; 1521*3dde7c95SVishal Kulkarni __be32 srqid; 1522*3dde7c95SVishal Kulkarni __be32 pdid; 1523*3dde7c95SVishal Kulkarni __be32 hwsrqsize; 1524*3dde7c95SVishal Kulkarni __be32 hwsrqaddr; 1525*3dde7c95SVishal Kulkarni } srq; 152656b2bdd1SGireesh Nagabhushana } u; 152756b2bdd1SGireesh Nagabhushana }; 152856b2bdd1SGireesh Nagabhushana 152956b2bdd1SGireesh Nagabhushana struct fw_ri_res_wr { 153056b2bdd1SGireesh Nagabhushana __be32 op_nres; 153156b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 153256b2bdd1SGireesh Nagabhushana __u64 cookie; 153356b2bdd1SGireesh Nagabhushana #ifndef C99_NOT_SUPPORTED 1534*3dde7c95SVishal Kulkarni struct fw_ri_res res[0]; 153556b2bdd1SGireesh Nagabhushana #endif 153656b2bdd1SGireesh Nagabhushana }; 153756b2bdd1SGireesh Nagabhushana 1538*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_VFN 8 1539*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_VFN 0xff 1540*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1541*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_VFN(x) \ 1542*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1543*3dde7c95SVishal Kulkarni 1544*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_NRES 0 1545*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_NRES 0xff 1546*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1547*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_NRES(x) \ 1548*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1549*3dde7c95SVishal Kulkarni 1550*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FETCHSZM 26 1551*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FETCHSZM 0x1 1552*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1553*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1554*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1555*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1556*3dde7c95SVishal Kulkarni 1557*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_STATUSPGNS 25 1558*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1559*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1560*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1561*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1562*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1563*3dde7c95SVishal Kulkarni 1564*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_STATUSPGRO 24 1565*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1566*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1567*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1568*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1569*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1570*3dde7c95SVishal Kulkarni 1571*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FETCHNS 23 1572*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FETCHNS 0x1 1573*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1574*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FETCHNS(x) \ 1575*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1576*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1577*3dde7c95SVishal Kulkarni 1578*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FETCHRO 22 1579*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FETCHRO 0x1 1580*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1581*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FETCHRO(x) \ 1582*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1583*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1584*3dde7c95SVishal Kulkarni 1585*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_HOSTFCMODE 20 1586*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1587*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1588*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1589*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1590*3dde7c95SVishal Kulkarni 1591*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_CPRIO 19 1592*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_CPRIO 0x1 1593*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1594*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_CPRIO(x) \ 1595*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1596*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1597*3dde7c95SVishal Kulkarni 1598*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_ONCHIP 18 1599*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_ONCHIP 0x1 1600*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1601*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_ONCHIP(x) \ 1602*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1603*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1604*3dde7c95SVishal Kulkarni 1605*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_PCIECHN 16 1606*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_PCIECHN 0x3 1607*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1608*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_PCIECHN(x) \ 1609*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1610*3dde7c95SVishal Kulkarni 1611*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQID 0 1612*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQID 0xffff 1613*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1614*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQID(x) \ 1615*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1616*3dde7c95SVishal Kulkarni 1617*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_DCAEN 31 1618*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_DCAEN 0x1 1619*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1620*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_DCAEN(x) \ 1621*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1622*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1623*3dde7c95SVishal Kulkarni 1624*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_DCACPU 26 1625*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_DCACPU 0x1f 1626*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1627*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_DCACPU(x) \ 1628*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1629*3dde7c95SVishal Kulkarni 1630*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FBMIN 23 1631*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FBMIN 0x7 1632*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1633*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FBMIN(x) \ 1634*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1635*3dde7c95SVishal Kulkarni 1636*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_FBMAX 20 1637*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_FBMAX 0x7 1638*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1639*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_FBMAX(x) \ 1640*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1641*3dde7c95SVishal Kulkarni 1642*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1643*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1644*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1645*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1646*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1647*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1648*3dde7c95SVishal Kulkarni 1649*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1650*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1651*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1652*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1653*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1654*3dde7c95SVishal Kulkarni 1655*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_EQSIZE 0 1656*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_EQSIZE 0xffff 1657*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1658*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_EQSIZE(x) \ 1659*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1660*3dde7c95SVishal Kulkarni 1661*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANDST 15 1662*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANDST 0x1 1663*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1664*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANDST(x) \ 1665*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1666*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1667*3dde7c95SVishal Kulkarni 1668*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANUS 14 1669*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANUS 0x1 1670*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1671*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANUS(x) \ 1672*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1673*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1674*3dde7c95SVishal Kulkarni 1675*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANUD 12 1676*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANUD 0x3 1677*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1678*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANUD(x) \ 1679*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1680*3dde7c95SVishal Kulkarni 1681*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1682*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1683*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1684*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1685*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1686*3dde7c95SVishal Kulkarni 1687*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQDROPRSS 15 1688*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1689*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1690*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1691*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1692*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1693*3dde7c95SVishal Kulkarni 1694*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQGTSMODE 14 1695*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1696*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1697*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1698*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1699*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1700*3dde7c95SVishal Kulkarni 1701*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQPCIECH 12 1702*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQPCIECH 0x3 1703*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1704*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1705*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1706*3dde7c95SVishal Kulkarni 1707*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQDCAEN 11 1708*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQDCAEN 0x1 1709*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1710*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1711*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1712*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1713*3dde7c95SVishal Kulkarni 1714*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQDCACPU 6 1715*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1716*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1717*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1718*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1719*3dde7c95SVishal Kulkarni 1720*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1721*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1722*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1723*3dde7c95SVishal Kulkarni ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1724*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1725*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1726*3dde7c95SVishal Kulkarni 1727*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQO 3 1728*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQO 0x1 1729*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1730*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQO(x) \ 1731*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1732*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1733*3dde7c95SVishal Kulkarni 1734*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQCPRIO 2 1735*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQCPRIO 0x1 1736*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1737*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1738*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1739*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1740*3dde7c95SVishal Kulkarni 1741*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQESIZE 0 1742*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQESIZE 0x3 1743*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1744*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQESIZE(x) \ 1745*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1746*3dde7c95SVishal Kulkarni 1747*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQNS 31 1748*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQNS 0x1 1749*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1750*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQNS(x) \ 1751*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1752*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1753*3dde7c95SVishal Kulkarni 1754*3dde7c95SVishal Kulkarni #define S_FW_RI_RES_WR_IQRO 30 1755*3dde7c95SVishal Kulkarni #define M_FW_RI_RES_WR_IQRO 0x1 1756*3dde7c95SVishal Kulkarni #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1757*3dde7c95SVishal Kulkarni #define G_FW_RI_RES_WR_IQRO(x) \ 1758*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1759*3dde7c95SVishal Kulkarni #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 176056b2bdd1SGireesh Nagabhushana 176156b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_write_wr { 176256b2bdd1SGireesh Nagabhushana __u8 opcode; 176356b2bdd1SGireesh Nagabhushana __u8 flags; 176456b2bdd1SGireesh Nagabhushana __u16 wrid; 176556b2bdd1SGireesh Nagabhushana __u8 r1[3]; 176656b2bdd1SGireesh Nagabhushana __u8 len16; 176756b2bdd1SGireesh Nagabhushana __be64 r2; 176856b2bdd1SGireesh Nagabhushana __be32 plen; 176956b2bdd1SGireesh Nagabhushana __be32 stag_sink; 177056b2bdd1SGireesh Nagabhushana __be64 to_sink; 1771*3dde7c95SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 1772*3dde7c95SVishal Kulkarni union { 1773*3dde7c95SVishal Kulkarni struct fw_ri_immd immd_src[0]; 1774*3dde7c95SVishal Kulkarni struct fw_ri_isgl isgl_src[0]; 1775*3dde7c95SVishal Kulkarni } u; 1776*3dde7c95SVishal Kulkarni #endif 177756b2bdd1SGireesh Nagabhushana }; 177856b2bdd1SGireesh Nagabhushana 177956b2bdd1SGireesh Nagabhushana struct fw_ri_send_wr { 178056b2bdd1SGireesh Nagabhushana __u8 opcode; 178156b2bdd1SGireesh Nagabhushana __u8 flags; 178256b2bdd1SGireesh Nagabhushana __u16 wrid; 178356b2bdd1SGireesh Nagabhushana __u8 r1[3]; 178456b2bdd1SGireesh Nagabhushana __u8 len16; 178556b2bdd1SGireesh Nagabhushana __be32 sendop_pkd; 178656b2bdd1SGireesh Nagabhushana __be32 stag_inv; 178756b2bdd1SGireesh Nagabhushana __be32 plen; 178856b2bdd1SGireesh Nagabhushana __be32 r3; 178956b2bdd1SGireesh Nagabhushana __be64 r4; 1790*3dde7c95SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 1791*3dde7c95SVishal Kulkarni union { 1792*3dde7c95SVishal Kulkarni struct fw_ri_immd immd_src[0]; 1793*3dde7c95SVishal Kulkarni struct fw_ri_isgl isgl_src[0]; 1794*3dde7c95SVishal Kulkarni } u; 1795*3dde7c95SVishal Kulkarni #endif 179656b2bdd1SGireesh Nagabhushana }; 179756b2bdd1SGireesh Nagabhushana 1798*3dde7c95SVishal Kulkarni #define S_FW_RI_SEND_WR_SENDOP 0 1799*3dde7c95SVishal Kulkarni #define M_FW_RI_SEND_WR_SENDOP 0xf 1800*3dde7c95SVishal Kulkarni #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1801*3dde7c95SVishal Kulkarni #define G_FW_RI_SEND_WR_SENDOP(x) \ 1802*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 180356b2bdd1SGireesh Nagabhushana 180456b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_read_wr { 180556b2bdd1SGireesh Nagabhushana __u8 opcode; 180656b2bdd1SGireesh Nagabhushana __u8 flags; 180756b2bdd1SGireesh Nagabhushana __u16 wrid; 180856b2bdd1SGireesh Nagabhushana __u8 r1[3]; 180956b2bdd1SGireesh Nagabhushana __u8 len16; 181056b2bdd1SGireesh Nagabhushana __be64 r2; 181156b2bdd1SGireesh Nagabhushana __be32 stag_sink; 181256b2bdd1SGireesh Nagabhushana __be32 to_sink_hi; 181356b2bdd1SGireesh Nagabhushana __be32 to_sink_lo; 181456b2bdd1SGireesh Nagabhushana __be32 plen; 181556b2bdd1SGireesh Nagabhushana __be32 stag_src; 181656b2bdd1SGireesh Nagabhushana __be32 to_src_hi; 181756b2bdd1SGireesh Nagabhushana __be32 to_src_lo; 181856b2bdd1SGireesh Nagabhushana __be32 r5; 181956b2bdd1SGireesh Nagabhushana }; 182056b2bdd1SGireesh Nagabhushana 182156b2bdd1SGireesh Nagabhushana struct fw_ri_recv_wr { 182256b2bdd1SGireesh Nagabhushana __u8 opcode; 182356b2bdd1SGireesh Nagabhushana __u8 r1; 182456b2bdd1SGireesh Nagabhushana __u16 wrid; 182556b2bdd1SGireesh Nagabhushana __u8 r2[3]; 182656b2bdd1SGireesh Nagabhushana __u8 len16; 1827*3dde7c95SVishal Kulkarni struct fw_ri_isgl isgl; 182856b2bdd1SGireesh Nagabhushana }; 182956b2bdd1SGireesh Nagabhushana 183056b2bdd1SGireesh Nagabhushana struct fw_ri_bind_mw_wr { 183156b2bdd1SGireesh Nagabhushana __u8 opcode; 183256b2bdd1SGireesh Nagabhushana __u8 flags; 183356b2bdd1SGireesh Nagabhushana __u16 wrid; 183456b2bdd1SGireesh Nagabhushana __u8 r1[3]; 183556b2bdd1SGireesh Nagabhushana __u8 len16; 183656b2bdd1SGireesh Nagabhushana __u8 qpbinde_to_dcacpu; 183756b2bdd1SGireesh Nagabhushana __u8 pgsz_shift; 183856b2bdd1SGireesh Nagabhushana __u8 addr_type; 183956b2bdd1SGireesh Nagabhushana __u8 mem_perms; 184056b2bdd1SGireesh Nagabhushana __be32 stag_mr; 184156b2bdd1SGireesh Nagabhushana __be32 stag_mw; 184256b2bdd1SGireesh Nagabhushana __be32 r3; 184356b2bdd1SGireesh Nagabhushana __be64 len_mw; 184456b2bdd1SGireesh Nagabhushana __be64 va_fbo; 184556b2bdd1SGireesh Nagabhushana __be64 r4; 184656b2bdd1SGireesh Nagabhushana }; 184756b2bdd1SGireesh Nagabhushana 1848*3dde7c95SVishal Kulkarni #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1849*3dde7c95SVishal Kulkarni #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1850*3dde7c95SVishal Kulkarni #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1851*3dde7c95SVishal Kulkarni #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1852*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1853*3dde7c95SVishal Kulkarni #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 185456b2bdd1SGireesh Nagabhushana 1855*3dde7c95SVishal Kulkarni #define S_FW_RI_BIND_MW_WR_NS 5 1856*3dde7c95SVishal Kulkarni #define M_FW_RI_BIND_MW_WR_NS 0x1 1857*3dde7c95SVishal Kulkarni #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1858*3dde7c95SVishal Kulkarni #define G_FW_RI_BIND_MW_WR_NS(x) \ 1859*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1860*3dde7c95SVishal Kulkarni #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 186156b2bdd1SGireesh Nagabhushana 1862*3dde7c95SVishal Kulkarni #define S_FW_RI_BIND_MW_WR_DCACPU 0 1863*3dde7c95SVishal Kulkarni #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1864*3dde7c95SVishal Kulkarni #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1865*3dde7c95SVishal Kulkarni #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1866*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 186756b2bdd1SGireesh Nagabhushana 186856b2bdd1SGireesh Nagabhushana struct fw_ri_fr_nsmr_wr { 186956b2bdd1SGireesh Nagabhushana __u8 opcode; 187056b2bdd1SGireesh Nagabhushana __u8 flags; 187156b2bdd1SGireesh Nagabhushana __u16 wrid; 187256b2bdd1SGireesh Nagabhushana __u8 r1[3]; 187356b2bdd1SGireesh Nagabhushana __u8 len16; 187456b2bdd1SGireesh Nagabhushana __u8 qpbinde_to_dcacpu; 187556b2bdd1SGireesh Nagabhushana __u8 pgsz_shift; 187656b2bdd1SGireesh Nagabhushana __u8 addr_type; 187756b2bdd1SGireesh Nagabhushana __u8 mem_perms; 187856b2bdd1SGireesh Nagabhushana __be32 stag; 187956b2bdd1SGireesh Nagabhushana __be32 len_hi; 188056b2bdd1SGireesh Nagabhushana __be32 len_lo; 188156b2bdd1SGireesh Nagabhushana __be32 va_hi; 188256b2bdd1SGireesh Nagabhushana __be32 va_lo_fbo; 188356b2bdd1SGireesh Nagabhushana }; 188456b2bdd1SGireesh Nagabhushana 1885*3dde7c95SVishal Kulkarni #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1886*3dde7c95SVishal Kulkarni #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1887*3dde7c95SVishal Kulkarni #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1888*3dde7c95SVishal Kulkarni #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1889*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1890*3dde7c95SVishal Kulkarni #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1891*3dde7c95SVishal Kulkarni 1892*3dde7c95SVishal Kulkarni #define S_FW_RI_FR_NSMR_WR_NS 5 1893*3dde7c95SVishal Kulkarni #define M_FW_RI_FR_NSMR_WR_NS 0x1 1894*3dde7c95SVishal Kulkarni #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1895*3dde7c95SVishal Kulkarni #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1896*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1897*3dde7c95SVishal Kulkarni #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 189856b2bdd1SGireesh Nagabhushana 1899*3dde7c95SVishal Kulkarni #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1900*3dde7c95SVishal Kulkarni #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1901*3dde7c95SVishal Kulkarni #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1902*3dde7c95SVishal Kulkarni #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1903*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 190456b2bdd1SGireesh Nagabhushana 1905*3dde7c95SVishal Kulkarni struct fw_ri_fr_nsmr_tpte_wr { 1906*3dde7c95SVishal Kulkarni __u8 opcode; 1907*3dde7c95SVishal Kulkarni __u8 flags; 1908*3dde7c95SVishal Kulkarni __u16 wrid; 1909*3dde7c95SVishal Kulkarni __u8 r1[3]; 1910*3dde7c95SVishal Kulkarni __u8 len16; 1911*3dde7c95SVishal Kulkarni __be32 r2; 1912*3dde7c95SVishal Kulkarni __be32 stag; 1913*3dde7c95SVishal Kulkarni struct fw_ri_tpte tpte; 1914*3dde7c95SVishal Kulkarni __be64 pbl[2]; 1915*3dde7c95SVishal Kulkarni }; 191656b2bdd1SGireesh Nagabhushana 191756b2bdd1SGireesh Nagabhushana struct fw_ri_inv_lstag_wr { 191856b2bdd1SGireesh Nagabhushana __u8 opcode; 191956b2bdd1SGireesh Nagabhushana __u8 flags; 192056b2bdd1SGireesh Nagabhushana __u16 wrid; 192156b2bdd1SGireesh Nagabhushana __u8 r1[3]; 192256b2bdd1SGireesh Nagabhushana __u8 len16; 192356b2bdd1SGireesh Nagabhushana __be32 r2; 192456b2bdd1SGireesh Nagabhushana __be32 stag_inv; 192556b2bdd1SGireesh Nagabhushana }; 192656b2bdd1SGireesh Nagabhushana 192756b2bdd1SGireesh Nagabhushana struct fw_ri_send_immediate_wr { 192856b2bdd1SGireesh Nagabhushana __u8 opcode; 192956b2bdd1SGireesh Nagabhushana __u8 flags; 193056b2bdd1SGireesh Nagabhushana __u16 wrid; 193156b2bdd1SGireesh Nagabhushana __u8 r1[3]; 193256b2bdd1SGireesh Nagabhushana __u8 len16; 193356b2bdd1SGireesh Nagabhushana __be32 sendimmop_pkd; 193456b2bdd1SGireesh Nagabhushana __be32 r3; 193556b2bdd1SGireesh Nagabhushana __be32 plen; 193656b2bdd1SGireesh Nagabhushana __be32 r4; 193756b2bdd1SGireesh Nagabhushana __be64 r5; 1938*3dde7c95SVishal Kulkarni #ifndef C99_NOT_SUPPORTED 1939*3dde7c95SVishal Kulkarni struct fw_ri_immd immd_src[0]; 1940*3dde7c95SVishal Kulkarni #endif 194156b2bdd1SGireesh Nagabhushana }; 194256b2bdd1SGireesh Nagabhushana 1943*3dde7c95SVishal Kulkarni #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1944*3dde7c95SVishal Kulkarni #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1945*3dde7c95SVishal Kulkarni #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1946*3dde7c95SVishal Kulkarni ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1947*3dde7c95SVishal Kulkarni #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1948*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1949*3dde7c95SVishal Kulkarni M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 195056b2bdd1SGireesh Nagabhushana 195156b2bdd1SGireesh Nagabhushana enum fw_ri_atomic_op { 195256b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_FETCHADD, 195356b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_SWAP, 195456b2bdd1SGireesh Nagabhushana FW_RI_ATOMIC_OP_CMDSWAP, 195556b2bdd1SGireesh Nagabhushana }; 195656b2bdd1SGireesh Nagabhushana 195756b2bdd1SGireesh Nagabhushana struct fw_ri_atomic_wr { 195856b2bdd1SGireesh Nagabhushana __u8 opcode; 195956b2bdd1SGireesh Nagabhushana __u8 flags; 196056b2bdd1SGireesh Nagabhushana __u16 wrid; 196156b2bdd1SGireesh Nagabhushana __u8 r1[3]; 196256b2bdd1SGireesh Nagabhushana __u8 len16; 196356b2bdd1SGireesh Nagabhushana __be32 atomicop_pkd; 196456b2bdd1SGireesh Nagabhushana __be64 r3; 196556b2bdd1SGireesh Nagabhushana __be32 aopcode_pkd; 196656b2bdd1SGireesh Nagabhushana __be32 reqid; 196756b2bdd1SGireesh Nagabhushana __be32 stag; 196856b2bdd1SGireesh Nagabhushana __be32 to_hi; 196956b2bdd1SGireesh Nagabhushana __be32 to_lo; 197056b2bdd1SGireesh Nagabhushana __be32 addswap_data_hi; 197156b2bdd1SGireesh Nagabhushana __be32 addswap_data_lo; 197256b2bdd1SGireesh Nagabhushana __be32 addswap_mask_hi; 197356b2bdd1SGireesh Nagabhushana __be32 addswap_mask_lo; 197456b2bdd1SGireesh Nagabhushana __be32 compare_data_hi; 197556b2bdd1SGireesh Nagabhushana __be32 compare_data_lo; 197656b2bdd1SGireesh Nagabhushana __be32 compare_mask_hi; 197756b2bdd1SGireesh Nagabhushana __be32 compare_mask_lo; 197856b2bdd1SGireesh Nagabhushana __be32 r5; 197956b2bdd1SGireesh Nagabhushana }; 198056b2bdd1SGireesh Nagabhushana 1981*3dde7c95SVishal Kulkarni #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1982*3dde7c95SVishal Kulkarni #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1983*3dde7c95SVishal Kulkarni #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1984*3dde7c95SVishal Kulkarni #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1985*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 198656b2bdd1SGireesh Nagabhushana 1987*3dde7c95SVishal Kulkarni #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1988*3dde7c95SVishal Kulkarni #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1989*3dde7c95SVishal Kulkarni #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1990*3dde7c95SVishal Kulkarni #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1991*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 199256b2bdd1SGireesh Nagabhushana 199356b2bdd1SGireesh Nagabhushana enum fw_ri_type { 199456b2bdd1SGireesh Nagabhushana FW_RI_TYPE_INIT, 199556b2bdd1SGireesh Nagabhushana FW_RI_TYPE_FINI, 199656b2bdd1SGireesh Nagabhushana FW_RI_TYPE_TERMINATE 199756b2bdd1SGireesh Nagabhushana }; 199856b2bdd1SGireesh Nagabhushana 199956b2bdd1SGireesh Nagabhushana enum fw_ri_init_p2ptype { 200056b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 200156b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 200256b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 200356b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 200456b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 200556b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 200656b2bdd1SGireesh Nagabhushana FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 200756b2bdd1SGireesh Nagabhushana }; 200856b2bdd1SGireesh Nagabhushana 2009*3dde7c95SVishal Kulkarni enum fw_ri_init_rqeqid_srq { 2010*3dde7c95SVishal Kulkarni FW_RI_INIT_RQEQID_SRQ = 1U << 31, 2011*3dde7c95SVishal Kulkarni }; 2012*3dde7c95SVishal Kulkarni 201356b2bdd1SGireesh Nagabhushana struct fw_ri_wr { 201456b2bdd1SGireesh Nagabhushana __be32 op_compl; 201556b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 201656b2bdd1SGireesh Nagabhushana __u64 cookie; 201756b2bdd1SGireesh Nagabhushana union fw_ri { 201856b2bdd1SGireesh Nagabhushana struct fw_ri_init { 201956b2bdd1SGireesh Nagabhushana __u8 type; 202056b2bdd1SGireesh Nagabhushana __u8 mpareqbit_p2ptype; 202156b2bdd1SGireesh Nagabhushana __u8 r4[2]; 202256b2bdd1SGireesh Nagabhushana __u8 mpa_attrs; 202356b2bdd1SGireesh Nagabhushana __u8 qp_caps; 202456b2bdd1SGireesh Nagabhushana __be16 nrqe; 202556b2bdd1SGireesh Nagabhushana __be32 pdid; 202656b2bdd1SGireesh Nagabhushana __be32 qpid; 202756b2bdd1SGireesh Nagabhushana __be32 sq_eqid; 202856b2bdd1SGireesh Nagabhushana __be32 rq_eqid; 202956b2bdd1SGireesh Nagabhushana __be32 scqid; 203056b2bdd1SGireesh Nagabhushana __be32 rcqid; 203156b2bdd1SGireesh Nagabhushana __be32 ord_max; 203256b2bdd1SGireesh Nagabhushana __be32 ird_max; 203356b2bdd1SGireesh Nagabhushana __be32 iss; 203456b2bdd1SGireesh Nagabhushana __be32 irs; 203556b2bdd1SGireesh Nagabhushana __be32 hwrqsize; 203656b2bdd1SGireesh Nagabhushana __be32 hwrqaddr; 203756b2bdd1SGireesh Nagabhushana __be64 r5; 203856b2bdd1SGireesh Nagabhushana union fw_ri_init_p2p { 203956b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_write_wr write; 204056b2bdd1SGireesh Nagabhushana struct fw_ri_rdma_read_wr read; 204156b2bdd1SGireesh Nagabhushana struct fw_ri_send_wr send; 204256b2bdd1SGireesh Nagabhushana } u; 204356b2bdd1SGireesh Nagabhushana } init; 204456b2bdd1SGireesh Nagabhushana struct fw_ri_fini { 204556b2bdd1SGireesh Nagabhushana __u8 type; 204656b2bdd1SGireesh Nagabhushana __u8 r3[7]; 204756b2bdd1SGireesh Nagabhushana __be64 r4; 204856b2bdd1SGireesh Nagabhushana } fini; 204956b2bdd1SGireesh Nagabhushana struct fw_ri_terminate { 205056b2bdd1SGireesh Nagabhushana __u8 type; 205156b2bdd1SGireesh Nagabhushana __u8 r3[3]; 205256b2bdd1SGireesh Nagabhushana __be32 immdlen; 205356b2bdd1SGireesh Nagabhushana __u8 termmsg[40]; 205456b2bdd1SGireesh Nagabhushana } terminate; 205556b2bdd1SGireesh Nagabhushana } u; 205656b2bdd1SGireesh Nagabhushana }; 205756b2bdd1SGireesh Nagabhushana 2058*3dde7c95SVishal Kulkarni #define S_FW_RI_WR_MPAREQBIT 7 2059*3dde7c95SVishal Kulkarni #define M_FW_RI_WR_MPAREQBIT 0x1 2060*3dde7c95SVishal Kulkarni #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2061*3dde7c95SVishal Kulkarni #define G_FW_RI_WR_MPAREQBIT(x) \ 2062*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2063*3dde7c95SVishal Kulkarni #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 206456b2bdd1SGireesh Nagabhushana 2065*3dde7c95SVishal Kulkarni #define S_FW_RI_WR_0BRRBIT 6 2066*3dde7c95SVishal Kulkarni #define M_FW_RI_WR_0BRRBIT 0x1 2067*3dde7c95SVishal Kulkarni #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2068*3dde7c95SVishal Kulkarni #define G_FW_RI_WR_0BRRBIT(x) \ 2069*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2070*3dde7c95SVishal Kulkarni #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 207156b2bdd1SGireesh Nagabhushana 2072*3dde7c95SVishal Kulkarni #define S_FW_RI_WR_P2PTYPE 0 2073*3dde7c95SVishal Kulkarni #define M_FW_RI_WR_P2PTYPE 0xf 2074*3dde7c95SVishal Kulkarni #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2075*3dde7c95SVishal Kulkarni #define G_FW_RI_WR_P2PTYPE(x) \ 2076*3dde7c95SVishal Kulkarni (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 207756b2bdd1SGireesh Nagabhushana 2078*3dde7c95SVishal Kulkarni /****************************************************************************** 2079*3dde7c95SVishal Kulkarni * F O i S C S I W O R K R E Q U E S T s 2080*3dde7c95SVishal Kulkarni *********************************************/ 208156b2bdd1SGireesh Nagabhushana 208256b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_NAME_MAX_LEN 224 208356b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_ALIAS_MAX_LEN 224 2084*3dde7c95SVishal Kulkarni #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 208556b2bdd1SGireesh Nagabhushana #define FW_FOISCSI_INIT_NODE_MAX 8 208656b2bdd1SGireesh Nagabhushana 208756b2bdd1SGireesh Nagabhushana enum fw_chnet_ifconf_wr_subop { 208856b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 208956b2bdd1SGireesh Nagabhushana 209056b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 209156b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 209256b2bdd1SGireesh Nagabhushana 209356b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 209456b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 209556b2bdd1SGireesh Nagabhushana 209656b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 209756b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 209856b2bdd1SGireesh Nagabhushana 209956b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 210056b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 210156b2bdd1SGireesh Nagabhushana 210256b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 210356b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 210456b2bdd1SGireesh Nagabhushana 210556b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 210656b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 210756b2bdd1SGireesh Nagabhushana 2108*3dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2109*3dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2110*3dde7c95SVishal Kulkarni 2111*3dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2112*3dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2113*3dde7c95SVishal Kulkarni FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2114*3dde7c95SVishal Kulkarni 211556b2bdd1SGireesh Nagabhushana FW_CHNET_IFCONF_WR_SUBOP_MAX, 211656b2bdd1SGireesh Nagabhushana }; 211756b2bdd1SGireesh Nagabhushana 211856b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_wr { 211956b2bdd1SGireesh Nagabhushana __be32 op_compl; 212056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 212156b2bdd1SGireesh Nagabhushana __be64 cookie; 212256b2bdd1SGireesh Nagabhushana __be32 if_flowid; 212356b2bdd1SGireesh Nagabhushana __u8 idx; 212456b2bdd1SGireesh Nagabhushana __u8 subop; 212556b2bdd1SGireesh Nagabhushana __u8 retval; 212656b2bdd1SGireesh Nagabhushana __u8 r2; 212756b2bdd1SGireesh Nagabhushana __be64 r3; 212856b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_params { 212956b2bdd1SGireesh Nagabhushana __be32 r0; 213056b2bdd1SGireesh Nagabhushana __be16 vlanid; 213156b2bdd1SGireesh Nagabhushana __be16 mtu; 213256b2bdd1SGireesh Nagabhushana union fw_chnet_ifconf_addr_type { 213356b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_ipv4 { 213456b2bdd1SGireesh Nagabhushana __be32 addr; 213556b2bdd1SGireesh Nagabhushana __be32 mask; 213656b2bdd1SGireesh Nagabhushana __be32 router; 213756b2bdd1SGireesh Nagabhushana __be32 r0; 213856b2bdd1SGireesh Nagabhushana __be64 r1; 213956b2bdd1SGireesh Nagabhushana } ipv4; 214056b2bdd1SGireesh Nagabhushana struct fw_chnet_ifconf_ipv6 { 2141*3dde7c95SVishal Kulkarni __u8 prefix_len; 2142*3dde7c95SVishal Kulkarni __u8 r0; 2143*3dde7c95SVishal Kulkarni __be16 r1; 2144*3dde7c95SVishal Kulkarni __be32 r2; 2145*3dde7c95SVishal Kulkarni __be64 addr_hi; 2146*3dde7c95SVishal Kulkarni __be64 addr_lo; 214756b2bdd1SGireesh Nagabhushana __be64 router_hi; 214856b2bdd1SGireesh Nagabhushana __be64 router_lo; 214956b2bdd1SGireesh Nagabhushana } ipv6; 215056b2bdd1SGireesh Nagabhushana } in_attr; 215156b2bdd1SGireesh Nagabhushana } param; 215256b2bdd1SGireesh Nagabhushana }; 215356b2bdd1SGireesh Nagabhushana 2154de483253SVishal Kulkarni enum fw_foiscsi_node_type { 2155de483253SVishal Kulkarni FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2156de483253SVishal Kulkarni FW_FOISCSI_NODE_TYPE_TARGET, 2157de483253SVishal Kulkarni }; 2158de483253SVishal Kulkarni 215956b2bdd1SGireesh Nagabhushana enum fw_foiscsi_session_type { 216056b2bdd1SGireesh Nagabhushana FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 216156b2bdd1SGireesh Nagabhushana FW_FOISCSI_SESSION_TYPE_NORMAL, 216256b2bdd1SGireesh Nagabhushana }; 216356b2bdd1SGireesh Nagabhushana 216456b2bdd1SGireesh Nagabhushana enum fw_foiscsi_auth_policy { 216556b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 216656b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_POLICY_MUTUAL, 216756b2bdd1SGireesh Nagabhushana }; 216856b2bdd1SGireesh Nagabhushana 216956b2bdd1SGireesh Nagabhushana enum fw_foiscsi_auth_method { 217056b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_NONE = 0, 217156b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP, 217256b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP_FST, 217356b2bdd1SGireesh Nagabhushana FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 217456b2bdd1SGireesh Nagabhushana }; 217556b2bdd1SGireesh Nagabhushana 217656b2bdd1SGireesh Nagabhushana enum fw_foiscsi_digest_type { 217756b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_NONE = 0, 217856b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32, 217956b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 218056b2bdd1SGireesh Nagabhushana FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 218156b2bdd1SGireesh Nagabhushana }; 218256b2bdd1SGireesh Nagabhushana 218356b2bdd1SGireesh Nagabhushana enum fw_foiscsi_wr_subop { 218456b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_ADD = 1, 218556b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_DEL = 2, 218656b2bdd1SGireesh Nagabhushana FW_FOISCSI_WR_SUBOP_MOD = 4, 218756b2bdd1SGireesh Nagabhushana }; 218856b2bdd1SGireesh Nagabhushana 218956b2bdd1SGireesh Nagabhushana enum fw_foiscsi_ctrl_state { 219056b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_FREE = 0, 219156b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_ONLINE = 1, 219256b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_FAILED, 219356b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 219456b2bdd1SGireesh Nagabhushana FW_FOISCSI_CTRL_STATE_REDIRECT, 219556b2bdd1SGireesh Nagabhushana }; 219656b2bdd1SGireesh Nagabhushana 219756b2bdd1SGireesh Nagabhushana struct fw_rdev_wr { 219856b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 219956b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 220056b2bdd1SGireesh Nagabhushana __be64 cookie; 220156b2bdd1SGireesh Nagabhushana __u8 protocol; 220256b2bdd1SGireesh Nagabhushana __u8 event_cause; 220356b2bdd1SGireesh Nagabhushana __u8 cur_state; 220456b2bdd1SGireesh Nagabhushana __u8 prev_state; 220556b2bdd1SGireesh Nagabhushana __be32 flags_to_assoc_flowid; 220656b2bdd1SGireesh Nagabhushana union rdev_entry { 220756b2bdd1SGireesh Nagabhushana struct fcoe_rdev_entry { 220856b2bdd1SGireesh Nagabhushana __be32 flowid; 220956b2bdd1SGireesh Nagabhushana __u8 protocol; 221056b2bdd1SGireesh Nagabhushana __u8 event_cause; 221156b2bdd1SGireesh Nagabhushana __u8 flags; 221256b2bdd1SGireesh Nagabhushana __u8 rjt_reason; 221356b2bdd1SGireesh Nagabhushana __u8 cur_login_st; 221456b2bdd1SGireesh Nagabhushana __u8 prev_login_st; 221556b2bdd1SGireesh Nagabhushana __be16 rcv_fr_sz; 221656b2bdd1SGireesh Nagabhushana __u8 rd_xfer_rdy_to_rport_type; 221756b2bdd1SGireesh Nagabhushana __u8 vft_to_qos; 221856b2bdd1SGireesh Nagabhushana __u8 org_proc_assoc_to_acc_rsp_code; 221956b2bdd1SGireesh Nagabhushana __u8 enh_disc_to_tgt; 222056b2bdd1SGireesh Nagabhushana __u8 wwnn[8]; 222156b2bdd1SGireesh Nagabhushana __u8 wwpn[8]; 222256b2bdd1SGireesh Nagabhushana __be16 iqid; 222356b2bdd1SGireesh Nagabhushana __u8 fc_oui[3]; 222456b2bdd1SGireesh Nagabhushana __u8 r_id[3]; 222556b2bdd1SGireesh Nagabhushana } fcoe_rdev; 222656b2bdd1SGireesh Nagabhushana struct iscsi_rdev_entry { 222756b2bdd1SGireesh Nagabhushana __be32 flowid; 222856b2bdd1SGireesh Nagabhushana __u8 protocol; 222956b2bdd1SGireesh Nagabhushana __u8 event_cause; 223056b2bdd1SGireesh Nagabhushana __u8 flags; 223156b2bdd1SGireesh Nagabhushana __u8 r3; 223256b2bdd1SGireesh Nagabhushana __be16 iscsi_opts; 223356b2bdd1SGireesh Nagabhushana __be16 tcp_opts; 223456b2bdd1SGireesh Nagabhushana __be16 ip_opts; 223556b2bdd1SGireesh Nagabhushana __be16 max_rcv_len; 223656b2bdd1SGireesh Nagabhushana __be16 max_snd_len; 223756b2bdd1SGireesh Nagabhushana __be16 first_brst_len; 223856b2bdd1SGireesh Nagabhushana __be16 max_brst_len; 223956b2bdd1SGireesh Nagabhushana __be16 r4; 224056b2bdd1SGireesh Nagabhushana __be16 def_time2wait; 224156b2bdd1SGireesh Nagabhushana __be16 def_time2ret; 224256b2bdd1SGireesh Nagabhushana __be16 nop_out_intrvl; 224356b2bdd1SGireesh Nagabhushana __be16 non_scsi_to; 224456b2bdd1SGireesh Nagabhushana __be16 isid; 224556b2bdd1SGireesh Nagabhushana __be16 tsid; 224656b2bdd1SGireesh Nagabhushana __be16 port; 224756b2bdd1SGireesh Nagabhushana __be16 tpgt; 224856b2bdd1SGireesh Nagabhushana __u8 r5[6]; 224956b2bdd1SGireesh Nagabhushana __be16 iqid; 225056b2bdd1SGireesh Nagabhushana } iscsi_rdev; 225156b2bdd1SGireesh Nagabhushana } u; 225256b2bdd1SGireesh Nagabhushana }; 225356b2bdd1SGireesh Nagabhushana 2254*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_IMMDLEN 0 2255*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_IMMDLEN 0xff 2256*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2257*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_IMMDLEN(x) \ 2258*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2259*3dde7c95SVishal Kulkarni 2260*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ALLOC 31 2261*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ALLOC 0x1 2262*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2263*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ALLOC(x) \ 2264*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2265*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2266*3dde7c95SVishal Kulkarni 2267*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FREE 30 2268*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FREE 0x1 2269*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2270*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FREE(x) \ 2271*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2272*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2273*3dde7c95SVishal Kulkarni 2274*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_MODIFY 29 2275*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_MODIFY 0x1 2276*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2277*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_MODIFY(x) \ 2278*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2279*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2280*3dde7c95SVishal Kulkarni 2281*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FLOWID 8 2282*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FLOWID 0xfffff 2283*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2284*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FLOWID(x) \ 2285*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2286*3dde7c95SVishal Kulkarni 2287*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_LEN16 0 2288*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_LEN16 0xff 2289*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2290*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_LEN16(x) \ 2291*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2292*3dde7c95SVishal Kulkarni 2293*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FLAGS 24 2294*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FLAGS 0xff 2295*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2296*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FLAGS(x) \ 2297*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2298*3dde7c95SVishal Kulkarni 2299*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_GET_NEXT 20 2300*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_GET_NEXT 0xf 2301*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2302*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_GET_NEXT(x) \ 2303*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2304*3dde7c95SVishal Kulkarni 2305*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2306*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2307*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2308*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2309*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2310*3dde7c95SVishal Kulkarni 2311*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RJT 7 2312*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RJT 0x1 2313*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2314*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2315*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2316*3dde7c95SVishal Kulkarni 2317*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_REASON 0 2318*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_REASON 0x7f 2319*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2320*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_REASON(x) \ 2321*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2322*3dde7c95SVishal Kulkarni 2323*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RD_XFER_RDY 7 2324*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2325*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2326*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2327*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2328*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2329*3dde7c95SVishal Kulkarni 2330*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_WR_XFER_RDY 6 2331*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2332*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2333*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2334*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2335*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2336*3dde7c95SVishal Kulkarni 2337*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_FC_SP 5 2338*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_FC_SP 0x1 2339*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2340*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_FC_SP(x) \ 2341*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2342*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2343*3dde7c95SVishal Kulkarni 2344*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RPORT_TYPE 0 2345*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2346*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2347*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2348*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2349*3dde7c95SVishal Kulkarni 2350*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_VFT 7 2351*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_VFT 0x1 2352*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2353*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2354*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2355*3dde7c95SVishal Kulkarni 2356*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_NPIV 6 2357*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_NPIV 0x1 2358*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2359*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_NPIV(x) \ 2360*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2361*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2362*3dde7c95SVishal Kulkarni 2363*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_CLASS 4 2364*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_CLASS 0x3 2365*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2366*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_CLASS(x) \ 2367*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2368*3dde7c95SVishal Kulkarni 2369*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_SEQ_DEL 3 2370*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_SEQ_DEL 0x1 2371*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2372*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2373*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2374*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2375*3dde7c95SVishal Kulkarni 2376*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_PRIO_PREEMP 2 2377*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2378*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2379*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2380*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2381*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2382*3dde7c95SVishal Kulkarni 2383*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_PREF 1 2384*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_PREF 0x1 2385*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2386*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_PREF(x) \ 2387*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2388*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2389*3dde7c95SVishal Kulkarni 2390*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_QOS 0 2391*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_QOS 0x1 2392*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2393*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2394*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2395*3dde7c95SVishal Kulkarni 2396*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2397*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2398*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2399*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2400*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2401*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2402*3dde7c95SVishal Kulkarni 2403*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2404*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2405*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2406*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2407*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2408*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2409*3dde7c95SVishal Kulkarni 2410*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_IMAGE_PAIR 5 2411*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2412*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2413*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2414*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2415*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2416*3dde7c95SVishal Kulkarni 2417*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2418*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2419*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2420*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2421*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2422*3dde7c95SVishal Kulkarni 2423*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_ENH_DISC 7 2424*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_ENH_DISC 0x1 2425*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2426*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_ENH_DISC(x) \ 2427*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2428*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2429*3dde7c95SVishal Kulkarni 2430*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_REC 6 2431*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_REC 0x1 2432*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2433*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2434*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2435*3dde7c95SVishal Kulkarni 2436*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2437*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2438*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2439*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2440*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2441*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2442*3dde7c95SVishal Kulkarni 2443*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_RETRY 4 2444*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_RETRY 0x1 2445*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2446*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_RETRY(x) \ 2447*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2448*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2449*3dde7c95SVishal Kulkarni 2450*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_CONF_CMPL 3 2451*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_CONF_CMPL 0x1 2452*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2453*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2454*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2455*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2456*3dde7c95SVishal Kulkarni 2457*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_DATA_OVLY 2 2458*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_DATA_OVLY 0x1 2459*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2460*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2461*3dde7c95SVishal Kulkarni (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2462*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2463*3dde7c95SVishal Kulkarni 2464*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_INI 1 2465*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_INI 0x1 2466*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2467*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2468*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2469*3dde7c95SVishal Kulkarni 2470*3dde7c95SVishal Kulkarni #define S_FW_RDEV_WR_TGT 0 2471*3dde7c95SVishal Kulkarni #define M_FW_RDEV_WR_TGT 0x1 2472*3dde7c95SVishal Kulkarni #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2473*3dde7c95SVishal Kulkarni #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2474*3dde7c95SVishal Kulkarni #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 247556b2bdd1SGireesh Nagabhushana 247656b2bdd1SGireesh Nagabhushana struct fw_foiscsi_node_wr { 247756b2bdd1SGireesh Nagabhushana __be32 op_to_immdlen; 247856b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 247956b2bdd1SGireesh Nagabhushana __u64 cookie; 248056b2bdd1SGireesh Nagabhushana __u8 subop; 248156b2bdd1SGireesh Nagabhushana __u8 status; 248256b2bdd1SGireesh Nagabhushana __u8 alias_len; 248356b2bdd1SGireesh Nagabhushana __u8 iqn_len; 248456b2bdd1SGireesh Nagabhushana __be32 node_flowid; 248556b2bdd1SGireesh Nagabhushana __be16 nodeid; 248656b2bdd1SGireesh Nagabhushana __be16 login_retry; 248756b2bdd1SGireesh Nagabhushana __be16 retry_timeout; 248856b2bdd1SGireesh Nagabhushana __be16 r3; 248956b2bdd1SGireesh Nagabhushana __u8 iqn[224]; 249056b2bdd1SGireesh Nagabhushana __u8 alias[224]; 249156b2bdd1SGireesh Nagabhushana }; 249256b2bdd1SGireesh Nagabhushana 2493*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2494*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2495*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2496*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2497*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 249856b2bdd1SGireesh Nagabhushana 249956b2bdd1SGireesh Nagabhushana struct fw_foiscsi_ctrl_wr { 250056b2bdd1SGireesh Nagabhushana __be32 op_compl; 250156b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 250256b2bdd1SGireesh Nagabhushana __u64 cookie; 250356b2bdd1SGireesh Nagabhushana __u8 subop; 250456b2bdd1SGireesh Nagabhushana __u8 status; 250556b2bdd1SGireesh Nagabhushana __u8 ctrl_state; 250656b2bdd1SGireesh Nagabhushana __u8 io_state; 250756b2bdd1SGireesh Nagabhushana __be32 node_id; 250856b2bdd1SGireesh Nagabhushana __be32 ctrl_id; 250956b2bdd1SGireesh Nagabhushana __be32 io_id; 251056b2bdd1SGireesh Nagabhushana struct fw_foiscsi_sess_attr { 251156b2bdd1SGireesh Nagabhushana __be32 sess_type_to_erl; 251256b2bdd1SGireesh Nagabhushana __be16 max_conn; 251356b2bdd1SGireesh Nagabhushana __be16 max_r2t; 251456b2bdd1SGireesh Nagabhushana __be16 time2wait; 251556b2bdd1SGireesh Nagabhushana __be16 time2retain; 251656b2bdd1SGireesh Nagabhushana __be32 max_burst; 251756b2bdd1SGireesh Nagabhushana __be32 first_burst; 251856b2bdd1SGireesh Nagabhushana __be32 r1; 251956b2bdd1SGireesh Nagabhushana } sess_attr; 252056b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr { 2521de483253SVishal Kulkarni __be32 hdigest_to_ddp_pgsz; 252256b2bdd1SGireesh Nagabhushana __be32 max_rcv_dsl; 252356b2bdd1SGireesh Nagabhushana __be32 ping_tmo; 252456b2bdd1SGireesh Nagabhushana __be16 dst_port; 252556b2bdd1SGireesh Nagabhushana __be16 src_port; 252656b2bdd1SGireesh Nagabhushana union fw_foiscsi_conn_attr_addr { 252756b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr_ipv6 { 252856b2bdd1SGireesh Nagabhushana __be64 dst_addr[2]; 252956b2bdd1SGireesh Nagabhushana __be64 src_addr[2]; 253056b2bdd1SGireesh Nagabhushana } ipv6_addr; 253156b2bdd1SGireesh Nagabhushana struct fw_foiscsi_conn_attr_ipv4 { 253256b2bdd1SGireesh Nagabhushana __be32 dst_addr; 253356b2bdd1SGireesh Nagabhushana __be32 src_addr; 253456b2bdd1SGireesh Nagabhushana } ipv4_addr; 253556b2bdd1SGireesh Nagabhushana } u; 253656b2bdd1SGireesh Nagabhushana } conn_attr; 253756b2bdd1SGireesh Nagabhushana __u8 tgt_name_len; 253856b2bdd1SGireesh Nagabhushana __u8 r3[7]; 2539de483253SVishal Kulkarni __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 254056b2bdd1SGireesh Nagabhushana }; 254156b2bdd1SGireesh Nagabhushana 2542*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2543*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2544*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2545*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2546*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2547*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2548*3dde7c95SVishal Kulkarni 2549*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2550*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2551*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2552*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2553*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2554*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2555*3dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2556*3dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 255756b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 255856b2bdd1SGireesh Nagabhushana 2559*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2560*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2561*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2562*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2563*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2564*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2565*3dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2566*3dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 256756b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 256856b2bdd1SGireesh Nagabhushana 2569*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2570*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2571*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2572*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2573*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2574*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2575*3dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2576*3dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 257756b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 257856b2bdd1SGireesh Nagabhushana 2579*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2580*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2581*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2582*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2583*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2584*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2585*3dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2586*3dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 258756b2bdd1SGireesh Nagabhushana V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 258856b2bdd1SGireesh Nagabhushana 2589*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_ERL 24 2590*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2591*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2592*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2593*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2594*3dde7c95SVishal Kulkarni 2595*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2596*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2597*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2598*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2599*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2600*3dde7c95SVishal Kulkarni 2601*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2602*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2603*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2604*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2605*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2606*3dde7c95SVishal Kulkarni 2607*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2608*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2609*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2610*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2611*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2612*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2613*3dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2614*3dde7c95SVishal Kulkarni 2615*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2616*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2617*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2618*3dde7c95SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2619*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2620*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2621*3dde7c95SVishal Kulkarni M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 262256b2bdd1SGireesh Nagabhushana 2623de483253SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2624de483253SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2625de483253SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2626de483253SVishal Kulkarni ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2627de483253SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2628de483253SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2629de483253SVishal Kulkarni 2630*3dde7c95SVishal Kulkarni #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2631*3dde7c95SVishal Kulkarni #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2632*3dde7c95SVishal Kulkarni #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2633*3dde7c95SVishal Kulkarni #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2634*3dde7c95SVishal Kulkarni (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2635*3dde7c95SVishal Kulkarni #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2636*3dde7c95SVishal Kulkarni 263756b2bdd1SGireesh Nagabhushana struct fw_foiscsi_chap_wr { 263856b2bdd1SGireesh Nagabhushana __be32 op_compl; 263956b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 264056b2bdd1SGireesh Nagabhushana __u64 cookie; 264156b2bdd1SGireesh Nagabhushana __u8 status; 264256b2bdd1SGireesh Nagabhushana __u8 id_len; 264356b2bdd1SGireesh Nagabhushana __u8 sec_len; 2644de483253SVishal Kulkarni __u8 node_type; 264556b2bdd1SGireesh Nagabhushana __be16 node_id; 2646de483253SVishal Kulkarni __u8 r3[2]; 2647de483253SVishal Kulkarni __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2648de483253SVishal Kulkarni __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 264956b2bdd1SGireesh Nagabhushana }; 265056b2bdd1SGireesh Nagabhushana 2651*3dde7c95SVishal Kulkarni /****************************************************************************** 2652*3dde7c95SVishal Kulkarni * C O i S C S I W O R K R E Q U E S T S 2653*3dde7c95SVishal Kulkarni ********************************************/ 2654*3dde7c95SVishal Kulkarni 2655*3dde7c95SVishal Kulkarni enum fw_chnet_addr_type { 2656*3dde7c95SVishal Kulkarni FW_CHNET_ADDD_TYPE_NONE = 0, 2657*3dde7c95SVishal Kulkarni FW_CHNET_ADDR_TYPE_IPV4, 2658*3dde7c95SVishal Kulkarni FW_CHNET_ADDR_TYPE_IPV6, 2659*3dde7c95SVishal Kulkarni }; 2660*3dde7c95SVishal Kulkarni 2661*3dde7c95SVishal Kulkarni enum fw_msg_wr_type { 2662*3dde7c95SVishal Kulkarni FW_MSG_WR_TYPE_RPL = 0, 2663*3dde7c95SVishal Kulkarni FW_MSG_WR_TYPE_ERR, 2664*3dde7c95SVishal Kulkarni FW_MSG_WR_TYPE_PLD, 2665*3dde7c95SVishal Kulkarni }; 2666*3dde7c95SVishal Kulkarni 2667*3dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_wr { 2668*3dde7c95SVishal Kulkarni __be32 op_compl; 2669*3dde7c95SVishal Kulkarni __be32 flowid_len16; 2670*3dde7c95SVishal Kulkarni __u64 cookie; 2671*3dde7c95SVishal Kulkarni __u8 subop; 2672*3dde7c95SVishal Kulkarni __u8 status; 2673*3dde7c95SVishal Kulkarni __be16 r4; 2674*3dde7c95SVishal Kulkarni __be32 flags; 2675*3dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_conn_attr { 2676*3dde7c95SVishal Kulkarni __be32 in_tid; 2677*3dde7c95SVishal Kulkarni __be16 in_port; 2678*3dde7c95SVishal Kulkarni __u8 in_type; 2679*3dde7c95SVishal Kulkarni __u8 r6; 2680*3dde7c95SVishal Kulkarni union fw_coiscsi_tgt_conn_attr_addr { 2681*3dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_conn_attr_in_addr { 2682*3dde7c95SVishal Kulkarni __be32 addr; 2683*3dde7c95SVishal Kulkarni __be32 r7; 2684*3dde7c95SVishal Kulkarni __be32 r8[2]; 2685*3dde7c95SVishal Kulkarni } in_addr; 2686*3dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2687*3dde7c95SVishal Kulkarni __be64 addr[2]; 2688*3dde7c95SVishal Kulkarni } in_addr6; 2689*3dde7c95SVishal Kulkarni } u; 2690*3dde7c95SVishal Kulkarni } conn_attr; 2691*3dde7c95SVishal Kulkarni }; 2692*3dde7c95SVishal Kulkarni 2693*3dde7c95SVishal Kulkarni struct fw_coiscsi_tgt_xmit_wr { 2694*3dde7c95SVishal Kulkarni __be32 op_to_immdlen; 2695*3dde7c95SVishal Kulkarni __be32 flowid_len16; 2696*3dde7c95SVishal Kulkarni __be64 cookie; 2697*3dde7c95SVishal Kulkarni __be16 iq_id; 2698*3dde7c95SVishal Kulkarni __be16 r4; 2699*3dde7c95SVishal Kulkarni __be32 datasn; 2700*3dde7c95SVishal Kulkarni __be32 t_xfer_len; 2701*3dde7c95SVishal Kulkarni __be32 flags; 2702*3dde7c95SVishal Kulkarni __be32 tag; 2703*3dde7c95SVishal Kulkarni __be32 tidx; 2704*3dde7c95SVishal Kulkarni __be32 r5[2]; 2705*3dde7c95SVishal Kulkarni }; 2706*3dde7c95SVishal Kulkarni 2707*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2708*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2709*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2710*3dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2711*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2712*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2713*3dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2714*3dde7c95SVishal Kulkarni 2715*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2716*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2717*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2718*3dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2719*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2720*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2721*3dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2722*3dde7c95SVishal Kulkarni 2723*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2724*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2725*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2726*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2727*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2728*3dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2729*3dde7c95SVishal Kulkarni 2730*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 2731*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 2732*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2733*3dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2734*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2735*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2736*3dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 2737*3dde7c95SVishal Kulkarni 2738*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 2739*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 2740*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2741*3dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2742*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2743*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2744*3dde7c95SVishal Kulkarni #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 2745*3dde7c95SVishal Kulkarni 2746*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 2747*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 2748*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2749*3dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2750*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2751*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 2752*3dde7c95SVishal Kulkarni M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2753*3dde7c95SVishal Kulkarni 2754*3dde7c95SVishal Kulkarni #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2755*3dde7c95SVishal Kulkarni #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2756*3dde7c95SVishal Kulkarni #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2757*3dde7c95SVishal Kulkarni ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2758*3dde7c95SVishal Kulkarni #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2759*3dde7c95SVishal Kulkarni (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2760*3dde7c95SVishal Kulkarni M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2761*3dde7c95SVishal Kulkarni 2762*3dde7c95SVishal Kulkarni struct fw_isns_wr { 2763*3dde7c95SVishal Kulkarni __be32 op_compl; 2764*3dde7c95SVishal Kulkarni __be32 flowid_len16; 2765*3dde7c95SVishal Kulkarni __u64 cookie; 2766*3dde7c95SVishal Kulkarni __u8 subop; 2767*3dde7c95SVishal Kulkarni __u8 status; 2768*3dde7c95SVishal Kulkarni __be16 iq_id; 2769*3dde7c95SVishal Kulkarni __be32 r4; 2770*3dde7c95SVishal Kulkarni struct fw_tcp_conn_attr { 2771*3dde7c95SVishal Kulkarni __be32 in_tid; 2772*3dde7c95SVishal Kulkarni __be16 in_port; 2773*3dde7c95SVishal Kulkarni __u8 in_type; 2774*3dde7c95SVishal Kulkarni __u8 r6; 2775*3dde7c95SVishal Kulkarni union fw_tcp_conn_attr_addr { 2776*3dde7c95SVishal Kulkarni struct fw_tcp_conn_attr_in_addr { 2777*3dde7c95SVishal Kulkarni __be32 addr; 2778*3dde7c95SVishal Kulkarni __be32 r7; 2779*3dde7c95SVishal Kulkarni __be32 r8[2]; 2780*3dde7c95SVishal Kulkarni } in_addr; 2781*3dde7c95SVishal Kulkarni struct fw_tcp_conn_attr_in_addr6 { 2782*3dde7c95SVishal Kulkarni __be64 addr[2]; 2783*3dde7c95SVishal Kulkarni } in_addr6; 2784*3dde7c95SVishal Kulkarni } u; 2785*3dde7c95SVishal Kulkarni } conn_attr; 2786*3dde7c95SVishal Kulkarni }; 2787*3dde7c95SVishal Kulkarni 2788*3dde7c95SVishal Kulkarni struct fw_isns_xmit_wr { 2789*3dde7c95SVishal Kulkarni __be32 op_to_immdlen; 2790*3dde7c95SVishal Kulkarni __be32 flowid_len16; 2791*3dde7c95SVishal Kulkarni __be64 cookie; 2792*3dde7c95SVishal Kulkarni __be16 iq_id; 2793*3dde7c95SVishal Kulkarni __be16 r4; 2794*3dde7c95SVishal Kulkarni __be32 xfer_len; 2795*3dde7c95SVishal Kulkarni __be64 r5; 2796*3dde7c95SVishal Kulkarni }; 2797*3dde7c95SVishal Kulkarni 2798*3dde7c95SVishal Kulkarni #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2799*3dde7c95SVishal Kulkarni #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2800*3dde7c95SVishal Kulkarni #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2801*3dde7c95SVishal Kulkarni #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2802*3dde7c95SVishal Kulkarni (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2803*3dde7c95SVishal Kulkarni 2804*3dde7c95SVishal Kulkarni /****************************************************************************** 2805*3dde7c95SVishal Kulkarni * F O F C O E W O R K R E Q U E S T s 2806*3dde7c95SVishal Kulkarni *******************************************/ 280756b2bdd1SGireesh Nagabhushana 280856b2bdd1SGireesh Nagabhushana struct fw_fcoe_els_ct_wr { 280956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 281056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 281156b2bdd1SGireesh Nagabhushana __be64 cookie; 281256b2bdd1SGireesh Nagabhushana __be16 iqid; 281356b2bdd1SGireesh Nagabhushana __u8 tmo_val; 281456b2bdd1SGireesh Nagabhushana __u8 els_ct_type; 281556b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 281656b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 281756b2bdd1SGireesh Nagabhushana __be16 xfer_cnt; 281856b2bdd1SGireesh Nagabhushana __u8 fl_to_sp; 281956b2bdd1SGireesh Nagabhushana __u8 l_id[3]; 282056b2bdd1SGireesh Nagabhushana __u8 r5; 282156b2bdd1SGireesh Nagabhushana __u8 r_id[3]; 282256b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 282356b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 282456b2bdd1SGireesh Nagabhushana __be32 r6; 282556b2bdd1SGireesh Nagabhushana }; 282656b2bdd1SGireesh Nagabhushana 2827*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2828*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2829*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2830*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2831*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2832*3dde7c95SVishal Kulkarni 2833*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2834*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2835*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2836*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2837*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2838*3dde7c95SVishal Kulkarni 2839*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2840*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2841*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2842*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2843*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2844*3dde7c95SVishal Kulkarni 2845*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2846*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2847*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2848*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2849*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2850*3dde7c95SVishal Kulkarni 2851*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2852*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2853*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2854*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2855*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2856*3dde7c95SVishal Kulkarni 2857*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2858*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2859*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2860*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2861*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2862*3dde7c95SVishal Kulkarni 2863*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_FL 2 2864*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2865*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2866*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2867*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2868*3dde7c95SVishal Kulkarni #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2869*3dde7c95SVishal Kulkarni 2870*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2871*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2872*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2873*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2874*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2875*3dde7c95SVishal Kulkarni #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2876*3dde7c95SVishal Kulkarni 2877*3dde7c95SVishal Kulkarni #define S_FW_FCOE_ELS_CT_WR_SP 0 2878*3dde7c95SVishal Kulkarni #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2879*3dde7c95SVishal Kulkarni #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2880*3dde7c95SVishal Kulkarni #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2881*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2882*3dde7c95SVishal Kulkarni #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2883*3dde7c95SVishal Kulkarni 2884*3dde7c95SVishal Kulkarni /****************************************************************************** 2885*3dde7c95SVishal Kulkarni * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2886*3dde7c95SVishal Kulkarni *****************************************************************************/ 288756b2bdd1SGireesh Nagabhushana 288856b2bdd1SGireesh Nagabhushana struct fw_scsi_write_wr { 288956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 289056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 289156b2bdd1SGireesh Nagabhushana __be64 cookie; 289256b2bdd1SGireesh Nagabhushana __be16 iqid; 289356b2bdd1SGireesh Nagabhushana __u8 tmo_val; 289456b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 289556b2bdd1SGireesh Nagabhushana union fw_scsi_write_priv { 289656b2bdd1SGireesh Nagabhushana struct fcoe_write_priv { 289756b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 289856b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 289956b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 290056b2bdd1SGireesh Nagabhushana } fcoe; 290156b2bdd1SGireesh Nagabhushana struct iscsi_write_priv { 290256b2bdd1SGireesh Nagabhushana __u8 r3[4]; 290356b2bdd1SGireesh Nagabhushana } iscsi; 290456b2bdd1SGireesh Nagabhushana } u; 290556b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 290656b2bdd1SGireesh Nagabhushana __be32 ini_xfer_cnt; 290756b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 290856b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 290956b2bdd1SGireesh Nagabhushana __be32 r4; 291056b2bdd1SGireesh Nagabhushana }; 291156b2bdd1SGireesh Nagabhushana 2912*3dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_OPCODE 24 2913*3dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2914*3dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2915*3dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2916*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2917*3dde7c95SVishal Kulkarni 2918*3dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2919*3dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2920*3dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2921*3dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2922*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2923*3dde7c95SVishal Kulkarni 2924*3dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_FLOWID 8 2925*3dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2926*3dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2927*3dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2928*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2929*3dde7c95SVishal Kulkarni 2930*3dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_LEN16 0 2931*3dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2932*3dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2933*3dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2934*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2935*3dde7c95SVishal Kulkarni 2936*3dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_CP_EN 6 2937*3dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2938*3dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2939*3dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2940*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2941*3dde7c95SVishal Kulkarni 2942*3dde7c95SVishal Kulkarni #define S_FW_SCSI_WRITE_WR_CLASS 4 2943*3dde7c95SVishal Kulkarni #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2944*3dde7c95SVishal Kulkarni #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2945*3dde7c95SVishal Kulkarni #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2946*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 294756b2bdd1SGireesh Nagabhushana 294856b2bdd1SGireesh Nagabhushana struct fw_scsi_read_wr { 294956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 295056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 295156b2bdd1SGireesh Nagabhushana __be64 cookie; 295256b2bdd1SGireesh Nagabhushana __be16 iqid; 295356b2bdd1SGireesh Nagabhushana __u8 tmo_val; 295456b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 295556b2bdd1SGireesh Nagabhushana union fw_scsi_read_priv { 295656b2bdd1SGireesh Nagabhushana struct fcoe_read_priv { 295756b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 295856b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 295956b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 296056b2bdd1SGireesh Nagabhushana } fcoe; 296156b2bdd1SGireesh Nagabhushana struct iscsi_read_priv { 296256b2bdd1SGireesh Nagabhushana __u8 r3[4]; 296356b2bdd1SGireesh Nagabhushana } iscsi; 296456b2bdd1SGireesh Nagabhushana } u; 296556b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 296656b2bdd1SGireesh Nagabhushana __be32 ini_xfer_cnt; 296756b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 296856b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 296956b2bdd1SGireesh Nagabhushana __be32 r4; 297056b2bdd1SGireesh Nagabhushana }; 297156b2bdd1SGireesh Nagabhushana 2972*3dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_OPCODE 24 2973*3dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_OPCODE 0xff 2974*3dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2975*3dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2976*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2977*3dde7c95SVishal Kulkarni 2978*3dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_IMMDLEN 0 2979*3dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2980*3dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2981*3dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2982*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2983*3dde7c95SVishal Kulkarni 2984*3dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_FLOWID 8 2985*3dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2986*3dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2987*3dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2988*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2989*3dde7c95SVishal Kulkarni 2990*3dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_LEN16 0 2991*3dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_LEN16 0xff 2992*3dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2993*3dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_LEN16(x) \ 2994*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2995*3dde7c95SVishal Kulkarni 2996*3dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_CP_EN 6 2997*3dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_CP_EN 0x3 2998*3dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2999*3dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3000*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3001*3dde7c95SVishal Kulkarni 3002*3dde7c95SVishal Kulkarni #define S_FW_SCSI_READ_WR_CLASS 4 3003*3dde7c95SVishal Kulkarni #define M_FW_SCSI_READ_WR_CLASS 0x3 3004*3dde7c95SVishal Kulkarni #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3005*3dde7c95SVishal Kulkarni #define G_FW_SCSI_READ_WR_CLASS(x) \ 3006*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 300756b2bdd1SGireesh Nagabhushana 300856b2bdd1SGireesh Nagabhushana struct fw_scsi_cmd_wr { 300956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 301056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 301156b2bdd1SGireesh Nagabhushana __be64 cookie; 301256b2bdd1SGireesh Nagabhushana __be16 iqid; 301356b2bdd1SGireesh Nagabhushana __u8 tmo_val; 301456b2bdd1SGireesh Nagabhushana __u8 r3; 301556b2bdd1SGireesh Nagabhushana union fw_scsi_cmd_priv { 301656b2bdd1SGireesh Nagabhushana struct fcoe_cmd_priv { 301756b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 301856b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 301956b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 302056b2bdd1SGireesh Nagabhushana } fcoe; 302156b2bdd1SGireesh Nagabhushana struct iscsi_cmd_priv { 302256b2bdd1SGireesh Nagabhushana __u8 r4[4]; 302356b2bdd1SGireesh Nagabhushana } iscsi; 302456b2bdd1SGireesh Nagabhushana } u; 302556b2bdd1SGireesh Nagabhushana __u8 r5[8]; 302656b2bdd1SGireesh Nagabhushana __be64 rsp_dmaaddr; 302756b2bdd1SGireesh Nagabhushana __be32 rsp_dmalen; 302856b2bdd1SGireesh Nagabhushana __be32 r6; 302956b2bdd1SGireesh Nagabhushana }; 303056b2bdd1SGireesh Nagabhushana 3031*3dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_OPCODE 24 3032*3dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_OPCODE 0xff 3033*3dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3034*3dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3035*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3036*3dde7c95SVishal Kulkarni 3037*3dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_IMMDLEN 0 3038*3dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3039*3dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3040*3dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3041*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3042*3dde7c95SVishal Kulkarni 3043*3dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_FLOWID 8 3044*3dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3045*3dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3046*3dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3047*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3048*3dde7c95SVishal Kulkarni 3049*3dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_LEN16 0 3050*3dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_LEN16 0xff 3051*3dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3052*3dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_LEN16(x) \ 3053*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3054*3dde7c95SVishal Kulkarni 3055*3dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_CP_EN 6 3056*3dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_CP_EN 0x3 3057*3dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3058*3dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3059*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3060*3dde7c95SVishal Kulkarni 3061*3dde7c95SVishal Kulkarni #define S_FW_SCSI_CMD_WR_CLASS 4 3062*3dde7c95SVishal Kulkarni #define M_FW_SCSI_CMD_WR_CLASS 0x3 3063*3dde7c95SVishal Kulkarni #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3064*3dde7c95SVishal Kulkarni #define G_FW_SCSI_CMD_WR_CLASS(x) \ 3065*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 306656b2bdd1SGireesh Nagabhushana 306756b2bdd1SGireesh Nagabhushana struct fw_scsi_abrt_cls_wr { 306856b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 306956b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 307056b2bdd1SGireesh Nagabhushana __be64 cookie; 307156b2bdd1SGireesh Nagabhushana __be16 iqid; 307256b2bdd1SGireesh Nagabhushana __u8 tmo_val; 307356b2bdd1SGireesh Nagabhushana __u8 sub_opcode_to_chk_all_io; 307456b2bdd1SGireesh Nagabhushana __u8 r3[4]; 307556b2bdd1SGireesh Nagabhushana __be64 t_cookie; 307656b2bdd1SGireesh Nagabhushana }; 307756b2bdd1SGireesh Nagabhushana 3078*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3079*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3080*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3081*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3082*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3083*3dde7c95SVishal Kulkarni 3084*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3085*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3086*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3087*3dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3088*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3089*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3090*3dde7c95SVishal Kulkarni 3091*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3092*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3093*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3094*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3095*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3096*3dde7c95SVishal Kulkarni 3097*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3098*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3099*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3100*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3101*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3102*3dde7c95SVishal Kulkarni 3103*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3104*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3105*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3106*3dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3107*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3108*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3109*3dde7c95SVishal Kulkarni M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3110*3dde7c95SVishal Kulkarni 3111*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3112*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3113*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3114*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3115*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3116*3dde7c95SVishal Kulkarni #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3117*3dde7c95SVishal Kulkarni 3118*3dde7c95SVishal Kulkarni #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3119*3dde7c95SVishal Kulkarni #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3120*3dde7c95SVishal Kulkarni #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3121*3dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3122*3dde7c95SVishal Kulkarni #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3123*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3124*3dde7c95SVishal Kulkarni M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3125*3dde7c95SVishal Kulkarni #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 312656b2bdd1SGireesh Nagabhushana V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 312756b2bdd1SGireesh Nagabhushana 312856b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_acc_wr { 312956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 313056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 313156b2bdd1SGireesh Nagabhushana __be64 cookie; 313256b2bdd1SGireesh Nagabhushana __be16 iqid; 313356b2bdd1SGireesh Nagabhushana __u8 r3; 313456b2bdd1SGireesh Nagabhushana __u8 use_burst_len; 313556b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_acc_priv { 313656b2bdd1SGireesh Nagabhushana struct fcoe_tgt_acc_priv { 313756b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 313856b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 313956b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 314056b2bdd1SGireesh Nagabhushana } fcoe; 314156b2bdd1SGireesh Nagabhushana struct iscsi_tgt_acc_priv { 314256b2bdd1SGireesh Nagabhushana __u8 r4[4]; 314356b2bdd1SGireesh Nagabhushana } iscsi; 314456b2bdd1SGireesh Nagabhushana } u; 314556b2bdd1SGireesh Nagabhushana __be32 burst_len; 314656b2bdd1SGireesh Nagabhushana __be32 rel_off; 314756b2bdd1SGireesh Nagabhushana __be64 r5; 314856b2bdd1SGireesh Nagabhushana __be32 r6; 314956b2bdd1SGireesh Nagabhushana __be32 tot_xfer_len; 315056b2bdd1SGireesh Nagabhushana }; 315156b2bdd1SGireesh Nagabhushana 3152*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3153*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3154*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3155*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3156*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3157*3dde7c95SVishal Kulkarni 3158*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3159*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3160*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3161*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3162*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3163*3dde7c95SVishal Kulkarni 3164*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3165*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3166*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3167*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3168*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3169*3dde7c95SVishal Kulkarni 3170*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3171*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3172*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3173*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3174*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3175*3dde7c95SVishal Kulkarni 3176*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3177*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3178*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3179*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3180*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3181*3dde7c95SVishal Kulkarni 3182*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3183*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3184*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3185*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3186*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 318756b2bdd1SGireesh Nagabhushana 318856b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_xmit_wr { 318956b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 319056b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 319156b2bdd1SGireesh Nagabhushana __be64 cookie; 319256b2bdd1SGireesh Nagabhushana __be16 iqid; 319356b2bdd1SGireesh Nagabhushana __u8 auto_rsp; 319456b2bdd1SGireesh Nagabhushana __u8 use_xfer_cnt; 319556b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_xmit_priv { 319656b2bdd1SGireesh Nagabhushana struct fcoe_tgt_xmit_priv { 319756b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 319856b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 319956b2bdd1SGireesh Nagabhushana __u8 r3_lo[2]; 320056b2bdd1SGireesh Nagabhushana } fcoe; 320156b2bdd1SGireesh Nagabhushana struct iscsi_tgt_xmit_priv { 320256b2bdd1SGireesh Nagabhushana __u8 r3[4]; 320356b2bdd1SGireesh Nagabhushana } iscsi; 320456b2bdd1SGireesh Nagabhushana } u; 320556b2bdd1SGireesh Nagabhushana __be32 xfer_cnt; 320656b2bdd1SGireesh Nagabhushana __be32 r4; 320756b2bdd1SGireesh Nagabhushana __be64 r5; 320856b2bdd1SGireesh Nagabhushana __be32 r6; 320956b2bdd1SGireesh Nagabhushana __be32 tot_xfer_len; 321056b2bdd1SGireesh Nagabhushana }; 321156b2bdd1SGireesh Nagabhushana 3212*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3213*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3214*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3215*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3216*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3217*3dde7c95SVishal Kulkarni 3218*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3219*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3220*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3221*3dde7c95SVishal Kulkarni ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3222*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3223*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3224*3dde7c95SVishal Kulkarni 3225*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3226*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3227*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3228*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3229*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3230*3dde7c95SVishal Kulkarni 3231*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3232*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3233*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3234*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3235*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3236*3dde7c95SVishal Kulkarni 3237*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3238*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3239*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3240*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3241*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3242*3dde7c95SVishal Kulkarni 3243*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3244*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3245*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3246*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3247*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 324856b2bdd1SGireesh Nagabhushana 324956b2bdd1SGireesh Nagabhushana struct fw_scsi_tgt_rsp_wr { 325056b2bdd1SGireesh Nagabhushana __be32 op_immdlen; 325156b2bdd1SGireesh Nagabhushana __be32 flowid_len16; 325256b2bdd1SGireesh Nagabhushana __be64 cookie; 325356b2bdd1SGireesh Nagabhushana __be16 iqid; 325456b2bdd1SGireesh Nagabhushana __u8 r3[2]; 325556b2bdd1SGireesh Nagabhushana union fw_scsi_tgt_rsp_priv { 325656b2bdd1SGireesh Nagabhushana struct fcoe_tgt_rsp_priv { 325756b2bdd1SGireesh Nagabhushana __u8 ctl_pri; 325856b2bdd1SGireesh Nagabhushana __u8 cp_en_class; 325956b2bdd1SGireesh Nagabhushana __u8 r4_lo[2]; 326056b2bdd1SGireesh Nagabhushana } fcoe; 326156b2bdd1SGireesh Nagabhushana struct iscsi_tgt_rsp_priv { 326256b2bdd1SGireesh Nagabhushana __u8 r4[4]; 326356b2bdd1SGireesh Nagabhushana } iscsi; 326456b2bdd1SGireesh Nagabhushana } u; 326556b2bdd1SGireesh Nagabhushana __u8 r5[8]; 326656b2bdd1SGireesh Nagabhushana }; 326756b2bdd1SGireesh Nagabhushana 3268*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3269*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3270*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3271*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3272*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3273*3dde7c95SVishal Kulkarni 3274*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3275*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3276*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3277*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3278*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3279*3dde7c95SVishal Kulkarni 3280*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3281*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3282*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3283*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3284*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3285*3dde7c95SVishal Kulkarni 3286*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3287*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3288*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3289*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3290*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3291*3dde7c95SVishal Kulkarni 3292*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3293*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3294*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3295*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3296*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3297*3dde7c95SVishal Kulkarni 3298*3dde7c95SVishal Kulkarni #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3299*3dde7c95SVishal Kulkarni #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3300*3dde7c95SVishal Kulkarni #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3301*3dde7c95SVishal Kulkarni #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3302*3dde7c95SVishal Kulkarni (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 330356b2bdd1SGireesh Nagabhushana 3304de483253SVishal Kulkarni struct fw_pofcoe_tcb_wr { 3305de483253SVishal Kulkarni __be32 op_compl; 3306de483253SVishal Kulkarni __be32 equiq_to_len16; 3307*3dde7c95SVishal Kulkarni __be32 r4; 3308*3dde7c95SVishal Kulkarni __be32 xfer_len; 3309de483253SVishal Kulkarni __be32 tid_to_port; 3310de483253SVishal Kulkarni __be16 x_id; 3311de483253SVishal Kulkarni __be16 vlan_id; 3312*3dde7c95SVishal Kulkarni __be64 cookie; 3313de483253SVishal Kulkarni __be32 s_id; 3314de483253SVishal Kulkarni __be32 d_id; 3315de483253SVishal Kulkarni __be32 tag; 3316*3dde7c95SVishal Kulkarni __be16 r6; 3317de483253SVishal Kulkarni __be16 iqid; 3318de483253SVishal Kulkarni }; 3319de483253SVishal Kulkarni 3320de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_TID 12 3321de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3322de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3323de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_TID(x) \ 3324de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3325de483253SVishal Kulkarni 3326*3dde7c95SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_ALLOC 4 3327de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3328de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3329de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3330de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3331de483253SVishal Kulkarni #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3332de483253SVishal Kulkarni 3333de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_FREE 3 3334de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_FREE 0x1 3335de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3336de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3337de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3338de483253SVishal Kulkarni #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3339de483253SVishal Kulkarni 3340de483253SVishal Kulkarni #define S_FW_POFCOE_TCB_WR_PORT 0 3341de483253SVishal Kulkarni #define M_FW_POFCOE_TCB_WR_PORT 0x7 3342de483253SVishal Kulkarni #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3343de483253SVishal Kulkarni #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3344de483253SVishal Kulkarni (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3345de483253SVishal Kulkarni 3346de483253SVishal Kulkarni struct fw_pofcoe_ulptx_wr { 3347de483253SVishal Kulkarni __be32 op_pkd; 3348de483253SVishal Kulkarni __be32 equiq_to_len16; 3349de483253SVishal Kulkarni __u64 cookie; 3350de483253SVishal Kulkarni }; 3351de483253SVishal Kulkarni 3352*3dde7c95SVishal Kulkarni /******************************************************************* 3353*3dde7c95SVishal Kulkarni * T10 DIF related definition 3354*3dde7c95SVishal Kulkarni *******************************************************************/ 3355*3dde7c95SVishal Kulkarni struct fw_tx_pi_header { 3356*3dde7c95SVishal Kulkarni __be16 op_to_inline; 3357*3dde7c95SVishal Kulkarni __u8 pi_interval_tag_type; 3358*3dde7c95SVishal Kulkarni __u8 num_pi; 3359*3dde7c95SVishal Kulkarni __be32 pi_start4_pi_end4; 3360*3dde7c95SVishal Kulkarni __u8 tag_gen_enabled_pkd; 3361*3dde7c95SVishal Kulkarni __u8 num_pi_dsg; 3362*3dde7c95SVishal Kulkarni __be16 app_tag; 3363*3dde7c95SVishal Kulkarni __be32 ref_tag; 3364*3dde7c95SVishal Kulkarni }; 3365*3dde7c95SVishal Kulkarni 3366*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_OP 8 3367*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_OP 0xff 3368*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3369*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_OP(x) \ 3370*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3371*3dde7c95SVishal Kulkarni 3372*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3373*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3374*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3375*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3376*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3377*3dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3378*3dde7c95SVishal Kulkarni 3379*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3380*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3381*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3382*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3383*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3384*3dde7c95SVishal Kulkarni 3385*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3386*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3387*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3388*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3389*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3390*3dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3391*3dde7c95SVishal Kulkarni 3392*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_VALIDATE 1 3393*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3394*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3395*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3396*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3397*3dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3398*3dde7c95SVishal Kulkarni 3399*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_INLINE 0 3400*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_INLINE 0x1 3401*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3402*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_INLINE(x) \ 3403*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3404*3dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3405*3dde7c95SVishal Kulkarni 3406*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3407*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3408*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3409*3dde7c95SVishal Kulkarni ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3410*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3411*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3412*3dde7c95SVishal Kulkarni #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3413*3dde7c95SVishal Kulkarni 3414*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3415*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3416*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3417*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3418*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3419*3dde7c95SVishal Kulkarni 3420*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_START4 22 3421*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3422*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3423*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3424*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3425*3dde7c95SVishal Kulkarni 3426*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_PI_END4 0 3427*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3428*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3429*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3430*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3431*3dde7c95SVishal Kulkarni 3432*3dde7c95SVishal Kulkarni #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3433*3dde7c95SVishal Kulkarni #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3434*3dde7c95SVishal Kulkarni #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3435*3dde7c95SVishal Kulkarni ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3436*3dde7c95SVishal Kulkarni #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3437*3dde7c95SVishal Kulkarni (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3438*3dde7c95SVishal Kulkarni M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3439*3dde7c95SVishal Kulkarni 3440*3dde7c95SVishal Kulkarni enum fw_pi_error_type { 3441*3dde7c95SVishal Kulkarni FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3442*3dde7c95SVishal Kulkarni }; 3443*3dde7c95SVishal Kulkarni 3444*3dde7c95SVishal Kulkarni struct fw_pi_error { 3445*3dde7c95SVishal Kulkarni __be32 err_type_pkd; 3446*3dde7c95SVishal Kulkarni __be32 flowid_len16; 3447*3dde7c95SVishal Kulkarni __be16 r2; 3448*3dde7c95SVishal Kulkarni __be16 app_tag; 3449*3dde7c95SVishal Kulkarni __be32 ref_tag; 3450*3dde7c95SVishal Kulkarni __be32 pisc[4]; 3451*3dde7c95SVishal Kulkarni }; 3452*3dde7c95SVishal Kulkarni 3453*3dde7c95SVishal Kulkarni #define S_FW_PI_ERROR_ERR_TYPE 24 3454*3dde7c95SVishal Kulkarni #define M_FW_PI_ERROR_ERR_TYPE 0xff 3455*3dde7c95SVishal Kulkarni #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3456*3dde7c95SVishal Kulkarni #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3457*3dde7c95SVishal Kulkarni (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3458*3dde7c95SVishal Kulkarni 3459*3dde7c95SVishal Kulkarni struct fw_tlstx_data_wr { 3460*3dde7c95SVishal Kulkarni __be32 op_to_immdlen; 3461*3dde7c95SVishal Kulkarni __be32 flowid_len16; 3462*3dde7c95SVishal Kulkarni __be32 plen; 3463*3dde7c95SVishal Kulkarni __be32 lsodisable_to_flags; 3464*3dde7c95SVishal Kulkarni __be32 r5; 3465*3dde7c95SVishal Kulkarni __be32 ctxloc_to_exp; 3466*3dde7c95SVishal Kulkarni __be16 mfs; 3467*3dde7c95SVishal Kulkarni __be16 adjustedplen_pkd; 3468*3dde7c95SVishal Kulkarni __be16 expinplenmax_pkd; 3469*3dde7c95SVishal Kulkarni __u8 pdusinplenmax_pkd; 3470*3dde7c95SVishal Kulkarni __u8 r10; 3471*3dde7c95SVishal Kulkarni }; 3472*3dde7c95SVishal Kulkarni 3473*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_OPCODE 24 3474*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3475*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3476*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3477*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3478*3dde7c95SVishal Kulkarni 3479*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_COMPL 21 3480*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3481*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3482*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3483*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3484*3dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3485*3dde7c95SVishal Kulkarni 3486*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3487*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3488*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3489*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3490*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3491*3dde7c95SVishal Kulkarni 3492*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_FLOWID 8 3493*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3494*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3495*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3496*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3497*3dde7c95SVishal Kulkarni 3498*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_LEN16 0 3499*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3500*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3501*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3502*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3503*3dde7c95SVishal Kulkarni 3504*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3505*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3506*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3507*3dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3508*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3509*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3510*3dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3511*3dde7c95SVishal Kulkarni 3512*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3513*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3514*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3515*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3516*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3517*3dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3518*3dde7c95SVishal Kulkarni 3519*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3520*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3521*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3522*3dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3523*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3524*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3525*3dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3526*3dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3527*3dde7c95SVishal Kulkarni 3528*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_FLAGS 0 3529*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3530*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3531*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3532*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3533*3dde7c95SVishal Kulkarni 3534*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3535*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3536*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3537*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3538*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3539*3dde7c95SVishal Kulkarni 3540*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3541*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3542*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3543*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3544*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3545*3dde7c95SVishal Kulkarni #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3546*3dde7c95SVishal Kulkarni 3547*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3548*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3549*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3550*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3551*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3552*3dde7c95SVishal Kulkarni 3553*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3554*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3555*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3556*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3557*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3558*3dde7c95SVishal Kulkarni 3559*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_EXP 0 3560*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3561*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3562*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3563*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3564*3dde7c95SVishal Kulkarni 3565*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3566*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3567*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3568*3dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3569*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3570*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3571*3dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3572*3dde7c95SVishal Kulkarni 3573*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3574*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3575*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3576*3dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3577*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3578*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3579*3dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3580*3dde7c95SVishal Kulkarni 3581*3dde7c95SVishal Kulkarni #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3582*3dde7c95SVishal Kulkarni #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3583*3dde7c95SVishal Kulkarni #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3584*3dde7c95SVishal Kulkarni ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3585*3dde7c95SVishal Kulkarni #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3586*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3587*3dde7c95SVishal Kulkarni M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3588*3dde7c95SVishal Kulkarni 3589*3dde7c95SVishal Kulkarni struct fw_tls_keyctx_tx_wr { 3590*3dde7c95SVishal Kulkarni __be32 op_to_compl; 3591*3dde7c95SVishal Kulkarni __be32 flowid_len16; 3592*3dde7c95SVishal Kulkarni union fw_key_ctx { 3593*3dde7c95SVishal Kulkarni struct fw_tx_keyctx_hdr { 3594*3dde7c95SVishal Kulkarni __u8 ctxlen; 3595*3dde7c95SVishal Kulkarni __u8 r2; 3596*3dde7c95SVishal Kulkarni __be16 dualck_to_txvalid; 3597*3dde7c95SVishal Kulkarni __u8 txsalt[4]; 3598*3dde7c95SVishal Kulkarni __be64 r5; 3599*3dde7c95SVishal Kulkarni } txhdr; 3600*3dde7c95SVishal Kulkarni struct fw_rx_keyctx_hdr { 3601*3dde7c95SVishal Kulkarni __u8 flitcnt_hmacctrl; 3602*3dde7c95SVishal Kulkarni __u8 protover_ciphmode; 3603*3dde7c95SVishal Kulkarni __u8 authmode_to_rxvalid; 3604*3dde7c95SVishal Kulkarni __u8 ivpresent_to_rxmk_size; 3605*3dde7c95SVishal Kulkarni __u8 rxsalt[4]; 3606*3dde7c95SVishal Kulkarni __be64 ivinsert_to_authinsrt; 3607*3dde7c95SVishal Kulkarni } rxhdr; 3608*3dde7c95SVishal Kulkarni struct fw_keyctx_clear { 3609*3dde7c95SVishal Kulkarni __be32 tx_key; 3610*3dde7c95SVishal Kulkarni __be32 rx_key; 3611*3dde7c95SVishal Kulkarni } kctx_clr; 3612*3dde7c95SVishal Kulkarni } u; 3613*3dde7c95SVishal Kulkarni struct keys { 3614*3dde7c95SVishal Kulkarni __u8 edkey[32]; 3615*3dde7c95SVishal Kulkarni __u8 ipad[64]; 3616*3dde7c95SVishal Kulkarni __u8 opad[64]; 3617*3dde7c95SVishal Kulkarni } keys; 3618*3dde7c95SVishal Kulkarni __u8 reneg_to_write_rx; 3619*3dde7c95SVishal Kulkarni __u8 protocol; 3620*3dde7c95SVishal Kulkarni __be16 mfs; 3621*3dde7c95SVishal Kulkarni __be32 ftid; 3622*3dde7c95SVishal Kulkarni }; 3623*3dde7c95SVishal Kulkarni 3624*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24 3625*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff 3626*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE) 3627*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \ 3628*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE) 3629*3dde7c95SVishal Kulkarni 3630*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23 3631*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1 3632*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3633*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \ 3634*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3635*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U) 3636*3dde7c95SVishal Kulkarni 3637*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22 3638*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1 3639*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH) 3640*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \ 3641*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH) 3642*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U) 3643*3dde7c95SVishal Kulkarni 3644*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_COMPL 21 3645*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1 3646*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL) 3647*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \ 3648*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL) 3649*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U) 3650*3dde7c95SVishal Kulkarni 3651*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8 3652*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff 3653*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID) 3654*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \ 3655*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID) 3656*3dde7c95SVishal Kulkarni 3657*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_LEN16 0 3658*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff 3659*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16) 3660*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \ 3661*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16) 3662*3dde7c95SVishal Kulkarni 3663*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12 3664*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1 3665*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK) 3666*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \ 3667*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK) 3668*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U) 3669*3dde7c95SVishal Kulkarni 3670*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11 3671*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1 3672*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3673*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3674*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3675*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \ 3676*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3677*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \ 3678*3dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U) 3679*3dde7c95SVishal Kulkarni 3680*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10 3681*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1 3682*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3683*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3684*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3685*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \ 3686*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3687*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \ 3688*3dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U) 3689*3dde7c95SVishal Kulkarni 3690*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6 3691*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf 3692*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3693*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3694*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3695*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \ 3696*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3697*3dde7c95SVishal Kulkarni 3698*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2 3699*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf 3700*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3701*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3702*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3703*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \ 3704*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3705*3dde7c95SVishal Kulkarni 3706*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0 3707*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1 3708*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3709*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID) 3710*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3711*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID) 3712*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U) 3713*3dde7c95SVishal Kulkarni 3714*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3 3715*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f 3716*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3717*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3718*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3719*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3720*3dde7c95SVishal Kulkarni 3721*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0 3722*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7 3723*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3724*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3725*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3726*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3727*3dde7c95SVishal Kulkarni 3728*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4 3729*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf 3730*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3731*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3732*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3733*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3734*3dde7c95SVishal Kulkarni 3735*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0 3736*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf 3737*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3738*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3739*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3740*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3741*3dde7c95SVishal Kulkarni 3742*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4 3743*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf 3744*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3745*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3746*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3747*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3748*3dde7c95SVishal Kulkarni 3749*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3 3750*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1 3751*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3752*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3753*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3754*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \ 3755*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3756*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \ 3757*3dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U) 3758*3dde7c95SVishal Kulkarni 3759*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1 3760*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3 3761*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3762*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3763*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3764*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \ 3765*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3766*3dde7c95SVishal Kulkarni 3767*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0 3768*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1 3769*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3770*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID) 3771*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3772*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID) 3773*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U) 3774*3dde7c95SVishal Kulkarni 3775*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7 3776*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1 3777*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3778*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3779*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3780*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \ 3781*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3782*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U) 3783*3dde7c95SVishal Kulkarni 3784*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6 3785*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1 3786*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3787*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3788*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3789*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \ 3790*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3791*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \ 3792*3dde7c95SVishal Kulkarni V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U) 3793*3dde7c95SVishal Kulkarni 3794*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3 3795*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7 3796*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3797*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3798*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3799*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \ 3800*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3801*3dde7c95SVishal Kulkarni 3802*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0 3803*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7 3804*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3805*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3806*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3807*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \ 3808*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3809*3dde7c95SVishal Kulkarni 3810*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55 3811*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL 3812*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3813*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3814*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3815*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3816*3dde7c95SVishal Kulkarni 3817*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47 3818*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL 3819*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3820*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3821*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3822*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \ 3823*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3824*3dde7c95SVishal Kulkarni 3825*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39 3826*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL 3827*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3828*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3829*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3830*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \ 3831*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3832*3dde7c95SVishal Kulkarni 3833*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30 3834*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL 3835*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3836*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3837*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3838*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \ 3839*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3840*3dde7c95SVishal Kulkarni 3841*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23 3842*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f 3843*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3844*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3845*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3846*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \ 3847*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3848*3dde7c95SVishal Kulkarni 3849*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14 3850*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff 3851*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3852*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3853*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3854*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \ 3855*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3856*3dde7c95SVishal Kulkarni 3857*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7 3858*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f 3859*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3860*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3861*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3862*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \ 3863*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3864*3dde7c95SVishal Kulkarni 3865*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0 3866*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f 3867*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3868*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3869*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3870*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \ 3871*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3872*3dde7c95SVishal Kulkarni 3873*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_RENEG 4 3874*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1 3875*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG) 3876*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \ 3877*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG) 3878*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U) 3879*3dde7c95SVishal Kulkarni 3880*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3 3881*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1 3882*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3883*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3884*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3885*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \ 3886*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3887*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U) 3888*3dde7c95SVishal Kulkarni 3889*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2 3890*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1 3891*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3892*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3893*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3894*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \ 3895*3dde7c95SVishal Kulkarni M_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3896*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U) 3897*3dde7c95SVishal Kulkarni 3898*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1 3899*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1 3900*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3901*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3902*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3903*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3904*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U) 3905*3dde7c95SVishal Kulkarni 3906*3dde7c95SVishal Kulkarni #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0 3907*3dde7c95SVishal Kulkarni #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1 3908*3dde7c95SVishal Kulkarni #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3909*3dde7c95SVishal Kulkarni ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3910*3dde7c95SVishal Kulkarni #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3911*3dde7c95SVishal Kulkarni (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3912*3dde7c95SVishal Kulkarni #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U) 3913*3dde7c95SVishal Kulkarni 3914*3dde7c95SVishal Kulkarni struct fw_crypto_lookaside_wr { 3915*3dde7c95SVishal Kulkarni __be32 op_to_cctx_size; 3916*3dde7c95SVishal Kulkarni __be32 len16_pkd; 3917*3dde7c95SVishal Kulkarni __be32 session_id; 3918*3dde7c95SVishal Kulkarni __be32 rx_chid_to_rx_q_id; 3919*3dde7c95SVishal Kulkarni __be32 key_addr; 3920*3dde7c95SVishal Kulkarni __be32 pld_size_hash_size; 3921*3dde7c95SVishal Kulkarni __be64 cookie; 3922*3dde7c95SVishal Kulkarni }; 3923*3dde7c95SVishal Kulkarni 3924*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3925*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3926*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3927*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3928*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3929*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3930*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3931*3dde7c95SVishal Kulkarni 3932*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3933*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3934*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3935*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3936*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3937*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3938*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3939*3dde7c95SVishal Kulkarni #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3940*3dde7c95SVishal Kulkarni 3941*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3942*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3943*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3944*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3945*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3946*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3947*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3948*3dde7c95SVishal Kulkarni 3949*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3950*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3951*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3952*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3953*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3954*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 3955*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3956*3dde7c95SVishal Kulkarni 3957*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 3958*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 3959*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3960*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3961*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3962*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 3963*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3964*3dde7c95SVishal Kulkarni 3965*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 3966*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 3967*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3968*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3969*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3970*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 3971*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3972*3dde7c95SVishal Kulkarni 3973*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 3974*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 3975*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3976*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3977*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3978*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 3979*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3980*3dde7c95SVishal Kulkarni 3981*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 3982*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 3983*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3984*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 3985*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3986*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 3987*3dde7c95SVishal Kulkarni 3988*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 3989*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 3990*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 3991*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 3992*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 3993*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 3994*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 3995*3dde7c95SVishal Kulkarni 3996*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 3997*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 3998*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 3999*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4000*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4001*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4002*3dde7c95SVishal Kulkarni 4003*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4004*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4005*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4006*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4007*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4008*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4009*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4010*3dde7c95SVishal Kulkarni 4011*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4012*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4013*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4014*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4015*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4016*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4017*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4018*3dde7c95SVishal Kulkarni 4019*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4020*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4021*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4022*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4023*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4024*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4025*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4026*3dde7c95SVishal Kulkarni 4027*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4028*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4029*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4030*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4031*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4032*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4033*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4034*3dde7c95SVishal Kulkarni 4035*3dde7c95SVishal Kulkarni #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4036*3dde7c95SVishal Kulkarni #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4037*3dde7c95SVishal Kulkarni #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4038*3dde7c95SVishal Kulkarni ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4039*3dde7c95SVishal Kulkarni #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4040*3dde7c95SVishal Kulkarni (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4041*3dde7c95SVishal Kulkarni M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4042*3dde7c95SVishal Kulkarni 4043*3dde7c95SVishal Kulkarni /****************************************************************************** 4044*3dde7c95SVishal Kulkarni * C O M M A N D s 4045*3dde7c95SVishal Kulkarni *********************/ 404656b2bdd1SGireesh Nagabhushana 404756b2bdd1SGireesh Nagabhushana /* 404856b2bdd1SGireesh Nagabhushana * The maximum length of time, in miliseconds, that we expect any firmware 404956b2bdd1SGireesh Nagabhushana * command to take to execute and return a reply to the host. The RESET 405056b2bdd1SGireesh Nagabhushana * and INITIALIZE commands can take a fair amount of time to execute but 405156b2bdd1SGireesh Nagabhushana * most execute in far less time than this maximum. This constant is used 405256b2bdd1SGireesh Nagabhushana * by host software to determine how long to wait for a firmware command 405356b2bdd1SGireesh Nagabhushana * reply before declaring the firmware as dead/unreachable ... 405456b2bdd1SGireesh Nagabhushana */ 4055*3dde7c95SVishal Kulkarni #define FW_CMD_MAX_TIMEOUT 10000 405656b2bdd1SGireesh Nagabhushana 405756b2bdd1SGireesh Nagabhushana /* 405856b2bdd1SGireesh Nagabhushana * If a host driver does a HELLO and discovers that there's already a MASTER 405956b2bdd1SGireesh Nagabhushana * selected, we may have to wait for that MASTER to finish issuing RESET, 406056b2bdd1SGireesh Nagabhushana * configuration and INITIALIZE commands. Also, there's a possibility that 406156b2bdd1SGireesh Nagabhushana * our own HELLO may get lost if it happens right as the MASTER is issuign a 406256b2bdd1SGireesh Nagabhushana * RESET command, so we need to be willing to make a few retries of our HELLO. 406356b2bdd1SGireesh Nagabhushana */ 4064*3dde7c95SVishal Kulkarni #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4065*3dde7c95SVishal Kulkarni #define FW_CMD_HELLO_RETRIES 3 406656b2bdd1SGireesh Nagabhushana 406756b2bdd1SGireesh Nagabhushana enum fw_cmd_opcodes { 4068*3dde7c95SVishal Kulkarni FW_LDST_CMD = 0x01, 4069*3dde7c95SVishal Kulkarni FW_RESET_CMD = 0x03, 4070*3dde7c95SVishal Kulkarni FW_HELLO_CMD = 0x04, 4071*3dde7c95SVishal Kulkarni FW_BYE_CMD = 0x05, 4072*3dde7c95SVishal Kulkarni FW_INITIALIZE_CMD = 0x06, 4073*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_CMD = 0x07, 4074*3dde7c95SVishal Kulkarni FW_PARAMS_CMD = 0x08, 4075*3dde7c95SVishal Kulkarni FW_PFVF_CMD = 0x09, 4076*3dde7c95SVishal Kulkarni FW_IQ_CMD = 0x10, 4077*3dde7c95SVishal Kulkarni FW_EQ_MNGT_CMD = 0x11, 4078*3dde7c95SVishal Kulkarni FW_EQ_ETH_CMD = 0x12, 4079*3dde7c95SVishal Kulkarni FW_EQ_CTRL_CMD = 0x13, 4080*3dde7c95SVishal Kulkarni FW_EQ_OFLD_CMD = 0x21, 4081*3dde7c95SVishal Kulkarni FW_VI_CMD = 0x14, 4082*3dde7c95SVishal Kulkarni FW_VI_MAC_CMD = 0x15, 4083*3dde7c95SVishal Kulkarni FW_VI_RXMODE_CMD = 0x16, 4084*3dde7c95SVishal Kulkarni FW_VI_ENABLE_CMD = 0x17, 4085*3dde7c95SVishal Kulkarni FW_VI_STATS_CMD = 0x1a, 4086*3dde7c95SVishal Kulkarni FW_ACL_MAC_CMD = 0x18, 4087*3dde7c95SVishal Kulkarni FW_ACL_VLAN_CMD = 0x19, 4088*3dde7c95SVishal Kulkarni FW_PORT_CMD = 0x1b, 4089*3dde7c95SVishal Kulkarni FW_PORT_STATS_CMD = 0x1c, 4090*3dde7c95SVishal Kulkarni FW_PORT_LB_STATS_CMD = 0x1d, 4091*3dde7c95SVishal Kulkarni FW_PORT_TRACE_CMD = 0x1e, 4092*3dde7c95SVishal Kulkarni FW_PORT_TRACE_MMAP_CMD = 0x1f, 4093*3dde7c95SVishal Kulkarni FW_RSS_IND_TBL_CMD = 0x20, 4094*3dde7c95SVishal Kulkarni FW_RSS_GLB_CONFIG_CMD = 0x22, 4095*3dde7c95SVishal Kulkarni FW_RSS_VI_CONFIG_CMD = 0x23, 4096*3dde7c95SVishal Kulkarni FW_SCHED_CMD = 0x24, 4097*3dde7c95SVishal Kulkarni FW_DEVLOG_CMD = 0x25, 4098*3dde7c95SVishal Kulkarni FW_WATCHDOG_CMD = 0x27, 4099*3dde7c95SVishal Kulkarni FW_CLIP_CMD = 0x28, 4100*3dde7c95SVishal Kulkarni FW_CHNET_IFACE_CMD = 0x26, 4101*3dde7c95SVishal Kulkarni FW_FCOE_RES_INFO_CMD = 0x31, 4102*3dde7c95SVishal Kulkarni FW_FCOE_LINK_CMD = 0x32, 4103*3dde7c95SVishal Kulkarni FW_FCOE_VNP_CMD = 0x33, 4104*3dde7c95SVishal Kulkarni FW_FCOE_SPARAMS_CMD = 0x35, 4105*3dde7c95SVishal Kulkarni FW_FCOE_STATS_CMD = 0x37, 4106*3dde7c95SVishal Kulkarni FW_FCOE_FCF_CMD = 0x38, 4107*3dde7c95SVishal Kulkarni FW_DCB_IEEE_CMD = 0x3a, 4108*3dde7c95SVishal Kulkarni FW_DIAG_CMD = 0x3d, 4109*3dde7c95SVishal Kulkarni FW_PTP_CMD = 0x3e, 4110*3dde7c95SVishal Kulkarni FW_LASTC2E_CMD = 0x40, 4111*3dde7c95SVishal Kulkarni FW_ERROR_CMD = 0x80, 4112*3dde7c95SVishal Kulkarni FW_DEBUG_CMD = 0x81, 411356b2bdd1SGireesh Nagabhushana }; 411456b2bdd1SGireesh Nagabhushana 411556b2bdd1SGireesh Nagabhushana enum fw_cmd_cap { 4116*3dde7c95SVishal Kulkarni FW_CMD_CAP_PF = 0x01, 4117*3dde7c95SVishal Kulkarni FW_CMD_CAP_DMAQ = 0x02, 4118*3dde7c95SVishal Kulkarni FW_CMD_CAP_PORT = 0x04, 4119*3dde7c95SVishal Kulkarni FW_CMD_CAP_PORTPROMISC = 0x08, 4120*3dde7c95SVishal Kulkarni FW_CMD_CAP_PORTSTATS = 0x10, 4121*3dde7c95SVishal Kulkarni FW_CMD_CAP_VF = 0x80, 412256b2bdd1SGireesh Nagabhushana }; 412356b2bdd1SGireesh Nagabhushana 412456b2bdd1SGireesh Nagabhushana /* 412556b2bdd1SGireesh Nagabhushana * Generic command header flit0 412656b2bdd1SGireesh Nagabhushana */ 412756b2bdd1SGireesh Nagabhushana struct fw_cmd_hdr { 412856b2bdd1SGireesh Nagabhushana __be32 hi; 412956b2bdd1SGireesh Nagabhushana __be32 lo; 413056b2bdd1SGireesh Nagabhushana }; 413156b2bdd1SGireesh Nagabhushana 4132*3dde7c95SVishal Kulkarni #define S_FW_CMD_OP 24 4133*3dde7c95SVishal Kulkarni #define M_FW_CMD_OP 0xff 4134*3dde7c95SVishal Kulkarni #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4135*3dde7c95SVishal Kulkarni #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4136*3dde7c95SVishal Kulkarni 4137*3dde7c95SVishal Kulkarni #define S_FW_CMD_REQUEST 23 4138*3dde7c95SVishal Kulkarni #define M_FW_CMD_REQUEST 0x1 4139*3dde7c95SVishal Kulkarni #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4140*3dde7c95SVishal Kulkarni #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4141*3dde7c95SVishal Kulkarni #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4142*3dde7c95SVishal Kulkarni 4143*3dde7c95SVishal Kulkarni #define S_FW_CMD_READ 22 4144*3dde7c95SVishal Kulkarni #define M_FW_CMD_READ 0x1 4145*3dde7c95SVishal Kulkarni #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4146*3dde7c95SVishal Kulkarni #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4147*3dde7c95SVishal Kulkarni #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4148*3dde7c95SVishal Kulkarni 4149*3dde7c95SVishal Kulkarni #define S_FW_CMD_WRITE 21 4150*3dde7c95SVishal Kulkarni #define M_FW_CMD_WRITE 0x1 4151*3dde7c95SVishal Kulkarni #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4152*3dde7c95SVishal Kulkarni #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4153*3dde7c95SVishal Kulkarni #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4154*3dde7c95SVishal Kulkarni 4155*3dde7c95SVishal Kulkarni #define S_FW_CMD_EXEC 20 4156*3dde7c95SVishal Kulkarni #define M_FW_CMD_EXEC 0x1 4157*3dde7c95SVishal Kulkarni #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4158*3dde7c95SVishal Kulkarni #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4159*3dde7c95SVishal Kulkarni #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4160*3dde7c95SVishal Kulkarni 4161*3dde7c95SVishal Kulkarni #define S_FW_CMD_RAMASK 20 4162*3dde7c95SVishal Kulkarni #define M_FW_CMD_RAMASK 0xf 4163*3dde7c95SVishal Kulkarni #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4164*3dde7c95SVishal Kulkarni #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4165*3dde7c95SVishal Kulkarni 4166*3dde7c95SVishal Kulkarni #define S_FW_CMD_RETVAL 8 4167*3dde7c95SVishal Kulkarni #define M_FW_CMD_RETVAL 0xff 4168*3dde7c95SVishal Kulkarni #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4169*3dde7c95SVishal Kulkarni #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4170*3dde7c95SVishal Kulkarni 4171*3dde7c95SVishal Kulkarni #define S_FW_CMD_LEN16 0 4172*3dde7c95SVishal Kulkarni #define M_FW_CMD_LEN16 0xff 4173*3dde7c95SVishal Kulkarni #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4174*3dde7c95SVishal Kulkarni #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4175*3dde7c95SVishal Kulkarni 4176*3dde7c95SVishal Kulkarni #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 417756b2bdd1SGireesh Nagabhushana 417856b2bdd1SGireesh Nagabhushana /* 417956b2bdd1SGireesh Nagabhushana * address spaces 418056b2bdd1SGireesh Nagabhushana */ 418156b2bdd1SGireesh Nagabhushana enum fw_ldst_addrspc { 418256b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 418356b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 418456b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 418556b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 418656b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4187*3dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_TP_PIO = 0x0010, 418856b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4189*3dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4190*3dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_MDIO = 0x0018, 4191*3dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_MPS = 0x0020, 4192*3dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_FUNC = 0x0028, 419356b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4194de483253SVishal Kulkarni FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 419556b2bdd1SGireesh Nagabhushana FW_LDST_ADDRSPC_LE = 0x0030, 4196de483253SVishal Kulkarni FW_LDST_ADDRSPC_I2C = 0x0038, 4197de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4198de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4199de483253SVishal Kulkarni FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4200*3dde7c95SVishal Kulkarni FW_LDST_ADDRSPC_CIM_Q = 0x0048, 420156b2bdd1SGireesh Nagabhushana }; 420256b2bdd1SGireesh Nagabhushana 420356b2bdd1SGireesh Nagabhushana /* 420456b2bdd1SGireesh Nagabhushana * MDIO VSC8634 register access control field 420556b2bdd1SGireesh Nagabhushana */ 420656b2bdd1SGireesh Nagabhushana enum fw_ldst_mdio_vsc8634_aid { 420756b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_STANDARD, 420856b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_EXTENDED, 420956b2bdd1SGireesh Nagabhushana FW_LDST_MDIO_VS_GPIO 421056b2bdd1SGireesh Nagabhushana }; 421156b2bdd1SGireesh Nagabhushana 421256b2bdd1SGireesh Nagabhushana enum fw_ldst_mps_fid { 421356b2bdd1SGireesh Nagabhushana FW_LDST_MPS_ATRB, 421456b2bdd1SGireesh Nagabhushana FW_LDST_MPS_RPLC 421556b2bdd1SGireesh Nagabhushana }; 421656b2bdd1SGireesh Nagabhushana 421756b2bdd1SGireesh Nagabhushana enum fw_ldst_func_access_ctl { 421856b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_ACC_CTL_VIID, 421956b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_ACC_CTL_FID 422056b2bdd1SGireesh Nagabhushana }; 422156b2bdd1SGireesh Nagabhushana 422256b2bdd1SGireesh Nagabhushana enum fw_ldst_func_mod_index { 422356b2bdd1SGireesh Nagabhushana FW_LDST_FUNC_MPS 422456b2bdd1SGireesh Nagabhushana }; 422556b2bdd1SGireesh Nagabhushana 422656b2bdd1SGireesh Nagabhushana struct fw_ldst_cmd { 422756b2bdd1SGireesh Nagabhushana __be32 op_to_addrspace; 422856b2bdd1SGireesh Nagabhushana __be32 cycles_to_len16; 422956b2bdd1SGireesh Nagabhushana union fw_ldst { 423056b2bdd1SGireesh Nagabhushana struct fw_ldst_addrval { 423156b2bdd1SGireesh Nagabhushana __be32 addr; 423256b2bdd1SGireesh Nagabhushana __be32 val; 423356b2bdd1SGireesh Nagabhushana } addrval; 423456b2bdd1SGireesh Nagabhushana struct fw_ldst_idctxt { 423556b2bdd1SGireesh Nagabhushana __be32 physid; 423656b2bdd1SGireesh Nagabhushana __be32 msg_ctxtflush; 423756b2bdd1SGireesh Nagabhushana __be32 ctxt_data7; 423856b2bdd1SGireesh Nagabhushana __be32 ctxt_data6; 423956b2bdd1SGireesh Nagabhushana __be32 ctxt_data5; 424056b2bdd1SGireesh Nagabhushana __be32 ctxt_data4; 424156b2bdd1SGireesh Nagabhushana __be32 ctxt_data3; 424256b2bdd1SGireesh Nagabhushana __be32 ctxt_data2; 424356b2bdd1SGireesh Nagabhushana __be32 ctxt_data1; 424456b2bdd1SGireesh Nagabhushana __be32 ctxt_data0; 424556b2bdd1SGireesh Nagabhushana } idctxt; 424656b2bdd1SGireesh Nagabhushana struct fw_ldst_mdio { 424756b2bdd1SGireesh Nagabhushana __be16 paddr_mmd; 424856b2bdd1SGireesh Nagabhushana __be16 raddr; 424956b2bdd1SGireesh Nagabhushana __be16 vctl; 425056b2bdd1SGireesh Nagabhushana __be16 rval; 425156b2bdd1SGireesh Nagabhushana } mdio; 4252*3dde7c95SVishal Kulkarni struct fw_ldst_cim_rq { 4253*3dde7c95SVishal Kulkarni __u8 req_first64[8]; 4254*3dde7c95SVishal Kulkarni __u8 req_second64[8]; 4255*3dde7c95SVishal Kulkarni __u8 resp_first64[8]; 4256*3dde7c95SVishal Kulkarni __u8 resp_second64[8]; 4257*3dde7c95SVishal Kulkarni __be32 r3[2]; 4258*3dde7c95SVishal Kulkarni } cim_rq; 4259*3dde7c95SVishal Kulkarni union fw_ldst_mps { 4260*3dde7c95SVishal Kulkarni struct fw_ldst_mps_rplc { 4261*3dde7c95SVishal Kulkarni __be16 fid_idx; 4262*3dde7c95SVishal Kulkarni __be16 rplcpf_pkd; 4263*3dde7c95SVishal Kulkarni __be32 rplc255_224; 4264*3dde7c95SVishal Kulkarni __be32 rplc223_192; 4265*3dde7c95SVishal Kulkarni __be32 rplc191_160; 4266*3dde7c95SVishal Kulkarni __be32 rplc159_128; 4267*3dde7c95SVishal Kulkarni __be32 rplc127_96; 4268*3dde7c95SVishal Kulkarni __be32 rplc95_64; 4269*3dde7c95SVishal Kulkarni __be32 rplc63_32; 4270*3dde7c95SVishal Kulkarni __be32 rplc31_0; 4271*3dde7c95SVishal Kulkarni } rplc; 4272*3dde7c95SVishal Kulkarni struct fw_ldst_mps_atrb { 4273*3dde7c95SVishal Kulkarni __be16 fid_mpsid; 4274*3dde7c95SVishal Kulkarni __be16 r2[3]; 4275*3dde7c95SVishal Kulkarni __be32 r3[2]; 4276*3dde7c95SVishal Kulkarni __be32 r4; 4277*3dde7c95SVishal Kulkarni __be32 atrb; 4278*3dde7c95SVishal Kulkarni __be16 vlan[16]; 4279*3dde7c95SVishal Kulkarni } atrb; 428056b2bdd1SGireesh Nagabhushana } mps; 428156b2bdd1SGireesh Nagabhushana struct fw_ldst_func { 428256b2bdd1SGireesh Nagabhushana __u8 access_ctl; 428356b2bdd1SGireesh Nagabhushana __u8 mod_index; 428456b2bdd1SGireesh Nagabhushana __be16 ctl_id; 428556b2bdd1SGireesh Nagabhushana __be32 offset; 428656b2bdd1SGireesh Nagabhushana __be64 data0; 428756b2bdd1SGireesh Nagabhushana __be64 data1; 428856b2bdd1SGireesh Nagabhushana } func; 428956b2bdd1SGireesh Nagabhushana struct fw_ldst_pcie { 429056b2bdd1SGireesh Nagabhushana __u8 ctrl_to_fn; 429156b2bdd1SGireesh Nagabhushana __u8 bnum; 429256b2bdd1SGireesh Nagabhushana __u8 r; 429356b2bdd1SGireesh Nagabhushana __u8 ext_r; 429456b2bdd1SGireesh Nagabhushana __u8 select_naccess; 429556b2bdd1SGireesh Nagabhushana __u8 pcie_fn; 429656b2bdd1SGireesh Nagabhushana __be16 nset_pkd; 429756b2bdd1SGireesh Nagabhushana __be32 data[12]; 429856b2bdd1SGireesh Nagabhushana } pcie; 4299de483253SVishal Kulkarni struct fw_ldst_i2c_deprecated { 430056b2bdd1SGireesh Nagabhushana __u8 pid_pkd; 430156b2bdd1SGireesh Nagabhushana __u8 base; 430256b2bdd1SGireesh Nagabhushana __u8 boffset; 430356b2bdd1SGireesh Nagabhushana __u8 data; 430456b2bdd1SGireesh Nagabhushana __be32 r9; 4305de483253SVishal Kulkarni } i2c_deprecated; 4306de483253SVishal Kulkarni struct fw_ldst_i2c { 4307de483253SVishal Kulkarni __u8 pid; 4308de483253SVishal Kulkarni __u8 did; 4309de483253SVishal Kulkarni __u8 boffset; 4310de483253SVishal Kulkarni __u8 blen; 4311de483253SVishal Kulkarni __be32 r9; 4312de483253SVishal Kulkarni __u8 data[48]; 4313*3dde7c95SVishal Kulkarni } i2c; 431456b2bdd1SGireesh Nagabhushana struct fw_ldst_le { 4315de483253SVishal Kulkarni __be32 index; 4316de483253SVishal Kulkarni __be32 r9; 4317de483253SVishal Kulkarni __u8 val[33]; 4318de483253SVishal Kulkarni __u8 r11[7]; 431956b2bdd1SGireesh Nagabhushana } le; 432056b2bdd1SGireesh Nagabhushana } u; 432156b2bdd1SGireesh Nagabhushana }; 432256b2bdd1SGireesh Nagabhushana 4323*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_ADDRSPACE 0 4324*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_ADDRSPACE 0xff 4325*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4326*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4327*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4328*3dde7c95SVishal Kulkarni 4329*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_CYCLES 16 4330*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_CYCLES 0xffff 4331*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4332*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_CYCLES(x) \ 4333*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4334*3dde7c95SVishal Kulkarni 4335*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_MSG 31 4336*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_MSG 0x1 4337*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4338*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_MSG(x) \ 4339*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4340*3dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4341*3dde7c95SVishal Kulkarni 4342*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_CTXTFLUSH 30 4343*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4344*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4345*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4346*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4347*3dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4348*3dde7c95SVishal Kulkarni 4349*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_PADDR 8 4350*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_PADDR 0x1f 4351*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4352*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_PADDR(x) \ 4353*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4354*3dde7c95SVishal Kulkarni 4355*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_MMD 0 4356*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_MMD 0x1f 4357*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4358*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_MMD(x) \ 4359*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4360*3dde7c95SVishal Kulkarni 4361*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_FID 15 4362*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_FID 0x1 4363*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4364*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_FID(x) \ 4365*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4366*3dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4367*3dde7c95SVishal Kulkarni 4368*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_IDX 0 4369*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_IDX 0x7fff 4370*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4371*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_IDX(x) \ 4372*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4373*3dde7c95SVishal Kulkarni 4374*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_RPLCPF 0 4375*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_RPLCPF 0xff 4376*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4377*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_RPLCPF(x) \ 4378*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4379*3dde7c95SVishal Kulkarni 4380*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_MPSID 0 4381*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_MPSID 0x7fff 4382*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4383*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_MPSID(x) \ 4384*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4385*3dde7c95SVishal Kulkarni 4386*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_CTRL 7 4387*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_CTRL 0x1 4388*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4389*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_CTRL(x) \ 4390*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4391*3dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4392*3dde7c95SVishal Kulkarni 4393*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_LC 4 4394*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_LC 0x1 4395*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4396*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_LC(x) \ 4397*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4398*3dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4399*3dde7c95SVishal Kulkarni 4400*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_AI 3 4401*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_AI 0x1 4402*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4403*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_AI(x) \ 4404*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4405*3dde7c95SVishal Kulkarni #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4406*3dde7c95SVishal Kulkarni 4407*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_FN 0 4408*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_FN 0x7 4409*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4410*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_FN(x) \ 4411*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4412*3dde7c95SVishal Kulkarni 4413*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_SELECT 4 4414*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_SELECT 0xf 4415*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4416*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_SELECT(x) \ 4417*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4418*3dde7c95SVishal Kulkarni 4419*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_NACCESS 0 4420*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_NACCESS 0xf 4421*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4422*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_NACCESS(x) \ 4423*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4424*3dde7c95SVishal Kulkarni 4425*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_NSET 14 4426*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_NSET 0x3 4427*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4428*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_NSET(x) \ 4429*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4430*3dde7c95SVishal Kulkarni 4431*3dde7c95SVishal Kulkarni #define S_FW_LDST_CMD_PID 6 4432*3dde7c95SVishal Kulkarni #define M_FW_LDST_CMD_PID 0x3 4433*3dde7c95SVishal Kulkarni #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4434*3dde7c95SVishal Kulkarni #define G_FW_LDST_CMD_PID(x) \ 4435*3dde7c95SVishal Kulkarni (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 443656b2bdd1SGireesh Nagabhushana 443756b2bdd1SGireesh Nagabhushana struct fw_reset_cmd { 443856b2bdd1SGireesh Nagabhushana __be32 op_to_write; 443956b2bdd1SGireesh Nagabhushana __be32 retval_len16; 444056b2bdd1SGireesh Nagabhushana __be32 val; 444156b2bdd1SGireesh Nagabhushana __be32 halt_pkd; 444256b2bdd1SGireesh Nagabhushana }; 444356b2bdd1SGireesh Nagabhushana 4444*3dde7c95SVishal Kulkarni #define S_FW_RESET_CMD_HALT 31 4445*3dde7c95SVishal Kulkarni #define M_FW_RESET_CMD_HALT 0x1 4446*3dde7c95SVishal Kulkarni #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4447*3dde7c95SVishal Kulkarni #define G_FW_RESET_CMD_HALT(x) \ 4448*3dde7c95SVishal Kulkarni (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4449*3dde7c95SVishal Kulkarni #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 445056b2bdd1SGireesh Nagabhushana 445156b2bdd1SGireesh Nagabhushana enum { 445256b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_OS = 0, 445356b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_PREOS0 = 1, 445456b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_PREOS1 = 2, 445556b2bdd1SGireesh Nagabhushana FW_HELLO_CMD_STAGE_POSTOS = 3, 445656b2bdd1SGireesh Nagabhushana }; 445756b2bdd1SGireesh Nagabhushana 445856b2bdd1SGireesh Nagabhushana struct fw_hello_cmd { 445956b2bdd1SGireesh Nagabhushana __be32 op_to_write; 446056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 446156b2bdd1SGireesh Nagabhushana __be32 err_to_clearinit; 446256b2bdd1SGireesh Nagabhushana __be32 fwrev; 446356b2bdd1SGireesh Nagabhushana }; 446456b2bdd1SGireesh Nagabhushana 4465*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_ERR 31 4466*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_ERR 0x1 4467*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4468*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_ERR(x) \ 4469*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4470*3dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4471*3dde7c95SVishal Kulkarni 4472*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_INIT 30 4473*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_INIT 0x1 4474*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4475*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_INIT(x) \ 4476*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4477*3dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4478*3dde7c95SVishal Kulkarni 4479*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MASTERDIS 29 4480*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MASTERDIS 0x1 4481*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4482*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4483*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4484*3dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4485*3dde7c95SVishal Kulkarni 4486*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MASTERFORCE 28 4487*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4488*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4489*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4490*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4491*3dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4492*3dde7c95SVishal Kulkarni 4493*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MBMASTER 24 4494*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MBMASTER 0xf 4495*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4496*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MBMASTER(x) \ 4497*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4498*3dde7c95SVishal Kulkarni 4499*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4500*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4501*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4502*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4503*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4504*3dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4505*3dde7c95SVishal Kulkarni 4506*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_MBASYNCNOT 20 4507*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4508*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4509*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4510*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4511*3dde7c95SVishal Kulkarni 4512*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_STAGE 17 4513*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_STAGE 0x7 4514*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4515*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_STAGE(x) \ 4516*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4517*3dde7c95SVishal Kulkarni 4518*3dde7c95SVishal Kulkarni #define S_FW_HELLO_CMD_CLEARINIT 16 4519*3dde7c95SVishal Kulkarni #define M_FW_HELLO_CMD_CLEARINIT 0x1 4520*3dde7c95SVishal Kulkarni #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4521*3dde7c95SVishal Kulkarni #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4522*3dde7c95SVishal Kulkarni (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4523*3dde7c95SVishal Kulkarni #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 452456b2bdd1SGireesh Nagabhushana 452556b2bdd1SGireesh Nagabhushana struct fw_bye_cmd { 452656b2bdd1SGireesh Nagabhushana __be32 op_to_write; 452756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 452856b2bdd1SGireesh Nagabhushana __be64 r3; 452956b2bdd1SGireesh Nagabhushana }; 453056b2bdd1SGireesh Nagabhushana 453156b2bdd1SGireesh Nagabhushana struct fw_initialize_cmd { 453256b2bdd1SGireesh Nagabhushana __be32 op_to_write; 453356b2bdd1SGireesh Nagabhushana __be32 retval_len16; 453456b2bdd1SGireesh Nagabhushana __be64 r3; 453556b2bdd1SGireesh Nagabhushana }; 453656b2bdd1SGireesh Nagabhushana 453756b2bdd1SGireesh Nagabhushana enum fw_caps_config_hm { 453856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 453956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PL = 0x00000002, 454056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SGE = 0x00000004, 454156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_CIM = 0x00000008, 454256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 454356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_TP = 0x00000020, 454456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 454556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 454656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 454756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MC = 0x00000200, 454856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_LE = 0x00000400, 454956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MPS = 0x00000800, 455056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 455156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 455256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 455356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MI = 0x00008000, 455456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 455556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 455656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SMB = 0x00040000, 455756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_MA = 0x00080000, 455856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 455956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_PMU = 0x00200000, 456056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_UART = 0x00400000, 456156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_HM_SF = 0x00800000, 456256b2bdd1SGireesh Nagabhushana }; 456356b2bdd1SGireesh Nagabhushana 456456b2bdd1SGireesh Nagabhushana /* 456556b2bdd1SGireesh Nagabhushana * The VF Register Map. 456656b2bdd1SGireesh Nagabhushana * 456756b2bdd1SGireesh Nagabhushana * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 456856b2bdd1SGireesh Nagabhushana * bus module (PL) and CPU Interface Module (CIM) components are mapped via 456956b2bdd1SGireesh Nagabhushana * the Slice to Module Map Table (see below) in the Physical Function Register 457056b2bdd1SGireesh Nagabhushana * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 457156b2bdd1SGireesh Nagabhushana * and Offset registers in the PF Register Map. The MBDATA base address is 457256b2bdd1SGireesh Nagabhushana * quite constrained as it determines the Mailbox Data addresses for both PFs 457356b2bdd1SGireesh Nagabhushana * and VFs, and therefore must fit in both the VF and PF Register Maps without 457456b2bdd1SGireesh Nagabhushana * overlapping other registers. 457556b2bdd1SGireesh Nagabhushana */ 4576*3dde7c95SVishal Kulkarni #define FW_T4VF_SGE_BASE_ADDR 0x0000 4577*3dde7c95SVishal Kulkarni #define FW_T4VF_MPS_BASE_ADDR 0x0100 4578*3dde7c95SVishal Kulkarni #define FW_T4VF_PL_BASE_ADDR 0x0200 4579*3dde7c95SVishal Kulkarni #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4580*3dde7c95SVishal Kulkarni #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4581*3dde7c95SVishal Kulkarni #define FW_T4VF_CIM_BASE_ADDR 0x0300 458256b2bdd1SGireesh Nagabhushana 4583*3dde7c95SVishal Kulkarni #define FW_T4VF_REGMAP_START 0x0000 4584*3dde7c95SVishal Kulkarni #define FW_T4VF_REGMAP_SIZE 0x0400 458556b2bdd1SGireesh Nagabhushana 458656b2bdd1SGireesh Nagabhushana enum fw_caps_config_nbm { 458756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 458856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 458956b2bdd1SGireesh Nagabhushana }; 459056b2bdd1SGireesh Nagabhushana 459156b2bdd1SGireesh Nagabhushana enum fw_caps_config_link { 459256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 459356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 459456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 459556b2bdd1SGireesh Nagabhushana }; 459656b2bdd1SGireesh Nagabhushana 459756b2bdd1SGireesh Nagabhushana enum fw_caps_config_switch { 459856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 459956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 460056b2bdd1SGireesh Nagabhushana }; 460156b2bdd1SGireesh Nagabhushana 460256b2bdd1SGireesh Nagabhushana enum fw_caps_config_nic { 460356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC = 0x00000001, 460456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_VM = 0x00000002, 460556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 460656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_UM = 0x00000008, 460756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4608*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4609*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 461056b2bdd1SGireesh Nagabhushana }; 461156b2bdd1SGireesh Nagabhushana 461256b2bdd1SGireesh Nagabhushana enum fw_caps_config_toe { 461356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_TOE = 0x00000001, 461456b2bdd1SGireesh Nagabhushana }; 461556b2bdd1SGireesh Nagabhushana 461656b2bdd1SGireesh Nagabhushana enum fw_caps_config_rdma { 461756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 461856b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 461956b2bdd1SGireesh Nagabhushana }; 462056b2bdd1SGireesh Nagabhushana 462156b2bdd1SGireesh Nagabhushana enum fw_caps_config_iscsi { 462256b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 462356b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 462456b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 462556b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 462656b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 462756b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4628*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4629*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4630*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4631*3dde7c95SVishal Kulkarni }; 463256b2bdd1SGireesh Nagabhushana 4633*3dde7c95SVishal Kulkarni enum fw_caps_config_crypto { 4634*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4635*3dde7c95SVishal Kulkarni FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 463656b2bdd1SGireesh Nagabhushana }; 463756b2bdd1SGireesh Nagabhushana 463856b2bdd1SGireesh Nagabhushana enum fw_caps_config_fcoe { 463956b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 464056b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 464156b2bdd1SGireesh Nagabhushana FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4642de483253SVishal Kulkarni FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4643de483253SVishal Kulkarni FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 464456b2bdd1SGireesh Nagabhushana }; 464556b2bdd1SGireesh Nagabhushana 464656b2bdd1SGireesh Nagabhushana enum fw_memtype_cf { 4647*3dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4648*3dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4649*3dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4650*3dde7c95SVishal Kulkarni FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4651*3dde7c95SVishal Kulkarni FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4652*3dde7c95SVishal Kulkarni FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 465356b2bdd1SGireesh Nagabhushana }; 465456b2bdd1SGireesh Nagabhushana 465556b2bdd1SGireesh Nagabhushana struct fw_caps_config_cmd { 465656b2bdd1SGireesh Nagabhushana __be32 op_to_write; 465756b2bdd1SGireesh Nagabhushana __be32 cfvalid_to_len16; 465856b2bdd1SGireesh Nagabhushana __be32 r2; 465956b2bdd1SGireesh Nagabhushana __be32 hwmbitmap; 466056b2bdd1SGireesh Nagabhushana __be16 nbmcaps; 466156b2bdd1SGireesh Nagabhushana __be16 linkcaps; 466256b2bdd1SGireesh Nagabhushana __be16 switchcaps; 466356b2bdd1SGireesh Nagabhushana __be16 r3; 466456b2bdd1SGireesh Nagabhushana __be16 niccaps; 466556b2bdd1SGireesh Nagabhushana __be16 toecaps; 466656b2bdd1SGireesh Nagabhushana __be16 rdmacaps; 4667*3dde7c95SVishal Kulkarni __be16 cryptocaps; 466856b2bdd1SGireesh Nagabhushana __be16 iscsicaps; 466956b2bdd1SGireesh Nagabhushana __be16 fcoecaps; 467056b2bdd1SGireesh Nagabhushana __be32 cfcsum; 467156b2bdd1SGireesh Nagabhushana __be32 finiver; 467256b2bdd1SGireesh Nagabhushana __be32 finicsum; 467356b2bdd1SGireesh Nagabhushana }; 467456b2bdd1SGireesh Nagabhushana 4675*3dde7c95SVishal Kulkarni #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4676*3dde7c95SVishal Kulkarni #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4677*3dde7c95SVishal Kulkarni #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4678*3dde7c95SVishal Kulkarni #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4679*3dde7c95SVishal Kulkarni (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4680*3dde7c95SVishal Kulkarni #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4681*3dde7c95SVishal Kulkarni 4682*3dde7c95SVishal Kulkarni #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4683*3dde7c95SVishal Kulkarni #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4684*3dde7c95SVishal Kulkarni #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4685*3dde7c95SVishal Kulkarni ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4686*3dde7c95SVishal Kulkarni #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4687*3dde7c95SVishal Kulkarni (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4688*3dde7c95SVishal Kulkarni M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4689*3dde7c95SVishal Kulkarni 4690*3dde7c95SVishal Kulkarni #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4691*3dde7c95SVishal Kulkarni #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4692*3dde7c95SVishal Kulkarni #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4693*3dde7c95SVishal Kulkarni ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4694*3dde7c95SVishal Kulkarni #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4695*3dde7c95SVishal Kulkarni (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4696*3dde7c95SVishal Kulkarni M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 469756b2bdd1SGireesh Nagabhushana 469856b2bdd1SGireesh Nagabhushana /* 469956b2bdd1SGireesh Nagabhushana * params command mnemonics 470056b2bdd1SGireesh Nagabhushana */ 470156b2bdd1SGireesh Nagabhushana enum fw_params_mnem { 470256b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_DEV = 1, /* device params */ 470356b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_PFVF = 2, /* function params */ 470456b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_REG = 3, /* limited register access */ 470556b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4706*3dde7c95SVishal Kulkarni FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 470756b2bdd1SGireesh Nagabhushana FW_PARAMS_MNEM_LAST 470856b2bdd1SGireesh Nagabhushana }; 470956b2bdd1SGireesh Nagabhushana 471056b2bdd1SGireesh Nagabhushana /* 471156b2bdd1SGireesh Nagabhushana * device parameters 471256b2bdd1SGireesh Nagabhushana */ 471356b2bdd1SGireesh Nagabhushana enum fw_params_param_dev { 471456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 471556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4716*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4717*3dde7c95SVishal Kulkarni * allocated by the device's 4718*3dde7c95SVishal Kulkarni * Lookup Engine 4719*3dde7c95SVishal Kulkarni */ 472056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 472156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 472256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 472356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 472456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 472556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 472656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 472756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4728de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4729de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4730de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_CF = 0x0D, 4731de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4732de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4733de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4734de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4735de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4736de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4737de483253SVishal Kulkarni */ 4738de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4739de483253SVishal Kulkarni */ 4740de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4741de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4742de483253SVishal Kulkarni FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4743*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4744*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4745*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4746*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4747*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4748*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4749*3dde7c95SVishal Kulkarni 4750*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4751*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4752*3dde7c95SVishal Kulkarni }; 4753*3dde7c95SVishal Kulkarni 4754*3dde7c95SVishal Kulkarni /* 4755*3dde7c95SVishal Kulkarni * dev bypass parameters; actions and modes 4756*3dde7c95SVishal Kulkarni */ 4757*3dde7c95SVishal Kulkarni enum fw_params_param_dev_bypass { 4758*3dde7c95SVishal Kulkarni 4759*3dde7c95SVishal Kulkarni /* actions 4760*3dde7c95SVishal Kulkarni */ 4761*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4762*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4763*3dde7c95SVishal Kulkarni 4764*3dde7c95SVishal Kulkarni /* modes 4765*3dde7c95SVishal Kulkarni */ 4766*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4767*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4768*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4769*3dde7c95SVishal Kulkarni }; 4770*3dde7c95SVishal Kulkarni 4771*3dde7c95SVishal Kulkarni enum fw_params_param_dev_phyfw { 4772*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4773*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4774*3dde7c95SVishal Kulkarni }; 4775*3dde7c95SVishal Kulkarni 4776*3dde7c95SVishal Kulkarni enum fw_params_param_dev_diag { 4777*3dde7c95SVishal Kulkarni FW_PARAM_DEV_DIAG_TMP = 0x00, 4778*3dde7c95SVishal Kulkarni FW_PARAM_DEV_DIAG_VDD = 0x01, 4779*3dde7c95SVishal Kulkarni }; 4780*3dde7c95SVishal Kulkarni 4781*3dde7c95SVishal Kulkarni enum fw_params_param_dev_fwcache { 4782*3dde7c95SVishal Kulkarni FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4783*3dde7c95SVishal Kulkarni FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 478456b2bdd1SGireesh Nagabhushana }; 478556b2bdd1SGireesh Nagabhushana 478656b2bdd1SGireesh Nagabhushana /* 478756b2bdd1SGireesh Nagabhushana * physical and virtual function parameters 478856b2bdd1SGireesh Nagabhushana */ 478956b2bdd1SGireesh Nagabhushana enum fw_params_param_pfvf { 479056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 479156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 479256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 479356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 479456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 479556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 479656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 479756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 479856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 479956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 480056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 480156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 480256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 480356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 480456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 480556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 480656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 480756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 480856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 480956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 481056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 481156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 481256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 481356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 481456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4815*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4816*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 481756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 481856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_VIID = 0x24, 481956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 482056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 482156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 482256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 482356b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 482456b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 482556b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 482656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 482756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 482856b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 482956b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4830de483253SVishal Kulkarni FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4831*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4832*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4833*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4834*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4835*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4836*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4837*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4838*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4839*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 484056b2bdd1SGireesh Nagabhushana }; 484156b2bdd1SGireesh Nagabhushana 484256b2bdd1SGireesh Nagabhushana /* 484356b2bdd1SGireesh Nagabhushana * dma queue parameters 484456b2bdd1SGireesh Nagabhushana */ 484556b2bdd1SGireesh Nagabhushana enum fw_params_param_dmaq { 484656b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 484756b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4848*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4849*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 485056b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 485156b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 485256b2bdd1SGireesh Nagabhushana FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4853de483253SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4854*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4855*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4856*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 485756b2bdd1SGireesh Nagabhushana }; 485856b2bdd1SGireesh Nagabhushana 485956b2bdd1SGireesh Nagabhushana /* 4860*3dde7c95SVishal Kulkarni * chnet parameters 486156b2bdd1SGireesh Nagabhushana */ 4862*3dde7c95SVishal Kulkarni enum fw_params_param_chnet { 4863*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4864*3dde7c95SVishal Kulkarni }; 4865*3dde7c95SVishal Kulkarni 4866*3dde7c95SVishal Kulkarni enum fw_params_param_chnet_flags { 4867*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4868*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4869*3dde7c95SVishal Kulkarni FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4870*3dde7c95SVishal Kulkarni }; 4871*3dde7c95SVishal Kulkarni 4872*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_MNEM 24 4873*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_MNEM 0xff 4874*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4875*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_MNEM(x) \ 4876*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4877*3dde7c95SVishal Kulkarni 4878*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_X 16 4879*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_X 0xff 4880*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4881*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_X(x) \ 4882*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4883*3dde7c95SVishal Kulkarni 4884*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_Y 8 4885*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_Y 0xff 4886*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4887*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_Y(x) \ 4888*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4889*3dde7c95SVishal Kulkarni 4890*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_Z 0 4891*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_Z 0xff 4892*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4893*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_Z(x) \ 4894*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4895*3dde7c95SVishal Kulkarni 4896*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_XYZ 0 4897*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4898*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4899*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_XYZ(x) \ 4900*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4901*3dde7c95SVishal Kulkarni 4902*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_YZ 0 4903*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_YZ 0xffff 4904*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4905*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_YZ(x) \ 4906*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4907*3dde7c95SVishal Kulkarni 4908*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4909*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4910*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4911*3dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4912*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4913*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4914*3dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4915*3dde7c95SVishal Kulkarni 4916*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4917*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4918*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4919*3dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4920*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4921*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4922*3dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4923*3dde7c95SVishal Kulkarni 4924*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4925*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4926*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4927*3dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4928*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4929*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4930*3dde7c95SVishal Kulkarni 4931*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 4932*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 4933*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4934*3dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4935*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4936*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 4937*3dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4938*3dde7c95SVishal Kulkarni 4939*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 4940*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 4941*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4942*3dde7c95SVishal Kulkarni ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4943*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4944*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 4945*3dde7c95SVishal Kulkarni M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 494656b2bdd1SGireesh Nagabhushana 494756b2bdd1SGireesh Nagabhushana struct fw_params_cmd { 494856b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 494956b2bdd1SGireesh Nagabhushana __be32 retval_len16; 495056b2bdd1SGireesh Nagabhushana struct fw_params_param { 495156b2bdd1SGireesh Nagabhushana __be32 mnem; 495256b2bdd1SGireesh Nagabhushana __be32 val; 495356b2bdd1SGireesh Nagabhushana } param[7]; 495456b2bdd1SGireesh Nagabhushana }; 495556b2bdd1SGireesh Nagabhushana 4956*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_CMD_PFN 8 4957*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_CMD_PFN 0x7 4958*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4959*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_CMD_PFN(x) \ 4960*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 496156b2bdd1SGireesh Nagabhushana 4962*3dde7c95SVishal Kulkarni #define S_FW_PARAMS_CMD_VFN 0 4963*3dde7c95SVishal Kulkarni #define M_FW_PARAMS_CMD_VFN 0xff 4964*3dde7c95SVishal Kulkarni #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4965*3dde7c95SVishal Kulkarni #define G_FW_PARAMS_CMD_VFN(x) \ 4966*3dde7c95SVishal Kulkarni (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 496756b2bdd1SGireesh Nagabhushana 496856b2bdd1SGireesh Nagabhushana struct fw_pfvf_cmd { 496956b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 497056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 497156b2bdd1SGireesh Nagabhushana __be32 niqflint_niq; 497256b2bdd1SGireesh Nagabhushana __be32 type_to_neq; 497356b2bdd1SGireesh Nagabhushana __be32 tc_to_nexactf; 497456b2bdd1SGireesh Nagabhushana __be32 r_caps_to_nethctrl; 497556b2bdd1SGireesh Nagabhushana __be16 nricq; 497656b2bdd1SGireesh Nagabhushana __be16 nriqp; 497756b2bdd1SGireesh Nagabhushana __be32 r4; 497856b2bdd1SGireesh Nagabhushana }; 497956b2bdd1SGireesh Nagabhushana 4980*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_PFN 8 4981*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_PFN 0x7 4982*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 4983*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_PFN(x) \ 4984*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 4985*3dde7c95SVishal Kulkarni 4986*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_VFN 0 4987*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_VFN 0xff 4988*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 4989*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_VFN(x) \ 4990*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 4991*3dde7c95SVishal Kulkarni 4992*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NIQFLINT 20 4993*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NIQFLINT 0xfff 4994*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 4995*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NIQFLINT(x) \ 4996*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 4997*3dde7c95SVishal Kulkarni 4998*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NIQ 0 4999*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NIQ 0xfffff 5000*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5001*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NIQ(x) \ 5002*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5003*3dde7c95SVishal Kulkarni 5004*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_TYPE 31 5005*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_TYPE 0x1 5006*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5007*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_TYPE(x) \ 5008*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5009*3dde7c95SVishal Kulkarni #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5010*3dde7c95SVishal Kulkarni 5011*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_CMASK 24 5012*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_CMASK 0xf 5013*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5014*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_CMASK(x) \ 5015*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5016*3dde7c95SVishal Kulkarni 5017*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_PMASK 20 5018*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_PMASK 0xf 5019*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5020*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_PMASK(x) \ 5021*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5022*3dde7c95SVishal Kulkarni 5023*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NEQ 0 5024*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NEQ 0xfffff 5025*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5026*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NEQ(x) \ 5027*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5028*3dde7c95SVishal Kulkarni 5029*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_TC 24 5030*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_TC 0xff 5031*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5032*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_TC(x) \ 5033*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5034*3dde7c95SVishal Kulkarni 5035*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NVI 16 5036*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NVI 0xff 5037*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5038*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NVI(x) \ 5039*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5040*3dde7c95SVishal Kulkarni 5041*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NEXACTF 0 5042*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NEXACTF 0xffff 5043*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5044*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NEXACTF(x) \ 5045*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5046*3dde7c95SVishal Kulkarni 5047*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_R_CAPS 24 5048*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_R_CAPS 0xff 5049*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5050*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_R_CAPS(x) \ 5051*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5052*3dde7c95SVishal Kulkarni 5053*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_WX_CAPS 16 5054*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_WX_CAPS 0xff 5055*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5056*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_WX_CAPS(x) \ 5057*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5058*3dde7c95SVishal Kulkarni 5059*3dde7c95SVishal Kulkarni #define S_FW_PFVF_CMD_NETHCTRL 0 5060*3dde7c95SVishal Kulkarni #define M_FW_PFVF_CMD_NETHCTRL 0xffff 5061*3dde7c95SVishal Kulkarni #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5062*3dde7c95SVishal Kulkarni #define G_FW_PFVF_CMD_NETHCTRL(x) \ 5063*3dde7c95SVishal Kulkarni (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 506456b2bdd1SGireesh Nagabhushana 506556b2bdd1SGireesh Nagabhushana /* 506656b2bdd1SGireesh Nagabhushana * ingress queue type; the first 1K ingress queues can have associated 0, 506756b2bdd1SGireesh Nagabhushana * 1 or 2 free lists and an interrupt, all other ingress queues lack these 506856b2bdd1SGireesh Nagabhushana * capabilities 506956b2bdd1SGireesh Nagabhushana */ 507056b2bdd1SGireesh Nagabhushana enum fw_iq_type { 507156b2bdd1SGireesh Nagabhushana FW_IQ_TYPE_FL_INT_CAP, 5072*3dde7c95SVishal Kulkarni FW_IQ_TYPE_NO_FL_INT_CAP, 5073*3dde7c95SVishal Kulkarni FW_IQ_TYPE_VF_CQ 507456b2bdd1SGireesh Nagabhushana }; 507556b2bdd1SGireesh Nagabhushana 507656b2bdd1SGireesh Nagabhushana struct fw_iq_cmd { 507756b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 507856b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 507956b2bdd1SGireesh Nagabhushana __be16 physiqid; 508056b2bdd1SGireesh Nagabhushana __be16 iqid; 508156b2bdd1SGireesh Nagabhushana __be16 fl0id; 508256b2bdd1SGireesh Nagabhushana __be16 fl1id; 508356b2bdd1SGireesh Nagabhushana __be32 type_to_iqandstindex; 508456b2bdd1SGireesh Nagabhushana __be16 iqdroprss_to_iqesize; 508556b2bdd1SGireesh Nagabhushana __be16 iqsize; 508656b2bdd1SGireesh Nagabhushana __be64 iqaddr; 508756b2bdd1SGireesh Nagabhushana __be32 iqns_to_fl0congen; 508856b2bdd1SGireesh Nagabhushana __be16 fl0dcaen_to_fl0cidxfthresh; 508956b2bdd1SGireesh Nagabhushana __be16 fl0size; 509056b2bdd1SGireesh Nagabhushana __be64 fl0addr; 509156b2bdd1SGireesh Nagabhushana __be32 fl1cngchmap_to_fl1congen; 509256b2bdd1SGireesh Nagabhushana __be16 fl1dcaen_to_fl1cidxfthresh; 509356b2bdd1SGireesh Nagabhushana __be16 fl1size; 509456b2bdd1SGireesh Nagabhushana __be64 fl1addr; 509556b2bdd1SGireesh Nagabhushana }; 509656b2bdd1SGireesh Nagabhushana 5097*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_PFN 8 5098*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_PFN 0x7 5099*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5100*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_PFN(x) \ 5101*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5102*3dde7c95SVishal Kulkarni 5103*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_VFN 0 5104*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_VFN 0xff 5105*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5106*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_VFN(x) \ 5107*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5108*3dde7c95SVishal Kulkarni 5109*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_ALLOC 31 5110*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_ALLOC 0x1 5111*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5112*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_ALLOC(x) \ 5113*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5114*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5115*3dde7c95SVishal Kulkarni 5116*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FREE 30 5117*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FREE 0x1 5118*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5119*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FREE(x) \ 5120*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5121*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5122*3dde7c95SVishal Kulkarni 5123*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_MODIFY 29 5124*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_MODIFY 0x1 5125*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5126*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_MODIFY(x) \ 5127*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5128*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5129*3dde7c95SVishal Kulkarni 5130*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQSTART 28 5131*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQSTART 0x1 5132*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5133*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQSTART(x) \ 5134*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5135*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5136*3dde7c95SVishal Kulkarni 5137*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQSTOP 27 5138*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQSTOP 0x1 5139*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5140*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQSTOP(x) \ 5141*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5142*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5143*3dde7c95SVishal Kulkarni 5144*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_TYPE 29 5145*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_TYPE 0x7 5146*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5147*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_TYPE(x) \ 5148*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5149*3dde7c95SVishal Kulkarni 5150*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQASYNCH 28 5151*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQASYNCH 0x1 5152*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5153*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQASYNCH(x) \ 5154*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5155*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5156*3dde7c95SVishal Kulkarni 5157*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_VIID 16 5158*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_VIID 0xfff 5159*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5160*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_VIID(x) \ 5161*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5162*3dde7c95SVishal Kulkarni 5163*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANDST 15 5164*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANDST 0x1 5165*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5166*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANDST(x) \ 5167*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5168*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5169*3dde7c95SVishal Kulkarni 5170*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANUS 14 5171*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANUS 0x1 5172*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5173*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANUS(x) \ 5174*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5175*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5176*3dde7c95SVishal Kulkarni 5177*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANUD 12 5178*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANUD 0x3 5179*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5180*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANUD(x) \ 5181*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5182*3dde7c95SVishal Kulkarni 5183*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQANDSTINDEX 0 5184*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5185*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5186*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5187*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5188*3dde7c95SVishal Kulkarni 5189*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQDROPRSS 15 5190*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQDROPRSS 0x1 5191*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5192*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5193*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5194*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5195*3dde7c95SVishal Kulkarni 5196*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQGTSMODE 14 5197*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQGTSMODE 0x1 5198*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5199*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5200*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5201*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5202*3dde7c95SVishal Kulkarni 5203*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQPCIECH 12 5204*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQPCIECH 0x3 5205*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5206*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQPCIECH(x) \ 5207*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5208*3dde7c95SVishal Kulkarni 5209*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQDCAEN 11 5210*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQDCAEN 0x1 5211*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5212*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQDCAEN(x) \ 5213*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5214*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5215*3dde7c95SVishal Kulkarni 5216*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQDCACPU 6 5217*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQDCACPU 0x1f 5218*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5219*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQDCACPU(x) \ 5220*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5221*3dde7c95SVishal Kulkarni 5222*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5223*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5224*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5225*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5226*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5227*3dde7c95SVishal Kulkarni 5228*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQO 3 5229*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQO 0x1 5230*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5231*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQO(x) \ 5232*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5233*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5234*3dde7c95SVishal Kulkarni 5235*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQCPRIO 2 5236*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQCPRIO 0x1 5237*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5238*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQCPRIO(x) \ 5239*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5240*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5241*3dde7c95SVishal Kulkarni 5242*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQESIZE 0 5243*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQESIZE 0x3 5244*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5245*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQESIZE(x) \ 5246*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5247*3dde7c95SVishal Kulkarni 5248*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQNS 31 5249*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQNS 0x1 5250*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5251*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQNS(x) \ 5252*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5253*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5254*3dde7c95SVishal Kulkarni 5255*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQRO 30 5256*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQRO 0x1 5257*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5258*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQRO(x) \ 5259*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5260*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5261*3dde7c95SVishal Kulkarni 5262*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5263*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5264*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5265*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5266*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5267*3dde7c95SVishal Kulkarni 5268*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5269*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5270*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5271*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5272*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5273*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5274*3dde7c95SVishal Kulkarni 5275*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5276*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5277*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5278*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5279*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5280*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5281*3dde7c95SVishal Kulkarni 5282*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5283*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5284*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5285*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5286*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5287*3dde7c95SVishal Kulkarni 5288*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CONGDROP 16 5289*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5290*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5291*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5292*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5293*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5294*3dde7c95SVishal Kulkarni 5295*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CACHELOCK 15 5296*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5297*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5298*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5299*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5300*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5301*3dde7c95SVishal Kulkarni 5302*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DBP 14 5303*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DBP 0x1 5304*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5305*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DBP(x) \ 5306*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5307*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5308*3dde7c95SVishal Kulkarni 5309*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DATANS 13 5310*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DATANS 0x1 5311*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5312*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DATANS(x) \ 5313*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5314*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5315*3dde7c95SVishal Kulkarni 5316*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DATARO 12 5317*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DATARO 0x1 5318*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5319*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DATARO(x) \ 5320*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5321*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5322*3dde7c95SVishal Kulkarni 5323*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CONGCIF 11 5324*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5325*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5326*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5327*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5328*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5329*3dde7c95SVishal Kulkarni 5330*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0ONCHIP 10 5331*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5332*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5333*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5334*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5335*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5336*3dde7c95SVishal Kulkarni 5337*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5338*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5339*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5340*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5341*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5342*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5343*3dde7c95SVishal Kulkarni 5344*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5345*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5346*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5347*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5348*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5349*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5350*3dde7c95SVishal Kulkarni 5351*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FETCHNS 7 5352*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5353*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5354*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5355*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5356*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5357*3dde7c95SVishal Kulkarni 5358*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FETCHRO 6 5359*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5360*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5361*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5362*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5363*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5364*3dde7c95SVishal Kulkarni 5365*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5366*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5367*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5368*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5369*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5370*3dde7c95SVishal Kulkarni 5371*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CPRIO 3 5372*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CPRIO 0x1 5373*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5374*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5375*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5376*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5377*3dde7c95SVishal Kulkarni 5378*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0PADEN 2 5379*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0PADEN 0x1 5380*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5381*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0PADEN(x) \ 5382*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5383*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5384*3dde7c95SVishal Kulkarni 5385*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0PACKEN 1 5386*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0PACKEN 0x1 5387*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5388*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5389*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5390*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5391*3dde7c95SVishal Kulkarni 5392*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CONGEN 0 5393*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CONGEN 0x1 5394*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5395*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5396*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5397*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5398*3dde7c95SVishal Kulkarni 5399*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DCAEN 15 5400*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DCAEN 0x1 5401*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5402*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5403*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5404*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5405*3dde7c95SVishal Kulkarni 5406*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0DCACPU 10 5407*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5408*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5409*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5410*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5411*3dde7c95SVishal Kulkarni 5412*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FBMIN 7 5413*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FBMIN 0x7 5414*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5415*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5416*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5417*3dde7c95SVishal Kulkarni 5418*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0FBMAX 4 5419*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0FBMAX 0x7 5420*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5421*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5422*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5423*3dde7c95SVishal Kulkarni 5424*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5425*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5426*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5427*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5428*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5429*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5430*3dde7c95SVishal Kulkarni 5431*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5432*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5433*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5434*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5435*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5436*3dde7c95SVishal Kulkarni 5437*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5438*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5439*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5440*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5441*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5442*3dde7c95SVishal Kulkarni 5443*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CONGDROP 16 5444*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5445*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5446*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5447*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5448*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5449*3dde7c95SVishal Kulkarni 5450*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CACHELOCK 15 5451*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5452*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5453*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5454*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5455*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5456*3dde7c95SVishal Kulkarni 5457*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DBP 14 5458*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DBP 0x1 5459*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5460*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DBP(x) \ 5461*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5462*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5463*3dde7c95SVishal Kulkarni 5464*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DATANS 13 5465*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DATANS 0x1 5466*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5467*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DATANS(x) \ 5468*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5469*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5470*3dde7c95SVishal Kulkarni 5471*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DATARO 12 5472*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DATARO 0x1 5473*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5474*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DATARO(x) \ 5475*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5476*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5477*3dde7c95SVishal Kulkarni 5478*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CONGCIF 11 5479*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5480*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5481*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5482*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5483*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5484*3dde7c95SVishal Kulkarni 5485*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1ONCHIP 10 5486*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5487*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5488*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5489*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5490*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5491*3dde7c95SVishal Kulkarni 5492*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5493*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5494*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5495*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5496*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5497*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5498*3dde7c95SVishal Kulkarni 5499*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5500*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5501*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5502*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5503*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5504*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5505*3dde7c95SVishal Kulkarni 5506*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FETCHNS 7 5507*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5508*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5509*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5510*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5511*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5512*3dde7c95SVishal Kulkarni 5513*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FETCHRO 6 5514*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5515*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5516*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5517*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5518*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5519*3dde7c95SVishal Kulkarni 5520*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5521*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5522*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5523*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5524*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5525*3dde7c95SVishal Kulkarni 5526*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CPRIO 3 5527*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CPRIO 0x1 5528*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5529*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5530*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5531*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5532*3dde7c95SVishal Kulkarni 5533*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1PADEN 2 5534*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1PADEN 0x1 5535*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5536*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1PADEN(x) \ 5537*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5538*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5539*3dde7c95SVishal Kulkarni 5540*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1PACKEN 1 5541*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1PACKEN 0x1 5542*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5543*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5544*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5545*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5546*3dde7c95SVishal Kulkarni 5547*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CONGEN 0 5548*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CONGEN 0x1 5549*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5550*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5551*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5552*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5553*3dde7c95SVishal Kulkarni 5554*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DCAEN 15 5555*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DCAEN 0x1 5556*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5557*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5558*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5559*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5560*3dde7c95SVishal Kulkarni 5561*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1DCACPU 10 5562*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5563*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5564*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5565*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5566*3dde7c95SVishal Kulkarni 5567*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FBMIN 7 5568*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FBMIN 0x7 5569*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5570*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5571*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5572*3dde7c95SVishal Kulkarni 5573*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1FBMAX 4 5574*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1FBMAX 0x7 5575*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5576*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5577*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5578*3dde7c95SVishal Kulkarni 5579*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5580*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5581*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5582*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5583*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5584*3dde7c95SVishal Kulkarni #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5585*3dde7c95SVishal Kulkarni 5586*3dde7c95SVishal Kulkarni #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5587*3dde7c95SVishal Kulkarni #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5588*3dde7c95SVishal Kulkarni #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5589*3dde7c95SVishal Kulkarni #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5590*3dde7c95SVishal Kulkarni (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 559156b2bdd1SGireesh Nagabhushana 559256b2bdd1SGireesh Nagabhushana struct fw_eq_mngt_cmd { 559356b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 559456b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 559556b2bdd1SGireesh Nagabhushana __be32 cmpliqid_eqid; 559656b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 559756b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 559856b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 559956b2bdd1SGireesh Nagabhushana __be64 eqaddr; 560056b2bdd1SGireesh Nagabhushana }; 560156b2bdd1SGireesh Nagabhushana 5602*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_PFN 8 5603*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_PFN 0x7 5604*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5605*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5606*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5607*3dde7c95SVishal Kulkarni 5608*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_VFN 0 5609*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_VFN 0xff 5610*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5611*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5612*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5613*3dde7c95SVishal Kulkarni 5614*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_ALLOC 31 5615*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5616*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5617*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5618*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5619*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5620*3dde7c95SVishal Kulkarni 5621*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FREE 30 5622*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FREE 0x1 5623*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5624*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5625*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5626*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5627*3dde7c95SVishal Kulkarni 5628*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_MODIFY 29 5629*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5630*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5631*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5632*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5633*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5634*3dde7c95SVishal Kulkarni 5635*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQSTART 28 5636*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5637*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5638*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5639*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5640*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5641*3dde7c95SVishal Kulkarni 5642*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5643*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5644*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5645*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5646*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5647*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5648*3dde7c95SVishal Kulkarni 5649*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5650*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5651*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5652*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5653*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5654*3dde7c95SVishal Kulkarni 5655*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQID 0 5656*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5657*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5658*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5659*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5660*3dde7c95SVishal Kulkarni 5661*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5662*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5663*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5664*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5665*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5666*3dde7c95SVishal Kulkarni 5667*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5668*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5669*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5670*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5671*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5672*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5673*3dde7c95SVishal Kulkarni 5674*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5675*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5676*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5677*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5678*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5679*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5680*3dde7c95SVishal Kulkarni 5681*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5682*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5683*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5684*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5685*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5686*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5687*3dde7c95SVishal Kulkarni 5688*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5689*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5690*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5691*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5692*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5693*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5694*3dde7c95SVishal Kulkarni 5695*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5696*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5697*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5698*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5699*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5700*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5701*3dde7c95SVishal Kulkarni 5702*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5703*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5704*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5705*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5706*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5707*3dde7c95SVishal Kulkarni 5708*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CPRIO 19 5709*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5710*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5711*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5712*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5713*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5714*3dde7c95SVishal Kulkarni 5715*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5716*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5717*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5718*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5719*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5720*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5721*3dde7c95SVishal Kulkarni 5722*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5723*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5724*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5725*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5726*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5727*3dde7c95SVishal Kulkarni 5728*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_IQID 0 5729*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5730*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5731*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5732*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5733*3dde7c95SVishal Kulkarni 5734*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_DCAEN 31 5735*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5736*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5737*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5738*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5739*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5740*3dde7c95SVishal Kulkarni 5741*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_DCACPU 26 5742*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5743*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5744*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5745*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5746*3dde7c95SVishal Kulkarni 5747*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FBMIN 23 5748*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5749*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5750*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5751*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5752*3dde7c95SVishal Kulkarni 5753*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_FBMAX 20 5754*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5755*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5756*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5757*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5758*3dde7c95SVishal Kulkarni 5759*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5760*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5761*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5762*3dde7c95SVishal Kulkarni ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5763*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5764*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5765*3dde7c95SVishal Kulkarni #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5766*3dde7c95SVishal Kulkarni 5767*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5768*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5769*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5770*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5771*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5772*3dde7c95SVishal Kulkarni 5773*3dde7c95SVishal Kulkarni #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5774*3dde7c95SVishal Kulkarni #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5775*3dde7c95SVishal Kulkarni #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5776*3dde7c95SVishal Kulkarni #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5777*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 577856b2bdd1SGireesh Nagabhushana 577956b2bdd1SGireesh Nagabhushana struct fw_eq_eth_cmd { 578056b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 578156b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 578256b2bdd1SGireesh Nagabhushana __be32 eqid_pkd; 578356b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 578456b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 578556b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 578656b2bdd1SGireesh Nagabhushana __be64 eqaddr; 5787*3dde7c95SVishal Kulkarni __be32 autoequiqe_to_viid; 578856b2bdd1SGireesh Nagabhushana __be32 r8_lo; 578956b2bdd1SGireesh Nagabhushana __be64 r9; 579056b2bdd1SGireesh Nagabhushana }; 579156b2bdd1SGireesh Nagabhushana 5792*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_PFN 8 5793*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_PFN 0x7 5794*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5795*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_PFN(x) \ 5796*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5797*3dde7c95SVishal Kulkarni 5798*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_VFN 0 5799*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_VFN 0xff 5800*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5801*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_VFN(x) \ 5802*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5803*3dde7c95SVishal Kulkarni 5804*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_ALLOC 31 5805*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5806*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5807*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5808*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5809*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5810*3dde7c95SVishal Kulkarni 5811*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FREE 30 5812*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FREE 0x1 5813*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5814*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FREE(x) \ 5815*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5816*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5817*3dde7c95SVishal Kulkarni 5818*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_MODIFY 29 5819*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5820*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5821*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5822*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5823*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5824*3dde7c95SVishal Kulkarni 5825*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQSTART 28 5826*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5827*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5828*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5829*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5830*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5831*3dde7c95SVishal Kulkarni 5832*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQSTOP 27 5833*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5834*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5835*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5836*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5837*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5838*3dde7c95SVishal Kulkarni 5839*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQID 0 5840*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5841*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5842*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQID(x) \ 5843*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5844*3dde7c95SVishal Kulkarni 5845*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5846*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5847*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5848*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5849*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5850*3dde7c95SVishal Kulkarni 5851*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5852*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5853*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5854*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5855*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5856*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5857*3dde7c95SVishal Kulkarni 5858*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5859*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5860*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5861*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5862*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5863*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5864*3dde7c95SVishal Kulkarni 5865*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5866*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5867*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5868*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5869*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5870*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5871*3dde7c95SVishal Kulkarni 5872*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FETCHNS 23 5873*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5874*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5875*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5876*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5877*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5878*3dde7c95SVishal Kulkarni 5879*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FETCHRO 22 5880*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5881*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5882*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5883*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5884*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5885*3dde7c95SVishal Kulkarni 5886*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5887*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5888*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5889*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5890*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5891*3dde7c95SVishal Kulkarni 5892*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_CPRIO 19 5893*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5894*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5895*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5896*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5897*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5898*3dde7c95SVishal Kulkarni 5899*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_ONCHIP 18 5900*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5901*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5902*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5903*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5904*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5905*3dde7c95SVishal Kulkarni 5906*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_PCIECHN 16 5907*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5908*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5909*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5910*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5911*3dde7c95SVishal Kulkarni 5912*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_IQID 0 5913*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_IQID 0xffff 5914*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5915*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_IQID(x) \ 5916*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5917*3dde7c95SVishal Kulkarni 5918*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_DCAEN 31 5919*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5920*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5921*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5922*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5923*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5924*3dde7c95SVishal Kulkarni 5925*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_DCACPU 26 5926*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5927*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5928*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5929*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5930*3dde7c95SVishal Kulkarni 5931*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FBMIN 23 5932*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FBMIN 0x7 5933*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5934*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5935*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5936*3dde7c95SVishal Kulkarni 5937*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_FBMAX 20 5938*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_FBMAX 0x7 5939*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5940*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5941*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5942*3dde7c95SVishal Kulkarni 5943*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5944*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5945*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5946*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5947*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5948*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5949*3dde7c95SVishal Kulkarni 5950*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5951*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5952*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5953*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5954*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5955*3dde7c95SVishal Kulkarni 5956*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_EQSIZE 0 5957*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5958*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5959*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5960*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5961*3dde7c95SVishal Kulkarni 5962*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5963*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5964*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5965*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5966*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 5967*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 5968*3dde7c95SVishal Kulkarni 5969*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 5970*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 5971*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 5972*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 5973*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 5974*3dde7c95SVishal Kulkarni #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 5975*3dde7c95SVishal Kulkarni 5976*3dde7c95SVishal Kulkarni #define S_FW_EQ_ETH_CMD_VIID 16 5977*3dde7c95SVishal Kulkarni #define M_FW_EQ_ETH_CMD_VIID 0xfff 5978*3dde7c95SVishal Kulkarni #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 5979*3dde7c95SVishal Kulkarni #define G_FW_EQ_ETH_CMD_VIID(x) \ 5980*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 598156b2bdd1SGireesh Nagabhushana 598256b2bdd1SGireesh Nagabhushana struct fw_eq_ctrl_cmd { 598356b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 598456b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 598556b2bdd1SGireesh Nagabhushana __be32 cmpliqid_eqid; 598656b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 598756b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 598856b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 598956b2bdd1SGireesh Nagabhushana __be64 eqaddr; 599056b2bdd1SGireesh Nagabhushana }; 599156b2bdd1SGireesh Nagabhushana 5992*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_PFN 8 5993*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_PFN 0x7 5994*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 5995*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_PFN(x) \ 5996*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 5997*3dde7c95SVishal Kulkarni 5998*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_VFN 0 5999*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_VFN 0xff 6000*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6001*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_VFN(x) \ 6002*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6003*3dde7c95SVishal Kulkarni 6004*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_ALLOC 31 6005*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6006*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6007*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6008*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6009*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6010*3dde7c95SVishal Kulkarni 6011*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FREE 30 6012*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FREE 0x1 6013*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6014*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FREE(x) \ 6015*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6016*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6017*3dde7c95SVishal Kulkarni 6018*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_MODIFY 29 6019*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6020*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6021*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6022*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6023*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6024*3dde7c95SVishal Kulkarni 6025*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQSTART 28 6026*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6027*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6028*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6029*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6030*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6031*3dde7c95SVishal Kulkarni 6032*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQSTOP 27 6033*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6034*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6035*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6036*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6037*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6038*3dde7c95SVishal Kulkarni 6039*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6040*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6041*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6042*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6043*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6044*3dde7c95SVishal Kulkarni 6045*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQID 0 6046*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6047*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6048*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQID(x) \ 6049*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6050*3dde7c95SVishal Kulkarni 6051*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6052*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6053*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6054*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6055*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6056*3dde7c95SVishal Kulkarni 6057*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6058*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6059*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6060*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6061*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6062*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6063*3dde7c95SVishal Kulkarni 6064*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6065*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6066*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6067*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6068*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6069*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6070*3dde7c95SVishal Kulkarni 6071*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6072*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6073*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6074*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6075*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6076*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6077*3dde7c95SVishal Kulkarni 6078*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FETCHNS 23 6079*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6080*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6081*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6082*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6083*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6084*3dde7c95SVishal Kulkarni 6085*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FETCHRO 22 6086*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6087*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6088*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6089*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6090*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6091*3dde7c95SVishal Kulkarni 6092*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6093*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6094*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6095*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6096*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6097*3dde7c95SVishal Kulkarni 6098*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CPRIO 19 6099*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6100*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6101*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6102*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6103*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6104*3dde7c95SVishal Kulkarni 6105*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_ONCHIP 18 6106*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6107*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6108*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6109*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6110*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6111*3dde7c95SVishal Kulkarni 6112*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_PCIECHN 16 6113*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6114*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6115*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6116*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6117*3dde7c95SVishal Kulkarni 6118*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_IQID 0 6119*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_IQID 0xffff 6120*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6121*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_IQID(x) \ 6122*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6123*3dde7c95SVishal Kulkarni 6124*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_DCAEN 31 6125*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6126*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6127*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6128*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6129*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6130*3dde7c95SVishal Kulkarni 6131*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_DCACPU 26 6132*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6133*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6134*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6135*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6136*3dde7c95SVishal Kulkarni 6137*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FBMIN 23 6138*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6139*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6140*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6141*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6142*3dde7c95SVishal Kulkarni 6143*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_FBMAX 20 6144*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6145*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6146*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6147*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6148*3dde7c95SVishal Kulkarni 6149*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6150*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6151*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6152*3dde7c95SVishal Kulkarni ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6153*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6154*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6155*3dde7c95SVishal Kulkarni #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6156*3dde7c95SVishal Kulkarni 6157*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6158*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6159*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6160*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6161*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6162*3dde7c95SVishal Kulkarni 6163*3dde7c95SVishal Kulkarni #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6164*3dde7c95SVishal Kulkarni #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6165*3dde7c95SVishal Kulkarni #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6166*3dde7c95SVishal Kulkarni #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6167*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 616856b2bdd1SGireesh Nagabhushana 616956b2bdd1SGireesh Nagabhushana struct fw_eq_ofld_cmd { 617056b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 617156b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 617256b2bdd1SGireesh Nagabhushana __be32 eqid_pkd; 617356b2bdd1SGireesh Nagabhushana __be32 physeqid_pkd; 617456b2bdd1SGireesh Nagabhushana __be32 fetchszm_to_iqid; 617556b2bdd1SGireesh Nagabhushana __be32 dcaen_to_eqsize; 617656b2bdd1SGireesh Nagabhushana __be64 eqaddr; 617756b2bdd1SGireesh Nagabhushana }; 617856b2bdd1SGireesh Nagabhushana 6179*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_PFN 8 6180*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_PFN 0x7 6181*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6182*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6183*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6184*3dde7c95SVishal Kulkarni 6185*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_VFN 0 6186*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_VFN 0xff 6187*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6188*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6189*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6190*3dde7c95SVishal Kulkarni 6191*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_ALLOC 31 6192*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6193*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6194*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6195*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6196*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6197*3dde7c95SVishal Kulkarni 6198*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FREE 30 6199*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FREE 0x1 6200*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6201*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6202*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6203*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6204*3dde7c95SVishal Kulkarni 6205*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_MODIFY 29 6206*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6207*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6208*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6209*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6210*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6211*3dde7c95SVishal Kulkarni 6212*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQSTART 28 6213*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6214*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6215*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6216*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6217*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6218*3dde7c95SVishal Kulkarni 6219*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6220*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6221*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6222*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6223*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6224*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6225*3dde7c95SVishal Kulkarni 6226*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQID 0 6227*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6228*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6229*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6230*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6231*3dde7c95SVishal Kulkarni 6232*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6233*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6234*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6235*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6236*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6237*3dde7c95SVishal Kulkarni 6238*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6239*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6240*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6241*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6242*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6243*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6244*3dde7c95SVishal Kulkarni 6245*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6246*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6247*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6248*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6249*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6250*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6251*3dde7c95SVishal Kulkarni 6252*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6253*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6254*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6255*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6256*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6257*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6258*3dde7c95SVishal Kulkarni 6259*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6260*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6261*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6262*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6263*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6264*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6265*3dde7c95SVishal Kulkarni 6266*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6267*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6268*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6269*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6270*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6271*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6272*3dde7c95SVishal Kulkarni 6273*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6274*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6275*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6276*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6277*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6278*3dde7c95SVishal Kulkarni 6279*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_CPRIO 19 6280*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6281*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6282*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6283*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6284*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6285*3dde7c95SVishal Kulkarni 6286*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6287*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6288*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6289*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6290*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6291*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6292*3dde7c95SVishal Kulkarni 6293*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6294*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6295*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6296*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6297*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6298*3dde7c95SVishal Kulkarni 6299*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_IQID 0 6300*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6301*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6302*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6303*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6304*3dde7c95SVishal Kulkarni 6305*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_DCAEN 31 6306*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6307*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6308*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6309*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6310*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6311*3dde7c95SVishal Kulkarni 6312*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_DCACPU 26 6313*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6314*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6315*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6316*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6317*3dde7c95SVishal Kulkarni 6318*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FBMIN 23 6319*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6320*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6321*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6322*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6323*3dde7c95SVishal Kulkarni 6324*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_FBMAX 20 6325*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6326*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6327*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6328*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6329*3dde7c95SVishal Kulkarni 6330*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6331*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6332*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6333*3dde7c95SVishal Kulkarni ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6334*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6335*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6336*3dde7c95SVishal Kulkarni #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6337*3dde7c95SVishal Kulkarni 6338*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6339*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6340*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6341*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6342*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6343*3dde7c95SVishal Kulkarni 6344*3dde7c95SVishal Kulkarni #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6345*3dde7c95SVishal Kulkarni #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6346*3dde7c95SVishal Kulkarni #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6347*3dde7c95SVishal Kulkarni #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6348*3dde7c95SVishal Kulkarni (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6349*3dde7c95SVishal Kulkarni 6350*3dde7c95SVishal Kulkarni /* Macros for VIID parsing: 6351*3dde7c95SVishal Kulkarni VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6352*3dde7c95SVishal Kulkarni #define S_FW_VIID_PFN 8 6353*3dde7c95SVishal Kulkarni #define M_FW_VIID_PFN 0x7 6354*3dde7c95SVishal Kulkarni #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6355*3dde7c95SVishal Kulkarni #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6356*3dde7c95SVishal Kulkarni 6357*3dde7c95SVishal Kulkarni #define S_FW_VIID_VIVLD 7 6358*3dde7c95SVishal Kulkarni #define M_FW_VIID_VIVLD 0x1 6359*3dde7c95SVishal Kulkarni #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6360*3dde7c95SVishal Kulkarni #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6361*3dde7c95SVishal Kulkarni 6362*3dde7c95SVishal Kulkarni #define S_FW_VIID_VIN 0 6363*3dde7c95SVishal Kulkarni #define M_FW_VIID_VIN 0x7F 6364*3dde7c95SVishal Kulkarni #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6365*3dde7c95SVishal Kulkarni #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 636656b2bdd1SGireesh Nagabhushana 636756b2bdd1SGireesh Nagabhushana enum fw_vi_func { 636856b2bdd1SGireesh Nagabhushana FW_VI_FUNC_ETH, 636956b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OFLD, 637056b2bdd1SGireesh Nagabhushana FW_VI_FUNC_IWARP, 637156b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OPENISCSI, 637256b2bdd1SGireesh Nagabhushana FW_VI_FUNC_OPENFCOE, 637356b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FOISCSI, 637456b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FOFCOE, 637556b2bdd1SGireesh Nagabhushana FW_VI_FUNC_FW, 637656b2bdd1SGireesh Nagabhushana }; 637756b2bdd1SGireesh Nagabhushana 637856b2bdd1SGireesh Nagabhushana struct fw_vi_cmd { 637956b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 638056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 638156b2bdd1SGireesh Nagabhushana __be16 type_to_viid; 638256b2bdd1SGireesh Nagabhushana __u8 mac[6]; 638356b2bdd1SGireesh Nagabhushana __u8 portid_pkd; 638456b2bdd1SGireesh Nagabhushana __u8 nmac; 638556b2bdd1SGireesh Nagabhushana __u8 nmac0[6]; 6386de483253SVishal Kulkarni __be16 norss_rsssize; 638756b2bdd1SGireesh Nagabhushana __u8 nmac1[6]; 638856b2bdd1SGireesh Nagabhushana __be16 idsiiq_pkd; 638956b2bdd1SGireesh Nagabhushana __u8 nmac2[6]; 639056b2bdd1SGireesh Nagabhushana __be16 idseiq_pkd; 639156b2bdd1SGireesh Nagabhushana __u8 nmac3[6]; 639256b2bdd1SGireesh Nagabhushana __be64 r9; 639356b2bdd1SGireesh Nagabhushana __be64 r10; 639456b2bdd1SGireesh Nagabhushana }; 639556b2bdd1SGireesh Nagabhushana 6396*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_PFN 8 6397*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_PFN 0x7 6398*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6399*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_PFN(x) \ 6400*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6401*3dde7c95SVishal Kulkarni 6402*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_VFN 0 6403*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_VFN 0xff 6404*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6405*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_VFN(x) \ 6406*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6407*3dde7c95SVishal Kulkarni 6408*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_ALLOC 31 6409*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_ALLOC 0x1 6410*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6411*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_ALLOC(x) \ 6412*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6413*3dde7c95SVishal Kulkarni #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6414*3dde7c95SVishal Kulkarni 6415*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_FREE 30 6416*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_FREE 0x1 6417*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6418*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_FREE(x) \ 6419*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6420*3dde7c95SVishal Kulkarni #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6421*3dde7c95SVishal Kulkarni 6422*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_TYPE 15 6423*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_TYPE 0x1 6424*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6425*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_TYPE(x) \ 6426*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6427*3dde7c95SVishal Kulkarni #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6428*3dde7c95SVishal Kulkarni 6429*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_FUNC 12 6430*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_FUNC 0x7 6431*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6432*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_FUNC(x) \ 6433*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6434*3dde7c95SVishal Kulkarni 6435*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_VIID 0 6436*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_VIID 0xfff 6437*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6438*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_VIID(x) \ 6439*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6440*3dde7c95SVishal Kulkarni 6441*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_PORTID 4 6442*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_PORTID 0xf 6443*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6444*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_PORTID(x) \ 6445*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6446*3dde7c95SVishal Kulkarni 6447*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_NORSS 11 6448*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_NORSS 0x1 6449*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6450*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_NORSS(x) \ 6451de483253SVishal Kulkarni (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6452*3dde7c95SVishal Kulkarni #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6453*3dde7c95SVishal Kulkarni 6454*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_RSSSIZE 0 6455*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_RSSSIZE 0x7ff 6456*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6457*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_RSSSIZE(x) \ 6458*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6459*3dde7c95SVishal Kulkarni 6460*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_IDSIIQ 0 6461*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_IDSIIQ 0x3ff 6462*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6463*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_IDSIIQ(x) \ 6464*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6465*3dde7c95SVishal Kulkarni 6466*3dde7c95SVishal Kulkarni #define S_FW_VI_CMD_IDSEIQ 0 6467*3dde7c95SVishal Kulkarni #define M_FW_VI_CMD_IDSEIQ 0x3ff 6468*3dde7c95SVishal Kulkarni #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6469*3dde7c95SVishal Kulkarni #define G_FW_VI_CMD_IDSEIQ(x) \ 6470*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 647156b2bdd1SGireesh Nagabhushana 647256b2bdd1SGireesh Nagabhushana /* Special VI_MAC command index ids */ 6473*3dde7c95SVishal Kulkarni #define FW_VI_MAC_ADD_MAC 0x3FF 6474*3dde7c95SVishal Kulkarni #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6475*3dde7c95SVishal Kulkarni #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 647656b2bdd1SGireesh Nagabhushana 647756b2bdd1SGireesh Nagabhushana enum fw_vi_mac_smac { 647856b2bdd1SGireesh Nagabhushana FW_VI_MAC_MPS_TCAM_ENTRY, 647956b2bdd1SGireesh Nagabhushana FW_VI_MAC_MPS_TCAM_ONLY, 648056b2bdd1SGireesh Nagabhushana FW_VI_MAC_SMT_ONLY, 648156b2bdd1SGireesh Nagabhushana FW_VI_MAC_SMT_AND_MPSTCAM 648256b2bdd1SGireesh Nagabhushana }; 648356b2bdd1SGireesh Nagabhushana 648456b2bdd1SGireesh Nagabhushana enum fw_vi_mac_result { 648556b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_SUCCESS, 648656b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 648756b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_SMAC_FAIL, 648856b2bdd1SGireesh Nagabhushana FW_VI_MAC_R_F_ACL_CHECK 648956b2bdd1SGireesh Nagabhushana }; 649056b2bdd1SGireesh Nagabhushana 6491*3dde7c95SVishal Kulkarni enum fw_vi_mac_entry_types { 6492*3dde7c95SVishal Kulkarni FW_VI_MAC_TYPE_EXACTMAC, 6493*3dde7c95SVishal Kulkarni FW_VI_MAC_TYPE_HASHVEC, 6494*3dde7c95SVishal Kulkarni FW_VI_MAC_TYPE_RAW, 6495*3dde7c95SVishal Kulkarni }; 6496*3dde7c95SVishal Kulkarni 649756b2bdd1SGireesh Nagabhushana struct fw_vi_mac_cmd { 649856b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 649956b2bdd1SGireesh Nagabhushana __be32 freemacs_to_len16; 650056b2bdd1SGireesh Nagabhushana union fw_vi_mac { 650156b2bdd1SGireesh Nagabhushana struct fw_vi_mac_exact { 650256b2bdd1SGireesh Nagabhushana __be16 valid_to_idx; 650356b2bdd1SGireesh Nagabhushana __u8 macaddr[6]; 650456b2bdd1SGireesh Nagabhushana } exact[7]; 650556b2bdd1SGireesh Nagabhushana struct fw_vi_mac_hash { 650656b2bdd1SGireesh Nagabhushana __be64 hashvec; 650756b2bdd1SGireesh Nagabhushana } hash; 6508*3dde7c95SVishal Kulkarni struct fw_vi_mac_raw { 6509*3dde7c95SVishal Kulkarni __be32 raw_idx_pkd; 6510*3dde7c95SVishal Kulkarni __be32 data0_pkd; 6511*3dde7c95SVishal Kulkarni __be32 data1[2]; 6512*3dde7c95SVishal Kulkarni __be64 data0m_pkd; 6513*3dde7c95SVishal Kulkarni __be32 data1m[2]; 6514*3dde7c95SVishal Kulkarni } raw; 651556b2bdd1SGireesh Nagabhushana } u; 651656b2bdd1SGireesh Nagabhushana }; 651756b2bdd1SGireesh Nagabhushana 6518*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_VIID 0 6519*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_VIID 0xfff 6520*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6521*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_VIID(x) \ 6522*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6523*3dde7c95SVishal Kulkarni 6524*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_FREEMACS 31 6525*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6526*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6527*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6528*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6529*3dde7c95SVishal Kulkarni #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6530*3dde7c95SVishal Kulkarni 6531*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6532*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6533*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6534*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6535*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6536*3dde7c95SVishal Kulkarni 6537*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6538*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6539*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6540*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6541*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6542*3dde7c95SVishal Kulkarni #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6543*3dde7c95SVishal Kulkarni 6544*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_VALID 15 6545*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_VALID 0x1 6546*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6547*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_VALID(x) \ 6548*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6549*3dde7c95SVishal Kulkarni #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6550*3dde7c95SVishal Kulkarni 6551*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_PRIO 12 6552*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_PRIO 0x7 6553*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6554*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_PRIO(x) \ 6555*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6556*3dde7c95SVishal Kulkarni 6557*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6558*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6559*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6560*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6561*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6562*3dde7c95SVishal Kulkarni 6563*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_IDX 0 6564*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_IDX 0x3ff 6565*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6566*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_IDX(x) \ 6567*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6568*3dde7c95SVishal Kulkarni 6569*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_RAW_IDX 16 6570*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6571*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6572*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6573*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6574*3dde7c95SVishal Kulkarni 6575*3dde7c95SVishal Kulkarni #define S_FW_VI_MAC_CMD_DATA0 0 6576*3dde7c95SVishal Kulkarni #define M_FW_VI_MAC_CMD_DATA0 0xffff 6577*3dde7c95SVishal Kulkarni #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6578*3dde7c95SVishal Kulkarni #define G_FW_VI_MAC_CMD_DATA0(x) \ 6579*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 658056b2bdd1SGireesh Nagabhushana 658156b2bdd1SGireesh Nagabhushana /* T4 max MTU supported */ 6582*3dde7c95SVishal Kulkarni #define T4_MAX_MTU_SUPPORTED 9600 6583*3dde7c95SVishal Kulkarni #define FW_RXMODE_MTU_NO_CHG 65535 658456b2bdd1SGireesh Nagabhushana 658556b2bdd1SGireesh Nagabhushana struct fw_vi_rxmode_cmd { 658656b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 658756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 658856b2bdd1SGireesh Nagabhushana __be32 mtu_to_vlanexen; 658956b2bdd1SGireesh Nagabhushana __be32 r4_lo; 659056b2bdd1SGireesh Nagabhushana }; 659156b2bdd1SGireesh Nagabhushana 6592*3dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_VIID 0 6593*3dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6594*3dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6595*3dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6596*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6597*3dde7c95SVishal Kulkarni 6598*3dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_MTU 16 6599*3dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6600*3dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6601*3dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6602*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6603*3dde7c95SVishal Kulkarni 6604*3dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6605*3dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6606*3dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6607*3dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6608*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6609*3dde7c95SVishal Kulkarni 6610*3dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6611*3dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6612*3dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6613*3dde7c95SVishal Kulkarni ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6614*3dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6615*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6616*3dde7c95SVishal Kulkarni 6617*3dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6618*3dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6619*3dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6620*3dde7c95SVishal Kulkarni ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6621*3dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6622*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6623*3dde7c95SVishal Kulkarni 6624*3dde7c95SVishal Kulkarni #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6625*3dde7c95SVishal Kulkarni #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6626*3dde7c95SVishal Kulkarni #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6627*3dde7c95SVishal Kulkarni #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6628*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 662956b2bdd1SGireesh Nagabhushana 663056b2bdd1SGireesh Nagabhushana struct fw_vi_enable_cmd { 663156b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 663256b2bdd1SGireesh Nagabhushana __be32 ien_to_len16; 663356b2bdd1SGireesh Nagabhushana __be16 blinkdur; 663456b2bdd1SGireesh Nagabhushana __be16 r3; 663556b2bdd1SGireesh Nagabhushana __be32 r4; 663656b2bdd1SGireesh Nagabhushana }; 663756b2bdd1SGireesh Nagabhushana 6638*3dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_VIID 0 6639*3dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6640*3dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6641*3dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6642*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6643*3dde7c95SVishal Kulkarni 6644*3dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_IEN 31 6645*3dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_IEN 0x1 6646*3dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6647*3dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6648*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6649*3dde7c95SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6650*3dde7c95SVishal Kulkarni 6651*3dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_EEN 30 6652*3dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_EEN 0x1 6653*3dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6654*3dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6655*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6656*3dde7c95SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6657*3dde7c95SVishal Kulkarni 6658*3dde7c95SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_LED 29 6659*3dde7c95SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_LED 0x1 6660*3dde7c95SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6661*3dde7c95SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_LED(x) \ 6662*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6663*3dde7c95SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 666456b2bdd1SGireesh Nagabhushana 6665de483253SVishal Kulkarni #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6666de483253SVishal Kulkarni #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6667de483253SVishal Kulkarni #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6668de483253SVishal Kulkarni #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6669de483253SVishal Kulkarni (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6670de483253SVishal Kulkarni #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6671de483253SVishal Kulkarni 667256b2bdd1SGireesh Nagabhushana /* VI VF stats offset definitions */ 6673*3dde7c95SVishal Kulkarni #define VI_VF_NUM_STATS 16 667456b2bdd1SGireesh Nagabhushana enum fw_vi_stats_vf_index { 667556b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 667656b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 667756b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 667856b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 667956b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 668056b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 668156b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 668256b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 668356b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 668456b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 668556b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 668656b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 668756b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 668856b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 668956b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 669056b2bdd1SGireesh Nagabhushana FW_VI_VF_STAT_RX_ERR_FRAMES_IX 669156b2bdd1SGireesh Nagabhushana }; 669256b2bdd1SGireesh Nagabhushana 669356b2bdd1SGireesh Nagabhushana /* VI PF stats offset definitions */ 6694*3dde7c95SVishal Kulkarni #define VI_PF_NUM_STATS 17 669556b2bdd1SGireesh Nagabhushana enum fw_vi_stats_pf_index { 669656b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 669756b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 669856b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 669956b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 670056b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 670156b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 670256b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 670356b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 670456b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BYTES_IX, 670556b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_FRAMES_IX, 670656b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 670756b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 670856b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 670956b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 671056b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 671156b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 671256b2bdd1SGireesh Nagabhushana FW_VI_PF_STAT_RX_ERR_FRAMES_IX 671356b2bdd1SGireesh Nagabhushana }; 671456b2bdd1SGireesh Nagabhushana 671556b2bdd1SGireesh Nagabhushana struct fw_vi_stats_cmd { 671656b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 671756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 671856b2bdd1SGireesh Nagabhushana union fw_vi_stats { 671956b2bdd1SGireesh Nagabhushana struct fw_vi_stats_ctl { 672056b2bdd1SGireesh Nagabhushana __be16 nstats_ix; 672156b2bdd1SGireesh Nagabhushana __be16 r6; 672256b2bdd1SGireesh Nagabhushana __be32 r7; 672356b2bdd1SGireesh Nagabhushana __be64 stat0; 672456b2bdd1SGireesh Nagabhushana __be64 stat1; 672556b2bdd1SGireesh Nagabhushana __be64 stat2; 672656b2bdd1SGireesh Nagabhushana __be64 stat3; 672756b2bdd1SGireesh Nagabhushana __be64 stat4; 672856b2bdd1SGireesh Nagabhushana __be64 stat5; 672956b2bdd1SGireesh Nagabhushana } ctl; 673056b2bdd1SGireesh Nagabhushana struct fw_vi_stats_pf { 673156b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 673256b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 673356b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 673456b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 673556b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 673656b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 673756b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 673856b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 673956b2bdd1SGireesh Nagabhushana __be64 rx_pf_bytes; 674056b2bdd1SGireesh Nagabhushana __be64 rx_pf_frames; 674156b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 674256b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 674356b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 674456b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 674556b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 674656b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 674756b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 674856b2bdd1SGireesh Nagabhushana } pf; 674956b2bdd1SGireesh Nagabhushana struct fw_vi_stats_vf { 675056b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 675156b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 675256b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 675356b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 675456b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 675556b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 675656b2bdd1SGireesh Nagabhushana __be64 tx_drop_frames; 675756b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 675856b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 675956b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 676056b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 676156b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 676256b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 676356b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 676456b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 676556b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 676656b2bdd1SGireesh Nagabhushana } vf; 676756b2bdd1SGireesh Nagabhushana } u; 676856b2bdd1SGireesh Nagabhushana }; 676956b2bdd1SGireesh Nagabhushana 6770*3dde7c95SVishal Kulkarni #define S_FW_VI_STATS_CMD_VIID 0 6771*3dde7c95SVishal Kulkarni #define M_FW_VI_STATS_CMD_VIID 0xfff 6772*3dde7c95SVishal Kulkarni #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6773*3dde7c95SVishal Kulkarni #define G_FW_VI_STATS_CMD_VIID(x) \ 6774*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 677556b2bdd1SGireesh Nagabhushana 6776*3dde7c95SVishal Kulkarni #define S_FW_VI_STATS_CMD_NSTATS 12 6777*3dde7c95SVishal Kulkarni #define M_FW_VI_STATS_CMD_NSTATS 0x7 6778*3dde7c95SVishal Kulkarni #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6779*3dde7c95SVishal Kulkarni #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6780*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 678156b2bdd1SGireesh Nagabhushana 6782*3dde7c95SVishal Kulkarni #define S_FW_VI_STATS_CMD_IX 0 6783*3dde7c95SVishal Kulkarni #define M_FW_VI_STATS_CMD_IX 0x1f 6784*3dde7c95SVishal Kulkarni #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6785*3dde7c95SVishal Kulkarni #define G_FW_VI_STATS_CMD_IX(x) \ 6786*3dde7c95SVishal Kulkarni (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 678756b2bdd1SGireesh Nagabhushana 678856b2bdd1SGireesh Nagabhushana struct fw_acl_mac_cmd { 678956b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 679056b2bdd1SGireesh Nagabhushana __be32 en_to_len16; 679156b2bdd1SGireesh Nagabhushana __u8 nmac; 679256b2bdd1SGireesh Nagabhushana __u8 r3[7]; 679356b2bdd1SGireesh Nagabhushana __be16 r4; 679456b2bdd1SGireesh Nagabhushana __u8 macaddr0[6]; 679556b2bdd1SGireesh Nagabhushana __be16 r5; 679656b2bdd1SGireesh Nagabhushana __u8 macaddr1[6]; 679756b2bdd1SGireesh Nagabhushana __be16 r6; 679856b2bdd1SGireesh Nagabhushana __u8 macaddr2[6]; 679956b2bdd1SGireesh Nagabhushana __be16 r7; 680056b2bdd1SGireesh Nagabhushana __u8 macaddr3[6]; 680156b2bdd1SGireesh Nagabhushana }; 680256b2bdd1SGireesh Nagabhushana 6803*3dde7c95SVishal Kulkarni #define S_FW_ACL_MAC_CMD_PFN 8 6804*3dde7c95SVishal Kulkarni #define M_FW_ACL_MAC_CMD_PFN 0x7 6805*3dde7c95SVishal Kulkarni #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6806*3dde7c95SVishal Kulkarni #define G_FW_ACL_MAC_CMD_PFN(x) \ 6807*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 680856b2bdd1SGireesh Nagabhushana 6809*3dde7c95SVishal Kulkarni #define S_FW_ACL_MAC_CMD_VFN 0 6810*3dde7c95SVishal Kulkarni #define M_FW_ACL_MAC_CMD_VFN 0xff 6811*3dde7c95SVishal Kulkarni #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6812*3dde7c95SVishal Kulkarni #define G_FW_ACL_MAC_CMD_VFN(x) \ 6813*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 681456b2bdd1SGireesh Nagabhushana 6815*3dde7c95SVishal Kulkarni #define S_FW_ACL_MAC_CMD_EN 31 6816*3dde7c95SVishal Kulkarni #define M_FW_ACL_MAC_CMD_EN 0x1 6817*3dde7c95SVishal Kulkarni #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6818*3dde7c95SVishal Kulkarni #define G_FW_ACL_MAC_CMD_EN(x) \ 6819*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6820*3dde7c95SVishal Kulkarni #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 682156b2bdd1SGireesh Nagabhushana 682256b2bdd1SGireesh Nagabhushana struct fw_acl_vlan_cmd { 682356b2bdd1SGireesh Nagabhushana __be32 op_to_vfn; 682456b2bdd1SGireesh Nagabhushana __be32 en_to_len16; 682556b2bdd1SGireesh Nagabhushana __u8 nvlan; 682656b2bdd1SGireesh Nagabhushana __u8 dropnovlan_fm; 682756b2bdd1SGireesh Nagabhushana __u8 r3_lo[6]; 682856b2bdd1SGireesh Nagabhushana __be16 vlanid[16]; 682956b2bdd1SGireesh Nagabhushana }; 683056b2bdd1SGireesh Nagabhushana 6831*3dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_PFN 8 6832*3dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_PFN 0x7 6833*3dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6834*3dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6835*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6836*3dde7c95SVishal Kulkarni 6837*3dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_VFN 0 6838*3dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_VFN 0xff 6839*3dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6840*3dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_VFN(x) \ 6841*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6842*3dde7c95SVishal Kulkarni 6843*3dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_EN 31 6844*3dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_EN 0x1 6845*3dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6846*3dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_EN(x) \ 6847*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6848*3dde7c95SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6849*3dde7c95SVishal Kulkarni 6850*3dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6851*3dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6852*3dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6853*3dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6854*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6855*3dde7c95SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6856*3dde7c95SVishal Kulkarni 6857*3dde7c95SVishal Kulkarni #define S_FW_ACL_VLAN_CMD_FM 6 6858*3dde7c95SVishal Kulkarni #define M_FW_ACL_VLAN_CMD_FM 0x1 6859*3dde7c95SVishal Kulkarni #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6860*3dde7c95SVishal Kulkarni #define G_FW_ACL_VLAN_CMD_FM(x) \ 6861*3dde7c95SVishal Kulkarni (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6862*3dde7c95SVishal Kulkarni #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 686356b2bdd1SGireesh Nagabhushana 686456b2bdd1SGireesh Nagabhushana /* port capabilities bitmap */ 686556b2bdd1SGireesh Nagabhushana enum fw_port_cap { 686656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_100M = 0x0001, 686756b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_1G = 0x0002, 6868*3dde7c95SVishal Kulkarni FW_PORT_CAP_SPEED_25G = 0x0004, 686956b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_10G = 0x0008, 687056b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_40G = 0x0010, 687156b2bdd1SGireesh Nagabhushana FW_PORT_CAP_SPEED_100G = 0x0020, 687256b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FC_RX = 0x0040, 687356b2bdd1SGireesh Nagabhushana FW_PORT_CAP_FC_TX = 0x0080, 687456b2bdd1SGireesh Nagabhushana FW_PORT_CAP_ANEG = 0x0100, 687556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDIX = 0x0200, 687656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDIAUTO = 0x0400, 6877*3dde7c95SVishal Kulkarni FW_PORT_CAP_FEC_RS = 0x0800, 6878*3dde7c95SVishal Kulkarni FW_PORT_CAP_FEC_BASER_RS = 0x1000, 6879*3dde7c95SVishal Kulkarni FW_PORT_CAP_FEC_RESERVED = 0x2000, 6880*3dde7c95SVishal Kulkarni FW_PORT_CAP_802_3_PAUSE = 0x4000, 6881*3dde7c95SVishal Kulkarni FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6882*3dde7c95SVishal Kulkarni }; 6883*3dde7c95SVishal Kulkarni 6884*3dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_SPEED 0 6885*3dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_SPEED 0x3f 6886*3dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6887*3dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_SPEED(x) \ 6888*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6889*3dde7c95SVishal Kulkarni 6890*3dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_FC 6 6891*3dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_FC 0x3 6892*3dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6893*3dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_FC(x) \ 6894*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6895*3dde7c95SVishal Kulkarni 6896*3dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_ANEG 8 6897*3dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_ANEG 0x1 6898*3dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6899*3dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_ANEG(x) \ 6900*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6901*3dde7c95SVishal Kulkarni 6902*3dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_FEC 11 6903*3dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_FEC 0x7 6904*3dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 6905*3dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_FEC(x) \ 6906*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 6907*3dde7c95SVishal Kulkarni 6908*3dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_802_3 14 6909*3dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_802_3 0x3 6910*3dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 6911*3dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_802_3(x) \ 6912*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 691356b2bdd1SGireesh Nagabhushana 691456b2bdd1SGireesh Nagabhushana enum fw_port_mdi { 691556b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_UNCHANGED, 691656b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_AUTO, 691756b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_F_STRAIGHT, 691856b2bdd1SGireesh Nagabhushana FW_PORT_CAP_MDI_F_CROSSOVER 691956b2bdd1SGireesh Nagabhushana }; 692056b2bdd1SGireesh Nagabhushana 6921*3dde7c95SVishal Kulkarni #define S_FW_PORT_CAP_MDI 9 6922*3dde7c95SVishal Kulkarni #define M_FW_PORT_CAP_MDI 3 6923*3dde7c95SVishal Kulkarni #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 6924*3dde7c95SVishal Kulkarni #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 6925*3dde7c95SVishal Kulkarni 6926*3dde7c95SVishal Kulkarni #define S_FW_PORT_AUXLINFO_KX4 2 6927*3dde7c95SVishal Kulkarni #define M_FW_PORT_AUXLINFO_KX4 0x1 6928*3dde7c95SVishal Kulkarni #define V_FW_PORT_AUXLINFO_KX4(x) \ 6929*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_AUXLINFO_KX4) 6930*3dde7c95SVishal Kulkarni #define G_FW_PORT_AUXLINFO_KX4(x) \ 6931*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 6932*3dde7c95SVishal Kulkarni #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 6933*3dde7c95SVishal Kulkarni 6934*3dde7c95SVishal Kulkarni #define S_FW_PORT_AUXLINFO_KR 1 6935*3dde7c95SVishal Kulkarni #define M_FW_PORT_AUXLINFO_KR 0x1 6936*3dde7c95SVishal Kulkarni #define V_FW_PORT_AUXLINFO_KR(x) \ 6937*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_AUXLINFO_KR) 6938*3dde7c95SVishal Kulkarni #define G_FW_PORT_AUXLINFO_KR(x) \ 6939*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 6940*3dde7c95SVishal Kulkarni #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 694156b2bdd1SGireesh Nagabhushana 694256b2bdd1SGireesh Nagabhushana enum fw_port_action { 694356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_CFG = 0x0001, 694456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_CFG = 0x0002, 694556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 694656b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 694756b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 6948de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 6949de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 6950de483253SVishal Kulkarni FW_PORT_ACTION_DCB_READ_DET = 0x0008, 695156b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 695256b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 695356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 695456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 6955*3dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 6956*3dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 6957*3dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 6958*3dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 6959de483253SVishal Kulkarni FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 6960*3dde7c95SVishal Kulkarni FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 696156b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PHY_RESET = 0x0040, 696256b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PMA_RESET = 0x0041, 696356b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PCS_RESET = 0x0042, 696456b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_PHYXS_RESET = 0x0043, 696556b2bdd1SGireesh Nagabhushana FW_PORT_ACTION_DTEXS_REEST = 0x0044, 6966de483253SVishal Kulkarni FW_PORT_ACTION_AN_RESET = 0x0045, 6967*3dde7c95SVishal Kulkarni 696856b2bdd1SGireesh Nagabhushana }; 696956b2bdd1SGireesh Nagabhushana 697056b2bdd1SGireesh Nagabhushana enum fw_port_l2cfg_ctlbf { 697156b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 697256b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 697356b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 697456b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 697556b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_IVLAN = 0x10, 697656b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_TXIPG = 0x20, 697756b2bdd1SGireesh Nagabhushana FW_PORT_L2_CTLBF_MTU = 0x40 697856b2bdd1SGireesh Nagabhushana }; 697956b2bdd1SGireesh Nagabhushana 6980*3dde7c95SVishal Kulkarni enum fw_dcb_app_tlv_sf { 6981*3dde7c95SVishal Kulkarni FW_DCB_APP_SF_ETHERTYPE, 6982*3dde7c95SVishal Kulkarni FW_DCB_APP_SF_SOCKET_TCP, 6983*3dde7c95SVishal Kulkarni FW_DCB_APP_SF_SOCKET_UDP, 6984*3dde7c95SVishal Kulkarni FW_DCB_APP_SF_SOCKET_ALL, 6985*3dde7c95SVishal Kulkarni }; 6986*3dde7c95SVishal Kulkarni 6987*3dde7c95SVishal Kulkarni enum fw_port_dcb_versions { 6988*3dde7c95SVishal Kulkarni FW_PORT_DCB_VER_UNKNOWN, 6989*3dde7c95SVishal Kulkarni FW_PORT_DCB_VER_CEE1D0, 6990*3dde7c95SVishal Kulkarni FW_PORT_DCB_VER_CEE1D01, 6991*3dde7c95SVishal Kulkarni FW_PORT_DCB_VER_IEEE, 6992*3dde7c95SVishal Kulkarni FW_PORT_DCB_VER_AUTO=7 6993*3dde7c95SVishal Kulkarni }; 6994*3dde7c95SVishal Kulkarni 699556b2bdd1SGireesh Nagabhushana enum fw_port_dcb_cfg { 699656b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_PG = 0x01, 699756b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_PFC = 0x02, 699856b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_APPL = 0x04 699956b2bdd1SGireesh Nagabhushana }; 700056b2bdd1SGireesh Nagabhushana 700156b2bdd1SGireesh Nagabhushana enum fw_port_dcb_cfg_rc { 700256b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_SUCCESS = 0x0, 700356b2bdd1SGireesh Nagabhushana FW_PORT_DCB_CFG_ERROR = 0x1 700456b2bdd1SGireesh Nagabhushana }; 700556b2bdd1SGireesh Nagabhushana 700656b2bdd1SGireesh Nagabhushana enum fw_port_dcb_type { 700756b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PGID = 0x00, 700856b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PGRATE = 0x01, 700956b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PRIORATE = 0x02, 701056b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_PFC = 0x03, 701156b2bdd1SGireesh Nagabhushana FW_PORT_DCB_TYPE_APP_ID = 0x04, 7012*3dde7c95SVishal Kulkarni FW_PORT_DCB_TYPE_CONTROL = 0x05, 7013*3dde7c95SVishal Kulkarni }; 7014*3dde7c95SVishal Kulkarni 7015*3dde7c95SVishal Kulkarni enum fw_port_dcb_feature_state { 7016*3dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7017*3dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7018*3dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7019*3dde7c95SVishal Kulkarni FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7020de483253SVishal Kulkarni }; 7021de483253SVishal Kulkarni 7022de483253SVishal Kulkarni enum fw_port_diag_ops { 7023de483253SVishal Kulkarni FW_PORT_DIAGS_TEMP = 0x00, 7024de483253SVishal Kulkarni FW_PORT_DIAGS_TX_POWER = 0x01, 7025de483253SVishal Kulkarni FW_PORT_DIAGS_RX_POWER = 0x02, 7026*3dde7c95SVishal Kulkarni FW_PORT_DIAGS_TX_DIS = 0x03, 702756b2bdd1SGireesh Nagabhushana }; 702856b2bdd1SGireesh Nagabhushana 702956b2bdd1SGireesh Nagabhushana struct fw_port_cmd { 703056b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 703156b2bdd1SGireesh Nagabhushana __be32 action_to_len16; 703256b2bdd1SGireesh Nagabhushana union fw_port { 703356b2bdd1SGireesh Nagabhushana struct fw_port_l1cfg { 703456b2bdd1SGireesh Nagabhushana __be32 rcap; 703556b2bdd1SGireesh Nagabhushana __be32 r; 703656b2bdd1SGireesh Nagabhushana } l1cfg; 703756b2bdd1SGireesh Nagabhushana struct fw_port_l2cfg { 703856b2bdd1SGireesh Nagabhushana __u8 ctlbf; 703956b2bdd1SGireesh Nagabhushana __u8 ovlan3_to_ivlan0; 704056b2bdd1SGireesh Nagabhushana __be16 ivlantype; 704156b2bdd1SGireesh Nagabhushana __be16 txipg_force_pinfo; 704256b2bdd1SGireesh Nagabhushana __be16 mtu; 704356b2bdd1SGireesh Nagabhushana __be16 ovlan0mask; 704456b2bdd1SGireesh Nagabhushana __be16 ovlan0type; 704556b2bdd1SGireesh Nagabhushana __be16 ovlan1mask; 704656b2bdd1SGireesh Nagabhushana __be16 ovlan1type; 704756b2bdd1SGireesh Nagabhushana __be16 ovlan2mask; 704856b2bdd1SGireesh Nagabhushana __be16 ovlan2type; 704956b2bdd1SGireesh Nagabhushana __be16 ovlan3mask; 705056b2bdd1SGireesh Nagabhushana __be16 ovlan3type; 705156b2bdd1SGireesh Nagabhushana } l2cfg; 705256b2bdd1SGireesh Nagabhushana struct fw_port_info { 705356b2bdd1SGireesh Nagabhushana __be32 lstatus_to_modtype; 705456b2bdd1SGireesh Nagabhushana __be16 pcap; 705556b2bdd1SGireesh Nagabhushana __be16 acap; 705656b2bdd1SGireesh Nagabhushana __be16 mtu; 705756b2bdd1SGireesh Nagabhushana __u8 cbllen; 705856b2bdd1SGireesh Nagabhushana __u8 auxlinfo; 7059*3dde7c95SVishal Kulkarni __u8 dcbxdis_pkd; 7060*3dde7c95SVishal Kulkarni __u8 r8_lo; 7061*3dde7c95SVishal Kulkarni __be16 lpacap; 706256b2bdd1SGireesh Nagabhushana __be64 r9; 706356b2bdd1SGireesh Nagabhushana } info; 7064de483253SVishal Kulkarni struct fw_port_diags { 7065de483253SVishal Kulkarni __u8 diagop; 7066de483253SVishal Kulkarni __u8 r[3]; 7067de483253SVishal Kulkarni __be32 diagval; 7068de483253SVishal Kulkarni } diags; 706956b2bdd1SGireesh Nagabhushana union fw_port_dcb { 707056b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pgid { 707156b2bdd1SGireesh Nagabhushana __u8 type; 707256b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 707356b2bdd1SGireesh Nagabhushana __u8 r10_lo[2]; 707456b2bdd1SGireesh Nagabhushana __be32 pgid; 707556b2bdd1SGireesh Nagabhushana __be64 r11; 707656b2bdd1SGireesh Nagabhushana } pgid; 707756b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pgrate { 707856b2bdd1SGireesh Nagabhushana __u8 type; 707956b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 708056b2bdd1SGireesh Nagabhushana __u8 r10_lo[5]; 708156b2bdd1SGireesh Nagabhushana __u8 num_tcs_supported; 708256b2bdd1SGireesh Nagabhushana __u8 pgrate[8]; 7083*3dde7c95SVishal Kulkarni __u8 tsa[8]; 708456b2bdd1SGireesh Nagabhushana } pgrate; 708556b2bdd1SGireesh Nagabhushana struct fw_port_dcb_priorate { 708656b2bdd1SGireesh Nagabhushana __u8 type; 708756b2bdd1SGireesh Nagabhushana __u8 apply_pkd; 708856b2bdd1SGireesh Nagabhushana __u8 r10_lo[6]; 708956b2bdd1SGireesh Nagabhushana __u8 strict_priorate[8]; 709056b2bdd1SGireesh Nagabhushana } priorate; 709156b2bdd1SGireesh Nagabhushana struct fw_port_dcb_pfc { 709256b2bdd1SGireesh Nagabhushana __u8 type; 709356b2bdd1SGireesh Nagabhushana __u8 pfcen; 7094*3dde7c95SVishal Kulkarni __u8 r10[5]; 7095*3dde7c95SVishal Kulkarni __u8 max_pfc_tcs; 709656b2bdd1SGireesh Nagabhushana __be64 r11; 709756b2bdd1SGireesh Nagabhushana } pfc; 709856b2bdd1SGireesh Nagabhushana struct fw_port_app_priority { 709956b2bdd1SGireesh Nagabhushana __u8 type; 710056b2bdd1SGireesh Nagabhushana __u8 r10[2]; 710156b2bdd1SGireesh Nagabhushana __u8 idx; 710256b2bdd1SGireesh Nagabhushana __u8 user_prio_map; 710356b2bdd1SGireesh Nagabhushana __u8 sel_field; 710456b2bdd1SGireesh Nagabhushana __be16 protocolid; 710556b2bdd1SGireesh Nagabhushana __be64 r12; 710656b2bdd1SGireesh Nagabhushana } app_priority; 7107de483253SVishal Kulkarni struct fw_port_dcb_control { 7108de483253SVishal Kulkarni __u8 type; 7109de483253SVishal Kulkarni __u8 all_syncd_pkd; 7110*3dde7c95SVishal Kulkarni __be16 dcb_version_to_app_state; 7111*3dde7c95SVishal Kulkarni __be32 r11; 7112*3dde7c95SVishal Kulkarni __be64 r12; 7113de483253SVishal Kulkarni } control; 711456b2bdd1SGireesh Nagabhushana } dcb; 711556b2bdd1SGireesh Nagabhushana } u; 711656b2bdd1SGireesh Nagabhushana }; 711756b2bdd1SGireesh Nagabhushana 7118*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_READ 22 7119*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_READ 0x1 7120*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7121*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_READ(x) \ 7122*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7123*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7124*3dde7c95SVishal Kulkarni 7125*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_PORTID 0 7126*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_PORTID 0xf 7127*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7128*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_PORTID(x) \ 7129*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7130*3dde7c95SVishal Kulkarni 7131*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_ACTION 16 7132*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_ACTION 0xffff 7133*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7134*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_ACTION(x) \ 7135*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7136*3dde7c95SVishal Kulkarni 7137*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN3 7 7138*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN3 0x1 7139*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7140*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN3(x) \ 7141*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7142*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7143*3dde7c95SVishal Kulkarni 7144*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN2 6 7145*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN2 0x1 7146*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7147*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN2(x) \ 7148*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7149*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7150*3dde7c95SVishal Kulkarni 7151*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN1 5 7152*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN1 0x1 7153*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7154*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN1(x) \ 7155*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7156*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7157*3dde7c95SVishal Kulkarni 7158*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_OVLAN0 4 7159*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_OVLAN0 0x1 7160*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7161*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_OVLAN0(x) \ 7162*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7163*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7164*3dde7c95SVishal Kulkarni 7165*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_IVLAN0 3 7166*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_IVLAN0 0x1 7167*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7168*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_IVLAN0(x) \ 7169*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7170*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7171*3dde7c95SVishal Kulkarni 7172*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_TXIPG 3 7173*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_TXIPG 0x1fff 7174*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7175*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_TXIPG(x) \ 7176*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7177*3dde7c95SVishal Kulkarni 7178*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_FORCE_PINFO 0 7179*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7180*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7181*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7182*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7183*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7184*3dde7c95SVishal Kulkarni 7185*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LSTATUS 31 7186*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LSTATUS 0x1 7187*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7188*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LSTATUS(x) \ 7189*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7190*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7191*3dde7c95SVishal Kulkarni 7192*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LSPEED 24 7193*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LSPEED 0x3f 7194*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7195*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LSPEED(x) \ 7196*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7197*3dde7c95SVishal Kulkarni 7198*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_TXPAUSE 23 7199*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_TXPAUSE 0x1 7200*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7201*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_TXPAUSE(x) \ 7202*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7203*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7204*3dde7c95SVishal Kulkarni 7205*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_RXPAUSE 22 7206*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_RXPAUSE 0x1 7207*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7208*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_RXPAUSE(x) \ 7209*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7210*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7211*3dde7c95SVishal Kulkarni 7212*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_MDIOCAP 21 7213*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_MDIOCAP 0x1 7214*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7215*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_MDIOCAP(x) \ 7216*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7217*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7218*3dde7c95SVishal Kulkarni 7219*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_MDIOADDR 16 7220*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_MDIOADDR 0x1f 7221*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7222*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_MDIOADDR(x) \ 7223*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7224*3dde7c95SVishal Kulkarni 7225*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LPTXPAUSE 15 7226*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7227*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7228*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7229*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7230*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7231*3dde7c95SVishal Kulkarni 7232*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LPRXPAUSE 14 7233*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7234*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7235*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7236*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7237*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7238*3dde7c95SVishal Kulkarni 7239*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_PTYPE 8 7240*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_PTYPE 0x1f 7241*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7242*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_PTYPE(x) \ 7243*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7244*3dde7c95SVishal Kulkarni 7245*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_LINKDNRC 5 7246*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_LINKDNRC 0x7 7247*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7248*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_LINKDNRC(x) \ 7249*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7250*3dde7c95SVishal Kulkarni 7251*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_MODTYPE 0 7252*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_MODTYPE 0x1f 7253*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7254*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_MODTYPE(x) \ 7255*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7256*3dde7c95SVishal Kulkarni 7257*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_DCBXDIS 7 7258*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_DCBXDIS 0x1 7259*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7260*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_DCBXDIS(x) \ 7261*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7262*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7263*3dde7c95SVishal Kulkarni 7264*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_APPLY 7 7265*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_APPLY 0x1 7266*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7267*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_APPLY(x) \ 7268*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7269*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 727056b2bdd1SGireesh Nagabhushana 7271de483253SVishal Kulkarni #define S_FW_PORT_CMD_ALL_SYNCD 7 7272de483253SVishal Kulkarni #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7273de483253SVishal Kulkarni #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7274de483253SVishal Kulkarni #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7275de483253SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7276*3dde7c95SVishal Kulkarni #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7277*3dde7c95SVishal Kulkarni 7278*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_DCB_VERSION 12 7279*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_DCB_VERSION 0x7 7280*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7281*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7282*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7283*3dde7c95SVishal Kulkarni 7284*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_PFC_STATE 8 7285*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_PFC_STATE 0xf 7286*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7287*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_PFC_STATE(x) \ 7288*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7289*3dde7c95SVishal Kulkarni 7290*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_ETS_STATE 4 7291*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_ETS_STATE 0xf 7292*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7293*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_ETS_STATE(x) \ 7294*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7295*3dde7c95SVishal Kulkarni 7296*3dde7c95SVishal Kulkarni #define S_FW_PORT_CMD_APP_STATE 0 7297*3dde7c95SVishal Kulkarni #define M_FW_PORT_CMD_APP_STATE 0xf 7298*3dde7c95SVishal Kulkarni #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7299*3dde7c95SVishal Kulkarni #define G_FW_PORT_CMD_APP_STATE(x) \ 7300*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7301de483253SVishal Kulkarni 730256b2bdd1SGireesh Nagabhushana /* 730356b2bdd1SGireesh Nagabhushana * These are configured into the VPD and hence tools that generate 730456b2bdd1SGireesh Nagabhushana * VPD may use this enumeration. 730556b2bdd1SGireesh Nagabhushana * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7306*3dde7c95SVishal Kulkarni * 7307*3dde7c95SVishal Kulkarni * REMEMBER: 7308*3dde7c95SVishal Kulkarni * Update the Common Code t4_hw.c:t4_get_port_type_description() 7309*3dde7c95SVishal Kulkarni * with any new Firmware Port Technology Types! 731056b2bdd1SGireesh Nagabhushana */ 731156b2bdd1SGireesh Nagabhushana enum fw_port_type { 731256b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 731356b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 731456b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7315*3dde7c95SVishal Kulkarni FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7316*3dde7c95SVishal Kulkarni FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 731756b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 731856b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 731956b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 732056b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 732156b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7322*3dde7c95SVishal Kulkarni FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7323*3dde7c95SVishal Kulkarni FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7324de483253SVishal Kulkarni FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7325*3dde7c95SVishal Kulkarni FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7326de483253SVishal Kulkarni FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7327*3dde7c95SVishal Kulkarni FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7328*3dde7c95SVishal Kulkarni FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7329*3dde7c95SVishal Kulkarni FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7330*3dde7c95SVishal Kulkarni FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7331*3dde7c95SVishal Kulkarni FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7332*3dde7c95SVishal Kulkarni FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7333*3dde7c95SVishal Kulkarni FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 733456b2bdd1SGireesh Nagabhushana FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 733556b2bdd1SGireesh Nagabhushana }; 733656b2bdd1SGireesh Nagabhushana 7337*3dde7c95SVishal Kulkarni /* These are read from module's EEPROM and determined once the 7338*3dde7c95SVishal Kulkarni module is inserted. */ 733956b2bdd1SGireesh Nagabhushana enum fw_port_module_type { 734056b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NA = 0x0, 734156b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_LR = 0x1, 734256b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_SR = 0x2, 734356b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_ER = 0x3, 734456b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 734556b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 734656b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_LRM = 0x6, 734756b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 734856b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 734956b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 735056b2bdd1SGireesh Nagabhushana FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 735156b2bdd1SGireesh Nagabhushana }; 735256b2bdd1SGireesh Nagabhushana 735356b2bdd1SGireesh Nagabhushana /* used by FW and tools may use this to generate VPD */ 735456b2bdd1SGireesh Nagabhushana enum fw_port_mod_sub_type { 735556b2bdd1SGireesh Nagabhushana FW_PORT_MOD_SUB_TYPE_NA, 7356*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7357*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7358*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7359*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7360*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7361*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7362*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7363*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 736456b2bdd1SGireesh Nagabhushana 736556b2bdd1SGireesh Nagabhushana /* 736656b2bdd1SGireesh Nagabhushana * The following will never been in the VPD. They are TWINAX cable 736756b2bdd1SGireesh Nagabhushana * lengths decoded from SFP+ module i2c PROMs. These should almost 736856b2bdd1SGireesh Nagabhushana * certainly go somewhere else ... 736956b2bdd1SGireesh Nagabhushana */ 7370*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7371*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7372*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7373*3dde7c95SVishal Kulkarni FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 737456b2bdd1SGireesh Nagabhushana }; 737556b2bdd1SGireesh Nagabhushana 737656b2bdd1SGireesh Nagabhushana /* link down reason codes (3b) */ 737756b2bdd1SGireesh Nagabhushana enum fw_port_link_dn_rc { 737856b2bdd1SGireesh Nagabhushana FW_PORT_LINK_DN_RC_NONE, 7379de483253SVishal Kulkarni FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7380de483253SVishal Kulkarni FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7381de483253SVishal Kulkarni FW_PORT_LINK_DN_RESERVED3, 7382de483253SVishal Kulkarni FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7383de483253SVishal Kulkarni FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7384de483253SVishal Kulkarni FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7385de483253SVishal Kulkarni FW_PORT_LINK_DN_RESERVED7 738656b2bdd1SGireesh Nagabhushana }; 738756b2bdd1SGireesh Nagabhushana enum fw_port_stats_tx_index { 7388*3dde7c95SVishal Kulkarni FW_STAT_TX_PORT_BYTES_IX = 0, 738956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_FRAMES_IX, 739056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_BCAST_IX, 739156b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_MCAST_IX, 739256b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_UCAST_IX, 739356b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_ERROR_IX, 739456b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_64B_IX, 739556b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_65B_127B_IX, 739656b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_128B_255B_IX, 739756b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_256B_511B_IX, 739856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_512B_1023B_IX, 739956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_1024B_1518B_IX, 740056b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_1519B_MAX_IX, 740156b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_DROP_IX, 740256b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PAUSE_IX, 740356b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP0_IX, 740456b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP1_IX, 740556b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP2_IX, 740656b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP3_IX, 740756b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP4_IX, 740856b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP5_IX, 740956b2bdd1SGireesh Nagabhushana FW_STAT_TX_PORT_PPP6_IX, 7410*3dde7c95SVishal Kulkarni FW_STAT_TX_PORT_PPP7_IX, 7411*3dde7c95SVishal Kulkarni FW_NUM_PORT_TX_STATS 741256b2bdd1SGireesh Nagabhushana }; 741356b2bdd1SGireesh Nagabhushana 741456b2bdd1SGireesh Nagabhushana enum fw_port_stat_rx_index { 7415*3dde7c95SVishal Kulkarni FW_STAT_RX_PORT_BYTES_IX = 0, 741656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_FRAMES_IX, 741756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_BCAST_IX, 741856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MCAST_IX, 741956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_UCAST_IX, 742056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MTU_ERROR_IX, 742156b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 742256b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_CRC_ERROR_IX, 742356b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_LEN_ERROR_IX, 742456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_SYM_ERROR_IX, 742556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_64B_IX, 742656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_65B_127B_IX, 742756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_128B_255B_IX, 742856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_256B_511B_IX, 742956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_512B_1023B_IX, 743056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_1024B_1518B_IX, 743156b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_1519B_MAX_IX, 743256b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PAUSE_IX, 743356b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP0_IX, 743456b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP1_IX, 743556b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP2_IX, 743656b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP3_IX, 743756b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP4_IX, 743856b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP5_IX, 743956b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP6_IX, 744056b2bdd1SGireesh Nagabhushana FW_STAT_RX_PORT_PPP7_IX, 7441*3dde7c95SVishal Kulkarni FW_STAT_RX_PORT_LESS_64B_IX, 7442*3dde7c95SVishal Kulkarni FW_STAT_RX_PORT_MAC_ERROR_IX, 7443*3dde7c95SVishal Kulkarni FW_NUM_PORT_RX_STATS 744456b2bdd1SGireesh Nagabhushana }; 7445*3dde7c95SVishal Kulkarni /* port stats */ 7446*3dde7c95SVishal Kulkarni #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7447*3dde7c95SVishal Kulkarni FW_NUM_PORT_RX_STATS) 7448*3dde7c95SVishal Kulkarni 744956b2bdd1SGireesh Nagabhushana 745056b2bdd1SGireesh Nagabhushana struct fw_port_stats_cmd { 745156b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 745256b2bdd1SGireesh Nagabhushana __be32 retval_len16; 745356b2bdd1SGireesh Nagabhushana union fw_port_stats { 745456b2bdd1SGireesh Nagabhushana struct fw_port_stats_ctl { 745556b2bdd1SGireesh Nagabhushana __u8 nstats_bg_bm; 745656b2bdd1SGireesh Nagabhushana __u8 tx_ix; 745756b2bdd1SGireesh Nagabhushana __be16 r6; 745856b2bdd1SGireesh Nagabhushana __be32 r7; 745956b2bdd1SGireesh Nagabhushana __be64 stat0; 746056b2bdd1SGireesh Nagabhushana __be64 stat1; 746156b2bdd1SGireesh Nagabhushana __be64 stat2; 746256b2bdd1SGireesh Nagabhushana __be64 stat3; 746356b2bdd1SGireesh Nagabhushana __be64 stat4; 746456b2bdd1SGireesh Nagabhushana __be64 stat5; 746556b2bdd1SGireesh Nagabhushana } ctl; 746656b2bdd1SGireesh Nagabhushana struct fw_port_stats_all { 746756b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 746856b2bdd1SGireesh Nagabhushana __be64 tx_frames; 746956b2bdd1SGireesh Nagabhushana __be64 tx_bcast; 747056b2bdd1SGireesh Nagabhushana __be64 tx_mcast; 747156b2bdd1SGireesh Nagabhushana __be64 tx_ucast; 747256b2bdd1SGireesh Nagabhushana __be64 tx_error; 747356b2bdd1SGireesh Nagabhushana __be64 tx_64b; 747456b2bdd1SGireesh Nagabhushana __be64 tx_65b_127b; 747556b2bdd1SGireesh Nagabhushana __be64 tx_128b_255b; 747656b2bdd1SGireesh Nagabhushana __be64 tx_256b_511b; 747756b2bdd1SGireesh Nagabhushana __be64 tx_512b_1023b; 747856b2bdd1SGireesh Nagabhushana __be64 tx_1024b_1518b; 747956b2bdd1SGireesh Nagabhushana __be64 tx_1519b_max; 748056b2bdd1SGireesh Nagabhushana __be64 tx_drop; 748156b2bdd1SGireesh Nagabhushana __be64 tx_pause; 748256b2bdd1SGireesh Nagabhushana __be64 tx_ppp0; 748356b2bdd1SGireesh Nagabhushana __be64 tx_ppp1; 748456b2bdd1SGireesh Nagabhushana __be64 tx_ppp2; 748556b2bdd1SGireesh Nagabhushana __be64 tx_ppp3; 748656b2bdd1SGireesh Nagabhushana __be64 tx_ppp4; 748756b2bdd1SGireesh Nagabhushana __be64 tx_ppp5; 748856b2bdd1SGireesh Nagabhushana __be64 tx_ppp6; 748956b2bdd1SGireesh Nagabhushana __be64 tx_ppp7; 749056b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 749156b2bdd1SGireesh Nagabhushana __be64 rx_frames; 749256b2bdd1SGireesh Nagabhushana __be64 rx_bcast; 749356b2bdd1SGireesh Nagabhushana __be64 rx_mcast; 749456b2bdd1SGireesh Nagabhushana __be64 rx_ucast; 749556b2bdd1SGireesh Nagabhushana __be64 rx_mtu_error; 749656b2bdd1SGireesh Nagabhushana __be64 rx_mtu_crc_error; 749756b2bdd1SGireesh Nagabhushana __be64 rx_crc_error; 749856b2bdd1SGireesh Nagabhushana __be64 rx_len_error; 749956b2bdd1SGireesh Nagabhushana __be64 rx_sym_error; 750056b2bdd1SGireesh Nagabhushana __be64 rx_64b; 750156b2bdd1SGireesh Nagabhushana __be64 rx_65b_127b; 750256b2bdd1SGireesh Nagabhushana __be64 rx_128b_255b; 750356b2bdd1SGireesh Nagabhushana __be64 rx_256b_511b; 750456b2bdd1SGireesh Nagabhushana __be64 rx_512b_1023b; 750556b2bdd1SGireesh Nagabhushana __be64 rx_1024b_1518b; 750656b2bdd1SGireesh Nagabhushana __be64 rx_1519b_max; 750756b2bdd1SGireesh Nagabhushana __be64 rx_pause; 750856b2bdd1SGireesh Nagabhushana __be64 rx_ppp0; 750956b2bdd1SGireesh Nagabhushana __be64 rx_ppp1; 751056b2bdd1SGireesh Nagabhushana __be64 rx_ppp2; 751156b2bdd1SGireesh Nagabhushana __be64 rx_ppp3; 751256b2bdd1SGireesh Nagabhushana __be64 rx_ppp4; 751356b2bdd1SGireesh Nagabhushana __be64 rx_ppp5; 751456b2bdd1SGireesh Nagabhushana __be64 rx_ppp6; 751556b2bdd1SGireesh Nagabhushana __be64 rx_ppp7; 751656b2bdd1SGireesh Nagabhushana __be64 rx_less_64b; 751756b2bdd1SGireesh Nagabhushana __be64 rx_bg_drop; 751856b2bdd1SGireesh Nagabhushana __be64 rx_bg_trunc; 751956b2bdd1SGireesh Nagabhushana } all; 752056b2bdd1SGireesh Nagabhushana } u; 752156b2bdd1SGireesh Nagabhushana }; 752256b2bdd1SGireesh Nagabhushana 7523*3dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_NSTATS 4 7524*3dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7525*3dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7526*3dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7527*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 752856b2bdd1SGireesh Nagabhushana 7529*3dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_BG_BM 0 7530*3dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7531*3dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7532*3dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7533*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 753456b2bdd1SGireesh Nagabhushana 7535*3dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_TX 7 7536*3dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_TX 0x1 7537*3dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7538*3dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_TX(x) \ 7539*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7540*3dde7c95SVishal Kulkarni #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 754156b2bdd1SGireesh Nagabhushana 7542*3dde7c95SVishal Kulkarni #define S_FW_PORT_STATS_CMD_IX 0 7543*3dde7c95SVishal Kulkarni #define M_FW_PORT_STATS_CMD_IX 0x3f 7544*3dde7c95SVishal Kulkarni #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7545*3dde7c95SVishal Kulkarni #define G_FW_PORT_STATS_CMD_IX(x) \ 7546*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 754756b2bdd1SGireesh Nagabhushana 754856b2bdd1SGireesh Nagabhushana /* port loopback stats */ 7549*3dde7c95SVishal Kulkarni #define FW_NUM_LB_STATS 14 755056b2bdd1SGireesh Nagabhushana enum fw_port_lb_stats_index { 755156b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_BYTES_IX, 755256b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_FRAMES_IX, 755356b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_BCAST_IX, 755456b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_MCAST_IX, 755556b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_UCAST_IX, 755656b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_ERROR_IX, 755756b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_64B_IX, 755856b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_65B_127B_IX, 755956b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_128B_255B_IX, 756056b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_256B_511B_IX, 756156b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_512B_1023B_IX, 756256b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_1024B_1518B_IX, 756356b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_1519B_MAX_IX, 756456b2bdd1SGireesh Nagabhushana FW_STAT_LB_PORT_DROP_FRAMES_IX 756556b2bdd1SGireesh Nagabhushana }; 756656b2bdd1SGireesh Nagabhushana 756756b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_cmd { 756856b2bdd1SGireesh Nagabhushana __be32 op_to_lbport; 756956b2bdd1SGireesh Nagabhushana __be32 retval_len16; 757056b2bdd1SGireesh Nagabhushana union fw_port_lb_stats { 757156b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_ctl { 757256b2bdd1SGireesh Nagabhushana __u8 nstats_bg_bm; 757356b2bdd1SGireesh Nagabhushana __u8 ix_pkd; 757456b2bdd1SGireesh Nagabhushana __be16 r6; 757556b2bdd1SGireesh Nagabhushana __be32 r7; 757656b2bdd1SGireesh Nagabhushana __be64 stat0; 757756b2bdd1SGireesh Nagabhushana __be64 stat1; 757856b2bdd1SGireesh Nagabhushana __be64 stat2; 757956b2bdd1SGireesh Nagabhushana __be64 stat3; 758056b2bdd1SGireesh Nagabhushana __be64 stat4; 758156b2bdd1SGireesh Nagabhushana __be64 stat5; 758256b2bdd1SGireesh Nagabhushana } ctl; 758356b2bdd1SGireesh Nagabhushana struct fw_port_lb_stats_all { 758456b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 758556b2bdd1SGireesh Nagabhushana __be64 tx_frames; 758656b2bdd1SGireesh Nagabhushana __be64 tx_bcast; 758756b2bdd1SGireesh Nagabhushana __be64 tx_mcast; 758856b2bdd1SGireesh Nagabhushana __be64 tx_ucast; 758956b2bdd1SGireesh Nagabhushana __be64 tx_error; 759056b2bdd1SGireesh Nagabhushana __be64 tx_64b; 759156b2bdd1SGireesh Nagabhushana __be64 tx_65b_127b; 759256b2bdd1SGireesh Nagabhushana __be64 tx_128b_255b; 759356b2bdd1SGireesh Nagabhushana __be64 tx_256b_511b; 759456b2bdd1SGireesh Nagabhushana __be64 tx_512b_1023b; 759556b2bdd1SGireesh Nagabhushana __be64 tx_1024b_1518b; 759656b2bdd1SGireesh Nagabhushana __be64 tx_1519b_max; 759756b2bdd1SGireesh Nagabhushana __be64 rx_lb_drop; 759856b2bdd1SGireesh Nagabhushana __be64 rx_lb_trunc; 759956b2bdd1SGireesh Nagabhushana } all; 760056b2bdd1SGireesh Nagabhushana } u; 760156b2bdd1SGireesh Nagabhushana }; 760256b2bdd1SGireesh Nagabhushana 7603*3dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7604*3dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7605*3dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7606*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7607*3dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7608*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7609*3dde7c95SVishal Kulkarni 7610*3dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7611*3dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7612*3dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7613*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7614*3dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7615*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7616*3dde7c95SVishal Kulkarni 7617*3dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7618*3dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7619*3dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7620*3dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7621*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7622*3dde7c95SVishal Kulkarni 7623*3dde7c95SVishal Kulkarni #define S_FW_PORT_LB_STATS_CMD_IX 0 7624*3dde7c95SVishal Kulkarni #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7625*3dde7c95SVishal Kulkarni #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7626*3dde7c95SVishal Kulkarni #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7627*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 762856b2bdd1SGireesh Nagabhushana 762956b2bdd1SGireesh Nagabhushana /* Trace related defines */ 7630*3dde7c95SVishal Kulkarni #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7631*3dde7c95SVishal Kulkarni #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 763256b2bdd1SGireesh Nagabhushana 763356b2bdd1SGireesh Nagabhushana struct fw_port_trace_cmd { 763456b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 763556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 763656b2bdd1SGireesh Nagabhushana __be16 traceen_to_pciech; 763756b2bdd1SGireesh Nagabhushana __be16 qnum; 763856b2bdd1SGireesh Nagabhushana __be32 r5; 763956b2bdd1SGireesh Nagabhushana }; 764056b2bdd1SGireesh Nagabhushana 7641*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_PORTID 0 7642*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_PORTID 0xf 7643*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7644*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7645*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7646*3dde7c95SVishal Kulkarni 7647*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_TRACEEN 15 7648*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7649*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7650*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7651*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7652*3dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7653*3dde7c95SVishal Kulkarni 7654*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_FLTMODE 14 7655*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7656*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7657*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7658*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7659*3dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7660*3dde7c95SVishal Kulkarni 7661*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_DUPLEN 13 7662*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7663*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7664*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7665*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7666*3dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7667*3dde7c95SVishal Kulkarni 7668*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7669*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7670*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7671*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7672*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7673*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7674*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7675*3dde7c95SVishal Kulkarni 7676*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_CMD_PCIECH 6 7677*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7678*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7679*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7680*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 768156b2bdd1SGireesh Nagabhushana 768256b2bdd1SGireesh Nagabhushana struct fw_port_trace_mmap_cmd { 768356b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 768456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 768556b2bdd1SGireesh Nagabhushana __be32 fid_to_skipoffset; 768656b2bdd1SGireesh Nagabhushana __be32 minpktsize_capturemax; 768756b2bdd1SGireesh Nagabhushana __u8 map[224]; 768856b2bdd1SGireesh Nagabhushana }; 768956b2bdd1SGireesh Nagabhushana 7690*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7691*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7692*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7693*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7694*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7695*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7696*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7697*3dde7c95SVishal Kulkarni 7698*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7699*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7700*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7701*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7702*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7703*3dde7c95SVishal Kulkarni 7704*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7705*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7706*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7707*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7708*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7709*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7710*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7711*3dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7712*3dde7c95SVishal Kulkarni 7713*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7714*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7715*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7716*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7717*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7718*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7719*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7720*3dde7c95SVishal Kulkarni #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7721*3dde7c95SVishal Kulkarni 7722*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7723*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7724*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7725*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7726*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7727*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 7728*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7729*3dde7c95SVishal Kulkarni 7730*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 7731*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 7732*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7733*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7734*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7735*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 7736*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7737*3dde7c95SVishal Kulkarni 7738*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 7739*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 7740*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7741*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7742*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7743*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 7744*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7745*3dde7c95SVishal Kulkarni 7746*3dde7c95SVishal Kulkarni #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 7747*3dde7c95SVishal Kulkarni #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 7748*3dde7c95SVishal Kulkarni #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7749*3dde7c95SVishal Kulkarni ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7750*3dde7c95SVishal Kulkarni #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7751*3dde7c95SVishal Kulkarni (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 7752*3dde7c95SVishal Kulkarni M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7753*3dde7c95SVishal Kulkarni 7754*3dde7c95SVishal Kulkarni enum fw_ptp_subop { 7755*3dde7c95SVishal Kulkarni 7756*3dde7c95SVishal Kulkarni /* none */ 7757*3dde7c95SVishal Kulkarni FW_PTP_SC_INIT_TIMER = 0x00, 7758*3dde7c95SVishal Kulkarni FW_PTP_SC_TX_TYPE = 0x01, 7759*3dde7c95SVishal Kulkarni 7760*3dde7c95SVishal Kulkarni /* init */ 7761*3dde7c95SVishal Kulkarni FW_PTP_SC_RXTIME_STAMP = 0x08, 7762*3dde7c95SVishal Kulkarni FW_PTP_SC_RDRX_TYPE = 0x09, 7763*3dde7c95SVishal Kulkarni 7764*3dde7c95SVishal Kulkarni /* ts */ 7765*3dde7c95SVishal Kulkarni FW_PTP_SC_ADJ_FREQ = 0x10, 7766*3dde7c95SVishal Kulkarni FW_PTP_SC_ADJ_TIME = 0x11, 7767*3dde7c95SVishal Kulkarni FW_PTP_SC_ADJ_FTIME = 0x12, 7768*3dde7c95SVishal Kulkarni FW_PTP_SC_WALL_CLOCK = 0x13, 7769*3dde7c95SVishal Kulkarni FW_PTP_SC_GET_TIME = 0x14, 7770*3dde7c95SVishal Kulkarni FW_PTP_SC_SET_TIME = 0x15, 7771*3dde7c95SVishal Kulkarni }; 7772*3dde7c95SVishal Kulkarni 7773*3dde7c95SVishal Kulkarni struct fw_ptp_cmd { 7774*3dde7c95SVishal Kulkarni __be32 op_to_portid; 7775*3dde7c95SVishal Kulkarni __be32 retval_len16; 7776*3dde7c95SVishal Kulkarni union fw_ptp { 7777*3dde7c95SVishal Kulkarni struct fw_ptp_sc { 7778*3dde7c95SVishal Kulkarni __u8 sc; 7779*3dde7c95SVishal Kulkarni __u8 r3[7]; 7780*3dde7c95SVishal Kulkarni } scmd; 7781*3dde7c95SVishal Kulkarni struct fw_ptp_init { 7782*3dde7c95SVishal Kulkarni __u8 sc; 7783*3dde7c95SVishal Kulkarni __u8 txchan; 7784*3dde7c95SVishal Kulkarni __be16 absid; 7785*3dde7c95SVishal Kulkarni __be16 mode; 7786*3dde7c95SVishal Kulkarni __be16 r3; 7787*3dde7c95SVishal Kulkarni } init; 7788*3dde7c95SVishal Kulkarni struct fw_ptp_ts { 7789*3dde7c95SVishal Kulkarni __u8 sc; 7790*3dde7c95SVishal Kulkarni __u8 sign; 7791*3dde7c95SVishal Kulkarni __be16 r3; 7792*3dde7c95SVishal Kulkarni __be32 ppb; 7793*3dde7c95SVishal Kulkarni __be64 tm; 7794*3dde7c95SVishal Kulkarni } ts; 7795*3dde7c95SVishal Kulkarni } u; 7796*3dde7c95SVishal Kulkarni __be64 r3; 7797*3dde7c95SVishal Kulkarni }; 7798*3dde7c95SVishal Kulkarni 7799*3dde7c95SVishal Kulkarni #define S_FW_PTP_CMD_PORTID 0 7800*3dde7c95SVishal Kulkarni #define M_FW_PTP_CMD_PORTID 0xf 7801*3dde7c95SVishal Kulkarni #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 7802*3dde7c95SVishal Kulkarni #define G_FW_PTP_CMD_PORTID(x) \ 7803*3dde7c95SVishal Kulkarni (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 780456b2bdd1SGireesh Nagabhushana 780556b2bdd1SGireesh Nagabhushana struct fw_rss_ind_tbl_cmd { 780656b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 780756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 780856b2bdd1SGireesh Nagabhushana __be16 niqid; 780956b2bdd1SGireesh Nagabhushana __be16 startidx; 781056b2bdd1SGireesh Nagabhushana __be32 r3; 781156b2bdd1SGireesh Nagabhushana __be32 iq0_to_iq2; 781256b2bdd1SGireesh Nagabhushana __be32 iq3_to_iq5; 781356b2bdd1SGireesh Nagabhushana __be32 iq6_to_iq8; 781456b2bdd1SGireesh Nagabhushana __be32 iq9_to_iq11; 781556b2bdd1SGireesh Nagabhushana __be32 iq12_to_iq14; 781656b2bdd1SGireesh Nagabhushana __be32 iq15_to_iq17; 781756b2bdd1SGireesh Nagabhushana __be32 iq18_to_iq20; 781856b2bdd1SGireesh Nagabhushana __be32 iq21_to_iq23; 781956b2bdd1SGireesh Nagabhushana __be32 iq24_to_iq26; 782056b2bdd1SGireesh Nagabhushana __be32 iq27_to_iq29; 782156b2bdd1SGireesh Nagabhushana __be32 iq30_iq31; 782256b2bdd1SGireesh Nagabhushana __be32 r15_lo; 782356b2bdd1SGireesh Nagabhushana }; 782456b2bdd1SGireesh Nagabhushana 7825*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_VIID 0 7826*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 7827*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 7828*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 7829*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 7830*3dde7c95SVishal Kulkarni 7831*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ0 20 7832*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 7833*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 7834*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 7835*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 7836*3dde7c95SVishal Kulkarni 7837*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ1 10 7838*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 7839*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 7840*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 7841*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 7842*3dde7c95SVishal Kulkarni 7843*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ2 0 7844*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 7845*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 7846*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 7847*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 7848*3dde7c95SVishal Kulkarni 7849*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ3 20 7850*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 7851*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 7852*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 7853*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 7854*3dde7c95SVishal Kulkarni 7855*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ4 10 7856*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 7857*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 7858*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 7859*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 7860*3dde7c95SVishal Kulkarni 7861*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ5 0 7862*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 7863*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 7864*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 7865*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 7866*3dde7c95SVishal Kulkarni 7867*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ6 20 7868*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 7869*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 7870*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 7871*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 7872*3dde7c95SVishal Kulkarni 7873*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ7 10 7874*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 7875*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 7876*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 7877*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 7878*3dde7c95SVishal Kulkarni 7879*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ8 0 7880*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 7881*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 7882*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 7883*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 7884*3dde7c95SVishal Kulkarni 7885*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ9 20 7886*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 7887*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 7888*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 7889*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 7890*3dde7c95SVishal Kulkarni 7891*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ10 10 7892*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 7893*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 7894*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 7895*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 7896*3dde7c95SVishal Kulkarni 7897*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ11 0 7898*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 7899*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 7900*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 7901*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 7902*3dde7c95SVishal Kulkarni 7903*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ12 20 7904*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 7905*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 7906*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 7907*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 7908*3dde7c95SVishal Kulkarni 7909*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ13 10 7910*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 7911*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 7912*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 7913*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 7914*3dde7c95SVishal Kulkarni 7915*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ14 0 7916*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 7917*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 7918*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 7919*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 7920*3dde7c95SVishal Kulkarni 7921*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ15 20 7922*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 7923*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 7924*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 7925*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 7926*3dde7c95SVishal Kulkarni 7927*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ16 10 7928*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 7929*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 7930*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 7931*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 7932*3dde7c95SVishal Kulkarni 7933*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ17 0 7934*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 7935*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 7936*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 7937*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 7938*3dde7c95SVishal Kulkarni 7939*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ18 20 7940*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 7941*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 7942*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 7943*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 7944*3dde7c95SVishal Kulkarni 7945*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ19 10 7946*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 7947*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 7948*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 7949*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 7950*3dde7c95SVishal Kulkarni 7951*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ20 0 7952*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 7953*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 7954*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 7955*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 7956*3dde7c95SVishal Kulkarni 7957*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ21 20 7958*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 7959*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 7960*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 7961*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 7962*3dde7c95SVishal Kulkarni 7963*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ22 10 7964*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 7965*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 7966*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 7967*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 7968*3dde7c95SVishal Kulkarni 7969*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ23 0 7970*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 7971*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 7972*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 7973*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 7974*3dde7c95SVishal Kulkarni 7975*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ24 20 7976*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 7977*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 7978*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 7979*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 7980*3dde7c95SVishal Kulkarni 7981*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ25 10 7982*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 7983*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 7984*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 7985*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 7986*3dde7c95SVishal Kulkarni 7987*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ26 0 7988*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 7989*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 7990*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 7991*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 7992*3dde7c95SVishal Kulkarni 7993*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ27 20 7994*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 7995*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 7996*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 7997*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 7998*3dde7c95SVishal Kulkarni 7999*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ28 10 8000*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8001*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8002*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8003*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8004*3dde7c95SVishal Kulkarni 8005*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ29 0 8006*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8007*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8008*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8009*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8010*3dde7c95SVishal Kulkarni 8011*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ30 20 8012*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8013*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8014*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8015*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8016*3dde7c95SVishal Kulkarni 8017*3dde7c95SVishal Kulkarni #define S_FW_RSS_IND_TBL_CMD_IQ31 10 8018*3dde7c95SVishal Kulkarni #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8019*3dde7c95SVishal Kulkarni #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8020*3dde7c95SVishal Kulkarni #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8021*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 802256b2bdd1SGireesh Nagabhushana 802356b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_cmd { 802456b2bdd1SGireesh Nagabhushana __be32 op_to_write; 802556b2bdd1SGireesh Nagabhushana __be32 retval_len16; 802656b2bdd1SGireesh Nagabhushana union fw_rss_glb_config { 802756b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_manual { 802856b2bdd1SGireesh Nagabhushana __be32 mode_pkd; 802956b2bdd1SGireesh Nagabhushana __be32 r3; 803056b2bdd1SGireesh Nagabhushana __be64 r4; 803156b2bdd1SGireesh Nagabhushana __be64 r5; 803256b2bdd1SGireesh Nagabhushana } manual; 803356b2bdd1SGireesh Nagabhushana struct fw_rss_glb_config_basicvirtual { 8034*3dde7c95SVishal Kulkarni __be32 mode_keymode; 803556b2bdd1SGireesh Nagabhushana __be32 synmapen_to_hashtoeplitz; 803656b2bdd1SGireesh Nagabhushana __be64 r8; 803756b2bdd1SGireesh Nagabhushana __be64 r9; 803856b2bdd1SGireesh Nagabhushana } basicvirtual; 803956b2bdd1SGireesh Nagabhushana } u; 804056b2bdd1SGireesh Nagabhushana }; 804156b2bdd1SGireesh Nagabhushana 8042*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8043*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8044*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8045*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8046*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8047*3dde7c95SVishal Kulkarni 8048*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8049*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8050*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8051*3dde7c95SVishal Kulkarni 8052*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8053*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8054*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8055*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8056*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8057*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8058*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8059*3dde7c95SVishal Kulkarni 8060*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8061*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8062*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8063*3dde7c95SVishal Kulkarni #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8064*3dde7c95SVishal Kulkarni 8065*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8066*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8067*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8068*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8069*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8070*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8071*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8072*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8073*3dde7c95SVishal Kulkarni 8074*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8075*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8076*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8077*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8078*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8079*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8080*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8081*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 808256b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 808356b2bdd1SGireesh Nagabhushana 8084*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8085*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8086*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8087*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8088*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8089*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8090*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8091*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 809256b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 809356b2bdd1SGireesh Nagabhushana 8094*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8095*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8096*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8097*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8098*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8099*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8100*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8101*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 810256b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 810356b2bdd1SGireesh Nagabhushana 8104*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8105*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8106*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8107*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8108*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8109*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8110*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8111*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 811256b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 811356b2bdd1SGireesh Nagabhushana 8114*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8115*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8116*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8117*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8118*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8119*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8120*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8121*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8122*3dde7c95SVishal Kulkarni 8123*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8124*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8125*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8126*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8127*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8128*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8129*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8130*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8131*3dde7c95SVishal Kulkarni 8132*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8133*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8134*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8135*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8136*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8137*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8138*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8139*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 814056b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 814156b2bdd1SGireesh Nagabhushana 8142*3dde7c95SVishal Kulkarni #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8143*3dde7c95SVishal Kulkarni #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8144*3dde7c95SVishal Kulkarni #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8145*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8146*3dde7c95SVishal Kulkarni #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8147*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8148*3dde7c95SVishal Kulkarni M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8149*3dde7c95SVishal Kulkarni #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 815056b2bdd1SGireesh Nagabhushana V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 815156b2bdd1SGireesh Nagabhushana 815256b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_cmd { 815356b2bdd1SGireesh Nagabhushana __be32 op_to_viid; 815456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 815556b2bdd1SGireesh Nagabhushana union fw_rss_vi_config { 815656b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_manual { 815756b2bdd1SGireesh Nagabhushana __be64 r3; 815856b2bdd1SGireesh Nagabhushana __be64 r4; 815956b2bdd1SGireesh Nagabhushana __be64 r5; 816056b2bdd1SGireesh Nagabhushana } manual; 816156b2bdd1SGireesh Nagabhushana struct fw_rss_vi_config_basicvirtual { 816256b2bdd1SGireesh Nagabhushana __be32 r6; 816356b2bdd1SGireesh Nagabhushana __be32 defaultq_to_udpen; 8164*3dde7c95SVishal Kulkarni __be32 secretkeyidx_pkd; 8165*3dde7c95SVishal Kulkarni __be32 secretkeyxor; 816656b2bdd1SGireesh Nagabhushana __be64 r10; 816756b2bdd1SGireesh Nagabhushana } basicvirtual; 816856b2bdd1SGireesh Nagabhushana } u; 816956b2bdd1SGireesh Nagabhushana }; 817056b2bdd1SGireesh Nagabhushana 8171*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8172*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8173*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8174*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8175*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8176*3dde7c95SVishal Kulkarni 8177*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8178*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8179*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8180*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8181*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8182*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8183*3dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8184*3dde7c95SVishal Kulkarni 8185*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8186*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8187*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8188*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8189*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8190*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8191*3dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8192*3dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 819356b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 819456b2bdd1SGireesh Nagabhushana 8195*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8196*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8197*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8198*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8199*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8200*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8201*3dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8202*3dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 820356b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 820456b2bdd1SGireesh Nagabhushana 8205*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8206*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8207*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8208*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8209*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8210*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8211*3dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8212*3dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 821356b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 821456b2bdd1SGireesh Nagabhushana 8215*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8216*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8217*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8218*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8219*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8220*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8221*3dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8222*3dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 822356b2bdd1SGireesh Nagabhushana V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 822456b2bdd1SGireesh Nagabhushana 8225*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8226*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8227*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8228*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8229*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8230*3dde7c95SVishal Kulkarni #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8231*3dde7c95SVishal Kulkarni 8232*3dde7c95SVishal Kulkarni #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8233*3dde7c95SVishal Kulkarni #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8234*3dde7c95SVishal Kulkarni #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8235*3dde7c95SVishal Kulkarni ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8236*3dde7c95SVishal Kulkarni #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8237*3dde7c95SVishal Kulkarni (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8238*3dde7c95SVishal Kulkarni M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 823956b2bdd1SGireesh Nagabhushana 824056b2bdd1SGireesh Nagabhushana enum fw_sched_sc { 824156b2bdd1SGireesh Nagabhushana FW_SCHED_SC_CONFIG = 0, 824256b2bdd1SGireesh Nagabhushana FW_SCHED_SC_PARAMS = 1, 824356b2bdd1SGireesh Nagabhushana }; 824456b2bdd1SGireesh Nagabhushana 824556b2bdd1SGireesh Nagabhushana enum fw_sched_type { 8246*3dde7c95SVishal Kulkarni FW_SCHED_TYPE_PKTSCHED = 0, 8247*3dde7c95SVishal Kulkarni FW_SCHED_TYPE_STREAMSCHED = 1, 824856b2bdd1SGireesh Nagabhushana }; 824956b2bdd1SGireesh Nagabhushana 825056b2bdd1SGireesh Nagabhushana enum fw_sched_params_level { 825156b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 825256b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 825356b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 825456b2bdd1SGireesh Nagabhushana }; 825556b2bdd1SGireesh Nagabhushana 825656b2bdd1SGireesh Nagabhushana enum fw_sched_params_mode { 825756b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_MODE_CLASS = 0, 825856b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_MODE_FLOW = 1, 825956b2bdd1SGireesh Nagabhushana }; 826056b2bdd1SGireesh Nagabhushana 826156b2bdd1SGireesh Nagabhushana enum fw_sched_params_unit { 826256b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_UNIT_BITRATE = 0, 826356b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 826456b2bdd1SGireesh Nagabhushana }; 826556b2bdd1SGireesh Nagabhushana 826656b2bdd1SGireesh Nagabhushana enum fw_sched_params_rate { 826756b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_RATE_REL = 0, 826856b2bdd1SGireesh Nagabhushana FW_SCHED_PARAMS_RATE_ABS = 1, 826956b2bdd1SGireesh Nagabhushana }; 827056b2bdd1SGireesh Nagabhushana 827156b2bdd1SGireesh Nagabhushana struct fw_sched_cmd { 827256b2bdd1SGireesh Nagabhushana __be32 op_to_write; 827356b2bdd1SGireesh Nagabhushana __be32 retval_len16; 827456b2bdd1SGireesh Nagabhushana union fw_sched { 827556b2bdd1SGireesh Nagabhushana struct fw_sched_config { 827656b2bdd1SGireesh Nagabhushana __u8 sc; 827756b2bdd1SGireesh Nagabhushana __u8 type; 827856b2bdd1SGireesh Nagabhushana __u8 minmaxen; 827956b2bdd1SGireesh Nagabhushana __u8 r3[5]; 8280de483253SVishal Kulkarni __u8 nclasses[4]; 8281de483253SVishal Kulkarni __be32 r4; 828256b2bdd1SGireesh Nagabhushana } config; 828356b2bdd1SGireesh Nagabhushana struct fw_sched_params { 828456b2bdd1SGireesh Nagabhushana __u8 sc; 828556b2bdd1SGireesh Nagabhushana __u8 type; 828656b2bdd1SGireesh Nagabhushana __u8 level; 828756b2bdd1SGireesh Nagabhushana __u8 mode; 828856b2bdd1SGireesh Nagabhushana __u8 unit; 828956b2bdd1SGireesh Nagabhushana __u8 rate; 829056b2bdd1SGireesh Nagabhushana __u8 ch; 829156b2bdd1SGireesh Nagabhushana __u8 cl; 829256b2bdd1SGireesh Nagabhushana __be32 min; 829356b2bdd1SGireesh Nagabhushana __be32 max; 829456b2bdd1SGireesh Nagabhushana __be16 weight; 829556b2bdd1SGireesh Nagabhushana __be16 pktsize; 8296de483253SVishal Kulkarni __be16 burstsize; 8297de483253SVishal Kulkarni __be16 r4; 829856b2bdd1SGireesh Nagabhushana } params; 829956b2bdd1SGireesh Nagabhushana } u; 830056b2bdd1SGireesh Nagabhushana }; 830156b2bdd1SGireesh Nagabhushana 830256b2bdd1SGireesh Nagabhushana /* 830356b2bdd1SGireesh Nagabhushana * length of the formatting string 830456b2bdd1SGireesh Nagabhushana */ 8305*3dde7c95SVishal Kulkarni #define FW_DEVLOG_FMT_LEN 192 830656b2bdd1SGireesh Nagabhushana 830756b2bdd1SGireesh Nagabhushana /* 830856b2bdd1SGireesh Nagabhushana * maximum number of the formatting string parameters 830956b2bdd1SGireesh Nagabhushana */ 8310*3dde7c95SVishal Kulkarni #define FW_DEVLOG_FMT_PARAMS_NUM 8 831156b2bdd1SGireesh Nagabhushana 831256b2bdd1SGireesh Nagabhushana /* 831356b2bdd1SGireesh Nagabhushana * priority levels 831456b2bdd1SGireesh Nagabhushana */ 831556b2bdd1SGireesh Nagabhushana enum fw_devlog_level { 831656b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_EMERG = 0x0, 831756b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_CRIT = 0x1, 831856b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_ERR = 0x2, 831956b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_NOTICE = 0x3, 832056b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_INFO = 0x4, 832156b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_DEBUG = 0x5, 832256b2bdd1SGireesh Nagabhushana FW_DEVLOG_LEVEL_MAX = 0x5, 832356b2bdd1SGireesh Nagabhushana }; 832456b2bdd1SGireesh Nagabhushana 832556b2bdd1SGireesh Nagabhushana /* 832656b2bdd1SGireesh Nagabhushana * facilities that may send a log message 832756b2bdd1SGireesh Nagabhushana */ 832856b2bdd1SGireesh Nagabhushana enum fw_devlog_facility { 832956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_CORE = 0x00, 8330de483253SVishal Kulkarni FW_DEVLOG_FACILITY_CF = 0x01, 833156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_SCHED = 0x02, 833256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_TIMER = 0x04, 833356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_RES = 0x06, 833456b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_HW = 0x08, 833556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FLR = 0x10, 833656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_DMAQ = 0x12, 833756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_PHY = 0x14, 833856b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_MAC = 0x16, 833956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_PORT = 0x18, 834056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_VI = 0x1A, 834156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FILTER = 0x1C, 834256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ACL = 0x1E, 834356b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_TM = 0x20, 834456b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_QFC = 0x22, 834556b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_DCB = 0x24, 834656b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ETH = 0x26, 834756b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_OFLD = 0x28, 834856b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_RI = 0x2A, 834956b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_ISCSI = 0x2C, 835056b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FCOE = 0x2E, 835156b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FOISCSI = 0x30, 835256b2bdd1SGireesh Nagabhushana FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8353*3dde7c95SVishal Kulkarni FW_DEVLOG_FACILITY_CHNET = 0x34, 8354*3dde7c95SVishal Kulkarni FW_DEVLOG_FACILITY_COiSCSI = 0x36, 8355*3dde7c95SVishal Kulkarni FW_DEVLOG_FACILITY_MAX = 0x38, 835656b2bdd1SGireesh Nagabhushana }; 835756b2bdd1SGireesh Nagabhushana 835856b2bdd1SGireesh Nagabhushana /* 835956b2bdd1SGireesh Nagabhushana * log message format 836056b2bdd1SGireesh Nagabhushana */ 836156b2bdd1SGireesh Nagabhushana struct fw_devlog_e { 836256b2bdd1SGireesh Nagabhushana __be64 timestamp; 836356b2bdd1SGireesh Nagabhushana __be32 seqno; 836456b2bdd1SGireesh Nagabhushana __be16 reserved1; 836556b2bdd1SGireesh Nagabhushana __u8 level; 836656b2bdd1SGireesh Nagabhushana __u8 facility; 836756b2bdd1SGireesh Nagabhushana __u8 fmt[FW_DEVLOG_FMT_LEN]; 836856b2bdd1SGireesh Nagabhushana __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 836956b2bdd1SGireesh Nagabhushana __be32 reserved3[4]; 837056b2bdd1SGireesh Nagabhushana }; 837156b2bdd1SGireesh Nagabhushana 837256b2bdd1SGireesh Nagabhushana struct fw_devlog_cmd { 837356b2bdd1SGireesh Nagabhushana __be32 op_to_write; 837456b2bdd1SGireesh Nagabhushana __be32 retval_len16; 837556b2bdd1SGireesh Nagabhushana __u8 level; 837656b2bdd1SGireesh Nagabhushana __u8 r2[7]; 837756b2bdd1SGireesh Nagabhushana __be32 memtype_devlog_memaddr16_devlog; 837856b2bdd1SGireesh Nagabhushana __be32 memsize_devlog; 837956b2bdd1SGireesh Nagabhushana __be32 r3[2]; 838056b2bdd1SGireesh Nagabhushana }; 838156b2bdd1SGireesh Nagabhushana 8382*3dde7c95SVishal Kulkarni #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8383*3dde7c95SVishal Kulkarni #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8384*3dde7c95SVishal Kulkarni #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8385*3dde7c95SVishal Kulkarni ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8386*3dde7c95SVishal Kulkarni #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8387*3dde7c95SVishal Kulkarni (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 838856b2bdd1SGireesh Nagabhushana 8389*3dde7c95SVishal Kulkarni #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8390*3dde7c95SVishal Kulkarni #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8391*3dde7c95SVishal Kulkarni #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8392*3dde7c95SVishal Kulkarni ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8393*3dde7c95SVishal Kulkarni #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8394*3dde7c95SVishal Kulkarni (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8395*3dde7c95SVishal Kulkarni M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 839656b2bdd1SGireesh Nagabhushana 839756b2bdd1SGireesh Nagabhushana enum fw_watchdog_actions { 8398de483253SVishal Kulkarni FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8399de483253SVishal Kulkarni FW_WATCHDOG_ACTION_FLR = 1, 8400de483253SVishal Kulkarni FW_WATCHDOG_ACTION_BYPASS = 2, 8401de483253SVishal Kulkarni FW_WATCHDOG_ACTION_TMPCHK = 3, 8402*3dde7c95SVishal Kulkarni FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8403de483253SVishal Kulkarni 8404*3dde7c95SVishal Kulkarni FW_WATCHDOG_ACTION_MAX = 5, 840556b2bdd1SGireesh Nagabhushana }; 840656b2bdd1SGireesh Nagabhushana 8407*3dde7c95SVishal Kulkarni #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 840856b2bdd1SGireesh Nagabhushana 840956b2bdd1SGireesh Nagabhushana struct fw_watchdog_cmd { 8410de483253SVishal Kulkarni __be32 op_to_vfn; 841156b2bdd1SGireesh Nagabhushana __be32 retval_len16; 841256b2bdd1SGireesh Nagabhushana __be32 timeout; 8413de483253SVishal Kulkarni __be32 action; 841456b2bdd1SGireesh Nagabhushana }; 841556b2bdd1SGireesh Nagabhushana 8416de483253SVishal Kulkarni #define S_FW_WATCHDOG_CMD_PFN 8 8417de483253SVishal Kulkarni #define M_FW_WATCHDOG_CMD_PFN 0x7 8418de483253SVishal Kulkarni #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8419de483253SVishal Kulkarni #define G_FW_WATCHDOG_CMD_PFN(x) \ 8420de483253SVishal Kulkarni (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8421de483253SVishal Kulkarni 8422de483253SVishal Kulkarni #define S_FW_WATCHDOG_CMD_VFN 0 8423de483253SVishal Kulkarni #define M_FW_WATCHDOG_CMD_VFN 0xff 8424de483253SVishal Kulkarni #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8425de483253SVishal Kulkarni #define G_FW_WATCHDOG_CMD_VFN(x) \ 8426de483253SVishal Kulkarni (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8427*3dde7c95SVishal Kulkarni 842856b2bdd1SGireesh Nagabhushana struct fw_clip_cmd { 842956b2bdd1SGireesh Nagabhushana __be32 op_to_write; 843056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 843156b2bdd1SGireesh Nagabhushana __be64 ip_hi; 843256b2bdd1SGireesh Nagabhushana __be64 ip_lo; 843356b2bdd1SGireesh Nagabhushana __be32 r4[2]; 843456b2bdd1SGireesh Nagabhushana }; 843556b2bdd1SGireesh Nagabhushana 8436*3dde7c95SVishal Kulkarni #define S_FW_CLIP_CMD_ALLOC 31 8437*3dde7c95SVishal Kulkarni #define M_FW_CLIP_CMD_ALLOC 0x1 8438*3dde7c95SVishal Kulkarni #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8439*3dde7c95SVishal Kulkarni #define G_FW_CLIP_CMD_ALLOC(x) \ 8440*3dde7c95SVishal Kulkarni (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8441*3dde7c95SVishal Kulkarni #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 844256b2bdd1SGireesh Nagabhushana 8443*3dde7c95SVishal Kulkarni #define S_FW_CLIP_CMD_FREE 30 8444*3dde7c95SVishal Kulkarni #define M_FW_CLIP_CMD_FREE 0x1 8445*3dde7c95SVishal Kulkarni #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8446*3dde7c95SVishal Kulkarni #define G_FW_CLIP_CMD_FREE(x) \ 8447*3dde7c95SVishal Kulkarni (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8448*3dde7c95SVishal Kulkarni #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 844956b2bdd1SGireesh Nagabhushana 8450*3dde7c95SVishal Kulkarni /****************************************************************************** 8451*3dde7c95SVishal Kulkarni * F O i S C S I C O M M A N D s 8452*3dde7c95SVishal Kulkarni **************************************/ 845356b2bdd1SGireesh Nagabhushana 845456b2bdd1SGireesh Nagabhushana #define FW_CHNET_IFACE_ADDR_MAX 3 845556b2bdd1SGireesh Nagabhushana 845656b2bdd1SGireesh Nagabhushana enum fw_chnet_iface_cmd_subop { 845756b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 845856b2bdd1SGireesh Nagabhushana 845956b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 846056b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 846156b2bdd1SGireesh Nagabhushana 846256b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 846356b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 846456b2bdd1SGireesh Nagabhushana 846556b2bdd1SGireesh Nagabhushana FW_CHNET_IFACE_CMD_SUBOP_MAX, 846656b2bdd1SGireesh Nagabhushana }; 846756b2bdd1SGireesh Nagabhushana 846856b2bdd1SGireesh Nagabhushana struct fw_chnet_iface_cmd { 846956b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 847056b2bdd1SGireesh Nagabhushana __be32 retval_len16; 847156b2bdd1SGireesh Nagabhushana __u8 subop; 847256b2bdd1SGireesh Nagabhushana __u8 r2[3]; 847356b2bdd1SGireesh Nagabhushana __be32 ifid_ifstate; 847456b2bdd1SGireesh Nagabhushana __be16 mtu; 847556b2bdd1SGireesh Nagabhushana __be16 vlanid; 847656b2bdd1SGireesh Nagabhushana __be32 r3; 847756b2bdd1SGireesh Nagabhushana __be16 r4; 847856b2bdd1SGireesh Nagabhushana __u8 mac[6]; 847956b2bdd1SGireesh Nagabhushana }; 848056b2bdd1SGireesh Nagabhushana 8481*3dde7c95SVishal Kulkarni #define S_FW_CHNET_IFACE_CMD_PORTID 0 8482*3dde7c95SVishal Kulkarni #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8483*3dde7c95SVishal Kulkarni #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8484*3dde7c95SVishal Kulkarni #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8485*3dde7c95SVishal Kulkarni (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 848656b2bdd1SGireesh Nagabhushana 8487*3dde7c95SVishal Kulkarni #define S_FW_CHNET_IFACE_CMD_IFID 8 8488*3dde7c95SVishal Kulkarni #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8489*3dde7c95SVishal Kulkarni #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8490*3dde7c95SVishal Kulkarni #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8491*3dde7c95SVishal Kulkarni (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 849256b2bdd1SGireesh Nagabhushana 8493*3dde7c95SVishal Kulkarni #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8494*3dde7c95SVishal Kulkarni #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8495*3dde7c95SVishal Kulkarni #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8496*3dde7c95SVishal Kulkarni #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8497*3dde7c95SVishal Kulkarni (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 849856b2bdd1SGireesh Nagabhushana 849956b2bdd1SGireesh Nagabhushana struct fw_fcoe_res_info_cmd { 850056b2bdd1SGireesh Nagabhushana __be32 op_to_read; 850156b2bdd1SGireesh Nagabhushana __be32 retval_len16; 850256b2bdd1SGireesh Nagabhushana __be16 e_d_tov; 850356b2bdd1SGireesh Nagabhushana __be16 r_a_tov_seq; 850456b2bdd1SGireesh Nagabhushana __be16 r_a_tov_els; 850556b2bdd1SGireesh Nagabhushana __be16 r_r_tov; 850656b2bdd1SGireesh Nagabhushana __be32 max_xchgs; 850756b2bdd1SGireesh Nagabhushana __be32 max_ssns; 850856b2bdd1SGireesh Nagabhushana __be32 used_xchgs; 850956b2bdd1SGireesh Nagabhushana __be32 used_ssns; 851056b2bdd1SGireesh Nagabhushana __be32 max_fcfs; 851156b2bdd1SGireesh Nagabhushana __be32 max_vnps; 851256b2bdd1SGireesh Nagabhushana __be32 used_fcfs; 851356b2bdd1SGireesh Nagabhushana __be32 used_vnps; 851456b2bdd1SGireesh Nagabhushana }; 851556b2bdd1SGireesh Nagabhushana 851656b2bdd1SGireesh Nagabhushana struct fw_fcoe_link_cmd { 851756b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 851856b2bdd1SGireesh Nagabhushana __be32 retval_len16; 851956b2bdd1SGireesh Nagabhushana __be32 sub_opcode_fcfi; 852056b2bdd1SGireesh Nagabhushana __u8 r3; 852156b2bdd1SGireesh Nagabhushana __u8 lstatus; 852256b2bdd1SGireesh Nagabhushana __be16 flags; 852356b2bdd1SGireesh Nagabhushana __u8 r4; 852456b2bdd1SGireesh Nagabhushana __u8 set_vlan; 852556b2bdd1SGireesh Nagabhushana __be16 vlan_id; 852656b2bdd1SGireesh Nagabhushana __be32 vnpi_pkd; 852756b2bdd1SGireesh Nagabhushana __be16 r6; 852856b2bdd1SGireesh Nagabhushana __u8 phy_mac[6]; 852956b2bdd1SGireesh Nagabhushana __u8 vnport_wwnn[8]; 853056b2bdd1SGireesh Nagabhushana __u8 vnport_wwpn[8]; 853156b2bdd1SGireesh Nagabhushana }; 853256b2bdd1SGireesh Nagabhushana 8533*3dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_PORTID 0 8534*3dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_PORTID 0xf 8535*3dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8536*3dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8537*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 853856b2bdd1SGireesh Nagabhushana 8539*3dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8540*3dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8541*3dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8542*3dde7c95SVishal Kulkarni ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8543*3dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8544*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 854556b2bdd1SGireesh Nagabhushana 8546*3dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_FCFI 0 8547*3dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8548*3dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8549*3dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8550*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 855156b2bdd1SGireesh Nagabhushana 8552*3dde7c95SVishal Kulkarni #define S_FW_FCOE_LINK_CMD_VNPI 0 8553*3dde7c95SVishal Kulkarni #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8554*3dde7c95SVishal Kulkarni #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8555*3dde7c95SVishal Kulkarni #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8556*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 855756b2bdd1SGireesh Nagabhushana 855856b2bdd1SGireesh Nagabhushana struct fw_fcoe_vnp_cmd { 855956b2bdd1SGireesh Nagabhushana __be32 op_to_fcfi; 856056b2bdd1SGireesh Nagabhushana __be32 alloc_to_len16; 856156b2bdd1SGireesh Nagabhushana __be32 gen_wwn_to_vnpi; 856256b2bdd1SGireesh Nagabhushana __be32 vf_id; 856356b2bdd1SGireesh Nagabhushana __be16 iqid; 856456b2bdd1SGireesh Nagabhushana __u8 vnport_mac[6]; 856556b2bdd1SGireesh Nagabhushana __u8 vnport_wwnn[8]; 856656b2bdd1SGireesh Nagabhushana __u8 vnport_wwpn[8]; 856756b2bdd1SGireesh Nagabhushana __u8 cmn_srv_parms[16]; 856856b2bdd1SGireesh Nagabhushana __u8 clsp_word_0_1[8]; 856956b2bdd1SGireesh Nagabhushana }; 857056b2bdd1SGireesh Nagabhushana 8571*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_FCFI 0 8572*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8573*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8574*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8575*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8576*3dde7c95SVishal Kulkarni 8577*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_ALLOC 31 8578*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8579*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8580*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8581*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8582*3dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8583*3dde7c95SVishal Kulkarni 8584*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_FREE 30 8585*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_FREE 0x1 8586*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8587*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_FREE(x) \ 8588*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8589*3dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8590*3dde7c95SVishal Kulkarni 8591*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_MODIFY 29 8592*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8593*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8594*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8595*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8596*3dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8597*3dde7c95SVishal Kulkarni 8598*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8599*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8600*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8601*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8602*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8603*3dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8604*3dde7c95SVishal Kulkarni 8605*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_PERSIST 21 8606*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8607*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8608*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8609*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8610*3dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8611*3dde7c95SVishal Kulkarni 8612*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8613*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8614*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8615*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8616*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8617*3dde7c95SVishal Kulkarni #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8618*3dde7c95SVishal Kulkarni 8619*3dde7c95SVishal Kulkarni #define S_FW_FCOE_VNP_CMD_VNPI 0 8620*3dde7c95SVishal Kulkarni #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8621*3dde7c95SVishal Kulkarni #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8622*3dde7c95SVishal Kulkarni #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8623*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 862456b2bdd1SGireesh Nagabhushana 862556b2bdd1SGireesh Nagabhushana struct fw_fcoe_sparams_cmd { 862656b2bdd1SGireesh Nagabhushana __be32 op_to_portid; 862756b2bdd1SGireesh Nagabhushana __be32 retval_len16; 862856b2bdd1SGireesh Nagabhushana __u8 r3[7]; 862956b2bdd1SGireesh Nagabhushana __u8 cos; 863056b2bdd1SGireesh Nagabhushana __u8 lport_wwnn[8]; 863156b2bdd1SGireesh Nagabhushana __u8 lport_wwpn[8]; 863256b2bdd1SGireesh Nagabhushana __u8 cmn_srv_parms[16]; 863356b2bdd1SGireesh Nagabhushana __u8 cls_srv_parms[16]; 863456b2bdd1SGireesh Nagabhushana }; 863556b2bdd1SGireesh Nagabhushana 8636*3dde7c95SVishal Kulkarni #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8637*3dde7c95SVishal Kulkarni #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8638*3dde7c95SVishal Kulkarni #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8639*3dde7c95SVishal Kulkarni #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8640*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 864156b2bdd1SGireesh Nagabhushana 864256b2bdd1SGireesh Nagabhushana struct fw_fcoe_stats_cmd { 864356b2bdd1SGireesh Nagabhushana __be32 op_to_flowid; 864456b2bdd1SGireesh Nagabhushana __be32 free_to_len16; 864556b2bdd1SGireesh Nagabhushana union fw_fcoe_stats { 864656b2bdd1SGireesh Nagabhushana struct fw_fcoe_stats_ctl { 864756b2bdd1SGireesh Nagabhushana __u8 nstats_port; 864856b2bdd1SGireesh Nagabhushana __u8 port_valid_ix; 864956b2bdd1SGireesh Nagabhushana __be16 r6; 865056b2bdd1SGireesh Nagabhushana __be32 r7; 865156b2bdd1SGireesh Nagabhushana __be64 stat0; 865256b2bdd1SGireesh Nagabhushana __be64 stat1; 865356b2bdd1SGireesh Nagabhushana __be64 stat2; 865456b2bdd1SGireesh Nagabhushana __be64 stat3; 865556b2bdd1SGireesh Nagabhushana __be64 stat4; 865656b2bdd1SGireesh Nagabhushana __be64 stat5; 865756b2bdd1SGireesh Nagabhushana } ctl; 865856b2bdd1SGireesh Nagabhushana struct fw_fcoe_port_stats { 865956b2bdd1SGireesh Nagabhushana __be64 tx_bcast_bytes; 866056b2bdd1SGireesh Nagabhushana __be64 tx_bcast_frames; 866156b2bdd1SGireesh Nagabhushana __be64 tx_mcast_bytes; 866256b2bdd1SGireesh Nagabhushana __be64 tx_mcast_frames; 866356b2bdd1SGireesh Nagabhushana __be64 tx_ucast_bytes; 866456b2bdd1SGireesh Nagabhushana __be64 tx_ucast_frames; 866556b2bdd1SGireesh Nagabhushana __be64 tx_drop_frames; 866656b2bdd1SGireesh Nagabhushana __be64 tx_offload_bytes; 866756b2bdd1SGireesh Nagabhushana __be64 tx_offload_frames; 866856b2bdd1SGireesh Nagabhushana __be64 rx_bcast_bytes; 866956b2bdd1SGireesh Nagabhushana __be64 rx_bcast_frames; 867056b2bdd1SGireesh Nagabhushana __be64 rx_mcast_bytes; 867156b2bdd1SGireesh Nagabhushana __be64 rx_mcast_frames; 867256b2bdd1SGireesh Nagabhushana __be64 rx_ucast_bytes; 867356b2bdd1SGireesh Nagabhushana __be64 rx_ucast_frames; 867456b2bdd1SGireesh Nagabhushana __be64 rx_err_frames; 867556b2bdd1SGireesh Nagabhushana } port_stats; 867656b2bdd1SGireesh Nagabhushana struct fw_fcoe_fcf_stats { 867756b2bdd1SGireesh Nagabhushana __be32 fip_tx_bytes; 867856b2bdd1SGireesh Nagabhushana __be32 fip_tx_fr; 867956b2bdd1SGireesh Nagabhushana __be64 fcf_ka; 868056b2bdd1SGireesh Nagabhushana __be64 mcast_adv_rcvd; 868156b2bdd1SGireesh Nagabhushana __be16 ucast_adv_rcvd; 868256b2bdd1SGireesh Nagabhushana __be16 sol_sent; 868356b2bdd1SGireesh Nagabhushana __be16 vlan_req; 868456b2bdd1SGireesh Nagabhushana __be16 vlan_rpl; 868556b2bdd1SGireesh Nagabhushana __be16 clr_vlink; 868656b2bdd1SGireesh Nagabhushana __be16 link_down; 868756b2bdd1SGireesh Nagabhushana __be16 link_up; 868856b2bdd1SGireesh Nagabhushana __be16 logo; 868956b2bdd1SGireesh Nagabhushana __be16 flogi_req; 869056b2bdd1SGireesh Nagabhushana __be16 flogi_rpl; 869156b2bdd1SGireesh Nagabhushana __be16 fdisc_req; 869256b2bdd1SGireesh Nagabhushana __be16 fdisc_rpl; 869356b2bdd1SGireesh Nagabhushana __be16 fka_prd_chg; 869456b2bdd1SGireesh Nagabhushana __be16 fc_map_chg; 869556b2bdd1SGireesh Nagabhushana __be16 vfid_chg; 869656b2bdd1SGireesh Nagabhushana __u8 no_fka_req; 869756b2bdd1SGireesh Nagabhushana __u8 no_vnp; 869856b2bdd1SGireesh Nagabhushana } fcf_stats; 869956b2bdd1SGireesh Nagabhushana struct fw_fcoe_pcb_stats { 870056b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 870156b2bdd1SGireesh Nagabhushana __be64 tx_frames; 870256b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 870356b2bdd1SGireesh Nagabhushana __be64 rx_frames; 870456b2bdd1SGireesh Nagabhushana __be32 vnp_ka; 870556b2bdd1SGireesh Nagabhushana __be32 unsol_els_rcvd; 870656b2bdd1SGireesh Nagabhushana __be64 unsol_cmd_rcvd; 870756b2bdd1SGireesh Nagabhushana __be16 implicit_logo; 870856b2bdd1SGireesh Nagabhushana __be16 flogi_inv_sparm; 870956b2bdd1SGireesh Nagabhushana __be16 fdisc_inv_sparm; 871056b2bdd1SGireesh Nagabhushana __be16 flogi_rjt; 871156b2bdd1SGireesh Nagabhushana __be16 fdisc_rjt; 871256b2bdd1SGireesh Nagabhushana __be16 no_ssn; 871356b2bdd1SGireesh Nagabhushana __be16 mac_flt_fail; 871456b2bdd1SGireesh Nagabhushana __be16 inv_fr_rcvd; 871556b2bdd1SGireesh Nagabhushana } pcb_stats; 871656b2bdd1SGireesh Nagabhushana struct fw_fcoe_scb_stats { 871756b2bdd1SGireesh Nagabhushana __be64 tx_bytes; 871856b2bdd1SGireesh Nagabhushana __be64 tx_frames; 871956b2bdd1SGireesh Nagabhushana __be64 rx_bytes; 872056b2bdd1SGireesh Nagabhushana __be64 rx_frames; 872156b2bdd1SGireesh Nagabhushana __be32 host_abrt_req; 872256b2bdd1SGireesh Nagabhushana __be32 adap_auto_abrt; 872356b2bdd1SGireesh Nagabhushana __be32 adap_abrt_rsp; 872456b2bdd1SGireesh Nagabhushana __be32 host_ios_req; 872556b2bdd1SGireesh Nagabhushana __be16 ssn_offl_ios; 872656b2bdd1SGireesh Nagabhushana __be16 ssn_not_rdy_ios; 872756b2bdd1SGireesh Nagabhushana __u8 rx_data_ddp_err; 872856b2bdd1SGireesh Nagabhushana __u8 ddp_flt_set_err; 872956b2bdd1SGireesh Nagabhushana __be16 rx_data_fr_err; 873056b2bdd1SGireesh Nagabhushana __u8 bad_st_abrt_req; 873156b2bdd1SGireesh Nagabhushana __u8 no_io_abrt_req; 873256b2bdd1SGireesh Nagabhushana __u8 abort_tmo; 873356b2bdd1SGireesh Nagabhushana __u8 abort_tmo_2; 873456b2bdd1SGireesh Nagabhushana __be32 abort_req; 873556b2bdd1SGireesh Nagabhushana __u8 no_ppod_res_tmo; 873656b2bdd1SGireesh Nagabhushana __u8 bp_tmo; 873756b2bdd1SGireesh Nagabhushana __u8 adap_auto_cls; 873856b2bdd1SGireesh Nagabhushana __u8 no_io_cls_req; 873956b2bdd1SGireesh Nagabhushana __be32 host_cls_req; 874056b2bdd1SGireesh Nagabhushana __be64 unsol_cmd_rcvd; 874156b2bdd1SGireesh Nagabhushana __be32 plogi_req_rcvd; 874256b2bdd1SGireesh Nagabhushana __be32 prli_req_rcvd; 874356b2bdd1SGireesh Nagabhushana __be16 logo_req_rcvd; 874456b2bdd1SGireesh Nagabhushana __be16 prlo_req_rcvd; 874556b2bdd1SGireesh Nagabhushana __be16 plogi_rjt_rcvd; 874656b2bdd1SGireesh Nagabhushana __be16 prli_rjt_rcvd; 874756b2bdd1SGireesh Nagabhushana __be32 adisc_req_rcvd; 874856b2bdd1SGireesh Nagabhushana __be32 rscn_rcvd; 874956b2bdd1SGireesh Nagabhushana __be32 rrq_req_rcvd; 875056b2bdd1SGireesh Nagabhushana __be32 unsol_els_rcvd; 875156b2bdd1SGireesh Nagabhushana __u8 adisc_rjt_rcvd; 875256b2bdd1SGireesh Nagabhushana __u8 scr_rjt; 875356b2bdd1SGireesh Nagabhushana __u8 ct_rjt; 875456b2bdd1SGireesh Nagabhushana __u8 inval_bls_rcvd; 875556b2bdd1SGireesh Nagabhushana __be32 ba_rjt_rcvd; 875656b2bdd1SGireesh Nagabhushana } scb_stats; 875756b2bdd1SGireesh Nagabhushana } u; 875856b2bdd1SGireesh Nagabhushana }; 875956b2bdd1SGireesh Nagabhushana 8760*3dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_FLOWID 0 8761*3dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 8762*3dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 8763*3dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 8764*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 8765*3dde7c95SVishal Kulkarni 8766*3dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_FREE 30 8767*3dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_FREE 0x1 8768*3dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 8769*3dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_FREE(x) \ 8770*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 8771*3dde7c95SVishal Kulkarni #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 8772*3dde7c95SVishal Kulkarni 8773*3dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_NSTATS 4 8774*3dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 8775*3dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 8776*3dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 8777*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 8778*3dde7c95SVishal Kulkarni 8779*3dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_PORT 0 8780*3dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_PORT 0x3 8781*3dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 8782*3dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_PORT(x) \ 8783*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 8784*3dde7c95SVishal Kulkarni 8785*3dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 8786*3dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 8787*3dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8788*3dde7c95SVishal Kulkarni ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 8789*3dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8790*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 8791*3dde7c95SVishal Kulkarni #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 8792*3dde7c95SVishal Kulkarni 8793*3dde7c95SVishal Kulkarni #define S_FW_FCOE_STATS_CMD_IX 0 8794*3dde7c95SVishal Kulkarni #define M_FW_FCOE_STATS_CMD_IX 0x3f 8795*3dde7c95SVishal Kulkarni #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 8796*3dde7c95SVishal Kulkarni #define G_FW_FCOE_STATS_CMD_IX(x) \ 8797*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 879856b2bdd1SGireesh Nagabhushana 879956b2bdd1SGireesh Nagabhushana struct fw_fcoe_fcf_cmd { 880056b2bdd1SGireesh Nagabhushana __be32 op_to_fcfi; 880156b2bdd1SGireesh Nagabhushana __be32 retval_len16; 880256b2bdd1SGireesh Nagabhushana __be16 priority_pkd; 880356b2bdd1SGireesh Nagabhushana __u8 mac[6]; 880456b2bdd1SGireesh Nagabhushana __u8 name_id[8]; 880556b2bdd1SGireesh Nagabhushana __u8 fabric[8]; 880656b2bdd1SGireesh Nagabhushana __be16 vf_id; 880756b2bdd1SGireesh Nagabhushana __be16 max_fcoe_size; 880856b2bdd1SGireesh Nagabhushana __u8 vlan_id; 880956b2bdd1SGireesh Nagabhushana __u8 fc_map[3]; 881056b2bdd1SGireesh Nagabhushana __be32 fka_adv; 881156b2bdd1SGireesh Nagabhushana __be32 r6; 881256b2bdd1SGireesh Nagabhushana __u8 r7_hi; 881356b2bdd1SGireesh Nagabhushana __u8 fpma_to_portid; 881456b2bdd1SGireesh Nagabhushana __u8 spma_mac[6]; 881556b2bdd1SGireesh Nagabhushana __be64 r8; 881656b2bdd1SGireesh Nagabhushana }; 881756b2bdd1SGireesh Nagabhushana 8818*3dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_FCFI 0 8819*3dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 8820*3dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 8821*3dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 8822*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 8823*3dde7c95SVishal Kulkarni 8824*3dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_PRIORITY 0 8825*3dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 8826*3dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 8827*3dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 8828*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 8829*3dde7c95SVishal Kulkarni 8830*3dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_FPMA 6 8831*3dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_FPMA 0x1 8832*3dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 8833*3dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 8834*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 8835*3dde7c95SVishal Kulkarni #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 8836*3dde7c95SVishal Kulkarni 8837*3dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_SPMA 5 8838*3dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_SPMA 0x1 8839*3dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 8840*3dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 8841*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 8842*3dde7c95SVishal Kulkarni #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 8843*3dde7c95SVishal Kulkarni 8844*3dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_LOGIN 4 8845*3dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 8846*3dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 8847*3dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 8848*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 8849*3dde7c95SVishal Kulkarni #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 8850*3dde7c95SVishal Kulkarni 8851*3dde7c95SVishal Kulkarni #define S_FW_FCOE_FCF_CMD_PORTID 0 8852*3dde7c95SVishal Kulkarni #define M_FW_FCOE_FCF_CMD_PORTID 0xf 8853*3dde7c95SVishal Kulkarni #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 8854*3dde7c95SVishal Kulkarni #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 8855*3dde7c95SVishal Kulkarni (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 8856*3dde7c95SVishal Kulkarni 8857*3dde7c95SVishal Kulkarni /****************************************************************************** 8858*3dde7c95SVishal Kulkarni * E R R O R a n d D E B U G C O M M A N D s 8859*3dde7c95SVishal Kulkarni ******************************************************/ 886056b2bdd1SGireesh Nagabhushana 886156b2bdd1SGireesh Nagabhushana enum fw_error_type { 8862de483253SVishal Kulkarni FW_ERROR_TYPE_EXCEPTION = 0x0, 8863de483253SVishal Kulkarni FW_ERROR_TYPE_HWMODULE = 0x1, 8864de483253SVishal Kulkarni FW_ERROR_TYPE_WR = 0x2, 8865de483253SVishal Kulkarni FW_ERROR_TYPE_ACL = 0x3, 886656b2bdd1SGireesh Nagabhushana }; 886756b2bdd1SGireesh Nagabhushana 8868*3dde7c95SVishal Kulkarni enum fw_dcb_ieee_locations { 8869*3dde7c95SVishal Kulkarni FW_IEEE_LOC_LOCAL, 8870*3dde7c95SVishal Kulkarni FW_IEEE_LOC_PEER, 8871*3dde7c95SVishal Kulkarni FW_IEEE_LOC_OPERATIONAL, 8872*3dde7c95SVishal Kulkarni }; 8873*3dde7c95SVishal Kulkarni 8874*3dde7c95SVishal Kulkarni struct fw_dcb_ieee_cmd { 8875*3dde7c95SVishal Kulkarni __be32 op_to_location; 8876*3dde7c95SVishal Kulkarni __be32 changed_to_len16; 8877*3dde7c95SVishal Kulkarni union fw_dcbx_stats { 8878*3dde7c95SVishal Kulkarni struct fw_dcbx_pfc_stats_ieee { 8879*3dde7c95SVishal Kulkarni __be32 pfc_mbc_pkd; 8880*3dde7c95SVishal Kulkarni __be32 pfc_willing_to_pfc_en; 8881*3dde7c95SVishal Kulkarni } dcbx_pfc_stats; 8882*3dde7c95SVishal Kulkarni struct fw_dcbx_ets_stats_ieee { 8883*3dde7c95SVishal Kulkarni __be32 cbs_to_ets_max_tc; 8884*3dde7c95SVishal Kulkarni __be32 pg_table; 8885*3dde7c95SVishal Kulkarni __u8 pg_percent[8]; 8886*3dde7c95SVishal Kulkarni __u8 tsa[8]; 8887*3dde7c95SVishal Kulkarni } dcbx_ets_stats; 8888*3dde7c95SVishal Kulkarni struct fw_dcbx_app_stats_ieee { 8889*3dde7c95SVishal Kulkarni __be32 num_apps_pkd; 8890*3dde7c95SVishal Kulkarni __be32 r6; 8891*3dde7c95SVishal Kulkarni __be32 app[4]; 8892*3dde7c95SVishal Kulkarni } dcbx_app_stats; 8893*3dde7c95SVishal Kulkarni struct fw_dcbx_control { 8894*3dde7c95SVishal Kulkarni __be32 multi_peer_invalidated; 8895*3dde7c95SVishal Kulkarni __be32 r5_lo; 8896*3dde7c95SVishal Kulkarni } dcbx_control; 8897*3dde7c95SVishal Kulkarni } u; 8898*3dde7c95SVishal Kulkarni }; 8899*3dde7c95SVishal Kulkarni 8900*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PORT 8 8901*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PORT 0x7 8902*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 8903*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PORT(x) \ 8904*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 8905*3dde7c95SVishal Kulkarni 8906*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_FEATURE 2 8907*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 8908*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 8909*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 8910*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 8911*3dde7c95SVishal Kulkarni 8912*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_LOCATION 0 8913*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 8914*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 8915*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 8916*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 8917*3dde7c95SVishal Kulkarni 8918*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_CHANGED 20 8919*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 8920*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 8921*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 8922*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 8923*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 8924*3dde7c95SVishal Kulkarni 8925*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_RECEIVED 19 8926*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 8927*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 8928*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 8929*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 8930*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 8931*3dde7c95SVishal Kulkarni 8932*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APPLY 18 8933*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APPLY 0x1 8934*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 8935*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 8936*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 8937*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 8938*3dde7c95SVishal Kulkarni 8939*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_DISABLED 17 8940*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 8941*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 8942*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 8943*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 8944*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 8945*3dde7c95SVishal Kulkarni 8946*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_MORE 16 8947*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_MORE 0x1 8948*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 8949*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_MORE(x) \ 8950*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 8951*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 8952*3dde7c95SVishal Kulkarni 8953*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 8954*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 8955*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 8956*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 8957*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 8958*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 8959*3dde7c95SVishal Kulkarni 8960*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 8961*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 8962*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8963*3dde7c95SVishal Kulkarni ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 8964*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8965*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 8966*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 8967*3dde7c95SVishal Kulkarni 8968*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 8969*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 8970*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8971*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 8972*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8973*3dde7c95SVishal Kulkarni 8974*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_PFC_EN 0 8975*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 8976*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 8977*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 8978*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 8979*3dde7c95SVishal Kulkarni 8980*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_CBS 16 8981*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_CBS 0x1 8982*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 8983*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_CBS(x) \ 8984*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 8985*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 8986*3dde7c95SVishal Kulkarni 8987*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 8988*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 8989*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8990*3dde7c95SVishal Kulkarni ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 8991*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8992*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 8993*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 8994*3dde7c95SVishal Kulkarni 8995*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 8996*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 8997*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8998*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 8999*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9000*3dde7c95SVishal Kulkarni 9001*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9002*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9003*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9004*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9005*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9006*3dde7c95SVishal Kulkarni 9007*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9008*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9009*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9010*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9011*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9012*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9013*3dde7c95SVishal Kulkarni 9014*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9015*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9016*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9017*3dde7c95SVishal Kulkarni ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9018*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9019*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9020*3dde7c95SVishal Kulkarni #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9021*3dde7c95SVishal Kulkarni 9022*3dde7c95SVishal Kulkarni /* Hand-written */ 9023*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9024*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9025*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9026*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9027*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9028*3dde7c95SVishal Kulkarni 9029*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9030*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9031*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9032*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9033*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9034*3dde7c95SVishal Kulkarni 9035*3dde7c95SVishal Kulkarni #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9036*3dde7c95SVishal Kulkarni #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9037*3dde7c95SVishal Kulkarni #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9038*3dde7c95SVishal Kulkarni #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9039*3dde7c95SVishal Kulkarni (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9040*3dde7c95SVishal Kulkarni 9041*3dde7c95SVishal Kulkarni 904256b2bdd1SGireesh Nagabhushana struct fw_error_cmd { 904356b2bdd1SGireesh Nagabhushana __be32 op_to_type; 904456b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 904556b2bdd1SGireesh Nagabhushana union fw_error { 904656b2bdd1SGireesh Nagabhushana struct fw_error_exception { 904756b2bdd1SGireesh Nagabhushana __be32 info[6]; 904856b2bdd1SGireesh Nagabhushana } exception; 904956b2bdd1SGireesh Nagabhushana struct fw_error_hwmodule { 905056b2bdd1SGireesh Nagabhushana __be32 regaddr; 905156b2bdd1SGireesh Nagabhushana __be32 regval; 905256b2bdd1SGireesh Nagabhushana } hwmodule; 905356b2bdd1SGireesh Nagabhushana struct fw_error_wr { 905456b2bdd1SGireesh Nagabhushana __be16 cidx; 905556b2bdd1SGireesh Nagabhushana __be16 pfn_vfn; 905656b2bdd1SGireesh Nagabhushana __be32 eqid; 905756b2bdd1SGireesh Nagabhushana __u8 wrhdr[16]; 905856b2bdd1SGireesh Nagabhushana } wr; 905956b2bdd1SGireesh Nagabhushana struct fw_error_acl { 906056b2bdd1SGireesh Nagabhushana __be16 cidx; 906156b2bdd1SGireesh Nagabhushana __be16 pfn_vfn; 906256b2bdd1SGireesh Nagabhushana __be32 eqid; 906356b2bdd1SGireesh Nagabhushana __be16 mv_pkd; 906456b2bdd1SGireesh Nagabhushana __u8 val[6]; 906556b2bdd1SGireesh Nagabhushana __be64 r4; 906656b2bdd1SGireesh Nagabhushana } acl; 906756b2bdd1SGireesh Nagabhushana } u; 906856b2bdd1SGireesh Nagabhushana }; 906956b2bdd1SGireesh Nagabhushana 9070*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_FATAL 4 9071*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_FATAL 0x1 9072*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9073*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_FATAL(x) \ 9074*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9075*3dde7c95SVishal Kulkarni #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9076*3dde7c95SVishal Kulkarni 9077*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_TYPE 0 9078*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_TYPE 0xf 9079*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9080*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_TYPE(x) \ 9081*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9082*3dde7c95SVishal Kulkarni 9083*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_PFN 8 9084*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_PFN 0x7 9085*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9086*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_PFN(x) \ 9087*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9088*3dde7c95SVishal Kulkarni 9089*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_VFN 0 9090*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_VFN 0xff 9091*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9092*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_VFN(x) \ 9093*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9094*3dde7c95SVishal Kulkarni 9095*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_PFN 8 9096*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_PFN 0x7 9097*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9098*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_PFN(x) \ 9099*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9100*3dde7c95SVishal Kulkarni 9101*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_VFN 0 9102*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_VFN 0xff 9103*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9104*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_VFN(x) \ 9105*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9106*3dde7c95SVishal Kulkarni 9107*3dde7c95SVishal Kulkarni #define S_FW_ERROR_CMD_MV 15 9108*3dde7c95SVishal Kulkarni #define M_FW_ERROR_CMD_MV 0x1 9109*3dde7c95SVishal Kulkarni #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9110*3dde7c95SVishal Kulkarni #define G_FW_ERROR_CMD_MV(x) \ 9111*3dde7c95SVishal Kulkarni (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9112*3dde7c95SVishal Kulkarni #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 911356b2bdd1SGireesh Nagabhushana 911456b2bdd1SGireesh Nagabhushana struct fw_debug_cmd { 911556b2bdd1SGireesh Nagabhushana __be32 op_type; 911656b2bdd1SGireesh Nagabhushana __be32 len16_pkd; 911756b2bdd1SGireesh Nagabhushana union fw_debug { 911856b2bdd1SGireesh Nagabhushana struct fw_debug_assert { 911956b2bdd1SGireesh Nagabhushana __be32 fcid; 912056b2bdd1SGireesh Nagabhushana __be32 line; 912156b2bdd1SGireesh Nagabhushana __be32 x; 912256b2bdd1SGireesh Nagabhushana __be32 y; 912356b2bdd1SGireesh Nagabhushana __u8 filename_0_7[8]; 912456b2bdd1SGireesh Nagabhushana __u8 filename_8_15[8]; 912556b2bdd1SGireesh Nagabhushana __be64 r3; 912656b2bdd1SGireesh Nagabhushana } assert; 912756b2bdd1SGireesh Nagabhushana struct fw_debug_prt { 912856b2bdd1SGireesh Nagabhushana __be16 dprtstridx; 912956b2bdd1SGireesh Nagabhushana __be16 r3[3]; 913056b2bdd1SGireesh Nagabhushana __be32 dprtstrparam0; 913156b2bdd1SGireesh Nagabhushana __be32 dprtstrparam1; 913256b2bdd1SGireesh Nagabhushana __be32 dprtstrparam2; 913356b2bdd1SGireesh Nagabhushana __be32 dprtstrparam3; 913456b2bdd1SGireesh Nagabhushana } prt; 913556b2bdd1SGireesh Nagabhushana } u; 913656b2bdd1SGireesh Nagabhushana }; 913756b2bdd1SGireesh Nagabhushana 9138*3dde7c95SVishal Kulkarni #define S_FW_DEBUG_CMD_TYPE 0 9139*3dde7c95SVishal Kulkarni #define M_FW_DEBUG_CMD_TYPE 0xff 9140*3dde7c95SVishal Kulkarni #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9141*3dde7c95SVishal Kulkarni #define G_FW_DEBUG_CMD_TYPE(x) \ 9142*3dde7c95SVishal Kulkarni (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 914356b2bdd1SGireesh Nagabhushana 9144*3dde7c95SVishal Kulkarni enum fw_diag_cmd_type { 9145*3dde7c95SVishal Kulkarni FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9146*3dde7c95SVishal Kulkarni }; 9147*3dde7c95SVishal Kulkarni 9148*3dde7c95SVishal Kulkarni enum fw_diag_cmd_ofldiag_op { 9149*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9150*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_START, 9151*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9152*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9153*3dde7c95SVishal Kulkarni }; 9154*3dde7c95SVishal Kulkarni 9155*3dde7c95SVishal Kulkarni enum fw_diag_cmd_ofldiag_status { 9156*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9157*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9158*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9159*3dde7c95SVishal Kulkarni FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9160*3dde7c95SVishal Kulkarni }; 9161*3dde7c95SVishal Kulkarni 9162*3dde7c95SVishal Kulkarni struct fw_diag_cmd { 9163*3dde7c95SVishal Kulkarni __be32 op_type; 9164*3dde7c95SVishal Kulkarni __be32 len16_pkd; 9165*3dde7c95SVishal Kulkarni union fw_diag_test { 9166*3dde7c95SVishal Kulkarni struct fw_diag_test_ofldiag { 9167*3dde7c95SVishal Kulkarni __u8 test_op; 9168*3dde7c95SVishal Kulkarni __u8 r3; 9169*3dde7c95SVishal Kulkarni __be16 test_status; 9170*3dde7c95SVishal Kulkarni __be32 duration; 9171*3dde7c95SVishal Kulkarni } ofldiag; 9172*3dde7c95SVishal Kulkarni } u; 9173*3dde7c95SVishal Kulkarni }; 9174*3dde7c95SVishal Kulkarni 9175*3dde7c95SVishal Kulkarni #define S_FW_DIAG_CMD_TYPE 0 9176*3dde7c95SVishal Kulkarni #define M_FW_DIAG_CMD_TYPE 0xff 9177*3dde7c95SVishal Kulkarni #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9178*3dde7c95SVishal Kulkarni #define G_FW_DIAG_CMD_TYPE(x) \ 9179*3dde7c95SVishal Kulkarni (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9180*3dde7c95SVishal Kulkarni 9181*3dde7c95SVishal Kulkarni /****************************************************************************** 9182*3dde7c95SVishal Kulkarni * P C I E F W R E G I S T E R 9183*3dde7c95SVishal Kulkarni **************************************/ 918456b2bdd1SGireesh Nagabhushana 9185de483253SVishal Kulkarni enum pcie_fw_eval { 9186de483253SVishal Kulkarni PCIE_FW_EVAL_CRASH = 0, 9187de483253SVishal Kulkarni PCIE_FW_EVAL_PREP = 1, 9188de483253SVishal Kulkarni PCIE_FW_EVAL_CONF = 2, 9189de483253SVishal Kulkarni PCIE_FW_EVAL_INIT = 3, 9190de483253SVishal Kulkarni PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9191de483253SVishal Kulkarni PCIE_FW_EVAL_OVERHEAT = 5, 9192de483253SVishal Kulkarni PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9193de483253SVishal Kulkarni }; 9194de483253SVishal Kulkarni 9195*3dde7c95SVishal Kulkarni /** 919656b2bdd1SGireesh Nagabhushana * Register definitions for the PCIE_FW register which the firmware uses 9197de483253SVishal Kulkarni * to retain status across RESETs. This register should be considered 919856b2bdd1SGireesh Nagabhushana * as a READ-ONLY register for Host Software and only to be used to 919956b2bdd1SGireesh Nagabhushana * track firmware initialization/error state, etc. 920056b2bdd1SGireesh Nagabhushana */ 9201*3dde7c95SVishal Kulkarni #define S_PCIE_FW_ERR 31 9202*3dde7c95SVishal Kulkarni #define M_PCIE_FW_ERR 0x1 9203*3dde7c95SVishal Kulkarni #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9204*3dde7c95SVishal Kulkarni #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9205*3dde7c95SVishal Kulkarni #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9206*3dde7c95SVishal Kulkarni 9207*3dde7c95SVishal Kulkarni #define S_PCIE_FW_INIT 30 9208*3dde7c95SVishal Kulkarni #define M_PCIE_FW_INIT 0x1 9209*3dde7c95SVishal Kulkarni #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9210*3dde7c95SVishal Kulkarni #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9211*3dde7c95SVishal Kulkarni #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9212*3dde7c95SVishal Kulkarni 9213*3dde7c95SVishal Kulkarni #define S_PCIE_FW_HALT 29 9214*3dde7c95SVishal Kulkarni #define M_PCIE_FW_HALT 0x1 9215*3dde7c95SVishal Kulkarni #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9216*3dde7c95SVishal Kulkarni #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9217*3dde7c95SVishal Kulkarni #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 921856b2bdd1SGireesh Nagabhushana 9219de483253SVishal Kulkarni #define S_PCIE_FW_EVAL 24 9220de483253SVishal Kulkarni #define M_PCIE_FW_EVAL 0x7 9221de483253SVishal Kulkarni #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9222de483253SVishal Kulkarni #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9223de483253SVishal Kulkarni 9224*3dde7c95SVishal Kulkarni #define S_PCIE_FW_STAGE 21 9225*3dde7c95SVishal Kulkarni #define M_PCIE_FW_STAGE 0x7 9226*3dde7c95SVishal Kulkarni #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9227*3dde7c95SVishal Kulkarni #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9228*3dde7c95SVishal Kulkarni 9229*3dde7c95SVishal Kulkarni #define S_PCIE_FW_ASYNCNOT_VLD 20 9230*3dde7c95SVishal Kulkarni #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9231*3dde7c95SVishal Kulkarni #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9232*3dde7c95SVishal Kulkarni ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9233*3dde7c95SVishal Kulkarni #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9234*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9235*3dde7c95SVishal Kulkarni #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9236*3dde7c95SVishal Kulkarni 9237*3dde7c95SVishal Kulkarni #define S_PCIE_FW_ASYNCNOTINT 19 9238*3dde7c95SVishal Kulkarni #define M_PCIE_FW_ASYNCNOTINT 0x1 9239*3dde7c95SVishal Kulkarni #define V_PCIE_FW_ASYNCNOTINT(x) \ 9240*3dde7c95SVishal Kulkarni ((x) << S_PCIE_FW_ASYNCNOTINT) 9241*3dde7c95SVishal Kulkarni #define G_PCIE_FW_ASYNCNOTINT(x) \ 9242*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9243*3dde7c95SVishal Kulkarni #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9244*3dde7c95SVishal Kulkarni 9245*3dde7c95SVishal Kulkarni #define S_PCIE_FW_ASYNCNOT 16 9246*3dde7c95SVishal Kulkarni #define M_PCIE_FW_ASYNCNOT 0x7 9247*3dde7c95SVishal Kulkarni #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9248*3dde7c95SVishal Kulkarni #define G_PCIE_FW_ASYNCNOT(x) \ 9249*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9250*3dde7c95SVishal Kulkarni 9251*3dde7c95SVishal Kulkarni #define S_PCIE_FW_MASTER_VLD 15 9252*3dde7c95SVishal Kulkarni #define M_PCIE_FW_MASTER_VLD 0x1 9253*3dde7c95SVishal Kulkarni #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9254*3dde7c95SVishal Kulkarni #define G_PCIE_FW_MASTER_VLD(x) \ 9255*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9256*3dde7c95SVishal Kulkarni #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9257*3dde7c95SVishal Kulkarni 9258*3dde7c95SVishal Kulkarni #define S_PCIE_FW_MASTER 12 9259*3dde7c95SVishal Kulkarni #define M_PCIE_FW_MASTER 0x7 9260*3dde7c95SVishal Kulkarni #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9261*3dde7c95SVishal Kulkarni #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9262*3dde7c95SVishal Kulkarni 9263*3dde7c95SVishal Kulkarni #define S_PCIE_FW_RESET_VLD 11 9264*3dde7c95SVishal Kulkarni #define M_PCIE_FW_RESET_VLD 0x1 9265*3dde7c95SVishal Kulkarni #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9266*3dde7c95SVishal Kulkarni #define G_PCIE_FW_RESET_VLD(x) \ 9267*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9268*3dde7c95SVishal Kulkarni #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9269*3dde7c95SVishal Kulkarni 9270*3dde7c95SVishal Kulkarni #define S_PCIE_FW_RESET 8 9271*3dde7c95SVishal Kulkarni #define M_PCIE_FW_RESET 0x7 9272*3dde7c95SVishal Kulkarni #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9273*3dde7c95SVishal Kulkarni #define G_PCIE_FW_RESET(x) \ 9274*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9275*3dde7c95SVishal Kulkarni 9276*3dde7c95SVishal Kulkarni #define S_PCIE_FW_REGISTERED 0 9277*3dde7c95SVishal Kulkarni #define M_PCIE_FW_REGISTERED 0xff 9278*3dde7c95SVishal Kulkarni #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9279*3dde7c95SVishal Kulkarni #define G_PCIE_FW_REGISTERED(x) \ 9280*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9281*3dde7c95SVishal Kulkarni 9282*3dde7c95SVishal Kulkarni 9283*3dde7c95SVishal Kulkarni /****************************************************************************** 9284*3dde7c95SVishal Kulkarni * P C I E F W P F 0 R E G I S T E R 9285*3dde7c95SVishal Kulkarni **********************************************/ 928656b2bdd1SGireesh Nagabhushana 928756b2bdd1SGireesh Nagabhushana /* 9288*3dde7c95SVishal Kulkarni * this register is available as 32-bit of persistent storage (accross 9289*3dde7c95SVishal Kulkarni * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9290*3dde7c95SVishal Kulkarni * will not write it) 929156b2bdd1SGireesh Nagabhushana */ 929256b2bdd1SGireesh Nagabhushana 9293*3dde7c95SVishal Kulkarni 9294*3dde7c95SVishal Kulkarni /****************************************************************************** 9295*3dde7c95SVishal Kulkarni * P C I E F W P F 7 R E G I S T E R 9296*3dde7c95SVishal Kulkarni **********************************************/ 9297*3dde7c95SVishal Kulkarni 9298*3dde7c95SVishal Kulkarni /* 9299*3dde7c95SVishal Kulkarni * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9300*3dde7c95SVishal Kulkarni * access the "devlog" which needing to contact firmware. The encoding is 9301*3dde7c95SVishal Kulkarni * mostly the same as that returned by the DEVLOG command except for the size 9302*3dde7c95SVishal Kulkarni * which is encoded as the number of entries in multiples-1 of 128 here rather 9303*3dde7c95SVishal Kulkarni * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9304*3dde7c95SVishal Kulkarni * and 15 means 2048. This of course in turn constrains the allowed values 9305*3dde7c95SVishal Kulkarni * for the devlog size ... 9306*3dde7c95SVishal Kulkarni */ 9307*3dde7c95SVishal Kulkarni #define PCIE_FW_PF_DEVLOG 7 9308*3dde7c95SVishal Kulkarni 9309*3dde7c95SVishal Kulkarni #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9310*3dde7c95SVishal Kulkarni #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9311*3dde7c95SVishal Kulkarni #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9312*3dde7c95SVishal Kulkarni ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9313*3dde7c95SVishal Kulkarni #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9314*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9315*3dde7c95SVishal Kulkarni M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9316*3dde7c95SVishal Kulkarni 9317*3dde7c95SVishal Kulkarni #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9318*3dde7c95SVishal Kulkarni #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9319*3dde7c95SVishal Kulkarni #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9320*3dde7c95SVishal Kulkarni #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9321*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9322*3dde7c95SVishal Kulkarni 9323*3dde7c95SVishal Kulkarni #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9324*3dde7c95SVishal Kulkarni #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9325*3dde7c95SVishal Kulkarni #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9326*3dde7c95SVishal Kulkarni #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9327*3dde7c95SVishal Kulkarni (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9328*3dde7c95SVishal Kulkarni 9329*3dde7c95SVishal Kulkarni 9330*3dde7c95SVishal Kulkarni /****************************************************************************** 9331*3dde7c95SVishal Kulkarni * B I N A R Y H E A D E R F O R M A T 9332*3dde7c95SVishal Kulkarni **********************************************/ 9333*3dde7c95SVishal Kulkarni 933456b2bdd1SGireesh Nagabhushana /* 933556b2bdd1SGireesh Nagabhushana * firmware binary header format 933656b2bdd1SGireesh Nagabhushana */ 933756b2bdd1SGireesh Nagabhushana struct fw_hdr { 933856b2bdd1SGireesh Nagabhushana __u8 ver; 933956b2bdd1SGireesh Nagabhushana __u8 chip; /* terminator chip family */ 934056b2bdd1SGireesh Nagabhushana __be16 len512; /* bin length in units of 512-bytes */ 934156b2bdd1SGireesh Nagabhushana __be32 fw_ver; /* firmware version */ 934256b2bdd1SGireesh Nagabhushana __be32 tp_microcode_ver; /* tcp processor microcode version */ 934356b2bdd1SGireesh Nagabhushana __u8 intfver_nic; 934456b2bdd1SGireesh Nagabhushana __u8 intfver_vnic; 934556b2bdd1SGireesh Nagabhushana __u8 intfver_ofld; 934656b2bdd1SGireesh Nagabhushana __u8 intfver_ri; 934756b2bdd1SGireesh Nagabhushana __u8 intfver_iscsipdu; 934856b2bdd1SGireesh Nagabhushana __u8 intfver_iscsi; 9349de483253SVishal Kulkarni __u8 intfver_fcoepdu; 935056b2bdd1SGireesh Nagabhushana __u8 intfver_fcoe; 9351de483253SVishal Kulkarni __u32 reserved2; 935256b2bdd1SGireesh Nagabhushana __u32 reserved3; 9353*3dde7c95SVishal Kulkarni __be32 magic; /* runtime or bootstrap fw */ 935456b2bdd1SGireesh Nagabhushana __be32 flags; 935556b2bdd1SGireesh Nagabhushana __be32 reserved6[23]; 935656b2bdd1SGireesh Nagabhushana }; 935756b2bdd1SGireesh Nagabhushana 935856b2bdd1SGireesh Nagabhushana enum fw_hdr_chip { 935956b2bdd1SGireesh Nagabhushana FW_HDR_CHIP_T4, 9360*3dde7c95SVishal Kulkarni FW_HDR_CHIP_T5, 9361*3dde7c95SVishal Kulkarni FW_HDR_CHIP_T6 9362*3dde7c95SVishal Kulkarni }; 9363*3dde7c95SVishal Kulkarni 9364*3dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_MAJOR 24 9365*3dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_MAJOR 0xff 9366*3dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_MAJOR(x) \ 9367*3dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_MAJOR) 9368*3dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_MAJOR(x) \ 9369*3dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9370*3dde7c95SVishal Kulkarni 9371*3dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_MINOR 16 9372*3dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_MINOR 0xff 9373*3dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_MINOR(x) \ 9374*3dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_MINOR) 9375*3dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_MINOR(x) \ 9376*3dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9377*3dde7c95SVishal Kulkarni 9378*3dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_MICRO 8 9379*3dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_MICRO 0xff 9380*3dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_MICRO(x) \ 9381*3dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_MICRO) 9382*3dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_MICRO(x) \ 9383*3dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9384*3dde7c95SVishal Kulkarni 9385*3dde7c95SVishal Kulkarni #define S_FW_HDR_FW_VER_BUILD 0 9386*3dde7c95SVishal Kulkarni #define M_FW_HDR_FW_VER_BUILD 0xff 9387*3dde7c95SVishal Kulkarni #define V_FW_HDR_FW_VER_BUILD(x) \ 9388*3dde7c95SVishal Kulkarni ((x) << S_FW_HDR_FW_VER_BUILD) 9389*3dde7c95SVishal Kulkarni #define G_FW_HDR_FW_VER_BUILD(x) \ 9390*3dde7c95SVishal Kulkarni (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9391de483253SVishal Kulkarni 9392de483253SVishal Kulkarni enum { 9393*3dde7c95SVishal Kulkarni /* T4 9394*3dde7c95SVishal Kulkarni */ 9395*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_NIC = 0x00, 9396*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_VNIC = 0x00, 9397*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_OFLD = 0x00, 9398*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_RI = 0x00, 9399*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_ISCSIPDU = 0x00, 9400*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_ISCSI = 0x00, 9401*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_FCOEPDU = 0x00, 9402*3dde7c95SVishal Kulkarni FW_HDR_INTFVER_FCOE = 0x00, 9403*3dde7c95SVishal Kulkarni 9404*3dde7c95SVishal Kulkarni /* T5 9405*3dde7c95SVishal Kulkarni */ 9406*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_NIC = 0x00, 9407*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_VNIC = 0x00, 9408*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_OFLD = 0x00, 9409*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_RI = 0x00, 9410*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9411*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_ISCSI = 0x00, 9412*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9413*3dde7c95SVishal Kulkarni T5FW_HDR_INTFVER_FCOE = 0x00, 9414*3dde7c95SVishal Kulkarni 9415*3dde7c95SVishal Kulkarni /* T6 9416*3dde7c95SVishal Kulkarni */ 9417*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_NIC = 0x00, 9418*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_VNIC = 0x00, 9419*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_OFLD = 0x00, 9420*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_RI = 0x00, 9421*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9422*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_ISCSI = 0x00, 9423*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9424*3dde7c95SVishal Kulkarni T6FW_HDR_INTFVER_FCOE = 0x00, 942556b2bdd1SGireesh Nagabhushana }; 942656b2bdd1SGireesh Nagabhushana 9427de483253SVishal Kulkarni enum { 9428de483253SVishal Kulkarni FW_HDR_MAGIC_RUNTIME = 0x00000000, 9429de483253SVishal Kulkarni FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9430de483253SVishal Kulkarni }; 9431*3dde7c95SVishal Kulkarni 943256b2bdd1SGireesh Nagabhushana enum fw_hdr_flags { 943356b2bdd1SGireesh Nagabhushana FW_HDR_FLAGS_RESET_HALT = 0x00000001, 943456b2bdd1SGireesh Nagabhushana }; 943556b2bdd1SGireesh Nagabhushana 9436*3dde7c95SVishal Kulkarni /* 9437*3dde7c95SVishal Kulkarni * External PHY firmware binary header format 9438*3dde7c95SVishal Kulkarni */ 9439*3dde7c95SVishal Kulkarni struct fw_ephy_hdr { 9440*3dde7c95SVishal Kulkarni __u8 ver; 9441*3dde7c95SVishal Kulkarni __u8 reserved; 9442*3dde7c95SVishal Kulkarni __be16 len512; /* bin length in units of 512-bytes */ 9443*3dde7c95SVishal Kulkarni __be32 magic; 9444*3dde7c95SVishal Kulkarni 9445*3dde7c95SVishal Kulkarni __be16 vendor_id; 9446*3dde7c95SVishal Kulkarni __be16 device_id; 9447*3dde7c95SVishal Kulkarni __be32 version; 9448*3dde7c95SVishal Kulkarni 9449*3dde7c95SVishal Kulkarni __be32 reserved1[4]; 9450*3dde7c95SVishal Kulkarni }; 9451*3dde7c95SVishal Kulkarni 9452*3dde7c95SVishal Kulkarni enum { 9453*3dde7c95SVishal Kulkarni FW_EPHY_HDR_MAGIC = 0x65706879, 9454*3dde7c95SVishal Kulkarni }; 9455*3dde7c95SVishal Kulkarni 945656b2bdd1SGireesh Nagabhushana #endif /* _T4FW_INTERFACE_H_ */ 9457