1
2/*
3 * This file and its contents are supplied under the terms of the
4 * Common Development and Distribution License ("CDDL"), version 1.0.
5 * You may only use this file in accordance with the terms of version
6 * 1.0 of the CDDL.
7 *
8 * A full copy of the text of the CDDL should have accompanied this
9 * source. A copy of the CDDL is also available via the Internet at
10 * http://www.illumos.org/license/CDDL.
11 */
12
13/* This file is automatically generated --- changes will be lost */
14/* Generation Date : Fri Jun 22 10:51:50 PDT 2018 */
15/* Directory name: t4_reg.txt, Date: Not specified */
16/* Directory name: t5_reg.txt, Changeset: 6940:daefc1fa1d8a */
17/* Directory name: t6_reg.txt, Changeset: 4270:552778f380ec */
18
19#define MYPF_BASE 0x1b000
20#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
21
22#define PF0_BASE 0x1e000
23#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
24
25#define PF1_BASE 0x1e400
26#define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
27
28#define PF2_BASE 0x1e800
29#define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
30
31#define PF3_BASE 0x1ec00
32#define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
33
34#define PF4_BASE 0x1f000
35#define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
36
37#define PF5_BASE 0x1f400
38#define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
39
40#define PF6_BASE 0x1f800
41#define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
42
43#define PF7_BASE 0x1fc00
44#define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
45
46#define PF_STRIDE 0x400
47#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
48#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
49
50#define VF_SGE_BASE 0x0
51#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
52
53#define VF_MPS_BASE 0x100
54#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
55
56#define VF_PL_BASE 0x200
57#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
58
59#define VF_MBDATA_BASE 0x240
60#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
61
62#define VF_CIM_BASE 0x300
63#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
64
65#define MYPORT_BASE 0x1c000
66#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
67
68#define PORT0_BASE 0x20000
69#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
70
71#define PORT1_BASE 0x22000
72#define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
73
74#define PORT2_BASE 0x24000
75#define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
76
77#define PORT3_BASE 0x26000
78#define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
79
80#define PORT_STRIDE 0x2000
81#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
82#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
83
84#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
85#define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
86
87#define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
88#define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
89
90#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
91#define NUM_PCIE_DMA_INSTANCES 4
92
93#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
94#define NUM_PCIE_CMD_INSTANCES 2
95
96#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
97#define NUM_PCIE_HMA_INSTANCES 1
98
99#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
100#define NUM_PCIE_MEM_ACCESS_INSTANCES 8
101
102#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
103#define NUM_PCIE_MAILBOX_INSTANCES 1
104
105#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
106#define NUM_PCIE_FW_INSTANCES 8
107
108#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
109#define NUM_PCIE_FUNC_INSTANCES 256
110
111#define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
112#define NUM_PCIE_FID_INSTANCES 2048
113
114#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
115#define NUM_PCIE_DMA_BUF_INSTANCES 4
116
117#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
118#define NUM_MC_DDR3PHYDATX8_INSTANCES 9
119
120#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
121#define NUM_MC_BIST_STATUS_INSTANCES 18
122
123#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
124#define NUM_EDC_BIST_STATUS_INSTANCES 18
125
126#define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
127#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
128
129#define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
130#define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
131
132#define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
133#define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
134
135#define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
136#define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
137
138#define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
139#define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
140
141#define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
142#define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
143
144#define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
145#define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
146
147#define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
148#define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
149
150#define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
151#define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
152
153#define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
154#define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
155
156#define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
157#define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
158
159#define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
160#define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
161
162#define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
163#define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
164
165#define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
166#define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
167
168#define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
169#define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
170
171#define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
172#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
173
174#define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
175#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
176
177#define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
178#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
179
180#define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
181#define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
182
183#define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
184#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
185
186#define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
187#define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
188
189#define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
190#define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
191
192#define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
193#define NUM_PL_VF_SLICE_L_INSTANCES 8
194
195#define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
196#define NUM_PL_VF_SLICE_H_INSTANCES 8
197
198#define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
199#define NUM_PL_FLR_VF_STATUS_INSTANCES 4
200
201#define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
202#define NUM_PL_VFID_MAP_INSTANCES 256
203
204#define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
205#define NUM_LE_DB_MASK_IPV4_INSTANCES 17
206
207#define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
208#define NUM_LE_DB_MASK_IPV6_INSTANCES 17
209
210#define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
211#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
212
213#define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
214#define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
215
216#define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
217#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
218
219#define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
220#define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
221
222#define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
223#define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
224
225#define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
226#define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
227
228#define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
229#define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
230
231#define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
232#define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
233
234#define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
235#define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
236
237#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
238#define NUM_UP_TSCH_CHANNEL_INSTANCES 4
239
240#define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
241#define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
242
243#define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
244#define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
245
246#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
247#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
248
249#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
250#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
251
252#define T5_MYPORT_BASE 0x2c000
253#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
254
255#define T5_PORT0_BASE 0x30000
256#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
257
258#define T5_PORT1_BASE 0x34000
259#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
260
261#define T5_PORT2_BASE 0x38000
262#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
263
264#define T5_PORT3_BASE 0x3c000
265#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
266
267#define T5_PORT_STRIDE 0x4000
268#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
269#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
270
271#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
272#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
273
274#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
275#define NUM_PCIE_PF_INT_INSTANCES 8
276
277#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
278#define NUM_PCIE_VF_INT_INSTANCES 128
279
280#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
281#define NUM_PCIE_FID_VFID_INSTANCES 2048
282
283#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
284#define NUM_PCIE_COOKIE_INSTANCES 8
285
286#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
287#define NUM_PCIE_T5_DMA_INSTANCES 4
288
289#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
290#define NUM_PCIE_T5_CMD_INSTANCES 3
291
292#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
293#define NUM_PCIE_T5_HMA_INSTANCES 1
294
295#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
296#define NUM_PCIE_PHY_PRESET_INSTANCES 11
297
298#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
299#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
300
301#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
302#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
303
304#define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
305#define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
306
307#define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
308#define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
309
310#define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
311#define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
312
313#define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
314#define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
315
316#define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
317#define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
318
319#define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
320#define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
321
322#define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
323#define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
324
325#define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
326#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
327
328#define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
329#define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
330
331#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
332#define NUM_MC_ADR_INSTANCES 2
333
334#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
335#define NUM_MC_DDRPHY_DP18_INSTANCES 5
336
337#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
338#define NUM_MC_CE_ERR_DATA_INSTANCES 8
339
340#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
341#define NUM_MC_CE_COR_DATA_INSTANCES 8
342
343#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
344#define NUM_MC_UE_ERR_DATA_INSTANCES 8
345
346#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
347#define NUM_MC_UE_COR_DATA_INSTANCES 8
348
349#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
350#define NUM_MC_P_BIST_STATUS_INSTANCES 18
351
352#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
353#define NUM_EDC_H_BIST_STATUS_INSTANCES 18
354
355#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
356#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
357
358#define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
359#define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
360
361#define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
362#define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
363
364#define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
365#define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
366
367#define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
368#define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
369
370#define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
371#define NUM_PCIE_T6_DMA_INSTANCES 2
372
373#define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
374#define NUM_PCIE_T6_CMD_INSTANCES 1
375
376#define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
377#define NUM_PCIE_VF_256_INT_INSTANCES 128
378
379#define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
380#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
381
382#define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
383#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
384
385#define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
386#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
387
388#define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
389#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
390
391#define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
392#define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
393
394#define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
395#define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
396
397#define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
398#define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
399
400#define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
401#define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
402
403#define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
404#define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
405
406#define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
407#define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
408
409#define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
410#define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
411
412#define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
413#define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
414
415#define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
416#define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
417
418#define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
419#define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
420
421#define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
422#define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
423
424#define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
425#define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
426
427#define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
428#define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
429
430#define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
431#define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
432
433#define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
434#define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
435
436#define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
437#define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
438
439#define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
440#define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
441
442#define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
443#define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
444
445#define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
446#define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
447
448#define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
449#define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
450
451#define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
452#define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
453
454#define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
455#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
456
457#define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
458#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
459
460#define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
461#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
462
463#define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
464#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
465
466#define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
467#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
468
469#define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
470#define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
471
472#define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
473#define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
474
475#define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
476#define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
477
478#define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
479#define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
480
481#define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
482#define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
483
484#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
485#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
486
487#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
488#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
489
490/* registers for module SGE */
491#define SGE_BASE_ADDR 0x1000
492
493#define A_SGE_PF_KDOORBELL 0x0
494
495#define S_QID    15
496#define M_QID    0x1ffffU
497#define V_QID(x) ((x) << S_QID)
498#define G_QID(x) (((x) >> S_QID) & M_QID)
499
500#define S_DBPRIO    14
501#define V_DBPRIO(x) ((x) << S_DBPRIO)
502#define F_DBPRIO    V_DBPRIO(1U)
503
504#define S_PIDX    0
505#define M_PIDX    0x3fffU
506#define V_PIDX(x) ((x) << S_PIDX)
507#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
508
509#define A_SGE_VF_KDOORBELL 0x0
510
511#define S_DBTYPE    13
512#define V_DBTYPE(x) ((x) << S_DBTYPE)
513#define F_DBTYPE    V_DBTYPE(1U)
514
515#define S_PIDX_T5    0
516#define M_PIDX_T5    0x1fffU
517#define V_PIDX_T5(x) ((x) << S_PIDX_T5)
518#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
519
520#define S_SYNC_T6    14
521#define V_SYNC_T6(x) ((x) << S_SYNC_T6)
522#define F_SYNC_T6    V_SYNC_T6(1U)
523
524#define A_SGE_PF_GTS 0x4
525
526#define S_INGRESSQID    16
527#define M_INGRESSQID    0xffffU
528#define V_INGRESSQID(x) ((x) << S_INGRESSQID)
529#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
530
531#define S_TIMERREG    13
532#define M_TIMERREG    0x7U
533#define V_TIMERREG(x) ((x) << S_TIMERREG)
534#define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
535
536#define S_SEINTARM    12
537#define V_SEINTARM(x) ((x) << S_SEINTARM)
538#define F_SEINTARM    V_SEINTARM(1U)
539
540#define S_CIDXINC    0
541#define M_CIDXINC    0xfffU
542#define V_CIDXINC(x) ((x) << S_CIDXINC)
543#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
544
545#define A_SGE_VF_GTS 0x4
546#define A_SGE_PF_KTIMESTAMP_LO 0x8
547#define A_SGE_VF_KTIMESTAMP_LO 0x8
548#define A_SGE_PF_KTIMESTAMP_HI 0xc
549
550#define S_TSTAMPVAL    0
551#define M_TSTAMPVAL    0xfffffffU
552#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
553#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
554
555#define A_SGE_VF_KTIMESTAMP_HI 0xc
556#define A_SGE_CONTROL 0x1008
557
558#define S_FLSPLITMODE    20
559#define M_FLSPLITMODE    0x3U
560#define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
561#define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
562
563#define S_RXPKTCPLMODE    18
564#define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
565#define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)
566
567#define S_EGRSTATUSPAGESIZE    17
568#define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
569#define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)
570
571#define S_PKTSHIFT    10
572#define M_PKTSHIFT    0x7U
573#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
574#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
575
576#define S_INGPADBOUNDARY    4
577#define M_INGPADBOUNDARY    0x7U
578#define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
579#define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
580
581#define S_GLOBALENABLE    0
582#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
583#define F_GLOBALENABLE    V_GLOBALENABLE(1U)
584
585#define S_IGRALLCPLTOFL    31
586#define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
587#define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)
588
589#define S_FLSPLITMIN    22
590#define M_FLSPLITMIN    0x1ffU
591#define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
592#define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
593
594#define S_INGHINTENABLE1    15
595#define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
596#define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)
597
598#define S_INGHINTENABLE0    14
599#define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
600#define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)
601
602#define S_INGINTCOMPAREIDX    13
603#define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
604#define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)
605
606#define S_INGPCIEBOUNDARY    7
607#define M_INGPCIEBOUNDARY    0x7U
608#define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
609#define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
610
611#define A_SGE_HOST_PAGE_SIZE 0x100c
612
613#define S_HOSTPAGESIZEPF7    28
614#define M_HOSTPAGESIZEPF7    0xfU
615#define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
616#define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
617
618#define S_HOSTPAGESIZEPF6    24
619#define M_HOSTPAGESIZEPF6    0xfU
620#define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
621#define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
622
623#define S_HOSTPAGESIZEPF5    20
624#define M_HOSTPAGESIZEPF5    0xfU
625#define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
626#define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
627
628#define S_HOSTPAGESIZEPF4    16
629#define M_HOSTPAGESIZEPF4    0xfU
630#define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
631#define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
632
633#define S_HOSTPAGESIZEPF3    12
634#define M_HOSTPAGESIZEPF3    0xfU
635#define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
636#define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
637
638#define S_HOSTPAGESIZEPF2    8
639#define M_HOSTPAGESIZEPF2    0xfU
640#define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
641#define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
642
643#define S_HOSTPAGESIZEPF1    4
644#define M_HOSTPAGESIZEPF1    0xfU
645#define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
646#define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
647
648#define S_HOSTPAGESIZEPF0    0
649#define M_HOSTPAGESIZEPF0    0xfU
650#define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
651#define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
652
653#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
654
655#define S_QUEUESPERPAGEPF7    28
656#define M_QUEUESPERPAGEPF7    0xfU
657#define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
658#define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
659
660#define S_QUEUESPERPAGEPF6    24
661#define M_QUEUESPERPAGEPF6    0xfU
662#define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
663#define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
664
665#define S_QUEUESPERPAGEPF5    20
666#define M_QUEUESPERPAGEPF5    0xfU
667#define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
668#define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
669
670#define S_QUEUESPERPAGEPF4    16
671#define M_QUEUESPERPAGEPF4    0xfU
672#define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
673#define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
674
675#define S_QUEUESPERPAGEPF3    12
676#define M_QUEUESPERPAGEPF3    0xfU
677#define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
678#define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
679
680#define S_QUEUESPERPAGEPF2    8
681#define M_QUEUESPERPAGEPF2    0xfU
682#define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
683#define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
684
685#define S_QUEUESPERPAGEPF1    4
686#define M_QUEUESPERPAGEPF1    0xfU
687#define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
688#define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
689
690#define S_QUEUESPERPAGEPF0    0
691#define M_QUEUESPERPAGEPF0    0xfU
692#define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
693#define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
694
695#define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
696
697#define S_QUEUESPERPAGEVFPF7    28
698#define M_QUEUESPERPAGEVFPF7    0xfU
699#define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
700#define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
701
702#define S_QUEUESPERPAGEVFPF6    24
703#define M_QUEUESPERPAGEVFPF6    0xfU
704#define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
705#define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
706
707#define S_QUEUESPERPAGEVFPF5    20
708#define M_QUEUESPERPAGEVFPF5    0xfU
709#define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
710#define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
711
712#define S_QUEUESPERPAGEVFPF4    16
713#define M_QUEUESPERPAGEVFPF4    0xfU
714#define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
715#define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
716
717#define S_QUEUESPERPAGEVFPF3    12
718#define M_QUEUESPERPAGEVFPF3    0xfU
719#define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
720#define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
721
722#define S_QUEUESPERPAGEVFPF2    8
723#define M_QUEUESPERPAGEVFPF2    0xfU
724#define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
725#define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
726
727#define S_QUEUESPERPAGEVFPF1    4
728#define M_QUEUESPERPAGEVFPF1    0xfU
729#define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
730#define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
731
732#define S_QUEUESPERPAGEVFPF0    0
733#define M_QUEUESPERPAGEVFPF0    0xfU
734#define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
735#define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
736
737#define A_SGE_USER_MODE_LIMITS 0x1018
738
739#define S_OPCODE_MIN    24
740#define M_OPCODE_MIN    0xffU
741#define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
742#define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
743
744#define S_OPCODE_MAX    16
745#define M_OPCODE_MAX    0xffU
746#define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
747#define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
748
749#define S_LENGTH_MIN    8
750#define M_LENGTH_MIN    0xffU
751#define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
752#define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
753
754#define S_LENGTH_MAX    0
755#define M_LENGTH_MAX    0xffU
756#define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
757#define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
758
759#define A_SGE_WR_ERROR 0x101c
760
761#define S_WR_ERROR_OPCODE    0
762#define M_WR_ERROR_OPCODE    0xffU
763#define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
764#define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
765
766#define A_SGE_INT_CAUSE1 0x1024
767
768#define S_PERR_FLM_CREDITFIFO    30
769#define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
770#define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)
771
772#define S_PERR_IMSG_HINT_FIFO    29
773#define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
774#define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)
775
776#define S_PERR_MC_PC    28
777#define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
778#define F_PERR_MC_PC    V_PERR_MC_PC(1U)
779
780#define S_PERR_MC_IGR_CTXT    27
781#define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
782#define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)
783
784#define S_PERR_MC_EGR_CTXT    26
785#define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
786#define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)
787
788#define S_PERR_MC_FLM    25
789#define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
790#define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)
791
792#define S_PERR_PC_MCTAG    24
793#define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
794#define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)
795
796#define S_PERR_PC_CHPI_RSP1    23
797#define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
798#define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)
799
800#define S_PERR_PC_CHPI_RSP0    22
801#define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
802#define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)
803
804#define S_PERR_DBP_PC_RSP_FIFO3    21
805#define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
806#define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)
807
808#define S_PERR_DBP_PC_RSP_FIFO2    20
809#define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
810#define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)
811
812#define S_PERR_DBP_PC_RSP_FIFO1    19
813#define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
814#define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)
815
816#define S_PERR_DBP_PC_RSP_FIFO0    18
817#define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
818#define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)
819
820#define S_PERR_DMARBT    17
821#define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
822#define F_PERR_DMARBT    V_PERR_DMARBT(1U)
823
824#define S_PERR_FLM_DBPFIFO    16
825#define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
826#define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)
827
828#define S_PERR_FLM_MCREQ_FIFO    15
829#define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
830#define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)
831
832#define S_PERR_FLM_HINTFIFO    14
833#define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
834#define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)
835
836#define S_PERR_ALIGN_CTL_FIFO3    13
837#define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
838#define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)
839
840#define S_PERR_ALIGN_CTL_FIFO2    12
841#define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
842#define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)
843
844#define S_PERR_ALIGN_CTL_FIFO1    11
845#define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
846#define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)
847
848#define S_PERR_ALIGN_CTL_FIFO0    10
849#define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
850#define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)
851
852#define S_PERR_EDMA_FIFO3    9
853#define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
854#define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)
855
856#define S_PERR_EDMA_FIFO2    8
857#define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
858#define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)
859
860#define S_PERR_EDMA_FIFO1    7
861#define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
862#define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)
863
864#define S_PERR_EDMA_FIFO0    6
865#define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
866#define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)
867
868#define S_PERR_PD_FIFO3    5
869#define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
870#define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)
871
872#define S_PERR_PD_FIFO2    4
873#define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
874#define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)
875
876#define S_PERR_PD_FIFO1    3
877#define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
878#define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)
879
880#define S_PERR_PD_FIFO0    2
881#define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
882#define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)
883
884#define S_PERR_ING_CTXT_MIFRSP    1
885#define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
886#define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)
887
888#define S_PERR_EGR_CTXT_MIFRSP    0
889#define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
890#define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)
891
892#define S_PERR_PC_CHPI_RSP2    31
893#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
894#define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
895
896#define S_PERR_PC_RSP    23
897#define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
898#define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)
899
900#define S_PERR_PC_REQ    22
901#define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
902#define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
903
904#define A_SGE_INT_ENABLE1 0x1028
905#define A_SGE_PERR_ENABLE1 0x102c
906#define A_SGE_INT_CAUSE2 0x1030
907
908#define S_PERR_HINT_DELAY_FIFO1    30
909#define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
910#define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)
911
912#define S_PERR_HINT_DELAY_FIFO0    29
913#define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
914#define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)
915
916#define S_PERR_IMSG_PD_FIFO    28
917#define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
918#define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)
919
920#define S_PERR_ULPTX_FIFO1    27
921#define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
922#define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)
923
924#define S_PERR_ULPTX_FIFO0    26
925#define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
926#define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)
927
928#define S_PERR_IDMA2IMSG_FIFO1    25
929#define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
930#define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)
931
932#define S_PERR_IDMA2IMSG_FIFO0    24
933#define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
934#define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)
935
936#define S_PERR_HEADERSPLIT_FIFO1    23
937#define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
938#define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)
939
940#define S_PERR_HEADERSPLIT_FIFO0    22
941#define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
942#define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)
943
944#define S_PERR_ESWITCH_FIFO3    21
945#define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
946#define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)
947
948#define S_PERR_ESWITCH_FIFO2    20
949#define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
950#define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)
951
952#define S_PERR_ESWITCH_FIFO1    19
953#define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
954#define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)
955
956#define S_PERR_ESWITCH_FIFO0    18
957#define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
958#define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)
959
960#define S_PERR_PC_DBP1    17
961#define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
962#define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)
963
964#define S_PERR_PC_DBP0    16
965#define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
966#define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)
967
968#define S_PERR_IMSG_OB_FIFO    15
969#define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
970#define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)
971
972#define S_PERR_CONM_SRAM    14
973#define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
974#define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)
975
976#define S_PERR_PC_MC_RSP    13
977#define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
978#define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)
979
980#define S_PERR_ISW_IDMA0_FIFO    12
981#define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
982#define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)
983
984#define S_PERR_ISW_IDMA1_FIFO    11
985#define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
986#define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)
987
988#define S_PERR_ISW_DBP_FIFO    10
989#define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
990#define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)
991
992#define S_PERR_ISW_GTS_FIFO    9
993#define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
994#define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)
995
996#define S_PERR_ITP_EVR    8
997#define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
998#define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)
999
1000#define S_PERR_FLM_CNTXMEM    7
1001#define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
1002#define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)
1003
1004#define S_PERR_FLM_L1CACHE    6
1005#define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
1006#define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)
1007
1008#define S_PERR_DBP_HINT_FIFO    5
1009#define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
1010#define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)
1011
1012#define S_PERR_DBP_HP_FIFO    4
1013#define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
1014#define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)
1015
1016#define S_PERR_DBP_LP_FIFO    3
1017#define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
1018#define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)
1019
1020#define S_PERR_ING_CTXT_CACHE    2
1021#define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
1022#define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)
1023
1024#define S_PERR_EGR_CTXT_CACHE    1
1025#define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
1026#define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)
1027
1028#define S_PERR_BASE_SIZE    0
1029#define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
1030#define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)
1031
1032#define S_PERR_DBP_HINT_FL_FIFO    24
1033#define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
1034#define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)
1035
1036#define S_PERR_EGR_DBP_TX_COAL    23
1037#define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
1038#define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)
1039
1040#define S_PERR_DBP_FL_FIFO    22
1041#define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
1042#define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)
1043
1044#define S_PERR_PC_DBP2    15
1045#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
1046#define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
1047
1048#define S_DEQ_LL_PERR    21
1049#define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
1050#define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)
1051
1052#define S_ENQ_PERR    20
1053#define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
1054#define F_ENQ_PERR    V_ENQ_PERR(1U)
1055
1056#define S_DEQ_OUT_PERR    19
1057#define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
1058#define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)
1059
1060#define S_BUF_PERR    18
1061#define V_BUF_PERR(x) ((x) << S_BUF_PERR)
1062#define F_BUF_PERR    V_BUF_PERR(1U)
1063
1064#define S_PERR_DB_FIFO    3
1065#define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
1066#define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
1067
1068#define A_SGE_INT_ENABLE2 0x1034
1069#define A_SGE_PERR_ENABLE2 0x1038
1070#define A_SGE_INT_CAUSE3 0x103c
1071
1072#define S_ERR_FLM_DBP    31
1073#define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
1074#define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)
1075
1076#define S_ERR_FLM_IDMA1    30
1077#define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
1078#define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)
1079
1080#define S_ERR_FLM_IDMA0    29
1081#define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
1082#define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)
1083
1084#define S_ERR_FLM_HINT    28
1085#define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
1086#define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)
1087
1088#define S_ERR_PCIE_ERROR3    27
1089#define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
1090#define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)
1091
1092#define S_ERR_PCIE_ERROR2    26
1093#define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
1094#define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)
1095
1096#define S_ERR_PCIE_ERROR1    25
1097#define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
1098#define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)
1099
1100#define S_ERR_PCIE_ERROR0    24
1101#define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
1102#define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)
1103
1104#define S_ERR_TIMER_ABOVE_MAX_QID    23
1105#define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
1106#define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)
1107
1108#define S_ERR_CPL_EXCEED_IQE_SIZE    22
1109#define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
1110#define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)
1111
1112#define S_ERR_INVALID_CIDX_INC    21
1113#define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
1114#define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)
1115
1116#define S_ERR_ITP_TIME_PAUSED    20
1117#define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
1118#define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)
1119
1120#define S_ERR_CPL_OPCODE_0    19
1121#define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
1122#define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)
1123
1124#define S_ERR_DROPPED_DB    18
1125#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
1126#define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)
1127
1128#define S_ERR_DATA_CPL_ON_HIGH_QID1    17
1129#define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1130#define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1131
1132#define S_ERR_DATA_CPL_ON_HIGH_QID0    16
1133#define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1134#define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1135
1136#define S_ERR_BAD_DB_PIDX3    15
1137#define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1138#define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)
1139
1140#define S_ERR_BAD_DB_PIDX2    14
1141#define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1142#define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)
1143
1144#define S_ERR_BAD_DB_PIDX1    13
1145#define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1146#define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)
1147
1148#define S_ERR_BAD_DB_PIDX0    12
1149#define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1150#define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)
1151
1152#define S_ERR_ING_PCIE_CHAN    11
1153#define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1154#define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)
1155
1156#define S_ERR_ING_CTXT_PRIO    10
1157#define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1158#define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)
1159
1160#define S_ERR_EGR_CTXT_PRIO    9
1161#define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1162#define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)
1163
1164#define S_DBFIFO_HP_INT    8
1165#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1166#define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)
1167
1168#define S_DBFIFO_LP_INT    7
1169#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1170#define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)
1171
1172#define S_REG_ADDRESS_ERR    6
1173#define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1174#define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)
1175
1176#define S_INGRESS_SIZE_ERR    5
1177#define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1178#define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)
1179
1180#define S_EGRESS_SIZE_ERR    4
1181#define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1182#define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)
1183
1184#define S_ERR_INV_CTXT3    3
1185#define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1186#define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)
1187
1188#define S_ERR_INV_CTXT2    2
1189#define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1190#define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)
1191
1192#define S_ERR_INV_CTXT1    1
1193#define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1194#define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)
1195
1196#define S_ERR_INV_CTXT0    0
1197#define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1198#define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
1199
1200#define S_DBP_TBUF_FULL    8
1201#define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
1202#define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)
1203
1204#define S_FATAL_WRE_LEN    7
1205#define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
1206#define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)
1207
1208#define A_SGE_INT_ENABLE3 0x1040
1209#define A_SGE_FL_BUFFER_SIZE0 0x1044
1210
1211#define S_SIZE    4
1212#define M_SIZE    0xfffffffU
1213#define V_SIZE(x) ((x) << S_SIZE)
1214#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1215
1216#define S_T6_SIZE    4
1217#define M_T6_SIZE    0xfffffU
1218#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1219#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1220
1221#define A_SGE_FL_BUFFER_SIZE1 0x1048
1222
1223#define S_T6_SIZE    4
1224#define M_T6_SIZE    0xfffffU
1225#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1226#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1227
1228#define A_SGE_FL_BUFFER_SIZE2 0x104c
1229
1230#define S_T6_SIZE    4
1231#define M_T6_SIZE    0xfffffU
1232#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1233#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1234
1235#define A_SGE_FL_BUFFER_SIZE3 0x1050
1236
1237#define S_T6_SIZE    4
1238#define M_T6_SIZE    0xfffffU
1239#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1240#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1241
1242#define A_SGE_FL_BUFFER_SIZE4 0x1054
1243
1244#define S_T6_SIZE    4
1245#define M_T6_SIZE    0xfffffU
1246#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1247#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1248
1249#define A_SGE_FL_BUFFER_SIZE5 0x1058
1250
1251#define S_T6_SIZE    4
1252#define M_T6_SIZE    0xfffffU
1253#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1254#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1255
1256#define A_SGE_FL_BUFFER_SIZE6 0x105c
1257
1258#define S_T6_SIZE    4
1259#define M_T6_SIZE    0xfffffU
1260#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1261#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1262
1263#define A_SGE_FL_BUFFER_SIZE7 0x1060
1264
1265#define S_T6_SIZE    4
1266#define M_T6_SIZE    0xfffffU
1267#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1268#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1269
1270#define A_SGE_FL_BUFFER_SIZE8 0x1064
1271
1272#define S_T6_SIZE    4
1273#define M_T6_SIZE    0xfffffU
1274#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1275#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1276
1277#define A_SGE_FL_BUFFER_SIZE9 0x1068
1278
1279#define S_T6_SIZE    4
1280#define M_T6_SIZE    0xfffffU
1281#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1282#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1283
1284#define A_SGE_FL_BUFFER_SIZE10 0x106c
1285
1286#define S_T6_SIZE    4
1287#define M_T6_SIZE    0xfffffU
1288#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1289#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1290
1291#define A_SGE_FL_BUFFER_SIZE11 0x1070
1292
1293#define S_T6_SIZE    4
1294#define M_T6_SIZE    0xfffffU
1295#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1296#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1297
1298#define A_SGE_FL_BUFFER_SIZE12 0x1074
1299
1300#define S_T6_SIZE    4
1301#define M_T6_SIZE    0xfffffU
1302#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1303#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1304
1305#define A_SGE_FL_BUFFER_SIZE13 0x1078
1306
1307#define S_T6_SIZE    4
1308#define M_T6_SIZE    0xfffffU
1309#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1310#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1311
1312#define A_SGE_FL_BUFFER_SIZE14 0x107c
1313
1314#define S_T6_SIZE    4
1315#define M_T6_SIZE    0xfffffU
1316#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1317#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1318
1319#define A_SGE_FL_BUFFER_SIZE15 0x1080
1320
1321#define S_T6_SIZE    4
1322#define M_T6_SIZE    0xfffffU
1323#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1324#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1325
1326#define A_SGE_DBQ_CTXT_BADDR 0x1084
1327
1328#define S_BASEADDR    3
1329#define M_BASEADDR    0x1fffffffU
1330#define V_BASEADDR(x) ((x) << S_BASEADDR)
1331#define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1332
1333#define A_SGE_IMSG_CTXT_BADDR 0x1088
1334#define A_SGE_FLM_CACHE_BADDR 0x108c
1335#define A_SGE_FLM_CFG 0x1090
1336
1337#define S_OPMODE    26
1338#define M_OPMODE    0x3fU
1339#define V_OPMODE(x) ((x) << S_OPMODE)
1340#define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1341
1342#define S_NULLPTR    20
1343#define M_NULLPTR    0xfU
1344#define V_NULLPTR(x) ((x) << S_NULLPTR)
1345#define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
1346
1347#define S_NULLPTREN    19
1348#define V_NULLPTREN(x) ((x) << S_NULLPTREN)
1349#define F_NULLPTREN    V_NULLPTREN(1U)
1350
1351#define S_NOHDR    18
1352#define V_NOHDR(x) ((x) << S_NOHDR)
1353#define F_NOHDR    V_NOHDR(1U)
1354
1355#define S_CACHEPTRCNT    16
1356#define M_CACHEPTRCNT    0x3U
1357#define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1358#define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1359
1360#define S_EDRAMPTRCNT    14
1361#define M_EDRAMPTRCNT    0x3U
1362#define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1363#define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1364
1365#define S_HDRSTARTFLQ    11
1366#define M_HDRSTARTFLQ    0x7U
1367#define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1368#define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1369
1370#define S_FETCHTHRESH    6
1371#define M_FETCHTHRESH    0x1fU
1372#define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1373#define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1374
1375#define S_CREDITCNT    4
1376#define M_CREDITCNT    0x3U
1377#define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1378#define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1379
1380#define S_CREDITCNTPACKING    2
1381#define M_CREDITCNTPACKING    0x3U
1382#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1383#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1384
1385#define S_NOEDRAM    0
1386#define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1387#define F_NOEDRAM    V_NOEDRAM(1U)
1388
1389#define A_SGE_CONM_CTRL 0x1094
1390
1391#define S_EGRTHRESHOLD    8
1392#define M_EGRTHRESHOLD    0x3fU
1393#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1394#define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1395
1396#define S_EGRTHRESHOLDPACKING    14
1397#define M_EGRTHRESHOLDPACKING    0x3fU
1398#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1399#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1400
1401#define S_T6_EGRTHRESHOLDPACKING    16
1402#define M_T6_EGRTHRESHOLDPACKING    0xffU
1403#define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
1404#define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
1405
1406#define S_T6_EGRTHRESHOLD    8
1407#define M_T6_EGRTHRESHOLD    0xffU
1408#define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
1409#define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
1410
1411#define S_INGTHRESHOLD    2
1412#define M_INGTHRESHOLD    0x3fU
1413#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1414#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1415
1416#define A_SGE_TIMESTAMP_LO 0x1098
1417#define A_SGE_TIMESTAMP_HI 0x109c
1418
1419#define S_TSOP    28
1420#define M_TSOP    0x3U
1421#define V_TSOP(x) ((x) << S_TSOP)
1422#define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1423
1424#define S_TSVAL    0
1425#define M_TSVAL    0xfffffffU
1426#define V_TSVAL(x) ((x) << S_TSVAL)
1427#define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1428
1429#define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1430
1431#define S_THRESHOLD_0    24
1432#define M_THRESHOLD_0    0x3fU
1433#define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1434#define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1435
1436#define S_THRESHOLD_1    16
1437#define M_THRESHOLD_1    0x3fU
1438#define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1439#define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1440
1441#define S_THRESHOLD_2    8
1442#define M_THRESHOLD_2    0x3fU
1443#define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1444#define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1445
1446#define S_THRESHOLD_3    0
1447#define M_THRESHOLD_3    0x3fU
1448#define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1449#define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1450
1451#define A_SGE_DBFIFO_STATUS 0x10a4
1452
1453#define S_HP_INT_THRESH    28
1454#define M_HP_INT_THRESH    0xfU
1455#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1456#define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1457
1458#define S_HP_COUNT    16
1459#define M_HP_COUNT    0x7ffU
1460#define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1461#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1462
1463#define S_LP_INT_THRESH    12
1464#define M_LP_INT_THRESH    0xfU
1465#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1466#define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1467
1468#define S_LP_COUNT    0
1469#define M_LP_COUNT    0x7ffU
1470#define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1471#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1472
1473#define S_BAR2VALID    31
1474#define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1475#define F_BAR2VALID    V_BAR2VALID(1U)
1476
1477#define S_BAR2FULL    30
1478#define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1479#define F_BAR2FULL    V_BAR2FULL(1U)
1480
1481#define S_LP_INT_THRESH_T5    18
1482#define M_LP_INT_THRESH_T5    0xfffU
1483#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1484#define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1485
1486#define S_LP_COUNT_T5    0
1487#define M_LP_COUNT_T5    0x3ffffU
1488#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1489#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1490
1491#define S_VFIFO_CNT    15
1492#define M_VFIFO_CNT    0x1ffffU
1493#define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
1494#define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
1495
1496#define S_COAL_CTL_FIFO_CNT    8
1497#define M_COAL_CTL_FIFO_CNT    0x3fU
1498#define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
1499#define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
1500
1501#define S_MERGE_FIFO_CNT    0
1502#define M_MERGE_FIFO_CNT    0x3fU
1503#define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
1504#define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
1505
1506#define A_SGE_DOORBELL_CONTROL 0x10a8
1507
1508#define S_HINTDEPTHCTL    27
1509#define M_HINTDEPTHCTL    0x1fU
1510#define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1511#define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1512
1513#define S_NOCOALESCE    26
1514#define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1515#define F_NOCOALESCE    V_NOCOALESCE(1U)
1516
1517#define S_HP_WEIGHT    24
1518#define M_HP_WEIGHT    0x3U
1519#define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1520#define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1521
1522#define S_HP_DISABLE    23
1523#define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1524#define F_HP_DISABLE    V_HP_DISABLE(1U)
1525
1526#define S_FORCEUSERDBTOLP    22
1527#define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1528#define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)
1529
1530#define S_FORCEVFPF0DBTOLP    21
1531#define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1532#define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)
1533
1534#define S_FORCEVFPF1DBTOLP    20
1535#define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1536#define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)
1537
1538#define S_FORCEVFPF2DBTOLP    19
1539#define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1540#define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)
1541
1542#define S_FORCEVFPF3DBTOLP    18
1543#define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1544#define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)
1545
1546#define S_FORCEVFPF4DBTOLP    17
1547#define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1548#define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)
1549
1550#define S_FORCEVFPF5DBTOLP    16
1551#define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1552#define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)
1553
1554#define S_FORCEVFPF6DBTOLP    15
1555#define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1556#define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)
1557
1558#define S_FORCEVFPF7DBTOLP    14
1559#define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1560#define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)
1561
1562#define S_ENABLE_DROP    13
1563#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1564#define F_ENABLE_DROP    V_ENABLE_DROP(1U)
1565
1566#define S_DROP_TIMEOUT    1
1567#define M_DROP_TIMEOUT    0xfffU
1568#define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1569#define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1570
1571#define S_DROPPED_DB    0
1572#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1573#define F_DROPPED_DB    V_DROPPED_DB(1U)
1574
1575#define S_T6_DROP_TIMEOUT    7
1576#define M_T6_DROP_TIMEOUT    0x3fU
1577#define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
1578#define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
1579
1580#define S_INVONDBSYNC    6
1581#define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
1582#define F_INVONDBSYNC    V_INVONDBSYNC(1U)
1583
1584#define S_INVONGTSSYNC    5
1585#define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
1586#define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)
1587
1588#define S_DB_DBG_EN    4
1589#define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
1590#define F_DB_DBG_EN    V_DB_DBG_EN(1U)
1591
1592#define S_GTS_DBG_TIMER_REG    1
1593#define M_GTS_DBG_TIMER_REG    0x7U
1594#define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
1595#define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
1596
1597#define S_GTS_DBG_EN    0
1598#define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
1599#define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)
1600
1601#define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1602
1603#define S_BAR2THROTTLECOUNT    16
1604#define M_BAR2THROTTLECOUNT    0xffU
1605#define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1606#define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1607
1608#define S_CLRCOALESCEDISABLE    15
1609#define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1610#define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)
1611
1612#define S_OPENBAR2GATEONCE    14
1613#define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1614#define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)
1615
1616#define S_FORCEOPENBAR2GATE    13
1617#define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1618#define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)
1619
1620#define A_SGE_ITP_CONTROL 0x10b4
1621
1622#define S_TSCALE    28
1623#define M_TSCALE    0xfU
1624#define V_TSCALE(x) ((x) << S_TSCALE)
1625#define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
1626
1627#define S_CRITICAL_TIME    10
1628#define M_CRITICAL_TIME    0x7fffU
1629#define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1630#define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1631
1632#define S_LL_EMPTY    4
1633#define M_LL_EMPTY    0x3fU
1634#define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1635#define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1636
1637#define S_LL_READ_WAIT_DISABLE    0
1638#define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1639#define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
1640
1641#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1642
1643#define S_TIMERVALUE0    16
1644#define M_TIMERVALUE0    0xffffU
1645#define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1646#define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1647
1648#define S_TIMERVALUE1    0
1649#define M_TIMERVALUE1    0xffffU
1650#define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1651#define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1652
1653#define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1654
1655#define S_TIMERVALUE2    16
1656#define M_TIMERVALUE2    0xffffU
1657#define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1658#define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1659
1660#define S_TIMERVALUE3    0
1661#define M_TIMERVALUE3    0xffffU
1662#define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1663#define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1664
1665#define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1666
1667#define S_TIMERVALUE4    16
1668#define M_TIMERVALUE4    0xffffU
1669#define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1670#define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1671
1672#define S_TIMERVALUE5    0
1673#define M_TIMERVALUE5    0xffffU
1674#define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1675#define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1676
1677#define A_SGE_GK_CONTROL 0x10c4
1678
1679#define S_EN_FLM_FIFTH    29
1680#define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
1681#define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)
1682
1683#define S_FL_PROG_THRESH    20
1684#define M_FL_PROG_THRESH    0x1ffU
1685#define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
1686#define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
1687
1688#define S_COAL_ALL_THREAD    19
1689#define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
1690#define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)
1691
1692#define S_EN_PSHB    18
1693#define V_EN_PSHB(x) ((x) << S_EN_PSHB)
1694#define F_EN_PSHB    V_EN_PSHB(1U)
1695
1696#define S_EN_DB_FIFTH    17
1697#define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
1698#define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)
1699
1700#define S_DB_PROG_THRESH    8
1701#define M_DB_PROG_THRESH    0x1ffU
1702#define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
1703#define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
1704
1705#define S_100NS_TIMER    0
1706#define M_100NS_TIMER    0xffU
1707#define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
1708#define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
1709
1710#define A_SGE_GK_CONTROL2 0x10c8
1711
1712#define S_DBQ_TIMER_TICK    16
1713#define M_DBQ_TIMER_TICK    0xffffU
1714#define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
1715#define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
1716
1717#define S_FL_MERGE_CNT_THRESH    8
1718#define M_FL_MERGE_CNT_THRESH    0xfU
1719#define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
1720#define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
1721
1722#define S_MERGE_CNT_THRESH    0
1723#define M_MERGE_CNT_THRESH    0x3fU
1724#define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
1725#define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
1726
1727#define A_SGE_DEBUG_INDEX 0x10cc
1728#define A_SGE_DEBUG_DATA_HIGH 0x10d0
1729#define A_SGE_DEBUG_DATA_LOW 0x10d4
1730#define A_SGE_INT_CAUSE4 0x10dc
1731
1732#define S_ERR_BAD_UPFL_INC_CREDIT3    8
1733#define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1734#define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1735
1736#define S_ERR_BAD_UPFL_INC_CREDIT2    7
1737#define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1738#define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1739
1740#define S_ERR_BAD_UPFL_INC_CREDIT1    6
1741#define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1742#define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1743
1744#define S_ERR_BAD_UPFL_INC_CREDIT0    5
1745#define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1746#define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1747
1748#define S_ERR_PHYSADDR_LEN0_IDMA1    4
1749#define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
1750#define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)
1751
1752#define S_ERR_PHYSADDR_LEN0_IDMA0    3
1753#define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
1754#define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)
1755
1756#define S_ERR_FLM_INVALID_PKT_DROP1    2
1757#define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
1758#define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)
1759
1760#define S_ERR_FLM_INVALID_PKT_DROP0    1
1761#define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
1762#define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)
1763
1764#define S_ERR_UNEXPECTED_TIMER    0
1765#define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
1766#define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)
1767
1768#define S_BAR2_EGRESS_LEN_OR_ADDR_ERR    29
1769#define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
1770#define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
1771
1772#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1    28
1773#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
1774#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
1775
1776#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0    27
1777#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
1778#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
1779
1780#define S_ERR_WR_LEN_TOO_LARGE3    26
1781#define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
1782#define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)
1783
1784#define S_ERR_WR_LEN_TOO_LARGE2    25
1785#define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
1786#define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)
1787
1788#define S_ERR_WR_LEN_TOO_LARGE1    24
1789#define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
1790#define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)
1791
1792#define S_ERR_WR_LEN_TOO_LARGE0    23
1793#define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
1794#define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)
1795
1796#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3    22
1797#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
1798#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
1799
1800#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2    21
1801#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
1802#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
1803
1804#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1    20
1805#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
1806#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
1807
1808#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0    19
1809#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
1810#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
1811
1812#define S_COAL_WITH_HP_DISABLE_ERR    18
1813#define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
1814#define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)
1815
1816#define S_BAR2_EGRESS_COAL0_ERR    17
1817#define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
1818#define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)
1819
1820#define S_BAR2_EGRESS_SIZE_ERR    16
1821#define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
1822#define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)
1823
1824#define S_FLM_PC_RSP_ERR    15
1825#define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
1826#define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)
1827
1828#define S_DBFIFO_HP_INT_LOW    14
1829#define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
1830#define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)
1831
1832#define S_DBFIFO_LP_INT_LOW    13
1833#define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
1834#define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)
1835
1836#define S_DBFIFO_FL_INT_LOW    12
1837#define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
1838#define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)
1839
1840#define S_DBFIFO_FL_INT    11
1841#define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
1842#define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)
1843
1844#define S_ERR_RX_CPL_PACKET_SIZE1    10
1845#define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
1846#define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)
1847
1848#define S_ERR_RX_CPL_PACKET_SIZE0    9
1849#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
1850#define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
1851
1852#define S_ERR_ISHIFT_UR1    31
1853#define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
1854#define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)
1855
1856#define S_ERR_ISHIFT_UR0    30
1857#define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
1858#define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)
1859
1860#define S_ERR_TH3_MAX_FETCH    14
1861#define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
1862#define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)
1863
1864#define S_ERR_TH2_MAX_FETCH    13
1865#define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
1866#define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)
1867
1868#define S_ERR_TH1_MAX_FETCH    12
1869#define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
1870#define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)
1871
1872#define S_ERR_TH0_MAX_FETCH    11
1873#define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
1874#define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)
1875
1876#define A_SGE_INT_ENABLE4 0x10e0
1877#define A_SGE_STAT_TOTAL 0x10e4
1878#define A_SGE_STAT_MATCH 0x10e8
1879#define A_SGE_STAT_CFG 0x10ec
1880
1881#define S_STATMODE    2
1882#define M_STATMODE    0x3U
1883#define V_STATMODE(x) ((x) << S_STATMODE)
1884#define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
1885
1886#define S_STATSOURCE    0
1887#define M_STATSOURCE    0x3U
1888#define V_STATSOURCE(x) ((x) << S_STATSOURCE)
1889#define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
1890
1891#define S_STATSOURCE_T5    9
1892#define M_STATSOURCE_T5    0xfU
1893#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
1894#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
1895
1896#define S_ITPOPMODE    8
1897#define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
1898#define F_ITPOPMODE    V_ITPOPMODE(1U)
1899
1900#define S_EGRCTXTOPMODE    6
1901#define M_EGRCTXTOPMODE    0x3U
1902#define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
1903#define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
1904
1905#define S_INGCTXTOPMODE    4
1906#define M_INGCTXTOPMODE    0x3U
1907#define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
1908#define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
1909
1910#define S_T6_STATMODE    0
1911#define M_T6_STATMODE    0xfU
1912#define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
1913#define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
1914
1915#define A_SGE_HINT_CFG 0x10f0
1916
1917#define S_UPCUTOFFTHRESHLP    12
1918#define M_UPCUTOFFTHRESHLP    0x7ffU
1919#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
1920#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
1921
1922#define S_HINTSALLOWEDNOHDR    6
1923#define M_HINTSALLOWEDNOHDR    0x3fU
1924#define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
1925#define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
1926
1927#define S_HINTSALLOWEDHDR    0
1928#define M_HINTSALLOWEDHDR    0x3fU
1929#define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
1930#define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
1931
1932#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
1933#define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
1934#define A_SGE_ERROR_STATS 0x1100
1935
1936#define S_UNCAPTURED_ERROR    18
1937#define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
1938#define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)
1939
1940#define S_ERROR_QID_VALID    17
1941#define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
1942#define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)
1943
1944#define S_ERROR_QID    0
1945#define M_ERROR_QID    0x1ffffU
1946#define V_ERROR_QID(x) ((x) << S_ERROR_QID)
1947#define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
1948
1949#define S_CAUSE_REGISTER    24
1950#define M_CAUSE_REGISTER    0x7U
1951#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
1952#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
1953
1954#define S_CAUSE_BIT    19
1955#define M_CAUSE_BIT    0x1fU
1956#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
1957#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
1958
1959#define A_SGE_IDMA0_DROP_CNT 0x1104
1960#define A_SGE_IDMA1_DROP_CNT 0x1108
1961#define A_SGE_INT_CAUSE5 0x110c
1962
1963#define S_ERR_T_RXCRC    31
1964#define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
1965#define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)
1966
1967#define S_PERR_MC_RSPDATA    30
1968#define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
1969#define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)
1970
1971#define S_PERR_PC_RSPDATA    29
1972#define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
1973#define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)
1974
1975#define S_PERR_PD_RDRSPDATA    28
1976#define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
1977#define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)
1978
1979#define S_PERR_U_RXDATA    27
1980#define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
1981#define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)
1982
1983#define S_PERR_UD_RXDATA    26
1984#define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
1985#define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)
1986
1987#define S_PERR_UP_DATA    25
1988#define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
1989#define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)
1990
1991#define S_PERR_CIM2SGE_RXDATA    24
1992#define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
1993#define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)
1994
1995#define S_PERR_HINT_DELAY_FIFO1_T5    23
1996#define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
1997#define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)
1998
1999#define S_PERR_HINT_DELAY_FIFO0_T5    22
2000#define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
2001#define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)
2002
2003#define S_PERR_IMSG_PD_FIFO_T5    21
2004#define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
2005#define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)
2006
2007#define S_PERR_ULPTX_FIFO1_T5    20
2008#define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
2009#define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)
2010
2011#define S_PERR_ULPTX_FIFO0_T5    19
2012#define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
2013#define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)
2014
2015#define S_PERR_IDMA2IMSG_FIFO1_T5    18
2016#define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
2017#define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)
2018
2019#define S_PERR_IDMA2IMSG_FIFO0_T5    17
2020#define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
2021#define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)
2022
2023#define S_PERR_POINTER_DATA_FIFO0    16
2024#define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
2025#define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)
2026
2027#define S_PERR_POINTER_DATA_FIFO1    15
2028#define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
2029#define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)
2030
2031#define S_PERR_POINTER_HDR_FIFO0    14
2032#define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
2033#define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)
2034
2035#define S_PERR_POINTER_HDR_FIFO1    13
2036#define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
2037#define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)
2038
2039#define S_PERR_PAYLOAD_FIFO0    12
2040#define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
2041#define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)
2042
2043#define S_PERR_PAYLOAD_FIFO1    11
2044#define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
2045#define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)
2046
2047#define S_PERR_EDMA_INPUT_FIFO3    10
2048#define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
2049#define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)
2050
2051#define S_PERR_EDMA_INPUT_FIFO2    9
2052#define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
2053#define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)
2054
2055#define S_PERR_EDMA_INPUT_FIFO1    8
2056#define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
2057#define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)
2058
2059#define S_PERR_EDMA_INPUT_FIFO0    7
2060#define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
2061#define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)
2062
2063#define S_PERR_MGT_BAR2_FIFO    6
2064#define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
2065#define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)
2066
2067#define S_PERR_HEADERSPLIT_FIFO1_T5    5
2068#define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
2069#define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)
2070
2071#define S_PERR_HEADERSPLIT_FIFO0_T5    4
2072#define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
2073#define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)
2074
2075#define S_PERR_CIM_FIFO1    3
2076#define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
2077#define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)
2078
2079#define S_PERR_CIM_FIFO0    2
2080#define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
2081#define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)
2082
2083#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
2084#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
2085#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
2086
2087#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
2088#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
2089#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
2090
2091#define A_SGE_INT_ENABLE5 0x1110
2092#define A_SGE_PERR_ENABLE5 0x1114
2093#define A_SGE_DBFIFO_STATUS2 0x1118
2094
2095#define S_FL_INT_THRESH    24
2096#define M_FL_INT_THRESH    0xfU
2097#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
2098#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
2099
2100#define S_FL_COUNT    14
2101#define M_FL_COUNT    0x3ffU
2102#define V_FL_COUNT(x) ((x) << S_FL_COUNT)
2103#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
2104
2105#define S_HP_INT_THRESH_T5    10
2106#define M_HP_INT_THRESH_T5    0xfU
2107#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
2108#define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
2109
2110#define S_HP_COUNT_T5    0
2111#define M_HP_COUNT_T5    0x3ffU
2112#define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
2113#define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
2114
2115#define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2116
2117#define S_FETCHBURSTMAX0    16
2118#define M_FETCHBURSTMAX0    0x3ffU
2119#define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
2120#define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
2121
2122#define S_FETCHBURSTMAX1    0
2123#define M_FETCHBURSTMAX1    0x3ffU
2124#define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
2125#define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
2126
2127#define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2128
2129#define S_FETCHBURSTMAX2    16
2130#define M_FETCHBURSTMAX2    0x3ffU
2131#define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
2132#define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
2133
2134#define S_FETCHBURSTMAX3    0
2135#define M_FETCHBURSTMAX3    0x3ffU
2136#define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
2137#define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
2138
2139#define A_SGE_CONTROL2 0x1124
2140
2141#define S_INGPACKBOUNDARY    16
2142#define M_INGPACKBOUNDARY    0x7U
2143#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
2144#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
2145
2146#define S_VFIFO_ENABLE    10
2147#define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
2148#define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)
2149
2150#define S_FLM_RESCHEDULE_MODE    9
2151#define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
2152#define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)
2153
2154#define S_HINTDEPTHCTLFL    4
2155#define M_HINTDEPTHCTLFL    0x1fU
2156#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
2157#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
2158
2159#define S_FORCE_ORDERING    3
2160#define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
2161#define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)
2162
2163#define S_TX_COALESCE_SIZE    2
2164#define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
2165#define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)
2166
2167#define S_COAL_STRICT_CIM_PRI    1
2168#define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
2169#define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)
2170
2171#define S_TX_COALESCE_PRI    0
2172#define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
2173#define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
2174
2175#define S_UPFLCUTOFFDIS    21
2176#define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
2177#define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)
2178
2179#define S_RXCPLSIZEAUTOCORRECT    20
2180#define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
2181#define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)
2182
2183#define S_IDMAARBROUNDROBIN    19
2184#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
2185#define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
2186
2187#define S_CGEN_EGRESS_CONTEXT    15
2188#define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
2189#define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)
2190
2191#define S_CGEN_INGRESS_CONTEXT    14
2192#define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
2193#define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)
2194
2195#define S_CGEN_IDMA    13
2196#define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
2197#define F_CGEN_IDMA    V_CGEN_IDMA(1U)
2198
2199#define S_CGEN_DBP    12
2200#define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
2201#define F_CGEN_DBP    V_CGEN_DBP(1U)
2202
2203#define S_CGEN_EDMA    11
2204#define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
2205#define F_CGEN_EDMA    V_CGEN_EDMA(1U)
2206
2207#define A_SGE_INT_CAUSE6 0x1128
2208
2209#define S_ERR_DB_SYNC    21
2210#define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
2211#define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)
2212
2213#define S_ERR_GTS_SYNC    20
2214#define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
2215#define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)
2216
2217#define S_FATAL_LARGE_COAL    19
2218#define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
2219#define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)
2220
2221#define S_PL_BAR2_FRM_ERR    18
2222#define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
2223#define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)
2224
2225#define S_SILENT_DROP_TX_COAL    17
2226#define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
2227#define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)
2228
2229#define S_ERR_INV_CTXT4    16
2230#define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
2231#define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)
2232
2233#define S_ERR_BAD_DB_PIDX4    15
2234#define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
2235#define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)
2236
2237#define S_ERR_BAD_UPFL_INC_CREDIT4    14
2238#define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
2239#define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)
2240
2241#define S_ERR_PC_RSP_LEN3    11
2242#define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
2243#define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)
2244
2245#define S_ERR_PC_RSP_LEN2    10
2246#define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
2247#define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)
2248
2249#define S_ERR_PC_RSP_LEN1    9
2250#define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
2251#define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)
2252
2253#define S_ERR_PC_RSP_LEN0    8
2254#define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
2255#define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)
2256
2257#define S_FATAL_ENQ2LL_VLD    7
2258#define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
2259#define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)
2260
2261#define S_FATAL_LL_EMPTY    6
2262#define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
2263#define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)
2264
2265#define S_FATAL_OFF_WDENQ    5
2266#define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
2267#define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)
2268
2269#define S_FATAL_DEQ_DRDY    3
2270#define M_FATAL_DEQ_DRDY    0x3U
2271#define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
2272#define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
2273
2274#define S_FATAL_OUTP_DRDY    1
2275#define M_FATAL_OUTP_DRDY    0x3U
2276#define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
2277#define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
2278
2279#define S_FATAL_DEQ    0
2280#define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
2281#define F_FATAL_DEQ    V_FATAL_DEQ(1U)
2282
2283#define A_SGE_INT_ENABLE6 0x112c
2284
2285#define S_FATAL_TAG_MISMATCH    13
2286#define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
2287#define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)
2288
2289#define S_FATAL_ENQ_CTL_RDY    12
2290#define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
2291#define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)
2292
2293#define A_SGE_DBVFIFO_BADDR 0x1138
2294#define A_SGE_DBVFIFO_SIZE 0x113c
2295
2296#define S_DBVFIFO_SIZE    6
2297#define M_DBVFIFO_SIZE    0xfffU
2298#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2299#define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2300
2301#define S_T6_DBVFIFO_SIZE    0
2302#define M_T6_DBVFIFO_SIZE    0x1fffU
2303#define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
2304#define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
2305
2306#define A_SGE_DBFIFO_STATUS3 0x1140
2307
2308#define S_LP_PTRS_EQUAL    21
2309#define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2310#define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)
2311
2312#define S_LP_SNAPHOT    20
2313#define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2314#define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)
2315
2316#define S_FL_INT_THRESH_LOW    16
2317#define M_FL_INT_THRESH_LOW    0xfU
2318#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2319#define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2320
2321#define S_HP_INT_THRESH_LOW    12
2322#define M_HP_INT_THRESH_LOW    0xfU
2323#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2324#define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2325
2326#define S_LP_INT_THRESH_LOW    0
2327#define M_LP_INT_THRESH_LOW    0xfffU
2328#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2329#define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2330
2331#define A_SGE_CHANGESET 0x1144
2332#define A_SGE_PC_RSP_ERROR 0x1148
2333#define A_SGE_TBUF_CONTROL 0x114c
2334
2335#define S_DBPTBUFRSV1    9
2336#define M_DBPTBUFRSV1    0x1ffU
2337#define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
2338#define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
2339
2340#define S_DBPTBUFRSV0    0
2341#define M_DBPTBUFRSV0    0x1ffU
2342#define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
2343#define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
2344
2345#define A_SGE_PC0_REQ_BIST_CMD 0x1180
2346#define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2347#define A_SGE_PC1_REQ_BIST_CMD 0x1190
2348#define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2349#define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2350#define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2351#define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2352#define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2353#define A_SGE_DBQ_TIMER_DBG 0x11c4
2354
2355#define S_DBQ_TIMER_CMD    31
2356#define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD)
2357#define F_DBQ_TIMER_CMD    V_DBQ_TIMER_CMD(1U)
2358
2359#define S_DBQ_TIMER_INDEX    24
2360#define M_DBQ_TIMER_INDEX    0x3fU
2361#define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX)
2362#define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX)
2363
2364#define S_DBQ_TIMER_QCNT    0
2365#define M_DBQ_TIMER_QCNT    0x1ffffU
2366#define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT)
2367#define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT)
2368
2369#define A_SGE_CTXT_CMD 0x11fc
2370
2371#define S_BUSY    31
2372#define V_BUSY(x) ((x) << S_BUSY)
2373#define F_BUSY    V_BUSY(1U)
2374
2375#define S_CTXTOP    28
2376#define M_CTXTOP    0x3U
2377#define V_CTXTOP(x) ((x) << S_CTXTOP)
2378#define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
2379
2380#define S_CTXTTYPE    24
2381#define M_CTXTTYPE    0x3U
2382#define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
2383#define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
2384
2385#define S_CTXTQID    0
2386#define M_CTXTQID    0x1ffffU
2387#define V_CTXTQID(x) ((x) << S_CTXTQID)
2388#define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
2389
2390#define A_SGE_CTXT_DATA0 0x1200
2391#define A_SGE_CTXT_DATA1 0x1204
2392#define A_SGE_CTXT_DATA2 0x1208
2393#define A_SGE_CTXT_DATA3 0x120c
2394#define A_SGE_CTXT_DATA4 0x1210
2395#define A_SGE_CTXT_DATA5 0x1214
2396#define A_SGE_CTXT_DATA6 0x1218
2397#define A_SGE_CTXT_DATA7 0x121c
2398#define A_SGE_CTXT_MASK0 0x1220
2399#define A_SGE_CTXT_MASK1 0x1224
2400#define A_SGE_CTXT_MASK2 0x1228
2401#define A_SGE_CTXT_MASK3 0x122c
2402#define A_SGE_CTXT_MASK4 0x1230
2403#define A_SGE_CTXT_MASK5 0x1234
2404#define A_SGE_CTXT_MASK6 0x1238
2405#define A_SGE_CTXT_MASK7 0x123c
2406#define A_SGE_QBASE_MAP0 0x1240
2407
2408#define S_EGRESS0_SIZE    24
2409#define M_EGRESS0_SIZE    0x1fU
2410#define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
2411#define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
2412
2413#define S_EGRESS1_SIZE    16
2414#define M_EGRESS1_SIZE    0x1fU
2415#define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
2416#define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
2417
2418#define S_INGRESS0_SIZE    8
2419#define M_INGRESS0_SIZE    0x1fU
2420#define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
2421#define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
2422
2423#define S_INGRESS1_SIZE    0
2424#define M_INGRESS1_SIZE    0x1fU
2425#define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
2426#define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
2427
2428#define A_SGE_QBASE_MAP1 0x1244
2429
2430#define S_EGRESS0_BASE    0
2431#define M_EGRESS0_BASE    0x1ffffU
2432#define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
2433#define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
2434
2435#define A_SGE_QBASE_MAP2 0x1248
2436
2437#define S_EGRESS1_BASE    0
2438#define M_EGRESS1_BASE    0x1ffffU
2439#define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
2440#define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
2441
2442#define A_SGE_QBASE_MAP3 0x124c
2443
2444#define S_INGRESS1_BASE_256VF    16
2445#define M_INGRESS1_BASE_256VF    0xffffU
2446#define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
2447#define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
2448
2449#define S_INGRESS0_BASE    0
2450#define M_INGRESS0_BASE    0xffffU
2451#define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
2452#define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
2453
2454#define A_SGE_QBASE_INDEX 0x1250
2455
2456#define S_QIDX    0
2457#define M_QIDX    0x1ffU
2458#define V_QIDX(x) ((x) << S_QIDX)
2459#define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
2460
2461#define A_SGE_CONM_CTRL2 0x1254
2462
2463#define S_FLMTHRESHPACK    8
2464#define M_FLMTHRESHPACK    0x7fU
2465#define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
2466#define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
2467
2468#define S_FLMTHRESH    0
2469#define M_FLMTHRESH    0x7fU
2470#define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
2471#define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
2472
2473#define A_SGE_DEBUG_CONM 0x1258
2474
2475#define S_MPS_CH_CNG    16
2476#define M_MPS_CH_CNG    0xffffU
2477#define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
2478#define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
2479
2480#define S_TP_CH_CNG    14
2481#define M_TP_CH_CNG    0x3U
2482#define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
2483#define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
2484
2485#define S_ST_CONG    12
2486#define M_ST_CONG    0x3U
2487#define V_ST_CONG(x) ((x) << S_ST_CONG)
2488#define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
2489
2490#define S_LAST_XOFF    10
2491#define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
2492#define F_LAST_XOFF    V_LAST_XOFF(1U)
2493
2494#define S_LAST_QID    0
2495#define M_LAST_QID    0x3ffU
2496#define V_LAST_QID(x) ((x) << S_LAST_QID)
2497#define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
2498
2499#define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
2500
2501#define S_IMSG_GTS_SEL    18
2502#define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
2503#define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)
2504
2505#define S_MGT_SEL    17
2506#define V_MGT_SEL(x) ((x) << S_MGT_SEL)
2507#define F_MGT_SEL    V_MGT_SEL(1U)
2508
2509#define S_DB_GTS_QID    0
2510#define M_DB_GTS_QID    0x1ffffU
2511#define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
2512#define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
2513
2514#define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
2515#define A_SGE_DBG_QUEUE_STAT0 0x1264
2516#define A_SGE_DBG_QUEUE_STAT1 0x1268
2517#define A_SGE_DBG_BAR2_PKT_CNT 0x126c
2518#define A_SGE_DBG_DB_PKT_CNT 0x1270
2519#define A_SGE_DBG_GTS_PKT_CNT 0x1274
2520#define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
2521
2522#define S_CIM_WM    24
2523#define M_CIM_WM    0x3U
2524#define V_CIM_WM(x) ((x) << S_CIM_WM)
2525#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
2526
2527#define S_DEBUG_UP_SOP_CNT    20
2528#define M_DEBUG_UP_SOP_CNT    0xfU
2529#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
2530#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
2531
2532#define S_DEBUG_UP_EOP_CNT    16
2533#define M_DEBUG_UP_EOP_CNT    0xfU
2534#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
2535#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
2536
2537#define S_DEBUG_CIM_SOP1_CNT    12
2538#define M_DEBUG_CIM_SOP1_CNT    0xfU
2539#define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
2540#define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
2541
2542#define S_DEBUG_CIM_EOP1_CNT    8
2543#define M_DEBUG_CIM_EOP1_CNT    0xfU
2544#define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
2545#define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
2546
2547#define S_DEBUG_CIM_SOP0_CNT    4
2548#define M_DEBUG_CIM_SOP0_CNT    0xfU
2549#define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
2550#define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
2551
2552#define S_DEBUG_CIM_EOP0_CNT    0
2553#define M_DEBUG_CIM_EOP0_CNT    0xfU
2554#define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
2555#define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
2556
2557#define S_DEBUG_BAR2_SOP_CNT    28
2558#define M_DEBUG_BAR2_SOP_CNT    0xfU
2559#define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
2560#define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
2561
2562#define S_DEBUG_BAR2_EOP_CNT    24
2563#define M_DEBUG_BAR2_EOP_CNT    0xfU
2564#define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
2565#define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
2566
2567#define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
2568
2569#define S_DEBUG_T_RX_SOP1_CNT    28
2570#define M_DEBUG_T_RX_SOP1_CNT    0xfU
2571#define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
2572#define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
2573
2574#define S_DEBUG_T_RX_EOP1_CNT    24
2575#define M_DEBUG_T_RX_EOP1_CNT    0xfU
2576#define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
2577#define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
2578
2579#define S_DEBUG_T_RX_SOP0_CNT    20
2580#define M_DEBUG_T_RX_SOP0_CNT    0xfU
2581#define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
2582#define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
2583
2584#define S_DEBUG_T_RX_EOP0_CNT    16
2585#define M_DEBUG_T_RX_EOP0_CNT    0xfU
2586#define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
2587#define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
2588
2589#define S_DEBUG_U_RX_SOP1_CNT    12
2590#define M_DEBUG_U_RX_SOP1_CNT    0xfU
2591#define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
2592#define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
2593
2594#define S_DEBUG_U_RX_EOP1_CNT    8
2595#define M_DEBUG_U_RX_EOP1_CNT    0xfU
2596#define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
2597#define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
2598
2599#define S_DEBUG_U_RX_SOP0_CNT    4
2600#define M_DEBUG_U_RX_SOP0_CNT    0xfU
2601#define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
2602#define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
2603
2604#define S_DEBUG_U_RX_EOP0_CNT    0
2605#define M_DEBUG_U_RX_EOP0_CNT    0xfU
2606#define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
2607#define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
2608
2609#define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
2610
2611#define S_DEBUG_UD_RX_SOP3_CNT    28
2612#define M_DEBUG_UD_RX_SOP3_CNT    0xfU
2613#define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
2614#define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
2615
2616#define S_DEBUG_UD_RX_EOP3_CNT    24
2617#define M_DEBUG_UD_RX_EOP3_CNT    0xfU
2618#define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
2619#define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
2620
2621#define S_DEBUG_UD_RX_SOP2_CNT    20
2622#define M_DEBUG_UD_RX_SOP2_CNT    0xfU
2623#define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
2624#define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
2625
2626#define S_DEBUG_UD_RX_EOP2_CNT    16
2627#define M_DEBUG_UD_RX_EOP2_CNT    0xfU
2628#define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
2629#define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
2630
2631#define S_DEBUG_UD_RX_SOP1_CNT    12
2632#define M_DEBUG_UD_RX_SOP1_CNT    0xfU
2633#define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
2634#define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
2635
2636#define S_DEBUG_UD_RX_EOP1_CNT    8
2637#define M_DEBUG_UD_RX_EOP1_CNT    0xfU
2638#define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
2639#define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
2640
2641#define S_DEBUG_UD_RX_SOP0_CNT    4
2642#define M_DEBUG_UD_RX_SOP0_CNT    0xfU
2643#define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
2644#define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
2645
2646#define S_DEBUG_UD_RX_EOP0_CNT    0
2647#define M_DEBUG_UD_RX_EOP0_CNT    0xfU
2648#define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
2649#define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
2650
2651#define S_DBG_TBUF_USED1    9
2652#define M_DBG_TBUF_USED1    0x1ffU
2653#define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
2654#define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
2655
2656#define S_DBG_TBUF_USED0    0
2657#define M_DBG_TBUF_USED0    0x1ffU
2658#define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
2659#define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
2660
2661#define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
2662
2663#define S_DEBUG_U_TX_SOP3_CNT    28
2664#define M_DEBUG_U_TX_SOP3_CNT    0xfU
2665#define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
2666#define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
2667
2668#define S_DEBUG_U_TX_EOP3_CNT    24
2669#define M_DEBUG_U_TX_EOP3_CNT    0xfU
2670#define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
2671#define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
2672
2673#define S_DEBUG_U_TX_SOP2_CNT    20
2674#define M_DEBUG_U_TX_SOP2_CNT    0xfU
2675#define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
2676#define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
2677
2678#define S_DEBUG_U_TX_EOP2_CNT    16
2679#define M_DEBUG_U_TX_EOP2_CNT    0xfU
2680#define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
2681#define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
2682
2683#define S_DEBUG_U_TX_SOP1_CNT    12
2684#define M_DEBUG_U_TX_SOP1_CNT    0xfU
2685#define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
2686#define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
2687
2688#define S_DEBUG_U_TX_EOP1_CNT    8
2689#define M_DEBUG_U_TX_EOP1_CNT    0xfU
2690#define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
2691#define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
2692
2693#define S_DEBUG_U_TX_SOP0_CNT    4
2694#define M_DEBUG_U_TX_SOP0_CNT    0xfU
2695#define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
2696#define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
2697
2698#define S_DEBUG_U_TX_EOP0_CNT    0
2699#define M_DEBUG_U_TX_EOP0_CNT    0xfU
2700#define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
2701#define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
2702
2703#define A_SGE_DEBUG1_DBP_THREAD 0x128c
2704
2705#define S_WR_DEQ_CNT    12
2706#define M_WR_DEQ_CNT    0xfU
2707#define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
2708#define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
2709
2710#define S_WR_ENQ_CNT    8
2711#define M_WR_ENQ_CNT    0xfU
2712#define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
2713#define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
2714
2715#define S_FL_DEQ_CNT    4
2716#define M_FL_DEQ_CNT    0xfU
2717#define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
2718#define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
2719
2720#define S_FL_ENQ_CNT    0
2721#define M_FL_ENQ_CNT    0xfU
2722#define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
2723#define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
2724
2725#define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
2726
2727#define S_DEBUG_PC_RSP_SOP1_CNT    28
2728#define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
2729#define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
2730#define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
2731
2732#define S_DEBUG_PC_RSP_EOP1_CNT    24
2733#define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
2734#define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
2735#define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
2736
2737#define S_DEBUG_PC_RSP_SOP0_CNT    20
2738#define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
2739#define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
2740#define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
2741
2742#define S_DEBUG_PC_RSP_EOP0_CNT    16
2743#define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
2744#define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
2745#define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
2746
2747#define S_DEBUG_PC_REQ_SOP1_CNT    12
2748#define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
2749#define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
2750#define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
2751
2752#define S_DEBUG_PC_REQ_EOP1_CNT    8
2753#define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
2754#define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
2755#define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
2756
2757#define S_DEBUG_PC_REQ_SOP0_CNT    4
2758#define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
2759#define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
2760#define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
2761
2762#define S_DEBUG_PC_REQ_EOP0_CNT    0
2763#define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
2764#define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
2765#define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
2766
2767#define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
2768
2769#define S_DEBUG_PD_RDREQ_SOP3_CNT    28
2770#define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
2771#define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
2772#define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
2773
2774#define S_DEBUG_PD_RDREQ_EOP3_CNT    24
2775#define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
2776#define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
2777#define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
2778
2779#define S_DEBUG_PD_RDREQ_SOP2_CNT    20
2780#define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
2781#define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
2782#define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
2783
2784#define S_DEBUG_PD_RDREQ_EOP2_CNT    16
2785#define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
2786#define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
2787#define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
2788
2789#define S_DEBUG_PD_RDREQ_SOP1_CNT    12
2790#define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
2791#define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
2792#define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
2793
2794#define S_DEBUG_PD_RDREQ_EOP1_CNT    8
2795#define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
2796#define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
2797#define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
2798
2799#define S_DEBUG_PD_RDREQ_SOP0_CNT    4
2800#define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
2801#define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
2802#define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
2803
2804#define S_DEBUG_PD_RDREQ_EOP0_CNT    0
2805#define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
2806#define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
2807#define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
2808
2809#define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
2810
2811#define S_DEBUG_PD_RDRSP_SOP3_CNT    28
2812#define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
2813#define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
2814#define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
2815
2816#define S_DEBUG_PD_RDRSP_EOP3_CNT    24
2817#define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
2818#define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
2819#define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
2820
2821#define S_DEBUG_PD_RDRSP_SOP2_CNT    20
2822#define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
2823#define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
2824#define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
2825
2826#define S_DEBUG_PD_RDRSP_EOP2_CNT    16
2827#define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
2828#define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
2829#define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
2830
2831#define S_DEBUG_PD_RDRSP_SOP1_CNT    12
2832#define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
2833#define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
2834#define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
2835
2836#define S_DEBUG_PD_RDRSP_EOP1_CNT    8
2837#define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
2838#define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
2839#define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
2840
2841#define S_DEBUG_PD_RDRSP_SOP0_CNT    4
2842#define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
2843#define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
2844#define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
2845
2846#define S_DEBUG_PD_RDRSP_EOP0_CNT    0
2847#define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
2848#define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
2849#define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
2850
2851#define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
2852
2853#define S_DEBUG_PD_WRREQ_SOP3_CNT    28
2854#define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
2855#define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
2856#define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
2857
2858#define S_DEBUG_PD_WRREQ_EOP3_CNT    24
2859#define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
2860#define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
2861#define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
2862
2863#define S_DEBUG_PD_WRREQ_SOP2_CNT    20
2864#define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
2865#define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
2866#define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
2867
2868#define S_DEBUG_PD_WRREQ_EOP2_CNT    16
2869#define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
2870#define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
2871#define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
2872
2873#define S_DEBUG_PD_WRREQ_SOP1_CNT    12
2874#define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
2875#define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
2876#define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
2877
2878#define S_DEBUG_PD_WRREQ_EOP1_CNT    8
2879#define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
2880#define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
2881#define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
2882
2883#define S_DEBUG_PD_WRREQ_SOP0_CNT    4
2884#define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
2885#define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
2886#define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
2887
2888#define S_DEBUG_PD_WRREQ_EOP0_CNT    0
2889#define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
2890#define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
2891#define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
2892
2893#define S_DEBUG_PC_RSP_SOP_CNT    28
2894#define M_DEBUG_PC_RSP_SOP_CNT    0xfU
2895#define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
2896#define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
2897
2898#define S_DEBUG_PC_RSP_EOP_CNT    24
2899#define M_DEBUG_PC_RSP_EOP_CNT    0xfU
2900#define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
2901#define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
2902
2903#define S_DEBUG_PC_REQ_SOP_CNT    20
2904#define M_DEBUG_PC_REQ_SOP_CNT    0xfU
2905#define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
2906#define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
2907
2908#define S_DEBUG_PC_REQ_EOP_CNT    16
2909#define M_DEBUG_PC_REQ_EOP_CNT    0xfU
2910#define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
2911#define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
2912
2913#define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
2914
2915#define S_GLOBALENABLE_OFF    29
2916#define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
2917#define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)
2918
2919#define S_DEBUG_CIM2SGE_RXAFULL_D    27
2920#define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
2921#define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
2922#define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
2923
2924#define S_DEBUG_CPLSW_CIM_TXAFULL_D    25
2925#define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
2926#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
2927#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
2928
2929#define S_DEBUG_UP_FULL    24
2930#define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
2931#define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)
2932
2933#define S_DEBUG_M_RD_REQ_OUTSTANDING_PC    23
2934#define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
2935#define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
2936
2937#define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    22
2938#define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
2939#define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
2940
2941#define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    21
2942#define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
2943#define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
2944
2945#define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    20
2946#define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
2947#define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
2948
2949#define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM    19
2950#define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
2951#define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
2952
2953#define S_DEBUG_M_REQVLD    18
2954#define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
2955#define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)
2956
2957#define S_DEBUG_M_REQRDY    17
2958#define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
2959#define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)
2960
2961#define S_DEBUG_M_RSPVLD    16
2962#define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
2963#define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)
2964
2965#define S_DEBUG_PD_WRREQ_INT3_CNT    12
2966#define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
2967#define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
2968#define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
2969
2970#define S_DEBUG_PD_WRREQ_INT2_CNT    8
2971#define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
2972#define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
2973#define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
2974
2975#define S_DEBUG_PD_WRREQ_INT1_CNT    4
2976#define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
2977#define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
2978#define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
2979
2980#define S_DEBUG_PD_WRREQ_INT0_CNT    0
2981#define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
2982#define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
2983#define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
2984
2985#define S_DEBUG_PL_BAR2_REQVLD    31
2986#define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
2987#define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)
2988
2989#define S_DEBUG_PL_BAR2_REQFULL    30
2990#define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
2991#define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)
2992
2993#define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
2994
2995#define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
2996#define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
2997#define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
2998#define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
2999
3000#define S_DEBUG_CPLSW_TP_RX_EOP1_CNT    24
3001#define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
3002#define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3003#define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3004
3005#define S_DEBUG_CPLSW_TP_RX_SOP0_CNT    20
3006#define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
3007#define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3008#define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3009
3010#define S_DEBUG_CPLSW_TP_RX_EOP0_CNT    16
3011#define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
3012#define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3013#define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3014
3015#define S_DEBUG_CPLSW_CIM_SOP1_CNT    12
3016#define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
3017#define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
3018#define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
3019
3020#define S_DEBUG_CPLSW_CIM_EOP1_CNT    8
3021#define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
3022#define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
3023#define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
3024
3025#define S_DEBUG_CPLSW_CIM_SOP0_CNT    4
3026#define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
3027#define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
3028#define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
3029
3030#define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
3031#define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
3032#define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
3033#define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
3034
3035#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3036
3037#define S_DEBUG_T_RXAFULL_D    30
3038#define M_DEBUG_T_RXAFULL_D    0x3U
3039#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
3040#define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
3041
3042#define S_DEBUG_PD_RDRSPAFULL_D    26
3043#define M_DEBUG_PD_RDRSPAFULL_D    0xfU
3044#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
3045#define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
3046
3047#define S_DEBUG_PD_RDREQAFULL_D    22
3048#define M_DEBUG_PD_RDREQAFULL_D    0xfU
3049#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
3050#define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
3051
3052#define S_DEBUG_PD_WRREQAFULL_D    18
3053#define M_DEBUG_PD_WRREQAFULL_D    0xfU
3054#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
3055#define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
3056
3057#define S_DEBUG_PC_RSPAFULL_D    15
3058#define M_DEBUG_PC_RSPAFULL_D    0x7U
3059#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
3060#define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
3061
3062#define S_DEBUG_PC_REQAFULL_D    12
3063#define M_DEBUG_PC_REQAFULL_D    0x7U
3064#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
3065#define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
3066
3067#define S_DEBUG_U_TXAFULL_D    8
3068#define M_DEBUG_U_TXAFULL_D    0xfU
3069#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
3070#define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
3071
3072#define S_DEBUG_UD_RXAFULL_D    4
3073#define M_DEBUG_UD_RXAFULL_D    0xfU
3074#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
3075#define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
3076
3077#define S_DEBUG_U_RXAFULL_D    2
3078#define M_DEBUG_U_RXAFULL_D    0x3U
3079#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
3080#define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
3081
3082#define S_DEBUG_CIM_AFULL_D    0
3083#define M_DEBUG_CIM_AFULL_D    0x3U
3084#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
3085#define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
3086
3087#define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    28
3088#define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
3089#define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3090#define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3091
3092#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    27
3093#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
3094#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
3095
3096#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    26
3097#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
3098#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
3099
3100#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    25
3101#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
3102#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3103
3104#define S_DEBUG_IDMA1_IDMA2IMSG_FULL    24
3105#define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
3106#define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
3107
3108#define S_DEBUG_IDMA1_IDMA2IMSG_EOP    23
3109#define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
3110#define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
3111
3112#define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    22
3113#define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
3114#define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
3115
3116#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    21
3117#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
3118#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
3119
3120#define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    17
3121#define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
3122#define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3123#define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3124
3125#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    16
3126#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
3127#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
3128
3129#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    15
3130#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
3131#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
3132
3133#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    14
3134#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
3135#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3136
3137#define S_DEBUG_IDMA0_IDMA2IMSG_FULL    13
3138#define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
3139#define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
3140
3141#define S_DEBUG_IDMA0_IDMA2IMSG_EOP    12
3142#define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
3143#define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
3144
3145#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    11
3146#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
3147#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
3148
3149#define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    10
3150#define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
3151#define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
3152
3153#define S_T6_DEBUG_T_RXAFULL_D    8
3154#define M_T6_DEBUG_T_RXAFULL_D    0x3U
3155#define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
3156#define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
3157
3158#define S_T6_DEBUG_PD_WRREQAFULL_D    6
3159#define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
3160#define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
3161#define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
3162
3163#define S_T6_DEBUG_PC_RSPAFULL_D    5
3164#define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
3165#define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)
3166
3167#define S_T6_DEBUG_PC_REQAFULL_D    4
3168#define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
3169#define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)
3170
3171#define S_T6_DEBUG_CIM_AFULL_D    0
3172#define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
3173#define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)
3174
3175#define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3176
3177#define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
3178#define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
3179#define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
3180
3181#define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    23
3182#define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
3183#define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
3184
3185#define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    22
3186#define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
3187#define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
3188
3189#define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    21
3190#define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
3191#define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
3192
3193#define S_DEBUG_ST_FLM_IDMA1_CACHE    19
3194#define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
3195#define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
3196#define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
3197
3198#define S_DEBUG_ST_FLM_IDMA1_CTXT    16
3199#define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
3200#define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
3201#define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
3202
3203#define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    8
3204#define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
3205#define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
3206
3207#define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    7
3208#define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
3209#define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
3210
3211#define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    6
3212#define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
3213#define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
3214
3215#define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    5
3216#define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
3217#define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
3218
3219#define S_DEBUG_ST_FLM_IDMA0_CACHE    3
3220#define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
3221#define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
3222#define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
3223
3224#define S_DEBUG_ST_FLM_IDMA0_CTXT    0
3225#define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
3226#define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
3227#define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
3228
3229#define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3230
3231#define S_DEBUG_CPLSW_SOP1_CNT    28
3232#define M_DEBUG_CPLSW_SOP1_CNT    0xfU
3233#define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
3234#define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
3235
3236#define S_DEBUG_CPLSW_EOP1_CNT    24
3237#define M_DEBUG_CPLSW_EOP1_CNT    0xfU
3238#define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
3239#define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
3240
3241#define S_DEBUG_CPLSW_SOP0_CNT    20
3242#define M_DEBUG_CPLSW_SOP0_CNT    0xfU
3243#define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
3244#define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
3245
3246#define S_DEBUG_CPLSW_EOP0_CNT    16
3247#define M_DEBUG_CPLSW_EOP0_CNT    0xfU
3248#define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
3249#define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
3250
3251#define S_DEBUG_PC_RSP_SOP2_CNT    12
3252#define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
3253#define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
3254#define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
3255
3256#define S_DEBUG_PC_RSP_EOP2_CNT    8
3257#define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
3258#define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
3259#define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
3260
3261#define S_DEBUG_PC_REQ_SOP2_CNT    4
3262#define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
3263#define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
3264#define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
3265
3266#define S_DEBUG_PC_REQ_EOP2_CNT    0
3267#define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
3268#define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
3269#define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
3270
3271#define S_DEBUG_IDMA1_ISHIFT_TX_SIZE    8
3272#define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
3273#define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3274#define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3275
3276#define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
3277#define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
3278#define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3279#define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3280
3281#define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3282#define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3283#define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3284#define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3285
3286#define S_DEBUG_ST_IDMA1_FLM_REQ    29
3287#define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
3288#define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
3289#define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
3290
3291#define S_DEBUG_ST_IDMA0_FLM_REQ    26
3292#define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
3293#define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
3294#define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
3295
3296#define S_DEBUG_ST_IMSG_CTXT    23
3297#define M_DEBUG_ST_IMSG_CTXT    0x7U
3298#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
3299#define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
3300
3301#define S_DEBUG_ST_IMSG    18
3302#define M_DEBUG_ST_IMSG    0x1fU
3303#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
3304#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
3305
3306#define S_DEBUG_ST_IDMA1_IALN    16
3307#define M_DEBUG_ST_IDMA1_IALN    0x3U
3308#define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
3309#define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
3310
3311#define S_DEBUG_ST_IDMA1_IDMA_SM    9
3312#define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
3313#define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
3314#define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
3315
3316#define S_DEBUG_ST_IDMA0_IALN    7
3317#define M_DEBUG_ST_IDMA0_IALN    0x3U
3318#define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
3319#define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
3320
3321#define S_DEBUG_ST_IDMA0_IDMA_SM    0
3322#define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
3323#define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
3324#define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
3325
3326#define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
3327
3328#define S_DEBUG_ITP_EMPTY    12
3329#define M_DEBUG_ITP_EMPTY    0x3fU
3330#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
3331#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
3332
3333#define S_DEBUG_ITP_EXPIRED    6
3334#define M_DEBUG_ITP_EXPIRED    0x3fU
3335#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
3336#define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
3337
3338#define S_DEBUG_ITP_PAUSE    5
3339#define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
3340#define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)
3341
3342#define S_DEBUG_ITP_DEL_DONE    4
3343#define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
3344#define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)
3345
3346#define S_DEBUG_ITP_ADD_DONE    3
3347#define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
3348#define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)
3349
3350#define S_DEBUG_ITP_EVR_STATE    0
3351#define M_DEBUG_ITP_EVR_STATE    0x7U
3352#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
3353#define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
3354
3355#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
3356
3357#define S_DEBUG_ST_DBP_THREAD2_CIMFL    25
3358#define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
3359#define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
3360#define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
3361
3362#define S_DEBUG_ST_DBP_THREAD2_MAIN    20
3363#define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
3364#define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
3365#define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
3366
3367#define S_DEBUG_ST_DBP_THREAD1_CIMFL    15
3368#define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
3369#define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
3370#define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
3371
3372#define S_DEBUG_ST_DBP_THREAD1_MAIN    10
3373#define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
3374#define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
3375#define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
3376
3377#define S_DEBUG_ST_DBP_THREAD0_CIMFL    5
3378#define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
3379#define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
3380#define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
3381
3382#define S_DEBUG_ST_DBP_THREAD0_MAIN    0
3383#define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
3384#define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
3385#define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
3386
3387#define S_T6_DEBUG_ST_DBP_UPCP_MAIN    14
3388#define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
3389#define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
3390#define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
3391
3392#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
3393
3394#define S_DEBUG_ST_DBP_UPCP_MAIN    14
3395#define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
3396#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
3397#define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
3398
3399#define S_DEBUG_ST_DBP_DBFIFO_MAIN    13
3400#define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
3401#define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
3402
3403#define S_DEBUG_ST_DBP_CTXT    10
3404#define M_DEBUG_ST_DBP_CTXT    0x7U
3405#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
3406#define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
3407
3408#define S_DEBUG_ST_DBP_THREAD3_CIMFL    5
3409#define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
3410#define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
3411#define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
3412
3413#define S_DEBUG_ST_DBP_THREAD3_MAIN    0
3414#define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
3415#define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
3416#define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
3417
3418#define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
3419
3420#define S_DEBUG_ST_EDMA3_ALIGN_SUB    29
3421#define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
3422#define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
3423#define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
3424
3425#define S_DEBUG_ST_EDMA3_ALIGN    27
3426#define M_DEBUG_ST_EDMA3_ALIGN    0x3U
3427#define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
3428#define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
3429
3430#define S_DEBUG_ST_EDMA3_REQ    24
3431#define M_DEBUG_ST_EDMA3_REQ    0x7U
3432#define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
3433#define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
3434
3435#define S_DEBUG_ST_EDMA2_ALIGN_SUB    21
3436#define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
3437#define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
3438#define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
3439
3440#define S_DEBUG_ST_EDMA2_ALIGN    19
3441#define M_DEBUG_ST_EDMA2_ALIGN    0x3U
3442#define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
3443#define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
3444
3445#define S_DEBUG_ST_EDMA2_REQ    16
3446#define M_DEBUG_ST_EDMA2_REQ    0x7U
3447#define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
3448#define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
3449
3450#define S_DEBUG_ST_EDMA1_ALIGN_SUB    13
3451#define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
3452#define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
3453#define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
3454
3455#define S_DEBUG_ST_EDMA1_ALIGN    11
3456#define M_DEBUG_ST_EDMA1_ALIGN    0x3U
3457#define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
3458#define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
3459
3460#define S_DEBUG_ST_EDMA1_REQ    8
3461#define M_DEBUG_ST_EDMA1_REQ    0x7U
3462#define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
3463#define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
3464
3465#define S_DEBUG_ST_EDMA0_ALIGN_SUB    5
3466#define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
3467#define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
3468#define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
3469
3470#define S_DEBUG_ST_EDMA0_ALIGN    3
3471#define M_DEBUG_ST_EDMA0_ALIGN    0x3U
3472#define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
3473#define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
3474
3475#define S_DEBUG_ST_EDMA0_REQ    0
3476#define M_DEBUG_ST_EDMA0_REQ    0x7U
3477#define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
3478#define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
3479
3480#define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
3481
3482#define S_DEBUG_ST_FLM_DBPTR    30
3483#define M_DEBUG_ST_FLM_DBPTR    0x3U
3484#define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
3485#define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
3486
3487#define S_DEBUG_FLM_CACHE_LOCKED_COUNT    23
3488#define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
3489#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
3490#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
3491
3492#define S_DEBUG_FLM_CACHE_AGENT    20
3493#define M_DEBUG_FLM_CACHE_AGENT    0x7U
3494#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
3495#define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
3496
3497#define S_DEBUG_ST_FLM_CACHE    16
3498#define M_DEBUG_ST_FLM_CACHE    0xfU
3499#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
3500#define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
3501
3502#define S_DEBUG_FLM_DBPTR_CIDX_STALL    12
3503#define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
3504#define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
3505
3506#define S_DEBUG_FLM_DBPTR_QID    0
3507#define