1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Definitions of T4 work request and CPL5 commands and status codes. 14 * 15 * Copyright (C) 2008-2013 Chelsio Communications. All rights reserved. 16 * 17 * Written by Dimitris Michailidis (dm@chelsio.com) 18 * 19 * This program is distributed in the hope that it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 22 * release for licensing terms and conditions. 23 */ 24 25 #ifndef __CXGBE_T4_MSG_H 26 #define __CXGBE_T4_MSG_H 27 28 enum { 29 CPL_PASS_OPEN_REQ = 0x1, 30 CPL_PASS_ACCEPT_RPL = 0x2, 31 CPL_ACT_OPEN_REQ = 0x3, 32 CPL_SET_TCB = 0x4, 33 CPL_SET_TCB_FIELD = 0x5, 34 CPL_GET_TCB = 0x6, 35 CPL_CLOSE_CON_REQ = 0x8, 36 CPL_CLOSE_LISTSRV_REQ = 0x9, 37 CPL_ABORT_REQ = 0xA, 38 CPL_ABORT_RPL = 0xB, 39 CPL_TX_DATA = 0xC, 40 CPL_RX_DATA_ACK = 0xD, 41 CPL_TX_PKT = 0xE, 42 CPL_RTE_DELETE_REQ = 0xF, 43 CPL_RTE_WRITE_REQ = 0x10, 44 CPL_RTE_READ_REQ = 0x11, 45 CPL_L2T_WRITE_REQ = 0x12, 46 CPL_L2T_READ_REQ = 0x13, 47 CPL_SMT_WRITE_REQ = 0x14, 48 CPL_SMT_READ_REQ = 0x15, 49 CPL_TAG_WRITE_REQ = 0x16, 50 CPL_BARRIER = 0x18, 51 CPL_TID_RELEASE = 0x1A, 52 CPL_TAG_READ_REQ = 0x1B, 53 CPL_TX_PKT_FSO = 0x1E, 54 CPL_TX_PKT_ISO = 0x1F, 55 56 CPL_CLOSE_LISTSRV_RPL = 0x20, 57 CPL_ERROR = 0x21, 58 CPL_GET_TCB_RPL = 0x22, 59 CPL_L2T_WRITE_RPL = 0x23, 60 CPL_PASS_OPEN_RPL = 0x24, 61 CPL_ACT_OPEN_RPL = 0x25, 62 CPL_PEER_CLOSE = 0x26, 63 CPL_RTE_DELETE_RPL = 0x27, 64 CPL_RTE_WRITE_RPL = 0x28, 65 CPL_RX_URG_PKT = 0x29, 66 CPL_TAG_WRITE_RPL = 0x2A, 67 CPL_ABORT_REQ_RSS = 0x2B, 68 CPL_RX_URG_NOTIFY = 0x2C, 69 CPL_ABORT_RPL_RSS = 0x2D, 70 CPL_SMT_WRITE_RPL = 0x2E, 71 CPL_TX_DATA_ACK = 0x2F, 72 73 CPL_RX_PHYS_ADDR = 0x30, 74 CPL_PCMD_READ_RPL = 0x31, 75 CPL_CLOSE_CON_RPL = 0x32, 76 CPL_ISCSI_HDR = 0x33, 77 CPL_L2T_READ_RPL = 0x34, 78 CPL_RDMA_CQE = 0x35, 79 CPL_RDMA_CQE_READ_RSP = 0x36, 80 CPL_RDMA_CQE_ERR = 0x37, 81 CPL_RTE_READ_RPL = 0x38, 82 CPL_RX_DATA = 0x39, 83 CPL_SET_TCB_RPL = 0x3A, 84 CPL_RX_PKT = 0x3B, 85 CPL_TAG_READ_RPL = 0x3C, 86 CPL_HIT_NOTIFY = 0x3D, 87 CPL_PKT_NOTIFY = 0x3E, 88 CPL_RX_DDP_COMPLETE = 0x3F, 89 90 CPL_ACT_ESTABLISH = 0x40, 91 CPL_PASS_ESTABLISH = 0x41, 92 CPL_RX_DATA_DDP = 0x42, 93 CPL_SMT_READ_RPL = 0x43, 94 CPL_PASS_ACCEPT_REQ = 0x44, 95 CPL_RX2TX_PKT = 0x45, 96 CPL_RX_FCOE_DDP = 0x46, 97 CPL_FCOE_HDR = 0x47, 98 CPL_T5_TRACE_PKT = 0x48, 99 CPL_RX_ISCSI_DDP = 0x49, 100 CPL_RX_FCOE_DIF = 0x4A, 101 CPL_RX_DATA_DIF = 0x4B, 102 CPL_ERR_NOTIFY = 0x4D, 103 104 CPL_RDMA_READ_REQ = 0x60, 105 CPL_RX_ISCSI_DIF = 0x60, 106 107 CPL_SET_LE_REQ = 0x80, 108 CPL_PASS_OPEN_REQ6 = 0x81, 109 CPL_ACT_OPEN_REQ6 = 0x83, 110 111 CPL_RDMA_TERMINATE = 0xA2, 112 CPL_RDMA_WRITE = 0xA4, 113 CPL_SGE_EGR_UPDATE = 0xA5, 114 CPL_SET_LE_RPL = 0xA6, 115 CPL_FW2_MSG = 0xA7, 116 CPL_FW2_PLD = 0xA8, 117 CPL_T5_RDMA_READ_REQ = 0xA9, 118 CPL_RDMA_ATOMIC_REQ = 0xAA, 119 CPL_RDMA_ATOMIC_RPL = 0xAB, 120 CPL_RDMA_IMM_DATA = 0xAC, 121 CPL_RDMA_IMM_DATA_SE = 0xAD, 122 123 CPL_TRACE_PKT = 0xB0, 124 CPL_TRACE_PKT_T5 = 0x48, 125 CPL_RX2TX_DATA = 0xB1, 126 CPL_ISCSI_DATA = 0xB2, 127 CPL_FCOE_DATA = 0xB3, 128 129 CPL_FW4_MSG = 0xC0, 130 CPL_FW4_PLD = 0xC1, 131 CPL_FW4_ACK = 0xC3, 132 133 CPL_FW6_MSG = 0xE0, 134 CPL_FW6_PLD = 0xE1, 135 CPL_TX_PKT_LSO = 0xED, 136 CPL_TX_PKT_XT = 0xEE, 137 138 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 139 }; 140 141 enum CPL_error { 142 CPL_ERR_NONE = 0, 143 CPL_ERR_TCAM_PARITY = 1, 144 CPL_ERR_TCAM_FULL = 3, 145 CPL_ERR_BAD_LENGTH = 15, 146 CPL_ERR_BAD_ROUTE = 18, 147 CPL_ERR_CONN_RESET = 20, 148 CPL_ERR_CONN_EXIST_SYNRECV = 21, 149 CPL_ERR_CONN_EXIST = 22, 150 CPL_ERR_ARP_MISS = 23, 151 CPL_ERR_BAD_SYN = 24, 152 CPL_ERR_CONN_TIMEDOUT = 30, 153 CPL_ERR_XMIT_TIMEDOUT = 31, 154 CPL_ERR_PERSIST_TIMEDOUT = 32, 155 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 156 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 157 CPL_ERR_RTX_NEG_ADVICE = 35, 158 CPL_ERR_PERSIST_NEG_ADVICE = 36, 159 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 160 CPL_ERR_WAIT_ARP_RPL = 41, 161 CPL_ERR_ABORT_FAILED = 42, 162 CPL_ERR_IWARP_FLM = 50, 163 }; 164 165 enum { 166 CPL_CONN_POLICY_AUTO = 0, 167 CPL_CONN_POLICY_ASK = 1, 168 CPL_CONN_POLICY_FILTER = 2, 169 CPL_CONN_POLICY_DENY = 3 170 }; 171 172 enum { 173 ULP_MODE_NONE = 0, 174 ULP_MODE_ISCSI = 2, 175 ULP_MODE_RDMA = 4, 176 ULP_MODE_TCPDDP = 5, 177 ULP_MODE_FCOE = 6, 178 }; 179 180 enum { 181 ULP_CRC_HEADER = 1 << 0, 182 ULP_CRC_DATA = 1 << 1 183 }; 184 185 enum { 186 CPL_PASS_OPEN_ACCEPT, 187 CPL_PASS_OPEN_REJECT, 188 CPL_PASS_OPEN_ACCEPT_TNL 189 }; 190 191 enum { 192 CPL_ABORT_SEND_RST = 0, 193 CPL_ABORT_NO_RST, 194 }; 195 196 enum { /* TX_PKT_XT checksum types */ 197 TX_CSUM_TCP = 0, 198 TX_CSUM_UDP = 1, 199 TX_CSUM_CRC16 = 4, 200 TX_CSUM_CRC32 = 5, 201 TX_CSUM_CRC32C = 6, 202 TX_CSUM_FCOE = 7, 203 TX_CSUM_TCPIP = 8, 204 TX_CSUM_UDPIP = 9, 205 TX_CSUM_TCPIP6 = 10, 206 TX_CSUM_UDPIP6 = 11, 207 TX_CSUM_IP = 12, 208 }; 209 210 enum { /* packet type in CPL_RX_PKT */ 211 PKTYPE_XACT_UCAST = 0, 212 PKTYPE_HASH_UCAST = 1, 213 PKTYPE_XACT_MCAST = 2, 214 PKTYPE_HASH_MCAST = 3, 215 PKTYPE_PROMISC = 4, 216 PKTYPE_HPROMISC = 5, 217 PKTYPE_BCAST = 6 218 }; 219 220 enum { /* DMAC type in CPL_RX_PKT */ 221 DATYPE_UCAST, 222 DATYPE_MCAST, 223 DATYPE_BCAST 224 }; 225 226 enum { /* TCP congestion control algorithms */ 227 CONG_ALG_RENO, 228 CONG_ALG_TAHOE, 229 CONG_ALG_NEWRENO, 230 CONG_ALG_HIGHSPEED 231 }; 232 233 enum { /* RSS hash type */ 234 RSS_HASH_NONE = 0, /* no hash computed */ 235 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 236 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 237 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 238 }; 239 240 enum { /* LE commands */ 241 LE_CMD_READ = 0x4, 242 LE_CMD_WRITE = 0xb 243 }; 244 245 enum { /* LE request size */ 246 LE_SZ_NONE = 0, 247 LE_SZ_33 = 1, 248 LE_SZ_66 = 2, 249 LE_SZ_132 = 3, 250 LE_SZ_264 = 4, 251 LE_SZ_528 = 5 252 }; 253 254 union opcode_tid { 255 __be32 opcode_tid; 256 __u8 opcode; 257 }; 258 259 #define S_CPL_OPCODE 24 260 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 261 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 262 #define G_TID(x) ((x) & 0xFFFFFF) 263 264 /* tid is assumed to be 24-bits */ 265 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 266 267 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 268 269 /* extract the TID from a CPL command */ 270 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 271 272 /* partitioning of TID fields that also carry a queue id */ 273 #define S_TID_TID 0 274 #define M_TID_TID 0x3fff 275 #define V_TID_TID(x) ((x) << S_TID_TID) 276 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 277 278 #define S_TID_QID 14 279 #define M_TID_QID 0x3ff 280 #define V_TID_QID(x) ((x) << S_TID_QID) 281 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 282 283 union opcode_info { 284 __be64 opcode_info; 285 __u8 opcode; 286 }; 287 288 struct tcp_options { 289 __be16 mss; 290 __u8 wsf; 291 #if defined(__LITTLE_ENDIAN_BITFIELD) 292 __u8 :4; 293 __u8 unknown:1; 294 __u8 ecn:1; 295 __u8 sack:1; 296 __u8 tstamp:1; 297 #else 298 __u8 tstamp:1; 299 __u8 sack:1; 300 __u8 ecn:1; 301 __u8 unknown:1; 302 __u8 :4; 303 #endif 304 }; 305 306 struct rss_header { 307 __u8 opcode; 308 #if defined(__LITTLE_ENDIAN_BITFIELD) 309 __u8 channel:2; 310 __u8 filter_hit:1; 311 __u8 filter_tid:1; 312 __u8 hash_type:2; 313 __u8 ipv6:1; 314 __u8 send2fw:1; 315 #else 316 __u8 send2fw:1; 317 __u8 ipv6:1; 318 __u8 hash_type:2; 319 __u8 filter_tid:1; 320 __u8 filter_hit:1; 321 __u8 channel:2; 322 #endif 323 __be16 qid; 324 __be32 hash_val; 325 }; 326 327 #define S_HASHTYPE 20 328 #define M_HASHTYPE 0x3 329 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 330 331 #define S_QNUM 0 332 #define M_QNUM 0xFFFF 333 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 334 335 #ifndef CHELSIO_FW 336 struct work_request_hdr { 337 __be32 wr_hi; 338 __be32 wr_mid; 339 __be64 wr_lo; 340 }; 341 342 /* wr_mid fields */ 343 #define S_WR_LEN16 0 344 #define M_WR_LEN16 0xFF 345 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 346 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 347 348 /* wr_hi fields */ 349 #define S_WR_OP 24 350 #define M_WR_OP 0xFF 351 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 352 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 353 354 #define WR_HDR struct work_request_hdr wr 355 #define WR_HDR_SIZE sizeof (struct work_request_hdr) 356 #define RSS_HDR 357 #else 358 #define WR_HDR 359 #define WR_HDR_SIZE 0 360 #define RSS_HDR struct rss_header rss_hdr; 361 #endif 362 363 /* option 0 fields */ 364 #define S_ACCEPT_MODE 0 365 #define M_ACCEPT_MODE 0x3 366 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 367 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 368 369 #define S_TX_CHAN 2 370 #define M_TX_CHAN 0x3 371 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 372 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 373 374 #define S_NO_CONG 4 375 #define V_NO_CONG(x) ((x) << S_NO_CONG) 376 #define F_NO_CONG V_NO_CONG(1U) 377 378 #define S_DELACK 5 379 #define V_DELACK(x) ((x) << S_DELACK) 380 #define F_DELACK V_DELACK(1U) 381 382 #define S_INJECT_TIMER 6 383 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 384 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 385 386 #define S_NON_OFFLOAD 7 387 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 388 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 389 390 #define S_ULP_MODE 8 391 #define M_ULP_MODE 0xF 392 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 393 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 394 395 #define S_RCV_BUFSIZ 12 396 #define M_RCV_BUFSIZ 0x3FFU 397 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 398 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 399 400 #define S_DSCP 22 401 #define M_DSCP 0x3F 402 #define V_DSCP(x) ((x) << S_DSCP) 403 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 404 405 #define S_SMAC_SEL 28 406 #define M_SMAC_SEL 0xFF 407 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 408 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 409 410 #define S_L2T_IDX 36 411 #define M_L2T_IDX 0xFFF 412 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 413 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 414 415 #define S_TCAM_BYPASS 48 416 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 417 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 418 419 #define S_NAGLE 49 420 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 421 #define F_NAGLE V_NAGLE(1ULL) 422 423 #define S_WND_SCALE 50 424 #define M_WND_SCALE 0xF 425 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 426 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 427 428 #define S_KEEP_ALIVE 54 429 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 430 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 431 432 #define S_MAX_RT 55 433 #define M_MAX_RT 0xF 434 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 435 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 436 437 #define S_MAX_RT_OVERRIDE 59 438 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 439 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 440 441 #define S_MSS_IDX 60 442 #define M_MSS_IDX 0xF 443 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 444 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 445 446 /* option 1 fields */ 447 #define S_SYN_RSS_ENABLE 0 448 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 449 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 450 451 #define S_SYN_RSS_USE_HASH 1 452 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 453 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 454 455 #define S_SYN_RSS_QUEUE 2 456 #define M_SYN_RSS_QUEUE 0x3FF 457 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 458 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 459 460 #define S_LISTEN_INTF 12 461 #define M_LISTEN_INTF 0xFF 462 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 463 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 464 465 #define S_LISTEN_FILTER 20 466 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 467 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 468 469 #define S_SYN_DEFENSE 21 470 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 471 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 472 473 #define S_CONN_POLICY 22 474 #define M_CONN_POLICY 0x3 475 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 476 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 477 478 #define S_FILT_INFO 28 479 #define M_FILT_INFO 0xfffffffffULL 480 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 481 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 482 483 /* option 2 fields */ 484 #define S_RSS_QUEUE 0 485 #define M_RSS_QUEUE 0x3FF 486 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 487 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 488 489 #define S_RSS_QUEUE_VALID 10 490 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 491 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 492 493 #define S_RX_COALESCE_VALID 11 494 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 495 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 496 497 #define S_RX_COALESCE 12 498 #define M_RX_COALESCE 0x3 499 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 500 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 501 502 #define S_CONG_CNTRL 14 503 #define M_CONG_CNTRL 0x3 504 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 505 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 506 507 #define S_PACE 16 508 #define M_PACE 0x3 509 #define V_PACE(x) ((x) << S_PACE) 510 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 511 512 #define S_CONG_CNTRL_VALID 18 513 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 514 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 515 516 #define S_PACE_VALID 19 517 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 518 #define F_PACE_VALID V_PACE_VALID(1U) 519 520 #define S_RX_FC_DISABLE 20 521 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 522 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 523 524 #define S_RX_FC_DDP 21 525 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 526 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 527 528 #define S_RX_FC_VALID 22 529 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 530 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 531 532 #define S_TX_QUEUE 23 533 #define M_TX_QUEUE 0x7 534 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 535 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 536 537 #define S_RX_CHANNEL 26 538 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 539 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 540 541 #define S_CCTRL_ECN 27 542 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 543 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 544 545 #define S_WND_SCALE_EN 28 546 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 547 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 548 549 #define S_TSTAMPS_EN 29 550 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 551 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 552 553 #define S_SACK_EN 30 554 #define V_SACK_EN(x) ((x) << S_SACK_EN) 555 #define F_SACK_EN V_SACK_EN(1U) 556 557 #define S_T5_OPT_2_VALID 31 558 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 559 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 560 561 struct cpl_pass_open_req { 562 WR_HDR; 563 union opcode_tid ot; 564 __be16 local_port; 565 __be16 peer_port; 566 __be32 local_ip; 567 __be32 peer_ip; 568 __be64 opt0; 569 __be64 opt1; 570 }; 571 572 struct cpl_pass_open_req6 { 573 WR_HDR; 574 union opcode_tid ot; 575 __be16 local_port; 576 __be16 peer_port; 577 __be64 local_ip_hi; 578 __be64 local_ip_lo; 579 __be64 peer_ip_hi; 580 __be64 peer_ip_lo; 581 __be64 opt0; 582 __be64 opt1; 583 }; 584 585 struct cpl_pass_open_rpl { 586 RSS_HDR 587 union opcode_tid ot; 588 __u8 rsvd[3]; 589 __u8 status; 590 }; 591 592 struct cpl_pass_establish { 593 RSS_HDR 594 union opcode_tid ot; 595 __be32 rsvd; 596 __be32 tos_stid; 597 __be16 mac_idx; 598 __be16 tcp_opt; 599 __be32 snd_isn; 600 __be32 rcv_isn; 601 }; 602 603 /* cpl_pass_establish.tos_stid fields */ 604 #define S_PASS_OPEN_TID 0 605 #define M_PASS_OPEN_TID 0xFFFFFF 606 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 607 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 608 609 #define S_PASS_OPEN_TOS 24 610 #define M_PASS_OPEN_TOS 0xFF 611 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 612 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 613 614 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 615 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 616 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 617 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 618 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 619 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 620 621 struct cpl_pass_accept_req { 622 RSS_HDR 623 union opcode_tid ot; 624 __be16 rsvd; 625 __be16 len; 626 __be32 hdr_len; 627 __be16 vlan; 628 __be16 l2info; 629 __be32 tos_stid; 630 struct tcp_options tcpopt; 631 }; 632 633 /* cpl_pass_accept_req.hdr_len fields */ 634 #define S_SYN_RX_CHAN 0 635 #define M_SYN_RX_CHAN 0xF 636 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 637 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 638 639 #define S_TCP_HDR_LEN 10 640 #define M_TCP_HDR_LEN 0x3F 641 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 642 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 643 644 #define S_IP_HDR_LEN 16 645 #define M_IP_HDR_LEN 0x3FF 646 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 647 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 648 649 #define S_ETH_HDR_LEN 26 650 #define M_ETH_HDR_LEN 0x3F 651 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 652 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 653 654 /* cpl_pass_accept_req.l2info fields */ 655 #define S_SYN_MAC_IDX 0 656 #define M_SYN_MAC_IDX 0x1FF 657 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 658 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 659 660 #define S_SYN_XACT_MATCH 9 661 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 662 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 663 664 #define S_SYN_INTF 12 665 #define M_SYN_INTF 0xF 666 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 667 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 668 669 struct cpl_pass_accept_rpl { 670 WR_HDR; 671 union opcode_tid ot; 672 __be32 opt2; 673 __be64 opt0; 674 }; 675 676 struct cpl_t5_pass_accept_rpl { 677 WR_HDR; 678 union opcode_tid ot; 679 __be32 opt2; 680 __be64 opt0; 681 __be32 iss; 682 __be32 rsvd; 683 }; 684 685 struct cpl_act_open_req { 686 WR_HDR; 687 union opcode_tid ot; 688 __be16 local_port; 689 __be16 peer_port; 690 __be32 local_ip; 691 __be32 peer_ip; 692 __be64 opt0; 693 __be32 params; 694 __be32 opt2; 695 }; 696 697 #define S_FILTER_TUPLE 24 698 #define M_FILTER_TUPLE 0xFFFFFFFFFF 699 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 700 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 701 struct cpl_t5_act_open_req { 702 WR_HDR; 703 union opcode_tid ot; 704 __be16 local_port; 705 __be16 peer_port; 706 __be32 local_ip; 707 __be32 peer_ip; 708 __be64 opt0; 709 __be32 iss; 710 __be32 opt2; 711 __be64 params; 712 }; 713 714 struct cpl_act_open_req6 { 715 WR_HDR; 716 union opcode_tid ot; 717 __be16 local_port; 718 __be16 peer_port; 719 __be64 local_ip_hi; 720 __be64 local_ip_lo; 721 __be64 peer_ip_hi; 722 __be64 peer_ip_lo; 723 __be64 opt0; 724 __be32 params; 725 __be32 opt2; 726 }; 727 728 struct cpl_t5_act_open_req6 { 729 WR_HDR; 730 union opcode_tid ot; 731 __be16 local_port; 732 __be16 peer_port; 733 __be64 local_ip_hi; 734 __be64 local_ip_lo; 735 __be64 peer_ip_hi; 736 __be64 peer_ip_lo; 737 __be64 opt0; 738 __be32 iss; 739 __be32 opt2; 740 __be64 params; 741 }; 742 743 struct cpl_act_open_rpl { 744 RSS_HDR 745 union opcode_tid ot; 746 __be32 atid_status; 747 }; 748 749 /* cpl_act_open_rpl.atid_status fields */ 750 #define S_AOPEN_STATUS 0 751 #define M_AOPEN_STATUS 0xFF 752 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 753 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 754 755 #define S_AOPEN_ATID 8 756 #define M_AOPEN_ATID 0xFFFFFF 757 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 758 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 759 760 struct cpl_act_establish { 761 RSS_HDR 762 union opcode_tid ot; 763 __be32 rsvd; 764 __be32 tos_atid; 765 __be16 mac_idx; 766 __be16 tcp_opt; 767 __be32 snd_isn; 768 __be32 rcv_isn; 769 }; 770 771 struct cpl_get_tcb { 772 WR_HDR; 773 union opcode_tid ot; 774 __be16 reply_ctrl; 775 __be16 cookie; 776 }; 777 778 /* cpl_get_tcb.reply_ctrl fields */ 779 #define S_QUEUENO 0 780 #define M_QUEUENO 0x3FF 781 #define V_QUEUENO(x) ((x) << S_QUEUENO) 782 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 783 784 #define S_REPLY_CHAN 14 785 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 786 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 787 788 #define S_NO_REPLY 15 789 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 790 #define F_NO_REPLY V_NO_REPLY(1U) 791 792 struct cpl_get_tcb_rpl { 793 RSS_HDR 794 union opcode_tid ot; 795 __u8 cookie; 796 __u8 status; 797 __be16 len; 798 }; 799 800 struct cpl_set_tcb { 801 WR_HDR; 802 union opcode_tid ot; 803 __be16 reply_ctrl; 804 __be16 cookie; 805 }; 806 807 struct cpl_set_tcb_field { 808 WR_HDR; 809 union opcode_tid ot; 810 __be16 reply_ctrl; 811 __be16 word_cookie; 812 __be64 mask; 813 __be64 val; 814 }; 815 816 struct cpl_set_tcb_field_core { 817 union opcode_tid ot; 818 __be16 reply_ctrl; 819 __be16 word_cookie; 820 __be64 mask; 821 __be64 val; 822 }; 823 824 /* cpl_set_tcb_field.word_cookie fields */ 825 #define S_WORD 0 826 #define M_WORD 0x1F 827 #define V_WORD(x) ((x) << S_WORD) 828 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 829 830 #define S_COOKIE 5 831 #define M_COOKIE 0x7 832 #define V_COOKIE(x) ((x) << S_COOKIE) 833 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 834 835 struct cpl_set_tcb_rpl { 836 RSS_HDR 837 union opcode_tid ot; 838 __be16 rsvd; 839 __u8 cookie; 840 __u8 status; 841 __be64 oldval; 842 }; 843 844 struct cpl_close_con_req { 845 WR_HDR; 846 union opcode_tid ot; 847 __be32 rsvd; 848 }; 849 850 struct cpl_close_con_rpl { 851 RSS_HDR 852 union opcode_tid ot; 853 __u8 rsvd[3]; 854 __u8 status; 855 __be32 snd_nxt; 856 __be32 rcv_nxt; 857 }; 858 859 struct cpl_close_listsvr_req { 860 WR_HDR; 861 union opcode_tid ot; 862 __be16 reply_ctrl; 863 __be16 rsvd; 864 }; 865 866 /* additional cpl_close_listsvr_req.reply_ctrl field */ 867 #define S_LISTSVR_IPV6 14 868 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 869 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 870 871 struct cpl_close_listsvr_rpl { 872 RSS_HDR 873 union opcode_tid ot; 874 __u8 rsvd[3]; 875 __u8 status; 876 }; 877 878 struct cpl_abort_req_rss { 879 RSS_HDR 880 union opcode_tid ot; 881 __u8 rsvd[3]; 882 __u8 status; 883 }; 884 885 struct cpl_abort_req { 886 WR_HDR; 887 union opcode_tid ot; 888 __be32 rsvd0; 889 __u8 rsvd1; 890 __u8 cmd; 891 __u8 rsvd2[6]; 892 }; 893 894 struct cpl_abort_rpl_rss { 895 RSS_HDR 896 union opcode_tid ot; 897 __u8 rsvd[3]; 898 __u8 status; 899 }; 900 901 struct cpl_abort_rpl { 902 WR_HDR; 903 union opcode_tid ot; 904 __be32 rsvd0; 905 __u8 rsvd1; 906 __u8 cmd; 907 __u8 rsvd2[6]; 908 }; 909 910 struct cpl_peer_close { 911 RSS_HDR 912 union opcode_tid ot; 913 __be32 rcv_nxt; 914 }; 915 916 struct cpl_tid_release { 917 WR_HDR; 918 union opcode_tid ot; 919 __be32 rsvd; 920 }; 921 922 struct tx_data_wr { 923 __be32 wr_hi; 924 __be32 wr_lo; 925 __be32 len; 926 __be32 flags; 927 __be32 sndseq; 928 __be32 param; 929 }; 930 931 /* tx_data_wr.flags fields */ 932 #define S_TX_ACK_PAGES 21 933 #define M_TX_ACK_PAGES 0x7 934 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 935 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 936 937 /* tx_data_wr.param fields */ 938 #define S_TX_PORT 0 939 #define M_TX_PORT 0x7 940 #define V_TX_PORT(x) ((x) << S_TX_PORT) 941 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 942 943 #define S_TX_MSS 4 944 #define M_TX_MSS 0xF 945 #define V_TX_MSS(x) ((x) << S_TX_MSS) 946 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 947 948 #define S_TX_QOS 8 949 #define M_TX_QOS 0xFF 950 #define V_TX_QOS(x) ((x) << S_TX_QOS) 951 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 952 953 #define S_TX_SNDBUF 16 954 #define M_TX_SNDBUF 0xFFFF 955 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 956 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 957 958 struct cpl_tx_data { 959 union opcode_tid ot; 960 __be32 len; 961 __be32 rsvd; 962 __be32 flags; 963 }; 964 965 /* cpl_tx_data.flags fields */ 966 #define S_TX_PROXY 5 967 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 968 #define F_TX_PROXY V_TX_PROXY(1U) 969 970 #define S_TX_ULP_SUBMODE 6 971 #define M_TX_ULP_SUBMODE 0xF 972 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 973 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 974 975 #define S_TX_ULP_MODE 10 976 #define M_TX_ULP_MODE 0xF 977 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 978 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 979 980 #define S_TX_SHOVE 14 981 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 982 #define F_TX_SHOVE V_TX_SHOVE(1U) 983 984 #define S_TX_MORE 15 985 #define V_TX_MORE(x) ((x) << S_TX_MORE) 986 #define F_TX_MORE V_TX_MORE(1U) 987 988 #define S_TX_URG 16 989 #define V_TX_URG(x) ((x) << S_TX_URG) 990 #define F_TX_URG V_TX_URG(1U) 991 992 #define S_TX_FLUSH 17 993 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 994 #define F_TX_FLUSH V_TX_FLUSH(1U) 995 996 #define S_TX_SAVE 18 997 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 998 #define F_TX_SAVE V_TX_SAVE(1U) 999 1000 #define S_TX_TNL 19 1001 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1002 #define F_TX_TNL V_TX_TNL(1U) 1003 1004 /* additional tx_data_wr.flags fields */ 1005 #define S_TX_CPU_IDX 0 1006 #define M_TX_CPU_IDX 0x3F 1007 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1008 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1009 1010 #define S_TX_CLOSE 17 1011 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1012 #define F_TX_CLOSE V_TX_CLOSE(1U) 1013 1014 #define S_TX_INIT 18 1015 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1016 #define F_TX_INIT V_TX_INIT(1U) 1017 1018 #define S_TX_IMM_ACK 19 1019 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1020 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1021 1022 #define S_TX_IMM_DMA 20 1023 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1024 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1025 1026 struct cpl_tx_data_ack { 1027 RSS_HDR 1028 union opcode_tid ot; 1029 __be32 snd_una; 1030 }; 1031 1032 struct cpl_wr_ack { /* TODO */ 1033 RSS_HDR 1034 union opcode_tid ot; 1035 __be16 credits; 1036 __be16 rsvd; 1037 __be32 snd_nxt; 1038 __be32 snd_una; 1039 }; 1040 1041 struct cpl_tx_pkt_core { 1042 __be32 ctrl0; 1043 __be16 pack; 1044 __be16 len; 1045 __be64 ctrl1; 1046 }; 1047 1048 struct cpl_tx_pkt { 1049 WR_HDR; 1050 struct cpl_tx_pkt_core c; 1051 }; 1052 1053 #define cpl_tx_pkt_xt cpl_tx_pkt 1054 1055 /* cpl_tx_pkt_core.ctrl0 fields */ 1056 #define S_TXPKT_VF 0 1057 #define M_TXPKT_VF 0xFF 1058 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1059 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1060 1061 #define S_TXPKT_PF 8 1062 #define M_TXPKT_PF 0x7 1063 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1064 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1065 1066 #define S_TXPKT_VF_VLD 11 1067 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1068 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1069 1070 #define S_TXPKT_OVLAN_IDX 12 1071 #define M_TXPKT_OVLAN_IDX 0xF 1072 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1073 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1074 1075 #define S_TXPKT_T5_OVLAN_IDX 12 1076 #define M_TXPKT_T5_OVLAN_IDX 0x7 1077 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1078 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1079 M_TXPKT_T5_OVLAN_IDX) 1080 1081 #define S_TXPKT_INTF 16 1082 #define M_TXPKT_INTF 0xF 1083 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1084 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1085 1086 #define S_TXPKT_SPECIAL_STAT 20 1087 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1088 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1089 1090 #define S_TXPKT_T5_FCS_DIS 21 1091 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1092 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1093 1094 #define S_TXPKT_INS_OVLAN 21 1095 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1096 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1097 1098 #define S_TXPKT_T5_INS_OVLAN 15 1099 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1100 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1101 1102 #define S_TXPKT_STAT_DIS 22 1103 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1104 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1105 1106 #define S_TXPKT_LOOPBACK 23 1107 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1108 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1109 1110 #define S_TXPKT_TSTAMP 23 1111 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1112 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1113 1114 #define S_TXPKT_OPCODE 24 1115 #define M_TXPKT_OPCODE 0xFF 1116 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1117 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1118 1119 /* cpl_tx_pkt_core.ctrl1 fields */ 1120 #define S_TXPKT_SA_IDX 0 1121 #define M_TXPKT_SA_IDX 0xFFF 1122 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1123 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1124 1125 #define S_TXPKT_CSUM_END 12 1126 #define M_TXPKT_CSUM_END 0xFF 1127 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1128 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1129 1130 #define S_TXPKT_CSUM_START 20 1131 #define M_TXPKT_CSUM_START 0x3FF 1132 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1133 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1134 1135 #define S_TXPKT_IPHDR_LEN 20 1136 #define M_TXPKT_IPHDR_LEN 0x3FFF 1137 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1138 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1139 1140 #define S_TXPKT_CSUM_LOC 30 1141 #define M_TXPKT_CSUM_LOC 0x3FF 1142 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1143 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1144 1145 #define S_TXPKT_ETHHDR_LEN 34 1146 #define M_TXPKT_ETHHDR_LEN 0x3F 1147 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1148 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1149 1150 #define S_TXPKT_CSUM_TYPE 40 1151 #define M_TXPKT_CSUM_TYPE 0xF 1152 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1153 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1154 1155 #define S_TXPKT_VLAN 44 1156 #define M_TXPKT_VLAN 0xFFFF 1157 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1158 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1159 1160 #define S_TXPKT_VLAN_VLD 60 1161 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1162 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1163 1164 #define S_TXPKT_IPSEC 61 1165 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1166 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1167 1168 #define S_TXPKT_IPCSUM_DIS 62 1169 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1170 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1171 1172 #define S_TXPKT_L4CSUM_DIS 63 1173 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1174 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1175 1176 struct cpl_tx_pkt_lso_core{ 1177 __be32 lso_ctrl; 1178 __be16 ipid_ofst; 1179 __be16 mss; 1180 __be32 seqno_offset; 1181 __be32 len; 1182 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1183 }; 1184 1185 struct cpl_tx_pkt_lso { 1186 WR_HDR; 1187 struct cpl_tx_pkt_lso_core c; 1188 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1189 }; 1190 1191 struct cpl_tx_pkt_ufo_core { 1192 __be16 ethlen; 1193 __be16 iplen; 1194 __be16 udplen; 1195 __be16 mss; 1196 __be32 len; 1197 __be32 r1; 1198 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1199 }; 1200 1201 struct cpl_tx_pkt_ufo { 1202 WR_HDR; 1203 struct cpl_tx_pkt_ufo_core c; 1204 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1205 }; 1206 1207 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1208 #define S_LSO_TCPHDR_LEN 0 1209 #define M_LSO_TCPHDR_LEN 0xF 1210 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1211 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1212 1213 #define S_LSO_IPHDR_LEN 4 1214 #define M_LSO_IPHDR_LEN 0xFFF 1215 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1216 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1217 1218 #define S_LSO_ETHHDR_LEN 16 1219 #define M_LSO_ETHHDR_LEN 0xF 1220 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1221 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1222 1223 #define S_LSO_IPV6 20 1224 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1225 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1226 1227 #define S_LSO_OFLD_ENCAP 21 1228 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1229 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1230 1231 #define S_LSO_LAST_SLICE 22 1232 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1233 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1234 1235 #define S_LSO_FIRST_SLICE 23 1236 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1237 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1238 1239 #define S_LSO_OPCODE 24 1240 #define M_LSO_OPCODE 0xFF 1241 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1242 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1243 1244 #define S_LSO_T5_XFER_SIZE 0 1245 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1246 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1247 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1248 1249 /* cpl_tx_pkt_lso_core.mss fields */ 1250 #define S_LSO_MSS 0 1251 #define M_LSO_MSS 0x3FFF 1252 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1253 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1254 1255 #define S_LSO_IPID_SPLIT 15 1256 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1257 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1258 1259 struct cpl_tx_pkt_fso { 1260 WR_HDR; 1261 __be32 fso_ctrl; 1262 __be16 seqcnt_ofst; 1263 __be16 mtu; 1264 __be32 param_offset; 1265 __be32 len; 1266 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1267 }; 1268 1269 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1270 #define S_FSO_XCHG_CLASS 21 1271 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1272 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1273 1274 #define S_FSO_INITIATOR 20 1275 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1276 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1277 1278 #define S_FSO_FCHDR_LEN 12 1279 #define M_FSO_FCHDR_LEN 0xF 1280 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1281 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1282 1283 struct cpl_iscsi_hdr_no_rss { 1284 union opcode_tid ot; 1285 __be16 pdu_len_ddp; 1286 __be16 len; 1287 __be32 seq; 1288 __be16 urg; 1289 __u8 rsvd; 1290 __u8 status; 1291 }; 1292 1293 struct cpl_tx_data_iso { 1294 WR_HDR; 1295 __be32 iso_ctrl; 1296 __u8 rsvd; 1297 __u8 ahs_len; 1298 __be16 mss; 1299 __be32 burst_size; 1300 __be32 len; 1301 /* encapsulated CPL_TX_DATA follows here */ 1302 }; 1303 1304 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1305 #define S_ISO_CPLHDR_LEN 18 1306 #define M_ISO_CPLHDR_LEN 0xF 1307 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1308 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1309 1310 #define S_ISO_HDR_CRC 17 1311 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1312 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1313 1314 #define S_ISO_DATA_CRC 16 1315 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1316 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1317 1318 #define S_ISO_IMD_DATA_EN 15 1319 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1320 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1321 1322 #define S_ISO_PDU_TYPE 13 1323 #define M_ISO_PDU_TYPE 0x3 1324 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1325 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1326 1327 struct cpl_iscsi_hdr { 1328 RSS_HDR 1329 union opcode_tid ot; 1330 __be16 pdu_len_ddp; 1331 __be16 len; 1332 __be32 seq; 1333 __be16 urg; 1334 __u8 rsvd; 1335 __u8 status; 1336 }; 1337 1338 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1339 #define S_ISCSI_PDU_LEN 0 1340 #define M_ISCSI_PDU_LEN 0x7FFF 1341 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1342 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1343 1344 #define S_ISCSI_DDP 15 1345 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1346 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1347 1348 struct cpl_iscsi_data { 1349 RSS_HDR 1350 union opcode_tid ot; 1351 __u8 rsvd0[2]; 1352 __be16 len; 1353 __be32 seq; 1354 __be16 urg; 1355 __u8 rsvd1; 1356 __u8 status; 1357 }; 1358 1359 struct cpl_rx_data { 1360 RSS_HDR 1361 union opcode_tid ot; 1362 __be16 rsvd; 1363 __be16 len; 1364 __be32 seq; 1365 __be16 urg; 1366 #if defined(__LITTLE_ENDIAN_BITFIELD) 1367 __u8 dack_mode:2; 1368 __u8 psh:1; 1369 __u8 heartbeat:1; 1370 __u8 ddp_off:1; 1371 __u8 :3; 1372 #else 1373 __u8 :3; 1374 __u8 ddp_off:1; 1375 __u8 heartbeat:1; 1376 __u8 psh:1; 1377 __u8 dack_mode:2; 1378 #endif 1379 __u8 status; 1380 }; 1381 1382 struct cpl_fcoe_hdr { 1383 RSS_HDR 1384 union opcode_tid ot; 1385 __be16 oxid; 1386 __be16 len; 1387 __be32 rctl_fctl; 1388 __u8 cs_ctl; 1389 __u8 df_ctl; 1390 __u8 sof; 1391 __u8 eof; 1392 __be16 seq_cnt; 1393 __u8 seq_id; 1394 __u8 type; 1395 __be32 param; 1396 }; 1397 1398 struct cpl_fcoe_data { 1399 RSS_HDR 1400 union opcode_tid ot; 1401 __u8 rsvd0[2]; 1402 __be16 len; 1403 __be32 seq; 1404 __u8 rsvd1[3]; 1405 __u8 status; 1406 }; 1407 1408 struct cpl_rx_urg_notify { 1409 RSS_HDR 1410 union opcode_tid ot; 1411 __be32 seq; 1412 }; 1413 1414 struct cpl_rx_urg_pkt { 1415 RSS_HDR 1416 union opcode_tid ot; 1417 __be16 rsvd; 1418 __be16 len; 1419 }; 1420 1421 struct cpl_rx_data_ack { 1422 WR_HDR; 1423 union opcode_tid ot; 1424 __be32 credit_dack; 1425 }; 1426 1427 struct cpl_rx_data_ack_core { 1428 union opcode_tid ot; 1429 __be32 credit_dack; 1430 }; 1431 1432 /* cpl_rx_data_ack.ack_seq fields */ 1433 #define S_RX_CREDITS 0 1434 #define M_RX_CREDITS 0x3FFFFFF 1435 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1436 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1437 1438 #define S_RX_MODULATE_TX 26 1439 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1440 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1441 1442 #define S_RX_MODULATE_RX 27 1443 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1444 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1445 1446 #define S_RX_FORCE_ACK 28 1447 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1448 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1449 1450 #define S_RX_DACK_MODE 29 1451 #define M_RX_DACK_MODE 0x3 1452 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1453 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1454 1455 #define S_RX_DACK_CHANGE 31 1456 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1457 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1458 1459 struct cpl_rx_ddp_complete { 1460 RSS_HDR 1461 union opcode_tid ot; 1462 __be32 ddp_report; 1463 __be32 rcv_nxt; 1464 __be32 rsvd; 1465 }; 1466 1467 struct cpl_rx_data_ddp { 1468 RSS_HDR 1469 union opcode_tid ot; 1470 __be16 urg; 1471 __be16 len; 1472 __be32 seq; 1473 union { 1474 __be32 nxt_seq; 1475 __be32 ddp_report; 1476 } u; 1477 __be32 ulp_crc; 1478 __be32 ddpvld; 1479 }; 1480 1481 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1482 1483 struct cpl_rx_fcoe_ddp { 1484 RSS_HDR 1485 union opcode_tid ot; 1486 __be16 rsvd; 1487 __be16 len; 1488 __be32 seq; 1489 __be32 ddp_report; 1490 __be32 ulp_crc; 1491 __be32 ddpvld; 1492 }; 1493 1494 struct cpl_rx_data_dif { 1495 RSS_HDR 1496 union opcode_tid ot; 1497 __be16 ddp_len; 1498 __be16 msg_len; 1499 __be32 seq; 1500 union { 1501 __be32 nxt_seq; 1502 __be32 ddp_report; 1503 } u; 1504 __be32 err_vec; 1505 __be32 ddpvld; 1506 }; 1507 1508 struct cpl_rx_iscsi_dif { 1509 RSS_HDR 1510 union opcode_tid ot; 1511 __be16 ddp_len; 1512 __be16 msg_len; 1513 __be32 seq; 1514 union { 1515 __be32 nxt_seq; 1516 __be32 ddp_report; 1517 } u; 1518 __be32 ulp_crc; 1519 __be32 ddpvld; 1520 __u8 rsvd0[8]; 1521 __be32 err_vec; 1522 __u8 rsvd1[4]; 1523 }; 1524 1525 struct cpl_rx_fcoe_dif { 1526 RSS_HDR 1527 union opcode_tid ot; 1528 __be16 ddp_len; 1529 __be16 msg_len; 1530 __be32 seq; 1531 __be32 ddp_report; 1532 __be32 err_vec; 1533 __be32 ddpvld; 1534 }; 1535 1536 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1537 #define S_DDP_VALID 15 1538 #define M_DDP_VALID 0x1FFFF 1539 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1540 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1541 1542 #define S_DDP_PPOD_MISMATCH 15 1543 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1544 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1545 1546 #define S_DDP_PDU 16 1547 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1548 #define F_DDP_PDU V_DDP_PDU(1U) 1549 1550 #define S_DDP_LLIMIT_ERR 17 1551 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1552 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1553 1554 #define S_DDP_PPOD_PARITY_ERR 18 1555 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1556 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1557 1558 #define S_DDP_PADDING_ERR 19 1559 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1560 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1561 1562 #define S_DDP_HDRCRC_ERR 20 1563 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1564 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1565 1566 #define S_DDP_DATACRC_ERR 21 1567 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1568 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1569 1570 #define S_DDP_INVALID_TAG 22 1571 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1572 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1573 1574 #define S_DDP_ULIMIT_ERR 23 1575 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1576 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1577 1578 #define S_DDP_OFFSET_ERR 24 1579 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1580 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1581 1582 #define S_DDP_COLOR_ERR 25 1583 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1584 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1585 1586 #define S_DDP_TID_MISMATCH 26 1587 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1588 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1589 1590 #define S_DDP_INVALID_PPOD 27 1591 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1592 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1593 1594 #define S_DDP_ULP_MODE 28 1595 #define M_DDP_ULP_MODE 0xF 1596 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1597 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1598 1599 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1600 #define S_DDP_OFFSET 0 1601 #define M_DDP_OFFSET 0xFFFFFF 1602 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1603 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1604 1605 #define S_DDP_DACK_MODE 24 1606 #define M_DDP_DACK_MODE 0x3 1607 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1608 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1609 1610 #define S_DDP_BUF_IDX 26 1611 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1612 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1613 1614 #define S_DDP_URG 27 1615 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1616 #define F_DDP_URG V_DDP_URG(1U) 1617 1618 #define S_DDP_PSH 28 1619 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1620 #define F_DDP_PSH V_DDP_PSH(1U) 1621 1622 #define S_DDP_BUF_COMPLETE 29 1623 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1624 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1625 1626 #define S_DDP_BUF_TIMED_OUT 30 1627 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1628 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1629 1630 #define S_DDP_INV 31 1631 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1632 #define F_DDP_INV V_DDP_INV(1U) 1633 1634 struct cpl_rx_pkt { 1635 RSS_HDR 1636 __u8 opcode; 1637 #if defined(__LITTLE_ENDIAN_BITFIELD) 1638 __u8 iff:4; 1639 __u8 csum_calc:1; 1640 __u8 ipmi_pkt:1; 1641 __u8 vlan_ex:1; 1642 __u8 ip_frag:1; 1643 #else 1644 __u8 ip_frag:1; 1645 __u8 vlan_ex:1; 1646 __u8 ipmi_pkt:1; 1647 __u8 csum_calc:1; 1648 __u8 iff:4; 1649 #endif 1650 __be16 csum; 1651 __be16 vlan; 1652 __be16 len; 1653 __be32 l2info; 1654 __be16 hdr_len; 1655 __be16 err_vec; 1656 }; 1657 1658 /* rx_pkt.l2info fields */ 1659 #define S_RX_ETHHDR_LEN 0 1660 #define M_RX_ETHHDR_LEN 0x1F 1661 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1662 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1663 1664 #define S_RX_T5_ETHHDR_LEN 0 1665 #define M_RX_T5_ETHHDR_LEN 0x3F 1666 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1667 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1668 1669 #define S_RX_PKTYPE 5 1670 #define M_RX_PKTYPE 0x7 1671 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1672 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1673 1674 #define S_RX_T5_DATYPE 6 1675 #define M_RX_T5_DATYPE 0x3 1676 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1677 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1678 1679 #define S_RX_MACIDX 8 1680 #define M_RX_MACIDX 0x1FF 1681 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1682 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1683 1684 #define S_RX_T5_PKTYPE 17 1685 #define M_RX_T5_PKTYPE 0x7 1686 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1687 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1688 1689 #define S_RX_DATYPE 18 1690 #define M_RX_DATYPE 0x3 1691 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1692 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1693 1694 #define S_RXF_PSH 20 1695 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1696 #define F_RXF_PSH V_RXF_PSH(1U) 1697 1698 #define S_RXF_SYN 21 1699 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1700 #define F_RXF_SYN V_RXF_SYN(1U) 1701 1702 #define S_RXF_UDP 22 1703 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1704 #define F_RXF_UDP V_RXF_UDP(1U) 1705 1706 #define S_RXF_TCP 23 1707 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1708 #define F_RXF_TCP V_RXF_TCP(1U) 1709 1710 #define S_RXF_IP 24 1711 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1712 #define F_RXF_IP V_RXF_IP(1U) 1713 1714 #define S_RXF_IP6 25 1715 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1716 #define F_RXF_IP6 V_RXF_IP6(1U) 1717 1718 #define S_RXF_SYN_COOKIE 26 1719 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1720 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1721 1722 #define S_RXF_FCOE 26 1723 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1724 #define F_RXF_FCOE V_RXF_FCOE(1U) 1725 1726 #define S_RXF_LRO 27 1727 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1728 #define F_RXF_LRO V_RXF_LRO(1U) 1729 1730 #define S_RX_CHAN 28 1731 #define M_RX_CHAN 0xF 1732 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1733 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1734 1735 /* rx_pkt.hdr_len fields */ 1736 #define S_RX_TCPHDR_LEN 0 1737 #define M_RX_TCPHDR_LEN 0x3F 1738 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1739 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1740 1741 #define S_RX_IPHDR_LEN 6 1742 #define M_RX_IPHDR_LEN 0x3FF 1743 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1744 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1745 1746 /* rx_pkt.err_vec fields */ 1747 #define S_RXERR_OR 0 1748 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1749 #define F_RXERR_OR V_RXERR_OR(1U) 1750 1751 #define S_RXERR_MAC 1 1752 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1753 #define F_RXERR_MAC V_RXERR_MAC(1U) 1754 1755 #define S_RXERR_IPVERS 2 1756 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1757 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1758 1759 #define S_RXERR_FRAG 3 1760 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1761 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1762 1763 #define S_RXERR_ATTACK 4 1764 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1765 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1766 1767 #define S_RXERR_ETHHDR_LEN 5 1768 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1769 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1770 1771 #define S_RXERR_IPHDR_LEN 6 1772 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1773 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1774 1775 #define S_RXERR_TCPHDR_LEN 7 1776 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1777 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1778 1779 #define S_RXERR_PKT_LEN 8 1780 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1781 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1782 1783 #define S_RXERR_TCP_OPT 9 1784 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1785 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1786 1787 #define S_RXERR_IPCSUM 12 1788 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1789 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1790 1791 #define S_RXERR_CSUM 13 1792 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1793 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1794 1795 #define S_RXERR_PING 14 1796 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1797 #define F_RXERR_PING V_RXERR_PING(1U) 1798 1799 struct cpl_trace_pkt { 1800 RSS_HDR 1801 __u8 opcode; 1802 __u8 intf; 1803 #if defined(__LITTLE_ENDIAN_BITFIELD) 1804 __u8 runt:4; 1805 __u8 filter_hit:4; 1806 __u8 :6; 1807 __u8 err:1; 1808 __u8 trunc:1; 1809 #else 1810 __u8 filter_hit:4; 1811 __u8 runt:4; 1812 __u8 trunc:1; 1813 __u8 err:1; 1814 __u8 :6; 1815 #endif 1816 __be16 rsvd; 1817 __be16 len; 1818 __be64 tstamp; 1819 }; 1820 1821 struct cpl_t5_trace_pkt { 1822 RSS_HDR 1823 __u8 opcode; 1824 __u8 intf; 1825 #if defined(__LITTLE_ENDIAN_BITFIELD) 1826 __u8 runt:4; 1827 __u8 filter_hit:4; 1828 __u8 :6; 1829 __u8 err:1; 1830 __u8 trunc:1; 1831 #else 1832 __u8 filter_hit:4; 1833 __u8 runt:4; 1834 __u8 trunc:1; 1835 __u8 err:1; 1836 __u8 :6; 1837 #endif 1838 __be16 rsvd; 1839 __be16 len; 1840 __be64 tstamp; 1841 __be64 rsvd1; 1842 }; 1843 1844 struct cpl_rte_delete_req { 1845 WR_HDR; 1846 union opcode_tid ot; 1847 __be32 params; 1848 }; 1849 1850 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1851 #define S_RTE_REQ_LUT_IX 8 1852 #define M_RTE_REQ_LUT_IX 0x7FF 1853 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1854 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1855 1856 #define S_RTE_REQ_LUT_BASE 19 1857 #define M_RTE_REQ_LUT_BASE 0x7FF 1858 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1859 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1860 1861 #define S_RTE_READ_REQ_SELECT 31 1862 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1863 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1864 1865 struct cpl_rte_delete_rpl { 1866 RSS_HDR 1867 union opcode_tid ot; 1868 __u8 status; 1869 __u8 rsvd[3]; 1870 }; 1871 1872 struct cpl_rte_write_req { 1873 WR_HDR; 1874 union opcode_tid ot; 1875 __u32 write_sel; 1876 __be32 lut_params; 1877 __be32 l2t_idx; 1878 __be32 netmask; 1879 __be32 faddr; 1880 }; 1881 1882 /* cpl_rte_write_req.write_sel fields */ 1883 #define S_RTE_WR_L2TIDX 31 1884 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1885 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1886 1887 #define S_RTE_WR_FADDR 30 1888 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1889 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1890 1891 /* cpl_rte_write_req.lut_params fields */ 1892 #define S_RTE_WR_LUT_IX 10 1893 #define M_RTE_WR_LUT_IX 0x7FF 1894 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1895 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1896 1897 #define S_RTE_WR_LUT_BASE 21 1898 #define M_RTE_WR_LUT_BASE 0x7FF 1899 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1900 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1901 1902 struct cpl_rte_write_rpl { 1903 RSS_HDR 1904 union opcode_tid ot; 1905 __u8 status; 1906 __u8 rsvd[3]; 1907 }; 1908 1909 struct cpl_rte_read_req { 1910 WR_HDR; 1911 union opcode_tid ot; 1912 __be32 params; 1913 }; 1914 1915 struct cpl_rte_read_rpl { 1916 RSS_HDR 1917 union opcode_tid ot; 1918 __u8 status; 1919 __u8 rsvd; 1920 __be16 l2t_idx; 1921 #if defined(__LITTLE_ENDIAN_BITFIELD) 1922 __u32 :30; 1923 __u32 select:1; 1924 #else 1925 __u32 select:1; 1926 __u32 :30; 1927 #endif 1928 __be32 addr; 1929 }; 1930 1931 struct cpl_l2t_write_req { 1932 WR_HDR; 1933 union opcode_tid ot; 1934 __be16 params; 1935 __be16 l2t_idx; 1936 __be16 vlan; 1937 __u8 dst_mac[6]; 1938 }; 1939 1940 /* cpl_l2t_write_req.params fields */ 1941 #define S_L2T_W_INFO 2 1942 #define M_L2T_W_INFO 0x3F 1943 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1944 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1945 1946 #define S_L2T_W_PORT 8 1947 #define M_L2T_W_PORT 0x3 1948 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1949 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1950 1951 #define S_L2T_W_LPBK 10 1952 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 1953 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 1954 1955 #define S_L2T_W_ARPMISS 11 1956 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 1957 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 1958 1959 #define S_L2T_W_NOREPLY 15 1960 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1961 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1962 1963 #define CPL_L2T_VLAN_NONE 0xfff 1964 1965 struct cpl_l2t_write_rpl { 1966 RSS_HDR 1967 union opcode_tid ot; 1968 __u8 status; 1969 __u8 rsvd[3]; 1970 }; 1971 1972 struct cpl_l2t_read_req { 1973 WR_HDR; 1974 union opcode_tid ot; 1975 __be32 l2t_idx; 1976 }; 1977 1978 struct cpl_l2t_read_rpl { 1979 RSS_HDR 1980 union opcode_tid ot; 1981 __u8 status; 1982 #if defined(__LITTLE_ENDIAN_BITFIELD) 1983 __u8 :4; 1984 __u8 iff:4; 1985 #else 1986 __u8 iff:4; 1987 __u8 :4; 1988 #endif 1989 __be16 vlan; 1990 __be16 info; 1991 __u8 dst_mac[6]; 1992 }; 1993 1994 struct cpl_smt_write_req { 1995 WR_HDR; 1996 union opcode_tid ot; 1997 __be32 params; 1998 __be16 pfvf1; 1999 __u8 src_mac1[6]; 2000 __be16 pfvf0; 2001 __u8 src_mac0[6]; 2002 }; 2003 2004 struct cpl_smt_write_rpl { 2005 RSS_HDR 2006 union opcode_tid ot; 2007 __u8 status; 2008 __u8 rsvd[3]; 2009 }; 2010 2011 struct cpl_smt_read_req { 2012 WR_HDR; 2013 union opcode_tid ot; 2014 __be32 params; 2015 }; 2016 2017 struct cpl_smt_read_rpl { 2018 RSS_HDR 2019 union opcode_tid ot; 2020 __u8 status; 2021 __u8 ovlan_idx; 2022 __be16 rsvd; 2023 __be16 pfvf1; 2024 __u8 src_mac1[6]; 2025 __be16 pfvf0; 2026 __u8 src_mac0[6]; 2027 }; 2028 2029 /* cpl_smt_{read,write}_req.params fields */ 2030 #define S_SMTW_OVLAN_IDX 16 2031 #define M_SMTW_OVLAN_IDX 0xF 2032 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2033 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2034 2035 #define S_SMTW_IDX 20 2036 #define M_SMTW_IDX 0x7F 2037 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2038 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2039 2040 #define S_SMTW_NORPL 31 2041 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2042 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2043 2044 /* cpl_smt_{read,write}_req.pfvf? fields */ 2045 #define S_SMTW_VF 0 2046 #define M_SMTW_VF 0xFF 2047 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2048 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2049 2050 #define S_SMTW_PF 8 2051 #define M_SMTW_PF 0x7 2052 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2053 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2054 2055 #define S_SMTW_VF_VLD 11 2056 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2057 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2058 2059 struct cpl_tag_write_req { 2060 WR_HDR; 2061 union opcode_tid ot; 2062 __be32 params; 2063 __be64 tag_val; 2064 }; 2065 2066 struct cpl_tag_write_rpl { 2067 2068 RSS_HDR 2069 union opcode_tid ot; 2070 __u8 status; 2071 __u8 rsvd[2]; 2072 __u8 idx; 2073 }; 2074 2075 struct cpl_tag_read_req { 2076 WR_HDR; 2077 union opcode_tid ot; 2078 __be32 params; 2079 }; 2080 2081 struct cpl_tag_read_rpl { 2082 RSS_HDR 2083 union opcode_tid ot; 2084 __u8 status; 2085 #if defined(__LITTLE_ENDIAN_BITFIELD) 2086 __u8 :4; 2087 __u8 tag_len:1; 2088 __u8 :2; 2089 __u8 ins_enable:1; 2090 #else 2091 __u8 ins_enable:1; 2092 __u8 :2; 2093 __u8 tag_len:1; 2094 __u8 :4; 2095 #endif 2096 __u8 rsvd; 2097 __u8 tag_idx; 2098 __be64 tag_val; 2099 }; 2100 2101 /* cpl_tag{read,write}_req.params fields */ 2102 #define S_TAGW_IDX 0 2103 #define M_TAGW_IDX 0x7F 2104 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2105 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2106 2107 #define S_TAGW_LEN 20 2108 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2109 #define F_TAGW_LEN V_TAGW_LEN(1U) 2110 2111 #define S_TAGW_INS_ENABLE 23 2112 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2113 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2114 2115 #define S_TAGW_NORPL 31 2116 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2117 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2118 2119 struct cpl_barrier { 2120 WR_HDR; 2121 __u8 opcode; 2122 __u8 chan_map; 2123 __be16 rsvd0; 2124 __be32 rsvd1; 2125 }; 2126 2127 /* cpl_barrier.chan_map fields */ 2128 #define S_CHAN_MAP 4 2129 #define M_CHAN_MAP 0xF 2130 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2131 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2132 2133 struct cpl_error { 2134 RSS_HDR 2135 union opcode_tid ot; 2136 __be32 error; 2137 }; 2138 2139 struct cpl_hit_notify { 2140 RSS_HDR 2141 union opcode_tid ot; 2142 __be32 rsvd; 2143 __be32 info; 2144 __be32 reason; 2145 }; 2146 2147 struct cpl_pkt_notify { 2148 RSS_HDR 2149 union opcode_tid ot; 2150 __be16 rsvd; 2151 __be16 len; 2152 __be32 info; 2153 __be32 reason; 2154 }; 2155 2156 /* cpl_{hit,pkt}_notify.info fields */ 2157 #define S_NTFY_MAC_IDX 0 2158 #define M_NTFY_MAC_IDX 0x1FF 2159 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2160 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2161 2162 #define S_NTFY_INTF 10 2163 #define M_NTFY_INTF 0xF 2164 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2165 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2166 2167 #define S_NTFY_TCPHDR_LEN 14 2168 #define M_NTFY_TCPHDR_LEN 0xF 2169 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2170 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2171 2172 #define S_NTFY_IPHDR_LEN 18 2173 #define M_NTFY_IPHDR_LEN 0x1FF 2174 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2175 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2176 2177 #define S_NTFY_ETHHDR_LEN 27 2178 #define M_NTFY_ETHHDR_LEN 0x1F 2179 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2180 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2181 2182 #define S_NTFY_T5_IPHDR_LEN 18 2183 #define M_NTFY_T5_IPHDR_LEN 0xFF 2184 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2185 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2186 2187 #define S_NTFY_T5_ETHHDR_LEN 26 2188 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2189 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2190 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2191 2192 struct cpl_rdma_terminate { 2193 RSS_HDR 2194 union opcode_tid ot; 2195 __be16 rsvd; 2196 __be16 len; 2197 }; 2198 2199 struct cpl_set_le_req { 2200 WR_HDR; 2201 union opcode_tid ot; 2202 __be16 reply_ctrl; 2203 __be16 params; 2204 __be64 mask_hi; 2205 __be64 mask_lo; 2206 __be64 val_hi; 2207 __be64 val_lo; 2208 }; 2209 2210 /* cpl_set_le_req.reply_ctrl additional fields */ 2211 #define S_LE_REQ_IP6 13 2212 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2213 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2214 2215 /* cpl_set_le_req.params fields */ 2216 #define S_LE_CHAN 0 2217 #define M_LE_CHAN 0x3 2218 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2219 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2220 2221 #define S_LE_OFFSET 5 2222 #define M_LE_OFFSET 0x7 2223 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2224 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2225 2226 #define S_LE_MORE 8 2227 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2228 #define F_LE_MORE V_LE_MORE(1U) 2229 2230 #define S_LE_REQSIZE 9 2231 #define M_LE_REQSIZE 0x7 2232 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2233 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2234 2235 #define S_LE_REQCMD 12 2236 #define M_LE_REQCMD 0xF 2237 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2238 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2239 2240 struct cpl_set_le_rpl { 2241 RSS_HDR 2242 union opcode_tid ot; 2243 __u8 chan; 2244 __u8 info; 2245 __be16 len; 2246 }; 2247 2248 /* cpl_set_le_rpl.info fields */ 2249 #define S_LE_RSPCMD 0 2250 #define M_LE_RSPCMD 0xF 2251 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2252 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2253 2254 #define S_LE_RSPSIZE 4 2255 #define M_LE_RSPSIZE 0x7 2256 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2257 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2258 2259 #define S_LE_RSPTYPE 7 2260 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2261 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2262 2263 struct cpl_sge_egr_update { 2264 RSS_HDR 2265 __be32 opcode_qid; 2266 __be16 cidx; 2267 __be16 pidx; 2268 }; 2269 2270 /* cpl_sge_egr_update.ot fields */ 2271 #define S_EGR_QID 0 2272 #define M_EGR_QID 0x1FFFF 2273 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2274 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2275 2276 /* cpl_fw*.type values */ 2277 enum { 2278 FW_TYPE_CMD_RPL = 0, 2279 FW_TYPE_WR_RPL = 1, 2280 FW_TYPE_CQE = 2, 2281 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2282 FW_TYPE_RSSCPL = 4, 2283 }; 2284 2285 struct cpl_fw2_pld { 2286 RSS_HDR 2287 u8 opcode; 2288 u8 rsvd[5]; 2289 __be16 len; 2290 }; 2291 2292 struct cpl_fw4_pld { 2293 RSS_HDR 2294 u8 opcode; 2295 u8 rsvd0[3]; 2296 u8 type; 2297 u8 rsvd1; 2298 __be16 len; 2299 __be64 data; 2300 __be64 rsvd2; 2301 }; 2302 2303 struct cpl_fw6_pld { 2304 RSS_HDR 2305 u8 opcode; 2306 u8 rsvd[5]; 2307 __be16 len; 2308 __be64 data[4]; 2309 }; 2310 2311 struct cpl_fw2_msg { 2312 RSS_HDR 2313 union opcode_info oi; 2314 }; 2315 2316 struct cpl_fw4_msg { 2317 RSS_HDR 2318 u8 opcode; 2319 u8 type; 2320 __be16 rsvd0; 2321 __be32 rsvd1; 2322 __be64 data[2]; 2323 }; 2324 2325 struct cpl_fw4_ack { 2326 RSS_HDR 2327 union opcode_tid ot; 2328 u8 credits; 2329 u8 rsvd0[2]; 2330 u8 flags; 2331 __be32 snd_nxt; 2332 __be32 snd_una; 2333 __be64 rsvd1; 2334 }; 2335 2336 enum { 2337 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2338 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2339 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2340 }; 2341 2342 struct cpl_fw6_msg { 2343 RSS_HDR 2344 u8 opcode; 2345 u8 type; 2346 __be16 rsvd0; 2347 __be32 rsvd1; 2348 __be64 data[4]; 2349 }; 2350 2351 /* cpl_fw6_msg.type values */ 2352 enum { 2353 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2354 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2355 FW6_TYPE_CQE = FW_TYPE_CQE, 2356 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2357 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2358 2359 NUM_FW6_TYPES 2360 }; 2361 2362 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2363 __u64 cookie; 2364 __be32 tid; /* or atid in case of active failure */ 2365 __u8 t_state; 2366 __u8 retval; 2367 __u8 rsvd[2]; 2368 }; 2369 2370 /* ULP_TX opcodes */ 2371 enum { 2372 ULP_TX_MEM_READ = 2, 2373 ULP_TX_MEM_WRITE = 3, 2374 ULP_TX_PKT = 4 2375 }; 2376 2377 enum { 2378 ULP_TX_SC_NOOP = 0x80, 2379 ULP_TX_SC_IMM = 0x81, 2380 ULP_TX_SC_DSGL = 0x82, 2381 ULP_TX_SC_ISGL = 0x83 2382 }; 2383 2384 #define S_ULPTX_CMD 24 2385 #define M_ULPTX_CMD 0xFF 2386 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2387 2388 #define S_ULPTX_LEN16 0 2389 #define M_ULPTX_LEN16 0xFF 2390 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2391 2392 #define S_ULP_TX_SC_MORE 23 2393 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2394 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2395 2396 struct ulptx_sge_pair { 2397 __be32 len[2]; 2398 __be64 addr[2]; 2399 }; 2400 2401 struct ulptx_sgl { 2402 __be32 cmd_nsge; 2403 __be32 len0; 2404 __be64 addr0; 2405 #if !(defined C99_NOT_SUPPORTED) 2406 struct ulptx_sge_pair sge[]; 2407 #endif 2408 }; 2409 2410 struct ulptx_isge { 2411 __be32 stag; 2412 __be32 len; 2413 __be64 target_ofst; 2414 }; 2415 2416 struct ulptx_isgl { 2417 __be32 cmd_nisge; 2418 __be32 rsvd; 2419 #if !(defined C99_NOT_SUPPORTED) 2420 struct ulptx_isge sge[]; 2421 #endif 2422 }; 2423 2424 struct ulptx_idata { 2425 __be32 cmd_more; 2426 __be32 len; 2427 }; 2428 2429 #define S_ULPTX_NSGE 0 2430 #define M_ULPTX_NSGE 0xFFFF 2431 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2432 2433 struct ulp_mem_io { 2434 WR_HDR; 2435 __be32 cmd; 2436 __be32 len16; /* command length */ 2437 __be32 dlen; /* data length in 32-byte units */ 2438 __be32 lock_addr; 2439 }; 2440 2441 /* additional ulp_mem_io.cmd fields */ 2442 #define S_ULP_MEMIO_ORDER 23 2443 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2444 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2445 2446 #define S_T5_ULP_MEMIO_IMM 23 2447 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2448 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2449 2450 #define S_T5_ULP_MEMIO_ORDER 22 2451 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2452 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2453 2454 /* ulp_mem_io.lock_addr fields */ 2455 #define S_ULP_MEMIO_ADDR 0 2456 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2457 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2458 2459 #define S_ULP_MEMIO_LOCK 31 2460 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2461 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2462 2463 /* ulp_mem_io.dlen fields */ 2464 #define S_ULP_MEMIO_DATA_LEN 0 2465 #define M_ULP_MEMIO_DATA_LEN 0x1F 2466 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2467 2468 /* ULP_TXPKT field values */ 2469 enum { 2470 ULP_TXPKT_DEST_TP = 0, 2471 ULP_TXPKT_DEST_SGE, 2472 ULP_TXPKT_DEST_UP, 2473 ULP_TXPKT_DEST_DEVNULL, 2474 }; 2475 2476 struct ulp_txpkt { 2477 __be32 cmd_dest; 2478 __be32 len; 2479 }; 2480 2481 /* ulp_txpkt.cmd_dest fields */ 2482 #define S_ULP_TXPKT_DEST 16 2483 #define M_ULP_TXPKT_DEST 0x3 2484 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2485 2486 #define S_ULP_TXPKT_FID 4 2487 #define M_ULP_TXPKT_FID 0x7ff 2488 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2489 2490 #define S_ULP_TXPKT_RO 3 2491 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2492 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2493 2494 #endif /* __CXGBE_T4_MSG_H */ 2495