1*56b2bdd1SGireesh Nagabhushana /* 2*56b2bdd1SGireesh Nagabhushana * This file and its contents are supplied under the terms of the 3*56b2bdd1SGireesh Nagabhushana * Common Development and Distribution License ("CDDL"), version 1.0. 4*56b2bdd1SGireesh Nagabhushana * You may only use this file in accordance with the terms of version 5*56b2bdd1SGireesh Nagabhushana * 1.0 of the CDDL. 6*56b2bdd1SGireesh Nagabhushana * 7*56b2bdd1SGireesh Nagabhushana * A full copy of the text of the CDDL should have accompanied this 8*56b2bdd1SGireesh Nagabhushana * source. A copy of the CDDL is also available via the Internet at 9*56b2bdd1SGireesh Nagabhushana * http://www.illumos.org/license/CDDL. 10*56b2bdd1SGireesh Nagabhushana */ 11*56b2bdd1SGireesh Nagabhushana 12*56b2bdd1SGireesh Nagabhushana /* 13*56b2bdd1SGireesh Nagabhushana * Definitions of T4 work request and CPL5 commands and status codes. 14*56b2bdd1SGireesh Nagabhushana * 15*56b2bdd1SGireesh Nagabhushana * Copyright (C) 2008-2013 Chelsio Communications. All rights reserved. 16*56b2bdd1SGireesh Nagabhushana * 17*56b2bdd1SGireesh Nagabhushana * Written by Dimitris Michailidis (dm@chelsio.com) 18*56b2bdd1SGireesh Nagabhushana * 19*56b2bdd1SGireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT 20*56b2bdd1SGireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21*56b2bdd1SGireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 22*56b2bdd1SGireesh Nagabhushana * release for licensing terms and conditions. 23*56b2bdd1SGireesh Nagabhushana */ 24*56b2bdd1SGireesh Nagabhushana 25*56b2bdd1SGireesh Nagabhushana #ifndef __CXGBE_T4_MSG_H 26*56b2bdd1SGireesh Nagabhushana #define __CXGBE_T4_MSG_H 27*56b2bdd1SGireesh Nagabhushana 28*56b2bdd1SGireesh Nagabhushana enum { 29*56b2bdd1SGireesh Nagabhushana CPL_PASS_OPEN_REQ = 0x1, 30*56b2bdd1SGireesh Nagabhushana CPL_PASS_ACCEPT_RPL = 0x2, 31*56b2bdd1SGireesh Nagabhushana CPL_ACT_OPEN_REQ = 0x3, 32*56b2bdd1SGireesh Nagabhushana CPL_SET_TCB = 0x4, 33*56b2bdd1SGireesh Nagabhushana CPL_SET_TCB_FIELD = 0x5, 34*56b2bdd1SGireesh Nagabhushana CPL_GET_TCB = 0x6, 35*56b2bdd1SGireesh Nagabhushana CPL_PCMD = 0x7, 36*56b2bdd1SGireesh Nagabhushana CPL_CLOSE_CON_REQ = 0x8, 37*56b2bdd1SGireesh Nagabhushana CPL_CLOSE_LISTSRV_REQ = 0x9, 38*56b2bdd1SGireesh Nagabhushana CPL_ABORT_REQ = 0xA, 39*56b2bdd1SGireesh Nagabhushana CPL_ABORT_RPL = 0xB, 40*56b2bdd1SGireesh Nagabhushana CPL_TX_DATA = 0xC, 41*56b2bdd1SGireesh Nagabhushana CPL_RX_DATA_ACK = 0xD, 42*56b2bdd1SGireesh Nagabhushana CPL_TX_PKT = 0xE, 43*56b2bdd1SGireesh Nagabhushana CPL_RTE_DELETE_REQ = 0xF, 44*56b2bdd1SGireesh Nagabhushana CPL_RTE_WRITE_REQ = 0x10, 45*56b2bdd1SGireesh Nagabhushana CPL_RTE_READ_REQ = 0x11, 46*56b2bdd1SGireesh Nagabhushana CPL_L2T_WRITE_REQ = 0x12, 47*56b2bdd1SGireesh Nagabhushana CPL_L2T_READ_REQ = 0x13, 48*56b2bdd1SGireesh Nagabhushana CPL_SMT_WRITE_REQ = 0x14, 49*56b2bdd1SGireesh Nagabhushana CPL_SMT_READ_REQ = 0x15, 50*56b2bdd1SGireesh Nagabhushana CPL_BARRIER = 0x18, 51*56b2bdd1SGireesh Nagabhushana CPL_TID_RELEASE = 0x1A, 52*56b2bdd1SGireesh Nagabhushana CPL_RX_MPS_PKT = 0x1B, 53*56b2bdd1SGireesh Nagabhushana 54*56b2bdd1SGireesh Nagabhushana CPL_CLOSE_LISTSRV_RPL = 0x20, 55*56b2bdd1SGireesh Nagabhushana CPL_ERROR = 0x21, 56*56b2bdd1SGireesh Nagabhushana CPL_GET_TCB_RPL = 0x22, 57*56b2bdd1SGireesh Nagabhushana CPL_L2T_WRITE_RPL = 0x23, 58*56b2bdd1SGireesh Nagabhushana CPL_PASS_OPEN_RPL = 0x24, 59*56b2bdd1SGireesh Nagabhushana CPL_ACT_OPEN_RPL = 0x25, 60*56b2bdd1SGireesh Nagabhushana CPL_PEER_CLOSE = 0x26, 61*56b2bdd1SGireesh Nagabhushana CPL_RTE_DELETE_RPL = 0x27, 62*56b2bdd1SGireesh Nagabhushana CPL_RTE_WRITE_RPL = 0x28, 63*56b2bdd1SGireesh Nagabhushana CPL_RX_URG_PKT = 0x29, 64*56b2bdd1SGireesh Nagabhushana CPL_ABORT_REQ_RSS = 0x2B, 65*56b2bdd1SGireesh Nagabhushana CPL_RX_URG_NOTIFY = 0x2C, 66*56b2bdd1SGireesh Nagabhushana CPL_ABORT_RPL_RSS = 0x2D, 67*56b2bdd1SGireesh Nagabhushana CPL_SMT_WRITE_RPL = 0x2E, 68*56b2bdd1SGireesh Nagabhushana CPL_TX_DATA_ACK = 0x2F, 69*56b2bdd1SGireesh Nagabhushana 70*56b2bdd1SGireesh Nagabhushana CPL_RX_PHYS_ADDR = 0x30, 71*56b2bdd1SGireesh Nagabhushana CPL_PCMD_READ_RPL = 0x31, 72*56b2bdd1SGireesh Nagabhushana CPL_CLOSE_CON_RPL = 0x32, 73*56b2bdd1SGireesh Nagabhushana CPL_ISCSI_HDR = 0x33, 74*56b2bdd1SGireesh Nagabhushana CPL_L2T_READ_RPL = 0x34, 75*56b2bdd1SGireesh Nagabhushana CPL_RDMA_CQE = 0x35, 76*56b2bdd1SGireesh Nagabhushana CPL_RDMA_CQE_READ_RSP = 0x36, 77*56b2bdd1SGireesh Nagabhushana CPL_RDMA_CQE_ERR = 0x37, 78*56b2bdd1SGireesh Nagabhushana CPL_RTE_READ_RPL = 0x38, 79*56b2bdd1SGireesh Nagabhushana CPL_RX_DATA = 0x39, 80*56b2bdd1SGireesh Nagabhushana CPL_SET_TCB_RPL = 0x3A, 81*56b2bdd1SGireesh Nagabhushana CPL_RX_PKT = 0x3B, 82*56b2bdd1SGireesh Nagabhushana CPL_PCMD_RPL = 0x3C, 83*56b2bdd1SGireesh Nagabhushana CPL_HIT_NOTIFY = 0x3D, 84*56b2bdd1SGireesh Nagabhushana CPL_PKT_NOTIFY = 0x3E, 85*56b2bdd1SGireesh Nagabhushana CPL_RX_DDP_COMPLETE = 0x3F, 86*56b2bdd1SGireesh Nagabhushana 87*56b2bdd1SGireesh Nagabhushana CPL_ACT_ESTABLISH = 0x40, 88*56b2bdd1SGireesh Nagabhushana CPL_PASS_ESTABLISH = 0x41, 89*56b2bdd1SGireesh Nagabhushana CPL_RX_DATA_DDP = 0x42, 90*56b2bdd1SGireesh Nagabhushana CPL_SMT_READ_RPL = 0x43, 91*56b2bdd1SGireesh Nagabhushana CPL_PASS_ACCEPT_REQ = 0x44, 92*56b2bdd1SGireesh Nagabhushana CPL_RX2TX_PKT = 0x45, 93*56b2bdd1SGireesh Nagabhushana CPL_RX_FCOE_DDP = 0x46, 94*56b2bdd1SGireesh Nagabhushana CPL_FCOE_HDR = 0x47, 95*56b2bdd1SGireesh Nagabhushana 96*56b2bdd1SGireesh Nagabhushana CPL_RDMA_READ_REQ = 0x60, 97*56b2bdd1SGireesh Nagabhushana 98*56b2bdd1SGireesh Nagabhushana CPL_SET_LE_REQ = 0x80, 99*56b2bdd1SGireesh Nagabhushana CPL_PASS_OPEN_REQ6 = 0x81, 100*56b2bdd1SGireesh Nagabhushana CPL_ACT_OPEN_REQ6 = 0x83, 101*56b2bdd1SGireesh Nagabhushana 102*56b2bdd1SGireesh Nagabhushana CPL_TX_DMA_ACK = 0xA0, 103*56b2bdd1SGireesh Nagabhushana CPL_RDMA_TERMINATE = 0xA2, 104*56b2bdd1SGireesh Nagabhushana CPL_RDMA_WRITE = 0xA4, 105*56b2bdd1SGireesh Nagabhushana CPL_SGE_EGR_UPDATE = 0xA5, 106*56b2bdd1SGireesh Nagabhushana CPL_SET_LE_RPL = 0xA6, 107*56b2bdd1SGireesh Nagabhushana CPL_FW2_MSG = 0xA7, 108*56b2bdd1SGireesh Nagabhushana CPL_FW2_PLD = 0xA8, 109*56b2bdd1SGireesh Nagabhushana 110*56b2bdd1SGireesh Nagabhushana CPL_TRACE_PKT = 0xB0, 111*56b2bdd1SGireesh Nagabhushana CPL_RX2TX_DATA = 0xB1, 112*56b2bdd1SGireesh Nagabhushana 113*56b2bdd1SGireesh Nagabhushana CPL_FW4_MSG = 0xC0, 114*56b2bdd1SGireesh Nagabhushana CPL_FW4_PLD = 0xC1, 115*56b2bdd1SGireesh Nagabhushana CPL_FW4_ACK = 0xC3, 116*56b2bdd1SGireesh Nagabhushana 117*56b2bdd1SGireesh Nagabhushana CPL_FW6_MSG = 0xE0, 118*56b2bdd1SGireesh Nagabhushana CPL_FW6_PLD = 0xE1, 119*56b2bdd1SGireesh Nagabhushana CPL_TX_PKT_LSO = 0xED, 120*56b2bdd1SGireesh Nagabhushana CPL_TX_PKT_XT = 0xEE, 121*56b2bdd1SGireesh Nagabhushana 122*56b2bdd1SGireesh Nagabhushana NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 123*56b2bdd1SGireesh Nagabhushana }; 124*56b2bdd1SGireesh Nagabhushana 125*56b2bdd1SGireesh Nagabhushana enum CPL_error { 126*56b2bdd1SGireesh Nagabhushana CPL_ERR_NONE = 0, 127*56b2bdd1SGireesh Nagabhushana CPL_ERR_TCAM_PARITY = 1, 128*56b2bdd1SGireesh Nagabhushana CPL_ERR_TCAM_FULL = 3, 129*56b2bdd1SGireesh Nagabhushana CPL_ERR_BAD_LENGTH = 15, 130*56b2bdd1SGireesh Nagabhushana CPL_ERR_BAD_ROUTE = 18, 131*56b2bdd1SGireesh Nagabhushana CPL_ERR_CONN_RESET = 20, 132*56b2bdd1SGireesh Nagabhushana CPL_ERR_CONN_EXIST_SYNRECV = 21, 133*56b2bdd1SGireesh Nagabhushana CPL_ERR_CONN_EXIST = 22, 134*56b2bdd1SGireesh Nagabhushana CPL_ERR_ARP_MISS = 23, 135*56b2bdd1SGireesh Nagabhushana CPL_ERR_BAD_SYN = 24, 136*56b2bdd1SGireesh Nagabhushana CPL_ERR_CONN_TIMEDOUT = 30, 137*56b2bdd1SGireesh Nagabhushana CPL_ERR_XMIT_TIMEDOUT = 31, 138*56b2bdd1SGireesh Nagabhushana CPL_ERR_PERSIST_TIMEDOUT = 32, 139*56b2bdd1SGireesh Nagabhushana CPL_ERR_FINWAIT2_TIMEDOUT = 33, 140*56b2bdd1SGireesh Nagabhushana CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 141*56b2bdd1SGireesh Nagabhushana CPL_ERR_RTX_NEG_ADVICE = 35, 142*56b2bdd1SGireesh Nagabhushana CPL_ERR_PERSIST_NEG_ADVICE = 36, 143*56b2bdd1SGireesh Nagabhushana CPL_ERR_KEEPALV_NEG_ADVICE = 37, 144*56b2bdd1SGireesh Nagabhushana CPL_ERR_WAIT_ARP_RPL = 41, 145*56b2bdd1SGireesh Nagabhushana CPL_ERR_ABORT_FAILED = 42, 146*56b2bdd1SGireesh Nagabhushana CPL_ERR_IWARP_FLM = 50, 147*56b2bdd1SGireesh Nagabhushana }; 148*56b2bdd1SGireesh Nagabhushana 149*56b2bdd1SGireesh Nagabhushana enum { 150*56b2bdd1SGireesh Nagabhushana CPL_CONN_POLICY_AUTO = 0, 151*56b2bdd1SGireesh Nagabhushana CPL_CONN_POLICY_ASK = 1, 152*56b2bdd1SGireesh Nagabhushana CPL_CONN_POLICY_FILTER = 2, 153*56b2bdd1SGireesh Nagabhushana CPL_CONN_POLICY_DENY = 3 154*56b2bdd1SGireesh Nagabhushana }; 155*56b2bdd1SGireesh Nagabhushana 156*56b2bdd1SGireesh Nagabhushana enum { 157*56b2bdd1SGireesh Nagabhushana ULP_MODE_NONE = 0, 158*56b2bdd1SGireesh Nagabhushana ULP_MODE_ISCSI = 2, 159*56b2bdd1SGireesh Nagabhushana ULP_MODE_RDMA = 4, 160*56b2bdd1SGireesh Nagabhushana ULP_MODE_TCPDDP = 5, 161*56b2bdd1SGireesh Nagabhushana ULP_MODE_FCOE = 6, 162*56b2bdd1SGireesh Nagabhushana }; 163*56b2bdd1SGireesh Nagabhushana 164*56b2bdd1SGireesh Nagabhushana enum { 165*56b2bdd1SGireesh Nagabhushana ULP_CRC_HEADER = 1 << 0, 166*56b2bdd1SGireesh Nagabhushana ULP_CRC_DATA = 1 << 1 167*56b2bdd1SGireesh Nagabhushana }; 168*56b2bdd1SGireesh Nagabhushana 169*56b2bdd1SGireesh Nagabhushana enum { 170*56b2bdd1SGireesh Nagabhushana CPL_PASS_OPEN_ACCEPT, 171*56b2bdd1SGireesh Nagabhushana CPL_PASS_OPEN_REJECT, 172*56b2bdd1SGireesh Nagabhushana CPL_PASS_OPEN_ACCEPT_TNL 173*56b2bdd1SGireesh Nagabhushana }; 174*56b2bdd1SGireesh Nagabhushana 175*56b2bdd1SGireesh Nagabhushana enum { 176*56b2bdd1SGireesh Nagabhushana CPL_ABORT_SEND_RST = 0, 177*56b2bdd1SGireesh Nagabhushana CPL_ABORT_NO_RST, 178*56b2bdd1SGireesh Nagabhushana }; 179*56b2bdd1SGireesh Nagabhushana 180*56b2bdd1SGireesh Nagabhushana enum { /* TX_PKT_XT checksum types */ 181*56b2bdd1SGireesh Nagabhushana TX_CSUM_TCP = 0, 182*56b2bdd1SGireesh Nagabhushana TX_CSUM_UDP = 1, 183*56b2bdd1SGireesh Nagabhushana TX_CSUM_CRC16 = 4, 184*56b2bdd1SGireesh Nagabhushana TX_CSUM_CRC32 = 5, 185*56b2bdd1SGireesh Nagabhushana TX_CSUM_CRC32C = 6, 186*56b2bdd1SGireesh Nagabhushana TX_CSUM_FCOE = 7, 187*56b2bdd1SGireesh Nagabhushana TX_CSUM_TCPIP = 8, 188*56b2bdd1SGireesh Nagabhushana TX_CSUM_UDPIP = 9, 189*56b2bdd1SGireesh Nagabhushana TX_CSUM_TCPIP6 = 10, 190*56b2bdd1SGireesh Nagabhushana TX_CSUM_UDPIP6 = 11, 191*56b2bdd1SGireesh Nagabhushana TX_CSUM_IP = 12, 192*56b2bdd1SGireesh Nagabhushana }; 193*56b2bdd1SGireesh Nagabhushana 194*56b2bdd1SGireesh Nagabhushana enum { /* packet type in CPL_RX_PKT */ 195*56b2bdd1SGireesh Nagabhushana PKTYPE_XACT_UCAST = 0, 196*56b2bdd1SGireesh Nagabhushana PKTYPE_HASH_UCAST = 1, 197*56b2bdd1SGireesh Nagabhushana PKTYPE_XACT_MCAST = 2, 198*56b2bdd1SGireesh Nagabhushana PKTYPE_HASH_MCAST = 3, 199*56b2bdd1SGireesh Nagabhushana PKTYPE_PROMISC = 4, 200*56b2bdd1SGireesh Nagabhushana PKTYPE_HPROMISC = 5, 201*56b2bdd1SGireesh Nagabhushana PKTYPE_BCAST = 6 202*56b2bdd1SGireesh Nagabhushana }; 203*56b2bdd1SGireesh Nagabhushana 204*56b2bdd1SGireesh Nagabhushana enum { /* DMAC type in CPL_RX_PKT */ 205*56b2bdd1SGireesh Nagabhushana DATYPE_UCAST, 206*56b2bdd1SGireesh Nagabhushana DATYPE_MCAST, 207*56b2bdd1SGireesh Nagabhushana DATYPE_BCAST 208*56b2bdd1SGireesh Nagabhushana }; 209*56b2bdd1SGireesh Nagabhushana 210*56b2bdd1SGireesh Nagabhushana enum { /* TCP congestion control algorithms */ 211*56b2bdd1SGireesh Nagabhushana CONG_ALG_RENO, 212*56b2bdd1SGireesh Nagabhushana CONG_ALG_TAHOE, 213*56b2bdd1SGireesh Nagabhushana CONG_ALG_NEWRENO, 214*56b2bdd1SGireesh Nagabhushana CONG_ALG_HIGHSPEED 215*56b2bdd1SGireesh Nagabhushana }; 216*56b2bdd1SGireesh Nagabhushana 217*56b2bdd1SGireesh Nagabhushana enum { /* RSS hash type */ 218*56b2bdd1SGireesh Nagabhushana RSS_HASH_NONE = 0, /* no hash computed */ 219*56b2bdd1SGireesh Nagabhushana RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 220*56b2bdd1SGireesh Nagabhushana RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 221*56b2bdd1SGireesh Nagabhushana RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 222*56b2bdd1SGireesh Nagabhushana }; 223*56b2bdd1SGireesh Nagabhushana 224*56b2bdd1SGireesh Nagabhushana enum { /* LE commands */ 225*56b2bdd1SGireesh Nagabhushana LE_CMD_READ = 0x4, 226*56b2bdd1SGireesh Nagabhushana LE_CMD_WRITE = 0xb 227*56b2bdd1SGireesh Nagabhushana }; 228*56b2bdd1SGireesh Nagabhushana 229*56b2bdd1SGireesh Nagabhushana enum { /* LE request size */ 230*56b2bdd1SGireesh Nagabhushana LE_SZ_NONE = 0, 231*56b2bdd1SGireesh Nagabhushana LE_SZ_33 = 1, 232*56b2bdd1SGireesh Nagabhushana LE_SZ_66 = 2, 233*56b2bdd1SGireesh Nagabhushana LE_SZ_132 = 3, 234*56b2bdd1SGireesh Nagabhushana LE_SZ_264 = 4, 235*56b2bdd1SGireesh Nagabhushana LE_SZ_528 = 5 236*56b2bdd1SGireesh Nagabhushana }; 237*56b2bdd1SGireesh Nagabhushana 238*56b2bdd1SGireesh Nagabhushana union opcode_tid { 239*56b2bdd1SGireesh Nagabhushana __be32 opcode_tid; 240*56b2bdd1SGireesh Nagabhushana __u8 opcode; 241*56b2bdd1SGireesh Nagabhushana }; 242*56b2bdd1SGireesh Nagabhushana 243*56b2bdd1SGireesh Nagabhushana #define S_CPL_OPCODE 24 244*56b2bdd1SGireesh Nagabhushana #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 245*56b2bdd1SGireesh Nagabhushana #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 246*56b2bdd1SGireesh Nagabhushana #define G_TID(x) ((x) & 0xFFFFFF) 247*56b2bdd1SGireesh Nagabhushana 248*56b2bdd1SGireesh Nagabhushana /* tid is assumed to be 24-bits */ 249*56b2bdd1SGireesh Nagabhushana #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 250*56b2bdd1SGireesh Nagabhushana 251*56b2bdd1SGireesh Nagabhushana #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 252*56b2bdd1SGireesh Nagabhushana 253*56b2bdd1SGireesh Nagabhushana /* extract the TID from a CPL command */ 254*56b2bdd1SGireesh Nagabhushana #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 255*56b2bdd1SGireesh Nagabhushana 256*56b2bdd1SGireesh Nagabhushana /* partitioning of TID fields that also carry a queue id */ 257*56b2bdd1SGireesh Nagabhushana #define S_TID_TID 0 258*56b2bdd1SGireesh Nagabhushana #define M_TID_TID 0x3fff 259*56b2bdd1SGireesh Nagabhushana #define V_TID_TID(x) ((x) << S_TID_TID) 260*56b2bdd1SGireesh Nagabhushana #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 261*56b2bdd1SGireesh Nagabhushana 262*56b2bdd1SGireesh Nagabhushana #define S_TID_QID 14 263*56b2bdd1SGireesh Nagabhushana #define M_TID_QID 0x3ff 264*56b2bdd1SGireesh Nagabhushana #define V_TID_QID(x) ((x) << S_TID_QID) 265*56b2bdd1SGireesh Nagabhushana #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 266*56b2bdd1SGireesh Nagabhushana 267*56b2bdd1SGireesh Nagabhushana union opcode_info { 268*56b2bdd1SGireesh Nagabhushana __be64 opcode_info; 269*56b2bdd1SGireesh Nagabhushana __u8 opcode; 270*56b2bdd1SGireesh Nagabhushana }; 271*56b2bdd1SGireesh Nagabhushana 272*56b2bdd1SGireesh Nagabhushana struct tcp_options { 273*56b2bdd1SGireesh Nagabhushana __be16 mss; 274*56b2bdd1SGireesh Nagabhushana __u8 wsf; 275*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 276*56b2bdd1SGireesh Nagabhushana __u8 :4; 277*56b2bdd1SGireesh Nagabhushana __u8 unknown:1; 278*56b2bdd1SGireesh Nagabhushana __u8 :1; 279*56b2bdd1SGireesh Nagabhushana __u8 sack:1; 280*56b2bdd1SGireesh Nagabhushana __u8 tstamp:1; 281*56b2bdd1SGireesh Nagabhushana #else 282*56b2bdd1SGireesh Nagabhushana __u8 tstamp:1; 283*56b2bdd1SGireesh Nagabhushana __u8 sack:1; 284*56b2bdd1SGireesh Nagabhushana __u8 :1; 285*56b2bdd1SGireesh Nagabhushana __u8 unknown:1; 286*56b2bdd1SGireesh Nagabhushana __u8 :4; 287*56b2bdd1SGireesh Nagabhushana #endif 288*56b2bdd1SGireesh Nagabhushana }; 289*56b2bdd1SGireesh Nagabhushana 290*56b2bdd1SGireesh Nagabhushana struct rss_header { 291*56b2bdd1SGireesh Nagabhushana __u8 opcode; 292*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 293*56b2bdd1SGireesh Nagabhushana __u8 channel:2; 294*56b2bdd1SGireesh Nagabhushana __u8 filter_hit:1; 295*56b2bdd1SGireesh Nagabhushana __u8 filter_tid:1; 296*56b2bdd1SGireesh Nagabhushana __u8 hash_type:2; 297*56b2bdd1SGireesh Nagabhushana __u8 ipv6:1; 298*56b2bdd1SGireesh Nagabhushana __u8 send2fw:1; 299*56b2bdd1SGireesh Nagabhushana #else 300*56b2bdd1SGireesh Nagabhushana __u8 send2fw:1; 301*56b2bdd1SGireesh Nagabhushana __u8 ipv6:1; 302*56b2bdd1SGireesh Nagabhushana __u8 hash_type:2; 303*56b2bdd1SGireesh Nagabhushana __u8 filter_tid:1; 304*56b2bdd1SGireesh Nagabhushana __u8 filter_hit:1; 305*56b2bdd1SGireesh Nagabhushana __u8 channel:2; 306*56b2bdd1SGireesh Nagabhushana #endif 307*56b2bdd1SGireesh Nagabhushana __be16 qid; 308*56b2bdd1SGireesh Nagabhushana __be32 hash_val; 309*56b2bdd1SGireesh Nagabhushana }; 310*56b2bdd1SGireesh Nagabhushana 311*56b2bdd1SGireesh Nagabhushana #define S_HASHTYPE 20 312*56b2bdd1SGireesh Nagabhushana #define M_HASHTYPE 0x3 313*56b2bdd1SGireesh Nagabhushana #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 314*56b2bdd1SGireesh Nagabhushana 315*56b2bdd1SGireesh Nagabhushana #define S_QNUM 0 316*56b2bdd1SGireesh Nagabhushana #define M_QNUM 0xFFFF 317*56b2bdd1SGireesh Nagabhushana #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 318*56b2bdd1SGireesh Nagabhushana 319*56b2bdd1SGireesh Nagabhushana #ifndef CHELSIO_FW 320*56b2bdd1SGireesh Nagabhushana struct work_request_hdr { 321*56b2bdd1SGireesh Nagabhushana __be32 wr_hi; 322*56b2bdd1SGireesh Nagabhushana __be32 wr_mid; 323*56b2bdd1SGireesh Nagabhushana __be64 wr_lo; 324*56b2bdd1SGireesh Nagabhushana }; 325*56b2bdd1SGireesh Nagabhushana 326*56b2bdd1SGireesh Nagabhushana /* wr_mid fields */ 327*56b2bdd1SGireesh Nagabhushana #define S_WR_LEN16 0 328*56b2bdd1SGireesh Nagabhushana #define M_WR_LEN16 0xFF 329*56b2bdd1SGireesh Nagabhushana #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 330*56b2bdd1SGireesh Nagabhushana #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 331*56b2bdd1SGireesh Nagabhushana 332*56b2bdd1SGireesh Nagabhushana /* wr_hi fields */ 333*56b2bdd1SGireesh Nagabhushana #define S_WR_OP 24 334*56b2bdd1SGireesh Nagabhushana #define M_WR_OP 0xFF 335*56b2bdd1SGireesh Nagabhushana #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 336*56b2bdd1SGireesh Nagabhushana #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 337*56b2bdd1SGireesh Nagabhushana 338*56b2bdd1SGireesh Nagabhushana #define WR_HDR struct work_request_hdr wr 339*56b2bdd1SGireesh Nagabhushana #define WR_HDR_SIZE sizeof (struct work_request_hdr) 340*56b2bdd1SGireesh Nagabhushana #define RSS_HDR 341*56b2bdd1SGireesh Nagabhushana #else 342*56b2bdd1SGireesh Nagabhushana #define WR_HDR 343*56b2bdd1SGireesh Nagabhushana #define WR_HDR_SIZE 0 344*56b2bdd1SGireesh Nagabhushana #define RSS_HDR struct rss_header rss_hdr; 345*56b2bdd1SGireesh Nagabhushana #endif 346*56b2bdd1SGireesh Nagabhushana 347*56b2bdd1SGireesh Nagabhushana /* option 0 fields */ 348*56b2bdd1SGireesh Nagabhushana #define S_ACCEPT_MODE 0 349*56b2bdd1SGireesh Nagabhushana #define M_ACCEPT_MODE 0x3 350*56b2bdd1SGireesh Nagabhushana #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 351*56b2bdd1SGireesh Nagabhushana #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 352*56b2bdd1SGireesh Nagabhushana 353*56b2bdd1SGireesh Nagabhushana #define S_TX_CHAN 2 354*56b2bdd1SGireesh Nagabhushana #define M_TX_CHAN 0x3 355*56b2bdd1SGireesh Nagabhushana #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 356*56b2bdd1SGireesh Nagabhushana #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 357*56b2bdd1SGireesh Nagabhushana 358*56b2bdd1SGireesh Nagabhushana #define S_NO_CONG 4 359*56b2bdd1SGireesh Nagabhushana #define V_NO_CONG(x) ((x) << S_NO_CONG) 360*56b2bdd1SGireesh Nagabhushana #define F_NO_CONG V_NO_CONG(1U) 361*56b2bdd1SGireesh Nagabhushana 362*56b2bdd1SGireesh Nagabhushana #define S_DELACK 5 363*56b2bdd1SGireesh Nagabhushana #define V_DELACK(x) ((x) << S_DELACK) 364*56b2bdd1SGireesh Nagabhushana #define F_DELACK V_DELACK(1U) 365*56b2bdd1SGireesh Nagabhushana 366*56b2bdd1SGireesh Nagabhushana #define S_INJECT_TIMER 6 367*56b2bdd1SGireesh Nagabhushana #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 368*56b2bdd1SGireesh Nagabhushana #define F_INJECT_TIMER V_INJECT_TIMER(1U) 369*56b2bdd1SGireesh Nagabhushana 370*56b2bdd1SGireesh Nagabhushana #define S_NON_OFFLOAD 7 371*56b2bdd1SGireesh Nagabhushana #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 372*56b2bdd1SGireesh Nagabhushana #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 373*56b2bdd1SGireesh Nagabhushana 374*56b2bdd1SGireesh Nagabhushana #define S_ULP_MODE 8 375*56b2bdd1SGireesh Nagabhushana #define M_ULP_MODE 0xF 376*56b2bdd1SGireesh Nagabhushana #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 377*56b2bdd1SGireesh Nagabhushana #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 378*56b2bdd1SGireesh Nagabhushana 379*56b2bdd1SGireesh Nagabhushana #define S_RCV_BUFSIZ 12 380*56b2bdd1SGireesh Nagabhushana #define M_RCV_BUFSIZ 0x3FFU 381*56b2bdd1SGireesh Nagabhushana #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 382*56b2bdd1SGireesh Nagabhushana #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 383*56b2bdd1SGireesh Nagabhushana 384*56b2bdd1SGireesh Nagabhushana #define S_DSCP 22 385*56b2bdd1SGireesh Nagabhushana #define M_DSCP 0x3F 386*56b2bdd1SGireesh Nagabhushana #define V_DSCP(x) ((x) << S_DSCP) 387*56b2bdd1SGireesh Nagabhushana #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 388*56b2bdd1SGireesh Nagabhushana 389*56b2bdd1SGireesh Nagabhushana #define S_SMAC_SEL 28 390*56b2bdd1SGireesh Nagabhushana #define M_SMAC_SEL 0xFF 391*56b2bdd1SGireesh Nagabhushana #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 392*56b2bdd1SGireesh Nagabhushana #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 393*56b2bdd1SGireesh Nagabhushana 394*56b2bdd1SGireesh Nagabhushana #define S_L2T_IDX 36 395*56b2bdd1SGireesh Nagabhushana #define M_L2T_IDX 0xFFF 396*56b2bdd1SGireesh Nagabhushana #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 397*56b2bdd1SGireesh Nagabhushana #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 398*56b2bdd1SGireesh Nagabhushana 399*56b2bdd1SGireesh Nagabhushana #define S_TCAM_BYPASS 48 400*56b2bdd1SGireesh Nagabhushana #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 401*56b2bdd1SGireesh Nagabhushana #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 402*56b2bdd1SGireesh Nagabhushana 403*56b2bdd1SGireesh Nagabhushana #define S_NAGLE 49 404*56b2bdd1SGireesh Nagabhushana #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 405*56b2bdd1SGireesh Nagabhushana #define F_NAGLE V_NAGLE(1ULL) 406*56b2bdd1SGireesh Nagabhushana 407*56b2bdd1SGireesh Nagabhushana #define S_WND_SCALE 50 408*56b2bdd1SGireesh Nagabhushana #define M_WND_SCALE 0xF 409*56b2bdd1SGireesh Nagabhushana #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 410*56b2bdd1SGireesh Nagabhushana #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 411*56b2bdd1SGireesh Nagabhushana 412*56b2bdd1SGireesh Nagabhushana #define S_KEEP_ALIVE 54 413*56b2bdd1SGireesh Nagabhushana #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 414*56b2bdd1SGireesh Nagabhushana #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 415*56b2bdd1SGireesh Nagabhushana 416*56b2bdd1SGireesh Nagabhushana #define S_MAX_RT 55 417*56b2bdd1SGireesh Nagabhushana #define M_MAX_RT 0xF 418*56b2bdd1SGireesh Nagabhushana #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 419*56b2bdd1SGireesh Nagabhushana #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 420*56b2bdd1SGireesh Nagabhushana 421*56b2bdd1SGireesh Nagabhushana #define S_MAX_RT_OVERRIDE 59 422*56b2bdd1SGireesh Nagabhushana #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 423*56b2bdd1SGireesh Nagabhushana #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 424*56b2bdd1SGireesh Nagabhushana 425*56b2bdd1SGireesh Nagabhushana #define S_MSS_IDX 60 426*56b2bdd1SGireesh Nagabhushana #define M_MSS_IDX 0xF 427*56b2bdd1SGireesh Nagabhushana #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 428*56b2bdd1SGireesh Nagabhushana #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 429*56b2bdd1SGireesh Nagabhushana 430*56b2bdd1SGireesh Nagabhushana /* option 1 fields */ 431*56b2bdd1SGireesh Nagabhushana #define S_SYN_RSS_ENABLE 0 432*56b2bdd1SGireesh Nagabhushana #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 433*56b2bdd1SGireesh Nagabhushana #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 434*56b2bdd1SGireesh Nagabhushana 435*56b2bdd1SGireesh Nagabhushana #define S_SYN_RSS_USE_HASH 1 436*56b2bdd1SGireesh Nagabhushana #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 437*56b2bdd1SGireesh Nagabhushana #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 438*56b2bdd1SGireesh Nagabhushana 439*56b2bdd1SGireesh Nagabhushana #define S_SYN_RSS_QUEUE 2 440*56b2bdd1SGireesh Nagabhushana #define M_SYN_RSS_QUEUE 0x3FF 441*56b2bdd1SGireesh Nagabhushana #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 442*56b2bdd1SGireesh Nagabhushana #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 443*56b2bdd1SGireesh Nagabhushana 444*56b2bdd1SGireesh Nagabhushana #define S_LISTEN_INTF 12 445*56b2bdd1SGireesh Nagabhushana #define M_LISTEN_INTF 0xFF 446*56b2bdd1SGireesh Nagabhushana #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 447*56b2bdd1SGireesh Nagabhushana #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 448*56b2bdd1SGireesh Nagabhushana 449*56b2bdd1SGireesh Nagabhushana #define S_LISTEN_FILTER 20 450*56b2bdd1SGireesh Nagabhushana #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 451*56b2bdd1SGireesh Nagabhushana #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 452*56b2bdd1SGireesh Nagabhushana 453*56b2bdd1SGireesh Nagabhushana #define S_SYN_DEFENSE 21 454*56b2bdd1SGireesh Nagabhushana #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 455*56b2bdd1SGireesh Nagabhushana #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 456*56b2bdd1SGireesh Nagabhushana 457*56b2bdd1SGireesh Nagabhushana #define S_CONN_POLICY 22 458*56b2bdd1SGireesh Nagabhushana #define M_CONN_POLICY 0x3 459*56b2bdd1SGireesh Nagabhushana #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 460*56b2bdd1SGireesh Nagabhushana #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 461*56b2bdd1SGireesh Nagabhushana 462*56b2bdd1SGireesh Nagabhushana /* option 2 fields */ 463*56b2bdd1SGireesh Nagabhushana #define S_RSS_QUEUE 0 464*56b2bdd1SGireesh Nagabhushana #define M_RSS_QUEUE 0x3FF 465*56b2bdd1SGireesh Nagabhushana #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 466*56b2bdd1SGireesh Nagabhushana #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 467*56b2bdd1SGireesh Nagabhushana 468*56b2bdd1SGireesh Nagabhushana #define S_RSS_QUEUE_VALID 10 469*56b2bdd1SGireesh Nagabhushana #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 470*56b2bdd1SGireesh Nagabhushana #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 471*56b2bdd1SGireesh Nagabhushana 472*56b2bdd1SGireesh Nagabhushana #define S_RX_COALESCE_VALID 11 473*56b2bdd1SGireesh Nagabhushana #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 474*56b2bdd1SGireesh Nagabhushana #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 475*56b2bdd1SGireesh Nagabhushana 476*56b2bdd1SGireesh Nagabhushana #define S_RX_COALESCE 12 477*56b2bdd1SGireesh Nagabhushana #define M_RX_COALESCE 0x3 478*56b2bdd1SGireesh Nagabhushana #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 479*56b2bdd1SGireesh Nagabhushana #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 480*56b2bdd1SGireesh Nagabhushana 481*56b2bdd1SGireesh Nagabhushana #define S_CONG_CNTRL 14 482*56b2bdd1SGireesh Nagabhushana #define M_CONG_CNTRL 0x3 483*56b2bdd1SGireesh Nagabhushana #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 484*56b2bdd1SGireesh Nagabhushana #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 485*56b2bdd1SGireesh Nagabhushana 486*56b2bdd1SGireesh Nagabhushana #define S_PACE 16 487*56b2bdd1SGireesh Nagabhushana #define M_PACE 0x3 488*56b2bdd1SGireesh Nagabhushana #define V_PACE(x) ((x) << S_PACE) 489*56b2bdd1SGireesh Nagabhushana #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 490*56b2bdd1SGireesh Nagabhushana 491*56b2bdd1SGireesh Nagabhushana #define S_CONG_CNTRL_VALID 18 492*56b2bdd1SGireesh Nagabhushana #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 493*56b2bdd1SGireesh Nagabhushana #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 494*56b2bdd1SGireesh Nagabhushana 495*56b2bdd1SGireesh Nagabhushana #define S_PACE_VALID 19 496*56b2bdd1SGireesh Nagabhushana #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 497*56b2bdd1SGireesh Nagabhushana #define F_PACE_VALID V_PACE_VALID(1U) 498*56b2bdd1SGireesh Nagabhushana 499*56b2bdd1SGireesh Nagabhushana #define S_RX_FC_DISABLE 20 500*56b2bdd1SGireesh Nagabhushana #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 501*56b2bdd1SGireesh Nagabhushana #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 502*56b2bdd1SGireesh Nagabhushana 503*56b2bdd1SGireesh Nagabhushana #define S_RX_FC_DDP 21 504*56b2bdd1SGireesh Nagabhushana #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 505*56b2bdd1SGireesh Nagabhushana #define F_RX_FC_DDP V_RX_FC_DDP(1U) 506*56b2bdd1SGireesh Nagabhushana 507*56b2bdd1SGireesh Nagabhushana #define S_RX_FC_VALID 22 508*56b2bdd1SGireesh Nagabhushana #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 509*56b2bdd1SGireesh Nagabhushana #define F_RX_FC_VALID V_RX_FC_VALID(1U) 510*56b2bdd1SGireesh Nagabhushana 511*56b2bdd1SGireesh Nagabhushana #define S_TX_QUEUE 23 512*56b2bdd1SGireesh Nagabhushana #define M_TX_QUEUE 0x7 513*56b2bdd1SGireesh Nagabhushana #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 514*56b2bdd1SGireesh Nagabhushana #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 515*56b2bdd1SGireesh Nagabhushana 516*56b2bdd1SGireesh Nagabhushana #define S_RX_CHANNEL 26 517*56b2bdd1SGireesh Nagabhushana #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 518*56b2bdd1SGireesh Nagabhushana #define F_RX_CHANNEL V_RX_CHANNEL(1U) 519*56b2bdd1SGireesh Nagabhushana 520*56b2bdd1SGireesh Nagabhushana #define S_CCTRL_ECN 27 521*56b2bdd1SGireesh Nagabhushana #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 522*56b2bdd1SGireesh Nagabhushana #define F_CCTRL_ECN V_CCTRL_ECN(1U) 523*56b2bdd1SGireesh Nagabhushana 524*56b2bdd1SGireesh Nagabhushana #define S_WND_SCALE_EN 28 525*56b2bdd1SGireesh Nagabhushana #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 526*56b2bdd1SGireesh Nagabhushana #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 527*56b2bdd1SGireesh Nagabhushana 528*56b2bdd1SGireesh Nagabhushana #define S_TSTAMPS_EN 29 529*56b2bdd1SGireesh Nagabhushana #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 530*56b2bdd1SGireesh Nagabhushana #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 531*56b2bdd1SGireesh Nagabhushana 532*56b2bdd1SGireesh Nagabhushana #define S_SACK_EN 30 533*56b2bdd1SGireesh Nagabhushana #define V_SACK_EN(x) ((x) << S_SACK_EN) 534*56b2bdd1SGireesh Nagabhushana #define F_SACK_EN V_SACK_EN(1U) 535*56b2bdd1SGireesh Nagabhushana 536*56b2bdd1SGireesh Nagabhushana struct cpl_pass_open_req { 537*56b2bdd1SGireesh Nagabhushana WR_HDR; 538*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 539*56b2bdd1SGireesh Nagabhushana __be16 local_port; 540*56b2bdd1SGireesh Nagabhushana __be16 peer_port; 541*56b2bdd1SGireesh Nagabhushana __be32 local_ip; 542*56b2bdd1SGireesh Nagabhushana __be32 peer_ip; 543*56b2bdd1SGireesh Nagabhushana __be64 opt0; 544*56b2bdd1SGireesh Nagabhushana __be64 opt1; 545*56b2bdd1SGireesh Nagabhushana }; 546*56b2bdd1SGireesh Nagabhushana 547*56b2bdd1SGireesh Nagabhushana struct cpl_pass_open_req6 { 548*56b2bdd1SGireesh Nagabhushana WR_HDR; 549*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 550*56b2bdd1SGireesh Nagabhushana __be16 local_port; 551*56b2bdd1SGireesh Nagabhushana __be16 peer_port; 552*56b2bdd1SGireesh Nagabhushana __be64 local_ip_hi; 553*56b2bdd1SGireesh Nagabhushana __be64 local_ip_lo; 554*56b2bdd1SGireesh Nagabhushana __be64 peer_ip_hi; 555*56b2bdd1SGireesh Nagabhushana __be64 peer_ip_lo; 556*56b2bdd1SGireesh Nagabhushana __be64 opt0; 557*56b2bdd1SGireesh Nagabhushana __be64 opt1; 558*56b2bdd1SGireesh Nagabhushana }; 559*56b2bdd1SGireesh Nagabhushana 560*56b2bdd1SGireesh Nagabhushana struct cpl_pass_open_rpl { 561*56b2bdd1SGireesh Nagabhushana RSS_HDR 562*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 563*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 564*56b2bdd1SGireesh Nagabhushana __u8 status; 565*56b2bdd1SGireesh Nagabhushana }; 566*56b2bdd1SGireesh Nagabhushana 567*56b2bdd1SGireesh Nagabhushana struct cpl_pass_establish { 568*56b2bdd1SGireesh Nagabhushana RSS_HDR 569*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 570*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 571*56b2bdd1SGireesh Nagabhushana __be32 tos_stid; 572*56b2bdd1SGireesh Nagabhushana __be16 mac_idx; 573*56b2bdd1SGireesh Nagabhushana __be16 tcp_opt; 574*56b2bdd1SGireesh Nagabhushana __be32 snd_isn; 575*56b2bdd1SGireesh Nagabhushana __be32 rcv_isn; 576*56b2bdd1SGireesh Nagabhushana }; 577*56b2bdd1SGireesh Nagabhushana 578*56b2bdd1SGireesh Nagabhushana /* cpl_pass_establish.tos_stid fields */ 579*56b2bdd1SGireesh Nagabhushana #define S_PASS_OPEN_TID 0 580*56b2bdd1SGireesh Nagabhushana #define M_PASS_OPEN_TID 0xFFFFFF 581*56b2bdd1SGireesh Nagabhushana #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 582*56b2bdd1SGireesh Nagabhushana #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 583*56b2bdd1SGireesh Nagabhushana 584*56b2bdd1SGireesh Nagabhushana #define S_PASS_OPEN_TOS 24 585*56b2bdd1SGireesh Nagabhushana #define M_PASS_OPEN_TOS 0xFF 586*56b2bdd1SGireesh Nagabhushana #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 587*56b2bdd1SGireesh Nagabhushana #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 588*56b2bdd1SGireesh Nagabhushana 589*56b2bdd1SGireesh Nagabhushana /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 590*56b2bdd1SGireesh Nagabhushana #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 591*56b2bdd1SGireesh Nagabhushana #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 592*56b2bdd1SGireesh Nagabhushana #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 593*56b2bdd1SGireesh Nagabhushana #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 594*56b2bdd1SGireesh Nagabhushana #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 595*56b2bdd1SGireesh Nagabhushana 596*56b2bdd1SGireesh Nagabhushana struct cpl_pass_accept_req { 597*56b2bdd1SGireesh Nagabhushana RSS_HDR 598*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 599*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 600*56b2bdd1SGireesh Nagabhushana __be16 len; 601*56b2bdd1SGireesh Nagabhushana __be32 hdr_len; 602*56b2bdd1SGireesh Nagabhushana __be16 vlan; 603*56b2bdd1SGireesh Nagabhushana __be16 l2info; 604*56b2bdd1SGireesh Nagabhushana __be32 tos_stid; 605*56b2bdd1SGireesh Nagabhushana struct tcp_options tcpopt; 606*56b2bdd1SGireesh Nagabhushana }; 607*56b2bdd1SGireesh Nagabhushana 608*56b2bdd1SGireesh Nagabhushana /* cpl_pass_accept_req.hdr_len fields */ 609*56b2bdd1SGireesh Nagabhushana #define S_SYN_RX_CHAN 0 610*56b2bdd1SGireesh Nagabhushana #define M_SYN_RX_CHAN 0xF 611*56b2bdd1SGireesh Nagabhushana #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 612*56b2bdd1SGireesh Nagabhushana #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 613*56b2bdd1SGireesh Nagabhushana 614*56b2bdd1SGireesh Nagabhushana #define S_TCP_HDR_LEN 10 615*56b2bdd1SGireesh Nagabhushana #define M_TCP_HDR_LEN 0x3F 616*56b2bdd1SGireesh Nagabhushana #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 617*56b2bdd1SGireesh Nagabhushana #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 618*56b2bdd1SGireesh Nagabhushana 619*56b2bdd1SGireesh Nagabhushana #define S_IP_HDR_LEN 16 620*56b2bdd1SGireesh Nagabhushana #define M_IP_HDR_LEN 0x3FF 621*56b2bdd1SGireesh Nagabhushana #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 622*56b2bdd1SGireesh Nagabhushana #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 623*56b2bdd1SGireesh Nagabhushana 624*56b2bdd1SGireesh Nagabhushana #define S_ETH_HDR_LEN 26 625*56b2bdd1SGireesh Nagabhushana #define M_ETH_HDR_LEN 0x1F 626*56b2bdd1SGireesh Nagabhushana #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 627*56b2bdd1SGireesh Nagabhushana #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 628*56b2bdd1SGireesh Nagabhushana 629*56b2bdd1SGireesh Nagabhushana /* cpl_pass_accept_req.l2info fields */ 630*56b2bdd1SGireesh Nagabhushana #define S_SYN_MAC_IDX 0 631*56b2bdd1SGireesh Nagabhushana #define M_SYN_MAC_IDX 0x1FF 632*56b2bdd1SGireesh Nagabhushana #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 633*56b2bdd1SGireesh Nagabhushana #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 634*56b2bdd1SGireesh Nagabhushana 635*56b2bdd1SGireesh Nagabhushana #define S_SYN_XACT_MATCH 9 636*56b2bdd1SGireesh Nagabhushana #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 637*56b2bdd1SGireesh Nagabhushana #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 638*56b2bdd1SGireesh Nagabhushana 639*56b2bdd1SGireesh Nagabhushana #define S_SYN_INTF 12 640*56b2bdd1SGireesh Nagabhushana #define M_SYN_INTF 0xF 641*56b2bdd1SGireesh Nagabhushana #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 642*56b2bdd1SGireesh Nagabhushana #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 643*56b2bdd1SGireesh Nagabhushana 644*56b2bdd1SGireesh Nagabhushana struct cpl_pass_accept_rpl { 645*56b2bdd1SGireesh Nagabhushana WR_HDR; 646*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 647*56b2bdd1SGireesh Nagabhushana __be32 opt2; 648*56b2bdd1SGireesh Nagabhushana __be64 opt0; 649*56b2bdd1SGireesh Nagabhushana }; 650*56b2bdd1SGireesh Nagabhushana 651*56b2bdd1SGireesh Nagabhushana struct cpl_act_open_req { 652*56b2bdd1SGireesh Nagabhushana WR_HDR; 653*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 654*56b2bdd1SGireesh Nagabhushana __be16 local_port; 655*56b2bdd1SGireesh Nagabhushana __be16 peer_port; 656*56b2bdd1SGireesh Nagabhushana __be32 local_ip; 657*56b2bdd1SGireesh Nagabhushana __be32 peer_ip; 658*56b2bdd1SGireesh Nagabhushana __be64 opt0; 659*56b2bdd1SGireesh Nagabhushana __be32 params; 660*56b2bdd1SGireesh Nagabhushana __be32 opt2; 661*56b2bdd1SGireesh Nagabhushana }; 662*56b2bdd1SGireesh Nagabhushana 663*56b2bdd1SGireesh Nagabhushana struct cpl_act_open_req6 { 664*56b2bdd1SGireesh Nagabhushana WR_HDR; 665*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 666*56b2bdd1SGireesh Nagabhushana __be16 local_port; 667*56b2bdd1SGireesh Nagabhushana __be16 peer_port; 668*56b2bdd1SGireesh Nagabhushana __be64 local_ip_hi; 669*56b2bdd1SGireesh Nagabhushana __be64 local_ip_lo; 670*56b2bdd1SGireesh Nagabhushana __be64 peer_ip_hi; 671*56b2bdd1SGireesh Nagabhushana __be64 peer_ip_lo; 672*56b2bdd1SGireesh Nagabhushana __be64 opt0; 673*56b2bdd1SGireesh Nagabhushana __be32 params; 674*56b2bdd1SGireesh Nagabhushana __be32 opt2; 675*56b2bdd1SGireesh Nagabhushana }; 676*56b2bdd1SGireesh Nagabhushana 677*56b2bdd1SGireesh Nagabhushana struct cpl_act_open_rpl { 678*56b2bdd1SGireesh Nagabhushana RSS_HDR 679*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 680*56b2bdd1SGireesh Nagabhushana __be32 atid_status; 681*56b2bdd1SGireesh Nagabhushana }; 682*56b2bdd1SGireesh Nagabhushana 683*56b2bdd1SGireesh Nagabhushana /* cpl_act_open_rpl.atid_status fields */ 684*56b2bdd1SGireesh Nagabhushana #define S_AOPEN_STATUS 0 685*56b2bdd1SGireesh Nagabhushana #define M_AOPEN_STATUS 0xFF 686*56b2bdd1SGireesh Nagabhushana #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 687*56b2bdd1SGireesh Nagabhushana #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 688*56b2bdd1SGireesh Nagabhushana 689*56b2bdd1SGireesh Nagabhushana #define S_AOPEN_ATID 8 690*56b2bdd1SGireesh Nagabhushana #define M_AOPEN_ATID 0xFFFFFF 691*56b2bdd1SGireesh Nagabhushana #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 692*56b2bdd1SGireesh Nagabhushana #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 693*56b2bdd1SGireesh Nagabhushana 694*56b2bdd1SGireesh Nagabhushana struct cpl_act_establish { 695*56b2bdd1SGireesh Nagabhushana RSS_HDR 696*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 697*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 698*56b2bdd1SGireesh Nagabhushana __be32 tos_atid; 699*56b2bdd1SGireesh Nagabhushana __be16 mac_idx; 700*56b2bdd1SGireesh Nagabhushana __be16 tcp_opt; 701*56b2bdd1SGireesh Nagabhushana __be32 snd_isn; 702*56b2bdd1SGireesh Nagabhushana __be32 rcv_isn; 703*56b2bdd1SGireesh Nagabhushana }; 704*56b2bdd1SGireesh Nagabhushana 705*56b2bdd1SGireesh Nagabhushana struct cpl_get_tcb { 706*56b2bdd1SGireesh Nagabhushana WR_HDR; 707*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 708*56b2bdd1SGireesh Nagabhushana __be16 reply_ctrl; 709*56b2bdd1SGireesh Nagabhushana __be16 cookie; 710*56b2bdd1SGireesh Nagabhushana }; 711*56b2bdd1SGireesh Nagabhushana 712*56b2bdd1SGireesh Nagabhushana /* cpl_get_tcb.reply_ctrl fields */ 713*56b2bdd1SGireesh Nagabhushana #define S_QUEUENO 0 714*56b2bdd1SGireesh Nagabhushana #define M_QUEUENO 0x3FF 715*56b2bdd1SGireesh Nagabhushana #define V_QUEUENO(x) ((x) << S_QUEUENO) 716*56b2bdd1SGireesh Nagabhushana #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 717*56b2bdd1SGireesh Nagabhushana 718*56b2bdd1SGireesh Nagabhushana #define S_REPLY_CHAN 14 719*56b2bdd1SGireesh Nagabhushana #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 720*56b2bdd1SGireesh Nagabhushana #define F_REPLY_CHAN V_REPLY_CHAN(1U) 721*56b2bdd1SGireesh Nagabhushana 722*56b2bdd1SGireesh Nagabhushana #define S_NO_REPLY 15 723*56b2bdd1SGireesh Nagabhushana #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 724*56b2bdd1SGireesh Nagabhushana #define F_NO_REPLY V_NO_REPLY(1U) 725*56b2bdd1SGireesh Nagabhushana 726*56b2bdd1SGireesh Nagabhushana struct cpl_get_tcb_rpl { 727*56b2bdd1SGireesh Nagabhushana RSS_HDR 728*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 729*56b2bdd1SGireesh Nagabhushana __u8 cookie; 730*56b2bdd1SGireesh Nagabhushana __u8 status; 731*56b2bdd1SGireesh Nagabhushana __be16 len; 732*56b2bdd1SGireesh Nagabhushana }; 733*56b2bdd1SGireesh Nagabhushana 734*56b2bdd1SGireesh Nagabhushana struct cpl_set_tcb { 735*56b2bdd1SGireesh Nagabhushana WR_HDR; 736*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 737*56b2bdd1SGireesh Nagabhushana __be16 reply_ctrl; 738*56b2bdd1SGireesh Nagabhushana __be16 cookie; 739*56b2bdd1SGireesh Nagabhushana }; 740*56b2bdd1SGireesh Nagabhushana 741*56b2bdd1SGireesh Nagabhushana struct cpl_set_tcb_field { 742*56b2bdd1SGireesh Nagabhushana WR_HDR; 743*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 744*56b2bdd1SGireesh Nagabhushana __be16 reply_ctrl; 745*56b2bdd1SGireesh Nagabhushana __be16 word_cookie; 746*56b2bdd1SGireesh Nagabhushana __be64 mask; 747*56b2bdd1SGireesh Nagabhushana __be64 val; 748*56b2bdd1SGireesh Nagabhushana }; 749*56b2bdd1SGireesh Nagabhushana 750*56b2bdd1SGireesh Nagabhushana /* cpl_set_tcb_field.word_cookie fields */ 751*56b2bdd1SGireesh Nagabhushana #define S_WORD 0 752*56b2bdd1SGireesh Nagabhushana #define M_WORD 0x1F 753*56b2bdd1SGireesh Nagabhushana #define V_WORD(x) ((x) << S_WORD) 754*56b2bdd1SGireesh Nagabhushana #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 755*56b2bdd1SGireesh Nagabhushana 756*56b2bdd1SGireesh Nagabhushana #define S_COOKIE 5 757*56b2bdd1SGireesh Nagabhushana #define M_COOKIE 0x7 758*56b2bdd1SGireesh Nagabhushana #define V_COOKIE(x) ((x) << S_COOKIE) 759*56b2bdd1SGireesh Nagabhushana #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 760*56b2bdd1SGireesh Nagabhushana 761*56b2bdd1SGireesh Nagabhushana struct cpl_set_tcb_rpl { 762*56b2bdd1SGireesh Nagabhushana RSS_HDR 763*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 764*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 765*56b2bdd1SGireesh Nagabhushana __u8 cookie; 766*56b2bdd1SGireesh Nagabhushana __u8 status; 767*56b2bdd1SGireesh Nagabhushana __be64 oldval; 768*56b2bdd1SGireesh Nagabhushana }; 769*56b2bdd1SGireesh Nagabhushana 770*56b2bdd1SGireesh Nagabhushana struct cpl_close_con_req { 771*56b2bdd1SGireesh Nagabhushana WR_HDR; 772*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 773*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 774*56b2bdd1SGireesh Nagabhushana }; 775*56b2bdd1SGireesh Nagabhushana 776*56b2bdd1SGireesh Nagabhushana struct cpl_close_con_rpl { 777*56b2bdd1SGireesh Nagabhushana RSS_HDR 778*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 779*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 780*56b2bdd1SGireesh Nagabhushana __u8 status; 781*56b2bdd1SGireesh Nagabhushana __be32 snd_nxt; 782*56b2bdd1SGireesh Nagabhushana __be32 rcv_nxt; 783*56b2bdd1SGireesh Nagabhushana }; 784*56b2bdd1SGireesh Nagabhushana 785*56b2bdd1SGireesh Nagabhushana struct cpl_close_listsvr_req { 786*56b2bdd1SGireesh Nagabhushana WR_HDR; 787*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 788*56b2bdd1SGireesh Nagabhushana __be16 reply_ctrl; 789*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 790*56b2bdd1SGireesh Nagabhushana }; 791*56b2bdd1SGireesh Nagabhushana 792*56b2bdd1SGireesh Nagabhushana /* additional cpl_close_listsvr_req.reply_ctrl field */ 793*56b2bdd1SGireesh Nagabhushana #define S_LISTSVR_IPV6 14 794*56b2bdd1SGireesh Nagabhushana #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 795*56b2bdd1SGireesh Nagabhushana #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 796*56b2bdd1SGireesh Nagabhushana 797*56b2bdd1SGireesh Nagabhushana struct cpl_close_listsvr_rpl { 798*56b2bdd1SGireesh Nagabhushana RSS_HDR 799*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 800*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 801*56b2bdd1SGireesh Nagabhushana __u8 status; 802*56b2bdd1SGireesh Nagabhushana }; 803*56b2bdd1SGireesh Nagabhushana 804*56b2bdd1SGireesh Nagabhushana struct cpl_abort_req_rss { 805*56b2bdd1SGireesh Nagabhushana RSS_HDR 806*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 807*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 808*56b2bdd1SGireesh Nagabhushana __u8 status; 809*56b2bdd1SGireesh Nagabhushana }; 810*56b2bdd1SGireesh Nagabhushana 811*56b2bdd1SGireesh Nagabhushana struct cpl_abort_req { 812*56b2bdd1SGireesh Nagabhushana WR_HDR; 813*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 814*56b2bdd1SGireesh Nagabhushana __be32 rsvd0; 815*56b2bdd1SGireesh Nagabhushana __u8 rsvd1; 816*56b2bdd1SGireesh Nagabhushana __u8 cmd; 817*56b2bdd1SGireesh Nagabhushana __u8 rsvd2[6]; 818*56b2bdd1SGireesh Nagabhushana }; 819*56b2bdd1SGireesh Nagabhushana 820*56b2bdd1SGireesh Nagabhushana struct cpl_abort_rpl_rss { 821*56b2bdd1SGireesh Nagabhushana RSS_HDR 822*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 823*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 824*56b2bdd1SGireesh Nagabhushana __u8 status; 825*56b2bdd1SGireesh Nagabhushana }; 826*56b2bdd1SGireesh Nagabhushana 827*56b2bdd1SGireesh Nagabhushana struct cpl_abort_rpl { 828*56b2bdd1SGireesh Nagabhushana WR_HDR; 829*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 830*56b2bdd1SGireesh Nagabhushana __be32 rsvd0; 831*56b2bdd1SGireesh Nagabhushana __u8 rsvd1; 832*56b2bdd1SGireesh Nagabhushana __u8 cmd; 833*56b2bdd1SGireesh Nagabhushana __u8 rsvd2[6]; 834*56b2bdd1SGireesh Nagabhushana }; 835*56b2bdd1SGireesh Nagabhushana 836*56b2bdd1SGireesh Nagabhushana struct cpl_peer_close { 837*56b2bdd1SGireesh Nagabhushana RSS_HDR 838*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 839*56b2bdd1SGireesh Nagabhushana __be32 rcv_nxt; 840*56b2bdd1SGireesh Nagabhushana }; 841*56b2bdd1SGireesh Nagabhushana 842*56b2bdd1SGireesh Nagabhushana struct cpl_tid_release { 843*56b2bdd1SGireesh Nagabhushana WR_HDR; 844*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 845*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 846*56b2bdd1SGireesh Nagabhushana }; 847*56b2bdd1SGireesh Nagabhushana 848*56b2bdd1SGireesh Nagabhushana struct tx_data_wr { 849*56b2bdd1SGireesh Nagabhushana __be32 wr_hi; 850*56b2bdd1SGireesh Nagabhushana __be32 wr_lo; 851*56b2bdd1SGireesh Nagabhushana __be32 len; 852*56b2bdd1SGireesh Nagabhushana __be32 flags; 853*56b2bdd1SGireesh Nagabhushana __be32 sndseq; 854*56b2bdd1SGireesh Nagabhushana __be32 param; 855*56b2bdd1SGireesh Nagabhushana }; 856*56b2bdd1SGireesh Nagabhushana 857*56b2bdd1SGireesh Nagabhushana /* tx_data_wr.flags fields */ 858*56b2bdd1SGireesh Nagabhushana #define S_TX_ACK_PAGES 21 859*56b2bdd1SGireesh Nagabhushana #define M_TX_ACK_PAGES 0x7 860*56b2bdd1SGireesh Nagabhushana #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 861*56b2bdd1SGireesh Nagabhushana #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 862*56b2bdd1SGireesh Nagabhushana 863*56b2bdd1SGireesh Nagabhushana /* tx_data_wr.param fields */ 864*56b2bdd1SGireesh Nagabhushana #define S_TX_PORT 0 865*56b2bdd1SGireesh Nagabhushana #define M_TX_PORT 0x7 866*56b2bdd1SGireesh Nagabhushana #define V_TX_PORT(x) ((x) << S_TX_PORT) 867*56b2bdd1SGireesh Nagabhushana #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 868*56b2bdd1SGireesh Nagabhushana 869*56b2bdd1SGireesh Nagabhushana #define S_TX_MSS 4 870*56b2bdd1SGireesh Nagabhushana #define M_TX_MSS 0xF 871*56b2bdd1SGireesh Nagabhushana #define V_TX_MSS(x) ((x) << S_TX_MSS) 872*56b2bdd1SGireesh Nagabhushana #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 873*56b2bdd1SGireesh Nagabhushana 874*56b2bdd1SGireesh Nagabhushana #define S_TX_QOS 8 875*56b2bdd1SGireesh Nagabhushana #define M_TX_QOS 0xFF 876*56b2bdd1SGireesh Nagabhushana #define V_TX_QOS(x) ((x) << S_TX_QOS) 877*56b2bdd1SGireesh Nagabhushana #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 878*56b2bdd1SGireesh Nagabhushana 879*56b2bdd1SGireesh Nagabhushana #define S_TX_SNDBUF 16 880*56b2bdd1SGireesh Nagabhushana #define M_TX_SNDBUF 0xFFFF 881*56b2bdd1SGireesh Nagabhushana #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 882*56b2bdd1SGireesh Nagabhushana #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 883*56b2bdd1SGireesh Nagabhushana 884*56b2bdd1SGireesh Nagabhushana struct cpl_tx_data { 885*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 886*56b2bdd1SGireesh Nagabhushana __be32 len; 887*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 888*56b2bdd1SGireesh Nagabhushana __be32 flags; 889*56b2bdd1SGireesh Nagabhushana }; 890*56b2bdd1SGireesh Nagabhushana 891*56b2bdd1SGireesh Nagabhushana /* cpl_tx_data.flags fields */ 892*56b2bdd1SGireesh Nagabhushana #define S_TX_PROXY 5 893*56b2bdd1SGireesh Nagabhushana #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 894*56b2bdd1SGireesh Nagabhushana #define F_TX_PROXY V_TX_PROXY(1U) 895*56b2bdd1SGireesh Nagabhushana 896*56b2bdd1SGireesh Nagabhushana #define S_TX_ULP_SUBMODE 6 897*56b2bdd1SGireesh Nagabhushana #define M_TX_ULP_SUBMODE 0xF 898*56b2bdd1SGireesh Nagabhushana #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 899*56b2bdd1SGireesh Nagabhushana #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 900*56b2bdd1SGireesh Nagabhushana 901*56b2bdd1SGireesh Nagabhushana #define S_TX_ULP_MODE 10 902*56b2bdd1SGireesh Nagabhushana #define M_TX_ULP_MODE 0xF 903*56b2bdd1SGireesh Nagabhushana #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 904*56b2bdd1SGireesh Nagabhushana #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 905*56b2bdd1SGireesh Nagabhushana 906*56b2bdd1SGireesh Nagabhushana #define S_TX_SHOVE 14 907*56b2bdd1SGireesh Nagabhushana #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 908*56b2bdd1SGireesh Nagabhushana #define F_TX_SHOVE V_TX_SHOVE(1U) 909*56b2bdd1SGireesh Nagabhushana 910*56b2bdd1SGireesh Nagabhushana #define S_TX_MORE 15 911*56b2bdd1SGireesh Nagabhushana #define V_TX_MORE(x) ((x) << S_TX_MORE) 912*56b2bdd1SGireesh Nagabhushana #define F_TX_MORE V_TX_MORE(1U) 913*56b2bdd1SGireesh Nagabhushana 914*56b2bdd1SGireesh Nagabhushana #define S_TX_URG 16 915*56b2bdd1SGireesh Nagabhushana #define V_TX_URG(x) ((x) << S_TX_URG) 916*56b2bdd1SGireesh Nagabhushana #define F_TX_URG V_TX_URG(1U) 917*56b2bdd1SGireesh Nagabhushana 918*56b2bdd1SGireesh Nagabhushana #define S_TX_FLUSH 17 919*56b2bdd1SGireesh Nagabhushana #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 920*56b2bdd1SGireesh Nagabhushana #define F_TX_FLUSH V_TX_FLUSH(1U) 921*56b2bdd1SGireesh Nagabhushana 922*56b2bdd1SGireesh Nagabhushana #define S_TX_SAVE 18 923*56b2bdd1SGireesh Nagabhushana #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 924*56b2bdd1SGireesh Nagabhushana #define F_TX_SAVE V_TX_SAVE(1U) 925*56b2bdd1SGireesh Nagabhushana 926*56b2bdd1SGireesh Nagabhushana #define S_TX_TNL 19 927*56b2bdd1SGireesh Nagabhushana #define V_TX_TNL(x) ((x) << S_TX_TNL) 928*56b2bdd1SGireesh Nagabhushana #define F_TX_TNL V_TX_TNL(1U) 929*56b2bdd1SGireesh Nagabhushana 930*56b2bdd1SGireesh Nagabhushana /* additional tx_data_wr.flags fields */ 931*56b2bdd1SGireesh Nagabhushana #define S_TX_CPU_IDX 0 932*56b2bdd1SGireesh Nagabhushana #define M_TX_CPU_IDX 0x3F 933*56b2bdd1SGireesh Nagabhushana #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 934*56b2bdd1SGireesh Nagabhushana #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 935*56b2bdd1SGireesh Nagabhushana 936*56b2bdd1SGireesh Nagabhushana #define S_TX_CLOSE 17 937*56b2bdd1SGireesh Nagabhushana #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 938*56b2bdd1SGireesh Nagabhushana #define F_TX_CLOSE V_TX_CLOSE(1U) 939*56b2bdd1SGireesh Nagabhushana 940*56b2bdd1SGireesh Nagabhushana #define S_TX_INIT 18 941*56b2bdd1SGireesh Nagabhushana #define V_TX_INIT(x) ((x) << S_TX_INIT) 942*56b2bdd1SGireesh Nagabhushana #define F_TX_INIT V_TX_INIT(1U) 943*56b2bdd1SGireesh Nagabhushana 944*56b2bdd1SGireesh Nagabhushana #define S_TX_IMM_ACK 19 945*56b2bdd1SGireesh Nagabhushana #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 946*56b2bdd1SGireesh Nagabhushana #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 947*56b2bdd1SGireesh Nagabhushana 948*56b2bdd1SGireesh Nagabhushana #define S_TX_IMM_DMA 20 949*56b2bdd1SGireesh Nagabhushana #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 950*56b2bdd1SGireesh Nagabhushana #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 951*56b2bdd1SGireesh Nagabhushana 952*56b2bdd1SGireesh Nagabhushana struct cpl_tx_data_ack { 953*56b2bdd1SGireesh Nagabhushana RSS_HDR 954*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 955*56b2bdd1SGireesh Nagabhushana __be32 snd_una; 956*56b2bdd1SGireesh Nagabhushana }; 957*56b2bdd1SGireesh Nagabhushana 958*56b2bdd1SGireesh Nagabhushana struct cpl_wr_ack { /* TODO */ 959*56b2bdd1SGireesh Nagabhushana RSS_HDR 960*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 961*56b2bdd1SGireesh Nagabhushana __be16 credits; 962*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 963*56b2bdd1SGireesh Nagabhushana __be32 snd_nxt; 964*56b2bdd1SGireesh Nagabhushana __be32 snd_una; 965*56b2bdd1SGireesh Nagabhushana }; 966*56b2bdd1SGireesh Nagabhushana 967*56b2bdd1SGireesh Nagabhushana struct cpl_tx_pkt_core { 968*56b2bdd1SGireesh Nagabhushana __be32 ctrl0; 969*56b2bdd1SGireesh Nagabhushana __be16 pack; 970*56b2bdd1SGireesh Nagabhushana __be16 len; 971*56b2bdd1SGireesh Nagabhushana __be64 ctrl1; 972*56b2bdd1SGireesh Nagabhushana }; 973*56b2bdd1SGireesh Nagabhushana 974*56b2bdd1SGireesh Nagabhushana struct cpl_tx_pkt { 975*56b2bdd1SGireesh Nagabhushana WR_HDR; 976*56b2bdd1SGireesh Nagabhushana struct cpl_tx_pkt_core c; 977*56b2bdd1SGireesh Nagabhushana }; 978*56b2bdd1SGireesh Nagabhushana 979*56b2bdd1SGireesh Nagabhushana #define cpl_tx_pkt_xt cpl_tx_pkt 980*56b2bdd1SGireesh Nagabhushana 981*56b2bdd1SGireesh Nagabhushana /* cpl_tx_pkt_core.ctrl0 fields */ 982*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_VF 0 983*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_VF 0xFF 984*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 985*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 986*56b2bdd1SGireesh Nagabhushana 987*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_PF 8 988*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_PF 0x7 989*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 990*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 991*56b2bdd1SGireesh Nagabhushana 992*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_VF_VLD 11 993*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 994*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 995*56b2bdd1SGireesh Nagabhushana 996*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_OVLAN_IDX 12 997*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_OVLAN_IDX 0xF 998*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 999*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1000*56b2bdd1SGireesh Nagabhushana 1001*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_INTF 16 1002*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_INTF 0xF 1003*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1004*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1005*56b2bdd1SGireesh Nagabhushana 1006*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_SPECIAL_STAT 20 1007*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1008*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1009*56b2bdd1SGireesh Nagabhushana 1010*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_INS_OVLAN 21 1011*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1012*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1013*56b2bdd1SGireesh Nagabhushana 1014*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_STAT_DIS 22 1015*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1016*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1017*56b2bdd1SGireesh Nagabhushana 1018*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_LOOPBACK 23 1019*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1020*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1021*56b2bdd1SGireesh Nagabhushana 1022*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_OPCODE 24 1023*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_OPCODE 0xFF 1024*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1025*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1026*56b2bdd1SGireesh Nagabhushana 1027*56b2bdd1SGireesh Nagabhushana /* cpl_tx_pkt_core.ctrl1 fields */ 1028*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_SA_IDX 0 1029*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_SA_IDX 0xFFF 1030*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1031*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1032*56b2bdd1SGireesh Nagabhushana 1033*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_CSUM_END 12 1034*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_CSUM_END 0xFF 1035*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1036*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1037*56b2bdd1SGireesh Nagabhushana 1038*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_CSUM_START 20 1039*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_CSUM_START 0x3FF 1040*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1041*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1042*56b2bdd1SGireesh Nagabhushana 1043*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_IPHDR_LEN 20 1044*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_IPHDR_LEN 0x3FFF 1045*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1046*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1047*56b2bdd1SGireesh Nagabhushana 1048*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_CSUM_LOC 30 1049*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_CSUM_LOC 0x3FF 1050*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1051*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1052*56b2bdd1SGireesh Nagabhushana 1053*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_ETHHDR_LEN 34 1054*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_ETHHDR_LEN 0x3F 1055*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1056*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1057*56b2bdd1SGireesh Nagabhushana 1058*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_CSUM_TYPE 40 1059*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_CSUM_TYPE 0xF 1060*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1061*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1062*56b2bdd1SGireesh Nagabhushana 1063*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_VLAN 44 1064*56b2bdd1SGireesh Nagabhushana #define M_TXPKT_VLAN 0xFFFF 1065*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1066*56b2bdd1SGireesh Nagabhushana #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1067*56b2bdd1SGireesh Nagabhushana 1068*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_VLAN_VLD 60 1069*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1070*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1071*56b2bdd1SGireesh Nagabhushana 1072*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_IPSEC 61 1073*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1074*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1075*56b2bdd1SGireesh Nagabhushana 1076*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_IPCSUM_DIS 62 1077*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1078*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1079*56b2bdd1SGireesh Nagabhushana 1080*56b2bdd1SGireesh Nagabhushana #define S_TXPKT_L4CSUM_DIS 63 1081*56b2bdd1SGireesh Nagabhushana #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1082*56b2bdd1SGireesh Nagabhushana #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1083*56b2bdd1SGireesh Nagabhushana 1084*56b2bdd1SGireesh Nagabhushana struct cpl_tx_pkt_lso { 1085*56b2bdd1SGireesh Nagabhushana __be32 lso_ctrl; 1086*56b2bdd1SGireesh Nagabhushana __be16 ipid_ofst; 1087*56b2bdd1SGireesh Nagabhushana __be16 mss; 1088*56b2bdd1SGireesh Nagabhushana __be32 seqno_offset; 1089*56b2bdd1SGireesh Nagabhushana __be32 len; 1090*56b2bdd1SGireesh Nagabhushana /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1091*56b2bdd1SGireesh Nagabhushana }; 1092*56b2bdd1SGireesh Nagabhushana 1093*56b2bdd1SGireesh Nagabhushana /* cpl_tx_pkt_lso.lso_ctrl fields */ 1094*56b2bdd1SGireesh Nagabhushana #define S_LSO_TCPHDR_LEN 0 1095*56b2bdd1SGireesh Nagabhushana #define M_LSO_TCPHDR_LEN 0xF 1096*56b2bdd1SGireesh Nagabhushana #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1097*56b2bdd1SGireesh Nagabhushana #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1098*56b2bdd1SGireesh Nagabhushana 1099*56b2bdd1SGireesh Nagabhushana #define S_LSO_IPHDR_LEN 4 1100*56b2bdd1SGireesh Nagabhushana #define M_LSO_IPHDR_LEN 0xFFF 1101*56b2bdd1SGireesh Nagabhushana #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1102*56b2bdd1SGireesh Nagabhushana #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1103*56b2bdd1SGireesh Nagabhushana 1104*56b2bdd1SGireesh Nagabhushana #define S_LSO_ETHHDR_LEN 16 1105*56b2bdd1SGireesh Nagabhushana #define M_LSO_ETHHDR_LEN 0xF 1106*56b2bdd1SGireesh Nagabhushana #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1107*56b2bdd1SGireesh Nagabhushana #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1108*56b2bdd1SGireesh Nagabhushana 1109*56b2bdd1SGireesh Nagabhushana #define S_LSO_IPV6 20 1110*56b2bdd1SGireesh Nagabhushana #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1111*56b2bdd1SGireesh Nagabhushana #define F_LSO_IPV6 V_LSO_IPV6(1U) 1112*56b2bdd1SGireesh Nagabhushana 1113*56b2bdd1SGireesh Nagabhushana #define S_LSO_OFLD_ENCAP 21 1114*56b2bdd1SGireesh Nagabhushana #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1115*56b2bdd1SGireesh Nagabhushana #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1116*56b2bdd1SGireesh Nagabhushana 1117*56b2bdd1SGireesh Nagabhushana #define S_LSO_LAST_SLICE 22 1118*56b2bdd1SGireesh Nagabhushana #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1119*56b2bdd1SGireesh Nagabhushana #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1120*56b2bdd1SGireesh Nagabhushana 1121*56b2bdd1SGireesh Nagabhushana #define S_LSO_FIRST_SLICE 23 1122*56b2bdd1SGireesh Nagabhushana #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1123*56b2bdd1SGireesh Nagabhushana #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1124*56b2bdd1SGireesh Nagabhushana 1125*56b2bdd1SGireesh Nagabhushana #define S_LSO_OPCODE 24 1126*56b2bdd1SGireesh Nagabhushana #define M_LSO_OPCODE 0xFF 1127*56b2bdd1SGireesh Nagabhushana #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1128*56b2bdd1SGireesh Nagabhushana #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1129*56b2bdd1SGireesh Nagabhushana 1130*56b2bdd1SGireesh Nagabhushana /* cpl_tx_pkt_lso.mss fields */ 1131*56b2bdd1SGireesh Nagabhushana #define S_LSO_MSS 0 1132*56b2bdd1SGireesh Nagabhushana #define M_LSO_MSS 0x3FFF 1133*56b2bdd1SGireesh Nagabhushana #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1134*56b2bdd1SGireesh Nagabhushana #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1135*56b2bdd1SGireesh Nagabhushana 1136*56b2bdd1SGireesh Nagabhushana #define S_LSO_IPID_SPLIT 15 1137*56b2bdd1SGireesh Nagabhushana #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1138*56b2bdd1SGireesh Nagabhushana #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1139*56b2bdd1SGireesh Nagabhushana 1140*56b2bdd1SGireesh Nagabhushana struct cpl_tx_pkt_coalesce { 1141*56b2bdd1SGireesh Nagabhushana __be32 cntrl; 1142*56b2bdd1SGireesh Nagabhushana __be32 len; 1143*56b2bdd1SGireesh Nagabhushana __be64 addr; 1144*56b2bdd1SGireesh Nagabhushana }; 1145*56b2bdd1SGireesh Nagabhushana 1146*56b2bdd1SGireesh Nagabhushana struct tx_pkt_coalesce_wr { 1147*56b2bdd1SGireesh Nagabhushana WR_HDR; 1148*56b2bdd1SGireesh Nagabhushana #if !(defined C99_NOT_SUPPORTED) 1149*56b2bdd1SGireesh Nagabhushana struct cpl_tx_pkt_coalesce cpl[]; 1150*56b2bdd1SGireesh Nagabhushana #endif 1151*56b2bdd1SGireesh Nagabhushana }; 1152*56b2bdd1SGireesh Nagabhushana 1153*56b2bdd1SGireesh Nagabhushana struct mngt_pktsched_wr { 1154*56b2bdd1SGireesh Nagabhushana __be32 wr_hi; 1155*56b2bdd1SGireesh Nagabhushana __be32 wr_lo; 1156*56b2bdd1SGireesh Nagabhushana __u8 mngt_opcode; 1157*56b2bdd1SGireesh Nagabhushana __u8 rsvd[7]; 1158*56b2bdd1SGireesh Nagabhushana __u8 sched; 1159*56b2bdd1SGireesh Nagabhushana __u8 idx; 1160*56b2bdd1SGireesh Nagabhushana __u8 min; 1161*56b2bdd1SGireesh Nagabhushana __u8 max; 1162*56b2bdd1SGireesh Nagabhushana __u8 binding; 1163*56b2bdd1SGireesh Nagabhushana __u8 rsvd1[3]; 1164*56b2bdd1SGireesh Nagabhushana }; 1165*56b2bdd1SGireesh Nagabhushana 1166*56b2bdd1SGireesh Nagabhushana struct cpl_iscsi_hdr_no_rss { 1167*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1168*56b2bdd1SGireesh Nagabhushana __be16 pdu_len_ddp; 1169*56b2bdd1SGireesh Nagabhushana __be16 len; 1170*56b2bdd1SGireesh Nagabhushana __be32 seq; 1171*56b2bdd1SGireesh Nagabhushana __be16 urg; 1172*56b2bdd1SGireesh Nagabhushana __u8 rsvd; 1173*56b2bdd1SGireesh Nagabhushana __u8 status; 1174*56b2bdd1SGireesh Nagabhushana }; 1175*56b2bdd1SGireesh Nagabhushana 1176*56b2bdd1SGireesh Nagabhushana struct cpl_iscsi_hdr { 1177*56b2bdd1SGireesh Nagabhushana RSS_HDR 1178*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1179*56b2bdd1SGireesh Nagabhushana __be16 pdu_len_ddp; 1180*56b2bdd1SGireesh Nagabhushana __be16 len; 1181*56b2bdd1SGireesh Nagabhushana __be32 seq; 1182*56b2bdd1SGireesh Nagabhushana __be16 urg; 1183*56b2bdd1SGireesh Nagabhushana __u8 rsvd; 1184*56b2bdd1SGireesh Nagabhushana __u8 status; 1185*56b2bdd1SGireesh Nagabhushana }; 1186*56b2bdd1SGireesh Nagabhushana 1187*56b2bdd1SGireesh Nagabhushana /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1188*56b2bdd1SGireesh Nagabhushana #define S_ISCSI_PDU_LEN 0 1189*56b2bdd1SGireesh Nagabhushana #define M_ISCSI_PDU_LEN 0x7FFF 1190*56b2bdd1SGireesh Nagabhushana #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1191*56b2bdd1SGireesh Nagabhushana #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1192*56b2bdd1SGireesh Nagabhushana 1193*56b2bdd1SGireesh Nagabhushana #define S_ISCSI_DDP 15 1194*56b2bdd1SGireesh Nagabhushana #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1195*56b2bdd1SGireesh Nagabhushana #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1196*56b2bdd1SGireesh Nagabhushana 1197*56b2bdd1SGireesh Nagabhushana struct cpl_rx_data { 1198*56b2bdd1SGireesh Nagabhushana RSS_HDR 1199*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1200*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1201*56b2bdd1SGireesh Nagabhushana __be16 len; 1202*56b2bdd1SGireesh Nagabhushana __be32 seq; 1203*56b2bdd1SGireesh Nagabhushana __be16 urg; 1204*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 1205*56b2bdd1SGireesh Nagabhushana __u8 dack_mode:2; 1206*56b2bdd1SGireesh Nagabhushana __u8 psh:1; 1207*56b2bdd1SGireesh Nagabhushana __u8 heartbeat:1; 1208*56b2bdd1SGireesh Nagabhushana __u8 ddp_off:1; 1209*56b2bdd1SGireesh Nagabhushana __u8 :3; 1210*56b2bdd1SGireesh Nagabhushana #else 1211*56b2bdd1SGireesh Nagabhushana __u8 :3; 1212*56b2bdd1SGireesh Nagabhushana __u8 ddp_off:1; 1213*56b2bdd1SGireesh Nagabhushana __u8 heartbeat:1; 1214*56b2bdd1SGireesh Nagabhushana __u8 psh:1; 1215*56b2bdd1SGireesh Nagabhushana __u8 dack_mode:2; 1216*56b2bdd1SGireesh Nagabhushana #endif 1217*56b2bdd1SGireesh Nagabhushana __u8 status; 1218*56b2bdd1SGireesh Nagabhushana }; 1219*56b2bdd1SGireesh Nagabhushana 1220*56b2bdd1SGireesh Nagabhushana struct cpl_fcoe_hdr { 1221*56b2bdd1SGireesh Nagabhushana RSS_HDR 1222*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1223*56b2bdd1SGireesh Nagabhushana __be16 oxid; 1224*56b2bdd1SGireesh Nagabhushana __be16 len; 1225*56b2bdd1SGireesh Nagabhushana __be32 rctl_fctl; 1226*56b2bdd1SGireesh Nagabhushana __u8 cs_ctl; 1227*56b2bdd1SGireesh Nagabhushana __u8 df_ctl; 1228*56b2bdd1SGireesh Nagabhushana __u8 sof; 1229*56b2bdd1SGireesh Nagabhushana __u8 eof; 1230*56b2bdd1SGireesh Nagabhushana __be16 seq_cnt; 1231*56b2bdd1SGireesh Nagabhushana __u8 seq_id; 1232*56b2bdd1SGireesh Nagabhushana __u8 type; 1233*56b2bdd1SGireesh Nagabhushana __be32 param; 1234*56b2bdd1SGireesh Nagabhushana }; 1235*56b2bdd1SGireesh Nagabhushana 1236*56b2bdd1SGireesh Nagabhushana struct cpl_rx_urg_notify { 1237*56b2bdd1SGireesh Nagabhushana RSS_HDR 1238*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1239*56b2bdd1SGireesh Nagabhushana __be32 seq; 1240*56b2bdd1SGireesh Nagabhushana }; 1241*56b2bdd1SGireesh Nagabhushana 1242*56b2bdd1SGireesh Nagabhushana struct cpl_rx_urg_pkt { 1243*56b2bdd1SGireesh Nagabhushana RSS_HDR 1244*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1245*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1246*56b2bdd1SGireesh Nagabhushana __be16 len; 1247*56b2bdd1SGireesh Nagabhushana }; 1248*56b2bdd1SGireesh Nagabhushana 1249*56b2bdd1SGireesh Nagabhushana struct cpl_rx_data_ack { 1250*56b2bdd1SGireesh Nagabhushana WR_HDR; 1251*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1252*56b2bdd1SGireesh Nagabhushana __be32 credit_dack; 1253*56b2bdd1SGireesh Nagabhushana }; 1254*56b2bdd1SGireesh Nagabhushana 1255*56b2bdd1SGireesh Nagabhushana /* cpl_rx_data_ack.ack_seq fields */ 1256*56b2bdd1SGireesh Nagabhushana #define S_RX_CREDITS 0 1257*56b2bdd1SGireesh Nagabhushana #define M_RX_CREDITS 0x3FFFFFF 1258*56b2bdd1SGireesh Nagabhushana #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1259*56b2bdd1SGireesh Nagabhushana #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1260*56b2bdd1SGireesh Nagabhushana 1261*56b2bdd1SGireesh Nagabhushana #define S_RX_MODULATE_TX 26 1262*56b2bdd1SGireesh Nagabhushana #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1263*56b2bdd1SGireesh Nagabhushana #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1264*56b2bdd1SGireesh Nagabhushana 1265*56b2bdd1SGireesh Nagabhushana #define S_RX_MODULATE_RX 27 1266*56b2bdd1SGireesh Nagabhushana #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1267*56b2bdd1SGireesh Nagabhushana #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1268*56b2bdd1SGireesh Nagabhushana 1269*56b2bdd1SGireesh Nagabhushana #define S_RX_FORCE_ACK 28 1270*56b2bdd1SGireesh Nagabhushana #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1271*56b2bdd1SGireesh Nagabhushana #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1272*56b2bdd1SGireesh Nagabhushana 1273*56b2bdd1SGireesh Nagabhushana #define S_RX_DACK_MODE 29 1274*56b2bdd1SGireesh Nagabhushana #define M_RX_DACK_MODE 0x3 1275*56b2bdd1SGireesh Nagabhushana #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1276*56b2bdd1SGireesh Nagabhushana #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1277*56b2bdd1SGireesh Nagabhushana 1278*56b2bdd1SGireesh Nagabhushana #define S_RX_DACK_CHANGE 31 1279*56b2bdd1SGireesh Nagabhushana #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1280*56b2bdd1SGireesh Nagabhushana #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1281*56b2bdd1SGireesh Nagabhushana 1282*56b2bdd1SGireesh Nagabhushana struct cpl_rx_ddp_complete { 1283*56b2bdd1SGireesh Nagabhushana RSS_HDR 1284*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1285*56b2bdd1SGireesh Nagabhushana __be32 ddp_report; 1286*56b2bdd1SGireesh Nagabhushana __be32 rcv_nxt; 1287*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 1288*56b2bdd1SGireesh Nagabhushana }; 1289*56b2bdd1SGireesh Nagabhushana 1290*56b2bdd1SGireesh Nagabhushana struct cpl_rx_data_ddp { 1291*56b2bdd1SGireesh Nagabhushana RSS_HDR 1292*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1293*56b2bdd1SGireesh Nagabhushana __be16 urg; 1294*56b2bdd1SGireesh Nagabhushana __be16 len; 1295*56b2bdd1SGireesh Nagabhushana __be32 seq; 1296*56b2bdd1SGireesh Nagabhushana union { 1297*56b2bdd1SGireesh Nagabhushana __be32 nxt_seq; 1298*56b2bdd1SGireesh Nagabhushana __be32 ddp_report; 1299*56b2bdd1SGireesh Nagabhushana } u; 1300*56b2bdd1SGireesh Nagabhushana __be32 ulp_crc; 1301*56b2bdd1SGireesh Nagabhushana __be32 ddpvld; 1302*56b2bdd1SGireesh Nagabhushana }; 1303*56b2bdd1SGireesh Nagabhushana 1304*56b2bdd1SGireesh Nagabhushana struct cpl_rx_fcoe_ddp { 1305*56b2bdd1SGireesh Nagabhushana RSS_HDR 1306*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1307*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1308*56b2bdd1SGireesh Nagabhushana __be16 len; 1309*56b2bdd1SGireesh Nagabhushana __be32 seq; 1310*56b2bdd1SGireesh Nagabhushana __be32 ddp_report; 1311*56b2bdd1SGireesh Nagabhushana __be32 ulp_crc; 1312*56b2bdd1SGireesh Nagabhushana __be32 ddpvld; 1313*56b2bdd1SGireesh Nagabhushana }; 1314*56b2bdd1SGireesh Nagabhushana 1315*56b2bdd1SGireesh Nagabhushana /* cpl_rx_{data,fcoe}_ddp.ddpvld fields */ 1316*56b2bdd1SGireesh Nagabhushana #define S_DDP_VALID 15 1317*56b2bdd1SGireesh Nagabhushana #define M_DDP_VALID 0x1FFFF 1318*56b2bdd1SGireesh Nagabhushana #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1319*56b2bdd1SGireesh Nagabhushana #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1320*56b2bdd1SGireesh Nagabhushana 1321*56b2bdd1SGireesh Nagabhushana #define S_DDP_PPOD_MISMATCH 15 1322*56b2bdd1SGireesh Nagabhushana #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1323*56b2bdd1SGireesh Nagabhushana #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1324*56b2bdd1SGireesh Nagabhushana 1325*56b2bdd1SGireesh Nagabhushana #define S_DDP_PDU 16 1326*56b2bdd1SGireesh Nagabhushana #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1327*56b2bdd1SGireesh Nagabhushana #define F_DDP_PDU V_DDP_PDU(1U) 1328*56b2bdd1SGireesh Nagabhushana 1329*56b2bdd1SGireesh Nagabhushana #define S_DDP_LLIMIT_ERR 17 1330*56b2bdd1SGireesh Nagabhushana #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1331*56b2bdd1SGireesh Nagabhushana #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1332*56b2bdd1SGireesh Nagabhushana 1333*56b2bdd1SGireesh Nagabhushana #define S_DDP_PPOD_PARITY_ERR 18 1334*56b2bdd1SGireesh Nagabhushana #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1335*56b2bdd1SGireesh Nagabhushana #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1336*56b2bdd1SGireesh Nagabhushana 1337*56b2bdd1SGireesh Nagabhushana #define S_DDP_PADDING_ERR 19 1338*56b2bdd1SGireesh Nagabhushana #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1339*56b2bdd1SGireesh Nagabhushana #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1340*56b2bdd1SGireesh Nagabhushana 1341*56b2bdd1SGireesh Nagabhushana #define S_DDP_HDRCRC_ERR 20 1342*56b2bdd1SGireesh Nagabhushana #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1343*56b2bdd1SGireesh Nagabhushana #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1344*56b2bdd1SGireesh Nagabhushana 1345*56b2bdd1SGireesh Nagabhushana #define S_DDP_DATACRC_ERR 21 1346*56b2bdd1SGireesh Nagabhushana #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1347*56b2bdd1SGireesh Nagabhushana #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1348*56b2bdd1SGireesh Nagabhushana 1349*56b2bdd1SGireesh Nagabhushana #define S_DDP_INVALID_TAG 22 1350*56b2bdd1SGireesh Nagabhushana #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1351*56b2bdd1SGireesh Nagabhushana #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1352*56b2bdd1SGireesh Nagabhushana 1353*56b2bdd1SGireesh Nagabhushana #define S_DDP_ULIMIT_ERR 23 1354*56b2bdd1SGireesh Nagabhushana #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1355*56b2bdd1SGireesh Nagabhushana #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1356*56b2bdd1SGireesh Nagabhushana 1357*56b2bdd1SGireesh Nagabhushana #define S_DDP_OFFSET_ERR 24 1358*56b2bdd1SGireesh Nagabhushana #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1359*56b2bdd1SGireesh Nagabhushana #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1360*56b2bdd1SGireesh Nagabhushana 1361*56b2bdd1SGireesh Nagabhushana #define S_DDP_COLOR_ERR 25 1362*56b2bdd1SGireesh Nagabhushana #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1363*56b2bdd1SGireesh Nagabhushana #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1364*56b2bdd1SGireesh Nagabhushana 1365*56b2bdd1SGireesh Nagabhushana #define S_DDP_TID_MISMATCH 26 1366*56b2bdd1SGireesh Nagabhushana #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1367*56b2bdd1SGireesh Nagabhushana #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1368*56b2bdd1SGireesh Nagabhushana 1369*56b2bdd1SGireesh Nagabhushana #define S_DDP_INVALID_PPOD 27 1370*56b2bdd1SGireesh Nagabhushana #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1371*56b2bdd1SGireesh Nagabhushana #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1372*56b2bdd1SGireesh Nagabhushana 1373*56b2bdd1SGireesh Nagabhushana #define S_DDP_ULP_MODE 28 1374*56b2bdd1SGireesh Nagabhushana #define M_DDP_ULP_MODE 0xF 1375*56b2bdd1SGireesh Nagabhushana #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1376*56b2bdd1SGireesh Nagabhushana #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1377*56b2bdd1SGireesh Nagabhushana 1378*56b2bdd1SGireesh Nagabhushana /* cpl_rx_{data,fcoe}_ddp.ddp_report fields */ 1379*56b2bdd1SGireesh Nagabhushana #define S_DDP_OFFSET 0 1380*56b2bdd1SGireesh Nagabhushana #define M_DDP_OFFSET 0xFFFFFF 1381*56b2bdd1SGireesh Nagabhushana #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1382*56b2bdd1SGireesh Nagabhushana #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1383*56b2bdd1SGireesh Nagabhushana 1384*56b2bdd1SGireesh Nagabhushana #define S_DDP_DACK_MODE 24 1385*56b2bdd1SGireesh Nagabhushana #define M_DDP_DACK_MODE 0x3 1386*56b2bdd1SGireesh Nagabhushana #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1387*56b2bdd1SGireesh Nagabhushana #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1388*56b2bdd1SGireesh Nagabhushana 1389*56b2bdd1SGireesh Nagabhushana #define S_DDP_BUF_IDX 26 1390*56b2bdd1SGireesh Nagabhushana #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1391*56b2bdd1SGireesh Nagabhushana #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1392*56b2bdd1SGireesh Nagabhushana 1393*56b2bdd1SGireesh Nagabhushana #define S_DDP_URG 27 1394*56b2bdd1SGireesh Nagabhushana #define V_DDP_URG(x) ((x) << S_DDP_URG) 1395*56b2bdd1SGireesh Nagabhushana #define F_DDP_URG V_DDP_URG(1U) 1396*56b2bdd1SGireesh Nagabhushana 1397*56b2bdd1SGireesh Nagabhushana #define S_DDP_PSH 28 1398*56b2bdd1SGireesh Nagabhushana #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1399*56b2bdd1SGireesh Nagabhushana #define F_DDP_PSH V_DDP_PSH(1U) 1400*56b2bdd1SGireesh Nagabhushana 1401*56b2bdd1SGireesh Nagabhushana #define S_DDP_BUF_COMPLETE 29 1402*56b2bdd1SGireesh Nagabhushana #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1403*56b2bdd1SGireesh Nagabhushana #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1404*56b2bdd1SGireesh Nagabhushana 1405*56b2bdd1SGireesh Nagabhushana #define S_DDP_BUF_TIMED_OUT 30 1406*56b2bdd1SGireesh Nagabhushana #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1407*56b2bdd1SGireesh Nagabhushana #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1408*56b2bdd1SGireesh Nagabhushana 1409*56b2bdd1SGireesh Nagabhushana #define S_DDP_INV 31 1410*56b2bdd1SGireesh Nagabhushana #define V_DDP_INV(x) ((x) << S_DDP_INV) 1411*56b2bdd1SGireesh Nagabhushana #define F_DDP_INV V_DDP_INV(1U) 1412*56b2bdd1SGireesh Nagabhushana 1413*56b2bdd1SGireesh Nagabhushana struct cpl_rx_pkt { 1414*56b2bdd1SGireesh Nagabhushana RSS_HDR 1415*56b2bdd1SGireesh Nagabhushana __u8 opcode; 1416*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 1417*56b2bdd1SGireesh Nagabhushana __u8 iff:4; 1418*56b2bdd1SGireesh Nagabhushana __u8 csum_calc:1; 1419*56b2bdd1SGireesh Nagabhushana __u8 ipmi_pkt:1; 1420*56b2bdd1SGireesh Nagabhushana __u8 vlan_ex:1; 1421*56b2bdd1SGireesh Nagabhushana __u8 ip_frag:1; 1422*56b2bdd1SGireesh Nagabhushana #else 1423*56b2bdd1SGireesh Nagabhushana __u8 ip_frag:1; 1424*56b2bdd1SGireesh Nagabhushana __u8 vlan_ex:1; 1425*56b2bdd1SGireesh Nagabhushana __u8 ipmi_pkt:1; 1426*56b2bdd1SGireesh Nagabhushana __u8 csum_calc:1; 1427*56b2bdd1SGireesh Nagabhushana __u8 iff:4; 1428*56b2bdd1SGireesh Nagabhushana #endif 1429*56b2bdd1SGireesh Nagabhushana __be16 csum; 1430*56b2bdd1SGireesh Nagabhushana __be16 vlan; 1431*56b2bdd1SGireesh Nagabhushana __be16 len; 1432*56b2bdd1SGireesh Nagabhushana __be32 l2info; 1433*56b2bdd1SGireesh Nagabhushana __be16 hdr_len; 1434*56b2bdd1SGireesh Nagabhushana __be16 err_vec; 1435*56b2bdd1SGireesh Nagabhushana }; 1436*56b2bdd1SGireesh Nagabhushana 1437*56b2bdd1SGireesh Nagabhushana /* rx_pkt.l2info fields */ 1438*56b2bdd1SGireesh Nagabhushana #define S_RX_ETHHDR_LEN 0 1439*56b2bdd1SGireesh Nagabhushana #define M_RX_ETHHDR_LEN 0x1F 1440*56b2bdd1SGireesh Nagabhushana #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1441*56b2bdd1SGireesh Nagabhushana #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1442*56b2bdd1SGireesh Nagabhushana 1443*56b2bdd1SGireesh Nagabhushana #define S_RX_PKTYPE 5 1444*56b2bdd1SGireesh Nagabhushana #define M_RX_PKTYPE 0x7 1445*56b2bdd1SGireesh Nagabhushana #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1446*56b2bdd1SGireesh Nagabhushana #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1447*56b2bdd1SGireesh Nagabhushana 1448*56b2bdd1SGireesh Nagabhushana #define S_RX_MACIDX 8 1449*56b2bdd1SGireesh Nagabhushana #define M_RX_MACIDX 0x1FF 1450*56b2bdd1SGireesh Nagabhushana #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1451*56b2bdd1SGireesh Nagabhushana #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1452*56b2bdd1SGireesh Nagabhushana 1453*56b2bdd1SGireesh Nagabhushana #define S_RX_DATYPE 18 1454*56b2bdd1SGireesh Nagabhushana #define M_RX_DATYPE 0x3 1455*56b2bdd1SGireesh Nagabhushana #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1456*56b2bdd1SGireesh Nagabhushana #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1457*56b2bdd1SGireesh Nagabhushana 1458*56b2bdd1SGireesh Nagabhushana #define S_RXF_PSH 20 1459*56b2bdd1SGireesh Nagabhushana #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1460*56b2bdd1SGireesh Nagabhushana #define F_RXF_PSH V_RXF_PSH(1U) 1461*56b2bdd1SGireesh Nagabhushana 1462*56b2bdd1SGireesh Nagabhushana #define S_RXF_SYN 21 1463*56b2bdd1SGireesh Nagabhushana #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1464*56b2bdd1SGireesh Nagabhushana #define F_RXF_SYN V_RXF_SYN(1U) 1465*56b2bdd1SGireesh Nagabhushana 1466*56b2bdd1SGireesh Nagabhushana #define S_RXF_UDP 22 1467*56b2bdd1SGireesh Nagabhushana #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1468*56b2bdd1SGireesh Nagabhushana #define F_RXF_UDP V_RXF_UDP(1U) 1469*56b2bdd1SGireesh Nagabhushana 1470*56b2bdd1SGireesh Nagabhushana #define S_RXF_TCP 23 1471*56b2bdd1SGireesh Nagabhushana #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1472*56b2bdd1SGireesh Nagabhushana #define F_RXF_TCP V_RXF_TCP(1U) 1473*56b2bdd1SGireesh Nagabhushana 1474*56b2bdd1SGireesh Nagabhushana #define S_RXF_IP 24 1475*56b2bdd1SGireesh Nagabhushana #define V_RXF_IP(x) ((x) << S_RXF_IP) 1476*56b2bdd1SGireesh Nagabhushana #define F_RXF_IP V_RXF_IP(1U) 1477*56b2bdd1SGireesh Nagabhushana 1478*56b2bdd1SGireesh Nagabhushana #define S_RXF_IP6 25 1479*56b2bdd1SGireesh Nagabhushana #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1480*56b2bdd1SGireesh Nagabhushana #define F_RXF_IP6 V_RXF_IP6(1U) 1481*56b2bdd1SGireesh Nagabhushana 1482*56b2bdd1SGireesh Nagabhushana #define S_RXF_SYN_COOKIE 26 1483*56b2bdd1SGireesh Nagabhushana #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1484*56b2bdd1SGireesh Nagabhushana #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1485*56b2bdd1SGireesh Nagabhushana 1486*56b2bdd1SGireesh Nagabhushana #define S_RXF_FCOE 26 1487*56b2bdd1SGireesh Nagabhushana #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1488*56b2bdd1SGireesh Nagabhushana #define F_RXF_FCOE V_RXF_FCOE(1U) 1489*56b2bdd1SGireesh Nagabhushana 1490*56b2bdd1SGireesh Nagabhushana #define S_RXF_LRO 27 1491*56b2bdd1SGireesh Nagabhushana #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1492*56b2bdd1SGireesh Nagabhushana #define F_RXF_LRO V_RXF_LRO(1U) 1493*56b2bdd1SGireesh Nagabhushana 1494*56b2bdd1SGireesh Nagabhushana #define S_RX_CHAN 28 1495*56b2bdd1SGireesh Nagabhushana #define M_RX_CHAN 0xF 1496*56b2bdd1SGireesh Nagabhushana #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1497*56b2bdd1SGireesh Nagabhushana #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1498*56b2bdd1SGireesh Nagabhushana 1499*56b2bdd1SGireesh Nagabhushana /* rx_pkt.hdr_len fields */ 1500*56b2bdd1SGireesh Nagabhushana #define S_RX_TCPHDR_LEN 0 1501*56b2bdd1SGireesh Nagabhushana #define M_RX_TCPHDR_LEN 0x3F 1502*56b2bdd1SGireesh Nagabhushana #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1503*56b2bdd1SGireesh Nagabhushana #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1504*56b2bdd1SGireesh Nagabhushana 1505*56b2bdd1SGireesh Nagabhushana #define S_RX_IPHDR_LEN 6 1506*56b2bdd1SGireesh Nagabhushana #define M_RX_IPHDR_LEN 0x3FF 1507*56b2bdd1SGireesh Nagabhushana #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1508*56b2bdd1SGireesh Nagabhushana #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1509*56b2bdd1SGireesh Nagabhushana 1510*56b2bdd1SGireesh Nagabhushana /* rx_pkt.err_vec fields */ 1511*56b2bdd1SGireesh Nagabhushana #define S_RXERR_OR 0 1512*56b2bdd1SGireesh Nagabhushana #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1513*56b2bdd1SGireesh Nagabhushana #define F_RXERR_OR V_RXERR_OR(1U) 1514*56b2bdd1SGireesh Nagabhushana 1515*56b2bdd1SGireesh Nagabhushana #define S_RXERR_MAC 1 1516*56b2bdd1SGireesh Nagabhushana #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1517*56b2bdd1SGireesh Nagabhushana #define F_RXERR_MAC V_RXERR_MAC(1U) 1518*56b2bdd1SGireesh Nagabhushana 1519*56b2bdd1SGireesh Nagabhushana #define S_RXERR_IPVERS 2 1520*56b2bdd1SGireesh Nagabhushana #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1521*56b2bdd1SGireesh Nagabhushana #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1522*56b2bdd1SGireesh Nagabhushana 1523*56b2bdd1SGireesh Nagabhushana #define S_RXERR_FRAG 3 1524*56b2bdd1SGireesh Nagabhushana #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1525*56b2bdd1SGireesh Nagabhushana #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1526*56b2bdd1SGireesh Nagabhushana 1527*56b2bdd1SGireesh Nagabhushana #define S_RXERR_ATTACK 4 1528*56b2bdd1SGireesh Nagabhushana #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1529*56b2bdd1SGireesh Nagabhushana #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1530*56b2bdd1SGireesh Nagabhushana 1531*56b2bdd1SGireesh Nagabhushana #define S_RXERR_ETHHDR_LEN 5 1532*56b2bdd1SGireesh Nagabhushana #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1533*56b2bdd1SGireesh Nagabhushana #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1534*56b2bdd1SGireesh Nagabhushana 1535*56b2bdd1SGireesh Nagabhushana #define S_RXERR_IPHDR_LEN 6 1536*56b2bdd1SGireesh Nagabhushana #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1537*56b2bdd1SGireesh Nagabhushana #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1538*56b2bdd1SGireesh Nagabhushana 1539*56b2bdd1SGireesh Nagabhushana #define S_RXERR_TCPHDR_LEN 7 1540*56b2bdd1SGireesh Nagabhushana #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1541*56b2bdd1SGireesh Nagabhushana #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1542*56b2bdd1SGireesh Nagabhushana 1543*56b2bdd1SGireesh Nagabhushana #define S_RXERR_PKT_LEN 8 1544*56b2bdd1SGireesh Nagabhushana #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1545*56b2bdd1SGireesh Nagabhushana #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1546*56b2bdd1SGireesh Nagabhushana 1547*56b2bdd1SGireesh Nagabhushana #define S_RXERR_TCP_OPT 9 1548*56b2bdd1SGireesh Nagabhushana #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1549*56b2bdd1SGireesh Nagabhushana #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1550*56b2bdd1SGireesh Nagabhushana 1551*56b2bdd1SGireesh Nagabhushana #define S_RXERR_IPCSUM 12 1552*56b2bdd1SGireesh Nagabhushana #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1553*56b2bdd1SGireesh Nagabhushana #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1554*56b2bdd1SGireesh Nagabhushana 1555*56b2bdd1SGireesh Nagabhushana #define S_RXERR_CSUM 13 1556*56b2bdd1SGireesh Nagabhushana #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1557*56b2bdd1SGireesh Nagabhushana #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1558*56b2bdd1SGireesh Nagabhushana 1559*56b2bdd1SGireesh Nagabhushana #define S_RXERR_PING 14 1560*56b2bdd1SGireesh Nagabhushana #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1561*56b2bdd1SGireesh Nagabhushana #define F_RXERR_PING V_RXERR_PING(1U) 1562*56b2bdd1SGireesh Nagabhushana 1563*56b2bdd1SGireesh Nagabhushana struct cpl_trace_pkt { 1564*56b2bdd1SGireesh Nagabhushana RSS_HDR 1565*56b2bdd1SGireesh Nagabhushana __u8 opcode; 1566*56b2bdd1SGireesh Nagabhushana __u8 intf; 1567*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 1568*56b2bdd1SGireesh Nagabhushana __u8 runt:4; 1569*56b2bdd1SGireesh Nagabhushana __u8 filter_hit:4; 1570*56b2bdd1SGireesh Nagabhushana __u8 :6; 1571*56b2bdd1SGireesh Nagabhushana __u8 err:1; 1572*56b2bdd1SGireesh Nagabhushana __u8 trunc:1; 1573*56b2bdd1SGireesh Nagabhushana #else 1574*56b2bdd1SGireesh Nagabhushana __u8 filter_hit:4; 1575*56b2bdd1SGireesh Nagabhushana __u8 runt:4; 1576*56b2bdd1SGireesh Nagabhushana __u8 trunc:1; 1577*56b2bdd1SGireesh Nagabhushana __u8 err:1; 1578*56b2bdd1SGireesh Nagabhushana __u8 :6; 1579*56b2bdd1SGireesh Nagabhushana #endif 1580*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1581*56b2bdd1SGireesh Nagabhushana __be16 len; 1582*56b2bdd1SGireesh Nagabhushana __be64 tstamp; 1583*56b2bdd1SGireesh Nagabhushana }; 1584*56b2bdd1SGireesh Nagabhushana 1585*56b2bdd1SGireesh Nagabhushana struct cpl_rte_delete_req { 1586*56b2bdd1SGireesh Nagabhushana WR_HDR; 1587*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1588*56b2bdd1SGireesh Nagabhushana __be32 params; 1589*56b2bdd1SGireesh Nagabhushana }; 1590*56b2bdd1SGireesh Nagabhushana 1591*56b2bdd1SGireesh Nagabhushana /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1592*56b2bdd1SGireesh Nagabhushana #define S_RTE_REQ_LUT_IX 8 1593*56b2bdd1SGireesh Nagabhushana #define M_RTE_REQ_LUT_IX 0x7FF 1594*56b2bdd1SGireesh Nagabhushana #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1595*56b2bdd1SGireesh Nagabhushana #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1596*56b2bdd1SGireesh Nagabhushana 1597*56b2bdd1SGireesh Nagabhushana #define S_RTE_REQ_LUT_BASE 19 1598*56b2bdd1SGireesh Nagabhushana #define M_RTE_REQ_LUT_BASE 0x7FF 1599*56b2bdd1SGireesh Nagabhushana #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1600*56b2bdd1SGireesh Nagabhushana #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1601*56b2bdd1SGireesh Nagabhushana 1602*56b2bdd1SGireesh Nagabhushana #define S_RTE_READ_REQ_SELECT 31 1603*56b2bdd1SGireesh Nagabhushana #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1604*56b2bdd1SGireesh Nagabhushana #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1605*56b2bdd1SGireesh Nagabhushana 1606*56b2bdd1SGireesh Nagabhushana struct cpl_rte_delete_rpl { 1607*56b2bdd1SGireesh Nagabhushana RSS_HDR 1608*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1609*56b2bdd1SGireesh Nagabhushana __u8 status; 1610*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 1611*56b2bdd1SGireesh Nagabhushana }; 1612*56b2bdd1SGireesh Nagabhushana 1613*56b2bdd1SGireesh Nagabhushana struct cpl_rte_write_req { 1614*56b2bdd1SGireesh Nagabhushana WR_HDR; 1615*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1616*56b2bdd1SGireesh Nagabhushana __u32 write_sel; 1617*56b2bdd1SGireesh Nagabhushana __be32 lut_params; 1618*56b2bdd1SGireesh Nagabhushana __be32 l2t_idx; 1619*56b2bdd1SGireesh Nagabhushana __be32 netmask; 1620*56b2bdd1SGireesh Nagabhushana __be32 faddr; 1621*56b2bdd1SGireesh Nagabhushana }; 1622*56b2bdd1SGireesh Nagabhushana 1623*56b2bdd1SGireesh Nagabhushana /* cpl_rte_write_req.write_sel fields */ 1624*56b2bdd1SGireesh Nagabhushana #define S_RTE_WR_L2TIDX 31 1625*56b2bdd1SGireesh Nagabhushana #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1626*56b2bdd1SGireesh Nagabhushana #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1627*56b2bdd1SGireesh Nagabhushana 1628*56b2bdd1SGireesh Nagabhushana #define S_RTE_WR_FADDR 30 1629*56b2bdd1SGireesh Nagabhushana #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1630*56b2bdd1SGireesh Nagabhushana #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1631*56b2bdd1SGireesh Nagabhushana 1632*56b2bdd1SGireesh Nagabhushana /* cpl_rte_write_req.lut_params fields */ 1633*56b2bdd1SGireesh Nagabhushana #define S_RTE_WR_LUT_IX 10 1634*56b2bdd1SGireesh Nagabhushana #define M_RTE_WR_LUT_IX 0x7FF 1635*56b2bdd1SGireesh Nagabhushana #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1636*56b2bdd1SGireesh Nagabhushana #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1637*56b2bdd1SGireesh Nagabhushana 1638*56b2bdd1SGireesh Nagabhushana #define S_RTE_WR_LUT_BASE 21 1639*56b2bdd1SGireesh Nagabhushana #define M_RTE_WR_LUT_BASE 0x7FF 1640*56b2bdd1SGireesh Nagabhushana #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1641*56b2bdd1SGireesh Nagabhushana #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1642*56b2bdd1SGireesh Nagabhushana 1643*56b2bdd1SGireesh Nagabhushana struct cpl_rte_write_rpl { 1644*56b2bdd1SGireesh Nagabhushana RSS_HDR 1645*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1646*56b2bdd1SGireesh Nagabhushana __u8 status; 1647*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 1648*56b2bdd1SGireesh Nagabhushana }; 1649*56b2bdd1SGireesh Nagabhushana 1650*56b2bdd1SGireesh Nagabhushana struct cpl_rte_read_req { 1651*56b2bdd1SGireesh Nagabhushana WR_HDR; 1652*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1653*56b2bdd1SGireesh Nagabhushana __be32 params; 1654*56b2bdd1SGireesh Nagabhushana }; 1655*56b2bdd1SGireesh Nagabhushana 1656*56b2bdd1SGireesh Nagabhushana struct cpl_rte_read_rpl { 1657*56b2bdd1SGireesh Nagabhushana RSS_HDR 1658*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1659*56b2bdd1SGireesh Nagabhushana __u8 status; 1660*56b2bdd1SGireesh Nagabhushana __u8 rsvd; 1661*56b2bdd1SGireesh Nagabhushana __be16 l2t_idx; 1662*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 1663*56b2bdd1SGireesh Nagabhushana __u32 :30; 1664*56b2bdd1SGireesh Nagabhushana __u32 select:1; 1665*56b2bdd1SGireesh Nagabhushana #else 1666*56b2bdd1SGireesh Nagabhushana __u32 select:1; 1667*56b2bdd1SGireesh Nagabhushana __u32 :30; 1668*56b2bdd1SGireesh Nagabhushana #endif 1669*56b2bdd1SGireesh Nagabhushana __be32 addr; 1670*56b2bdd1SGireesh Nagabhushana }; 1671*56b2bdd1SGireesh Nagabhushana 1672*56b2bdd1SGireesh Nagabhushana struct cpl_l2t_write_req { 1673*56b2bdd1SGireesh Nagabhushana WR_HDR; 1674*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1675*56b2bdd1SGireesh Nagabhushana __be16 params; 1676*56b2bdd1SGireesh Nagabhushana __be16 l2t_idx; 1677*56b2bdd1SGireesh Nagabhushana __be16 vlan; 1678*56b2bdd1SGireesh Nagabhushana __u8 dst_mac[6]; 1679*56b2bdd1SGireesh Nagabhushana }; 1680*56b2bdd1SGireesh Nagabhushana 1681*56b2bdd1SGireesh Nagabhushana /* cpl_l2t_write_req.params fields */ 1682*56b2bdd1SGireesh Nagabhushana #define S_L2T_W_INFO 2 1683*56b2bdd1SGireesh Nagabhushana #define M_L2T_W_INFO 0x3F 1684*56b2bdd1SGireesh Nagabhushana #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1685*56b2bdd1SGireesh Nagabhushana #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1686*56b2bdd1SGireesh Nagabhushana 1687*56b2bdd1SGireesh Nagabhushana #define S_L2T_W_PORT 8 1688*56b2bdd1SGireesh Nagabhushana #define M_L2T_W_PORT 0xF 1689*56b2bdd1SGireesh Nagabhushana #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1690*56b2bdd1SGireesh Nagabhushana #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1691*56b2bdd1SGireesh Nagabhushana 1692*56b2bdd1SGireesh Nagabhushana #define S_L2T_W_NOREPLY 15 1693*56b2bdd1SGireesh Nagabhushana #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1694*56b2bdd1SGireesh Nagabhushana #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1695*56b2bdd1SGireesh Nagabhushana 1696*56b2bdd1SGireesh Nagabhushana struct cpl_l2t_write_rpl { 1697*56b2bdd1SGireesh Nagabhushana RSS_HDR 1698*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1699*56b2bdd1SGireesh Nagabhushana __u8 status; 1700*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 1701*56b2bdd1SGireesh Nagabhushana }; 1702*56b2bdd1SGireesh Nagabhushana 1703*56b2bdd1SGireesh Nagabhushana struct cpl_l2t_read_req { 1704*56b2bdd1SGireesh Nagabhushana WR_HDR; 1705*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1706*56b2bdd1SGireesh Nagabhushana __be32 l2t_idx; 1707*56b2bdd1SGireesh Nagabhushana }; 1708*56b2bdd1SGireesh Nagabhushana 1709*56b2bdd1SGireesh Nagabhushana struct cpl_l2t_read_rpl { 1710*56b2bdd1SGireesh Nagabhushana RSS_HDR 1711*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1712*56b2bdd1SGireesh Nagabhushana __u8 status; 1713*56b2bdd1SGireesh Nagabhushana #if defined(__LITTLE_ENDIAN_BITFIELD) 1714*56b2bdd1SGireesh Nagabhushana __u8 :4; 1715*56b2bdd1SGireesh Nagabhushana __u8 iff:4; 1716*56b2bdd1SGireesh Nagabhushana #else 1717*56b2bdd1SGireesh Nagabhushana __u8 iff:4; 1718*56b2bdd1SGireesh Nagabhushana __u8 :4; 1719*56b2bdd1SGireesh Nagabhushana #endif 1720*56b2bdd1SGireesh Nagabhushana __be16 vlan; 1721*56b2bdd1SGireesh Nagabhushana __be16 info; 1722*56b2bdd1SGireesh Nagabhushana __u8 dst_mac[6]; 1723*56b2bdd1SGireesh Nagabhushana }; 1724*56b2bdd1SGireesh Nagabhushana 1725*56b2bdd1SGireesh Nagabhushana struct cpl_smt_write_req { 1726*56b2bdd1SGireesh Nagabhushana WR_HDR; 1727*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1728*56b2bdd1SGireesh Nagabhushana __be32 params; 1729*56b2bdd1SGireesh Nagabhushana __be16 pfvf1; 1730*56b2bdd1SGireesh Nagabhushana __u8 src_mac1[6]; 1731*56b2bdd1SGireesh Nagabhushana __be16 pfvf0; 1732*56b2bdd1SGireesh Nagabhushana __u8 src_mac0[6]; 1733*56b2bdd1SGireesh Nagabhushana }; 1734*56b2bdd1SGireesh Nagabhushana 1735*56b2bdd1SGireesh Nagabhushana /* cpl_smt_{read,write}_req.params fields */ 1736*56b2bdd1SGireesh Nagabhushana #define S_SMTW_OVLAN_IDX 16 1737*56b2bdd1SGireesh Nagabhushana #define M_SMTW_OVLAN_IDX 0xF 1738*56b2bdd1SGireesh Nagabhushana #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1739*56b2bdd1SGireesh Nagabhushana #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1740*56b2bdd1SGireesh Nagabhushana 1741*56b2bdd1SGireesh Nagabhushana #define S_SMTW_IDX 20 1742*56b2bdd1SGireesh Nagabhushana #define M_SMTW_IDX 0x7F 1743*56b2bdd1SGireesh Nagabhushana #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 1744*56b2bdd1SGireesh Nagabhushana #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 1745*56b2bdd1SGireesh Nagabhushana 1746*56b2bdd1SGireesh Nagabhushana #define S_SMTW_NORPL 31 1747*56b2bdd1SGireesh Nagabhushana #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 1748*56b2bdd1SGireesh Nagabhushana #define F_SMTW_NORPL V_SMTW_NORPL(1U) 1749*56b2bdd1SGireesh Nagabhushana 1750*56b2bdd1SGireesh Nagabhushana /* cpl_smt_{read,write}_req.pfvf? fields */ 1751*56b2bdd1SGireesh Nagabhushana #define S_SMTW_VF 0 1752*56b2bdd1SGireesh Nagabhushana #define M_SMTW_VF 0xFF 1753*56b2bdd1SGireesh Nagabhushana #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 1754*56b2bdd1SGireesh Nagabhushana #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 1755*56b2bdd1SGireesh Nagabhushana 1756*56b2bdd1SGireesh Nagabhushana #define S_SMTW_PF 8 1757*56b2bdd1SGireesh Nagabhushana #define M_SMTW_PF 0x7 1758*56b2bdd1SGireesh Nagabhushana #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 1759*56b2bdd1SGireesh Nagabhushana #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 1760*56b2bdd1SGireesh Nagabhushana 1761*56b2bdd1SGireesh Nagabhushana #define S_SMTW_VF_VLD 11 1762*56b2bdd1SGireesh Nagabhushana #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 1763*56b2bdd1SGireesh Nagabhushana #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 1764*56b2bdd1SGireesh Nagabhushana 1765*56b2bdd1SGireesh Nagabhushana struct cpl_smt_write_rpl { 1766*56b2bdd1SGireesh Nagabhushana RSS_HDR 1767*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1768*56b2bdd1SGireesh Nagabhushana __u8 status; 1769*56b2bdd1SGireesh Nagabhushana __u8 rsvd[3]; 1770*56b2bdd1SGireesh Nagabhushana }; 1771*56b2bdd1SGireesh Nagabhushana 1772*56b2bdd1SGireesh Nagabhushana struct cpl_smt_read_req { 1773*56b2bdd1SGireesh Nagabhushana WR_HDR; 1774*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1775*56b2bdd1SGireesh Nagabhushana __be32 params; 1776*56b2bdd1SGireesh Nagabhushana }; 1777*56b2bdd1SGireesh Nagabhushana 1778*56b2bdd1SGireesh Nagabhushana struct cpl_smt_read_rpl { 1779*56b2bdd1SGireesh Nagabhushana RSS_HDR 1780*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1781*56b2bdd1SGireesh Nagabhushana __u8 status; 1782*56b2bdd1SGireesh Nagabhushana __u8 ovlan_idx; 1783*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1784*56b2bdd1SGireesh Nagabhushana __be16 pfvf1; 1785*56b2bdd1SGireesh Nagabhushana __u8 src_mac1[6]; 1786*56b2bdd1SGireesh Nagabhushana __be16 pfvf0; 1787*56b2bdd1SGireesh Nagabhushana __u8 src_mac0[6]; 1788*56b2bdd1SGireesh Nagabhushana }; 1789*56b2bdd1SGireesh Nagabhushana 1790*56b2bdd1SGireesh Nagabhushana struct cpl_barrier { 1791*56b2bdd1SGireesh Nagabhushana WR_HDR; 1792*56b2bdd1SGireesh Nagabhushana __u8 opcode; 1793*56b2bdd1SGireesh Nagabhushana __u8 chan_map; 1794*56b2bdd1SGireesh Nagabhushana __be16 rsvd0; 1795*56b2bdd1SGireesh Nagabhushana __be32 rsvd1; 1796*56b2bdd1SGireesh Nagabhushana }; 1797*56b2bdd1SGireesh Nagabhushana 1798*56b2bdd1SGireesh Nagabhushana /* cpl_barrier.chan_map fields */ 1799*56b2bdd1SGireesh Nagabhushana #define S_CHAN_MAP 4 1800*56b2bdd1SGireesh Nagabhushana #define M_CHAN_MAP 0xF 1801*56b2bdd1SGireesh Nagabhushana #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 1802*56b2bdd1SGireesh Nagabhushana #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 1803*56b2bdd1SGireesh Nagabhushana 1804*56b2bdd1SGireesh Nagabhushana struct cpl_error { 1805*56b2bdd1SGireesh Nagabhushana RSS_HDR 1806*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1807*56b2bdd1SGireesh Nagabhushana __be32 error; 1808*56b2bdd1SGireesh Nagabhushana }; 1809*56b2bdd1SGireesh Nagabhushana 1810*56b2bdd1SGireesh Nagabhushana struct cpl_hit_notify { 1811*56b2bdd1SGireesh Nagabhushana RSS_HDR 1812*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1813*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 1814*56b2bdd1SGireesh Nagabhushana __be32 info; 1815*56b2bdd1SGireesh Nagabhushana __be32 reason; 1816*56b2bdd1SGireesh Nagabhushana }; 1817*56b2bdd1SGireesh Nagabhushana 1818*56b2bdd1SGireesh Nagabhushana struct cpl_pkt_notify { 1819*56b2bdd1SGireesh Nagabhushana RSS_HDR 1820*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1821*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1822*56b2bdd1SGireesh Nagabhushana __be16 len; 1823*56b2bdd1SGireesh Nagabhushana __be32 info; 1824*56b2bdd1SGireesh Nagabhushana __be32 reason; 1825*56b2bdd1SGireesh Nagabhushana }; 1826*56b2bdd1SGireesh Nagabhushana 1827*56b2bdd1SGireesh Nagabhushana /* cpl_{hit,pkt}_notify.info fields */ 1828*56b2bdd1SGireesh Nagabhushana #define S_NTFY_MAC_IDX 0 1829*56b2bdd1SGireesh Nagabhushana #define M_NTFY_MAC_IDX 0x1FF 1830*56b2bdd1SGireesh Nagabhushana #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 1831*56b2bdd1SGireesh Nagabhushana #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 1832*56b2bdd1SGireesh Nagabhushana 1833*56b2bdd1SGireesh Nagabhushana #define S_NTFY_INTF 10 1834*56b2bdd1SGireesh Nagabhushana #define M_NTFY_INTF 0xF 1835*56b2bdd1SGireesh Nagabhushana #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 1836*56b2bdd1SGireesh Nagabhushana #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 1837*56b2bdd1SGireesh Nagabhushana 1838*56b2bdd1SGireesh Nagabhushana #define S_NTFY_TCPHDR_LEN 14 1839*56b2bdd1SGireesh Nagabhushana #define M_NTFY_TCPHDR_LEN 0xF 1840*56b2bdd1SGireesh Nagabhushana #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 1841*56b2bdd1SGireesh Nagabhushana #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 1842*56b2bdd1SGireesh Nagabhushana 1843*56b2bdd1SGireesh Nagabhushana #define S_NTFY_IPHDR_LEN 18 1844*56b2bdd1SGireesh Nagabhushana #define M_NTFY_IPHDR_LEN 0x1FF 1845*56b2bdd1SGireesh Nagabhushana #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 1846*56b2bdd1SGireesh Nagabhushana #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 1847*56b2bdd1SGireesh Nagabhushana 1848*56b2bdd1SGireesh Nagabhushana #define S_NTFY_ETHHDR_LEN 27 1849*56b2bdd1SGireesh Nagabhushana #define M_NTFY_ETHHDR_LEN 0x1F 1850*56b2bdd1SGireesh Nagabhushana #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 1851*56b2bdd1SGireesh Nagabhushana #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 1852*56b2bdd1SGireesh Nagabhushana 1853*56b2bdd1SGireesh Nagabhushana struct cpl_rdma_terminate { 1854*56b2bdd1SGireesh Nagabhushana RSS_HDR 1855*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1856*56b2bdd1SGireesh Nagabhushana __be16 rsvd; 1857*56b2bdd1SGireesh Nagabhushana __be16 len; 1858*56b2bdd1SGireesh Nagabhushana }; 1859*56b2bdd1SGireesh Nagabhushana 1860*56b2bdd1SGireesh Nagabhushana struct cpl_set_le_req { 1861*56b2bdd1SGireesh Nagabhushana WR_HDR; 1862*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1863*56b2bdd1SGireesh Nagabhushana __be16 reply_ctrl; 1864*56b2bdd1SGireesh Nagabhushana __be16 params; 1865*56b2bdd1SGireesh Nagabhushana __be64 mask_hi; 1866*56b2bdd1SGireesh Nagabhushana __be64 mask_lo; 1867*56b2bdd1SGireesh Nagabhushana __be64 val_hi; 1868*56b2bdd1SGireesh Nagabhushana __be64 val_lo; 1869*56b2bdd1SGireesh Nagabhushana }; 1870*56b2bdd1SGireesh Nagabhushana 1871*56b2bdd1SGireesh Nagabhushana /* cpl_set_le_req.reply_ctrl additional fields */ 1872*56b2bdd1SGireesh Nagabhushana #define S_LE_REQ_IP6 13 1873*56b2bdd1SGireesh Nagabhushana #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 1874*56b2bdd1SGireesh Nagabhushana #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 1875*56b2bdd1SGireesh Nagabhushana 1876*56b2bdd1SGireesh Nagabhushana /* cpl_set_le_req.params fields */ 1877*56b2bdd1SGireesh Nagabhushana #define S_LE_CHAN 0 1878*56b2bdd1SGireesh Nagabhushana #define M_LE_CHAN 0x3 1879*56b2bdd1SGireesh Nagabhushana #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 1880*56b2bdd1SGireesh Nagabhushana #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 1881*56b2bdd1SGireesh Nagabhushana 1882*56b2bdd1SGireesh Nagabhushana #define S_LE_OFFSET 5 1883*56b2bdd1SGireesh Nagabhushana #define M_LE_OFFSET 0x7 1884*56b2bdd1SGireesh Nagabhushana #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 1885*56b2bdd1SGireesh Nagabhushana #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 1886*56b2bdd1SGireesh Nagabhushana 1887*56b2bdd1SGireesh Nagabhushana #define S_LE_MORE 8 1888*56b2bdd1SGireesh Nagabhushana #define V_LE_MORE(x) ((x) << S_LE_MORE) 1889*56b2bdd1SGireesh Nagabhushana #define F_LE_MORE V_LE_MORE(1U) 1890*56b2bdd1SGireesh Nagabhushana 1891*56b2bdd1SGireesh Nagabhushana #define S_LE_REQSIZE 9 1892*56b2bdd1SGireesh Nagabhushana #define M_LE_REQSIZE 0x7 1893*56b2bdd1SGireesh Nagabhushana #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 1894*56b2bdd1SGireesh Nagabhushana #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 1895*56b2bdd1SGireesh Nagabhushana 1896*56b2bdd1SGireesh Nagabhushana #define S_LE_REQCMD 12 1897*56b2bdd1SGireesh Nagabhushana #define M_LE_REQCMD 0xF 1898*56b2bdd1SGireesh Nagabhushana #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 1899*56b2bdd1SGireesh Nagabhushana #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 1900*56b2bdd1SGireesh Nagabhushana 1901*56b2bdd1SGireesh Nagabhushana struct cpl_set_le_rpl { 1902*56b2bdd1SGireesh Nagabhushana RSS_HDR 1903*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1904*56b2bdd1SGireesh Nagabhushana __u8 chan; 1905*56b2bdd1SGireesh Nagabhushana __u8 info; 1906*56b2bdd1SGireesh Nagabhushana __be16 len; 1907*56b2bdd1SGireesh Nagabhushana }; 1908*56b2bdd1SGireesh Nagabhushana 1909*56b2bdd1SGireesh Nagabhushana /* cpl_set_le_rpl.info fields */ 1910*56b2bdd1SGireesh Nagabhushana #define S_LE_RSPCMD 0 1911*56b2bdd1SGireesh Nagabhushana #define M_LE_RSPCMD 0xF 1912*56b2bdd1SGireesh Nagabhushana #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 1913*56b2bdd1SGireesh Nagabhushana #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 1914*56b2bdd1SGireesh Nagabhushana 1915*56b2bdd1SGireesh Nagabhushana #define S_LE_RSPSIZE 4 1916*56b2bdd1SGireesh Nagabhushana #define M_LE_RSPSIZE 0x7 1917*56b2bdd1SGireesh Nagabhushana #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 1918*56b2bdd1SGireesh Nagabhushana #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 1919*56b2bdd1SGireesh Nagabhushana 1920*56b2bdd1SGireesh Nagabhushana #define S_LE_RSPTYPE 7 1921*56b2bdd1SGireesh Nagabhushana #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 1922*56b2bdd1SGireesh Nagabhushana #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 1923*56b2bdd1SGireesh Nagabhushana 1924*56b2bdd1SGireesh Nagabhushana struct cpl_sge_egr_update { 1925*56b2bdd1SGireesh Nagabhushana RSS_HDR 1926*56b2bdd1SGireesh Nagabhushana __be32 opcode_qid; 1927*56b2bdd1SGireesh Nagabhushana __be16 cidx; 1928*56b2bdd1SGireesh Nagabhushana __be16 pidx; 1929*56b2bdd1SGireesh Nagabhushana }; 1930*56b2bdd1SGireesh Nagabhushana 1931*56b2bdd1SGireesh Nagabhushana /* cpl_sge_egr_update.ot fields */ 1932*56b2bdd1SGireesh Nagabhushana #define S_EGR_QID 0 1933*56b2bdd1SGireesh Nagabhushana #define M_EGR_QID 0x1FFFF 1934*56b2bdd1SGireesh Nagabhushana #define V_EGR_QID(x) ((x) << S_EGR_QID) 1935*56b2bdd1SGireesh Nagabhushana #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 1936*56b2bdd1SGireesh Nagabhushana 1937*56b2bdd1SGireesh Nagabhushana struct cpl_fw2_pld { 1938*56b2bdd1SGireesh Nagabhushana RSS_HDR 1939*56b2bdd1SGireesh Nagabhushana u8 opcode; 1940*56b2bdd1SGireesh Nagabhushana u8 rsvd[5]; 1941*56b2bdd1SGireesh Nagabhushana __be16 len; 1942*56b2bdd1SGireesh Nagabhushana }; 1943*56b2bdd1SGireesh Nagabhushana 1944*56b2bdd1SGireesh Nagabhushana struct cpl_fw4_pld { 1945*56b2bdd1SGireesh Nagabhushana RSS_HDR 1946*56b2bdd1SGireesh Nagabhushana u8 opcode; 1947*56b2bdd1SGireesh Nagabhushana u8 rsvd0[3]; 1948*56b2bdd1SGireesh Nagabhushana u8 type; 1949*56b2bdd1SGireesh Nagabhushana u8 rsvd1; 1950*56b2bdd1SGireesh Nagabhushana __be16 len; 1951*56b2bdd1SGireesh Nagabhushana __be64 data; 1952*56b2bdd1SGireesh Nagabhushana __be64 rsvd2; 1953*56b2bdd1SGireesh Nagabhushana }; 1954*56b2bdd1SGireesh Nagabhushana 1955*56b2bdd1SGireesh Nagabhushana struct cpl_fw6_pld { 1956*56b2bdd1SGireesh Nagabhushana RSS_HDR 1957*56b2bdd1SGireesh Nagabhushana u8 opcode; 1958*56b2bdd1SGireesh Nagabhushana u8 rsvd[5]; 1959*56b2bdd1SGireesh Nagabhushana __be16 len; 1960*56b2bdd1SGireesh Nagabhushana __be64 data[4]; 1961*56b2bdd1SGireesh Nagabhushana }; 1962*56b2bdd1SGireesh Nagabhushana 1963*56b2bdd1SGireesh Nagabhushana struct cpl_fw2_msg { 1964*56b2bdd1SGireesh Nagabhushana RSS_HDR 1965*56b2bdd1SGireesh Nagabhushana union opcode_info oi; 1966*56b2bdd1SGireesh Nagabhushana }; 1967*56b2bdd1SGireesh Nagabhushana 1968*56b2bdd1SGireesh Nagabhushana struct cpl_fw4_msg { 1969*56b2bdd1SGireesh Nagabhushana RSS_HDR 1970*56b2bdd1SGireesh Nagabhushana u8 opcode; 1971*56b2bdd1SGireesh Nagabhushana u8 type; 1972*56b2bdd1SGireesh Nagabhushana __be16 rsvd0; 1973*56b2bdd1SGireesh Nagabhushana __be32 rsvd1; 1974*56b2bdd1SGireesh Nagabhushana __be64 data[2]; 1975*56b2bdd1SGireesh Nagabhushana }; 1976*56b2bdd1SGireesh Nagabhushana 1977*56b2bdd1SGireesh Nagabhushana struct cpl_fw4_ack { 1978*56b2bdd1SGireesh Nagabhushana RSS_HDR 1979*56b2bdd1SGireesh Nagabhushana union opcode_tid ot; 1980*56b2bdd1SGireesh Nagabhushana u8 credits; 1981*56b2bdd1SGireesh Nagabhushana u8 rsvd0[2]; 1982*56b2bdd1SGireesh Nagabhushana u8 flags; 1983*56b2bdd1SGireesh Nagabhushana __be32 snd_nxt; 1984*56b2bdd1SGireesh Nagabhushana __be32 snd_una; 1985*56b2bdd1SGireesh Nagabhushana __be64 rsvd1; 1986*56b2bdd1SGireesh Nagabhushana }; 1987*56b2bdd1SGireesh Nagabhushana 1988*56b2bdd1SGireesh Nagabhushana enum { 1989*56b2bdd1SGireesh Nagabhushana CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1990*56b2bdd1SGireesh Nagabhushana CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1991*56b2bdd1SGireesh Nagabhushana CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1992*56b2bdd1SGireesh Nagabhushana }; 1993*56b2bdd1SGireesh Nagabhushana 1994*56b2bdd1SGireesh Nagabhushana struct cpl_fw6_msg { 1995*56b2bdd1SGireesh Nagabhushana RSS_HDR 1996*56b2bdd1SGireesh Nagabhushana u8 opcode; 1997*56b2bdd1SGireesh Nagabhushana u8 type; 1998*56b2bdd1SGireesh Nagabhushana __be16 rsvd0; 1999*56b2bdd1SGireesh Nagabhushana __be32 rsvd1; 2000*56b2bdd1SGireesh Nagabhushana __be64 data[4]; 2001*56b2bdd1SGireesh Nagabhushana }; 2002*56b2bdd1SGireesh Nagabhushana 2003*56b2bdd1SGireesh Nagabhushana /* cpl_fw6_msg.type values */ 2004*56b2bdd1SGireesh Nagabhushana enum { 2005*56b2bdd1SGireesh Nagabhushana FW6_TYPE_CMD_RPL = 0, 2006*56b2bdd1SGireesh Nagabhushana }; 2007*56b2bdd1SGireesh Nagabhushana 2008*56b2bdd1SGireesh Nagabhushana /* ULP_TX opcodes */ 2009*56b2bdd1SGireesh Nagabhushana enum { 2010*56b2bdd1SGireesh Nagabhushana ULP_TX_MEM_READ = 2, 2011*56b2bdd1SGireesh Nagabhushana ULP_TX_MEM_WRITE = 3, 2012*56b2bdd1SGireesh Nagabhushana ULP_TX_PKT = 4 2013*56b2bdd1SGireesh Nagabhushana }; 2014*56b2bdd1SGireesh Nagabhushana 2015*56b2bdd1SGireesh Nagabhushana enum { 2016*56b2bdd1SGireesh Nagabhushana ULP_TX_SC_NOOP = 0x80, 2017*56b2bdd1SGireesh Nagabhushana ULP_TX_SC_IMM = 0x81, 2018*56b2bdd1SGireesh Nagabhushana ULP_TX_SC_DSGL = 0x82, 2019*56b2bdd1SGireesh Nagabhushana ULP_TX_SC_ISGL = 0x83 2020*56b2bdd1SGireesh Nagabhushana }; 2021*56b2bdd1SGireesh Nagabhushana 2022*56b2bdd1SGireesh Nagabhushana #define S_ULPTX_CMD 24 2023*56b2bdd1SGireesh Nagabhushana #define M_ULPTX_CMD 0xFF 2024*56b2bdd1SGireesh Nagabhushana #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2025*56b2bdd1SGireesh Nagabhushana 2026*56b2bdd1SGireesh Nagabhushana #define S_ULPTX_LEN16 0 2027*56b2bdd1SGireesh Nagabhushana #define M_ULPTX_LEN16 0xFF 2028*56b2bdd1SGireesh Nagabhushana #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2029*56b2bdd1SGireesh Nagabhushana 2030*56b2bdd1SGireesh Nagabhushana #define S_ULP_TX_SC_MORE 23 2031*56b2bdd1SGireesh Nagabhushana #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2032*56b2bdd1SGireesh Nagabhushana #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2033*56b2bdd1SGireesh Nagabhushana 2034*56b2bdd1SGireesh Nagabhushana struct ulptx_sge_pair { 2035*56b2bdd1SGireesh Nagabhushana __be32 len[2]; 2036*56b2bdd1SGireesh Nagabhushana __be64 addr[2]; 2037*56b2bdd1SGireesh Nagabhushana }; 2038*56b2bdd1SGireesh Nagabhushana 2039*56b2bdd1SGireesh Nagabhushana struct ulptx_sgl { 2040*56b2bdd1SGireesh Nagabhushana __be32 cmd_nsge; 2041*56b2bdd1SGireesh Nagabhushana __be32 len0; 2042*56b2bdd1SGireesh Nagabhushana __be64 addr0; 2043*56b2bdd1SGireesh Nagabhushana #if !(defined C99_NOT_SUPPORTED) 2044*56b2bdd1SGireesh Nagabhushana struct ulptx_sge_pair sge[]; 2045*56b2bdd1SGireesh Nagabhushana #endif 2046*56b2bdd1SGireesh Nagabhushana }; 2047*56b2bdd1SGireesh Nagabhushana 2048*56b2bdd1SGireesh Nagabhushana struct ulptx_isge { 2049*56b2bdd1SGireesh Nagabhushana __be32 stag; 2050*56b2bdd1SGireesh Nagabhushana __be32 len; 2051*56b2bdd1SGireesh Nagabhushana __be64 target_ofst; 2052*56b2bdd1SGireesh Nagabhushana }; 2053*56b2bdd1SGireesh Nagabhushana 2054*56b2bdd1SGireesh Nagabhushana struct ulptx_isgl { 2055*56b2bdd1SGireesh Nagabhushana __be32 cmd_nisge; 2056*56b2bdd1SGireesh Nagabhushana __be32 rsvd; 2057*56b2bdd1SGireesh Nagabhushana #if !(defined C99_NOT_SUPPORTED) 2058*56b2bdd1SGireesh Nagabhushana struct ulptx_isge sge[]; 2059*56b2bdd1SGireesh Nagabhushana #endif 2060*56b2bdd1SGireesh Nagabhushana }; 2061*56b2bdd1SGireesh Nagabhushana 2062*56b2bdd1SGireesh Nagabhushana struct ulptx_idata { 2063*56b2bdd1SGireesh Nagabhushana __be32 cmd_more; 2064*56b2bdd1SGireesh Nagabhushana __be32 len; 2065*56b2bdd1SGireesh Nagabhushana }; 2066*56b2bdd1SGireesh Nagabhushana 2067*56b2bdd1SGireesh Nagabhushana #define S_ULPTX_NSGE 0 2068*56b2bdd1SGireesh Nagabhushana #define M_ULPTX_NSGE 0xFFFF 2069*56b2bdd1SGireesh Nagabhushana #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2070*56b2bdd1SGireesh Nagabhushana 2071*56b2bdd1SGireesh Nagabhushana struct ulp_mem_io { 2072*56b2bdd1SGireesh Nagabhushana WR_HDR; 2073*56b2bdd1SGireesh Nagabhushana __be32 cmd; 2074*56b2bdd1SGireesh Nagabhushana __be32 len16; /* command length */ 2075*56b2bdd1SGireesh Nagabhushana __be32 dlen; /* data length in 32-byte units */ 2076*56b2bdd1SGireesh Nagabhushana __be32 lock_addr; 2077*56b2bdd1SGireesh Nagabhushana }; 2078*56b2bdd1SGireesh Nagabhushana 2079*56b2bdd1SGireesh Nagabhushana /* additional ulp_mem_io.cmd fields */ 2080*56b2bdd1SGireesh Nagabhushana #define S_ULP_MEMIO_ORDER 23 2081*56b2bdd1SGireesh Nagabhushana #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2082*56b2bdd1SGireesh Nagabhushana #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2083*56b2bdd1SGireesh Nagabhushana 2084*56b2bdd1SGireesh Nagabhushana /* ulp_mem_io.lock_addr fields */ 2085*56b2bdd1SGireesh Nagabhushana #define S_ULP_MEMIO_ADDR 0 2086*56b2bdd1SGireesh Nagabhushana #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2087*56b2bdd1SGireesh Nagabhushana #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2088*56b2bdd1SGireesh Nagabhushana 2089*56b2bdd1SGireesh Nagabhushana #define S_ULP_MEMIO_LOCK 31 2090*56b2bdd1SGireesh Nagabhushana #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2091*56b2bdd1SGireesh Nagabhushana #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2092*56b2bdd1SGireesh Nagabhushana 2093*56b2bdd1SGireesh Nagabhushana /* ulp_mem_io.dlen fields */ 2094*56b2bdd1SGireesh Nagabhushana #define S_ULP_MEMIO_DATA_LEN 0 2095*56b2bdd1SGireesh Nagabhushana #define M_ULP_MEMIO_DATA_LEN 0x1F 2096*56b2bdd1SGireesh Nagabhushana #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2097*56b2bdd1SGireesh Nagabhushana 2098*56b2bdd1SGireesh Nagabhushana struct ulp_txpkt { 2099*56b2bdd1SGireesh Nagabhushana __be32 cmd_dest; 2100*56b2bdd1SGireesh Nagabhushana __be32 len; 2101*56b2bdd1SGireesh Nagabhushana }; 2102*56b2bdd1SGireesh Nagabhushana 2103*56b2bdd1SGireesh Nagabhushana /* ulp_txpkt.cmd_dest fields */ 2104*56b2bdd1SGireesh Nagabhushana #define S_ULP_TXPKT_DEST 16 2105*56b2bdd1SGireesh Nagabhushana #define M_ULP_TXPKT_DEST 0x3 2106*56b2bdd1SGireesh Nagabhushana #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2107*56b2bdd1SGireesh Nagabhushana 2108*56b2bdd1SGireesh Nagabhushana #define S_ULP_TXPKT_FID 4 2109*56b2bdd1SGireesh Nagabhushana #define M_ULP_TXPKT_FID 0x7ff 2110*56b2bdd1SGireesh Nagabhushana #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2111*56b2bdd1SGireesh Nagabhushana 2112*56b2bdd1SGireesh Nagabhushana #endif /* __CXGBE_T4_MSG_H */ 2113