xref: /illumos-gate/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h (revision 7e6ad4690aa1d3cbf260ef54d5e9632ae40a782e)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
14  *
15  * Copyright (C) 2003-2019 Chelsio Communications.  All rights reserved.
16  *
17  * This program is distributed in the hope that it will be useful, but WITHOUT
18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
20  * release for licensing terms and conditions.
21  */
22 #ifndef __T4_CHIP_TYPE_H__
23 #define __T4_CHIP_TYPE_H__
24 
25 /*
26  * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
27  *
28  *   V  = "4" for T4; "5" for T5, etc. or
29  *      = "a" for T4 FPGA; "b" for T4 FPGA, etc.
30  *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
31  *   PP = adapter product designation
32  *
33  * We use the "version" (V) of the adpater to code the Chip Version above
34  * but separate out the FPGA as a separate boolean as per above.
35  */
36 #define CHELSIO_PCI_ID_VER(__DeviceID)	((__DeviceID) >> 12)
37 #define CHELSIO_PCI_ID_FUNC(__DeviceID)	(((__DeviceID) >> 8) & 0xf)
38 #define CHELSIO_PCI_ID_PROD(__DeviceID)	((__DeviceID) & 0xff)
39 
40 #define CHELSIO_T4		0x4
41 #define CHELSIO_T4_FPGA		0xa
42 #define CHELSIO_T5		0x5
43 #define CHELSIO_T5_FPGA		0xb
44 #define CHELSIO_T6		0x6
45 #define CHELSIO_T6_FPGA		0xc
46 
47 /*
48  * Internally we code the Chelsio T4 Family "Chip Code" as a tuple:
49  *
50  *     (Is FPGA, Chip Version, Chip Revision)
51  *
52  * where:
53  *
54  *     Is FPGA: is 0/1 indicating whether we're working with an FPGA
55  *     Chip Version: is T4, T5, etc.
56  *     Chip Revision: is the FAB "spin" of the Chip Version.
57  */
58 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
59 #define CHELSIO_CHIP_FPGA          0x100
60 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
61 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
62 
63 enum chip_type {
64 	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
65 	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
66 	T4_FIRST_REV	= T4_A1,
67 	T4_LAST_REV	= T4_A2,
68 
69 	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
70 	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
71 	T5_FIRST_REV	= T5_A0,
72 	T5_LAST_REV	= T5_A1,
73 
74 	T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
75 	T6_FIRST_REV	= T6_A0,
76 	T6_LAST_REV	= T6_A0,
77 };
78 
79 int is_t4(enum chip_type chip);
80 int is_t5(enum chip_type chip);
81 int is_t6(enum chip_type chip);
82 int is_fpga(enum chip_type chip);
83 
84 #endif /* __T4_CHIP_TYPE_H__ */
85