1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver. 14 * 15 * Copyright (C) 2005-2019 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CHELSIO_COMMON_H 24 #define __CHELSIO_COMMON_H 25 26 #include "t4_hw.h" 27 #include "t4_chip_type.h" 28 #include "t4fw_version.h" 29 #include "t5fw_version.h" 30 #include "t6fw_version.h" 31 32 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 33 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 34 F_CPL_SWITCH | F_SGE | F_ULP_TX | F_SF) 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifndef __linux__ 41 #define __force 42 #define usleep_range(_min, _max) msleep(_max / 1000) 43 #endif 44 45 /* 46 * Firmware minimum version macros are used by t4_check_fw_version() to check 47 * if the FW is supported by the driver. 48 * Initially these macros were in t4fw_interface.h, but was removed, as the 49 * file is automatically replaced during a new FW commit. So untill these 50 * macros moves to one of the firmware header files, it has to be here. 51 */ 52 #define T4FW_MIN_VERSION_MAJOR 0x01 53 #define T4FW_MIN_VERSION_MINOR 0x04 54 #define T4FW_MIN_VERSION_MICRO 0x00 55 56 #define T5FW_MIN_VERSION_MAJOR 0x00 57 #define T5FW_MIN_VERSION_MINOR 0x00 58 #define T5FW_MIN_VERSION_MICRO 0x00 59 60 #define T6FW_MIN_VERSION_MAJOR 0x00 61 #define T6FW_MIN_VERSION_MINOR 0x00 62 #define T6FW_MIN_VERSION_MICRO 0x00 63 64 enum { 65 MAX_NPORTS = 4, /* max # of ports */ 66 SERNUM_LEN = 24, /* Serial # length */ 67 EC_LEN = 16, /* E/C length */ 68 ID_LEN = 16, /* ID length */ 69 PN_LEN = 16, /* Part Number length */ 70 MACADDR_LEN = 12, /* MAC Address length */ 71 }; 72 73 enum { 74 T4_REGMAP_SIZE = (160 * 1024), 75 T5_REGMAP_SIZE = (332 * 1024), 76 }; 77 78 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1, MEM_HMA }; 79 80 enum { 81 MEMWIN0_APERTURE = 2048, 82 MEMWIN0_BASE = 0x1b800, 83 84 MEMWIN1_APERTURE = 32768, 85 MEMWIN1_BASE = 0x28000, 86 87 MEMWIN2_APERTURE = 65536, 88 MEMWIN2_BASE = 0x30000, 89 90 MEMWIN2_APERTURE_T5 = 128 * 1024, 91 MEMWIN2_BASE_T5 = 0x60000, 92 }; 93 94 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 95 96 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 97 98 enum { 99 PAUSE_RX = 1 << 0, 100 PAUSE_TX = 1 << 1, 101 PAUSE_AUTONEG = 1 << 2 102 }; 103 typedef unsigned char cc_pause_t; 104 105 enum { 106 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 107 FEC_RS = 1 << 1, /* Reed-Solomon */ 108 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */ 109 }; 110 typedef unsigned char cc_fec_t; 111 112 enum { 113 ULP_T10DIF_ISCSI = 1 << 0, 114 ULP_T10DIF_FCOE = 1 << 1 115 }; 116 117 enum { 118 ULP_CRYPTO_LOOKASIDE = 1 << 0, 119 ULP_CRYPTO_INLINE_TLS = 1 << 1 120 }; 121 122 struct port_stats { 123 u64 tx_octets; /* total # of octets in good frames */ 124 u64 tx_frames; /* all good frames */ 125 u64 tx_bcast_frames; /* all broadcast frames */ 126 u64 tx_mcast_frames; /* all multicast frames */ 127 u64 tx_ucast_frames; /* all unicast frames */ 128 u64 tx_error_frames; /* all error frames */ 129 130 u64 tx_frames_64; /* # of Tx frames in a particular range */ 131 u64 tx_frames_65_127; 132 u64 tx_frames_128_255; 133 u64 tx_frames_256_511; 134 u64 tx_frames_512_1023; 135 u64 tx_frames_1024_1518; 136 u64 tx_frames_1519_max; 137 138 u64 tx_drop; /* # of dropped Tx frames */ 139 u64 tx_pause; /* # of transmitted pause frames */ 140 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 141 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 142 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 143 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 144 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 145 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 146 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 147 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 148 149 u64 rx_octets; /* total # of octets in good frames */ 150 u64 rx_frames; /* all good frames */ 151 u64 rx_bcast_frames; /* all broadcast frames */ 152 u64 rx_mcast_frames; /* all multicast frames */ 153 u64 rx_ucast_frames; /* all unicast frames */ 154 u64 rx_too_long; /* # of frames exceeding MTU */ 155 u64 rx_jabber; /* # of jabber frames */ 156 u64 rx_fcs_err; /* # of received frames with bad FCS */ 157 u64 rx_len_err; /* # of received frames with length error */ 158 u64 rx_symbol_err; /* symbol errors */ 159 u64 rx_runt; /* # of short frames */ 160 161 u64 rx_frames_64; /* # of Rx frames in a particular range */ 162 u64 rx_frames_65_127; 163 u64 rx_frames_128_255; 164 u64 rx_frames_256_511; 165 u64 rx_frames_512_1023; 166 u64 rx_frames_1024_1518; 167 u64 rx_frames_1519_max; 168 169 u64 rx_pause; /* # of received pause frames */ 170 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 171 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 172 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 173 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 174 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 175 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 176 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 177 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 178 179 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 180 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 181 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 182 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 183 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 184 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 185 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 186 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 187 }; 188 189 struct lb_port_stats { 190 u64 octets; 191 u64 frames; 192 u64 bcast_frames; 193 u64 mcast_frames; 194 u64 ucast_frames; 195 u64 error_frames; 196 197 u64 frames_64; 198 u64 frames_65_127; 199 u64 frames_128_255; 200 u64 frames_256_511; 201 u64 frames_512_1023; 202 u64 frames_1024_1518; 203 u64 frames_1519_max; 204 205 u64 drop; 206 207 u64 ovflow0; 208 u64 ovflow1; 209 u64 ovflow2; 210 u64 ovflow3; 211 u64 trunc0; 212 u64 trunc1; 213 u64 trunc2; 214 u64 trunc3; 215 }; 216 217 struct tp_tcp_stats { 218 u32 tcp_out_rsts; 219 u64 tcp_in_segs; 220 u64 tcp_out_segs; 221 u64 tcp_retrans_segs; 222 }; 223 224 struct tp_usm_stats { 225 u32 frames; 226 u32 drops; 227 u64 octets; 228 }; 229 230 struct tp_fcoe_stats { 231 u32 frames_ddp; 232 u32 frames_drop; 233 u64 octets_ddp; 234 }; 235 236 struct tp_err_stats { 237 u32 mac_in_errs[4]; 238 u32 hdr_in_errs[4]; 239 u32 tcp_in_errs[4]; 240 u32 tnl_cong_drops[4]; 241 u32 ofld_chan_drops[4]; 242 u32 tnl_tx_drops[4]; 243 u32 ofld_vlan_drops[4]; 244 u32 tcp6_in_errs[4]; 245 u32 ofld_no_neigh; 246 u32 ofld_cong_defer; 247 }; 248 249 struct tp_proxy_stats { 250 u32 proxy[4]; 251 }; 252 253 struct tp_cpl_stats { 254 u32 req[4]; 255 u32 rsp[4]; 256 }; 257 258 struct tp_rdma_stats { 259 u32 rqe_dfr_pkt; 260 u32 rqe_dfr_mod; 261 }; 262 263 struct sge_params { 264 u32 hps; /* host page size for our PF/VF */ 265 u32 eq_qpp; /* egress queues/page for our PF/VF */ 266 u32 iq_qpp; /* egress queues/page for our PF/VF */ 267 }; 268 269 struct tp_params { 270 unsigned int tre; /* log2 of core clocks per TP tick */ 271 unsigned int dack_re; /* DACK timer resolution */ 272 unsigned int la_mask; /* what events are recorded by TP LA */ 273 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 274 275 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 276 u32 filter_mask; 277 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 278 /* cached TP_OUT_CONFIG compressed error vector 279 * and passing outer header info for encapsulated packets. 280 */ 281 int rx_pkt_encap; 282 283 /* 284 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 285 * subset of the set of fields which may be present in the Compressed 286 * Filter Tuple portion of filters and TCP TCB connections. The 287 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 288 * Since a variable number of fields may or may not be present, their 289 * shifted field positions within the Compressed Filter Tuple may 290 * vary, or not even be present if the field isn't selected in 291 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 292 * places we store their offsets here, or a -1 if the field isn't 293 * present. 294 */ 295 int fcoe_shift; 296 int port_shift; 297 int vnic_shift; 298 int vlan_shift; 299 int tos_shift; 300 int protocol_shift; 301 int ethertype_shift; 302 int macmatch_shift; 303 int matchtype_shift; 304 int frag_shift; 305 }; 306 307 struct vpd_params { 308 unsigned int cclk; 309 u8 ec[EC_LEN + 1]; 310 u8 sn[SERNUM_LEN + 1]; 311 u8 id[ID_LEN + 1]; 312 u8 pn[PN_LEN + 1]; 313 u8 na[MACADDR_LEN + 1]; 314 }; 315 316 /* 317 * Maximum resources provisioned for a PCI PF. 318 */ 319 struct pf_resources { 320 unsigned int nvi; /* N virtual interfaces */ 321 unsigned int neq; /* N egress Qs */ 322 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 323 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 324 unsigned int niq; /* N ingress Qs */ 325 unsigned int tc; /* PCI-E traffic class */ 326 unsigned int pmask; /* port access rights mask */ 327 unsigned int nexactf; /* N exact MPS filters */ 328 unsigned int r_caps; /* read capabilities */ 329 unsigned int wx_caps; /* write/execute capabilities */ 330 }; 331 332 struct pci_params { 333 uint16_t vendor_id; 334 uint16_t device_id; 335 uint32_t vpd_cap_addr; 336 uint16_t speed; 337 uint8_t width; 338 }; 339 340 /* 341 * Firmware device log. 342 */ 343 struct devlog_params { 344 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 345 u32 start; /* start of log in firmware memory */ 346 u32 size; /* size of log */ 347 }; 348 349 /* Stores chip specific parameters */ 350 struct arch_specific_params { 351 u8 nchan; 352 u8 pm_stats_cnt; 353 u8 cng_ch_bits_log; /* congestion channel map bits width */ 354 u16 mps_rplc_size; 355 u16 vfcount; 356 u32 sge_fl_db; 357 u16 mps_tcam_size; 358 }; 359 360 struct adapter_params { 361 struct sge_params sge; 362 struct tp_params tp; 363 struct vpd_params vpd; 364 struct pf_resources pfres; 365 struct pci_params pci; 366 struct devlog_params devlog; 367 enum pcie_memwin drv_memwin; 368 369 unsigned int sf_size; /* serial flash size in bytes */ 370 unsigned int sf_nsec; /* # of flash sectors */ 371 372 unsigned int fw_vers; /* firmware version */ 373 unsigned int bs_vers; /* bootstrap version */ 374 unsigned int tp_vers; /* TP microcode version */ 375 unsigned int er_vers; /* expansion ROM version */ 376 unsigned int scfg_vers; /* Serial Configuration version */ 377 unsigned int vpd_vers; /* VPD version */ 378 379 unsigned short mtus[NMTUS]; 380 unsigned short a_wnd[NCCTRL_WIN]; 381 unsigned short b_wnd[NCCTRL_WIN]; 382 383 unsigned int mc_size; /* MC memory size */ 384 unsigned int nfilters; /* size of filter region */ 385 386 unsigned int cim_la_size; 387 388 unsigned char nports; /* # of ethernet ports */ 389 unsigned char portvec; 390 unsigned char offload; 391 392 unsigned char bypass; 393 unsigned char hash_filter; 394 395 enum chip_type chip; /* chip code */ 396 struct arch_specific_params arch; /* chip specific params */ 397 398 unsigned int ofldq_wr_cred; 399 400 unsigned int nsched_cls; /* number of traffic classes */ 401 402 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 403 unsigned int max_ird_adapter; /* Max read depth per adapter */ 404 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 405 unsigned char ulp_t10dif; /* t10dif support for ulp */ 406 unsigned char ulp_crypto; /* Crypto support */ 407 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 408 bool filter2_wr_support; /* FW support for FILTER2_WR */ 409 bool viid_smt_extn_support; /* FW returns vin and smt index? */ 410 u8 fw_caps_support; /* 32-bit Port Capabilities */ 411 412 /* 413 * MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 414 * used by the Port 415 */ 416 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 417 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 418 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 419 /* FW supports adding source mac address to TCAM */ 420 bool smac_add_support; 421 }; 422 423 /* 424 * State needed to monitor the forward progress of SGE Ingress DMA activities 425 * and possible hangs. 426 */ 427 struct sge_idma_monitor_state { 428 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 429 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 430 unsigned int idma_state[2]; /* IDMA Hang detect state */ 431 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 432 unsigned int idma_warn[2]; /* time to warning in HZ */ 433 }; 434 435 /* 436 * Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 437 * The access and execute times are signed in order to accommodate negative 438 * error returns. 439 */ 440 struct mbox_cmd { 441 u64 cmd[MBOX_LEN/8]; /* a Firmware Mailbox Command/Reply */ 442 u64 timestamp; /* OS-dependent timestamp */ 443 u32 seqno; /* sequence number */ 444 s16 access; /* time (ms) to access mailbox */ 445 s16 execute; /* time (ms) to execute */ 446 }; 447 448 struct mbox_cmd_log { 449 unsigned int size; /* number of entries in the log */ 450 unsigned int cursor; /* next position in the log to write */ 451 u32 seqno; /* next sequence number */ 452 /* variable length mailbox command log starts here */ 453 }; 454 455 struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 456 unsigned int entry_idx); 457 458 #include <t4fw_interface.h> 459 460 #define FW_VERSION(chip) ( \ 461 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 462 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 463 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 464 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 465 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 466 467 struct fw_info { 468 u8 chip; 469 char *fs_name; 470 char *fw_mod_name; 471 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 472 }; 473 474 struct trace_params { 475 u32 data[TRACE_LEN / 4]; 476 u32 mask[TRACE_LEN / 4]; 477 unsigned short snap_len; 478 unsigned short min_len; 479 unsigned char skip_ofst; 480 unsigned char skip_len; 481 unsigned char invert; 482 unsigned char port; 483 }; 484 485 /* 486 * Firmware Port Capabilities types. 487 */ 488 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 489 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 490 491 enum fw_caps { 492 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 493 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 494 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 495 }; 496 497 struct link_config { 498 fw_port_cap32_t pcaps; /* link capabilities */ 499 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 500 fw_port_cap32_t acaps; /* advertised capabilities */ 501 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 502 503 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 504 u32 speed; /* actual link speed (Mb/s) */ 505 506 cc_pause_t requested_fc; /* flow control user has requested */ 507 cc_pause_t fc; /* actual link flow control */ 508 509 cc_fec_t requested_fec; /* Forward Error Correction: */ 510 cc_fec_t fec; /* requested and actual in use */ 511 512 unsigned char autoneg; /* autonegotiating? */ 513 514 unsigned char link_ok; /* link up? */ 515 unsigned char link_down_rc; /* link down reason */ 516 517 /* 518 * State variables between Common Code and OS-dependent "contract" 519 * routines. These are used to communicate information and desired 520 * actions out-of-band. 521 */ 522 bool new_module; /* ->OS Transceiver Module inserted */ 523 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 524 }; 525 526 /* 527 * Partial EEPROM Vital Product Data structure. Includes only the ID and 528 * VPD-R sections. 529 */ 530 struct t4_vpd_hdr { 531 u8 id_tag; 532 u8 id_len[2]; 533 u8 id_data[ID_LEN]; 534 u8 vpdr_tag; 535 u8 vpdr_len[2]; 536 }; 537 538 #if _KERNEL 539 #include "adapter.h" 540 541 #ifndef PCI_VENDOR_ID_CHELSIO 542 # define PCI_VENDOR_ID_CHELSIO 0x1425 543 #endif 544 545 #define for_each_port(adapter, iter) \ 546 for (iter = 0; iter < (adapter)->params.nports; ++iter) 547 548 int is_offload(const struct adapter *adap); 549 unsigned int core_ticks_per_usec(const struct adapter *adap); 550 unsigned int us_to_core_ticks(const struct adapter *adap, 551 unsigned int us); 552 unsigned int dack_ticks_to_usec(const struct adapter *adap, 553 unsigned int ticks); 554 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 555 556 void t4_record_mbox_marker(struct adapter *adapter, 557 const void *marker, unsigned int size); 558 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 559 int size, void *rpl, bool sleep_ok, int timeout); 560 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 561 void *rpl, bool sleep_ok); 562 563 int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 564 const void *cmd, int size, void *rpl, 565 int timeout); 566 int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 567 int size, void *rpl); 568 int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 569 int size, void *rpl); 570 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 571 unsigned int data_reg, u32 *vals, unsigned int nregs, 572 unsigned int start_idx); 573 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 574 unsigned int data_reg, const u32 *vals, 575 unsigned int nregs, unsigned int start_idx); 576 577 void t4_hw_pci_read_cfg4(adapter_t *adapter, int reg, u32 *val); 578 579 struct fw_filter_wr; 580 581 void t4_intr_enable(struct adapter *adapter); 582 void t4_intr_disable(struct adapter *adapter); 583 int t4_slow_intr_handler(struct adapter *adapter); 584 585 int t4_hash_mac_addr(const u8 *addr); 586 587 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 588 struct link_config *lc); 589 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox, 590 unsigned int port, struct link_config *lc, 591 bool sleep_ok, int timeout); 592 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 593 unsigned int port, struct link_config *lc) 594 { 595 return t4_link_l1cfg_core(adapter, mbox, port, lc, 596 true, FW_CMD_MAX_TIMEOUT); 597 } 598 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 599 unsigned int port, struct link_config *lc) 600 { 601 return t4_link_l1cfg_core(adapter, mbox, port, lc, 602 false, FW_CMD_MAX_TIMEOUT); 603 } 604 605 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 606 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 607 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 608 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 609 int t4_seeprom_wp(struct adapter *adapter, int enable); 610 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 611 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 612 int t4_get_pfres(struct adapter *adapter); 613 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 614 u32 *data, int byte_oriented); 615 int t4_write_flash(struct adapter *adapter, unsigned int addr, 616 unsigned int n, const u8 *data, int byte_oriented); 617 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size, 618 unsigned int bootstrap); 619 int t4_load_phy_fw(struct adapter *adap, 620 int win, t4_os_lock_t *lock, 621 int (*phy_fw_version)(const u8 *, size_t), 622 const u8 *phy_fw_data, size_t phy_fw_size); 623 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 624 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 625 int t5_fw_init_extern_mem(struct adapter *adap); 626 #ifdef CHELSIO_T4_DIAGS 627 int t4_erase_sf(struct adapter *adapter); 628 #endif 629 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 630 int t4_read_bootcfg(struct adapter *adap, u8 *cfg_data, unsigned int size); 631 int t4_load_boot(struct adapter *adap, u8 *boot_data, 632 unsigned int boot_addr, unsigned int size); 633 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 634 int t4_flash_cfg_addr(struct adapter *adapter); 635 int t4_check_fw_version(struct adapter *adap); 636 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 637 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 638 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 639 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 640 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 641 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 642 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 643 int t4_get_version_info(struct adapter *adapter); 644 void t4_dump_version_info(struct adapter *adapter); 645 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 646 const u8 *fw_data, unsigned int fw_size, 647 struct fw_hdr *card_fw, const int t4_fw_install, 648 enum dev_state state, int *reset); 649 int t4_wait_dev_ready(struct adapter *adapter); 650 enum chip_type t4_get_chip_type(struct adapter *adap, int ver); 651 int t4_prep_adapter(struct adapter *adapter, bool reset); 652 int t4_prep_pf(struct adapter *adapter); 653 int t4_prep_master_pf(struct adapter *adapter); 654 int t4_shutdown_adapter(struct adapter *adapter); 655 656 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 657 int t4_bar2_sge_qregs(struct adapter *adapter, 658 unsigned int qid, 659 enum t4_bar2_qtype qtype, 660 int user, 661 u64 *pbar2_qoffset, 662 unsigned int *pbar2_qid); 663 664 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 665 int t4_init_sge_params(struct adapter *adapter); 666 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 667 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 668 int t4_create_filter_info(const struct adapter *adapter, 669 u64 *filter_value, u64 *filter_mask, 670 int fcoe, int port, int vnic_id, 671 int vlan, int vlan_pcp, int vlan_dei, 672 int tos, int protocol, int ethertype, 673 int macmatch, int mpshittype, int fragmentation); 674 int t4_init_rss_mode(struct adapter *adap, int mbox); 675 int t4_init_portinfo_viid(struct port_info *pi, int mbox, 676 int port, int pf, int vf, u8 mac[], bool alloc_vi); 677 int t4_init_portinfo(struct port_info *pi, int mbox, 678 int port, int pf, int vf, u8 mac[]); 679 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 680 int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf, 681 bool enable_mirror); 682 void t4_fatal_err(struct adapter *adapter); 683 void t4_db_full(struct adapter *adapter); 684 void t4_db_dropped(struct adapter *adapter); 685 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 686 int filter_index, int enable); 687 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 688 int filter_index, int *enabled); 689 unsigned int t4_chip_rss_size(struct adapter *adapter); 690 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 691 int start, int n, const u16 *rspq, unsigned int nrspq); 692 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 693 unsigned int flags); 694 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 695 unsigned int flags, unsigned int defq, unsigned int skeyidx, 696 unsigned int skey); 697 int t4_read_rss(struct adapter *adapter, u16 *entries); 698 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 699 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 700 bool sleep_ok); 701 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 702 u32 *valp, bool sleep_ok); 703 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 704 u32 val, bool sleep_ok); 705 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 706 u32 *vfl, u32 *vfh, bool sleep_ok); 707 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 708 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 709 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 710 unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx); 711 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 712 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 713 int t4_read_tcb(struct adapter *adap, int win, int tid, u32 tcb[TCB_SIZE/4]); 714 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 715 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 716 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 717 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 718 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 719 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 720 unsigned int *valp); 721 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 722 const unsigned int *valp); 723 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 724 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 725 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 726 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 727 int t4_get_flash_params(struct adapter *adapter); 728 729 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 730 int t4_get_util_window(struct adapter *adap, int drv_fw_attach); 731 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 732 void t4_idma_monitor_init(struct adapter *adapter, 733 struct sge_idma_monitor_state *idma); 734 void t4_idma_monitor(struct adapter *adapter, 735 struct sge_idma_monitor_state *idma, 736 int hz, int ticks); 737 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 738 unsigned int naddr, u8 *addr); 739 740 #define T4_MEMORY_WRITE 0 741 #define T4_MEMORY_READ 1 742 int t4_memory_rw_addr(struct adapter *adap, int win, 743 u32 addr, u32 len, 744 void *hbuf, int dir); 745 int t4_memory_rw_mtype(struct adapter *adap, int win, 746 int mtype, u32 maddr, u32 len, 747 void *hbuf, int dir); 748 749 int t4_memory_rw(struct adapter *adap, int win, 750 int mtype, u32 maddr, u32 len, 751 void *hbuf, int dir); 752 int hash_mac_addr(const u8 *addr); 753 754 bool t4_is_inserted_mod_type(unsigned int fw_mod_type); 755 extern unsigned int t4_get_regs_len(struct adapter *adapter); 756 extern void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 757 758 const char *t4_get_port_type_description(enum fw_port_type port_type); 759 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 760 void t4_get_port_stats_offset(struct adapter *adap, int idx, 761 struct port_stats *stats, 762 struct port_stats *offset); 763 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 764 void t4_clr_port_stats(struct adapter *adap, int idx); 765 766 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 767 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 768 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 769 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 770 unsigned int *ipg, bool sleep_ok); 771 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 772 unsigned int mask, unsigned int val); 773 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 774 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 775 bool sleep_ok); 776 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 777 bool sleep_ok); 778 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 779 bool sleep_ok); 780 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 781 bool sleep_ok); 782 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 783 struct tp_tcp_stats *v6, bool sleep_ok); 784 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 785 struct tp_fcoe_stats *st, bool sleep_ok); 786 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 787 const unsigned short *alpha, const unsigned short *beta); 788 789 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 790 791 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 792 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 793 bool sleep_ok); 794 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, 795 int rqtype, int qid); 796 797 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 798 enum dev_master master, enum dev_state *state); 799 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 800 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 801 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 802 const u8 *fw_data, unsigned int size, int force); 803 int t4_fl_pkt_align(struct adapter *adap, bool is_packed); 804 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 805 unsigned int cache_line_size, 806 enum chip_type chip_compat); 807 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 808 unsigned int cache_line_size); 809 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 810 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 811 unsigned int vf, unsigned int nparams, const u32 *params, 812 u32 *val); 813 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 814 unsigned int vf, unsigned int nparams, const u32 *params, 815 u32 *val); 816 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 817 unsigned int vf, unsigned int nparams, const u32 *params, 818 u32 *val, int rw, bool sleep_ok); 819 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 820 unsigned int pf, unsigned int vf, 821 unsigned int nparams, const u32 *params, 822 const u32 *val, int timeout); 823 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 824 unsigned int vf, unsigned int nparams, const u32 *params, 825 const u32 *val); 826 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 827 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 828 unsigned int rxqi, unsigned int rxq, unsigned int tc, 829 unsigned int vi, unsigned int cmask, unsigned int pmask, 830 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 831 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 832 unsigned int port, unsigned int pf, unsigned int vf, 833 unsigned int nmac, u8 *mac, unsigned int *rss_size, 834 u8 *vivld, u8 *vin, 835 unsigned int portfunc, unsigned int idstype); 836 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 837 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 838 unsigned int *rss_size, u8 *vivld, u8 *vin); 839 int t4_free_vi(struct adapter *adap, unsigned int mbox, 840 unsigned int pf, unsigned int vf, 841 unsigned int viid); 842 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 843 int mtu, int promisc, int all_multi, int bcast, int vlanex, 844 bool sleep_ok); 845 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 846 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 847 u64 *hash, bool sleep_ok); 848 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 849 unsigned int viid, unsigned int naddr, 850 const u8 **addr, bool sleep_ok); 851 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 852 int idx, bool sleep_ok); 853 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 854 const u8 *addr, const u8 *mask, unsigned int idx, 855 u8 lookup_type, u8 port_id, bool sleep_ok); 856 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 857 const u8 *addr, const u8 *mask, unsigned int idx, 858 u8 lookup_type, u8 port_id, bool sleep_ok); 859 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 860 const u8 *addr, const u8 *mask, unsigned int vni, 861 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 862 bool sleep_ok); 863 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 864 int idx, const u8 *addr, bool persist, u8 *smt_idx); 865 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 866 const u8 *addr, bool smac); 867 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 868 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac); 869 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 870 bool ucast, u64 vec, bool sleep_ok); 871 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 872 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 873 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 874 struct port_info *pi, 875 bool rx_en, bool tx_en, bool dcb_en); 876 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 877 bool rx_en, bool tx_en); 878 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 879 unsigned int nblinks); 880 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 881 unsigned int mmd, unsigned int reg, unsigned int *valp); 882 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 883 unsigned int mmd, unsigned int reg, unsigned int val); 884 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 885 int port, unsigned int devid, 886 unsigned int offset, unsigned int len, 887 u8 *buf, bool write); 888 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 889 int port, unsigned int devid, 890 unsigned int offset, unsigned int len, 891 u8 *buf); 892 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 893 int port, unsigned int devid, 894 unsigned int offset, unsigned int len, 895 u8 *buf); 896 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 897 unsigned int vf, unsigned int iqtype, unsigned int iqid, 898 unsigned int fl0id, unsigned int fl1id); 899 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 900 unsigned int vf, unsigned int iqtype, unsigned int iqid, 901 unsigned int fl0id, unsigned int fl1id); 902 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 903 unsigned int vf, unsigned int eqid); 904 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 905 unsigned int vf, unsigned int eqid); 906 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 907 unsigned int vf, unsigned int eqid); 908 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 909 enum ctxt_type ctype, u32 *data); 910 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 911 u32 *data); 912 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 913 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 914 u16 *dbqtimers); 915 const char *t4_link_down_rc_str(unsigned char link_down_rc); 916 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 917 int t4_update_port_info(struct port_info *pi); 918 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 919 unsigned int *speedp, unsigned int *mtup); 920 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 921 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 922 923 int t4_sched_config(struct adapter *adapter, int type, int minmaxen); 924 int t4_sched_params(struct adapter *adapter, 925 int channel, int cls, 926 int level, int mode, int type, 927 int rateunit, int ratemode, 928 int minrate, int maxrate, int weight, 929 int pktsize, int burstsize); 930 int t4_read_sched_params(struct adapter *adapter, 931 int channel, int cls, 932 int *level, int *mode, int *type, 933 int *rateunit, int *ratemode, 934 int *minrate, int *maxrate, int *weight, 935 int *pktsize, int *burstsize); 936 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 937 unsigned int pf, unsigned int vf, 938 unsigned int timeout, unsigned int action); 939 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 940 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 941 942 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 943 944 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 945 u32 start_index, bool sleep_ok); 946 void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs, 947 u32 start_index, bool sleep_ok); 948 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 949 u32 start_index, bool sleep_ok); 950 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 951 u32 start_index, bool sleep_ok); 952 int t4_configure_ringbb(struct adapter *adap); 953 int t4_configure_add_smac(struct adapter *adap); 954 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 955 u16 vlan); 956 #endif 957 #ifdef __cplusplus 958 } 959 #endif 960 #endif /* __CHELSIO_COMMON_H */ 961