1*d39a76e7Sxw /*
2*d39a76e7Sxw * CDDL HEADER START
3*d39a76e7Sxw *
4*d39a76e7Sxw * The contents of this file are subject to the terms of the
5*d39a76e7Sxw * Common Development and Distribution License (the "License").
6*d39a76e7Sxw * You may not use this file except in compliance with the License.
7*d39a76e7Sxw *
8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing.
10*d39a76e7Sxw * See the License for the specific language governing permissions
11*d39a76e7Sxw * and limitations under the License.
12*d39a76e7Sxw *
13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each
14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the
16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying
17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner]
18*d39a76e7Sxw *
19*d39a76e7Sxw * CDDL HEADER END
20*d39a76e7Sxw */
21*d39a76e7Sxw
22*d39a76e7Sxw /*
23*d39a76e7Sxw * This file is part of the Chelsio T1 Ethernet driver.
24*d39a76e7Sxw *
25*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
26*d39a76e7Sxw */
27*d39a76e7Sxw
28*d39a76e7Sxw #include "common.h"
29*d39a76e7Sxw #include "regs.h"
30*d39a76e7Sxw #include "mc4.h"
31*d39a76e7Sxw
32*d39a76e7Sxw struct pemc4 {
33*d39a76e7Sxw adapter_t *adapter;
34*d39a76e7Sxw unsigned int size;
35*d39a76e7Sxw unsigned int nwords; /* MC4 width in terms of 32-bit words */
36*d39a76e7Sxw struct pemc4_intr_counts intr_cnt;
37*d39a76e7Sxw };
38*d39a76e7Sxw
t1_mc4_destroy(struct pemc4 * mc4)39*d39a76e7Sxw void t1_mc4_destroy(struct pemc4 *mc4)
40*d39a76e7Sxw {
41*d39a76e7Sxw t1_os_free((void *)mc4, sizeof(*mc4));
42*d39a76e7Sxw }
43*d39a76e7Sxw
44*d39a76e7Sxw #define is_MC4A(adapter) (!t1_is_T1B(adapter))
45*d39a76e7Sxw
46*d39a76e7Sxw /* Calculate amount of MC4 memory. */
mc4_calc_size(adapter_t * adapter)47*d39a76e7Sxw static unsigned int __devinit mc4_calc_size(adapter_t *adapter)
48*d39a76e7Sxw {
49*d39a76e7Sxw u32 mc4_cfg = t1_read_reg_4(adapter, A_MC4_CFG);
50*d39a76e7Sxw unsigned int width = is_MC4A(adapter) ? G_MC4A_WIDTH(mc4_cfg) :
51*d39a76e7Sxw !!(mc4_cfg & F_MC4_NARROW);
52*d39a76e7Sxw
53*d39a76e7Sxw return (256 * 1024 * 1024) >> width;
54*d39a76e7Sxw }
55*d39a76e7Sxw
56*d39a76e7Sxw /*
57*d39a76e7Sxw * Write a value to a register and check that the write completed. These
58*d39a76e7Sxw * writes normally complete in a cycle or two, so one read should suffice but
59*d39a76e7Sxw * just in case we give them a bit of grace period. Note that the very first
60*d39a76e7Sxw * read exists to flush the posted write to the device.
61*d39a76e7Sxw */
wrreg_wait(adapter_t * adapter,unsigned int addr,u32 val)62*d39a76e7Sxw static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
63*d39a76e7Sxw {
64*d39a76e7Sxw int attempts = 2;
65*d39a76e7Sxw
66*d39a76e7Sxw t1_write_reg_4(adapter, addr, val);
67*d39a76e7Sxw val = t1_read_reg_4(adapter, addr); /* flush */
68*d39a76e7Sxw while (attempts--) {
69*d39a76e7Sxw if (!(t1_read_reg_4(adapter, addr) & F_BUSY))
70*d39a76e7Sxw return 0;
71*d39a76e7Sxw if (attempts)
72*d39a76e7Sxw DELAY_US(1);
73*d39a76e7Sxw }
74*d39a76e7Sxw CH_ERR("%s: write to MC4 register 0x%x timed out\n",
75*d39a76e7Sxw adapter_name(adapter), addr);
76*d39a76e7Sxw return -EIO;
77*d39a76e7Sxw }
78*d39a76e7Sxw
79*d39a76e7Sxw #define MC4_DLL_DONE (F_MASTER_DLL_LOCKED | F_MASTER_DLL_MAX_TAP_COUNT)
80*d39a76e7Sxw
t1_mc4_init(struct pemc4 * mc4,unsigned int mc4_clock)81*d39a76e7Sxw int t1_mc4_init(struct pemc4 *mc4, unsigned int mc4_clock)
82*d39a76e7Sxw {
83*d39a76e7Sxw int attempts;
84*d39a76e7Sxw u32 val;
85*d39a76e7Sxw unsigned int width, ext_mode, slow_mode;
86*d39a76e7Sxw adapter_t *adapter = mc4->adapter;
87*d39a76e7Sxw
88*d39a76e7Sxw /* Power up the FCRAMs. */
89*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_CFG);
90*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_CFG, val | F_POWER_UP);
91*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */
92*d39a76e7Sxw
93*d39a76e7Sxw if (is_MC4A(adapter)) {
94*d39a76e7Sxw slow_mode = val & F_MC4A_SLOW;
95*d39a76e7Sxw width = G_MC4A_WIDTH(val);
96*d39a76e7Sxw
97*d39a76e7Sxw /* If we're not in slow mode, we are using the DLLs */
98*d39a76e7Sxw if (!slow_mode) {
99*d39a76e7Sxw /* Clear Reset */
100*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_STROBE);
101*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_STROBE,
102*d39a76e7Sxw val & ~F_SLAVE_DLL_RESET);
103*d39a76e7Sxw
104*d39a76e7Sxw /* Wait for slave DLLs to lock */
105*d39a76e7Sxw DELAY_US(2 * 512 / (mc4_clock / 1000000) + 1);
106*d39a76e7Sxw }
107*d39a76e7Sxw } else {
108*d39a76e7Sxw slow_mode = val & F_MC4_SLOW;
109*d39a76e7Sxw width = !!(val & F_MC4_NARROW);
110*d39a76e7Sxw
111*d39a76e7Sxw /* Initializes the master DLL and slave delay lines. */
112*d39a76e7Sxw if (t1_is_asic(adapter) && !slow_mode) {
113*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_STROBE);
114*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_STROBE,
115*d39a76e7Sxw val & ~F_MASTER_DLL_RESET);
116*d39a76e7Sxw
117*d39a76e7Sxw /* Wait for the master DLL to lock. */
118*d39a76e7Sxw attempts = 100;
119*d39a76e7Sxw do {
120*d39a76e7Sxw DELAY_US(1);
121*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_STROBE);
122*d39a76e7Sxw } while (!(val & MC4_DLL_DONE) && --attempts);
123*d39a76e7Sxw if (!(val & MC4_DLL_DONE)) {
124*d39a76e7Sxw CH_ERR("%s: MC4 DLL lock failed\n",
125*d39a76e7Sxw adapter_name(adapter));
126*d39a76e7Sxw goto out_fail;
127*d39a76e7Sxw }
128*d39a76e7Sxw }
129*d39a76e7Sxw }
130*d39a76e7Sxw
131*d39a76e7Sxw mc4->nwords = 4 >> width;
132*d39a76e7Sxw
133*d39a76e7Sxw /* Set the FCRAM output drive strength and enable DLLs if needed */
134*d39a76e7Sxw ext_mode = t1_is_asic(adapter) && !slow_mode ? 0 : 1;
135*d39a76e7Sxw if (wrreg_wait(adapter, A_MC4_EXT_MODE, ext_mode))
136*d39a76e7Sxw goto out_fail;
137*d39a76e7Sxw
138*d39a76e7Sxw /* Specify the FCRAM operating parameters */
139*d39a76e7Sxw if (wrreg_wait(adapter, A_MC4_MODE, 0x32))
140*d39a76e7Sxw goto out_fail;
141*d39a76e7Sxw
142*d39a76e7Sxw /* Initiate an immediate refresh and wait for the write to complete. */
143*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_REFRESH);
144*d39a76e7Sxw if (wrreg_wait(adapter, A_MC4_REFRESH, val & ~F_REFRESH_ENABLE))
145*d39a76e7Sxw goto out_fail;
146*d39a76e7Sxw
147*d39a76e7Sxw /* 2nd immediate refresh as before */
148*d39a76e7Sxw if (wrreg_wait(adapter, A_MC4_REFRESH, val & ~F_REFRESH_ENABLE))
149*d39a76e7Sxw goto out_fail;
150*d39a76e7Sxw
151*d39a76e7Sxw /* Convert to KHz first to avoid 64-bit division. */
152*d39a76e7Sxw mc4_clock /= 1000; /* Hz->KHz */
153*d39a76e7Sxw mc4_clock = mc4_clock * 7812 + mc4_clock / 2; /* ns */
154*d39a76e7Sxw mc4_clock /= 1000000; /* KHz->MHz, ns->us */
155*d39a76e7Sxw
156*d39a76e7Sxw /* Enable periodic refresh. */
157*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_REFRESH,
158*d39a76e7Sxw F_REFRESH_ENABLE | V_REFRESH_DIVISOR(mc4_clock));
159*d39a76e7Sxw (void) t1_read_reg_4(adapter, A_MC4_REFRESH); /* flush */
160*d39a76e7Sxw
161*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_ECC_CNTL,
162*d39a76e7Sxw F_ECC_GENERATION_ENABLE | F_ECC_CHECK_ENABLE);
163*d39a76e7Sxw
164*d39a76e7Sxw /* Use the BIST engine to clear all of the MC4 memory. */
165*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0);
166*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_BIST_ADDR_END, (mc4->size << width) - 1);
167*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0);
168*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_BIST_OP, V_OP(1) | 0x1f0);
169*d39a76e7Sxw (void) t1_read_reg_4(adapter, A_MC4_BIST_OP); /* flush */
170*d39a76e7Sxw
171*d39a76e7Sxw attempts = 100;
172*d39a76e7Sxw do {
173*d39a76e7Sxw DELAY_MS(100);
174*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_BIST_OP);
175*d39a76e7Sxw } while ((val & F_BUSY) && --attempts);
176*d39a76e7Sxw if (val & F_BUSY) {
177*d39a76e7Sxw CH_ERR("%s: MC4 BIST timed out\n", adapter_name(adapter));
178*d39a76e7Sxw goto out_fail;
179*d39a76e7Sxw }
180*d39a76e7Sxw
181*d39a76e7Sxw /* Enable normal memory accesses. */
182*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_CFG);
183*d39a76e7Sxw t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY);
184*d39a76e7Sxw val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */
185*d39a76e7Sxw return 0;
186*d39a76e7Sxw
187*d39a76e7Sxw out_fail:
188*d39a76e7Sxw return -1;
189*d39a76e7Sxw }
190*d39a76e7Sxw
t1_mc4_create(adapter_t * adapter)191*d39a76e7Sxw struct pemc4 * __devinit t1_mc4_create(adapter_t *adapter)
192*d39a76e7Sxw {
193*d39a76e7Sxw struct pemc4 *mc4 = t1_os_malloc_wait_zero(sizeof(*mc4));
194*d39a76e7Sxw
195*d39a76e7Sxw if (mc4) {
196*d39a76e7Sxw mc4->adapter = adapter;
197*d39a76e7Sxw mc4->size = mc4_calc_size(adapter);
198*d39a76e7Sxw }
199*d39a76e7Sxw return mc4;
200*d39a76e7Sxw }
201*d39a76e7Sxw
t1_mc4_get_size(struct pemc4 * mc4)202*d39a76e7Sxw unsigned int t1_mc4_get_size(struct pemc4 *mc4)
203*d39a76e7Sxw {
204*d39a76e7Sxw return mc4->size;
205*d39a76e7Sxw }
206*d39a76e7Sxw
207*d39a76e7Sxw #define MC4_INT_MASK (F_MC4_CORR_ERR | F_MC4_UNCORR_ERR | F_MC4_ADDR_ERR)
208*d39a76e7Sxw #define MC4_INT_FATAL (F_MC4_UNCORR_ERR | F_MC4_ADDR_ERR)
209*d39a76e7Sxw
t1_mc4_intr_enable(struct pemc4 * mc4)210*d39a76e7Sxw void t1_mc4_intr_enable(struct pemc4 *mc4)
211*d39a76e7Sxw {
212*d39a76e7Sxw u32 pl_intr;
213*d39a76e7Sxw
214*d39a76e7Sxw if (t1_is_asic(mc4->adapter)) {
215*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_MC4_INT_ENABLE, MC4_INT_MASK);
216*d39a76e7Sxw
217*d39a76e7Sxw pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE);
218*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_PL_ENABLE,
219*d39a76e7Sxw pl_intr | F_PL_INTR_MC4);
220*d39a76e7Sxw }
221*d39a76e7Sxw }
222*d39a76e7Sxw
t1_mc4_intr_disable(struct pemc4 * mc4)223*d39a76e7Sxw void t1_mc4_intr_disable(struct pemc4 *mc4)
224*d39a76e7Sxw {
225*d39a76e7Sxw u32 pl_intr;
226*d39a76e7Sxw
227*d39a76e7Sxw if (t1_is_asic(mc4->adapter)) {
228*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_MC4_INT_ENABLE, 0);
229*d39a76e7Sxw
230*d39a76e7Sxw pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE);
231*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_PL_ENABLE,
232*d39a76e7Sxw pl_intr & ~F_PL_INTR_MC4);
233*d39a76e7Sxw }
234*d39a76e7Sxw }
235*d39a76e7Sxw
t1_mc4_intr_clear(struct pemc4 * mc4)236*d39a76e7Sxw void t1_mc4_intr_clear(struct pemc4 *mc4)
237*d39a76e7Sxw {
238*d39a76e7Sxw if (t1_is_asic(mc4->adapter)) {
239*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, 0xffffffff);
240*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_PL_CAUSE, F_PL_INTR_MC4);
241*d39a76e7Sxw }
242*d39a76e7Sxw }
243*d39a76e7Sxw
t1_mc4_intr_handler(struct pemc4 * mc4)244*d39a76e7Sxw int t1_mc4_intr_handler(struct pemc4 *mc4)
245*d39a76e7Sxw {
246*d39a76e7Sxw adapter_t *adapter = mc4->adapter;
247*d39a76e7Sxw u32 cause = t1_read_reg_4(adapter, A_MC4_INT_CAUSE);
248*d39a76e7Sxw
249*d39a76e7Sxw if (cause & F_MC4_CORR_ERR) {
250*d39a76e7Sxw mc4->intr_cnt.corr_err++;
251*d39a76e7Sxw CH_WARN("%s: MC4 correctable error at addr 0x%x, "
252*d39a76e7Sxw "data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
253*d39a76e7Sxw adapter_name(adapter),
254*d39a76e7Sxw G_MC4_CE_ADDR(t1_read_reg_4(adapter, A_MC4_CE_ADDR)),
255*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_CE_DATA0),
256*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_CE_DATA1),
257*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_CE_DATA2),
258*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_CE_DATA3),
259*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_CE_DATA4));
260*d39a76e7Sxw }
261*d39a76e7Sxw
262*d39a76e7Sxw if (cause & F_MC4_UNCORR_ERR) {
263*d39a76e7Sxw mc4->intr_cnt.uncorr_err++;
264*d39a76e7Sxw CH_ALERT("%s: MC4 uncorrectable error at addr 0x%x, "
265*d39a76e7Sxw "data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
266*d39a76e7Sxw adapter_name(adapter),
267*d39a76e7Sxw G_MC4_UE_ADDR(t1_read_reg_4(adapter, A_MC4_UE_ADDR)),
268*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_UE_DATA0),
269*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_UE_DATA1),
270*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_UE_DATA2),
271*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_UE_DATA3),
272*d39a76e7Sxw t1_read_reg_4(adapter, A_MC4_UE_DATA4));
273*d39a76e7Sxw }
274*d39a76e7Sxw
275*d39a76e7Sxw if (cause & F_MC4_ADDR_ERR) {
276*d39a76e7Sxw mc4->intr_cnt.addr_err++;
277*d39a76e7Sxw CH_ALERT("%s: MC4 address error\n", adapter_name(adapter));
278*d39a76e7Sxw }
279*d39a76e7Sxw
280*d39a76e7Sxw if (cause & MC4_INT_FATAL)
281*d39a76e7Sxw t1_fatal_err(adapter);
282*d39a76e7Sxw
283*d39a76e7Sxw t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, cause);
284*d39a76e7Sxw return 0;
285*d39a76e7Sxw }
286*d39a76e7Sxw
t1_mc4_get_intr_counts(struct pemc4 * mc4)287*d39a76e7Sxw const struct pemc4_intr_counts *t1_mc4_get_intr_counts(struct pemc4 *mc4)
288*d39a76e7Sxw {
289*d39a76e7Sxw return &mc4->intr_cnt;
290*d39a76e7Sxw }
291*d39a76e7Sxw
292*d39a76e7Sxw /*
293*d39a76e7Sxw * Read n 256-bit words from MC4 starting at word start, using backdoor
294*d39a76e7Sxw * accesses.
295*d39a76e7Sxw */
t1_mc4_bd_read(struct pemc4 * mc4,unsigned int start,unsigned int n,u32 * buf)296*d39a76e7Sxw int t1_mc4_bd_read(struct pemc4 *mc4, unsigned int start, unsigned int n,
297*d39a76e7Sxw u32 *buf)
298*d39a76e7Sxw {
299*d39a76e7Sxw adapter_t *adap = mc4->adapter;
300*d39a76e7Sxw unsigned int size256 = mc4->size / 32, c = 8 / mc4->nwords, i;
301*d39a76e7Sxw
302*d39a76e7Sxw if (start >= size256 || start + n > size256)
303*d39a76e7Sxw return -EINVAL;
304*d39a76e7Sxw
305*d39a76e7Sxw for (i = 8, start *= 16 * c, n *= c; n; --n, start += 16) {
306*d39a76e7Sxw int attempts = 10;
307*d39a76e7Sxw u32 val;
308*d39a76e7Sxw
309*d39a76e7Sxw t1_write_reg_4(adap, A_MC4_BD_ADDR, start);
310*d39a76e7Sxw t1_write_reg_4(adap, A_MC4_BD_OP, 0);
311*d39a76e7Sxw val = t1_read_reg_4(adap, A_MC4_BD_OP);
312*d39a76e7Sxw while ((val & F_BUSY) && attempts--)
313*d39a76e7Sxw val = t1_read_reg_4(adap, A_MC4_BD_OP);
314*d39a76e7Sxw
315*d39a76e7Sxw if (val & F_BUSY)
316*d39a76e7Sxw return -EIO;
317*d39a76e7Sxw
318*d39a76e7Sxw buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA3);
319*d39a76e7Sxw if (mc4->nwords >= 2)
320*d39a76e7Sxw buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA2);
321*d39a76e7Sxw if (mc4->nwords == 4) {
322*d39a76e7Sxw buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA1);
323*d39a76e7Sxw buf[--i] = t1_read_reg_4(adap, A_MC4_BD_DATA0);
324*d39a76e7Sxw }
325*d39a76e7Sxw if (i == 0) {
326*d39a76e7Sxw i = 8;
327*d39a76e7Sxw buf += 8;
328*d39a76e7Sxw }
329*d39a76e7Sxw }
330*d39a76e7Sxw return 0;
331*d39a76e7Sxw }
332