1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24*d39a76e7Sxw */ 25*d39a76e7Sxw 26*d39a76e7Sxw /* 27*d39a76e7Sxw * FPGA specific definitions 28*d39a76e7Sxw */ 29*d39a76e7Sxw 30*d39a76e7Sxw #ifndef __CHELSIO_FPGA_DEFS_H__ 31*d39a76e7Sxw #define __CHELSIO_FPGA_DEFS_H__ 32*d39a76e7Sxw 33*d39a76e7Sxw #define FPGA_PCIX_ADDR_VERSION 0xA08 34*d39a76e7Sxw #define FPGA_PCIX_ADDR_STAT 0xA0C 35*d39a76e7Sxw 36*d39a76e7Sxw /* FPGA master interrupt Cause/Enable bits */ 37*d39a76e7Sxw #define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1 38*d39a76e7Sxw #define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2 39*d39a76e7Sxw #define FPGA_PCIX_INTERRUPT_TP 0x4 40*d39a76e7Sxw #define FPGA_PCIX_INTERRUPT_MC3 0x8 41*d39a76e7Sxw #define FPGA_PCIX_INTERRUPT_GMAC 0x10 42*d39a76e7Sxw #define FPGA_PCIX_INTERRUPT_PCIX 0x20 43*d39a76e7Sxw 44*d39a76e7Sxw /* TP interrupt register addresses */ 45*d39a76e7Sxw #define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 46*d39a76e7Sxw #define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14 47*d39a76e7Sxw #define FPGA_TP_ADDR_VERSION 0xA18 48*d39a76e7Sxw 49*d39a76e7Sxw /* TP interrupt Cause/Enable bits */ 50*d39a76e7Sxw #define FPGA_TP_INTERRUPT_MC4 0x1 51*d39a76e7Sxw #define FPGA_TP_INTERRUPT_MC5 0x2 52*d39a76e7Sxw 53*d39a76e7Sxw /* 54*d39a76e7Sxw * PM interrupt register addresses 55*d39a76e7Sxw */ 56*d39a76e7Sxw #define FPGA_MC3_REG_INTRENABLE 0xA20 57*d39a76e7Sxw #define FPGA_MC3_REG_INTRCAUSE 0xA24 58*d39a76e7Sxw #define FPGA_MC3_REG_VERSION 0xA28 59*d39a76e7Sxw 60*d39a76e7Sxw /* 61*d39a76e7Sxw * GMAC interrupt register addresses 62*d39a76e7Sxw */ 63*d39a76e7Sxw #define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30 64*d39a76e7Sxw #define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34 65*d39a76e7Sxw #define FPGA_GMAC_ADDR_VERSION 0xA38 66*d39a76e7Sxw 67*d39a76e7Sxw /* GMAC Cause/Enable bits */ 68*d39a76e7Sxw #define FPGA_GMAC_INTERRUPT_PORT0 0x1 69*d39a76e7Sxw #define FPGA_GMAC_INTERRUPT_PORT1 0x2 70*d39a76e7Sxw #define FPGA_GMAC_INTERRUPT_PORT2 0x4 71*d39a76e7Sxw #define FPGA_GMAC_INTERRUPT_PORT3 0x8 72*d39a76e7Sxw 73*d39a76e7Sxw /* MI0 registers */ 74*d39a76e7Sxw #define A_MI0_CLK 0xb00 75*d39a76e7Sxw 76*d39a76e7Sxw #define S_MI0_CLK_DIV 0 77*d39a76e7Sxw #define M_MI0_CLK_DIV 0xff 78*d39a76e7Sxw #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) 79*d39a76e7Sxw #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) 80*d39a76e7Sxw 81*d39a76e7Sxw #define S_MI0_CLK_CNT 8 82*d39a76e7Sxw #define M_MI0_CLK_CNT 0xff 83*d39a76e7Sxw #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) 84*d39a76e7Sxw #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) 85*d39a76e7Sxw 86*d39a76e7Sxw #define A_MI0_CSR 0xb04 87*d39a76e7Sxw 88*d39a76e7Sxw #define S_MI0_CSR_POLL 0 89*d39a76e7Sxw #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) 90*d39a76e7Sxw #define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U) 91*d39a76e7Sxw 92*d39a76e7Sxw #define S_MI0_PREAMBLE 1 93*d39a76e7Sxw #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) 94*d39a76e7Sxw #define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U) 95*d39a76e7Sxw 96*d39a76e7Sxw #define S_MI0_INTR_ENABLE 2 97*d39a76e7Sxw #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) 98*d39a76e7Sxw #define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U) 99*d39a76e7Sxw 100*d39a76e7Sxw #define S_MI0_BUSY 3 101*d39a76e7Sxw #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) 102*d39a76e7Sxw #define F_MI0_BUSY V_MI0_BUSY(1U) 103*d39a76e7Sxw 104*d39a76e7Sxw #define S_MI0_MDIO 4 105*d39a76e7Sxw #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) 106*d39a76e7Sxw #define F_MI0_MDIO V_MI0_MDIO(1U) 107*d39a76e7Sxw 108*d39a76e7Sxw #define A_MI0_ADDR 0xb08 109*d39a76e7Sxw 110*d39a76e7Sxw #define S_MI0_PHY_REG_ADDR 0 111*d39a76e7Sxw #define M_MI0_PHY_REG_ADDR 0x1f 112*d39a76e7Sxw #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) 113*d39a76e7Sxw #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) 114*d39a76e7Sxw 115*d39a76e7Sxw #define S_MI0_PHY_ADDR 5 116*d39a76e7Sxw #define M_MI0_PHY_ADDR 0x1f 117*d39a76e7Sxw #define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR) 118*d39a76e7Sxw #define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) 119*d39a76e7Sxw 120*d39a76e7Sxw #define A_MI0_DATA_EXT 0xb0c 121*d39a76e7Sxw #define A_MI0_DATA_INT 0xb10 122*d39a76e7Sxw 123*d39a76e7Sxw /* GMAC registers */ 124*d39a76e7Sxw #define A_GMAC_MACID_LO 0x28 125*d39a76e7Sxw #define A_GMAC_MACID_HI 0x2c 126*d39a76e7Sxw #define A_GMAC_CSR 0x30 127*d39a76e7Sxw 128*d39a76e7Sxw #define S_INTERFACE 0 129*d39a76e7Sxw #define M_INTERFACE 0x3 130*d39a76e7Sxw #define V_INTERFACE(x) ((x) << S_INTERFACE) 131*d39a76e7Sxw #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) 132*d39a76e7Sxw 133*d39a76e7Sxw #define S_MAC_TX_ENABLE 2 134*d39a76e7Sxw #define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE) 135*d39a76e7Sxw #define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U) 136*d39a76e7Sxw 137*d39a76e7Sxw #define S_MAC_RX_ENABLE 3 138*d39a76e7Sxw #define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE) 139*d39a76e7Sxw #define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U) 140*d39a76e7Sxw 141*d39a76e7Sxw #define S_MAC_LB_ENABLE 4 142*d39a76e7Sxw #define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE) 143*d39a76e7Sxw #define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U) 144*d39a76e7Sxw 145*d39a76e7Sxw #define S_MAC_SPEED 5 146*d39a76e7Sxw #define M_MAC_SPEED 0x3 147*d39a76e7Sxw #define V_MAC_SPEED(x) ((x) << S_MAC_SPEED) 148*d39a76e7Sxw #define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED) 149*d39a76e7Sxw 150*d39a76e7Sxw #define S_MAC_HD_FC_ENABLE 7 151*d39a76e7Sxw #define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE) 152*d39a76e7Sxw #define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U) 153*d39a76e7Sxw 154*d39a76e7Sxw #define S_MAC_HALF_DUPLEX 8 155*d39a76e7Sxw #define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX) 156*d39a76e7Sxw #define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U) 157*d39a76e7Sxw 158*d39a76e7Sxw #define S_MAC_PROMISC 9 159*d39a76e7Sxw #define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC) 160*d39a76e7Sxw #define F_MAC_PROMISC V_MAC_PROMISC(1U) 161*d39a76e7Sxw 162*d39a76e7Sxw #define S_MAC_MC_ENABLE 10 163*d39a76e7Sxw #define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE) 164*d39a76e7Sxw #define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U) 165*d39a76e7Sxw 166*d39a76e7Sxw #define S_MAC_RESET 11 167*d39a76e7Sxw #define V_MAC_RESET(x) ((x) << S_MAC_RESET) 168*d39a76e7Sxw #define F_MAC_RESET V_MAC_RESET(1U) 169*d39a76e7Sxw 170*d39a76e7Sxw #define S_MAC_RX_PAUSE_ENABLE 12 171*d39a76e7Sxw #define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE) 172*d39a76e7Sxw #define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U) 173*d39a76e7Sxw 174*d39a76e7Sxw #define S_MAC_TX_PAUSE_ENABLE 13 175*d39a76e7Sxw #define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE) 176*d39a76e7Sxw #define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U) 177*d39a76e7Sxw 178*d39a76e7Sxw #define S_MAC_LWM_ENABLE 14 179*d39a76e7Sxw #define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE) 180*d39a76e7Sxw #define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U) 181*d39a76e7Sxw 182*d39a76e7Sxw #define S_MAC_MAGIC_PKT_ENABLE 15 183*d39a76e7Sxw #define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE) 184*d39a76e7Sxw #define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U) 185*d39a76e7Sxw 186*d39a76e7Sxw #define S_MAC_ISL_ENABLE 16 187*d39a76e7Sxw #define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE) 188*d39a76e7Sxw #define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U) 189*d39a76e7Sxw 190*d39a76e7Sxw #define S_MAC_JUMBO_ENABLE 17 191*d39a76e7Sxw #define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE) 192*d39a76e7Sxw #define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U) 193*d39a76e7Sxw 194*d39a76e7Sxw #define S_MAC_RX_PAD_ENABLE 18 195*d39a76e7Sxw #define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE) 196*d39a76e7Sxw #define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U) 197*d39a76e7Sxw 198*d39a76e7Sxw #define S_MAC_RX_CRC_ENABLE 19 199*d39a76e7Sxw #define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE) 200*d39a76e7Sxw #define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U) 201*d39a76e7Sxw 202*d39a76e7Sxw #define A_GMAC_IFS 0x34 203*d39a76e7Sxw 204*d39a76e7Sxw #define S_MAC_IFS2 0 205*d39a76e7Sxw #define M_MAC_IFS2 0x3f 206*d39a76e7Sxw #define V_MAC_IFS2(x) ((x) << S_MAC_IFS2) 207*d39a76e7Sxw #define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2) 208*d39a76e7Sxw 209*d39a76e7Sxw #define S_MAC_IFS1 8 210*d39a76e7Sxw #define M_MAC_IFS1 0x7f 211*d39a76e7Sxw #define V_MAC_IFS1(x) ((x) << S_MAC_IFS1) 212*d39a76e7Sxw #define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1) 213*d39a76e7Sxw 214*d39a76e7Sxw #define A_GMAC_JUMBO_FRAME_LEN 0x38 215*d39a76e7Sxw #define A_GMAC_LNK_DLY 0x3c 216*d39a76e7Sxw #define A_GMAC_PAUSETIME 0x40 217*d39a76e7Sxw #define A_GMAC_MCAST_LO 0x44 218*d39a76e7Sxw #define A_GMAC_MCAST_HI 0x48 219*d39a76e7Sxw #define A_GMAC_MCAST_MASK_LO 0x4c 220*d39a76e7Sxw #define A_GMAC_MCAST_MASK_HI 0x50 221*d39a76e7Sxw #define A_GMAC_RMT_CNT 0x54 222*d39a76e7Sxw #define A_GMAC_RMT_DATA 0x58 223*d39a76e7Sxw #define A_GMAC_BACKOFF_SEED 0x5c 224*d39a76e7Sxw #define A_GMAC_TXF_THRES 0x60 225*d39a76e7Sxw 226*d39a76e7Sxw #define S_TXF_READ_THRESHOLD 0 227*d39a76e7Sxw #define M_TXF_READ_THRESHOLD 0xff 228*d39a76e7Sxw #define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD) 229*d39a76e7Sxw #define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) 230*d39a76e7Sxw 231*d39a76e7Sxw #define S_TXF_WRITE_THRESHOLD 16 232*d39a76e7Sxw #define M_TXF_WRITE_THRESHOLD 0xff 233*d39a76e7Sxw #define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD) 234*d39a76e7Sxw #define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) 235*d39a76e7Sxw 236*d39a76e7Sxw #define MAC_REG_BASE 0x600 237*d39a76e7Sxw #define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) 238*d39a76e7Sxw 239*d39a76e7Sxw #define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO) 240*d39a76e7Sxw #define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI) 241*d39a76e7Sxw #define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR) 242*d39a76e7Sxw #define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS) 243*d39a76e7Sxw #define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) 244*d39a76e7Sxw #define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) 245*d39a76e7Sxw #define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) 246*d39a76e7Sxw #define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) 247*d39a76e7Sxw #define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) 248*d39a76e7Sxw #define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO) 249*d39a76e7Sxw #define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI) 250*d39a76e7Sxw #define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT) 251*d39a76e7Sxw #define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA) 252*d39a76e7Sxw #define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED) 253*d39a76e7Sxw #define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES) 254*d39a76e7Sxw 255*d39a76e7Sxw #endif 256