1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*d39a76e7Sxw * Use is subject to license terms. 25*d39a76e7Sxw */ 26*d39a76e7Sxw 27*d39a76e7Sxw /* 28*d39a76e7Sxw * This file is part of the Chelsio T1 Ethernet driver. 29*d39a76e7Sxw * 30*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31*d39a76e7Sxw */ 32*d39a76e7Sxw 33*d39a76e7Sxw #ifndef _CHELSIO_CH_H 34*d39a76e7Sxw #define _CHELSIO_CH_H 35*d39a76e7Sxw 36*d39a76e7Sxw #include <sys/debug.h> 37*d39a76e7Sxw 38*d39a76e7Sxw #ifdef __cplusplus 39*d39a76e7Sxw extern "C" { 40*d39a76e7Sxw #endif 41*d39a76e7Sxw 42*d39a76e7Sxw /* 43*d39a76e7Sxw * Definitions for module_info 44*d39a76e7Sxw */ 45*d39a76e7Sxw 46*d39a76e7Sxw #define CHIDNUM (666) /* module ID number */ 47*d39a76e7Sxw #define CHNAME "chxge" /* module name */ 48*d39a76e7Sxw #define CHMINPSZ (0) /* min packet size */ 49*d39a76e7Sxw #define CHMAXPSZ ETHERMTU /* max packet size */ 50*d39a76e7Sxw #define CHHIWAT (32 * 1024) /* hi-water mark */ 51*d39a76e7Sxw #define CHLOWAT (1) /* lo-water mark */ 52*d39a76e7Sxw 53*d39a76e7Sxw #define CH_NO_HWCKSUM 0x1 /* hardware should no add checksum */ 54*d39a76e7Sxw #define CH_NO_CPL 0x2 /* no cpl header with data */ 55*d39a76e7Sxw #define CH_OFFLOAD 0x4 /* do TCP/IP offload processing */ 56*d39a76e7Sxw #define CH_ARP 0x8 /* dummy arp packet (don't free) */ 57*d39a76e7Sxw #define CH_TCP_MF 0x10 /* Indicator of Fragmented TCP */ 58*d39a76e7Sxw #define CH_UDP_MF 0x20 /* Indicator of Fragmented UDP */ 59*d39a76e7Sxw #define CH_UDP 0x40 /* Indicator of regular TCP */ 60*d39a76e7Sxw 61*d39a76e7Sxw #define SZ_INUSE 64 /* # of in use counters */ 62*d39a76e7Sxw 63*d39a76e7Sxw /* 64*d39a76e7Sxw * PCI registers 65*d39a76e7Sxw */ 66*d39a76e7Sxw #define BAR0 1 67*d39a76e7Sxw #define BAR1 2 68*d39a76e7Sxw #define BAR2 3 69*d39a76e7Sxw #define BAR3 4 70*d39a76e7Sxw 71*d39a76e7Sxw #ifdef CONFIG_CHELSIO_T1_OFFLOAD 72*d39a76e7Sxw /* 73*d39a76e7Sxw * TOE pre-mapped buffer structure 74*d39a76e7Sxw */ 75*d39a76e7Sxw typedef struct tbuf { 76*d39a76e7Sxw struct tbuf *tb_next; /* next entry in free list */ 77*d39a76e7Sxw caddr_t tb_base; /* base of buffer */ 78*d39a76e7Sxw uint64_t tb_pa; /* physical address of buffer */ 79*d39a76e7Sxw ulong_t tb_dh; /* dma handle */ 80*d39a76e7Sxw ulong_t tb_ah; /* dma address handle */ 81*d39a76e7Sxw void *tb_sa; /* address of card ctrl struct */ 82*d39a76e7Sxw uint32_t tb_debug; /* initally 0 */ 83*d39a76e7Sxw uint32_t tb_len; /* length of data */ 84*d39a76e7Sxw } tbuf_t; 85*d39a76e7Sxw #endif /* CONFIG_CHELSIO_T1_OFFLOAD */ 86*d39a76e7Sxw 87*d39a76e7Sxw /* 88*d39a76e7Sxw * header structures to hold pre-mapped (DMA) kernel memory buffers. 89*d39a76e7Sxw */ 90*d39a76e7Sxw typedef struct ch_esb { 91*d39a76e7Sxw struct ch_esb *cs_next; /* next entry in list */ 92*d39a76e7Sxw struct ch_esb *cs_owner; /* list of buffers owned by ch_t */ 93*d39a76e7Sxw void *cs_sa; /* card structure to get ch ptr */ 94*d39a76e7Sxw ulong_t cs_dh; /* dma handle */ 95*d39a76e7Sxw ulong_t cs_ah; /* dma address handle */ 96*d39a76e7Sxw caddr_t cs_buf; /* vaddr of buffer */ 97*d39a76e7Sxw uint64_t cs_pa; /* paddr of buffer */ 98*d39a76e7Sxw uint32_t cs_index; /* index of buffer_in_use count */ 99*d39a76e7Sxw uint32_t cs_flag; /* if set, commit suicide */ 100*d39a76e7Sxw #ifdef FRAGMENT /* we assume no fragments */ 101*d39a76e7Sxw ddi_dma_cookie_t cs_cookie[MAXFS]; 102*d39a76e7Sxw uint_t cs_ncookie; 103*d39a76e7Sxw #endif 104*d39a76e7Sxw frtn_t cs_frtn; /* for esballoc */ 105*d39a76e7Sxw } ch_esb_t; 106*d39a76e7Sxw 107*d39a76e7Sxw /* 108*d39a76e7Sxw * structure for linked list of multicast addresses that have been 109*d39a76e7Sxw * assigned to the card. 110*d39a76e7Sxw */ 111*d39a76e7Sxw typedef struct ch_mc { 112*d39a76e7Sxw struct ch_mc *cmc_next; 113*d39a76e7Sxw uint8_t cmc_mca[6]; 114*d39a76e7Sxw } ch_mc_t; 115*d39a76e7Sxw 116*d39a76e7Sxw /* 117*d39a76e7Sxw * structure for linked list of pre-allocated dma handles for command Q 118*d39a76e7Sxw */ 119*d39a76e7Sxw typedef struct free_dh { 120*d39a76e7Sxw struct free_dh *dhe_next; 121*d39a76e7Sxw ulong_t dhe_dh; 122*d39a76e7Sxw } free_dh_t; 123*d39a76e7Sxw 124*d39a76e7Sxw /* 125*d39a76e7Sxw * instance configuration 126*d39a76e7Sxw */ 127*d39a76e7Sxw typedef struct ch_cfg { 128*d39a76e7Sxw uint32_t cksum_enabled: 1; 129*d39a76e7Sxw uint32_t burstsize_set: 1; 130*d39a76e7Sxw uint32_t burstsize: 2; 131*d39a76e7Sxw uint32_t transaction_cnt_set: 1; 132*d39a76e7Sxw uint32_t transaction_cnt: 3; 133*d39a76e7Sxw uint32_t relaxed_ordering: 1; 134*d39a76e7Sxw uint32_t enable_dvma: 1; 135*d39a76e7Sxw } ch_cfg_t; 136*d39a76e7Sxw 137*d39a76e7Sxw /* 138*d39a76e7Sxw * Per-card state information 139*d39a76e7Sxw */ 140*d39a76e7Sxw typedef struct ch { 141*d39a76e7Sxw dev_info_t *ch_dip; /* device dev info */ 142*d39a76e7Sxw gld_mac_info_t *ch_macp; /* gld mac structure */ 143*d39a76e7Sxw 144*d39a76e7Sxw ch_cfg_t ch_config; /* instance configuration */ 145*d39a76e7Sxw uint_t ch_flags; /* state flags */ 146*d39a76e7Sxw uint_t ch_state; /* card state */ 147*d39a76e7Sxw uint_t ch_blked; /* card is blked on output */ 148*d39a76e7Sxw kmutex_t ch_lock; /* lock for ch structure */ 149*d39a76e7Sxw 150*d39a76e7Sxw caddr_t ch_pci; /* PCI configuration vaddr */ 151*d39a76e7Sxw ddi_acc_handle_t ch_hpci; /* PCI configuration access handle */ 152*d39a76e7Sxw off_t ch_pcisz; /* size of PCI configuration space */ 153*d39a76e7Sxw 154*d39a76e7Sxw caddr_t ch_bar0; /* PCI BAR0 vaddr */ 155*d39a76e7Sxw ddi_acc_handle_t ch_hbar0; /* PCI BAR0 access handle */ 156*d39a76e7Sxw off_t ch_bar0sz; /* size of BAR0 space */ 157*d39a76e7Sxw 158*d39a76e7Sxw ddi_iblock_cookie_t ch_icookp; /* hardware interrupt cookie ptr */ 159*d39a76e7Sxw kmutex_t ch_intr; /* lock for interrupts */ 160*d39a76e7Sxw 161*d39a76e7Sxw uint32_t ch_maximum_mtu; /* maximum mtu for adapter */ 162*d39a76e7Sxw 163*d39a76e7Sxw uint32_t ch_sm_buf_sz; /* size of sm esballoc bufs */ 164*d39a76e7Sxw uint32_t ch_sm_buf_aln; /* alignment of sm esballoc bufs */ 165*d39a76e7Sxw ch_esb_t *ch_small_esb_free; /* free list sm esballoc bufs */ 166*d39a76e7Sxw ch_esb_t *ch_small_owner; /* list small bufs owned by ch_t */ 167*d39a76e7Sxw kmutex_t ch_small_esbl; /* lock for ch_small_esb list */ 168*d39a76e7Sxw uint_t ch_sm_index; /* small buffer in use count index */ 169*d39a76e7Sxw 170*d39a76e7Sxw uint32_t ch_bg_buf_sz; /* size of bg esballoc bufs */ 171*d39a76e7Sxw uint32_t ch_bg_buf_aln; /* alignment of bg esballoc bufs */ 172*d39a76e7Sxw ch_esb_t *ch_big_esb_free; /* free list of esballoc entries */ 173*d39a76e7Sxw ch_esb_t *ch_big_owner; /* list big bufs owned by ch_t */ 174*d39a76e7Sxw kmutex_t ch_big_esbl; /* lock for ch_esb list */ 175*d39a76e7Sxw uint_t ch_big_index; /* big buffer in use count index */ 176*d39a76e7Sxw 177*d39a76e7Sxw kmutex_t ch_mc_lck; /* lock of mulitcast list */ 178*d39a76e7Sxw ch_mc_t *ch_mc; /* list of multicast entries */ 179*d39a76e7Sxw uint32_t ch_mc_cnt; /* cnt of multicast entries */ 180*d39a76e7Sxw 181*d39a76e7Sxw /* XXX see how we can use cmdQ_ce list and get rid of lock */ 182*d39a76e7Sxw kmutex_t ch_dh_lck; /* lock for ch_dh list */ 183*d39a76e7Sxw free_dh_t *ch_dh; /* list of free dma headers for v2p */ 184*d39a76e7Sxw 185*d39a76e7Sxw #if defined(__sparc) 186*d39a76e7Sxw /* XXX see how we can use cmdQ_ce list and get rid of lock */ 187*d39a76e7Sxw free_dh_t *ch_vdh; /* list of free dvma headers for v2p */ 188*d39a76e7Sxw #endif 189*d39a76e7Sxw 190*d39a76e7Sxw uint32_t ch_ip; /* ip address from first arp */ 191*d39a76e7Sxw 192*d39a76e7Sxw uint32_t ch_mtu; /* size of device MTU (1500 default) */ 193*d39a76e7Sxw 194*d39a76e7Sxw /* XXX config_data needs cleanup */ 195*d39a76e7Sxw pe_config_data_t config_data; /* card configuration vector */ 196*d39a76e7Sxw 197*d39a76e7Sxw struct pe_port_t port[4]; /* from freebsd/oschtoe.h driver */ 198*d39a76e7Sxw pesge *sge; 199*d39a76e7Sxw struct pemc3 *mc3; 200*d39a76e7Sxw struct pemc4 *mc4; 201*d39a76e7Sxw struct pemc5 *mc5; 202*d39a76e7Sxw struct petp *tp; 203*d39a76e7Sxw struct pecspi *cspi; 204*d39a76e7Sxw struct peespi *espi; 205*d39a76e7Sxw struct peulp *ulp; 206*d39a76e7Sxw #ifdef CONFIG_CHELSIO_T1_OFFLOAD 207*d39a76e7Sxw uint32_t open_device_map; 208*d39a76e7Sxw #endif 209*d39a76e7Sxw struct adapter_params params; 210*d39a76e7Sxw uint16_t vendor_id; 211*d39a76e7Sxw uint16_t device_id; 212*d39a76e7Sxw uint16_t device_subid; 213*d39a76e7Sxw uint16_t chip_revision; 214*d39a76e7Sxw uint16_t chip_version; 215*d39a76e7Sxw uint32_t is_asic; 216*d39a76e7Sxw uint32_t config; 217*d39a76e7Sxw uint32_t ch_unit; 218*d39a76e7Sxw uint8_t init_counter; 219*d39a76e7Sxw char *ch_name; 220*d39a76e7Sxw /* statistics per card */ 221*d39a76e7Sxw uint32_t isr_intr; /* # interrupts */ 222*d39a76e7Sxw uint32_t oerr; /* send error (no mem) */ 223*d39a76e7Sxw uint32_t norcvbuf; 224*d39a76e7Sxw #ifdef CONFIG_CHELSIO_T1_OFFLOAD 225*d39a76e7Sxw int ch_refcnt; 226*d39a76e7Sxw void *ch_toeinst; 227*d39a76e7Sxw void (*toe_rcv)(void *, mblk_t *); 228*d39a76e7Sxw void (*toe_free)(void *, tbuf_t *); 229*d39a76e7Sxw int (*toe_tunnel)(void *, mblk_t *); 230*d39a76e7Sxw kcondvar_t *ch_tx_overflow_cv; 231*d39a76e7Sxw kmutex_t *ch_tx_overflow_mutex; 232*d39a76e7Sxw #endif 233*d39a76e7Sxw uint32_t slow_intr_mask; 234*d39a76e7Sxw #ifdef HOST_PAUSE 235*d39a76e7Sxw uint32_t txxg_cfg1; /* Place holder for MAC cfg reg1. */ 236*d39a76e7Sxw int pause_on; 237*d39a76e7Sxw hrtime_t pause_time; 238*d39a76e7Sxw #endif 239*d39a76e7Sxw kmutex_t mac_lock; /* lock for MAC structure */ 240*d39a76e7Sxw } ch_t; 241*d39a76e7Sxw 242*d39a76e7Sxw /* ch_flags */ 243*d39a76e7Sxw #define PEIDLE 0x00 /* chip is uninitialized */ 244*d39a76e7Sxw #define PERUNNING 0x01 /* chip is initialized */ 245*d39a76e7Sxw #define PEPROMISC 0x04 /* promiscuous mode enabled */ 246*d39a76e7Sxw #define PEALLMULTI 0x08 /* all multicast enabled */ 247*d39a76e7Sxw #define PESUSPENDED 0x20 /* suspended interface */ 248*d39a76e7Sxw #define PENORES 0x40 /* ran out of xmit resources */ 249*d39a76e7Sxw #define PESTOP 0x80 /* gldm_stop done */ 250*d39a76e7Sxw #define PEINITDONE 0x100 /* initialization done */ 251*d39a76e7Sxw #define TSO_CAPABLE 0x200 /* TSO able */ 252*d39a76e7Sxw 253*d39a76e7Sxw #ifdef CONFIG_CHELSIO_T1_OFFLOAD 254*d39a76e7Sxw /* open_device_map flag */ 255*d39a76e7Sxw #define TOEDEV_DEVMAP_BIT 0x1 256*d39a76e7Sxw #endif 257*d39a76e7Sxw 258*d39a76e7Sxw /* 259*d39a76e7Sxw * DMA mapping defines 260*d39a76e7Sxw */ 261*d39a76e7Sxw #define DMA_STREAM 1 /* use DDI_DMA_STREAMING for DMA xfers */ 262*d39a76e7Sxw #define DMA_4KALN 2 /* align memory to 4K page boundry */ 263*d39a76e7Sxw #define DMA_OUT 4 /* this is a write buffer */ 264*d39a76e7Sxw #define DMA_SMALN 8 /* aligned at small buffer boundry */ 265*d39a76e7Sxw #define DMA_BGALN 16 /* aligned at big buffer boundry */ 266*d39a76e7Sxw 267*d39a76e7Sxw /* 268*d39a76e7Sxw * Number of multicast addresses per stream 269*d39a76e7Sxw */ 270*d39a76e7Sxw #define CHMAXMC 64 271*d39a76e7Sxw #define CHMCALLOC (CHMAXMC * sizeof (struct ether_addr)) 272*d39a76e7Sxw 273*d39a76e7Sxw /* ----- Solaris memory - PCI - DMA mapping functions ------ */ 274*d39a76e7Sxw 275*d39a76e7Sxw void *ch_alloc_dma_mem(ch_t *, int, int, int, uint64_t *, ulong_t *, ulong_t *); 276*d39a76e7Sxw void ch_free_dma_mem(ulong_t, ulong_t); 277*d39a76e7Sxw void ch_unbind_dma_handle(ch_t *, free_dh_t *); 278*d39a76e7Sxw 279*d39a76e7Sxw void ch_send_up(ch_t *, mblk_t *, uint32_t, int); 280*d39a76e7Sxw 281*d39a76e7Sxw void ch_gld_ok(ch_t *); 282*d39a76e7Sxw 283*d39a76e7Sxw uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val); 284*d39a76e7Sxw void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val); 285*d39a76e7Sxw uint32_t t1_os_pci_read_config_2(ch_t *obj, uint32_t reg, uint16_t *val); 286*d39a76e7Sxw uint32_t t1_os_pci_read_config_4(ch_t *obj, uint32_t reg, uint32_t *val); 287*d39a76e7Sxw int t1_os_pci_write_config_2(ch_t *obj, uint32_t reg, uint16_t val); 288*d39a76e7Sxw int t1_os_pci_write_config_4(ch_t *obj, uint32_t reg, uint32_t val); 289*d39a76e7Sxw uint32_t le32_to_cpu(uint32_t data); 290*d39a76e7Sxw 291*d39a76e7Sxw void *t1_os_malloc_wait_zero(size_t len); 292*d39a76e7Sxw void t1_os_free(void *adr, size_t len); 293*d39a76e7Sxw int t1_num_of_ports(ch_t *obj); 294*d39a76e7Sxw int pe_os_mem_copy(ch_t *obj, void *dst, void *src, size_t len); 295*d39a76e7Sxw void *pe_os_malloc_contig_wait_zero(ch_t *, size_t, uint64_t *, 296*d39a76e7Sxw ulong_t *, ulong_t *, uint32_t); 297*d39a76e7Sxw void pe_set_mac(ch_t *sa, unsigned char *ac_enaddr); 298*d39a76e7Sxw unsigned char *pe_get_mac(ch_t *sa); 299*d39a76e7Sxw void pe_set_promiscuous(ch_t *sa, int flag); 300*d39a76e7Sxw int pe_get_stats(ch_t *sa, uint64_t *speed, uint32_t *intrcnt, 301*d39a76e7Sxw uint32_t *norcvbuf, uint32_t *oerrors, uint32_t *ierrors, 302*d39a76e7Sxw uint32_t *underrun, uint32_t *overrun, uint32_t *framing, 303*d39a76e7Sxw uint32_t *crc, uint32_t *carrier, uint32_t *collisions, 304*d39a76e7Sxw uint32_t *xcollisions, uint32_t *late, uint32_t *defer, 305*d39a76e7Sxw uint32_t *xerrs, uint32_t *rerrs, uint32_t *toolong, uint32_t *runt, 306*d39a76e7Sxw ulong_t *multixmt, ulong_t *multircv, ulong_t *brdcstxmt, 307*d39a76e7Sxw ulong_t *brdcstrcv); 308*d39a76e7Sxw int pe_attach(ch_t *); 309*d39a76e7Sxw void pe_detach(ch_t *); 310*d39a76e7Sxw void pe_init(void *); 311*d39a76e7Sxw uint_t pe_intr(ch_t *); 312*d39a76e7Sxw 313*d39a76e7Sxw #ifdef CONFIG_CHELSIO_T1_OFFLOAD 314*d39a76e7Sxw #define toe_running(a) (a->open_device_map & TOEDEV_DEVMAP_BIT) 315*d39a76e7Sxw #endif 316*d39a76e7Sxw 317*d39a76e7Sxw int pe_start(ch_t *sa, mblk_t *mb, uint32_t flg); 318*d39a76e7Sxw void pe_stop(ch_t *sa); 319*d39a76e7Sxw void pe_ioctl(ch_t *, queue_t *, mblk_t *); 320*d39a76e7Sxw int pe_set_mc(ch_t *, uint8_t *, int); 321*d39a76e7Sxw 322*d39a76e7Sxw int tpi_read(ch_t *obj, u32 addr, u32 *value); 323*d39a76e7Sxw 324*d39a76e7Sxw void CH_ALERT(const char *fmt, ...); 325*d39a76e7Sxw void CH_WARN(const char *fmt, ...); 326*d39a76e7Sxw void CH_ERR(const char *fmt, ...); 327*d39a76e7Sxw void t1_fatal_err(ch_t *chp); 328*d39a76e7Sxw 329*d39a76e7Sxw #define memset(s, c, n) bzero(s, n) 330*d39a76e7Sxw 331*d39a76e7Sxw extern int enable_checksum_offload; 332*d39a76e7Sxw 333*d39a76e7Sxw void pe_dma_handle_init(ch_t *, int); 334*d39a76e7Sxw free_dh_t *ch_get_dma_handle(ch_t *); 335*d39a76e7Sxw 336*d39a76e7Sxw void pe_free_fake_arp(void *); 337*d39a76e7Sxw 338*d39a76e7Sxw void pe_mark_freelists(ch_t *chp); 339*d39a76e7Sxw 340*d39a76e7Sxw #if defined(__sparc) 341*d39a76e7Sxw free_dh_t *ch_get_dvma_handle(ch_t *); 342*d39a76e7Sxw void ch_unbind_dvma_handle(ch_t *, free_dh_t *); 343*d39a76e7Sxw #endif 344*d39a76e7Sxw 345*d39a76e7Sxw #define AMD_VENDOR_ID 0x1022 346*d39a76e7Sxw #define AMD_BRIDGE 0x7450 347*d39a76e7Sxw #define AMD_BRIDGE_REV 0x12 348*d39a76e7Sxw 349*d39a76e7Sxw #ifdef __cplusplus 350*d39a76e7Sxw } 351*d39a76e7Sxw #endif 352*d39a76e7Sxw 353*d39a76e7Sxw #endif /* _CHELSIO_CH_H */ 354