1*d14abf15SRobert Mustacchi #ifndef __devinfo_h__ 2*d14abf15SRobert Mustacchi #define __devinfo_h__ 3*d14abf15SRobert Mustacchi 4*d14abf15SRobert Mustacchi #include "mac_drv_info.h" 5*d14abf15SRobert Mustacchi 6*d14abf15SRobert Mustacchi /**************************************************************************** 7*d14abf15SRobert Mustacchi * Shared HW configuration * 8*d14abf15SRobert Mustacchi ****************************************************************************/ 9*d14abf15SRobert Mustacchi #define PIN_CFG_NA 0x00000000 10*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO0_P0 0x00000001 11*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO1_P0 0x00000002 12*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO2_P0 0x00000003 13*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO3_P0 0x00000004 14*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO0_P1 0x00000005 15*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO1_P1 0x00000006 16*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO2_P1 0x00000007 17*d14abf15SRobert Mustacchi #define PIN_CFG_GPIO3_P1 0x00000008 18*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO0 0x00000009 19*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO1 0x0000000a 20*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO2 0x0000000b 21*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO3 0x0000000c 22*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO4 0x0000000d 23*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO5 0x0000000e 24*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO6 0x0000000f 25*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO7 0x00000010 26*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO8 0x00000011 27*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO9 0x00000012 28*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO10 0x00000013 29*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO11 0x00000014 30*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO12 0x00000015 31*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO13 0x00000016 32*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO14 0x00000017 33*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO15 0x00000018 34*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO16 0x00000019 35*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO17 0x0000001a 36*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO18 0x0000001b 37*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO19 0x0000001c 38*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO20 0x0000001d 39*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO21 0x0000001e 40*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO22 0x0000001f 41*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO23 0x00000020 42*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO24 0x00000021 43*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO25 0x00000022 44*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO26 0x00000023 45*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO27 0x00000024 46*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO28 0x00000025 47*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO29 0x00000026 48*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO30 0x00000027 49*d14abf15SRobert Mustacchi #define PIN_CFG_EPIO31 0x00000028 50*d14abf15SRobert Mustacchi 51*d14abf15SRobert Mustacchi /* EPIO definition */ 52*d14abf15SRobert Mustacchi #define EPIO_CFG_NA 0x00000000 53*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO0 0x00000001 54*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO1 0x00000002 55*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO2 0x00000003 56*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO3 0x00000004 57*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO4 0x00000005 58*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO5 0x00000006 59*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO6 0x00000007 60*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO7 0x00000008 61*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO8 0x00000009 62*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO9 0x0000000a 63*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO10 0x0000000b 64*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO11 0x0000000c 65*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO12 0x0000000d 66*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO13 0x0000000e 67*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO14 0x0000000f 68*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO15 0x00000010 69*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO16 0x00000011 70*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO17 0x00000012 71*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO18 0x00000013 72*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO19 0x00000014 73*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO20 0x00000015 74*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO21 0x00000016 75*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO22 0x00000017 76*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO23 0x00000018 77*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO24 0x00000019 78*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO25 0x0000001a 79*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO26 0x0000001b 80*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO27 0x0000001c 81*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO28 0x0000001d 82*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO29 0x0000001e 83*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO30 0x0000001f 84*d14abf15SRobert Mustacchi #define EPIO_CFG_EPIO31 0x00000020 85*d14abf15SRobert Mustacchi 86*d14abf15SRobert Mustacchi struct mac_addr { 87*d14abf15SRobert Mustacchi u32 upper; 88*d14abf15SRobert Mustacchi u32 lower; 89*d14abf15SRobert Mustacchi }; 90*d14abf15SRobert Mustacchi 91*d14abf15SRobert Mustacchi 92*d14abf15SRobert Mustacchi 93*d14abf15SRobert Mustacchi struct shared_hw_cfg { /* NVRAM Offset */ 94*d14abf15SRobert Mustacchi /* Up to 16 bytes of NULL-terminated string */ 95*d14abf15SRobert Mustacchi u8 part_num[16]; /* 0x104 */ 96*d14abf15SRobert Mustacchi 97*d14abf15SRobert Mustacchi u32 config; /* 0x114 */ 98*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 99*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 100*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 101*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 102*d14abf15SRobert Mustacchi 103*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PORT_SWAP 0x00000004 104*d14abf15SRobert Mustacchi 105*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 106*d14abf15SRobert Mustacchi 107*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 108*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 109*d14abf15SRobert Mustacchi 110*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 111*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 112*d14abf15SRobert Mustacchi /* Whatever MFW found in NVM 113*d14abf15SRobert Mustacchi (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 114*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 115*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 116*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 117*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 118*d14abf15SRobert Mustacchi /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 119*d14abf15SRobert Mustacchi (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 120*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 121*d14abf15SRobert Mustacchi /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 122*d14abf15SRobert Mustacchi (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 123*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 124*d14abf15SRobert Mustacchi /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 125*d14abf15SRobert Mustacchi (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 126*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 127*d14abf15SRobert Mustacchi 128*d14abf15SRobert Mustacchi /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 129*d14abf15SRobert Mustacchi backwards compatibility, value of 0 is disabling this feature. 130*d14abf15SRobert Mustacchi That means that though 0 is a valid value, it cannot be 131*d14abf15SRobert Mustacchi configured. */ 132*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 133*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 134*d14abf15SRobert Mustacchi 135*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 136*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_MODE_SHIFT 16 137*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_MAC1 0x00000000 138*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY1 0x00010000 139*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY2 0x00020000 140*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY3 0x00030000 141*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_MAC2 0x00040000 142*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY4 0x00050000 143*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY5 0x00060000 144*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY6 0x00070000 145*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_MAC3 0x00080000 146*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY7 0x00090000 147*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY9 0x000a0000 148*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY11 0x000b0000 149*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_MAC4 0x000c0000 150*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_PHY8 0x000d0000 151*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 152*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 153*d14abf15SRobert Mustacchi 154*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 155*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 156*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 157*d14abf15SRobert Mustacchi 158*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ATC_MASK 0x80000000 159*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 160*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 161*d14abf15SRobert Mustacchi 162*d14abf15SRobert Mustacchi u32 config2; /* 0x118 */ 163*d14abf15SRobert Mustacchi 164*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 165*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 166*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 167*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 168*d14abf15SRobert Mustacchi 169*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 170*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 171*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 172*d14abf15SRobert Mustacchi 173*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 174*d14abf15SRobert Mustacchi 175*d14abf15SRobert Mustacchi 176*d14abf15SRobert Mustacchi 177*d14abf15SRobert Mustacchi /* Output low when PERST is asserted */ 178*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 179*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 180*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 181*d14abf15SRobert Mustacchi 182*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 183*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 184*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 185*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 186*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 187*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 188*d14abf15SRobert Mustacchi 189*d14abf15SRobert Mustacchi /* The fan failure mechanism is usually related to the PHY type 190*d14abf15SRobert Mustacchi since the power consumption of the board is determined by the PHY. 191*d14abf15SRobert Mustacchi Currently, fan is required for most designs with SFX7101, BCM8727 192*d14abf15SRobert Mustacchi and BCM8481. If a fan is not required for a board which uses one 193*d14abf15SRobert Mustacchi of those PHYs, this field should be set to "Disabled". If a fan is 194*d14abf15SRobert Mustacchi required for a different PHY type, this option should be set to 195*d14abf15SRobert Mustacchi "Enabled". The fan failure indication is expected on SPIO5 */ 196*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 197*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 198*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 199*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 200*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 201*d14abf15SRobert Mustacchi 202*d14abf15SRobert Mustacchi /* ASPM Power Management support */ 203*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 204*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 205*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 206*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 207*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 208*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 209*d14abf15SRobert Mustacchi 210*d14abf15SRobert Mustacchi /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 211*d14abf15SRobert Mustacchi tl_control_0 (register 0x2800) */ 212*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 213*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 214*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 215*d14abf15SRobert Mustacchi 216*d14abf15SRobert Mustacchi 217*d14abf15SRobert Mustacchi /* Set the MDC/MDIO access for the first external phy */ 218*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 219*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 220*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 221*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 222*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 223*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 224*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 225*d14abf15SRobert Mustacchi 226*d14abf15SRobert Mustacchi /* Set the MDC/MDIO access for the second external phy */ 227*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 228*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 229*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 230*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 231*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 232*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 233*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 234*d14abf15SRobert Mustacchi 235*d14abf15SRobert Mustacchi /* Max number of PF MSIX vectors */ 236*d14abf15SRobert Mustacchi u32 config_3; /* 0x11C */ 237*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 238*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 239*d14abf15SRobert Mustacchi 240*d14abf15SRobert Mustacchi /* This field extends the mf mode chosen in nvm cfg #73 (as we ran 241*d14abf15SRobert Mustacchi out of bits) */ 242*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 243*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 244*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 245*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 246*d14abf15SRobert Mustacchi 247*d14abf15SRobert Mustacchi u32 ump_nc_si_config; /* 0x120 */ 248*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 249*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 250*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 251*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 252*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 253*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 254*d14abf15SRobert Mustacchi 255*d14abf15SRobert Mustacchi /* Reserved bits: 226-230 */ 256*d14abf15SRobert Mustacchi 257*d14abf15SRobert Mustacchi /* The output pin template BSC_SEL which selects the I2C for this 258*d14abf15SRobert Mustacchi port in the I2C Mux */ 259*d14abf15SRobert Mustacchi u32 board; /* 0x124 */ 260*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 261*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 262*d14abf15SRobert Mustacchi 263*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 264*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 265*d14abf15SRobert Mustacchi /* Use the PIN_CFG_XXX defines on top */ 266*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 267*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 268*d14abf15SRobert Mustacchi 269*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 270*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 271*d14abf15SRobert Mustacchi 272*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 273*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 274*d14abf15SRobert Mustacchi 275*d14abf15SRobert Mustacchi u32 wc_lane_config; /* 0x128 */ 276*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 277*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 278*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 279*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 280*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 281*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 282*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 283*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 284*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 285*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 286*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 287*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 288*d14abf15SRobert Mustacchi 289*d14abf15SRobert Mustacchi /* TX lane Polarity swap */ 290*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 291*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 292*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 293*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 294*d14abf15SRobert Mustacchi /* TX lane Polarity swap */ 295*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 296*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 297*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 298*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 299*d14abf15SRobert Mustacchi 300*d14abf15SRobert Mustacchi /* Selects the port layout of the board */ 301*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 302*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 303*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 304*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 305*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 306*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 307*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 308*d14abf15SRobert Mustacchi #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 309*d14abf15SRobert Mustacchi }; 310*d14abf15SRobert Mustacchi 311*d14abf15SRobert Mustacchi 312*d14abf15SRobert Mustacchi /**************************************************************************** 313*d14abf15SRobert Mustacchi * Port HW configuration * 314*d14abf15SRobert Mustacchi ****************************************************************************/ 315*d14abf15SRobert Mustacchi struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 316*d14abf15SRobert Mustacchi 317*d14abf15SRobert Mustacchi u32 pci_id; 318*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 319*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 320*d14abf15SRobert Mustacchi 321*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 322*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 323*d14abf15SRobert Mustacchi 324*d14abf15SRobert Mustacchi u32 pci_sub_id; 325*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 326*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 327*d14abf15SRobert Mustacchi 328*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 329*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 330*d14abf15SRobert Mustacchi 331*d14abf15SRobert Mustacchi u32 power_dissipated; 332*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 333*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 334*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 335*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 336*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 337*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 338*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 339*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 340*d14abf15SRobert Mustacchi 341*d14abf15SRobert Mustacchi u32 power_consumed; 342*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 343*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 344*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 345*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 346*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 347*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 348*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 349*d14abf15SRobert Mustacchi #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 350*d14abf15SRobert Mustacchi 351*d14abf15SRobert Mustacchi u32 mac_upper; 352*d14abf15SRobert Mustacchi u32 mac_lower; /* 0x140 */ 353*d14abf15SRobert Mustacchi #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 354*d14abf15SRobert Mustacchi #define PORT_HW_CFG_UPPERMAC_SHIFT 0 355*d14abf15SRobert Mustacchi 356*d14abf15SRobert Mustacchi 357*d14abf15SRobert Mustacchi u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 358*d14abf15SRobert Mustacchi u32 iscsi_mac_lower; 359*d14abf15SRobert Mustacchi 360*d14abf15SRobert Mustacchi u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 361*d14abf15SRobert Mustacchi u32 rdma_mac_lower; 362*d14abf15SRobert Mustacchi 363*d14abf15SRobert Mustacchi u32 serdes_config; 364*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 365*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 366*d14abf15SRobert Mustacchi 367*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 368*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 369*d14abf15SRobert Mustacchi 370*d14abf15SRobert Mustacchi 371*d14abf15SRobert Mustacchi /* Default values: 2P-64, 4P-32 */ 372*d14abf15SRobert Mustacchi u32 reserved; 373*d14abf15SRobert Mustacchi 374*d14abf15SRobert Mustacchi u32 vf_config; /* 0x15C */ 375*d14abf15SRobert Mustacchi #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 376*d14abf15SRobert Mustacchi #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 377*d14abf15SRobert Mustacchi 378*d14abf15SRobert Mustacchi u32 mf_pci_id; /* 0x160 */ 379*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 380*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 381*d14abf15SRobert Mustacchi 382*d14abf15SRobert Mustacchi /* Controls the TX laser of the SFP+ module */ 383*d14abf15SRobert Mustacchi u32 sfp_ctrl; /* 0x164 */ 384*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 385*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_SHIFT 0 386*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 387*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 388*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 389*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 390*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 391*d14abf15SRobert Mustacchi 392*d14abf15SRobert Mustacchi /* Controls the fault module LED of the SFP+ */ 393*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 394*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 395*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 396*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 397*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 398*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 399*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 400*d14abf15SRobert Mustacchi 401*d14abf15SRobert Mustacchi /* The output pin TX_DIS that controls the TX laser of the SFP+ 402*d14abf15SRobert Mustacchi module. Use the PIN_CFG_XXX defines on top */ 403*d14abf15SRobert Mustacchi u32 e3_sfp_ctrl; /* 0x168 */ 404*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 405*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 406*d14abf15SRobert Mustacchi 407*d14abf15SRobert Mustacchi /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 408*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 409*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 410*d14abf15SRobert Mustacchi 411*d14abf15SRobert Mustacchi /* The input pin MOD_ABS that indicates whether SFP+ module is 412*d14abf15SRobert Mustacchi present or not. Use the PIN_CFG_XXX defines on top */ 413*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 414*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 415*d14abf15SRobert Mustacchi 416*d14abf15SRobert Mustacchi /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 417*d14abf15SRobert Mustacchi module. Use the PIN_CFG_XXX defines on top */ 418*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 419*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 420*d14abf15SRobert Mustacchi 421*d14abf15SRobert Mustacchi /* 422*d14abf15SRobert Mustacchi * The input pin which signals module transmit fault. Use the 423*d14abf15SRobert Mustacchi * PIN_CFG_XXX defines on top 424*d14abf15SRobert Mustacchi */ 425*d14abf15SRobert Mustacchi u32 e3_cmn_pin_cfg; /* 0x16C */ 426*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 427*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 428*d14abf15SRobert Mustacchi 429*d14abf15SRobert Mustacchi /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 430*d14abf15SRobert Mustacchi top */ 431*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 432*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 433*d14abf15SRobert Mustacchi 434*d14abf15SRobert Mustacchi /* 435*d14abf15SRobert Mustacchi * The output pin which powers down the PHY. Use the PIN_CFG_XXX 436*d14abf15SRobert Mustacchi * defines on top 437*d14abf15SRobert Mustacchi */ 438*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 439*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 440*d14abf15SRobert Mustacchi 441*d14abf15SRobert Mustacchi /* The output pin values BSC_SEL which selects the I2C for this port 442*d14abf15SRobert Mustacchi in the I2C Mux */ 443*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 444*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 445*d14abf15SRobert Mustacchi 446*d14abf15SRobert Mustacchi 447*d14abf15SRobert Mustacchi /* 448*d14abf15SRobert Mustacchi * The input pin I_FAULT which indicate over-current has occurred. 449*d14abf15SRobert Mustacchi * Use the PIN_CFG_XXX defines on top 450*d14abf15SRobert Mustacchi */ 451*d14abf15SRobert Mustacchi u32 e3_cmn_pin_cfg1; /* 0x170 */ 452*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 453*d14abf15SRobert Mustacchi #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 454*d14abf15SRobert Mustacchi 455*d14abf15SRobert Mustacchi /* pause on host ring */ 456*d14abf15SRobert Mustacchi u32 generic_features; /* 0x174 */ 457*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 458*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 459*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 460*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 461*d14abf15SRobert Mustacchi 462*d14abf15SRobert Mustacchi /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 463*d14abf15SRobert Mustacchi * LOM recommended and tested value is 0xBEB2. Using a different 464*d14abf15SRobert Mustacchi * value means using a value not tested by BRCM 465*d14abf15SRobert Mustacchi */ 466*d14abf15SRobert Mustacchi u32 sfi_tap_values; /* 0x178 */ 467*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 468*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 469*d14abf15SRobert Mustacchi 470*d14abf15SRobert Mustacchi /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 471*d14abf15SRobert Mustacchi * value is 0x2. LOM recommended and tested value is 0x2. Using a 472*d14abf15SRobert Mustacchi * different value means using a value not tested by BRCM 473*d14abf15SRobert Mustacchi */ 474*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 475*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 476*d14abf15SRobert Mustacchi 477*d14abf15SRobert Mustacchi u32 reserved0[5]; /* 0x17c */ 478*d14abf15SRobert Mustacchi 479*d14abf15SRobert Mustacchi u32 aeu_int_mask; /* 0x190 */ 480*d14abf15SRobert Mustacchi 481*d14abf15SRobert Mustacchi u32 media_type; /* 0x194 */ 482*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 483*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 484*d14abf15SRobert Mustacchi 485*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 486*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 487*d14abf15SRobert Mustacchi 488*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 489*d14abf15SRobert Mustacchi #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 490*d14abf15SRobert Mustacchi 491*d14abf15SRobert Mustacchi /* 4 times 16 bits for all 4 lanes. In case external PHY is present 492*d14abf15SRobert Mustacchi (not direct mode), those values will not take effect on the 4 XGXS 493*d14abf15SRobert Mustacchi lanes. For some external PHYs (such as 8706 and 8726) the values 494*d14abf15SRobert Mustacchi will be used to configure the external PHY in those cases, not 495*d14abf15SRobert Mustacchi all 4 values are needed. */ 496*d14abf15SRobert Mustacchi u16 xgxs_config_rx[4]; /* 0x198 */ 497*d14abf15SRobert Mustacchi u16 xgxs_config_tx[4]; /* 0x1A0 */ 498*d14abf15SRobert Mustacchi 499*d14abf15SRobert Mustacchi 500*d14abf15SRobert Mustacchi /* For storing FCOE mac on shared memory */ 501*d14abf15SRobert Mustacchi u32 fcoe_fip_mac_upper; 502*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 503*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 504*d14abf15SRobert Mustacchi u32 fcoe_fip_mac_lower; 505*d14abf15SRobert Mustacchi 506*d14abf15SRobert Mustacchi u32 fcoe_wwn_port_name_upper; 507*d14abf15SRobert Mustacchi u32 fcoe_wwn_port_name_lower; 508*d14abf15SRobert Mustacchi 509*d14abf15SRobert Mustacchi u32 fcoe_wwn_node_name_upper; 510*d14abf15SRobert Mustacchi u32 fcoe_wwn_node_name_lower; 511*d14abf15SRobert Mustacchi 512*d14abf15SRobert Mustacchi /* wwpn for npiv enabled */ 513*d14abf15SRobert Mustacchi u32 wwpn_for_npiv_config; /* 0x1C0 */ 514*d14abf15SRobert Mustacchi #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 515*d14abf15SRobert Mustacchi #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 516*d14abf15SRobert Mustacchi #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 517*d14abf15SRobert Mustacchi #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 518*d14abf15SRobert Mustacchi 519*d14abf15SRobert Mustacchi /* wwpn for npiv valid addresses */ 520*d14abf15SRobert Mustacchi u32 wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 521*d14abf15SRobert Mustacchi #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 522*d14abf15SRobert Mustacchi #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 523*d14abf15SRobert Mustacchi 524*d14abf15SRobert Mustacchi struct mac_addr wwpn_for_niv_macs[16]; 525*d14abf15SRobert Mustacchi 526*d14abf15SRobert Mustacchi /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 527*d14abf15SRobert Mustacchi u32 Reserved1[14]; 528*d14abf15SRobert Mustacchi 529*d14abf15SRobert Mustacchi u32 pf_allocation; /* 0x280 */ 530*d14abf15SRobert Mustacchi /* number of vfs per PF, if 0 - sriov disabled */ 531*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 532*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 533*d14abf15SRobert Mustacchi 534*d14abf15SRobert Mustacchi /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 535*d14abf15SRobert Mustacchi 84833 only */ 536*d14abf15SRobert Mustacchi u32 xgbt_phy_cfg; /* 0x284 */ 537*d14abf15SRobert Mustacchi #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 538*d14abf15SRobert Mustacchi #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 539*d14abf15SRobert Mustacchi 540*d14abf15SRobert Mustacchi u32 default_cfg; /* 0x288 */ 541*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 542*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 543*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 544*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 545*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 546*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 547*d14abf15SRobert Mustacchi 548*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 549*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 550*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 551*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 552*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 553*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 554*d14abf15SRobert Mustacchi 555*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 556*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 557*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 558*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 559*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 560*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 561*d14abf15SRobert Mustacchi 562*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 563*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 564*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 565*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 566*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 567*d14abf15SRobert Mustacchi #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 568*d14abf15SRobert Mustacchi 569*d14abf15SRobert Mustacchi /* When KR link is required to be set to force which is not 570*d14abf15SRobert Mustacchi KR-compliant, this parameter determine what is the trigger for it. 571*d14abf15SRobert Mustacchi When GPIO is selected, low input will force the speed. Currently 572*d14abf15SRobert Mustacchi default speed is 1G. In the future, it may be widen to select the 573*d14abf15SRobert Mustacchi forced speed in with another parameter. Note when force-1G is 574*d14abf15SRobert Mustacchi enabled, it override option 56: Link Speed option. */ 575*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 576*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 577*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 578*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 579*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 580*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 581*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 582*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 583*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 584*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 585*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 586*d14abf15SRobert Mustacchi #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 587*d14abf15SRobert Mustacchi /* Enable to determine with which GPIO to reset the external phy */ 588*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 589*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 590*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 591*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 592*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 593*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 594*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 595*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 596*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 597*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 598*d14abf15SRobert Mustacchi #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 599*d14abf15SRobert Mustacchi 600*d14abf15SRobert Mustacchi /* Enable BAM on KR */ 601*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 602*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 603*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 604*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 605*d14abf15SRobert Mustacchi 606*d14abf15SRobert Mustacchi /* Enable Common Mode Sense */ 607*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 608*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 609*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 610*d14abf15SRobert Mustacchi #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 611*d14abf15SRobert Mustacchi 612*d14abf15SRobert Mustacchi /* Determine the Serdes electrical interface */ 613*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 614*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 615*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 616*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 617*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 618*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 619*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 620*d14abf15SRobert Mustacchi #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 621*d14abf15SRobert Mustacchi 622*d14abf15SRobert Mustacchi /* SFP+ main TAP and post TAP volumes */ 623*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 624*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 625*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 626*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 627*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 628*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 629*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 630*d14abf15SRobert Mustacchi #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 631*d14abf15SRobert Mustacchi 632*d14abf15SRobert Mustacchi u32 speed_capability_mask2; /* 0x28C */ 633*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 634*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 635*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 636*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 637*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 638*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 639*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 640*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 641*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 642*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 643*d14abf15SRobert Mustacchi 644*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 645*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 646*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 647*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 648*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 649*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 650*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 651*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 652*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 653*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 654*d14abf15SRobert Mustacchi 655*d14abf15SRobert Mustacchi 656*d14abf15SRobert Mustacchi /* In the case where two media types (e.g. copper and fiber) are 657*d14abf15SRobert Mustacchi present and electrically active at the same time, PHY Selection 658*d14abf15SRobert Mustacchi will determine which of the two PHYs will be designated as the 659*d14abf15SRobert Mustacchi Active PHY and used for a connection to the network. */ 660*d14abf15SRobert Mustacchi u32 multi_phy_config; /* 0x290 */ 661*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 662*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 663*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 664*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 665*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 666*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 667*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 668*d14abf15SRobert Mustacchi 669*d14abf15SRobert Mustacchi /* When enabled, all second phy nvram parameters will be swapped 670*d14abf15SRobert Mustacchi with the first phy parameters */ 671*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 672*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 673*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 674*d14abf15SRobert Mustacchi #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 675*d14abf15SRobert Mustacchi 676*d14abf15SRobert Mustacchi 677*d14abf15SRobert Mustacchi /* Address of the second external phy */ 678*d14abf15SRobert Mustacchi u32 external_phy_config2; /* 0x294 */ 679*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 680*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 681*d14abf15SRobert Mustacchi 682*d14abf15SRobert Mustacchi /* The second XGXS external PHY type */ 683*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 684*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 685*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 686*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 687*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 688*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 689*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 690*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 691*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 692*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 693*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 694*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 695*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 696*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 697*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 698*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 699*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 700*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 701*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 702*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 703*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 704*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 705*d14abf15SRobert Mustacchi 706*d14abf15SRobert Mustacchi 707*d14abf15SRobert Mustacchi /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 708*d14abf15SRobert Mustacchi 8706, 8726 and 8727) not all 4 values are needed. */ 709*d14abf15SRobert Mustacchi u16 xgxs_config2_rx[4]; /* 0x296 */ 710*d14abf15SRobert Mustacchi u16 xgxs_config2_tx[4]; /* 0x2A0 */ 711*d14abf15SRobert Mustacchi 712*d14abf15SRobert Mustacchi u32 lane_config; 713*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 714*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 715*d14abf15SRobert Mustacchi /* AN and forced */ 716*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 717*d14abf15SRobert Mustacchi /* forced only */ 718*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 719*d14abf15SRobert Mustacchi /* forced only */ 720*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 721*d14abf15SRobert Mustacchi /* forced only */ 722*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 723*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 724*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 725*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 726*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 727*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 728*d14abf15SRobert Mustacchi #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 729*d14abf15SRobert Mustacchi 730*d14abf15SRobert Mustacchi /* Indicate whether to swap the external phy polarity */ 731*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 732*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 733*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 734*d14abf15SRobert Mustacchi 735*d14abf15SRobert Mustacchi 736*d14abf15SRobert Mustacchi u32 external_phy_config; 737*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 738*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 739*d14abf15SRobert Mustacchi 740*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 741*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 742*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 743*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 744*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 745*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 746*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 747*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 748*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 749*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 750*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 751*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 752*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 753*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 754*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 755*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 756*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 757*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 758*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 759*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 760*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 761*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 762*d14abf15SRobert Mustacchi #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 763*d14abf15SRobert Mustacchi 764*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 765*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 766*d14abf15SRobert Mustacchi 767*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 768*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 769*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 770*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 771*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 772*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 773*d14abf15SRobert Mustacchi 774*d14abf15SRobert Mustacchi u32 speed_capability_mask; 775*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 776*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 777*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 778*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 779*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 780*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 781*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 782*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 783*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 784*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 785*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 786*d14abf15SRobert Mustacchi 787*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 788*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 789*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 790*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 791*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 792*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 793*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 794*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 795*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 796*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 797*d14abf15SRobert Mustacchi #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 798*d14abf15SRobert Mustacchi 799*d14abf15SRobert Mustacchi /* A place to hold the original MAC address as a backup */ 800*d14abf15SRobert Mustacchi u32 backup_mac_upper; /* 0x2B4 */ 801*d14abf15SRobert Mustacchi u32 backup_mac_lower; /* 0x2B8 */ 802*d14abf15SRobert Mustacchi 803*d14abf15SRobert Mustacchi }; 804*d14abf15SRobert Mustacchi 805*d14abf15SRobert Mustacchi 806*d14abf15SRobert Mustacchi /**************************************************************************** 807*d14abf15SRobert Mustacchi * Shared Feature configuration * 808*d14abf15SRobert Mustacchi ****************************************************************************/ 809*d14abf15SRobert Mustacchi struct shared_feat_cfg { /* NVRAM Offset */ 810*d14abf15SRobert Mustacchi 811*d14abf15SRobert Mustacchi u32 config; /* 0x450 */ 812*d14abf15SRobert Mustacchi #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 813*d14abf15SRobert Mustacchi 814*d14abf15SRobert Mustacchi /* Use NVRAM values instead of HW default values */ 815*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 816*d14abf15SRobert Mustacchi 0x00000002 817*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 818*d14abf15SRobert Mustacchi 0x00000000 819*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 820*d14abf15SRobert Mustacchi 0x00000002 821*d14abf15SRobert Mustacchi 822*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 823*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 824*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 825*d14abf15SRobert Mustacchi 826*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 827*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 828*d14abf15SRobert Mustacchi 829*d14abf15SRobert Mustacchi /* Override the OTP back to single function mode. When using GPIO, 830*d14abf15SRobert Mustacchi high means only SF, 0 is according to CLP configuration */ 831*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 832*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 833*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 834*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 835*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 836*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 837*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 838*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500 839*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 840*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 841*d14abf15SRobert Mustacchi 842*d14abf15SRobert Mustacchi /* Act as if the FCoE license is invalid */ 843*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 844*d14abf15SRobert Mustacchi 845*d14abf15SRobert Mustacchi /* Force FLR capability to all ports */ 846*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 847*d14abf15SRobert Mustacchi 848*d14abf15SRobert Mustacchi /* Act as if the iSCSI license is invalid */ 849*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 850*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 851*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 852*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 853*d14abf15SRobert Mustacchi 854*d14abf15SRobert Mustacchi /* The interval in seconds between sending LLDP packets. Set to zero 855*d14abf15SRobert Mustacchi to disable the feature */ 856*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 857*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 858*d14abf15SRobert Mustacchi 859*d14abf15SRobert Mustacchi /* The assigned device type ID for LLDP usage */ 860*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 861*d14abf15SRobert Mustacchi #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 862*d14abf15SRobert Mustacchi 863*d14abf15SRobert Mustacchi }; 864*d14abf15SRobert Mustacchi 865*d14abf15SRobert Mustacchi 866*d14abf15SRobert Mustacchi /**************************************************************************** 867*d14abf15SRobert Mustacchi * Port Feature configuration * 868*d14abf15SRobert Mustacchi ****************************************************************************/ 869*d14abf15SRobert Mustacchi struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 870*d14abf15SRobert Mustacchi 871*d14abf15SRobert Mustacchi u32 config; 872*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 873*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 874*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 875*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 876*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 877*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 878*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 879*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 880*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 881*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 882*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 883*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 884*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 885*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 886*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 887*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 888*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 889*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 890*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 891*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 892*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 893*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 894*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 895*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 896*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 897*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 898*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 899*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 900*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 901*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 902*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 903*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 904*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 905*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 906*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 907*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 908*d14abf15SRobert Mustacchi 909*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 910*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 911*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 912*d14abf15SRobert Mustacchi 913*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 914*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 915*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 916*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 917*d14abf15SRobert Mustacchi 918*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 919*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 920*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 921*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 922*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 923*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 924*d14abf15SRobert Mustacchi 925*d14abf15SRobert Mustacchi #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 926*d14abf15SRobert Mustacchi #define PORT_FEATURE_EN_SIZE_SHIFT 24 927*d14abf15SRobert Mustacchi #define PORT_FEATURE_WOL_ENABLED 0x01000000 928*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_ENABLED 0x02000000 929*d14abf15SRobert Mustacchi #define PORT_FEATURE_MFW_ENABLED 0x04000000 930*d14abf15SRobert Mustacchi 931*d14abf15SRobert Mustacchi /* Advertise expansion ROM even if MBA is disabled */ 932*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 933*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 934*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 935*d14abf15SRobert Mustacchi 936*d14abf15SRobert Mustacchi /* Check the optic vendor via i2c against a list of approved modules 937*d14abf15SRobert Mustacchi in a separate nvram image */ 938*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 939*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 940*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 941*d14abf15SRobert Mustacchi 0x00000000 942*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 943*d14abf15SRobert Mustacchi 0x20000000 944*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 945*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 946*d14abf15SRobert Mustacchi 947*d14abf15SRobert Mustacchi u32 wol_config; 948*d14abf15SRobert Mustacchi /* Default is used when driver sets to "auto" mode */ 949*d14abf15SRobert Mustacchi #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 950*d14abf15SRobert Mustacchi 951*d14abf15SRobert Mustacchi u32 mba_config; 952*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 953*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 954*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 955*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 956*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 957*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 958*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 959*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 960*d14abf15SRobert Mustacchi 961*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 962*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 963*d14abf15SRobert Mustacchi 964*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 965*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 966*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 967*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 968*d14abf15SRobert Mustacchi 969*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 970*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 971*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 972*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 973*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 974*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 975*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 976*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 977*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 978*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 979*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 980*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 981*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 982*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 983*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 984*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 985*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 986*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 987*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 988*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 989*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 990*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 991*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 992*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 993*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 994*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 995*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 996*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 997*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 998*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 999*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1000*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1001*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1002*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1003*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1004*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1005*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1006*d14abf15SRobert Mustacchi 1007*d14abf15SRobert Mustacchi u32 Reserved0; /* 0x460 */ 1008*d14abf15SRobert Mustacchi 1009*d14abf15SRobert Mustacchi u32 mba_vlan_cfg; 1010*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1011*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1012*d14abf15SRobert Mustacchi #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1013*d14abf15SRobert Mustacchi #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1014*d14abf15SRobert Mustacchi #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1015*d14abf15SRobert Mustacchi #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1016*d14abf15SRobert Mustacchi 1017*d14abf15SRobert Mustacchi u32 Reserved1; 1018*d14abf15SRobert Mustacchi u32 smbus_config; 1019*d14abf15SRobert Mustacchi #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1020*d14abf15SRobert Mustacchi #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1021*d14abf15SRobert Mustacchi 1022*d14abf15SRobert Mustacchi u32 vf_config; 1023*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1024*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1025*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1026*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1027*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1028*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1029*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1030*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1031*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1032*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1033*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1034*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1035*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1036*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1037*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1038*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1039*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1040*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1041*d14abf15SRobert Mustacchi 1042*d14abf15SRobert Mustacchi u32 link_config; /* Used as HW defaults for the driver */ 1043*d14abf15SRobert Mustacchi 1044*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1045*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1046*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1047*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1048*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1049*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1050*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1051*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1052*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1053*d14abf15SRobert Mustacchi #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1054*d14abf15SRobert Mustacchi 1055*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1056*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1057*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1058*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1059*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1060*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1061*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1062*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1063*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1064*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1065*d14abf15SRobert Mustacchi #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1066*d14abf15SRobert Mustacchi 1067*d14abf15SRobert Mustacchi #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1068*d14abf15SRobert Mustacchi #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1069*d14abf15SRobert Mustacchi /* (forced) low speed switch (< 10G) */ 1070*d14abf15SRobert Mustacchi #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1071*d14abf15SRobert Mustacchi /* (forced) high speed switch (>= 10G) */ 1072*d14abf15SRobert Mustacchi #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1073*d14abf15SRobert Mustacchi #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1074*d14abf15SRobert Mustacchi #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1075*d14abf15SRobert Mustacchi 1076*d14abf15SRobert Mustacchi 1077*d14abf15SRobert Mustacchi 1078*d14abf15SRobert Mustacchi 1079*d14abf15SRobert Mustacchi /* The default for MCP link configuration, 1080*d14abf15SRobert Mustacchi uses the same defines as link_config */ 1081*d14abf15SRobert Mustacchi u32 mfw_wol_link_cfg; 1082*d14abf15SRobert Mustacchi 1083*d14abf15SRobert Mustacchi /* The default for the driver of the second external phy, 1084*d14abf15SRobert Mustacchi uses the same defines as link_config */ 1085*d14abf15SRobert Mustacchi u32 link_config2; /* 0x47C */ 1086*d14abf15SRobert Mustacchi 1087*d14abf15SRobert Mustacchi /* The default for MCP of the second external phy, 1088*d14abf15SRobert Mustacchi uses the same defines as link_config */ 1089*d14abf15SRobert Mustacchi u32 mfw_wol_link_cfg2; /* 0x480 */ 1090*d14abf15SRobert Mustacchi 1091*d14abf15SRobert Mustacchi 1092*d14abf15SRobert Mustacchi 1093*d14abf15SRobert Mustacchi 1094*d14abf15SRobert Mustacchi /* EEE power saving mode */ 1095*d14abf15SRobert Mustacchi u32 eee_power_mode; /* 0x484 */ 1096*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1097*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1098*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1099*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1100*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1101*d14abf15SRobert Mustacchi #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1102*d14abf15SRobert Mustacchi 1103*d14abf15SRobert Mustacchi 1104*d14abf15SRobert Mustacchi u32 Reserved2[16]; /* 0x488 */ 1105*d14abf15SRobert Mustacchi }; 1106*d14abf15SRobert Mustacchi 1107*d14abf15SRobert Mustacchi /**************************************************************************** 1108*d14abf15SRobert Mustacchi * Device Information * 1109*d14abf15SRobert Mustacchi ****************************************************************************/ 1110*d14abf15SRobert Mustacchi struct shm_dev_info { /* size */ 1111*d14abf15SRobert Mustacchi 1112*d14abf15SRobert Mustacchi u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1113*d14abf15SRobert Mustacchi 1114*d14abf15SRobert Mustacchi struct shared_hw_cfg shared_hw_config; /* 40 */ 1115*d14abf15SRobert Mustacchi 1116*d14abf15SRobert Mustacchi struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1117*d14abf15SRobert Mustacchi 1118*d14abf15SRobert Mustacchi struct shared_feat_cfg shared_feature_config; /* 4 */ 1119*d14abf15SRobert Mustacchi 1120*d14abf15SRobert Mustacchi struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1121*d14abf15SRobert Mustacchi 1122*d14abf15SRobert Mustacchi }; 1123*d14abf15SRobert Mustacchi 1124*d14abf15SRobert Mustacchi struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1125*d14abf15SRobert Mustacchi 1126*d14abf15SRobert Mustacchi /* Threshold in celcius to start using the fan */ 1127*d14abf15SRobert Mustacchi u32 temperature_monitor1; /* 0x4000 */ 1128*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1129*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1130*d14abf15SRobert Mustacchi 1131*d14abf15SRobert Mustacchi /* Threshold in celcius to shut down the board */ 1132*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1133*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1134*d14abf15SRobert Mustacchi 1135*d14abf15SRobert Mustacchi /* EPIO of fan temperature status */ 1136*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1137*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1138*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1139*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1140*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1141*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1142*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1143*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1144*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1145*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1146*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1147*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1148*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1149*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1150*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1151*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1152*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1153*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1154*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1155*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1156*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1157*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1158*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1159*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1160*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1161*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1162*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1163*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1164*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1165*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1166*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1167*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1168*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1169*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1170*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1171*d14abf15SRobert Mustacchi 1172*d14abf15SRobert Mustacchi /* EPIO of shut down temperature status */ 1173*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1174*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1175*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1176*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1177*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1178*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1179*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1180*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1181*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1182*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1183*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1184*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1185*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1186*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1187*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1188*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1189*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1190*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1191*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1192*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1193*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1194*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1195*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1196*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1197*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1198*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1199*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1200*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1201*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1202*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1203*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1204*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1205*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1206*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1207*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1208*d14abf15SRobert Mustacchi 1209*d14abf15SRobert Mustacchi 1210*d14abf15SRobert Mustacchi /* EPIO of shut down temperature status */ 1211*d14abf15SRobert Mustacchi u32 temperature_monitor2; /* 0x4004 */ 1212*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1213*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1214*d14abf15SRobert Mustacchi 1215*d14abf15SRobert Mustacchi 1216*d14abf15SRobert Mustacchi /* MFW flavor to be used */ 1217*d14abf15SRobert Mustacchi u32 mfw_cfg; /* 0x4008 */ 1218*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1219*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1220*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1221*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1222*d14abf15SRobert Mustacchi 1223*d14abf15SRobert Mustacchi /* Should NIC data query remain enabled upon last drv unload */ 1224*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1225*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1226*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1227*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1228*d14abf15SRobert Mustacchi 1229*d14abf15SRobert Mustacchi /* Hide DCBX feature in CCM/BACS menus */ 1230*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1231*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1232*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1233*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1234*d14abf15SRobert Mustacchi 1235*d14abf15SRobert Mustacchi u32 smbus_config; /* 0x400C */ 1236*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1237*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1238*d14abf15SRobert Mustacchi 1239*d14abf15SRobert Mustacchi /* Switching regulator loop gain */ 1240*d14abf15SRobert Mustacchi u32 board_cfg; /* 0x4010 */ 1241*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1242*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1243*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1244*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1245*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1246*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1247*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1248*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1249*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1250*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1251*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1252*d14abf15SRobert Mustacchi 1253*d14abf15SRobert Mustacchi /* whether shadow swim feature is supported */ 1254*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1255*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1256*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1257*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1258*d14abf15SRobert Mustacchi 1259*d14abf15SRobert Mustacchi /* whether to show/hide SRIOV menu in CCM */ 1260*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1261*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1262*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1263*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1264*d14abf15SRobert Mustacchi 1265*d14abf15SRobert Mustacchi /* Overide PCIE revision ID when enabled the, 1266*d14abf15SRobert Mustacchi revision ID will set to B1=='0x11' */ 1267*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1268*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1269*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1270*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1271*d14abf15SRobert Mustacchi 1272*d14abf15SRobert Mustacchi /* Bypass slicer offset tuning */ 1273*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800 1274*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11 1275*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000 1276*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800 1277*d14abf15SRobert Mustacchi /* Control Revision ID */ 1278*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000 1279*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12 1280*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000 1281*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000 1282*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000 1283*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000 1284*d14abf15SRobert Mustacchi /* Threshold in celcius for max continuous operation */ 1285*d14abf15SRobert Mustacchi u32 temperature_report; /* 0x4014 */ 1286*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1287*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1288*d14abf15SRobert Mustacchi 1289*d14abf15SRobert Mustacchi /* Threshold in celcius for sensor caution */ 1290*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1291*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1292*d14abf15SRobert Mustacchi 1293*d14abf15SRobert Mustacchi /* wwn node prefix to be used (unless value is 0) */ 1294*d14abf15SRobert Mustacchi u32 wwn_prefix; /* 0x4018 */ 1295*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1296*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1297*d14abf15SRobert Mustacchi 1298*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1299*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1300*d14abf15SRobert Mustacchi 1301*d14abf15SRobert Mustacchi /* wwn port prefix to be used (unless value is 0) */ 1302*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1303*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1304*d14abf15SRobert Mustacchi 1305*d14abf15SRobert Mustacchi /* wwn port prefix to be used (unless value is 0) */ 1306*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1307*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1308*d14abf15SRobert Mustacchi 1309*d14abf15SRobert Mustacchi /* General debug nvm cfg */ 1310*d14abf15SRobert Mustacchi u32 dbg_cfg_flags; /* 0x401C */ 1311*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1312*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1313*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1314*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1315*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1316*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1317*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1318*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1319*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1320*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1321*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1322*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1323*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1324*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1325*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1326*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1327*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1328*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1329*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1330*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1331*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1332*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1333*d14abf15SRobert Mustacchi 1334*d14abf15SRobert Mustacchi /* Debug signet rx threshold */ 1335*d14abf15SRobert Mustacchi u32 dbg_rx_sigdet_threshold; /* 0x4020 */ 1336*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1337*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1338*d14abf15SRobert Mustacchi 1339*d14abf15SRobert Mustacchi /* Enable IFFE feature */ 1340*d14abf15SRobert Mustacchi u32 iffe_features; /* 0x4024 */ 1341*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1342*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1343*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1344*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1345*d14abf15SRobert Mustacchi 1346*d14abf15SRobert Mustacchi /* Allowable port enablement (bitmask for ports 3-1) */ 1347*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1348*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1349*d14abf15SRobert Mustacchi 1350*d14abf15SRobert Mustacchi /* Allow iSCSI offload override */ 1351*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1352*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1353*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1354*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1355*d14abf15SRobert Mustacchi 1356*d14abf15SRobert Mustacchi /* Allow FCoE offload override */ 1357*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1358*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1359*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1360*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1361*d14abf15SRobert Mustacchi 1362*d14abf15SRobert Mustacchi /* Tie to adaptor */ 1363*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1364*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1365*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1366*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1367*d14abf15SRobert Mustacchi 1368*d14abf15SRobert Mustacchi /* Currently enabled port(s) (bitmask for ports 3-1) */ 1369*d14abf15SRobert Mustacchi u32 current_iffe_mask; /* 0x4028 */ 1370*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1371*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1372*d14abf15SRobert Mustacchi 1373*d14abf15SRobert Mustacchi /* Current iSCSI offload */ 1374*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1375*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1376*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1377*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1378*d14abf15SRobert Mustacchi 1379*d14abf15SRobert Mustacchi /* Current FCoE offload */ 1380*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1381*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1382*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1383*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1384*d14abf15SRobert Mustacchi 1385*d14abf15SRobert Mustacchi /* FW set this pin to "0" (assert) these signal if either of its MAC 1386*d14abf15SRobert Mustacchi * or PHY specific threshold values is exceeded. 1387*d14abf15SRobert Mustacchi * Values are standard GPIO/EPIO pins. 1388*d14abf15SRobert Mustacchi */ 1389*d14abf15SRobert Mustacchi u32 threshold_pin; /* 0x402C */ 1390*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1391*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1392*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1393*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1394*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1395*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1396*d14abf15SRobert Mustacchi 1397*d14abf15SRobert Mustacchi /* MAC die temperature threshold in Celsius. */ 1398*d14abf15SRobert Mustacchi u32 mac_threshold_val; /* 0x4030 */ 1399*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1400*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1401*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1402*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1403*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1404*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1405*d14abf15SRobert Mustacchi 1406*d14abf15SRobert Mustacchi /* PHY die temperature threshold in Celsius. */ 1407*d14abf15SRobert Mustacchi u32 phy_threshold_val; /* 0x4034 */ 1408*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1409*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1410*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1411*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1412*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1413*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1414*d14abf15SRobert Mustacchi 1415*d14abf15SRobert Mustacchi /* External pins to communicate with host. 1416*d14abf15SRobert Mustacchi * Values are standard GPIO/EPIO pins. 1417*d14abf15SRobert Mustacchi */ 1418*d14abf15SRobert Mustacchi u32 host_pin; /* 0x4038 */ 1419*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1420*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1421*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1422*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1423*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1424*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1425*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1426*d14abf15SRobert Mustacchi #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1427*d14abf15SRobert Mustacchi }; 1428*d14abf15SRobert Mustacchi 1429*d14abf15SRobert Mustacchi #endif 1430