1
2#define MDIO_REG_BANK_CL73_IEEEB0			0x0
3	#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL		0x0
4		#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN	0x0200
5		#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN		0x1000
6		#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST	0x8000
7
8#define MDIO_REG_BANK_CL73_IEEEB1			0x10
9	#define MDIO_CL73_IEEEB1_AN_ADV1			0x00
10		#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE			0x0400
11		#define	MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 		0x0800
12		#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH		0x0C00
13		#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK		0x0C00
14	#define MDIO_CL73_IEEEB1_AN_ADV2				0x01
15		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M		0x0000
16		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX		0x0020
17		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4		0x0040
18		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR		0x0080
19	#define	MDIO_CL73_IEEEB1_AN_LP_ADV1			0x03
20		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE		0x0400
21		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 		0x0800
22		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH		0x0C00
23		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK		0x0C00
24	#define	MDIO_CL73_IEEEB1_AN_LP_ADV2			0x04
25
26#define	MDIO_REG_BANK_RX0				0x80b0
27	#define	MDIO_RX0_RX_STATUS				0x10
28		#define	MDIO_RX0_RX_STATUS_SIGDET			0x8000
29		#define	MDIO_RX0_RX_STATUS_RX_SEQ_DONE			0x1000
30	#define	MDIO_RX0_RX_EQ_BOOST				0x1c
31		#define	MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
32		#define	MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL		0x10
33
34#define	MDIO_REG_BANK_RX1				0x80c0
35	#define	MDIO_RX1_RX_EQ_BOOST				0x1c
36		#define	MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
37		#define	MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL		0x10
38
39#define	MDIO_REG_BANK_RX2				0x80d0
40	#define	MDIO_RX2_RX_EQ_BOOST				0x1c
41		#define	MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
42		#define	MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL		0x10
43
44#define	MDIO_REG_BANK_RX3				0x80e0
45	#define	MDIO_RX3_RX_EQ_BOOST				0x1c
46		#define	MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
47		#define	MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL		0x10
48
49#define	MDIO_REG_BANK_RX_ALL				0x80f0
50	#define	MDIO_RX_ALL_RX_EQ_BOOST				0x1c
51		#define	MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
52		#define	MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL	0x10
53
54#define	MDIO_REG_BANK_TX0				0x8060
55	#define	MDIO_TX0_TX_DRIVER				0x17
56		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
57		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
58		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
59		#define	MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
60		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
61		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
62		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
63		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
64		#define	MDIO_TX0_TX_DRIVER_ICBUF1T			1
65
66#define	MDIO_REG_BANK_TX1				0x8070
67	#define	MDIO_TX1_TX_DRIVER				0x17
68		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
69		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
70		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
71		#define	MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
72		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
73		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
74		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
75		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
76		#define	MDIO_TX0_TX_DRIVER_ICBUF1T			1
77
78#define	MDIO_REG_BANK_TX2				0x8080
79	#define	MDIO_TX2_TX_DRIVER				0x17
80		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
81		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
82		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
83		#define	MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
84		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
85		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
86		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
87		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
88		#define	MDIO_TX0_TX_DRIVER_ICBUF1T			1
89
90#define	MDIO_REG_BANK_TX3				0x8090
91	#define	MDIO_TX3_TX_DRIVER				0x17
92		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
93		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
94		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
95		#define	MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
96		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
97		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
98		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
99		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
100		#define	MDIO_TX0_TX_DRIVER_ICBUF1T			1
101
102#define	MDIO_REG_BANK_XGXS_BLOCK0			0x8000
103	#define	MDIO_BLOCK0_XGXS_CONTROL			0x10
104
105#define	MDIO_REG_BANK_XGXS_BLOCK1			0x8010
106	#define	MDIO_BLOCK1_LANE_CTRL0				0x15
107	#define	MDIO_BLOCK1_LANE_CTRL1				0x16
108	#define	MDIO_BLOCK1_LANE_CTRL2				0x17
109	#define	MDIO_BLOCK1_LANE_PRBS				0x19
110
111#define	MDIO_REG_BANK_XGXS_BLOCK2			0x8100
112	#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP			0x10
113		#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE		0x8000
114		#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE	0x4000
115		#define	MDIO_XGXS_BLOCK2_TX_LN_SWAP		0x11
116		#define	MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE		0x8000
117		#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G	0x14
118		#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS	0x0001
119		#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS	0x0010
120		#define	MDIO_XGXS_BLOCK2_TEST_MODE_LANE		0x15
121
122#define	MDIO_REG_BANK_GP_STATUS				0x8120
123#define	MDIO_GP_STATUS_TOP_AN_STATUS1				0x1B
124	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE	0x0001
125	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE	0x0002
126	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS		0x0004
127	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS		0x0008
128	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE	0x0010
129	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE	0x0020
130	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE	0x0040
131	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE	0x0080
132	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK		0x3f00
133	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M		0x0000
134	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M		0x0100
135	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G		0x0200
136	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G		0x0300
137	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G		0x0400
138	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G		0x0500
139	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG	0x0600
140	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4	0x0700
141	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG	0x0800
142	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G	0x0900
143	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G		0x0A00
144	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G		0x0B00
145	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G		0x0C00
146	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX	0x0D00
147	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4	0x0E00
148	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR	0x0F00
149	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI	0x1B00
150	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS	0x1E00
151	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI	0x1F00
152	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2	0x3900
153
154
155#define	MDIO_REG_BANK_10G_PARALLEL_DETECT		0x8130
156#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS		0x10
157#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK		0x8000
158#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL		0x11
159#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN	0x1
160#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK		0x13
161#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT		(0xb71<<1)
162
163#define	MDIO_REG_BANK_SERDES_DIGITAL			0x8300
164#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1			0x10
165#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE			0x0001
166#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF			0x0002
167#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN		0x0004
168#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT	0x0008
169#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET			0x0010
170#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE			0x0020
171#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2			0x11
172#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN			0x0001
173#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR			0x0040
174#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1			0x14
175#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII			0x0001
176#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK			0x0002
177#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX			0x0004
178#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK			0x0018
179#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT			3
180#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G			0x0018
181#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G			0x0010
182#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M			0x0008
183#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M			0x0000
184#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS2			0x15
185#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED			0x0002
186#define	MDIO_SERDES_DIGITAL_MISC1				0x18
187#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK			0xE000
188#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M			0x0000
189#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M			0x2000
190#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M			0x4000
191#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M			0x6000
192#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M			0x8000
193#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL			0x0010
194#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK			0x000f
195#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G			0x0000
196#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G			0x0001
197#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G			0x0002
198#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG			0x0003
199#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4			0x0004
200#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G			0x0005
201#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G			0x0006
202#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G			0x0007
203#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G			0x0008
204#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G			0x0009
205
206#define	MDIO_REG_BANK_OVER_1G				0x8320
207#define	MDIO_OVER_1G_DIGCTL_3_4					0x14
208#define	MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK				0xffe0
209#define	MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT				5
210#define	MDIO_OVER_1G_UP1					0x19
211#define	MDIO_OVER_1G_UP1_2_5G						0x0001
212#define	MDIO_OVER_1G_UP1_5G						0x0002
213#define	MDIO_OVER_1G_UP1_6G						0x0004
214#define	MDIO_OVER_1G_UP1_10G						0x0010
215#define	MDIO_OVER_1G_UP1_10GH						0x0008
216#define	MDIO_OVER_1G_UP1_12G						0x0020
217#define	MDIO_OVER_1G_UP1_12_5G						0x0040
218#define	MDIO_OVER_1G_UP1_13G						0x0080
219#define	MDIO_OVER_1G_UP1_15G						0x0100
220#define	MDIO_OVER_1G_UP1_16G						0x0200
221#define	MDIO_OVER_1G_UP2					0x1A
222#define	MDIO_OVER_1G_UP2_IPREDRIVER_MASK				0x0007
223#define	MDIO_OVER_1G_UP2_IDRIVER_MASK					0x0038
224#define	MDIO_OVER_1G_UP2_PREEMPHASIS_MASK				0x03C0
225#define	MDIO_OVER_1G_UP3					0x1B
226#define	MDIO_OVER_1G_UP3_HIGIG2						0x0001
227#define	MDIO_OVER_1G_LP_UP1					0x1C
228#define	MDIO_OVER_1G_LP_UP2					0x1D
229#define	MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK				0x03ff
230#define	MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK				0x0780
231#define	MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT				7
232#define	MDIO_OVER_1G_LP_UP3						0x1E
233
234#define	MDIO_REG_BANK_REMOTE_PHY			0x8330
235#define	MDIO_REMOTE_PHY_MISC_RX_STATUS				0x10
236#define	MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG	0x0010
237#define	MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG	0x0600
238
239#define	MDIO_REG_BANK_BAM_NEXT_PAGE			0x8350
240#define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL			0x10
241#define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE			0x0001
242#define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN			0x0002
243
244#define	MDIO_REG_BANK_CL73_USERB0		0x8370
245#define	MDIO_CL73_USERB0_CL73_UCTRL				0x10
246#define	MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL			0x0002
247#define	MDIO_CL73_USERB0_CL73_USTAT1				0x11
248#define	MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK			0x0100
249#define	MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37		0x0400
250#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1				0x12
251#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN				0x8000
252#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN		0x4000
253#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN		0x2000
254#define	MDIO_CL73_USERB0_CL73_BAM_CTRL3				0x14
255#define	MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR			0x0001
256
257#define	MDIO_REG_BANK_AER_BLOCK			0xFFD0
258#define	MDIO_AER_BLOCK_AER_REG					0x1E
259
260#define	MDIO_REG_BANK_COMBO_IEEE0		0xFFE0
261#define	MDIO_COMBO_IEEE0_MII_CONTROL				0x10
262#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK			0x2040
263#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10			0x0000
264#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100			0x2000
265#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000			0x0040
266#define	MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX				0x0100
267#define	MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN				0x0200
268#define	MDIO_COMBO_IEEO_MII_CONTROL_AN_EN				0x1000
269#define	MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK				0x4000
270#define	MDIO_COMBO_IEEO_MII_CONTROL_RESET				0x8000
271#define	MDIO_COMBO_IEEE0_MII_STATUS				0x11
272#define	MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS				0x0004
273#define	MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE			0x0020
274#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV				0x14
275#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX			0x0020
276#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX			0x0040
277#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK			0x0180
278#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE			0x0000
279#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC			0x0080
280#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC			0x0100
281#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH			0x0180
282#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE				0x8000
283#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1		0x15
284#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE	0x8000
285#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK		0x4000
286#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK	0x0180
287#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE	0x0000
288#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH	0x0180
289#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP	0x0040
290#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP	0x0020
291/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
292bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
293Theotherbitsarereservedandshouldbezero*/
294#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE	0x0001
295
296
297#define	MDIO_PMA_DEVAD			0x1
298/*ieee*/
299#define	MDIO_PMA_REG_CTRL		0x0
300#define	MDIO_PMA_REG_STATUS		0x1
301#define	MDIO_PMA_REG_10G_CTRL2		0x7
302#define MDIO_PMA_REG_TX_DISABLE		0x0009
303#define	MDIO_PMA_REG_RX_SD		0xa
304/*bcm*/
305#define	MDIO_PMA_REG_BCM_CTRL		0x0096
306#define MDIO_PMA_REG_FEC_CTRL		0x00ab
307#define	MDIO_PMA_LASI_RXCTRL		0x9000
308#define	MDIO_PMA_LASI_TXCTRL		0x9001
309#define	MDIO_PMA_LASI_CTRL		0x9002
310#define	MDIO_PMA_LASI_RXSTAT		0x9003
311#define	MDIO_PMA_LASI_TXSTAT		0x9004
312#define	MDIO_PMA_LASI_STAT		0x9005
313#define	MDIO_PMA_REG_PHY_IDENTIFIER	0xc800
314#define	MDIO_PMA_REG_DIGITAL_CTRL	0xc808
315#define	MDIO_PMA_REG_DIGITAL_STATUS	0xc809
316#define	MDIO_PMA_REG_TX_POWER_DOWN	0xca02
317#define	MDIO_PMA_REG_CMU_PLL_BYPASS	0xca09
318#define	MDIO_PMA_REG_MISC_CTRL		0xca0a
319#define	MDIO_PMA_REG_GEN_CTRL		0xca10
320	#define	MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP	0x0188
321	#define	MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET		0x018a
322#define	MDIO_PMA_REG_M8051_MSGIN_REG	0xca12
323#define	MDIO_PMA_REG_M8051_MSGOUT_REG	0xca13
324#define	MDIO_PMA_REG_ROM_VER1		0xca19
325#define	MDIO_PMA_REG_ROM_VER2		0xca1a
326#define	MDIO_PMA_REG_EDC_FFE_MAIN	0xca1b
327#define	MDIO_PMA_REG_PLL_BANDWIDTH	0xca1d
328#define MDIO_PMA_REG_PLL_CTRL 		0xca1e
329#define MDIO_PMA_REG_MISC_CTRL0 	0xca23
330#define MDIO_PMA_REG_LRM_MODE	 	0xca3f
331#define	MDIO_PMA_REG_CDR_BANDWIDTH 	0xca46
332#define	MDIO_PMA_REG_MISC_CTRL1		0xca85
333
334#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL		0x8000
335	#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 	0x000c
336		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 		0x0000
337		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 	0x0004
338		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 	0x0008
339		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 	0x000c
340#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 	0x8002
341#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 	0x8003
342#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF	0xc820
343	#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
344#define MDIO_PMA_REG_8726_TX_CTRL1		0xca01
345#define MDIO_PMA_REG_8726_TX_CTRL2		0xca05
346
347#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR	0x8005
348#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF	0x8007
349	#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
350#define MDIO_PMA_REG_8727_MISC_CTRL		0x8309
351#define MDIO_PMA_REG_8727_TX_CTRL1		0xca02
352#define MDIO_PMA_REG_8727_TX_CTRL2		0xca05
353#define MDIO_PMA_REG_8727_PCS_OPT_CTRL		0xc808
354#define MDIO_PMA_REG_8727_GPIO_CTRL		0xc80e
355#define MDIO_PMA_REG_8727_PCS_GP		0xc842
356#define MDIO_PMA_REG_8727_OPT_CFG_REG		0xc8e4
357
358#define MDIO_AN_REG_8727_MISC_CTRL		0x8309
359#define	MDIO_PMA_REG_8073_CHIP_REV			0xc801
360#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS		0xc820
361#define MDIO_PMA_REG_8073_XAUI_WA 			0xc841
362#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 		0xcd08
363
364#define MDIO_PMA_REG_7101_RESET		0xc000
365#define	MDIO_PMA_REG_7107_LED_CNTL	0xc007
366#define	MDIO_PMA_REG_7107_LINK_LED_CNTL	0xc009
367#define	MDIO_PMA_REG_7101_VER1		0xc026
368#define	MDIO_PMA_REG_7101_VER2		0xc027
369
370#define MDIO_PMA_REG_8481_PMD_SIGNAL	0xa811
371#define MDIO_PMA_REG_8481_LED1_MASK	0xa82c
372#define MDIO_PMA_REG_8481_LED2_MASK	0xa82f
373#define MDIO_PMA_REG_8481_LED3_MASK	0xa832
374#define MDIO_PMA_REG_8481_LED3_BLINK	0xa834
375#define MDIO_PMA_REG_8481_LED5_MASK	                0xa838
376#define MDIO_PMA_REG_8481_SIGNAL_MASK	0xa835
377#define MDIO_PMA_REG_8481_LINK_SIGNAL	0xa83b
378#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK	0x800
379#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT	11
380
381
382
383#define	MDIO_WIS_DEVAD			0x2
384/*bcm*/
385#define	MDIO_WIS_REG_LASI_CNTL		0x9002
386#define	MDIO_WIS_REG_LASI_STATUS	0x9005
387
388#define	MDIO_PCS_DEVAD			0x3
389#define	MDIO_PCS_REG_STATUS		0x0020
390#define MDIO_PCS_REG_LASI_STATUS	0x9005
391#define MDIO_PCS_REG_7101_DSP_ACCESS	0xD000
392#define MDIO_PCS_REG_7101_SPI_MUX 	0xD008
393#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
394	#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
395#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
396	#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
397	#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD   (0xC7)
398	#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
399#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
400
401
402
403#define	MDIO_XS_DEVAD			0x4
404#define	MDIO_XS_REG_STATUS		0x0001
405#define MDIO_XS_PLL_SEQUENCER 		0x8000
406#define	MDIO_XS_SFX7101_XGXS_TEST1	0xc00a
407
408#define MDIO_XS_8706_REG_BANK_RX0	0x80bc
409#define MDIO_XS_8706_REG_BANK_RX1	0x80cc
410#define MDIO_XS_8706_REG_BANK_RX2	0x80dc
411#define MDIO_XS_8706_REG_BANK_RX3	0x80ec
412#define MDIO_XS_8706_REG_BANK_RXA	0x80fc
413
414#define MDIO_XS_REG_8073_RX_CTRL_PCIE	0x80FA
415
416#define	MDIO_AN_DEVAD			0x7
417/*ieee*/
418#define	MDIO_AN_REG_CTRL		0x0000
419#define	MDIO_AN_REG_STATUS		0x0001
420	#define	MDIO_AN_REG_STATUS_AN_COMPLETE		0x0020
421#define	MDIO_AN_REG_ADV_PAUSE		0x0010
422	#define	MDIO_AN_REG_ADV_PAUSE_PAUSE		0x0400
423	#define	MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC	0x0800
424	#define	MDIO_AN_REG_ADV_PAUSE_BOTH		0x0C00
425	#define	MDIO_AN_REG_ADV_PAUSE_MASK		0x0C00
426#define	MDIO_AN_REG_ADV			0x0011
427#define MDIO_AN_REG_ADV2		0x0012
428#define	MDIO_AN_REG_LP_AUTO_NEG		0x0013
429#define	MDIO_AN_REG_LP_AUTO_NEG2	0x0014
430#define	MDIO_AN_REG_MASTER_STATUS	0x0021
431#define	MDIO_AN_REG_EEE_ADV		0x003c
432#define	MDIO_AN_REG_LP_EEE_ADV		0x003d
433/*bcm*/
434#define	MDIO_AN_REG_LINK_STATUS		0x8304
435#define	MDIO_AN_REG_CL37_CL73		0x8370
436#define	MDIO_AN_REG_CL37_AN		0xffe0
437#define	MDIO_AN_REG_CL37_FC_LD		0xffe4
438#define 	MDIO_AN_REG_CL37_FC_LP		0xffe5
439#define 	MDIO_AN_REG_1000T_STATUS	0xffea
440
441#define MDIO_AN_REG_8073_2_5G		0x8329
442#define MDIO_AN_REG_8073_BAM		0x8350
443
444#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL	0x0020
445#define MDIO_AN_REG_8481_LEGACY_MII_CTRL	0xffe0
446	#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G	0x40
447#define MDIO_AN_REG_8481_LEGACY_MII_STATUS	0xffe1
448#define MDIO_AN_REG_8481_LEGACY_AN_ADV		0xffe4
449#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION	0xffe6
450#define MDIO_AN_REG_8481_1000T_CTRL		0xffe9
451#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL	0xfff0
452	#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF	0x0008
453#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW	0xfff5
454#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS	0xfff7
455#define MDIO_AN_REG_8481_AUX_CTRL		0xfff8
456#define MDIO_AN_REG_8481_LEGACY_SHADOW		0xfffc
457
458/* BCM84823 only */
459#define	MDIO_CTL_DEVAD			0x1e
460#define MDIO_CTL_REG_84823_MEDIA		0x401a
461	#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK		0x0018
462	/* These pins configure the BCM84823 interface to MAC after reset. */
463		#define MDIO_CTL_REG_84823_CTRL_MAC_XFI			0x0008
464		#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M		0x0010
465	/* These pins configure the BCM84823 interface to Line after reset. */
466	#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK		0x0060
467		#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L		0x0020
468		#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI		0x0040
469	/* When this pin is active high during reset, 10GBASE-T core is power
470	 * down, When it is active low the 10GBASE-T is power up
471	 */
472	#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN	0x0080
473	#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK		0x0100
474		#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER	0x0000
475		#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER		0x0100
476	#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G			0x1000
477#define MDIO_CTL_REG_84823_USER_CTRL_REG			0x4005
478	#define MDIO_CTL_REG_84823_USER_CTRL_CMS			0x0080
479#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH		0xa82b
480	#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ	0x2f
481#define MDIO_PMA_REG_84823_CTL_LED_CTL_1			0xa8e3
482#define MDIO_PMA_REG_84833_CTL_LED_CTL_1			0xa8ec
483	#define MDIO_PMA_REG_84823_LED3_STRETCH_EN			0x0080
484
485/* BCM84833 only */
486#define MDIO_84833_TOP_CFG_FW_REV			0x400f
487	#define MDIO_84833_TOP_CFG_FW_EEE		0x10b1
488	#define MDIO_84833_TOP_CFG_FW_NO_EEE		0x1f81
489#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 		0x401a
490	#define MDIO_84833_SUPER_ISOLATE 		0x8000
491/* These are mailbox register set used by 84833. */
492#define MDIO_84833_TOP_CFG_SCRATCH_REG0			0x4005
493#define MDIO_84833_TOP_CFG_SCRATCH_REG1 		0x4006
494#define MDIO_84833_TOP_CFG_SCRATCH_REG2			0x4007
495#define MDIO_84833_TOP_CFG_SCRATCH_REG3			0x4008
496#define MDIO_84833_TOP_CFG_SCRATCH_REG4			0x4009
497#define MDIO_84833_TOP_CFG_SCRATCH_REG26		0x4037
498#define MDIO_84833_TOP_CFG_SCRATCH_REG27		0x4038
499#define MDIO_84833_TOP_CFG_SCRATCH_REG28		0x4039
500#define MDIO_84833_TOP_CFG_SCRATCH_REG29		0x403a
501#define MDIO_84833_TOP_CFG_SCRATCH_REG30		0x403b
502#define MDIO_84833_TOP_CFG_SCRATCH_REG31		0x403c
503#define MDIO_84833_CMD_HDLR_COMMAND	MDIO_84833_TOP_CFG_SCRATCH_REG0
504#define MDIO_84833_CMD_HDLR_STATUS	MDIO_84833_TOP_CFG_SCRATCH_REG26
505#define MDIO_84833_CMD_HDLR_DATA1	MDIO_84833_TOP_CFG_SCRATCH_REG27
506#define MDIO_84833_CMD_HDLR_DATA2	MDIO_84833_TOP_CFG_SCRATCH_REG28
507#define MDIO_84833_CMD_HDLR_DATA3	MDIO_84833_TOP_CFG_SCRATCH_REG29
508#define MDIO_84833_CMD_HDLR_DATA4	MDIO_84833_TOP_CFG_SCRATCH_REG30
509#define MDIO_84833_CMD_HDLR_DATA5	MDIO_84833_TOP_CFG_SCRATCH_REG31
510
511/* Mailbox command set used by 84833. */
512#define PHY84833_CMD_SET_PAIR_SWAP			0x8001
513#define PHY84833_CMD_GET_EEE_MODE			0x8008
514#define PHY84833_CMD_SET_EEE_MODE			0x8009
515#define PHY84833_CMD_GET_CURRENT_TEMP			0x8031
516/* Mailbox status set used by 84833. */
517#define PHY84833_STATUS_CMD_RECEIVED			0x0001
518#define PHY84833_STATUS_CMD_IN_PROGRESS			0x0002
519#define PHY84833_STATUS_CMD_COMPLETE_PASS		0x0004
520#define PHY84833_STATUS_CMD_COMPLETE_ERROR		0x0008
521#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS		0x0010
522#define PHY84833_STATUS_CMD_SYSTEM_BOOT			0x0020
523#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS		0x0040
524#define PHY84833_STATUS_CMD_CLEAR_COMPLETE		0x0080
525#define PHY84833_STATUS_CMD_OPEN_OVERRIDE		0xa5a5
526
527
528/* Warpcore clause 45 addressing */
529#define MDIO_WC_DEVAD					0x3
530#define MDIO_WC_REG_IEEE0BLK_MIICNTL                    0x0
531#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP                  0x7
532#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0       0x10
533#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1       0x11
534#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2       0x12
535	#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY	0x4000
536	#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ		0x8000
537#define MDIO_WC_REG_PCS_STATUS2				0x0021
538#define MDIO_WC_REG_PMD_KR_CONTROL			0x0096
539#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL                0x8000
540#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1               0x800e
541#define MDIO_WC_REG_XGXSBLK1_DESKEW                     0x8010
542#define MDIO_WC_REG_XGXSBLK1_LANECTRL0                  0x8015
543#define MDIO_WC_REG_XGXSBLK1_LANECTRL1                  0x8016
544#define MDIO_WC_REG_XGXSBLK1_LANECTRL2                  0x8017
545#define MDIO_WC_REG_XGXSBLK1_LANECTRL3                  0x8018
546#define MDIO_WC_REG_XGXSBLK1_LANETEST0                  0x801a
547#define MDIO_WC_REG_TX0_ANA_CTRL0			0x8061
548#define MDIO_WC_REG_TX1_ANA_CTRL0			0x8071
549#define MDIO_WC_REG_TX2_ANA_CTRL0			0x8081
550#define MDIO_WC_REG_TX3_ANA_CTRL0			0x8091
551#define MDIO_WC_REG_TX0_TX_DRIVER			0x8067
552#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET		0x04
553#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK			0x00f0
554#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET		0x08
555#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK				0x0f00
556#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET		0x0c
557#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK			0x7000
558#define MDIO_WC_REG_TX1_TX_DRIVER			0x8077
559#define MDIO_WC_REG_TX2_TX_DRIVER			0x8087
560#define MDIO_WC_REG_TX3_TX_DRIVER			0x8097
561#define MDIO_WC_REG_RX0_ANARXCONTROL1G                  0x80b9
562#define MDIO_WC_REG_RX2_ANARXCONTROL1G                  0x80d9
563#define MDIO_WC_REG_RX0_PCI_CTRL			0x80ba
564#define MDIO_WC_REG_RX1_PCI_CTRL			0x80ca
565#define MDIO_WC_REG_RX2_PCI_CTRL			0x80da
566#define MDIO_WC_REG_RX3_PCI_CTRL			0x80ea
567#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI		0x80fa
568#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 		0x8104
569#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 		0x810a
570#define MDIO_WC_REG_XGXS_STATUS3			0x8129
571#define MDIO_WC_REG_PAR_DET_10G_STATUS			0x8130
572#define MDIO_WC_REG_PAR_DET_10G_CTRL			0x8131
573#define MDIO_WC_REG_XGXS_STATUS4                        0x813c
574#define MDIO_WC_REG_XGXS_X2_CONTROL2 		        0x8141
575#define MDIO_WC_REG_XGXS_X2_CONTROL3 		        0x8142
576#define MDIO_WC_REG_XGXS_RX_LN_SWAP1		      	0x816B
577#define MDIO_WC_REG_XGXS_TX_LN_SWAP1		      	0x8169
578#define MDIO_WC_REG_GP2_STATUS_GP_2_0			0x81d0
579#define MDIO_WC_REG_GP2_STATUS_GP_2_1			0x81d1
580#define MDIO_WC_REG_GP2_STATUS_GP_2_2			0x81d2
581#define MDIO_WC_REG_GP2_STATUS_GP_2_3			0x81d3
582#define MDIO_WC_REG_GP2_STATUS_GP_2_4			0x81d4
583	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
584	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
585	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
586	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
587#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP                0x81EE
588#define MDIO_WC_REG_UC_INFO_B1_VERSION                  0x81F0
589#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE		0x81F2
590	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET	0x0
591		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT        0x0
592		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR     0x1
593		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC        0x2
594		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI      0x3
595		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G     0x4
596	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET	0x4
597	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET	0x8
598	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET	0xc
599#define MDIO_WC_REG_UC_INFO_B1_CRC                      0x81FE
600#define MDIO_WC_REG_DSC1B0_UC_CTRL				0x820e
601	#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD			(1<<7)
602#define MDIO_WC_REG_DSC_SMC				0x8213
603#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0		0x821e
604#define MDIO_WC_REG_TX_FIR_TAP				0x82e2
605	#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET		0x00
606	#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK			0x000f
607	#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET		0x04
608	#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK		0x03f0
609	#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET		0x0a
610	#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK		0x7c00
611	#define MDIO_WC_REG_TX_FIR_TAP_ENABLE		0x8000
612#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP		0x82e2
613#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL      0x82e3
614#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL	0x82e6
615#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL	0x82e7
616#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL	0x82e8
617#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL      0x82ec
618#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1         0x8300
619#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2         0x8301
620#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3         0x8302
621#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1          0x8304
622#define MDIO_WC_REG_SERDESDIGITAL_MISC1                 0x8308
623#define MDIO_WC_REG_SERDESDIGITAL_MISC2                 0x8309
624#define MDIO_WC_REG_DIGITAL3_UP1                        0x8329
625#define MDIO_WC_REG_DIGITAL3_LP_UP1                     0x832c
626#define MDIO_WC_REG_DIGITAL4_MISC3                      0x833c
627#define MDIO_WC_REG_DIGITAL4_MISC5                      0x833e
628#define MDIO_WC_REG_DIGITAL5_MISC6                      0x8345
629#define MDIO_WC_REG_DIGITAL5_MISC7                      0x8349
630#define MDIO_WC_REG_DIGITAL5_LINK_STATUS		0x834d
631#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED               0x834e
632#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL           0x8350
633#define MDIO_WC_REG_CL49_USERB0_CTRL	                0x8368
634#define MDIO_WC_REG_CL73_USERB0_CTRL                    0x8370
635#define MDIO_WC_REG_CL73_USERB0_USTAT                   0x8371
636#define MDIO_WC_REG_CL73_BAM_CTRL1			0x8372
637#define MDIO_WC_REG_CL73_BAM_CTRL2			0x8373
638#define MDIO_WC_REG_CL73_BAM_CTRL3			0x8374
639#define MDIO_WC_REG_CL73_BAM_CODE_FIELD			0x837b
640#define MDIO_WC_REG_EEE_COMBO_CONTROL0                  0x8390
641#define MDIO_WC_REG_TX66_CONTROL                        0x83b0
642#define MDIO_WC_REG_RX66_CONTROL                        0x83c0
643#define MDIO_WC_REG_RX66_SCW0                           0x83c2
644#define MDIO_WC_REG_RX66_SCW1                           0x83c3
645#define MDIO_WC_REG_RX66_SCW2                           0x83c4
646#define MDIO_WC_REG_RX66_SCW3                           0x83c5
647#define MDIO_WC_REG_RX66_SCW0_MASK                      0x83c6
648#define MDIO_WC_REG_RX66_SCW1_MASK                      0x83c7
649#define MDIO_WC_REG_RX66_SCW2_MASK                      0x83c8
650#define MDIO_WC_REG_RX66_SCW3_MASK                      0x83c9
651#define MDIO_WC_REG_FX100_CTRL1				0x8400
652#define MDIO_WC_REG_FX100_CTRL3				0x8402
653#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5		0x8436
654#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6		0x8437
655#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7		0x8438
656#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9		0x8439
657#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10		0x843a
658#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11		0x843b
659#define MDIO_WC_REG_ETA_CL73_OUI1			0x8453
660#define MDIO_WC_REG_ETA_CL73_OUI2			0x8454
661#define MDIO_WC_REG_ETA_CL73_OUI3			0x8455
662#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE		0x8456
663#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE			0x8457
664#define MDIO_WC_REG_MICROBLK_CMD                        0xffc2
665#define MDIO_WC_REG_MICROBLK_DL_STATUS                  0xffc5
666#define MDIO_WC_REG_MICROBLK_CMD3                       0xffcc
667
668#define MDIO_WC_REG_AERBLK_AER                          0xffde
669#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL			0xffe0
670#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT                0xffe1
671
672#define MDIO_WC0_XGXS_BLK2_LANE_RESET                   0x810A
673	#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 	0
674	#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 	4
675
676#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2             0x8141
677
678#define DIGITAL5_ACTUAL_SPEED_TX_MASK                   0x003f
679
680/* 54618se */
681#define MDIO_REG_GPHY_MII_STATUS			0x1
682#define MDIO_REG_GPHY_PHYID_LSB				0x3
683#define MDIO_REG_GPHY_CL45_ADDR_REG			0xd
684	#define MDIO_REG_GPHY_CL45_REG_WRITE		0x4000
685	#define MDIO_REG_GPHY_CL45_REG_READ		0xc000
686#define MDIO_REG_GPHY_CL45_DATA_REG			0xe
687	#define MDIO_REG_GPHY_EEE_RESOLVED		0x803e
688#define MDIO_REG_GPHY_EXP_ACCESS_GATE			0x15
689#define MDIO_REG_GPHY_EXP_ACCESS			0x17
690	#define MDIO_REG_GPHY_EXP_ACCESS_TOP		0xd00
691	#define MDIO_REG_GPHY_EXP_TOP_2K_BUF		0x40
692#define MDIO_REG_GPHY_AUX_STATUS			0x19
693#define MDIO_REG_INTR_STATUS				0x1a
694#define MDIO_REG_INTR_MASK				0x1b
695	#define MDIO_REG_INTR_MASK_LINK_STATUS			(0x1 << 1)
696#define MDIO_REG_GPHY_SHADOW				0x1c
697	#define MDIO_REG_GPHY_SHADOW_LED_SEL1			(0x0d << 10)
698	#define MDIO_REG_GPHY_SHADOW_LED_SEL2			(0x0e << 10)
699	#define MDIO_REG_GPHY_SHADOW_WR_ENA			(0x1 << 15)
700	#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED		(0x1e << 10)
701	#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD		(0x1 << 8)
702