1*d14abf15SRobert Mustacchi /* 2*d14abf15SRobert Mustacchi * CDDL HEADER START 3*d14abf15SRobert Mustacchi * 4*d14abf15SRobert Mustacchi * The contents of this file are subject to the terms of the 5*d14abf15SRobert Mustacchi * Common Development and Distribution License (the "License"). 6*d14abf15SRobert Mustacchi * You may not use this file except in compliance with the License. 7*d14abf15SRobert Mustacchi * 8*d14abf15SRobert Mustacchi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d14abf15SRobert Mustacchi * or http://www.opensolaris.org/os/licensing. 10*d14abf15SRobert Mustacchi * See the License for the specific language governing permissions 11*d14abf15SRobert Mustacchi * and limitations under the License. 12*d14abf15SRobert Mustacchi * 13*d14abf15SRobert Mustacchi * When distributing Covered Code, include this CDDL HEADER in each 14*d14abf15SRobert Mustacchi * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d14abf15SRobert Mustacchi * If applicable, add the following below this CDDL HEADER, with the 16*d14abf15SRobert Mustacchi * fields enclosed by brackets "[]" replaced with your own identifying 17*d14abf15SRobert Mustacchi * information: Portions Copyright [yyyy] [name of copyright owner] 18*d14abf15SRobert Mustacchi * 19*d14abf15SRobert Mustacchi * CDDL HEADER END 20*d14abf15SRobert Mustacchi * 21*d14abf15SRobert Mustacchi * Copyright 2014 QLogic Corporation 22*d14abf15SRobert Mustacchi * The contents of this file are subject to the terms of the 23*d14abf15SRobert Mustacchi * QLogic End User License (the "License"). 24*d14abf15SRobert Mustacchi * You may not use this file except in compliance with the License. 25*d14abf15SRobert Mustacchi * 26*d14abf15SRobert Mustacchi * You can obtain a copy of the License at 27*d14abf15SRobert Mustacchi * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 28*d14abf15SRobert Mustacchi * QLogic_End_User_Software_License.txt 29*d14abf15SRobert Mustacchi * See the License for the specific language governing permissions 30*d14abf15SRobert Mustacchi * and limitations under the License. 31*d14abf15SRobert Mustacchi * 32*d14abf15SRobert Mustacchi */ 33*d14abf15SRobert Mustacchi static const struct iro e1_iro_arr[385] = { 34*d14abf15SRobert Mustacchi { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE 35*d14abf15SRobert Mustacchi { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE 36*d14abf15SRobert Mustacchi { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE 37*d14abf15SRobert Mustacchi { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE 38*d14abf15SRobert Mustacchi { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE 39*d14abf15SRobert Mustacchi { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE 40*d14abf15SRobert Mustacchi { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE 41*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE 42*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID 43*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVENT_ID 44*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_OFFSET 45*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_OFFSET 46*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_OFFSET 47*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_RESULT_OFFSET 48*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_RESULT_OFFSET 49*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_RESULT_OFFSET 50*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_MASK 51*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_MASK 52*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_MASK 53*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_AGG_INT 54*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_EVENTID 55*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_PCI_READ_OPCODE 56*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_OPCODE 57*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_INCVAL 58*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_REGION 59*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_CID 60*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_RUN_PBF_ECHO_TEST 61*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_QM_PAUSE_OPCODE 62*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_SUCCESS_OPCODE_VALUE 63*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_OPCODE_VALUE 64*d14abf15SRobert Mustacchi { 0x3320, 0x10, 0x0, 0x0, 0x8}, // XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) 65*d14abf15SRobert Mustacchi { 0x3328, 0x10, 0x0, 0x0, 0x2}, // XSTORM_SPQ_PROD_OFFSET(funcId) 66*d14abf15SRobert Mustacchi { 0x3320, 0x10, 0x0, 0x0, 0x10}, // XSTORM_SPQ_DATA_OFFSET(funcId) 67*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId) 68*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId) 69*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId) 70*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId) 71*d14abf15SRobert Mustacchi { 0x3358, 0x1, 0x4, 0x0, 0x1}, // XSTORM_JUMBO_SUPPORT_OFFSET(pfId) 72*d14abf15SRobert Mustacchi { 0x3360, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_IP_ID_MASK_OFFSET 73*d14abf15SRobert Mustacchi { 0x3368, 0x0, 0x0, 0x0, 0x8}, // XSTORM_COMMON_RTC_PARAMS_OFFSET 74*d14abf15SRobert Mustacchi { 0x336c, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_RTC_RESOLUTION_OFFSET 75*d14abf15SRobert Mustacchi { 0x3920, 0x0, 0x0, 0x0, 0x8}, // XSTORM_FW_VERSION_OFFSET 76*d14abf15SRobert Mustacchi { 0x3af8, 0x40, 0x0, 0x0, 0x40}, // XSTORM_LICENSE_VALUES_OFFSET(pfId) 77*d14abf15SRobert Mustacchi { 0x3938, 0x80, 0x0, 0x0, 0x48}, // XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) 78*d14abf15SRobert Mustacchi { 0x3a38, 0x40, 0x0, 0x0, 0x8}, // XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) 79*d14abf15SRobert Mustacchi { 0x3a48, 0x40, 0x0, 0x0, 0x18}, // XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) 80*d14abf15SRobert Mustacchi { 0x3370, 0x28, 0x0, 0x0, 0x28}, // XSTORM_PER_QUEUE_STATS_OFFSET(xStatQueueId) 81*d14abf15SRobert Mustacchi { 0x3c20, 0x8, 0x0, 0x0, 0x1}, // XSTORM_FUNC_EN_OFFSET(funcId) 82*d14abf15SRobert Mustacchi { 0x3c21, 0x8, 0x0, 0x0, 0x1}, // XSTORM_VF_TO_PF_OFFSET(funcId) 83*d14abf15SRobert Mustacchi { 0x3c22, 0x8, 0x0, 0x0, 0x1}, // XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) 84*d14abf15SRobert Mustacchi { 0x2008, 0x10, 0x0, 0x0, 0x10}, // XSTORM_ASSERT_LIST_OFFSET(assertListEntry) 85*d14abf15SRobert Mustacchi { 0x2000, 0x0, 0x0, 0x0, 0x8}, // XSTORM_ASSERT_LIST_INDEX_OFFSET 86*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET 87*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // PCI_READ_KUKUE_CODE_OPPCOE 88*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // LOAD_CONTEXT_KUKUE_CODE_OPPCOE 89*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // QM_PAUSE_KUKUE_CODE_OPPCOE 90*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT0_KUKUE_CODE_OPPCOE 91*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT0_KUKUE_CODE_OPPCOE 92*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT1_KUKUE_CODE_OPPCOE 93*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT1_KUKUE_CODE_OPPCOE 94*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TEST_UNUSED_FOCS_KUKUE_CODE_OPPCOE 95*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // PBF_ECHO_KUKUE_CODE_OPPCOE 96*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT0_KUKUE_CODE_OPPCOE 97*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT1_KUKUE_CODE_OPPCOE 98*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // IGU_TEST_KUKUE_CODE_OPPCOE 99*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_INITIAL_CLEANUP_INDEX 100*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_INDEX 101*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE 102*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET 103*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET 104*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId) 105*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId) 106*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET 107*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_RAM_OFFSET 108*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_OPPORTUNISTIC_RAM_OFFSET 109*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_SIDE_INFO_INPUT_LSB_OFFSET 110*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_OFFSET 111*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_EN_OFFSET 112*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_LINE_OFFSET 113*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_RESULT_OFFSET 114*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_OP_GEN_VALUE 115*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES 116*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX 117*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX 118*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX 119*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DPM_BUFFER_OFFSET 120*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TEST_OPCODE_OFFSET 121*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET 122*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_OP_GEN_VALUE 123*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_QUEUE_MASK_OFFSET 124*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_GROUP_OFFSET 125*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_PORT_OFFSET 126*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_OPCODE 127*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_INCVAL 128*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_REGION 129*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_RUN_PBF_ECHO_TEST 130*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_CID 131*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_SUCCESS_VALUE 132*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId) 133*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INDIRECTION_TABLE_ENTRY_SIZE 134*d14abf15SRobert Mustacchi { 0x19c8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_COMMON_RTC_PARAMS_OFFSET 135*d14abf15SRobert Mustacchi { 0x2008, 0x10, 0x0, 0x0, 0x10}, // TSTORM_ASSERT_LIST_OFFSET(assertListEntry) 136*d14abf15SRobert Mustacchi { 0x2000, 0x0, 0x0, 0x0, 0x8}, // TSTORM_ASSERT_LIST_INDEX_OFFSET 137*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MEASURE_PCI_LATENCY_CTRL_OFFSET 138*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MEASURE_PCI_LATENCY_DATA_OFFSET 139*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_AGG_MEASURE_PCI_LATENCY_INDEX 140*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_AGG_MEASURE_PCI_LATENCY_COMP_TYPE 141*d14abf15SRobert Mustacchi { 0x4870, 0x8, 0x0, 0x0, 0x1}, // TSTORM_FUNC_EN_OFFSET(funcId) 142*d14abf15SRobert Mustacchi { 0x4871, 0x8, 0x0, 0x0, 0x1}, // TSTORM_VF_TO_PF_OFFSET(funcId) 143*d14abf15SRobert Mustacchi { 0x4872, 0x8, 0x0, 0x0, 0x1}, // TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) 144*d14abf15SRobert Mustacchi { 0x4040, 0x38, 0x0, 0x0, 0x38}, // TSTORM_PER_QUEUE_STATS_OFFSET(tStatQueueId) 145*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET 146*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET 147*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET 148*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId) 149*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_QUEUE_ZONE_OFFSET(queueId) 150*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VF_ZONE_OFFSET(vfId) 151*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_E2_INTEG_RAM_OFFSET 152*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_LSB_SIDE_BAND_INFO_OFFSET 153*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MSB_SIDE_BAND_INFO_OFFSET 154*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_LINE_OFFSET 155*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RESULT_OFFSET 156*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_OP_GEN_VALUE 157*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES 158*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX 159*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX 160*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX 161*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_TEST_OPCODE_OFFSET 162*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET 163*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_OP_GEN_VALUE 164*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET 165*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET 166*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET 167*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET 168*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET 169*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET 170*d14abf15SRobert Mustacchi { 0x4000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_OFFSET(sbId) 171*d14abf15SRobert Mustacchi { 0x4800, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) 172*d14abf15SRobert Mustacchi { 0x482e, 0x40, 0x0, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) 173*d14abf15SRobert Mustacchi { 0x4800, 0x40, 0x2, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId,hcIndex) 174*d14abf15SRobert Mustacchi { 0x4801, 0x40, 0x2, 0x0, 0x0}, // CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId,hcIndex) 175*d14abf15SRobert Mustacchi { 0x3000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_SYNC_BLOCK_OFFSET(sbId) 176*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex,sbId) 177*d14abf15SRobert Mustacchi { 0x3000, 0x8, 0x40, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex,sbId) 178*d14abf15SRobert Mustacchi { 0x3004, 0x8, 0x40, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_DHC_OFFSET(sbSyncLines,sbId) 179*d14abf15SRobert Mustacchi { 0x3b80, 0x28, 0x0, 0x0, 0x28}, // CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) 180*d14abf15SRobert Mustacchi { 0x3bd0, 0x10, 0x0, 0x0, 0x10}, // CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) 181*d14abf15SRobert Mustacchi { 0x3bda, 0x10, 0x0, 0x0, 0x1}, // CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) 182*d14abf15SRobert Mustacchi { 0x3800, 0x80, 0x0, 0x0, 0x80}, // CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) 183*d14abf15SRobert Mustacchi { 0x3800, 0x8, 0x80, 0x0, 0x2}, // CSTORM_SP_HC_SYNC_LINE_INDEX_OFFSET(hcSpIndex,pfId) 184*d14abf15SRobert Mustacchi { 0x3900, 0x40, 0x0, 0x0, 0x40}, // CSTORM_DYNAMIC_HC_CONFIG_OFFSET(pfId) 185*d14abf15SRobert Mustacchi { 0x2008, 0x10, 0x0, 0x0, 0x10}, // CSTORM_ASSERT_LIST_OFFSET(assertListEntry) 186*d14abf15SRobert Mustacchi { 0x2000, 0x0, 0x0, 0x0, 0x8}, // CSTORM_ASSERT_LIST_INDEX_OFFSET 187*d14abf15SRobert Mustacchi { 0x5198, 0x8, 0x0, 0x0, 0x1}, // CSTORM_FUNC_EN_OFFSET(funcId) 188*d14abf15SRobert Mustacchi { 0x5199, 0x8, 0x0, 0x0, 0x1}, // CSTORM_VF_TO_PF_OFFSET(funcId) 189*d14abf15SRobert Mustacchi { 0x519a, 0x8, 0x0, 0x0, 0x1}, // CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) 190*d14abf15SRobert Mustacchi { 0x3980, 0x10, 0x4, 0x0, 0x4}, // CSTORM_BYTE_COUNTER_OFFSET(sbId,dhcIndex) 191*d14abf15SRobert Mustacchi { 0x51a8, 0x30, 0x18, 0x0, 0x10}, // CSTORM_EVENT_RING_DATA_OFFSET(pfId) 192*d14abf15SRobert Mustacchi { 0x51b0, 0x30, 0x18, 0x0, 0x2}, // CSTORM_EVENT_RING_PROD_OFFSET(pfId) 193*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) 194*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) 195*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_MODE_OFFSET 196*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET 197*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) 198*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_QUEUE_ZONE_OFFSET(queueId) 199*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_ZONE_OFFSET(vfId) 200*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES 201*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX 202*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX 203*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX 204*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_TEST_OPCODE_OFFSET 205*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET 206*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_OP_GEN_VALUE 207*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_PF_ID_OFFSET 208*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_VF_ID_OFFSET 209*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_VF_VALID_OFFSET 210*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_ADDRESS_OFFSET 211*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_IGU_COMMAND_OFFSET 212*d14abf15SRobert Mustacchi { 0x23e8, 0x80, 0x0, 0x0, 0x80}, // USTORM_INDIRECTION_TABLE_OFFSET(portId) 213*d14abf15SRobert Mustacchi { 0x1, 0x0, 0x0, 0x0, 0x0}, // USTORM_INDIRECTION_TABLE_ENTRY_SIZE 214*d14abf15SRobert Mustacchi { 0x2008, 0x10, 0x0, 0x0, 0x10}, // USTORM_ASSERT_LIST_OFFSET(assertListEntry) 215*d14abf15SRobert Mustacchi { 0x2000, 0x0, 0x0, 0x0, 0x8}, // USTORM_ASSERT_LIST_INDEX_OFFSET 216*d14abf15SRobert Mustacchi { 0x2e70, 0x8, 0x0, 0x0, 0x1}, // USTORM_FUNC_EN_OFFSET(funcId) 217*d14abf15SRobert Mustacchi { 0x2e71, 0x8, 0x0, 0x0, 0x1}, // USTORM_VF_TO_PF_OFFSET(funcId) 218*d14abf15SRobert Mustacchi { 0x2e72, 0x8, 0x0, 0x0, 0x1}, // USTORM_RECORD_SLOW_PATH_OFFSET(funcId) 219*d14abf15SRobert Mustacchi { 0x24e8, 0x38, 0x0, 0x0, 0x38}, // USTORM_PER_QUEUE_STATS_OFFSET(uStatQueueId) 220*d14abf15SRobert Mustacchi { 0x2dd0, 0x8, 0x0, 0x0, 0x8}, // USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) 221*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) 222*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_PAUSE_ENABLED_OFFSET(portId) 223*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_MAX_PAUSE_TIME_USEC_OFFSET(portId) 224*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET 225*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_QUEUE_ZONE_OFFSET(queueId) 226*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_VF_ZONE_OFFSET(vfId) 227*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES 228*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX 229*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX 230*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX 231*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_TEST_OPCODE_OFFSET 232*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET 233*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_OP_GEN_VALUE 234*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET 235*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET 236*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET 237*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET 238*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET 239*d14abf15SRobert Mustacchi { 0x2500, 0x40, 0x0, 0x0, 0x8}, // TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) 240*d14abf15SRobert Mustacchi { 0x2508, 0x40, 0x0, 0x0, 0x20}, // TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) 241*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) 242*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET 243*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ACCEPT_CLASSIFY_FAIL_E2_ENABLE_OFFSET(portId) 244*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ACCEPT_CLASSIFY_FAIL_E2_VNIC_OFFSET(portId) 245*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CQE_PAGE_NEXT_OFFSET(portId,clientId) 246*d14abf15SRobert Mustacchi { 0x3000, 0x0, 0x0, 0x0, 0x1000}, // USTORM_AGG_DATA_OFFSET 247*d14abf15SRobert Mustacchi { 0x50a1, 0x0, 0x0, 0x0, 0x1}, // USTORM_TPA_BTR_OFFSET 248*d14abf15SRobert Mustacchi { 0x50b8, 0x0, 0x0, 0x0, 0x2}, // USTORM_ETH_DYNAMIC_HC_PARAM_OFFSET 249*d14abf15SRobert Mustacchi { 0x50c8, 0x90, 0x8, 0x0, 0x8}, // USTORM_RX_PRODS_E1X_OFFSET(portId,clientId) 250*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_RX_PRODS_E2_OFFSET(qzoneId) 251*d14abf15SRobert Mustacchi { 0x2960, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) 252*d14abf15SRobert Mustacchi { 0x2961, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) 253*d14abf15SRobert Mustacchi { 0x2970, 0x8, 0x4, 0x0, 0x2}, // XSTORM_TCP_IPID_OFFSET(pfId) 254*d14abf15SRobert Mustacchi { 0x2978, 0x8, 0x4, 0x0, 0x4}, // XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) 255*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TCP_TX_SWITCHING_EN_OFFSET(portId) 256*d14abf15SRobert Mustacchi { 0x2fb0, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_DUPLICATE_ACK_THRESHOLD_OFFSET(pfId) 257*d14abf15SRobert Mustacchi { 0x2fb4, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_MAX_CWND_OFFSET(pfId) 258*d14abf15SRobert Mustacchi { 0x2fc0, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_GLOBAL_PARAMS_OFFSET 259*d14abf15SRobert Mustacchi { 0x2fc8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_ISLES_ARRAY_DESCRIPTOR_OFFSET 260*d14abf15SRobert Mustacchi { 0x3000, 0x0, 0x0, 0x0, 0x10}, // TSTORM_TCP_ISLES_ARRAY_OFFSET 261*d14abf15SRobert Mustacchi { 0x5040, 0x1, 0x1, 0x0, 0x1}, // XSTORM_TOE_LLC_SNAP_ENABLED_OFFSET(pfId) 262*d14abf15SRobert Mustacchi { 0x5000, 0x0, 0x0, 0x0, 0x20}, // XSTORM_OUT_OCTETS_OFFSET 263*d14abf15SRobert Mustacchi { 0x808, 0x10, 0x0, 0x0, 0x4}, // TSTORM_TOE_MAX_SEG_RETRANSMIT_OFFSET(pfId) 264*d14abf15SRobert Mustacchi { 0x80c, 0x10, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOUBT_REACHABILITY_OFFSET(pfId) 265*d14abf15SRobert Mustacchi { 0x8b7, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_MAX_DOMINANCE_VALUE_OFFSET 266*d14abf15SRobert Mustacchi { 0x8b6, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOMINANCE_THRESHOLD_OFFSET 267*d14abf15SRobert Mustacchi { 0x1000, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId) 268*d14abf15SRobert Mustacchi { 0x1004, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId) 269*d14abf15SRobert Mustacchi { 0x1008, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_PROD_OFFSET(rssId,portId) 270*d14abf15SRobert Mustacchi { 0x100a, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_CONS_OFFSET(rssId,portId) 271*d14abf15SRobert Mustacchi { 0x100c, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId) 272*d14abf15SRobert Mustacchi { 0x100d, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId) 273*d14abf15SRobert Mustacchi { 0x100e, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId) 274*d14abf15SRobert Mustacchi { 0x1010, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId) 275*d14abf15SRobert Mustacchi { 0x1014, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId) 276*d14abf15SRobert Mustacchi { 0x1018, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_PROD_OFFSET(rssId,portId) 277*d14abf15SRobert Mustacchi { 0x101c, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_CONS_OFFSET(rssId,portId) 278*d14abf15SRobert Mustacchi { 0x3000, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_LO_OFFSET(rssId,portId,grqBdId) 279*d14abf15SRobert Mustacchi { 0x3004, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_HI_OFFSET(rssId,portId,grqBdId) 280*d14abf15SRobert Mustacchi { 0xa, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_CACHE_NUM_BDS 281*d14abf15SRobert Mustacchi { 0x3068, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_PROD_OFFSET(rssId,portId) 282*d14abf15SRobert Mustacchi { 0x3069, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_CONS_OFFSET(rssId,portId) 283*d14abf15SRobert Mustacchi { 0x306c, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_CONS_OFFSET(rssId,portId) 284*d14abf15SRobert Mustacchi { 0x306e, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_PROD_OFFSET(rssId,portId) 285*d14abf15SRobert Mustacchi { 0x3070, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(rssId,portId) 286*d14abf15SRobert Mustacchi { 0x3074, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(rssId,portId) 287*d14abf15SRobert Mustacchi { 0x3066, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_BUF_SIZE_OFFSET(rssId,portId) 288*d14abf15SRobert Mustacchi { 0x3064, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId) 289*d14abf15SRobert Mustacchi { 0x3060, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_CONS_OFFSET(rssId,portId) 290*d14abf15SRobert Mustacchi { 0x3062, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_PROD_OFFSET(rssId,portId) 291*d14abf15SRobert Mustacchi { 0x3050, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId) 292*d14abf15SRobert Mustacchi { 0x3054, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId) 293*d14abf15SRobert Mustacchi { 0x3058, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId) 294*d14abf15SRobert Mustacchi { 0x305c, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId) 295*d14abf15SRobert Mustacchi { 0x307c, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId) 296*d14abf15SRobert Mustacchi { 0x307d, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId) 297*d14abf15SRobert Mustacchi { 0x1c18, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_TCP_PUSH_TIMER_TICKS_OFFSET(pfId) 298*d14abf15SRobert Mustacchi { 0x1c30, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_GRQ_XOFF_COUNTER_OFFSET(pfId) 299*d14abf15SRobert Mustacchi { 0x1c38, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_RCQ_XOFF_COUNTER_OFFSET(pfId) 300*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_CQ_THR_LOW_OFFSET 301*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_THR_LOW_OFFSET 302*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_CQ_THR_HIGH_OFFSET 303*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_THR_HIGH_OFFSET 304*d14abf15SRobert Mustacchi { 0x4c10, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) 305*d14abf15SRobert Mustacchi { 0x4c12, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) 306*d14abf15SRobert Mustacchi { 0x4c14, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) 307*d14abf15SRobert Mustacchi { 0x4c16, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) 308*d14abf15SRobert Mustacchi { 0x4c20, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) 309*d14abf15SRobert Mustacchi { 0x4c00, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) 310*d14abf15SRobert Mustacchi { 0x4c02, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) 311*d14abf15SRobert Mustacchi { 0x4c04, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) 312*d14abf15SRobert Mustacchi { 0x4c30, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) 313*d14abf15SRobert Mustacchi { 0x4c40, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) 314*d14abf15SRobert Mustacchi { 0x4c44, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) 315*d14abf15SRobert Mustacchi { 0x4c50, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) 316*d14abf15SRobert Mustacchi { 0x4c54, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_RX_BDS_THRSHLD_OFFSET(pfId) 317*d14abf15SRobert Mustacchi { 0x4c52, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_CONS_OFFSET(pfId) 318*d14abf15SRobert Mustacchi { 0x4c60, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) 319*d14abf15SRobert Mustacchi { 0x1400, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) 320*d14abf15SRobert Mustacchi { 0x1402, 0x8, 0x0, 0x0, 0x1}, // USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) 321*d14abf15SRobert Mustacchi { 0x1404, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) 322*d14abf15SRobert Mustacchi { 0x1410, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) 323*d14abf15SRobert Mustacchi { 0x1414, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) 324*d14abf15SRobert Mustacchi { 0x1416, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) 325*d14abf15SRobert Mustacchi { 0x19b8, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) 326*d14abf15SRobert Mustacchi { 0x1420, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) 327*d14abf15SRobert Mustacchi { 0x1424, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) 328*d14abf15SRobert Mustacchi { 0x19c8, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) 329*d14abf15SRobert Mustacchi { 0x2c10, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) 330*d14abf15SRobert Mustacchi { 0x2c11, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) 331*d14abf15SRobert Mustacchi { 0x2c12, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) 332*d14abf15SRobert Mustacchi { 0x2c13, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) 333*d14abf15SRobert Mustacchi { 0x2c00, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) 334*d14abf15SRobert Mustacchi { 0x2c02, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) 335*d14abf15SRobert Mustacchi { 0x2c04, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) 336*d14abf15SRobert Mustacchi { 0x2c30, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) 337*d14abf15SRobert Mustacchi { 0x2c32, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) 338*d14abf15SRobert Mustacchi { 0x2c34, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) 339*d14abf15SRobert Mustacchi { 0x2c20, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) 340*d14abf15SRobert Mustacchi { 0x2c21, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) 341*d14abf15SRobert Mustacchi { 0x2c22, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) 342*d14abf15SRobert Mustacchi { 0x2c23, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) 343*d14abf15SRobert Mustacchi { 0x2c24, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) 344*d14abf15SRobert Mustacchi { 0x2c25, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) 345*d14abf15SRobert Mustacchi { 0x2c26, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) 346*d14abf15SRobert Mustacchi { 0x1480, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) 347*d14abf15SRobert Mustacchi { 0x1482, 0x8, 0x0, 0x0, 0x1}, // CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) 348*d14abf15SRobert Mustacchi { 0x1484, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) 349*d14abf15SRobert Mustacchi { 0x1492, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_PROD_OFFSET(pfId,iscsiEqId) 350*d14abf15SRobert Mustacchi { 0x1490, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_CONS_OFFSET(pfId,iscsiEqId) 351*d14abf15SRobert Mustacchi { 0x149c, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId,iscsiEqId) 352*d14abf15SRobert Mustacchi { 0x1494, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId,iscsiEqId) 353*d14abf15SRobert Mustacchi { 0x14a7, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId,iscsiEqId) 354*d14abf15SRobert Mustacchi { 0x14a4, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId,iscsiEqId) 355*d14abf15SRobert Mustacchi { 0x14a6, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId,iscsiEqId) 356*d14abf15SRobert Mustacchi { 0x1610, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) 357*d14abf15SRobert Mustacchi { 0x1620, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) 358*d14abf15SRobert Mustacchi { 0x1630, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) 359*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_EQ_PROD_OFFSET(pfId) 360*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_TIMER_PARAM_OFFSET 361*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TIMER_ARRAY_OFFSET 362*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FC_CRC_CNT_OFFSET 363*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_EOFA_DEL_CNT_OFFSET 364*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_MISS_FRAME_CNT_OFFSET 365*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_SEQ_TIMEOUT_CNT_OFFSET 366*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_DROP_SEQ_CNT_OFFSET 367*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET 368*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FCP_RX_PKT_CNT_OFFSET 369*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_OFFSET 370*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_DROP_PKT_CNT_OFFSET 371*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_OFFSET 372*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_ONE_OFFSET(cached_tbl_size) 373*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_TWO_OFFSET(cached_tbl_size) 374*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_ENTRY_TCE_OFFSET 375*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_ENTRY_MNG_INFO_OFFSET 376*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_CACHED_TCE_TBL_BIT_MAP_OFFSET 377*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAIT_4_BD_READ_OFFSET 378*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_DATA_OFFSET 379*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_NON_DATA_OFFSET 380*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_ERR_OFFSET 381*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_GLOBAL_TIMER_TASK_IN_USE_OFFSET 382*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_DEL_CACHED_TASK_OFFSET 383*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_SILENT_DROP_CACHED_TASK_OFFSET 384*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_OFFSET 385*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_DROP_OFFSET 386*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_CRC_ERROR_OFFSET 387*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_ERROR_OFFSET 388*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_PREVIOUS_THREAD_OFFSET 389*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DATA_IN_OFFSET 390*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_READ_TCE_OFFSET 391*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DROP_ERR_OFFSET 392*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_ERRORS_NUMBER_OFFSET 393*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_NUMBER_OFFSET 394*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_BITMAP_OFFSET 395*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_ENABLE_CONN_RACE_OFFSET 396*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_TASK_IN_USE_OFFSET 397*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_CRC_ERROR_TASK_IN_USE_OFFSET 398*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FCOE_TIMER_PARAM_OFFSET 399*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIMER_ARRAY_OFFSET 400*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCOE_TX_PKT_CNT_OFFSET 401*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCOE_TX_BYTE_CNT_OFFSET 402*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCP_TX_PKT_CNT_OFFSET 403*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_OFFSET 404*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_ABTS_BLOCK_SQ_CNT_OFFSET 405*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_CLEANUP_BLOCK_SQ_CNT_OFFSET 406*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_OFFSET 407*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_VER_CNT_OFFSET 408*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_PKT_CNT_OFFSET 409*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_BYTE_CNT_OFFSET 410*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET 411*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_OFFSET 412*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_WAIT_FOR_YOUR_TURN_SP_CNT_OFFSET 413*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_AFEX_ERROR_PACKETS_OFFSET 414*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_OFFSET 415*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_DATA_OFFSET 416*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_WAITING_TABLE_OFFSET 417*d14abf15SRobert Mustacchi { 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_WAITING_LIST_SIZE 418*d14abf15SRobert Mustacchi {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_WAITING_ENTRY_OFFSET 419*d14abf15SRobert Mustacchi }; 420