1d14abf15SRobert Mustacchi /*******************************************************************************
2d14abf15SRobert Mustacchi  * CDDL HEADER START
3d14abf15SRobert Mustacchi  *
4d14abf15SRobert Mustacchi  * The contents of this file are subject to the terms of the
5d14abf15SRobert Mustacchi  * Common Development and Distribution License (the "License").
6d14abf15SRobert Mustacchi  * You may not use this file except in compliance with the License.
7d14abf15SRobert Mustacchi  *
8d14abf15SRobert Mustacchi  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9d14abf15SRobert Mustacchi  * or http://www.opensolaris.org/os/licensing.
10d14abf15SRobert Mustacchi  * See the License for the specific language governing permissions
11d14abf15SRobert Mustacchi  * and limitations under the License.
12d14abf15SRobert Mustacchi  *
13d14abf15SRobert Mustacchi  * When distributing Covered Code, include this CDDL HEADER in each
14d14abf15SRobert Mustacchi  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15d14abf15SRobert Mustacchi  * If applicable, add the following below this CDDL HEADER, with the
16d14abf15SRobert Mustacchi  * fields enclosed by brackets "[]" replaced with your own identifying
17d14abf15SRobert Mustacchi  * information: Portions Copyright [yyyy] [name of copyright owner]
18d14abf15SRobert Mustacchi  *
19d14abf15SRobert Mustacchi  * CDDL HEADER END
20d14abf15SRobert Mustacchi  *
21d14abf15SRobert Mustacchi  * Copyright 2014 QLogic Corporation
22d14abf15SRobert Mustacchi  * The contents of this file are subject to the terms of the
23d14abf15SRobert Mustacchi  * QLogic End User License (the "License").
24d14abf15SRobert Mustacchi  * You may not use this file except in compliance with the License.
25d14abf15SRobert Mustacchi  *
26d14abf15SRobert Mustacchi  * You can obtain a copy of the License at
27d14abf15SRobert Mustacchi  * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
28d14abf15SRobert Mustacchi  * QLogic_End_User_Software_License.txt
29d14abf15SRobert Mustacchi  * See the License for the specific language governing permissions
30d14abf15SRobert Mustacchi  * and limitations under the License.
31d14abf15SRobert Mustacchi  *
32d14abf15SRobert Mustacchi  *
33d14abf15SRobert Mustacchi  * Module Description:
34d14abf15SRobert Mustacchi  *      This file contains functions that handle IGU access and SB management
35d14abf15SRobert Mustacchi  *
36d14abf15SRobert Mustacchi  ******************************************************************************/
37d14abf15SRobert Mustacchi 
38d14abf15SRobert Mustacchi #include "lm5710.h"
39d14abf15SRobert Mustacchi #include "577xx_int_offsets.h"
40d14abf15SRobert Mustacchi #include "bcmtype.h"
41d14abf15SRobert Mustacchi 
42d14abf15SRobert Mustacchi /* Reads IGU interrupt status register MSB / LSB */
lm_read_isr32(lm_device_t * pdev,u32_t addr)43d14abf15SRobert Mustacchi static u32_t lm_read_isr32 (
44d14abf15SRobert Mustacchi     lm_device_t *pdev,
45d14abf15SRobert Mustacchi     u32_t addr)
46d14abf15SRobert Mustacchi {
47d14abf15SRobert Mustacchi     u32 offset = IS_PFDEV(pdev) ? BAR_IGU_INTMEM : VF_BAR0_IGU_OFFSET;
48d14abf15SRobert Mustacchi     u32_t res = 0;
49d14abf15SRobert Mustacchi     u32_t value;
50d14abf15SRobert Mustacchi     do {
51d14abf15SRobert Mustacchi         /* Read the 32 bit value from BAR */
52d14abf15SRobert Mustacchi         LM_BAR_RD32_OFFSET(pdev,BAR_0,offset + addr, &value);
53d14abf15SRobert Mustacchi         DbgMessage(pdev, VERBOSEi, "  ### lm_read_isr32 read address 0x%x value=0x%x\n",addr,value);
54d14abf15SRobert Mustacchi         DbgBreakIf(value == 0xffffffff);
55d14abf15SRobert Mustacchi         res |= value;
56d14abf15SRobert Mustacchi         /* Do one more iteration if we got the value for a legitimate "all ones" */
57d14abf15SRobert Mustacchi     } while (value == 0xefffffff);
58d14abf15SRobert Mustacchi     return res;
59d14abf15SRobert Mustacchi }
60d14abf15SRobert Mustacchi 
61d14abf15SRobert Mustacchi /* Reads IGU interrupt status register MSB / LSB */
lm_read_isr64(lm_device_t * pdev,u32_t addr)62d14abf15SRobert Mustacchi static u64_t lm_read_isr64(
63d14abf15SRobert Mustacchi     lm_device_t *pdev,
64d14abf15SRobert Mustacchi     u32_t addr)
65d14abf15SRobert Mustacchi {
66d14abf15SRobert Mustacchi     u32 offset = IS_PFDEV(pdev) ? BAR_IGU_INTMEM : VF_BAR0_IGU_OFFSET;
67d14abf15SRobert Mustacchi     u64_t res = 0;
68d14abf15SRobert Mustacchi     u64_t value;
69d14abf15SRobert Mustacchi     do {
70d14abf15SRobert Mustacchi         /* Read the 32 bit value from BAR */
71d14abf15SRobert Mustacchi         LM_BAR_RD64_OFFSET(pdev,BAR_0, offset + addr,&value);
72d14abf15SRobert Mustacchi         DbgMessage(pdev, FATAL, "  ### lm_read_isr64 read address 0x%x value=0x%x 0x%x\n",addr,(u32_t)(value>>32),(u32_t)value);
73d14abf15SRobert Mustacchi         DbgBreakIf(value == 0xffffffffffffffffULL);
74d14abf15SRobert Mustacchi         res |= value;
75d14abf15SRobert Mustacchi         /* Do one more iteration if we got the value for a legitimate "all ones" */
76d14abf15SRobert Mustacchi     } while (value == 0xefffffffffffffffULL);
77d14abf15SRobert Mustacchi     DbgMessage(pdev, FATAL, "  ### lm_read_isr64 res=0x%x 0x%x\n",(u32_t)(res>>32),(u32_t)res);
78d14abf15SRobert Mustacchi     return res;
79d14abf15SRobert Mustacchi }
80d14abf15SRobert Mustacchi 
lm_igutest_get_isr32(struct _lm_device_t * pdev)81d14abf15SRobert Mustacchi u64_t lm_igutest_get_isr32(struct _lm_device_t *pdev)
82d14abf15SRobert Mustacchi {
83d14abf15SRobert Mustacchi     u64_t intr_status = 0;
84d14abf15SRobert Mustacchi     intr_status = ((u64_t)lm_read_isr32(pdev,8 * IGU_REG_SISR_MDPC_WMASK_MSB_UPPER) << 32) |
85d14abf15SRobert Mustacchi         lm_read_isr32(pdev,8 * IGU_REG_SISR_MDPC_WMASK_LSB_UPPER);
86d14abf15SRobert Mustacchi     return intr_status;
87d14abf15SRobert Mustacchi }
88d14abf15SRobert Mustacchi 
89d14abf15SRobert Mustacchi u64_t
lm_igutest_get_isr64(struct _lm_device_t * pdev)90d14abf15SRobert Mustacchi lm_igutest_get_isr64(struct _lm_device_t *pdev)
91d14abf15SRobert Mustacchi {
92d14abf15SRobert Mustacchi     return lm_read_isr64(pdev,8 * IGU_REG_SISR_MDPC_WMASK_UPPER);
93d14abf15SRobert Mustacchi }
94d14abf15SRobert Mustacchi 
95d14abf15SRobert Mustacchi lm_interrupt_status_t
lm_get_interrupt_status_wo_mask(lm_device_t * pdev)96d14abf15SRobert Mustacchi lm_get_interrupt_status_wo_mask(
97d14abf15SRobert Mustacchi     lm_device_t *pdev)
98d14abf15SRobert Mustacchi {
99d14abf15SRobert Mustacchi     lm_interrupt_status_t intr_status = 0;
100d14abf15SRobert Mustacchi     if (INTR_BLK_REQUIRE_CMD_CTRL(pdev)) {
101d14abf15SRobert Mustacchi         /* This is IGU GRC Access... need to write ctrl and then read data */
102d14abf15SRobert Mustacchi         REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WOMASK(pdev));
103d14abf15SRobert Mustacchi     }
104d14abf15SRobert Mustacchi     intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WOMASK(pdev));
105d14abf15SRobert Mustacchi     /* if above, need to read 64 bits from IGU...and take care of all-ones */
106d14abf15SRobert Mustacchi     ASSERT_STATIC(MAX_RSS_CHAINS <= 32);
107d14abf15SRobert Mustacchi     return intr_status;
108d14abf15SRobert Mustacchi }
109d14abf15SRobert Mustacchi 
110d14abf15SRobert Mustacchi lm_interrupt_status_t
lm_get_interrupt_status(lm_device_t * pdev)111d14abf15SRobert Mustacchi lm_get_interrupt_status(
112d14abf15SRobert Mustacchi     lm_device_t *pdev)
113d14abf15SRobert Mustacchi {
114d14abf15SRobert Mustacchi     lm_interrupt_status_t intr_status = 0;
115d14abf15SRobert Mustacchi 
116d14abf15SRobert Mustacchi     if (INTR_BLK_REQUIRE_CMD_CTRL(pdev)) {
117d14abf15SRobert Mustacchi         /* This is IGU GRC Access... need to write ctrl and then read data */
118d14abf15SRobert Mustacchi         REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WMASK(pdev));
119d14abf15SRobert Mustacchi     }
120d14abf15SRobert Mustacchi     intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WMASK(pdev));
121d14abf15SRobert Mustacchi     /* if above, need to read 64 bits from IGU...and take care of all-ones */
122d14abf15SRobert Mustacchi     ASSERT_STATIC(MAX_RSS_CHAINS <= 32);
123d14abf15SRobert Mustacchi     return intr_status;
124d14abf15SRobert Mustacchi } /* lm_get_interrupt_status */
125d14abf15SRobert Mustacchi 
lm_set_interrupt_moderation(struct _lm_device_t * pdev,u8_t is_enable)126d14abf15SRobert Mustacchi lm_status_t lm_set_interrupt_moderation(struct _lm_device_t *pdev, u8_t is_enable)
127d14abf15SRobert Mustacchi {
128d14abf15SRobert Mustacchi     lm_status_t lm_status = LM_STATUS_SUCCESS;
129d14abf15SRobert Mustacchi     u8_t            sb_id      = 0 ;
130d14abf15SRobert Mustacchi 
131d14abf15SRobert Mustacchi     pdev->params.int_coalesing_mode_disabled_by_ndis = !is_enable;
132d14abf15SRobert Mustacchi     if (pdev->params.int_coalesing_mode == LM_INT_COAL_NONE) {
133d14abf15SRobert Mustacchi         DbgMessage(pdev, WARN, "HC is not supported (disabled) in driver\n");
134d14abf15SRobert Mustacchi         return LM_STATUS_SUCCESS;
135d14abf15SRobert Mustacchi     }
136*9b622488SToomas Soome     if (IS_PFDEV(pdev))
137d14abf15SRobert Mustacchi     {
138d14abf15SRobert Mustacchi         LM_FOREACH_SB_ID(pdev, sb_id)
139d14abf15SRobert Mustacchi         {
140d14abf15SRobert Mustacchi             if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_TOE_RX_CQ_CONS, is_enable)) != LM_STATUS_SUCCESS)
141d14abf15SRobert Mustacchi                 break;
142d14abf15SRobert Mustacchi             if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_TOE_TX_CQ_CONS, is_enable)) != LM_STATUS_SUCCESS)
143d14abf15SRobert Mustacchi                 break;
144d14abf15SRobert Mustacchi             if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_RX_CQ_CONS, is_enable)) != LM_STATUS_SUCCESS)
145d14abf15SRobert Mustacchi                 break;
146d14abf15SRobert Mustacchi             if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_TX_CQ_CONS_COS0, is_enable)) != LM_STATUS_SUCCESS)
147d14abf15SRobert Mustacchi                 break;
148d14abf15SRobert Mustacchi             if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_TX_CQ_CONS_COS1, is_enable)) != LM_STATUS_SUCCESS)
149d14abf15SRobert Mustacchi                 break;
150d14abf15SRobert Mustacchi             if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_TX_CQ_CONS_COS2, is_enable)) != LM_STATUS_SUCCESS)
151d14abf15SRobert Mustacchi                 break;
152*9b622488SToomas Soome 
153d14abf15SRobert Mustacchi         }
154d14abf15SRobert Mustacchi     }
155d14abf15SRobert Mustacchi 
156d14abf15SRobert Mustacchi     return lm_status;
157d14abf15SRobert Mustacchi }
158d14abf15SRobert Mustacchi 
lm_set_igu_tmode(struct _lm_device_t * pdev,u8_t tmode)159d14abf15SRobert Mustacchi void lm_set_igu_tmode(struct _lm_device_t *pdev, u8_t tmode)
160d14abf15SRobert Mustacchi {
161d14abf15SRobert Mustacchi     pdev->vars.is_igu_test_mode = tmode;
162d14abf15SRobert Mustacchi }
163d14abf15SRobert Mustacchi 
lm_get_igu_tmode(struct _lm_device_t * pdev)164d14abf15SRobert Mustacchi u8_t lm_get_igu_tmode(struct _lm_device_t *pdev)
165d14abf15SRobert Mustacchi {
166d14abf15SRobert Mustacchi     return pdev->vars.is_igu_test_mode;
167d14abf15SRobert Mustacchi }
168d14abf15SRobert Mustacchi 
lm_set_interrupt_mode(struct _lm_device_t * pdev,u32_t mode)169d14abf15SRobert Mustacchi void lm_set_interrupt_mode(struct _lm_device_t *pdev, u32_t mode)
170d14abf15SRobert Mustacchi {
171d14abf15SRobert Mustacchi     DbgBreakIf(mode > LM_INT_MODE_MIMD);
172d14abf15SRobert Mustacchi     pdev->params.interrupt_mode = mode;
173d14abf15SRobert Mustacchi }
174d14abf15SRobert Mustacchi 
lm_get_interrupt_mode(struct _lm_device_t * pdev)175d14abf15SRobert Mustacchi u32_t lm_get_interrupt_mode(struct _lm_device_t *pdev)
176d14abf15SRobert Mustacchi {
177d14abf15SRobert Mustacchi     return pdev->params.interrupt_mode;
178d14abf15SRobert Mustacchi }
179d14abf15SRobert Mustacchi 
lm_get_num_fp_msix_messages(struct _lm_device_t * pdev)180d14abf15SRobert Mustacchi u8_t lm_get_num_fp_msix_messages(struct _lm_device_t *pdev)
181d14abf15SRobert Mustacchi {
182d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_IGU) {
183d14abf15SRobert Mustacchi         if (pdev->vars.is_igu_test_mode) {
184d14abf15SRobert Mustacchi             DbgMessage(pdev, FATAL, "IGU test mode: returned %d fp-messages\n", pdev->hw_info.intr_blk_info.igu_info.igu_test_sb_cnt + pdev->hw_info.intr_blk_info.igu_info.igu_sb_cnt);
185d14abf15SRobert Mustacchi             return (pdev->hw_info.intr_blk_info.igu_info.igu_test_sb_cnt + pdev->hw_info.intr_blk_info.igu_info.igu_sb_cnt);
186d14abf15SRobert Mustacchi         }
187d14abf15SRobert Mustacchi         return pdev->hw_info.intr_blk_info.igu_info.igu_sb_cnt;
188d14abf15SRobert Mustacchi     } else {
189d14abf15SRobert Mustacchi         return pdev->params.sb_cnt;
190d14abf15SRobert Mustacchi     }
191d14abf15SRobert Mustacchi }
192d14abf15SRobert Mustacchi 
lm_get_base_msix_msg(struct _lm_device_t * pdev)193d14abf15SRobert Mustacchi u8_t lm_get_base_msix_msg(struct _lm_device_t *pdev)
194d14abf15SRobert Mustacchi {
195d14abf15SRobert Mustacchi     if (IS_PFDEV(pdev)) {
196d14abf15SRobert Mustacchi         return 1;
197d14abf15SRobert Mustacchi     } else {
198d14abf15SRobert Mustacchi         return 0;
199d14abf15SRobert Mustacchi     }
200d14abf15SRobert Mustacchi }
201d14abf15SRobert Mustacchi 
lm_has_sp_msix_vector(struct _lm_device_t * pdev)202d14abf15SRobert Mustacchi u8_t lm_has_sp_msix_vector(struct _lm_device_t *pdev)
203d14abf15SRobert Mustacchi {
204d14abf15SRobert Mustacchi     if (IS_PFDEV(pdev)) {
205d14abf15SRobert Mustacchi         return TRUE;
206d14abf15SRobert Mustacchi     } else {
207d14abf15SRobert Mustacchi         return FALSE;
208d14abf15SRobert Mustacchi     }
209d14abf15SRobert Mustacchi }
210d14abf15SRobert Mustacchi 
lm_set_hc_flag(struct _lm_device_t * pdev,u8_t sb_id,u8_t idx,u8_t is_enable)211d14abf15SRobert Mustacchi lm_status_t lm_set_hc_flag(struct _lm_device_t *pdev, u8_t sb_id, u8_t idx, u8_t is_enable)
212d14abf15SRobert Mustacchi {
213d14abf15SRobert Mustacchi     lm_status_t lm_status = LM_STATUS_SUCCESS;
214d14abf15SRobert Mustacchi     struct hc_index_data * hc_index_entry;
215d14abf15SRobert Mustacchi     u8_t fw_sb_id;
216d14abf15SRobert Mustacchi     u8_t notify_fw = FALSE;
217d14abf15SRobert Mustacchi 
218d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
219d14abf15SRobert Mustacchi         hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.index_data + idx;
220d14abf15SRobert Mustacchi     } else {
221d14abf15SRobert Mustacchi         hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.index_data + idx;
222d14abf15SRobert Mustacchi     }
223d14abf15SRobert Mustacchi     if (pdev->params.int_coalesing_mode == LM_INT_COAL_PERIODIC_SYNC) {
224d14abf15SRobert Mustacchi         if (is_enable) {
225d14abf15SRobert Mustacchi             if (!(hc_index_entry->flags & HC_INDEX_DATA_HC_ENABLED) && hc_index_entry->timeout) {
226d14abf15SRobert Mustacchi                 hc_index_entry->flags |= HC_INDEX_DATA_HC_ENABLED;
227d14abf15SRobert Mustacchi                 notify_fw = TRUE;
228d14abf15SRobert Mustacchi             }
229d14abf15SRobert Mustacchi         } else {
230d14abf15SRobert Mustacchi             if (hc_index_entry->flags & HC_INDEX_DATA_HC_ENABLED) {
231d14abf15SRobert Mustacchi                 hc_index_entry->flags &= ~HC_INDEX_DATA_HC_ENABLED;
232d14abf15SRobert Mustacchi                 notify_fw = TRUE;
233d14abf15SRobert Mustacchi             }
234d14abf15SRobert Mustacchi         }
235d14abf15SRobert Mustacchi     }
236d14abf15SRobert Mustacchi     if (notify_fw) {
237d14abf15SRobert Mustacchi         fw_sb_id = LM_FW_SB_ID(pdev, sb_id);
238d14abf15SRobert Mustacchi         if (CHIP_IS_E1x(pdev)) {
239d14abf15SRobert Mustacchi             LM_INTMEM_WRITE8(PFDEV(pdev), (CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id)
240d14abf15SRobert Mustacchi                                            + OFFSETOF(struct hc_status_block_data_e1x, index_data)
241d14abf15SRobert Mustacchi                                            + sizeof(struct hc_index_data)*idx
242d14abf15SRobert Mustacchi                                            + OFFSETOF(struct hc_index_data,flags)),
243d14abf15SRobert Mustacchi                                            hc_index_entry->flags, BAR_CSTRORM_INTMEM);
244d14abf15SRobert Mustacchi         } else {
245d14abf15SRobert Mustacchi             LM_INTMEM_WRITE8(PFDEV(pdev), (CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id)
246d14abf15SRobert Mustacchi                                            + OFFSETOF(struct hc_status_block_data_e2, index_data)
247d14abf15SRobert Mustacchi                                            + sizeof(struct hc_index_data)*idx
248d14abf15SRobert Mustacchi                                            + OFFSETOF(struct hc_index_data,flags)),
249d14abf15SRobert Mustacchi                                            hc_index_entry->flags, BAR_CSTRORM_INTMEM);
250d14abf15SRobert Mustacchi 
251d14abf15SRobert Mustacchi         }
252d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "HC set to %d for SB%d(index%d)\n",is_enable,sb_id,idx);
253d14abf15SRobert Mustacchi     } else {
254d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "HC already set to %d for SB%d(index%d)\n",is_enable,sb_id,idx);
255d14abf15SRobert Mustacchi     }
256d14abf15SRobert Mustacchi 
257d14abf15SRobert Mustacchi     return lm_status;
258d14abf15SRobert Mustacchi }
259d14abf15SRobert Mustacchi 
lm_update_def_hc_indices(lm_device_t * pdev,u8_t dummy_sb_id,u32_t * activity_flg)260d14abf15SRobert Mustacchi void lm_update_def_hc_indices(lm_device_t *pdev, u8_t dummy_sb_id, u32_t *activity_flg)
261d14abf15SRobert Mustacchi {
262d14abf15SRobert Mustacchi     volatile struct hc_sp_status_block * sp_sb          = NULL;
263d14abf15SRobert Mustacchi     volatile struct atten_sp_status_block * attn_sb = NULL;
264d14abf15SRobert Mustacchi     u16_t                             atomic_index   = 0;
265d14abf15SRobert Mustacchi 
266d14abf15SRobert Mustacchi     *activity_flg = 0;
267d14abf15SRobert Mustacchi 
268d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
269d14abf15SRobert Mustacchi 
270d14abf15SRobert Mustacchi 
271d14abf15SRobert Mustacchi     //It's a default status block
272d14abf15SRobert Mustacchi 
273d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "BEFORE update: hc_def_ack:%d, attn_def_ack:%d\n",
274d14abf15SRobert Mustacchi             pdev->vars.hc_def_ack,
275d14abf15SRobert Mustacchi             pdev->vars.attn_def_ack);
276d14abf15SRobert Mustacchi 
277d14abf15SRobert Mustacchi     sp_sb = lm_get_default_status_block(pdev);
278d14abf15SRobert Mustacchi 
279d14abf15SRobert Mustacchi     atomic_index = mm_le16_to_cpu(sp_sb->running_index);
280d14abf15SRobert Mustacchi     if (atomic_index != pdev->vars.hc_def_ack)
281d14abf15SRobert Mustacchi     {
282d14abf15SRobert Mustacchi         pdev->vars.hc_def_ack = atomic_index;
283d14abf15SRobert Mustacchi         (*activity_flg) |= LM_SP_ACTIVE;
284d14abf15SRobert Mustacchi     }
285d14abf15SRobert Mustacchi 
286d14abf15SRobert Mustacchi 
287d14abf15SRobert Mustacchi     attn_sb = lm_get_attention_status_block(pdev);
288d14abf15SRobert Mustacchi 
289d14abf15SRobert Mustacchi     atomic_index = mm_le16_to_cpu(attn_sb->attn_bits_index);
290d14abf15SRobert Mustacchi     if (atomic_index != pdev->vars.attn_def_ack)
291d14abf15SRobert Mustacchi     {
292d14abf15SRobert Mustacchi         pdev->vars.attn_def_ack = atomic_index;
293d14abf15SRobert Mustacchi         (*activity_flg) |= LM_DEF_ATTN_ACTIVE;
294d14abf15SRobert Mustacchi     }
295d14abf15SRobert Mustacchi 
296d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "AFTER update: hc_def_ack:%d, attn_def_ack:%d\n",
297d14abf15SRobert Mustacchi         pdev->vars.hc_def_ack,
298d14abf15SRobert Mustacchi         pdev->vars.attn_def_ack);
299d14abf15SRobert Mustacchi }
300d14abf15SRobert Mustacchi 
lm_update_fp_hc_indices(lm_device_t * pdev,u8_t igu_sb_id,u32_t * activity_flg,u8_t * drv_rss_id)301d14abf15SRobert Mustacchi void lm_update_fp_hc_indices(lm_device_t *pdev, u8_t igu_sb_id, u32_t *activity_flg, u8_t *drv_rss_id)
302d14abf15SRobert Mustacchi {
303d14abf15SRobert Mustacchi     u16_t                                   atomic_index   = 0;
304d14abf15SRobert Mustacchi     u8_t flags;
305d14abf15SRobert Mustacchi     u8_t drv_sb_id;
306d14abf15SRobert Mustacchi 
307d14abf15SRobert Mustacchi     *activity_flg = 0;
308d14abf15SRobert Mustacchi     drv_sb_id = igu_sb_id;
309d14abf15SRobert Mustacchi 
310d14abf15SRobert Mustacchi     DbgBreakIf(!(pdev && (drv_sb_id <= ARRSIZE(pdev->vars.status_blocks_arr))));
311d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "lm_update_hc_indices: inside with sb_idx:%d\n", drv_sb_id);
312d14abf15SRobert Mustacchi 
313d14abf15SRobert Mustacchi     DbgBreakIf(!LM_SB_ID_VALID(pdev, drv_sb_id));
314d14abf15SRobert Mustacchi 
315d14abf15SRobert Mustacchi 
316d14abf15SRobert Mustacchi     flags = lm_query_storm_intr(pdev, igu_sb_id, &drv_sb_id);
317d14abf15SRobert Mustacchi 
318d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "BEFORE update: c_hc_ack:%d\n", pdev->vars.c_hc_ack[drv_sb_id]);
319d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "BEFORE update: u_hc_ack:%d\n", pdev->vars.u_hc_ack[drv_sb_id]);
320d14abf15SRobert Mustacchi 
321d14abf15SRobert Mustacchi     if (GET_FLAGS(flags, CSTORM_INTR_FLAG)) {
322d14abf15SRobert Mustacchi         atomic_index = lm_get_sb_running_index(pdev, drv_sb_id, SM_TX_ID);
323d14abf15SRobert Mustacchi 
324d14abf15SRobert Mustacchi         if (atomic_index != pdev->vars.c_hc_ack[drv_sb_id])
325d14abf15SRobert Mustacchi         {
326d14abf15SRobert Mustacchi             pdev->vars.c_hc_ack[drv_sb_id] = atomic_index;
327d14abf15SRobert Mustacchi             (*activity_flg) |= LM_NON_DEF_CSTORM_ACTIVE;
328d14abf15SRobert Mustacchi         }
329d14abf15SRobert Mustacchi     }
330d14abf15SRobert Mustacchi 
331d14abf15SRobert Mustacchi     if (GET_FLAGS(flags, USTORM_INTR_FLAG)) {
332d14abf15SRobert Mustacchi         atomic_index = lm_get_sb_running_index(pdev, drv_sb_id, SM_RX_ID);
333d14abf15SRobert Mustacchi 
334d14abf15SRobert Mustacchi         if (atomic_index != pdev->vars.u_hc_ack[drv_sb_id])
335d14abf15SRobert Mustacchi         {
336d14abf15SRobert Mustacchi             pdev->vars.u_hc_ack[drv_sb_id] = atomic_index;
337d14abf15SRobert Mustacchi             (*activity_flg) |= LM_NON_DEF_USTORM_ACTIVE;
338d14abf15SRobert Mustacchi             if ((pdev->params.ndsb_type == LM_SINGLE_SM) || (pdev->params.ndsb_type == LM_DOUBLE_SM_SINGLE_IGU)) {
339d14abf15SRobert Mustacchi                 (*activity_flg) |= LM_NON_DEF_CSTORM_ACTIVE;
340d14abf15SRobert Mustacchi             }
341d14abf15SRobert Mustacchi         }
342d14abf15SRobert Mustacchi     }
343d14abf15SRobert Mustacchi 
344d14abf15SRobert Mustacchi 
345d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "AFTER update: c_hc_ack:%d\n", pdev->vars.c_hc_ack[drv_sb_id]);
346d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "AFTER update: u_hc_ack:%d\n", pdev->vars.u_hc_ack[drv_sb_id]);
347d14abf15SRobert Mustacchi 
348d14abf15SRobert Mustacchi     /* Fixme - doesn't have to be... */
349d14abf15SRobert Mustacchi     *drv_rss_id = drv_sb_id;
350d14abf15SRobert Mustacchi }
351d14abf15SRobert Mustacchi 
lm_is_def_sb_updated(lm_device_t * pdev)352d14abf15SRobert Mustacchi u8_t lm_is_def_sb_updated(lm_device_t *pdev)
353d14abf15SRobert Mustacchi {
354d14abf15SRobert Mustacchi     volatile struct hc_sp_status_block * sp_sb                = NULL;
355d14abf15SRobert Mustacchi     volatile struct atten_sp_status_block * attn_sb           = NULL;
356d14abf15SRobert Mustacchi     u8_t result                                            = FALSE;
357d14abf15SRobert Mustacchi     u16_t hw_sb_idx                                        = 0;
358d14abf15SRobert Mustacchi 
359d14abf15SRobert Mustacchi     DbgBreakIfFastPath(!pdev);
360d14abf15SRobert Mustacchi     if (!pdev || IS_VFDEV(pdev))
361d14abf15SRobert Mustacchi     {
362d14abf15SRobert Mustacchi         return FALSE;
363d14abf15SRobert Mustacchi     }
364d14abf15SRobert Mustacchi 
365d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "lm_is_def_sb_updated() inside!\n");
366d14abf15SRobert Mustacchi 
367d14abf15SRobert Mustacchi     sp_sb = lm_get_default_status_block(pdev);
368d14abf15SRobert Mustacchi     //it is legit that only a subgroup of the storms may change between our local copy.
369d14abf15SRobert Mustacchi     //at least one storm index change implies that we have work to do on this sb
370d14abf15SRobert Mustacchi     hw_sb_idx = mm_le16_to_cpu(sp_sb->running_index);
371d14abf15SRobert Mustacchi     if (hw_sb_idx != pdev->vars.hc_def_ack)
372d14abf15SRobert Mustacchi     {
373d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "lm_is_sb_updated: sp running_index:%d, hc_def_ack:%d\n",
374d14abf15SRobert Mustacchi                     hw_sb_idx, pdev->vars.hc_def_ack);
375d14abf15SRobert Mustacchi 
376d14abf15SRobert Mustacchi         result     = TRUE;
377d14abf15SRobert Mustacchi     }
378d14abf15SRobert Mustacchi 
379d14abf15SRobert Mustacchi     attn_sb = lm_get_attention_status_block(pdev);
380d14abf15SRobert Mustacchi     hw_sb_idx = mm_le16_to_cpu(attn_sb->attn_bits_index);
381d14abf15SRobert Mustacchi     if (hw_sb_idx != pdev->vars.attn_def_ack)
382d14abf15SRobert Mustacchi     {
383d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "lm_is_sb_updated: def.attn_bits_index:%d attn_def_ack:%d\n",
384d14abf15SRobert Mustacchi                     hw_sb_idx, pdev->vars.attn_def_ack);
385d14abf15SRobert Mustacchi 
386d14abf15SRobert Mustacchi         result = TRUE;
387d14abf15SRobert Mustacchi     }
388d14abf15SRobert Mustacchi 
389d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "lm_is_def_sb_updated:  result:%s\n", result? "TRUE" : "FALSE");
390d14abf15SRobert Mustacchi 
391d14abf15SRobert Mustacchi     return result;
392d14abf15SRobert Mustacchi }
393d14abf15SRobert Mustacchi 
394d14abf15SRobert Mustacchi 
395d14abf15SRobert Mustacchi 
396d14abf15SRobert Mustacchi 
lm_handle_igu_sb_id(lm_device_t * pdev,u8_t igu_sb_id,u8_t * rx_rss_id,u8_t * tx_rss_id)397d14abf15SRobert Mustacchi u8_t lm_handle_igu_sb_id(lm_device_t *pdev, u8_t igu_sb_id, u8_t *rx_rss_id, u8_t *tx_rss_id)
398d14abf15SRobert Mustacchi {
399d14abf15SRobert Mustacchi     u16_t atomic_index = 0;
400d14abf15SRobert Mustacchi     u8_t  drv_sb_id = 0;
401d14abf15SRobert Mustacchi     u8_t  flags = 0;
402d14abf15SRobert Mustacchi     u8_t  drv_rss_id = 0;
403d14abf15SRobert Mustacchi 
404d14abf15SRobert Mustacchi     drv_sb_id = igu_sb_id;
405d14abf15SRobert Mustacchi 
406d14abf15SRobert Mustacchi     if ((INTR_BLK_TYPE(pdev) == INTR_BLK_HC) || (IGU_U_NDSB_OFFSET(pdev) == 0)) {
407d14abf15SRobert Mustacchi         /* One Segment Per u/c */
408d14abf15SRobert Mustacchi         SET_FLAGS(flags, USTORM_INTR_FLAG);
409d14abf15SRobert Mustacchi         SET_FLAGS(flags, CSTORM_INTR_FLAG);
410d14abf15SRobert Mustacchi     } else {
411d14abf15SRobert Mustacchi         if (drv_sb_id >= IGU_U_NDSB_OFFSET(pdev)) {
412d14abf15SRobert Mustacchi             drv_sb_id -= IGU_U_NDSB_OFFSET(pdev);
413d14abf15SRobert Mustacchi             SET_FLAGS(flags, USTORM_INTR_FLAG);
414d14abf15SRobert Mustacchi             //DbgMessage(pdev, FATAL, "Ustorm drv_sb_id=%d\n", drv_sb_id);
415d14abf15SRobert Mustacchi         } else {
416d14abf15SRobert Mustacchi             SET_FLAGS(flags, CSTORM_INTR_FLAG);
417d14abf15SRobert Mustacchi             //DbgMessage(pdev, FATAL, "Cstorm drv_sb_id=%d\n", drv_sb_id);
418d14abf15SRobert Mustacchi         }
419d14abf15SRobert Mustacchi     }
420d14abf15SRobert Mustacchi 
421d14abf15SRobert Mustacchi     if (GET_FLAGS(flags, USTORM_INTR_FLAG)) {
422d14abf15SRobert Mustacchi         atomic_index = lm_get_sb_running_index(pdev, drv_sb_id, SM_RX_ID);
423d14abf15SRobert Mustacchi 
424d14abf15SRobert Mustacchi         if (atomic_index != pdev->vars.u_hc_ack[drv_sb_id]) {
425d14abf15SRobert Mustacchi             pdev->vars.u_hc_ack[drv_sb_id] = atomic_index;
426d14abf15SRobert Mustacchi         }
427d14abf15SRobert Mustacchi 
428d14abf15SRobert Mustacchi         drv_rss_id = drv_sb_id; /* FIXME: doesn't have to be... */
429d14abf15SRobert Mustacchi         //Check for Rx completions
430d14abf15SRobert Mustacchi         if (lm_is_rx_completion(pdev, drv_rss_id))
431d14abf15SRobert Mustacchi         {
432d14abf15SRobert Mustacchi             //DbgMessage(pdev, FATAL, "RX_completion=%d\n", drv_rss_id);
433d14abf15SRobert Mustacchi             SET_FLAGS(flags, SERV_RX_INTR_FLAG);
434d14abf15SRobert Mustacchi         }
435d14abf15SRobert Mustacchi 
436d14abf15SRobert Mustacchi #ifdef INCLUDE_L4_SUPPORT
437d14abf15SRobert Mustacchi         //Check for L4 Rx completions
438d14abf15SRobert Mustacchi         if (lm_toe_is_rx_completion(pdev, drv_rss_id))
439d14abf15SRobert Mustacchi         {
440d14abf15SRobert Mustacchi             lm_toe_service_rx_intr(pdev, drv_rss_id);
441d14abf15SRobert Mustacchi         }
442d14abf15SRobert Mustacchi #endif
443d14abf15SRobert Mustacchi     }
444d14abf15SRobert Mustacchi     if (GET_FLAGS(flags, CSTORM_INTR_FLAG)) {
445d14abf15SRobert Mustacchi         if (IGU_U_NDSB_OFFSET(pdev)) {
446d14abf15SRobert Mustacchi             atomic_index = lm_get_sb_running_index(pdev, drv_sb_id, SM_TX_ID);
447d14abf15SRobert Mustacchi 
448d14abf15SRobert Mustacchi             if (atomic_index != pdev->vars.c_hc_ack[drv_sb_id]) {
449d14abf15SRobert Mustacchi                 pdev->vars.c_hc_ack[drv_sb_id] = atomic_index;
450d14abf15SRobert Mustacchi             }
451d14abf15SRobert Mustacchi         }
452d14abf15SRobert Mustacchi         drv_rss_id = drv_sb_id; /* FIXME: doesn't have to be... */
453d14abf15SRobert Mustacchi         //Check for Tx completions
454d14abf15SRobert Mustacchi         if (lm_is_tx_completion(pdev, drv_rss_id))
455d14abf15SRobert Mustacchi         {
456d14abf15SRobert Mustacchi             //DbgMessage(pdev, FATAL, "TX_completion=%d\n", drv_rss_id);
457d14abf15SRobert Mustacchi             SET_FLAGS(flags, SERV_TX_INTR_FLAG);
458d14abf15SRobert Mustacchi         }
459d14abf15SRobert Mustacchi 
460d14abf15SRobert Mustacchi 
461d14abf15SRobert Mustacchi #ifdef INCLUDE_L4_SUPPORT
462d14abf15SRobert Mustacchi         //Check for L4 Tx completions
463d14abf15SRobert Mustacchi         if (lm_toe_is_tx_completion(pdev, drv_rss_id))
464d14abf15SRobert Mustacchi         {
465d14abf15SRobert Mustacchi             lm_toe_service_tx_intr(pdev, drv_rss_id);
466d14abf15SRobert Mustacchi         }
467d14abf15SRobert Mustacchi #endif
468d14abf15SRobert Mustacchi     }
469d14abf15SRobert Mustacchi     *rx_rss_id = drv_rss_id;
470d14abf15SRobert Mustacchi     *tx_rss_id = drv_rss_id;
471d14abf15SRobert Mustacchi 
472d14abf15SRobert Mustacchi     return flags;
473d14abf15SRobert Mustacchi }
474d14abf15SRobert Mustacchi 
475d14abf15SRobert Mustacchi 
lm_get_e2_status_block(lm_device_t * pdev,u8_t rss_id)476d14abf15SRobert Mustacchi volatile struct host_hc_status_block_e2 * lm_get_e2_status_block(lm_device_t *pdev, u8_t rss_id)
477d14abf15SRobert Mustacchi {
478d14abf15SRobert Mustacchi     return pdev->vars.status_blocks_arr[rss_id].host_hc_status_block.e2_sb;
479d14abf15SRobert Mustacchi }
480d14abf15SRobert Mustacchi 
lm_get_e1x_status_block(lm_device_t * pdev,u8_t rss_id)481d14abf15SRobert Mustacchi volatile struct host_hc_status_block_e1x * lm_get_e1x_status_block(lm_device_t *pdev, u8_t rss_id)
482d14abf15SRobert Mustacchi {
483d14abf15SRobert Mustacchi     return pdev->vars.status_blocks_arr[rss_id].host_hc_status_block.e1x_sb;
484d14abf15SRobert Mustacchi }
485d14abf15SRobert Mustacchi 
lm_get_default_status_block(lm_device_t * pdev)486d14abf15SRobert Mustacchi volatile struct hc_sp_status_block * lm_get_default_status_block(lm_device_t *pdev)
487d14abf15SRobert Mustacchi {
488d14abf15SRobert Mustacchi     return &pdev->vars.gen_sp_status_block.hc_sp_status_blk->sp_sb;
489d14abf15SRobert Mustacchi }
490d14abf15SRobert Mustacchi 
lm_get_attention_status_block(lm_device_t * pdev)491d14abf15SRobert Mustacchi volatile struct atten_sp_status_block * lm_get_attention_status_block(lm_device_t *pdev)
492d14abf15SRobert Mustacchi {
493d14abf15SRobert Mustacchi     return &pdev->vars.gen_sp_status_block.hc_sp_status_blk->atten_status_block;
494d14abf15SRobert Mustacchi }
495d14abf15SRobert Mustacchi 
496d14abf15SRobert Mustacchi 
print_sb_info(lm_device_t * pdev)497d14abf15SRobert Mustacchi void print_sb_info(lm_device_t *pdev)
498d14abf15SRobert Mustacchi {
499d14abf15SRobert Mustacchi #if 0
500d14abf15SRobert Mustacchi     u8_t index                                    = 0;
501d14abf15SRobert Mustacchi     volatile struct host_status_block *rss_sb     = NULL;
502d14abf15SRobert Mustacchi 
503d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
504d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "print_sb_info() inside!\n");
505d14abf15SRobert Mustacchi     //print info of all non-default status blocks
506d14abf15SRobert Mustacchi     for(index=0; index < MAX_RSS_CHAINS; index++)
507d14abf15SRobert Mustacchi     {
508d14abf15SRobert Mustacchi         rss_sb = lm_get_status_block(pdev, index);
509d14abf15SRobert Mustacchi 
510d14abf15SRobert Mustacchi         DbgBreakIf(!rss_sb);
511d14abf15SRobert Mustacchi         DbgBreakIf(*(LM_RCQ(pdev, index).
512d14abf15SRobert Mustacchi              hw_con_idx_ptr) != rss_sb->u_status_block.index_values[HC_INDEX_U_ETH_RX_CQ_CONS]);
513d14abf15SRobert Mustacchi         DbgBreakIf(*(LM_TXQ(pdev, index).hw_con_idx_ptr) != rss_sb->c_status_block.index_values[HC_INDEX_C_ETH_TX_CQ_CONS]);
514d14abf15SRobert Mustacchi 
515d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "rss sb #%d: u_new_cons:%d, c_new_cons:%d, c_status idx:%d, c_sbID:%d, u_status idx:%d, u_sbID:%d\n",
516d14abf15SRobert Mustacchi             index,
517d14abf15SRobert Mustacchi             rss_sb->u_status_block.index_values[HC_INDEX_U_ETH_RX_CQ_CONS],
518d14abf15SRobert Mustacchi             rss_sb->c_status_block.index_values[HC_INDEX_C_ETH_TX_CQ_CONS],
519d14abf15SRobert Mustacchi             rss_sb->c_status_block.status_block_index,
520d14abf15SRobert Mustacchi             rss_sb->c_status_block.status_block_id,
521d14abf15SRobert Mustacchi             rss_sb->u_status_block.status_block_index,
522d14abf15SRobert Mustacchi             rss_sb->u_status_block.status_block_id);
523d14abf15SRobert Mustacchi 
524d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "____________________________________________________________\n");
525d14abf15SRobert Mustacchi     }
526d14abf15SRobert Mustacchi     //print info of the default status block
527d14abf15SRobert Mustacchi     DbgBreakIf(pdev->vars.gen_sp_status_block.hc_sp_status_blk == NULL);
528d14abf15SRobert Mustacchi 
529d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "sp sb: c_status idx:%d, c_sbID:%d\n",
530d14abf15SRobert Mustacchi         pdev->vars.gen_sp_status_block.hc_sp_status_blk->sp_sb.running_index, pdev->vars.gen_sp_status_block.sb_data.igu_sb_id);
531d14abf15SRobert Mustacchi 
532d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "____________________________________________________________\n");
533d14abf15SRobert Mustacchi #endif
534d14abf15SRobert Mustacchi }
535d14abf15SRobert Mustacchi 
536d14abf15SRobert Mustacchi /**
537d14abf15SRobert Mustacchi  * This function sets all the status-block ack values back to
538d14abf15SRobert Mustacchi  * zero. Must be called BEFORE initializing the igu + before
539d14abf15SRobert Mustacchi  * initializing status-blocks.
540d14abf15SRobert Mustacchi  *
541d14abf15SRobert Mustacchi  * @param pdev
542d14abf15SRobert Mustacchi  */
lm_reset_sb_ack_values(struct _lm_device_t * pdev)543d14abf15SRobert Mustacchi void lm_reset_sb_ack_values(struct _lm_device_t *pdev)
544d14abf15SRobert Mustacchi {
545d14abf15SRobert Mustacchi     //re-initialize all the local copy indices of sbs for load/unload scenarios
546d14abf15SRobert Mustacchi     pdev->vars.hc_def_ack = 0;
547d14abf15SRobert Mustacchi 
548d14abf15SRobert Mustacchi     //init attn state
549d14abf15SRobert Mustacchi     pdev->vars.attn_state = 0;
550d14abf15SRobert Mustacchi 
551d14abf15SRobert Mustacchi     pdev->vars.attn_def_ack = 0;
552d14abf15SRobert Mustacchi 
553d14abf15SRobert Mustacchi     mm_memset(pdev->vars.c_hc_ack, 0, sizeof(pdev->vars.c_hc_ack));
554d14abf15SRobert Mustacchi     mm_memset(pdev->vars.u_hc_ack, 0, sizeof(pdev->vars.u_hc_ack));
555d14abf15SRobert Mustacchi }
556d14abf15SRobert Mustacchi 
init_hc_attn_status_block(struct _lm_device_t * pdev,u8_t sb_id,lm_address_t * host_sb_addr)557d14abf15SRobert Mustacchi static void init_hc_attn_status_block(struct _lm_device_t *pdev,
558d14abf15SRobert Mustacchi                               u8_t  sb_id,
559d14abf15SRobert Mustacchi                               lm_address_t *host_sb_addr)
560d14abf15SRobert Mustacchi {
561d14abf15SRobert Mustacchi     volatile struct atten_sp_status_block * attention_sb = NULL;
562d14abf15SRobert Mustacchi     //give the IGU the status block number(ID) of attention bits section.
563d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
564d14abf15SRobert Mustacchi 
565d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "init_status_block: host_sb_addr_low:0x%x; host_sb_addr_low:0x%x\n",
566d14abf15SRobert Mustacchi                     host_sb_addr->as_u32.low, host_sb_addr->as_u32.high);
567d14abf15SRobert Mustacchi     attention_sb = lm_get_attention_status_block(pdev);
568d14abf15SRobert Mustacchi     attention_sb->status_block_id = sb_id;
569d14abf15SRobert Mustacchi     //write to IGU the physical address where the attention bits lie
570d14abf15SRobert Mustacchi     REG_WR(pdev,  HC_REG_ATTN_MSG0_ADDR_L + 8*PORT_ID(pdev), host_sb_addr->as_u32.low);
571d14abf15SRobert Mustacchi     REG_WR(pdev,  HC_REG_ATTN_MSG0_ADDR_H + 8*PORT_ID(pdev), host_sb_addr->as_u32.high);
572d14abf15SRobert Mustacchi }
573d14abf15SRobert Mustacchi 
init_igu_attn_status_block(struct _lm_device_t * pdev,lm_address_t * host_sb_addr)574d14abf15SRobert Mustacchi static void init_igu_attn_status_block(
575d14abf15SRobert Mustacchi     struct _lm_device_t *pdev,
576d14abf15SRobert Mustacchi     lm_address_t *host_sb_addr)
577d14abf15SRobert Mustacchi {
578d14abf15SRobert Mustacchi 
579d14abf15SRobert Mustacchi     //write to IGU the physical address where the attention bits lie
580d14abf15SRobert Mustacchi     REG_WR(pdev,  IGU_REG_ATTN_MSG_ADDR_L, host_sb_addr->as_u32.low);
581d14abf15SRobert Mustacchi     REG_WR(pdev,  IGU_REG_ATTN_MSG_ADDR_H, host_sb_addr->as_u32.high);
582d14abf15SRobert Mustacchi 
583d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "init_attn_igu_status_block: host_sb_addr_low:0x%x; host_sb_addr_low:0x%x\n",
584d14abf15SRobert Mustacchi                 host_sb_addr->as_u32.low, host_sb_addr->as_u32.high);
585d14abf15SRobert Mustacchi 
586d14abf15SRobert Mustacchi 
587d14abf15SRobert Mustacchi }
588d14abf15SRobert Mustacchi 
589d14abf15SRobert Mustacchi 
init_attn_status_block(struct _lm_device_t * pdev,u8_t sb_id,lm_address_t * host_sb_addr)590d14abf15SRobert Mustacchi static void init_attn_status_block(struct _lm_device_t *pdev,
591d14abf15SRobert Mustacchi                               u8_t  sb_id,
592d14abf15SRobert Mustacchi                               lm_address_t *host_sb_addr)
593d14abf15SRobert Mustacchi {
594d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
595d14abf15SRobert Mustacchi         init_hc_attn_status_block(pdev,sb_id,host_sb_addr);
596d14abf15SRobert Mustacchi     } else {
597d14abf15SRobert Mustacchi         init_igu_attn_status_block(pdev, host_sb_addr);
598d14abf15SRobert Mustacchi     }
599d14abf15SRobert Mustacchi }
600d14abf15SRobert Mustacchi 
lm_init_sp_status_block(struct _lm_device_t * pdev)601d14abf15SRobert Mustacchi static void lm_init_sp_status_block(struct _lm_device_t *pdev)
602d14abf15SRobert Mustacchi {
603d14abf15SRobert Mustacchi     lm_address_t    sb_phy_addr;
604d14abf15SRobert Mustacchi     u8_t igu_sp_sb_index; /* igu Status Block constant identifier (0-135) */
605d14abf15SRobert Mustacchi     u8_t igu_seg_id;
606d14abf15SRobert Mustacchi     u8_t func;
607d14abf15SRobert Mustacchi     u8_t i;
608d14abf15SRobert Mustacchi 
609d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
610d14abf15SRobert Mustacchi     DbgBreakIf(IS_VFDEV(pdev));
611d14abf15SRobert Mustacchi 
612d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_SP_STATUS_BLOCK_SIZE % 4) != 0);
613d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_SP_STATUS_BLOCK_DATA_SIZE % 4) != 0);
614d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_SP_SYNC_BLOCK_SIZE % 4) != 0);
615d14abf15SRobert Mustacchi     func = FUNC_ID(pdev);
616d14abf15SRobert Mustacchi 
617d14abf15SRobert Mustacchi     if ((INTR_BLK_TYPE(pdev) == INTR_BLK_IGU) && (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_NORM) ) {
618d14abf15SRobert Mustacchi         igu_sp_sb_index = IGU_DSB_ID(pdev);
619d14abf15SRobert Mustacchi         igu_seg_id = IGU_SEG_ACCESS_DEF;
620d14abf15SRobert Mustacchi     } else {
621d14abf15SRobert Mustacchi         igu_sp_sb_index = DEF_STATUS_BLOCK_IGU_INDEX;
622d14abf15SRobert Mustacchi         igu_seg_id = HC_SEG_ACCESS_DEF;
623d14abf15SRobert Mustacchi     }
624d14abf15SRobert Mustacchi 
625d14abf15SRobert Mustacchi     sb_phy_addr = pdev->vars.gen_sp_status_block.blk_phy_address;
626d14abf15SRobert Mustacchi 
627d14abf15SRobert Mustacchi     init_attn_status_block(pdev, igu_sp_sb_index, &sb_phy_addr);
628d14abf15SRobert Mustacchi 
629d14abf15SRobert Mustacchi     LM_INC64(&sb_phy_addr, OFFSETOF(struct host_sp_status_block, sp_sb));
630d14abf15SRobert Mustacchi 
631d14abf15SRobert Mustacchi     /* CQ#46240: Disable the function in the status-block data before nullifying sync-line + status-block */
632d14abf15SRobert Mustacchi     LM_INTMEM_WRITE8(pdev, CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
633d14abf15SRobert Mustacchi                      SB_DISABLED, BAR_CSTRORM_INTMEM);
634d14abf15SRobert Mustacchi 
635d14abf15SRobert Mustacchi     REG_WR_DMAE_LEN_ZERO(pdev, CSEM_REG_FAST_MEMORY + CSTORM_SP_SYNC_BLOCK_OFFSET(func), CSTORM_SP_SYNC_BLOCK_SIZE/4);
636d14abf15SRobert Mustacchi     REG_WR_DMAE_LEN_ZERO(pdev, CSEM_REG_FAST_MEMORY + CSTORM_SP_STATUS_BLOCK_OFFSET(func), CSTORM_SP_STATUS_BLOCK_SIZE/4);
637d14abf15SRobert Mustacchi 
638d14abf15SRobert Mustacchi 
639d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.host_sb_addr.lo = sb_phy_addr.as_u32.low;
640d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.host_sb_addr.hi = sb_phy_addr.as_u32.high;
641d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.igu_sb_id = igu_sp_sb_index;
642d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.igu_seg_id = igu_seg_id;
643d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.p_func.pf_id = func;
644d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.p_func.vnic_id = VNIC_ID(pdev);
645d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.p_func.vf_id = 0xff;
646d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.p_func.vf_valid = FALSE;
647d14abf15SRobert Mustacchi     pdev->vars.gen_sp_status_block.sb_data.state = SB_ENABLED;
648d14abf15SRobert Mustacchi 
649d14abf15SRobert Mustacchi     for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32_t); i++) {
650d14abf15SRobert Mustacchi         LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + i*sizeof(u32_t), *((u32_t*)&pdev->vars.gen_sp_status_block.sb_data + i), BAR_CSTRORM_INTMEM);
651d14abf15SRobert Mustacchi     }
652d14abf15SRobert Mustacchi 
653d14abf15SRobert Mustacchi 
654d14abf15SRobert Mustacchi }
655d14abf15SRobert Mustacchi 
656*9b622488SToomas Soome /* Initialize the whole status blocks per port - overall: 1 default sb, 16 non-default sbs
657d14abf15SRobert Mustacchi  *
658d14abf15SRobert Mustacchi  * Parameters:
659d14abf15SRobert Mustacchi  * pdev - the LM device which holds the sbs
660d14abf15SRobert Mustacchi  * port - the port number
661d14abf15SRobert Mustacchi  */
init_status_blocks(struct _lm_device_t * pdev)662d14abf15SRobert Mustacchi void init_status_blocks(struct _lm_device_t *pdev)
663d14abf15SRobert Mustacchi {
664d14abf15SRobert Mustacchi     u8_t                                    sb_id        = 0;
665d14abf15SRobert Mustacchi     u8_t                                    port         = PORT_ID(pdev);
666d14abf15SRobert Mustacchi     u8_t                                    group_idx;
667d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "init_status_blocks() inside! func:%d\n",FUNC_ID(pdev));
668d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
669d14abf15SRobert Mustacchi 
670d14abf15SRobert Mustacchi     pdev->vars.num_attn_sig_regs =
671d14abf15SRobert Mustacchi         (CHIP_IS_E1x(pdev))? NUM_ATTN_REGS_E1X : NUM_ATTN_REGS_E2;
672d14abf15SRobert Mustacchi 
673d14abf15SRobert Mustacchi     //Read routing configuration for attn signal output of groups. Currently, only group 0,1,2 are wired.
674d14abf15SRobert Mustacchi     for (group_idx = 0; group_idx < MAX_DYNAMIC_ATTN_GRPS; group_idx++)
675d14abf15SRobert Mustacchi     {
676d14abf15SRobert Mustacchi 
677d14abf15SRobert Mustacchi         //group index
678d14abf15SRobert Mustacchi         pdev->vars.attn_groups_output[group_idx].attn_sig_dword[0] =
679d14abf15SRobert Mustacchi             REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0) + group_idx*16);
680d14abf15SRobert Mustacchi         pdev->vars.attn_groups_output[group_idx].attn_sig_dword[1] =
681d14abf15SRobert Mustacchi             REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0) + group_idx*16);
682d14abf15SRobert Mustacchi         pdev->vars.attn_groups_output[group_idx].attn_sig_dword[2] =
683d14abf15SRobert Mustacchi             REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0) + group_idx*16);
684d14abf15SRobert Mustacchi         pdev->vars.attn_groups_output[group_idx].attn_sig_dword[3] =
685d14abf15SRobert Mustacchi             REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0) + group_idx*16);
686d14abf15SRobert Mustacchi         if (pdev->vars.num_attn_sig_regs == 5) {
687d14abf15SRobert Mustacchi             /* enable5 is separate from the rest of the registers, and therefore the address skip is 4 and not 16 between the different groups */
688d14abf15SRobert Mustacchi             pdev->vars.attn_groups_output[group_idx].attn_sig_dword[4] =
689d14abf15SRobert Mustacchi                 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0) + group_idx*4);
690d14abf15SRobert Mustacchi         } else {
691d14abf15SRobert Mustacchi             pdev->vars.attn_groups_output[group_idx].attn_sig_dword[4] = 0;
692d14abf15SRobert Mustacchi         }
693d14abf15SRobert Mustacchi 
694d14abf15SRobert Mustacchi         DbgMessage(pdev, INFORMi, "lm_handle_deassertion_processing: group %d mask1:0x%x, mask2:0x%x, mask3:0x%x, mask4:0x%x, mask5:0x%x\n",
695d14abf15SRobert Mustacchi                        group_idx,
696d14abf15SRobert Mustacchi                        pdev->vars.attn_groups_output[group_idx].attn_sig_dword[0],
697d14abf15SRobert Mustacchi                        pdev->vars.attn_groups_output[group_idx].attn_sig_dword[1],
698d14abf15SRobert Mustacchi                        pdev->vars.attn_groups_output[group_idx].attn_sig_dword[2],
699d14abf15SRobert Mustacchi                        pdev->vars.attn_groups_output[group_idx].attn_sig_dword[3],
700d14abf15SRobert Mustacchi                        pdev->vars.attn_groups_output[group_idx].attn_sig_dword[4]);
701d14abf15SRobert Mustacchi 
702d14abf15SRobert Mustacchi     }
703d14abf15SRobert Mustacchi     pdev->vars.attn_sig_af_inv_reg_addr[0] =
704d14abf15SRobert Mustacchi         PORT_ID(pdev) ? MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 : MISC_REG_AEU_AFTER_INVERT_1_FUNC_0;
705d14abf15SRobert Mustacchi     pdev->vars.attn_sig_af_inv_reg_addr[1] =
706d14abf15SRobert Mustacchi         PORT_ID(pdev) ? MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 : MISC_REG_AEU_AFTER_INVERT_2_FUNC_0;
707d14abf15SRobert Mustacchi     pdev->vars.attn_sig_af_inv_reg_addr[2] =
708d14abf15SRobert Mustacchi         PORT_ID(pdev) ? MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 : MISC_REG_AEU_AFTER_INVERT_3_FUNC_0;
709d14abf15SRobert Mustacchi     pdev->vars.attn_sig_af_inv_reg_addr[3] =
710d14abf15SRobert Mustacchi         PORT_ID(pdev) ? MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 : MISC_REG_AEU_AFTER_INVERT_4_FUNC_0;
711d14abf15SRobert Mustacchi     pdev->vars.attn_sig_af_inv_reg_addr[4] =
712d14abf15SRobert Mustacchi         PORT_ID(pdev) ? MISC_REG_AEU_AFTER_INVERT_5_FUNC_1 : MISC_REG_AEU_AFTER_INVERT_5_FUNC_0;
713d14abf15SRobert Mustacchi 
714d14abf15SRobert Mustacchi     // init the non-default status blocks
715d14abf15SRobert Mustacchi     LM_FOREACH_SB_ID(pdev, sb_id)
716d14abf15SRobert Mustacchi     {
717d14abf15SRobert Mustacchi         lm_init_non_def_status_block(pdev, sb_id, port);
718d14abf15SRobert Mustacchi     }
719d14abf15SRobert Mustacchi 
720d14abf15SRobert Mustacchi     if (pdev->params.int_coalesing_mode_disabled_by_ndis) {
721d14abf15SRobert Mustacchi         lm_set_interrupt_moderation(pdev, FALSE);
722d14abf15SRobert Mustacchi     }
723d14abf15SRobert Mustacchi     // init the default status block  - composed of 5 parts per storm: Attention bits, Ustorm, Cstorm, Xstorm, Tstorm
724d14abf15SRobert Mustacchi 
725d14abf15SRobert Mustacchi     //Init the attention bits part of the default status block
726d14abf15SRobert Mustacchi     lm_init_sp_status_block(pdev);
727d14abf15SRobert Mustacchi }
728d14abf15SRobert Mustacchi 
729d14abf15SRobert Mustacchi /* set interrupt coalesing parameters.
730d14abf15SRobert Mustacchi    - these settings are derived from user configured interrupt coalesing mode and tx/rx interrupts rate (lm params).
731d14abf15SRobert Mustacchi    - these settings are used for status blocks initialization */
lm_set_int_coal_info(struct _lm_device_t * pdev)732d14abf15SRobert Mustacchi void lm_set_int_coal_info(struct _lm_device_t *pdev)
733d14abf15SRobert Mustacchi {
734d14abf15SRobert Mustacchi     lm_int_coalesing_info* ic           = &pdev->vars.int_coal;
735d14abf15SRobert Mustacchi     u32_t                  rx_coal_usec[HC_USTORM_SB_NUM_INDICES];
736d14abf15SRobert Mustacchi     u32_t                  tx_coal_usec[HC_CSTORM_SB_NUM_INDICES];
737d14abf15SRobert Mustacchi     u32_t                  i            = 0;
738d14abf15SRobert Mustacchi 
739d14abf15SRobert Mustacchi     mm_mem_zero( ic, sizeof(lm_int_coalesing_info) );
740d14abf15SRobert Mustacchi 
741d14abf15SRobert Mustacchi     for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
742d14abf15SRobert Mustacchi         rx_coal_usec[i] = 0;
743d14abf15SRobert Mustacchi     }
744d14abf15SRobert Mustacchi 
745d14abf15SRobert Mustacchi     for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
746d14abf15SRobert Mustacchi         tx_coal_usec[i] = 0;
747d14abf15SRobert Mustacchi     }
748d14abf15SRobert Mustacchi 
749d14abf15SRobert Mustacchi     switch (pdev->params.int_coalesing_mode)
750d14abf15SRobert Mustacchi     {
751d14abf15SRobert Mustacchi     case LM_INT_COAL_PERIODIC_SYNC: /* static periodic sync */
752d14abf15SRobert Mustacchi         for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
753d14abf15SRobert Mustacchi             if (pdev->params.int_per_sec_rx_override)
754d14abf15SRobert Mustacchi                 pdev->params.int_per_sec_rx[i] = pdev->params.int_per_sec_rx_override;
755d14abf15SRobert Mustacchi 
756d14abf15SRobert Mustacchi             DbgMessage(pdev, WARN, "##lm_set_int_coal_info: int_per_sec_rx[%d] = %d\n",i,pdev->params.int_per_sec_rx[i]);
757d14abf15SRobert Mustacchi             if (pdev->params.int_per_sec_rx[i])
758d14abf15SRobert Mustacchi             {
759d14abf15SRobert Mustacchi                 rx_coal_usec[i] = 1000000 / pdev->params.int_per_sec_rx[i];
760d14abf15SRobert Mustacchi             }
761d14abf15SRobert Mustacchi             if(rx_coal_usec[i] > 0x3ff)
762d14abf15SRobert Mustacchi             {
763d14abf15SRobert Mustacchi                 rx_coal_usec[i] = 0x3ff; /* min 1k us, i.e. 1k int per sec */
764d14abf15SRobert Mustacchi             }
765d14abf15SRobert Mustacchi         }
766d14abf15SRobert Mustacchi 
767d14abf15SRobert Mustacchi         for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
768d14abf15SRobert Mustacchi             if (pdev->params.int_per_sec_tx_override)
769d14abf15SRobert Mustacchi                 pdev->params.int_per_sec_tx[i] = pdev->params.int_per_sec_tx_override;
770d14abf15SRobert Mustacchi 
771d14abf15SRobert Mustacchi             DbgMessage(pdev, WARN, "##lm_set_int_coal_info: int_per_sec_tx[%d] = %d\n",i,pdev->params.int_per_sec_tx[i]);
772d14abf15SRobert Mustacchi 
773d14abf15SRobert Mustacchi             if (pdev->params.int_per_sec_tx[i])
774d14abf15SRobert Mustacchi             {
775d14abf15SRobert Mustacchi                 tx_coal_usec[i] = 1000000 / pdev->params.int_per_sec_tx[i];
776d14abf15SRobert Mustacchi             }
777d14abf15SRobert Mustacchi             if(tx_coal_usec[i] > 0x3ff)
778d14abf15SRobert Mustacchi             {
779d14abf15SRobert Mustacchi                 tx_coal_usec[i] = 0x3ff; /* min 1k us, i.e. 1k int per sec */
780d14abf15SRobert Mustacchi             }
781d14abf15SRobert Mustacchi         }
782d14abf15SRobert Mustacchi         break;
783d14abf15SRobert Mustacchi 
784d14abf15SRobert Mustacchi     case LM_INT_COAL_NONE: /* this is the default */
785d14abf15SRobert Mustacchi     default:
786d14abf15SRobert Mustacchi         break;
787d14abf15SRobert Mustacchi     }
788d14abf15SRobert Mustacchi 
789d14abf15SRobert Mustacchi     /* set hc period for c sb for all indices */
790d14abf15SRobert Mustacchi     for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
791d14abf15SRobert Mustacchi         ic->hc_usec_c_sb[i] = tx_coal_usec[i];
792d14abf15SRobert Mustacchi     }
793d14abf15SRobert Mustacchi     /* set hc period for u sb for all indices */
794d14abf15SRobert Mustacchi     for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
795d14abf15SRobert Mustacchi         ic->hc_usec_u_sb[i] = rx_coal_usec[i];
796d14abf15SRobert Mustacchi     }
797d14abf15SRobert Mustacchi 
798d14abf15SRobert Mustacchi #if 0
799d14abf15SRobert Mustacchi     if (pdev->params.l4_fw_dca_enabled) {
800d14abf15SRobert Mustacchi         /* set TOE HC to minimum possible for ustorm */
801d14abf15SRobert Mustacchi         ic->hc_usec_u_sb[HC_INDEX_U_TOE_RX_CQ_CONS] = pdev->params.l4_hc_ustorm_thresh;  /* 12usec */
802d14abf15SRobert Mustacchi     }
803d14abf15SRobert Mustacchi #endif
804d14abf15SRobert Mustacchi 
805*9b622488SToomas Soome     /* by default set hc period for x/t/c/u default sb to NONE.
806d14abf15SRobert Mustacchi       (that was already implicitly done by memset 0 above) */
807d14abf15SRobert Mustacchi 
808d14abf15SRobert Mustacchi 
809d14abf15SRobert Mustacchi     /* set dynamic hc params */
810d14abf15SRobert Mustacchi     for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
811d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout0[i] = (u8_t)pdev->params.hc_timeout0[SM_RX_ID][i];
812d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout1[i] = (u8_t)pdev->params.hc_timeout1[SM_RX_ID][i];
813d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout2[i] = (u8_t)pdev->params.hc_timeout2[SM_RX_ID][i];
814d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout3[i] = (u8_t)pdev->params.hc_timeout3[SM_RX_ID][i];
815d14abf15SRobert Mustacchi     }
816d14abf15SRobert Mustacchi     ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].threshold[0] = pdev->params.hc_threshold0[SM_RX_ID];
817d14abf15SRobert Mustacchi     ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].threshold[1] = pdev->params.hc_threshold1[SM_RX_ID];
818d14abf15SRobert Mustacchi     ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].threshold[2] = pdev->params.hc_threshold2[SM_RX_ID];
819d14abf15SRobert Mustacchi 
820d14abf15SRobert Mustacchi     for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
821d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout0[i] = (u8_t)pdev->params.hc_timeout0[SM_TX_ID][i];
822d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout1[i] = (u8_t)pdev->params.hc_timeout1[SM_TX_ID][i];
823d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout2[i] = (u8_t)pdev->params.hc_timeout2[SM_TX_ID][i];
824d14abf15SRobert Mustacchi         ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout3[i] = (u8_t)pdev->params.hc_timeout3[SM_TX_ID][i];
825d14abf15SRobert Mustacchi     }
826d14abf15SRobert Mustacchi     ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].threshold[0] = pdev->params.hc_threshold0[SM_TX_ID];
827d14abf15SRobert Mustacchi     ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].threshold[1] = pdev->params.hc_threshold1[SM_TX_ID];
828d14abf15SRobert Mustacchi     ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].threshold[2] = pdev->params.hc_threshold2[SM_TX_ID];
829d14abf15SRobert Mustacchi }
830d14abf15SRobert Mustacchi 
831d14abf15SRobert Mustacchi 
832d14abf15SRobert Mustacchi 
lm_setup_ndsb_index(struct _lm_device_t * pdev,u8_t sb_id,u8_t idx,u8_t sm_idx,u8_t timeout,u8_t dhc_enable)833d14abf15SRobert Mustacchi void lm_setup_ndsb_index(struct _lm_device_t *pdev, u8_t sb_id, u8_t idx, u8_t sm_idx, u8_t timeout, u8_t dhc_enable)
834d14abf15SRobert Mustacchi {
835d14abf15SRobert Mustacchi     struct hc_index_data * hc_index_entry;
836d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
837d14abf15SRobert Mustacchi         hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.index_data + idx;
838d14abf15SRobert Mustacchi     } else {
839d14abf15SRobert Mustacchi         hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.index_data + idx;
840d14abf15SRobert Mustacchi     }
841d14abf15SRobert Mustacchi     hc_index_entry->timeout = timeout;
842d14abf15SRobert Mustacchi     hc_index_entry->flags = (sm_idx << HC_INDEX_DATA_SM_ID_SHIFT) & HC_INDEX_DATA_SM_ID;
843d14abf15SRobert Mustacchi     if (timeout) {
844d14abf15SRobert Mustacchi         hc_index_entry->flags |= HC_INDEX_DATA_HC_ENABLED;
845d14abf15SRobert Mustacchi     }
846d14abf15SRobert Mustacchi     if (dhc_enable) {
847d14abf15SRobert Mustacchi         hc_index_entry->flags |= HC_INDEX_DATA_DYNAMIC_HC_ENABLED;
848d14abf15SRobert Mustacchi     }
849d14abf15SRobert Mustacchi }
850d14abf15SRobert Mustacchi 
lm_setup_ndsb_state_machine(struct _lm_device_t * pdev,u8_t sb_id,u8_t sm_id,u8_t igu_sb_id,u8_t igu_seg_id)851d14abf15SRobert Mustacchi void lm_setup_ndsb_state_machine(struct _lm_device_t *pdev, u8_t sb_id, u8_t sm_id, u8_t igu_sb_id, u8_t igu_seg_id)
852d14abf15SRobert Mustacchi {
853d14abf15SRobert Mustacchi     struct hc_status_block_sm  * hc_state_machine;
854d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
855d14abf15SRobert Mustacchi         hc_state_machine = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.state_machine + sm_id;
856d14abf15SRobert Mustacchi     } else {
857d14abf15SRobert Mustacchi         hc_state_machine = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.state_machine + sm_id;
858d14abf15SRobert Mustacchi     }
859d14abf15SRobert Mustacchi 
860d14abf15SRobert Mustacchi     hc_state_machine->igu_sb_id = igu_sb_id;
861d14abf15SRobert Mustacchi     hc_state_machine->igu_seg_id = igu_seg_id;
862d14abf15SRobert Mustacchi     hc_state_machine->timer_value = 0xFF;
863d14abf15SRobert Mustacchi     hc_state_machine->time_to_expire = 0xFFFFFFFF;
864d14abf15SRobert Mustacchi }
865d14abf15SRobert Mustacchi 
866d14abf15SRobert Mustacchi 
867d14abf15SRobert Mustacchi 
lm_int_hc_ack_sb(lm_device_t * pdev,u8_t rss_id,u8_t storm_id,u16_t sb_index,u8_t int_op,u8_t is_update_idx)868d14abf15SRobert Mustacchi void lm_int_hc_ack_sb(lm_device_t *pdev, u8_t rss_id, u8_t storm_id, u16_t sb_index, u8_t int_op, u8_t is_update_idx)
869d14abf15SRobert Mustacchi {
870d14abf15SRobert Mustacchi     struct igu_ack_register hc_data;
871d14abf15SRobert Mustacchi 
872d14abf15SRobert Mustacchi     //this is the result which should be communicated to the driver!
873d14abf15SRobert Mustacchi     u32_t result = 0;
874d14abf15SRobert Mustacchi 
875d14abf15SRobert Mustacchi 
876d14abf15SRobert Mustacchi 
877d14abf15SRobert Mustacchi     //don't forget this
878d14abf15SRobert Mustacchi     hc_data.sb_id_and_flags    = 0;
879d14abf15SRobert Mustacchi     hc_data.status_block_index = 0;
880d14abf15SRobert Mustacchi 
881d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "lm_int_ack_sb() inside! rss_id:%d, sb_index:%d, func_num:%d is_update:%d\n", rss_id, sb_index, FUNC_ID(pdev), is_update_idx);
882d14abf15SRobert Mustacchi 
883d14abf15SRobert Mustacchi     hc_data.sb_id_and_flags   |= (0xffffffff & (int_op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
884d14abf15SRobert Mustacchi     hc_data.sb_id_and_flags   |= (0xffffffff & (rss_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT));
885d14abf15SRobert Mustacchi     hc_data.sb_id_and_flags   |= (0xffffffff & (storm_id << IGU_ACK_REGISTER_STORM_ID_SHIFT));
886d14abf15SRobert Mustacchi     hc_data.sb_id_and_flags   |= (0xffffffff & (is_update_idx << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT));
887d14abf15SRobert Mustacchi     hc_data.status_block_index = sb_index;
888d14abf15SRobert Mustacchi 
889d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "lm_int_ack_sb() inside! data:0x%x; status_block_index:%d\n", hc_data.sb_id_and_flags, hc_data.status_block_index);
890d14abf15SRobert Mustacchi 
891d14abf15SRobert Mustacchi     result = ((u32_t)hc_data.sb_id_and_flags) << 16 | hc_data.status_block_index;
892d14abf15SRobert Mustacchi 
893d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "lm_int_ack_sb() result:0x%x\n", result);
894d14abf15SRobert Mustacchi 
895d14abf15SRobert Mustacchi     // interrupt ack
896d14abf15SRobert Mustacchi     REG_WR(pdev,  HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_INT_ACK, result);
897d14abf15SRobert Mustacchi 
898d14abf15SRobert Mustacchi }
899d14abf15SRobert Mustacchi 
900d14abf15SRobert Mustacchi 
901d14abf15SRobert Mustacchi 
lm_int_igu_ack_sb(lm_device_t * pdev,u8_t igu_sb_id,u8_t segment_access,u16_t sb_index,u8_t int_op,u8_t is_update_idx)902d14abf15SRobert Mustacchi void lm_int_igu_ack_sb(lm_device_t *pdev, u8_t igu_sb_id, u8_t segment_access, u16_t sb_index, u8_t int_op, u8_t is_update_idx)
903d14abf15SRobert Mustacchi {
904d14abf15SRobert Mustacchi     struct igu_regular cmd_data;
905d14abf15SRobert Mustacchi     struct igu_ctrl_reg cmd_ctrl;
906d14abf15SRobert Mustacchi     u32_t cmd_addr;
907d14abf15SRobert Mustacchi 
908d14abf15SRobert Mustacchi     //DbgMessage(pdev, FATAL, "int-igu-ack segment_access=%d\n", segment_access);
909d14abf15SRobert Mustacchi     DbgBreakIf(sb_index & ~IGU_REGULAR_SB_INDEX);
910d14abf15SRobert Mustacchi 
911d14abf15SRobert Mustacchi     /*
912d14abf15SRobert Mustacchi      * We may get here with IGU disabled. In that case, no IGU access is permitted.
913d14abf15SRobert Mustacchi      */
914*9b622488SToomas Soome     if (!pdev->vars.enable_intr)
915d14abf15SRobert Mustacchi     {
916d14abf15SRobert Mustacchi         return;
917d14abf15SRobert Mustacchi     }
918d14abf15SRobert Mustacchi 
919d14abf15SRobert Mustacchi     cmd_data.sb_id_and_flags =
920d14abf15SRobert Mustacchi         ((sb_index << IGU_REGULAR_SB_INDEX_SHIFT) |
921d14abf15SRobert Mustacchi          (segment_access << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
922d14abf15SRobert Mustacchi          (is_update_idx << IGU_REGULAR_BUPDATE_SHIFT) |
923d14abf15SRobert Mustacchi          (int_op << IGU_REGULAR_ENABLE_INT_SHIFT));
924d14abf15SRobert Mustacchi 
925d14abf15SRobert Mustacchi     cmd_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
926d14abf15SRobert Mustacchi 
927d14abf15SRobert Mustacchi     if (INTR_BLK_ACCESS(pdev) == INTR_BLK_ACCESS_IGUMEM) {
928d14abf15SRobert Mustacchi         if (IS_PFDEV(pdev)) {
929d14abf15SRobert Mustacchi             REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, cmd_data.sb_id_and_flags);
930d14abf15SRobert Mustacchi         } else {
931d14abf15SRobert Mustacchi             VF_REG_WR(pdev, VF_BAR0_IGU_OFFSET + cmd_addr*8, cmd_data.sb_id_and_flags);
932d14abf15SRobert Mustacchi         }
933d14abf15SRobert Mustacchi     } else {
934d14abf15SRobert Mustacchi         u8_t igu_func_id = 0;
935d14abf15SRobert Mustacchi 
936d14abf15SRobert Mustacchi         /* GRC ACCESS: */
937d14abf15SRobert Mustacchi         DbgBreakIf(IS_VFDEV(pdev));
938d14abf15SRobert Mustacchi         /* Write the Data, then the control */
939d14abf15SRobert Mustacchi         /* [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:14] = 0; [13:12] = PF number) */
940d14abf15SRobert Mustacchi         igu_func_id = IGU_FUNC_ID(pdev);
941d14abf15SRobert Mustacchi         cmd_ctrl.ctrl_data =
942d14abf15SRobert Mustacchi             ((cmd_addr << IGU_CTRL_REG_ADDRESS_SHIFT) |
943d14abf15SRobert Mustacchi              (igu_func_id << IGU_CTRL_REG_FID_SHIFT) |
944d14abf15SRobert Mustacchi              (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
945d14abf15SRobert Mustacchi 
946d14abf15SRobert Mustacchi         REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
947d14abf15SRobert Mustacchi         REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
948d14abf15SRobert Mustacchi     }
949d14abf15SRobert Mustacchi }
950d14abf15SRobert Mustacchi 
lm_int_igu_sb_cleanup(lm_device_t * pdev,u8 igu_sb_id)951d14abf15SRobert Mustacchi void lm_int_igu_sb_cleanup(lm_device_t *pdev, u8 igu_sb_id)
952d14abf15SRobert Mustacchi {
953d14abf15SRobert Mustacchi     struct igu_regular  cmd_data = {0};
954d14abf15SRobert Mustacchi     struct igu_ctrl_reg cmd_ctrl = {0};
955d14abf15SRobert Mustacchi     u32_t igu_addr_ack           = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (igu_sb_id/32)*4;
956d14abf15SRobert Mustacchi     u32_t sb_bit                 =  1 << (igu_sb_id%32);
957d14abf15SRobert Mustacchi     u32_t cnt                    = 100;
958d14abf15SRobert Mustacchi 
959d14abf15SRobert Mustacchi #ifdef _VBD_CMD_
960d14abf15SRobert Mustacchi     return;
961d14abf15SRobert Mustacchi #endif
962d14abf15SRobert Mustacchi 
963d14abf15SRobert Mustacchi     /* Not supported in backward compatible mode! */
964d14abf15SRobert Mustacchi     if (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC)
965d14abf15SRobert Mustacchi     {
966d14abf15SRobert Mustacchi         return;
967d14abf15SRobert Mustacchi     }
968d14abf15SRobert Mustacchi 
969d14abf15SRobert Mustacchi     /* Cleanup can be done only via GRC access using the producer update command */
970d14abf15SRobert Mustacchi     cmd_data.sb_id_and_flags =
971d14abf15SRobert Mustacchi         ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
972d14abf15SRobert Mustacchi           IGU_REGULAR_CLEANUP_SET |
973d14abf15SRobert Mustacchi           IGU_REGULAR_BCLEANUP);
974d14abf15SRobert Mustacchi 
975d14abf15SRobert Mustacchi     cmd_ctrl.ctrl_data =
976d14abf15SRobert Mustacchi         (((IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id) << IGU_CTRL_REG_ADDRESS_SHIFT) |
977d14abf15SRobert Mustacchi          (IGU_FUNC_ID(pdev) << IGU_CTRL_REG_FID_SHIFT) |
978d14abf15SRobert Mustacchi          (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
979d14abf15SRobert Mustacchi 
980d14abf15SRobert Mustacchi     REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
981d14abf15SRobert Mustacchi     REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
982d14abf15SRobert Mustacchi 
983d14abf15SRobert Mustacchi     /* wait for clean up to finish */
984d14abf15SRobert Mustacchi     while (!(REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt)
985d14abf15SRobert Mustacchi     {
986d14abf15SRobert Mustacchi         mm_wait(pdev, 10);
987d14abf15SRobert Mustacchi     }
988d14abf15SRobert Mustacchi 
989d14abf15SRobert Mustacchi     if (!(REG_RD(pdev, igu_addr_ack) & sb_bit))
990d14abf15SRobert Mustacchi     {
991d14abf15SRobert Mustacchi         DbgMessage(pdev, FATAL, "Unable to finish IGU cleanup - set: igu_sb_id %d offset %d bit %d (cnt %d)\n",
992d14abf15SRobert Mustacchi                     igu_sb_id, igu_sb_id/32, igu_sb_id%32, cnt);
993d14abf15SRobert Mustacchi     }
994d14abf15SRobert Mustacchi 
995d14abf15SRobert Mustacchi     /* Now we clear the cleanup-bit... same command without cleanup_set... */
996d14abf15SRobert Mustacchi     cmd_data.sb_id_and_flags =
997d14abf15SRobert Mustacchi         ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
998d14abf15SRobert Mustacchi           IGU_REGULAR_BCLEANUP);
999d14abf15SRobert Mustacchi 
1000d14abf15SRobert Mustacchi 
1001d14abf15SRobert Mustacchi     REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
1002d14abf15SRobert Mustacchi     REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
1003d14abf15SRobert Mustacchi 
1004d14abf15SRobert Mustacchi     /* wait for clean up to finish */
1005d14abf15SRobert Mustacchi     while ((REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt)
1006d14abf15SRobert Mustacchi     {
1007d14abf15SRobert Mustacchi         mm_wait(pdev, 10);
1008d14abf15SRobert Mustacchi     }
1009d14abf15SRobert Mustacchi 
1010d14abf15SRobert Mustacchi     if ((REG_RD(pdev, igu_addr_ack) & sb_bit))
1011d14abf15SRobert Mustacchi     {
1012d14abf15SRobert Mustacchi         DbgMessage(pdev, FATAL, "Unable to finish IGU cleanup - clear: igu_sb_id %d offset %d bit %d (cnt %d)\n",
1013d14abf15SRobert Mustacchi                     igu_sb_id, igu_sb_id/32, igu_sb_id%32, cnt);
1014d14abf15SRobert Mustacchi     }
1015d14abf15SRobert Mustacchi }
1016d14abf15SRobert Mustacchi 
1017d14abf15SRobert Mustacchi 
lm_int_ack_def_sb_disable(lm_device_t * pdev)1018d14abf15SRobert Mustacchi void lm_int_ack_def_sb_disable(lm_device_t *pdev)
1019d14abf15SRobert Mustacchi {
1020d14abf15SRobert Mustacchi     pdev->debug_info.ack_def_dis++;
1021d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
1022d14abf15SRobert Mustacchi         lm_int_hc_ack_sb(pdev, DEF_STATUS_BLOCK_IGU_INDEX, HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_DISABLE, 0); //DEF_STATUS_BLOCK_INDEX
1023d14abf15SRobert Mustacchi     } else {
1024d14abf15SRobert Mustacchi         if (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC) {
1025d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_DISABLE, 0);
1026d14abf15SRobert Mustacchi         } else {
1027d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), IGU_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_DISABLE, 1);
1028d14abf15SRobert Mustacchi         }
1029d14abf15SRobert Mustacchi     }
1030d14abf15SRobert Mustacchi }
1031d14abf15SRobert Mustacchi 
1032d14abf15SRobert Mustacchi /* Assumptions: Called when acking a status-block and enabling interrupts */
lm_int_ack_def_sb_enable(lm_device_t * pdev)1033d14abf15SRobert Mustacchi void lm_int_ack_def_sb_enable(lm_device_t *pdev)
1034d14abf15SRobert Mustacchi {
1035d14abf15SRobert Mustacchi     pdev->debug_info.ack_def_en++;
1036d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
1037d14abf15SRobert Mustacchi         lm_int_hc_ack_sb(pdev, DEF_STATUS_BLOCK_IGU_INDEX, HC_SEG_ACCESS_ATTN, DEF_SB_INDEX_OF_ATTN(pdev), IGU_INT_NOP, 1); //DEF_STATUS_BLOCK_INDEX
1038d14abf15SRobert Mustacchi         lm_int_hc_ack_sb(pdev, DEF_STATUS_BLOCK_IGU_INDEX, HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_ENABLE, 1); //DEF_STATUS_BLOCK_INDEX
1039d14abf15SRobert Mustacchi     } else {
1040d14abf15SRobert Mustacchi         if (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC) {
1041d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), HC_SEG_ACCESS_ATTN, DEF_SB_INDEX_OF_ATTN(pdev), IGU_INT_NOP, 1);
1042d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_ENABLE, 1);
1043d14abf15SRobert Mustacchi         } else {
1044d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), IGU_SEG_ACCESS_ATTN, DEF_SB_INDEX_OF_ATTN(pdev), IGU_INT_NOP, 1);
1045d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), IGU_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_ENABLE, 1);
1046d14abf15SRobert Mustacchi         }
1047d14abf15SRobert Mustacchi     }
1048d14abf15SRobert Mustacchi }
1049d14abf15SRobert Mustacchi 
lm_int_ack_sb_disable(lm_device_t * pdev,u8_t rss_id)1050d14abf15SRobert Mustacchi void lm_int_ack_sb_disable(lm_device_t *pdev, u8_t rss_id)
1051d14abf15SRobert Mustacchi {
1052d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
1053d14abf15SRobert Mustacchi         lm_int_hc_ack_sb(pdev, rss_id , HC_SEG_ACCESS_NORM, 0, IGU_INT_DISABLE, 0);
1054d14abf15SRobert Mustacchi         pdev->debug_info.ack_dis[rss_id]++;
1055d14abf15SRobert Mustacchi     } else {
1056d14abf15SRobert Mustacchi         if (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC) {
1057d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, rss_id  + IGU_BASE_NDSB(pdev) , HC_SEG_ACCESS_NORM, 0, IGU_INT_DISABLE, 0);
1058d14abf15SRobert Mustacchi             pdev->debug_info.ack_dis[rss_id]++;
1059d14abf15SRobert Mustacchi         } else {
1060d14abf15SRobert Mustacchi             if (pdev->debug_info.ack_dis[rss_id] == pdev->debug_info.ack_en[rss_id]) {
1061d14abf15SRobert Mustacchi                 //DbgMessage(pdev, WARN, "********lm_int_ack_sb_disable() during DPC\n");
1062d14abf15SRobert Mustacchi //                REG_WR(PFDEV(pdev), IGU_REG_ECO_RESERVED, 8);
1063d14abf15SRobert Mustacchi //                DbgBreak();
1064d14abf15SRobert Mustacchi             }
1065*9b622488SToomas Soome             if (IS_PFDEV(pdev))
1066d14abf15SRobert Mustacchi             {
1067d14abf15SRobert Mustacchi                 lm_int_igu_ack_sb(pdev, rss_id  + IGU_BASE_NDSB(pdev), IGU_SEG_ACCESS_NORM, 0, IGU_INT_DISABLE, 0);
1068d14abf15SRobert Mustacchi             }
1069d14abf15SRobert Mustacchi             else
1070d14abf15SRobert Mustacchi             {
1071d14abf15SRobert Mustacchi                 lm_int_igu_ack_sb(pdev, IGU_VF_NDSB(pdev,rss_id), IGU_SEG_ACCESS_NORM, 0, IGU_INT_DISABLE, 0);
1072d14abf15SRobert Mustacchi             }
1073d14abf15SRobert Mustacchi             pdev->debug_info.ack_dis[rss_id]++;
1074d14abf15SRobert Mustacchi         }
1075d14abf15SRobert Mustacchi     }
1076d14abf15SRobert Mustacchi }
1077d14abf15SRobert Mustacchi 
lm_int_ack_sb_enable(lm_device_t * pdev,u8_t rss_id)1078d14abf15SRobert Mustacchi void lm_int_ack_sb_enable(lm_device_t *pdev, u8_t rss_id)
1079d14abf15SRobert Mustacchi {
1080d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
1081d14abf15SRobert Mustacchi         lm_int_hc_ack_sb(pdev, rss_id , HC_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
1082d14abf15SRobert Mustacchi         pdev->debug_info.ack_en[rss_id]++;
1083d14abf15SRobert Mustacchi     } else {
1084d14abf15SRobert Mustacchi         if (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC) {
1085d14abf15SRobert Mustacchi             lm_int_igu_ack_sb(pdev, rss_id  + IGU_BASE_NDSB(pdev) , HC_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
1086d14abf15SRobert Mustacchi             pdev->debug_info.ack_en[rss_id]++;
1087d14abf15SRobert Mustacchi         } else {
1088d14abf15SRobert Mustacchi             if (rss_id >= IGU_U_NDSB_OFFSET(pdev)) {
1089*9b622488SToomas Soome                 if (IS_PFDEV(pdev))
1090d14abf15SRobert Mustacchi                 {
1091d14abf15SRobert Mustacchi                     lm_int_igu_ack_sb(pdev, rss_id  + IGU_BASE_NDSB(pdev), IGU_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
1092d14abf15SRobert Mustacchi                 }
1093d14abf15SRobert Mustacchi                 else
1094d14abf15SRobert Mustacchi                 {
1095d14abf15SRobert Mustacchi                     lm_int_igu_ack_sb(pdev, IGU_VF_NDSB(pdev,rss_id), IGU_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
1096d14abf15SRobert Mustacchi                 }
1097d14abf15SRobert Mustacchi                 pdev->debug_info.ack_en[rss_id]++;
1098d14abf15SRobert Mustacchi             } else {
1099d14abf15SRobert Mustacchi                 lm_int_igu_ack_sb(pdev, rss_id  + IGU_BASE_NDSB(pdev), IGU_SEG_ACCESS_NORM, SB_TX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
1100d14abf15SRobert Mustacchi             }
1101d14abf15SRobert Mustacchi          }
1102d14abf15SRobert Mustacchi     }
1103d14abf15SRobert Mustacchi }
1104d14abf15SRobert Mustacchi 
lm_enable_hc_int(struct _lm_device_t * pdev)1105d14abf15SRobert Mustacchi void lm_enable_hc_int(struct _lm_device_t *pdev)
1106d14abf15SRobert Mustacchi {
1107d14abf15SRobert Mustacchi     u32_t val;
1108d14abf15SRobert Mustacchi     u32_t reg_name;
1109d14abf15SRobert Mustacchi 
1110d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
1111d14abf15SRobert Mustacchi 
1112d14abf15SRobert Mustacchi     reg_name = PORT_ID(pdev) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1113d14abf15SRobert Mustacchi 
1114d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMnv, "### lm_enable_int\n");
1115d14abf15SRobert Mustacchi 
1116d14abf15SRobert Mustacchi     val = 0x1000;
1117d14abf15SRobert Mustacchi 
1118d14abf15SRobert Mustacchi     SET_FLAGS(val, (PORT_ID(pdev)?  HC_CONFIG_1_REG_ATTN_BIT_EN_1 : HC_CONFIG_0_REG_ATTN_BIT_EN_0));
1119d14abf15SRobert Mustacchi 
1120d14abf15SRobert Mustacchi     switch (pdev->params.interrupt_mode) {
1121d14abf15SRobert Mustacchi     case LM_INT_MODE_INTA:
1122d14abf15SRobert Mustacchi         SET_FLAGS(val, (HC_CONFIG_0_REG_INT_LINE_EN_0 |
1123d14abf15SRobert Mustacchi                         HC_CONFIG_0_REG_SINGLE_ISR_EN_0));
1124d14abf15SRobert Mustacchi 
1125d14abf15SRobert Mustacchi         /* we trust that if we're in inta... the os will take care of the configuration space...and therefore
1126d14abf15SRobert Mustacchi          * that will determine whether we are in inta or msix and not this configuration, we can't take down msix
1127d14abf15SRobert Mustacchi          * due to a hw bug */
1128d14abf15SRobert Mustacchi         if (CHIP_IS_E1(pdev))
1129d14abf15SRobert Mustacchi         {
1130d14abf15SRobert Mustacchi             SET_FLAGS(val, HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0);
1131d14abf15SRobert Mustacchi         }
1132d14abf15SRobert Mustacchi         break;
1133d14abf15SRobert Mustacchi     case LM_INT_MODE_SIMD:
1134d14abf15SRobert Mustacchi         SET_FLAGS(val, (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0) );
1135d14abf15SRobert Mustacchi         RESET_FLAGS(val, HC_CONFIG_0_REG_INT_LINE_EN_0);
1136d14abf15SRobert Mustacchi         break;
1137d14abf15SRobert Mustacchi     case LM_INT_MODE_MIMD:
1138d14abf15SRobert Mustacchi         SET_FLAGS(val, HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0);
1139d14abf15SRobert Mustacchi         RESET_FLAGS(val, (HC_CONFIG_0_REG_INT_LINE_EN_0 |
1140d14abf15SRobert Mustacchi                           HC_CONFIG_0_REG_SINGLE_ISR_EN_0));
1141d14abf15SRobert Mustacchi         break;
1142d14abf15SRobert Mustacchi     default:
1143d14abf15SRobert Mustacchi         DbgBreakMsg("Wrong Interrupt Mode\n");
1144d14abf15SRobert Mustacchi         return;
1145d14abf15SRobert Mustacchi     }
1146d14abf15SRobert Mustacchi 
1147d14abf15SRobert Mustacchi     if (CHIP_IS_E1(pdev))
1148d14abf15SRobert Mustacchi     {
1149d14abf15SRobert Mustacchi         REG_WR(pdev, HC_REG_INT_MASK + PORT_ID(pdev)*4, 0x1FFFF);
1150d14abf15SRobert Mustacchi     }
1151d14abf15SRobert Mustacchi 
1152d14abf15SRobert Mustacchi     REG_WR(pdev,  reg_name, val);
1153d14abf15SRobert Mustacchi 
1154d14abf15SRobert Mustacchi     if(!CHIP_IS_E1(pdev))
1155d14abf15SRobert Mustacchi     {
1156d14abf15SRobert Mustacchi         /* init leading/trailing edge */
1157d14abf15SRobert Mustacchi         if(IS_MULTI_VNIC(pdev))
1158d14abf15SRobert Mustacchi         {
1159d14abf15SRobert Mustacchi             /* in mf mode:
1160d14abf15SRobert Mustacchi              *  - Set only VNIC bit out of the "per vnic group attentions" (bits[4-7]) */
1161d14abf15SRobert Mustacchi             val = (0xee0f | (1 << (VNIC_ID(pdev) + 4)));
1162d14abf15SRobert Mustacchi             /* Connect to PMF to NIG attention bit 8 */
1163d14abf15SRobert Mustacchi             if (IS_PMF(pdev)) {
1164d14abf15SRobert Mustacchi                 val |= 0x1100;
1165d14abf15SRobert Mustacchi             }
1166d14abf15SRobert Mustacchi         } else
1167d14abf15SRobert Mustacchi         {
1168d14abf15SRobert Mustacchi             val = 0xffff;
1169d14abf15SRobert Mustacchi         }
1170d14abf15SRobert Mustacchi         REG_WR(pdev,  (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), val);
1171d14abf15SRobert Mustacchi         REG_WR(pdev,  (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), val);
1172d14abf15SRobert Mustacchi     }
1173d14abf15SRobert Mustacchi 
1174d14abf15SRobert Mustacchi     pdev->vars.enable_intr = 1;
1175d14abf15SRobert Mustacchi }
1176d14abf15SRobert Mustacchi 
lm_enable_igu_int(struct _lm_device_t * pdev)1177d14abf15SRobert Mustacchi lm_status_t lm_enable_igu_int(struct _lm_device_t *pdev)
1178d14abf15SRobert Mustacchi {
1179d14abf15SRobert Mustacchi     u32_t val = 0;
1180d14abf15SRobert Mustacchi 
1181d14abf15SRobert Mustacchi     if(ERR_IF(!pdev)) {
1182d14abf15SRobert Mustacchi         return LM_STATUS_INVALID_PARAMETER;
1183d14abf15SRobert Mustacchi     }
1184d14abf15SRobert Mustacchi 
1185d14abf15SRobert Mustacchi #ifdef VF_INVOLVED
1186d14abf15SRobert Mustacchi     if (IS_VFDEV(pdev)) {
1187d14abf15SRobert Mustacchi         lm_status_t lm_status;
1188d14abf15SRobert Mustacchi         lm_status =  lm_vf_enable_igu_int(pdev);
1189d14abf15SRobert Mustacchi         if (lm_status != LM_STATUS_SUCCESS) {
1190d14abf15SRobert Mustacchi             DbgMessage(pdev, FATAL, "VF can't enable igu interrupt\n");
1191d14abf15SRobert Mustacchi             return lm_status;
1192d14abf15SRobert Mustacchi         }
1193d14abf15SRobert Mustacchi         pdev->vars.enable_intr = 1;
1194d14abf15SRobert Mustacchi         return lm_status;
1195d14abf15SRobert Mustacchi 
1196d14abf15SRobert Mustacchi     }
1197d14abf15SRobert Mustacchi #endif
1198d14abf15SRobert Mustacchi 
1199d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMnv, "### lm_enable_int\n");
1200d14abf15SRobert Mustacchi 
1201d14abf15SRobert Mustacchi     val=REG_RD(pdev, IGU_REG_PF_CONFIGURATION);
1202d14abf15SRobert Mustacchi 
1203d14abf15SRobert Mustacchi     SET_FLAGS(val, IGU_PF_CONF_FUNC_EN);
1204d14abf15SRobert Mustacchi     SET_FLAGS(val, IGU_PF_CONF_ATTN_BIT_EN);
1205d14abf15SRobert Mustacchi 
1206d14abf15SRobert Mustacchi     switch (pdev->params.interrupt_mode) {
1207d14abf15SRobert Mustacchi     case LM_INT_MODE_INTA:
1208d14abf15SRobert Mustacchi         SET_FLAGS(val, (IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN));
1209d14abf15SRobert Mustacchi         RESET_FLAGS(val, IGU_PF_CONF_MSI_MSIX_EN);
1210d14abf15SRobert Mustacchi         break;
1211d14abf15SRobert Mustacchi     case LM_INT_MODE_SIMD:
1212d14abf15SRobert Mustacchi         SET_FLAGS(val, (IGU_PF_CONF_SINGLE_ISR_EN | IGU_PF_CONF_MSI_MSIX_EN) );
1213d14abf15SRobert Mustacchi         RESET_FLAGS(val, IGU_PF_CONF_INT_LINE_EN);
1214d14abf15SRobert Mustacchi         break;
1215d14abf15SRobert Mustacchi     case LM_INT_MODE_MIMD:
1216d14abf15SRobert Mustacchi         SET_FLAGS(val, IGU_PF_CONF_MSI_MSIX_EN);
1217d14abf15SRobert Mustacchi         RESET_FLAGS(val, (IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN));
1218d14abf15SRobert Mustacchi         break;
1219d14abf15SRobert Mustacchi     default:
1220d14abf15SRobert Mustacchi         DbgBreakMsg("Wrong Interrupt Mode\n");
1221d14abf15SRobert Mustacchi         return LM_STATUS_FAILURE;
1222d14abf15SRobert Mustacchi     }
1223d14abf15SRobert Mustacchi 
1224d14abf15SRobert Mustacchi     REG_WR(pdev,  IGU_REG_PF_CONFIGURATION, val);
1225d14abf15SRobert Mustacchi 
1226d14abf15SRobert Mustacchi     if(!CHIP_IS_E1(pdev))
1227d14abf15SRobert Mustacchi     {
1228d14abf15SRobert Mustacchi         /* init leading/trailing edge */
1229d14abf15SRobert Mustacchi         if(IS_MULTI_VNIC(pdev))
1230d14abf15SRobert Mustacchi         {
1231d14abf15SRobert Mustacchi             /* in mf mode:
1232d14abf15SRobert Mustacchi              *  - Do not set the link attention (bit 11) (will be set by MCP for the PMF)
1233d14abf15SRobert Mustacchi              *  - Set only VNIC bit out of the "per vnic group attentions" (bits[4-7]) */
1234d14abf15SRobert Mustacchi             val = (0xee0f | (1 << (VNIC_ID(pdev) + 4)));
1235d14abf15SRobert Mustacchi             /* Connect to PMF to NIG attention bit 8 */
1236d14abf15SRobert Mustacchi             if (IS_PMF(pdev)) {
1237d14abf15SRobert Mustacchi                 val |= 0x1100;
1238d14abf15SRobert Mustacchi             }
1239d14abf15SRobert Mustacchi         } else
1240d14abf15SRobert Mustacchi         {
1241d14abf15SRobert Mustacchi             val = 0xffff;
1242d14abf15SRobert Mustacchi         }
1243d14abf15SRobert Mustacchi         if (CHIP_IS_E3(pdev)) {
1244*9b622488SToomas Soome             val &= ~ATTN_SW_TIMER_4_FUNC; // To prevent Timer4 expiration attention
1245d14abf15SRobert Mustacchi         }
1246d14abf15SRobert Mustacchi         REG_WR(pdev,  IGU_REG_TRAILING_EDGE_LATCH, val);
1247d14abf15SRobert Mustacchi         REG_WR(pdev,  IGU_REG_LEADING_EDGE_LATCH, val);
1248d14abf15SRobert Mustacchi     }
1249d14abf15SRobert Mustacchi 
1250d14abf15SRobert Mustacchi     pdev->vars.enable_intr = 1;
1251d14abf15SRobert Mustacchi 
1252d14abf15SRobert Mustacchi     return LM_STATUS_SUCCESS;
1253d14abf15SRobert Mustacchi }
1254d14abf15SRobert Mustacchi 
lm_enable_int(struct _lm_device_t * pdev)1255d14abf15SRobert Mustacchi void lm_enable_int(struct _lm_device_t *pdev)
1256d14abf15SRobert Mustacchi {
1257d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
1258d14abf15SRobert Mustacchi         lm_enable_hc_int(pdev);
1259d14abf15SRobert Mustacchi     } else {
1260d14abf15SRobert Mustacchi         lm_enable_igu_int(pdev);
1261d14abf15SRobert Mustacchi     }
1262d14abf15SRobert Mustacchi }
1263d14abf15SRobert Mustacchi 
1264d14abf15SRobert Mustacchi 
lm_disable_hc_int(struct _lm_device_t * pdev)1265d14abf15SRobert Mustacchi void lm_disable_hc_int(struct _lm_device_t *pdev)
1266d14abf15SRobert Mustacchi {
1267d14abf15SRobert Mustacchi     u32_t val;
1268d14abf15SRobert Mustacchi     u32_t reg_name;
1269d14abf15SRobert Mustacchi 
1270d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
1271d14abf15SRobert Mustacchi 
1272d14abf15SRobert Mustacchi     reg_name = PORT_ID(pdev) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1273d14abf15SRobert Mustacchi 
1274d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMnv, "### lm_disable_int\n");
1275d14abf15SRobert Mustacchi 
1276d14abf15SRobert Mustacchi     val=REG_RD(pdev, reg_name);
1277d14abf15SRobert Mustacchi 
1278d14abf15SRobert Mustacchi     /* disable both bits, for INTA, MSI and MSI-X. */
1279d14abf15SRobert Mustacchi     RESET_FLAGS(val, (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1280d14abf15SRobert Mustacchi                       HC_CONFIG_0_REG_INT_LINE_EN_0 |
1281d14abf15SRobert Mustacchi                       HC_CONFIG_0_REG_ATTN_BIT_EN_0 |
1282d14abf15SRobert Mustacchi                       HC_CONFIG_0_REG_SINGLE_ISR_EN_0));
1283d14abf15SRobert Mustacchi 
1284d14abf15SRobert Mustacchi     if (CHIP_IS_E1(pdev))
1285d14abf15SRobert Mustacchi     {
1286d14abf15SRobert Mustacchi         REG_WR(pdev, HC_REG_INT_MASK + PORT_ID(pdev)*4, 0);
1287d14abf15SRobert Mustacchi 
1288d14abf15SRobert Mustacchi         /* E1 Errate: can't ever take msix bit down */
1289d14abf15SRobert Mustacchi         SET_FLAGS(val,HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0);
1290d14abf15SRobert Mustacchi     }
1291d14abf15SRobert Mustacchi 
1292d14abf15SRobert Mustacchi     REG_WR(pdev,  reg_name, val);
1293d14abf15SRobert Mustacchi 
1294d14abf15SRobert Mustacchi     pdev->vars.enable_intr = 0;
1295d14abf15SRobert Mustacchi }
1296d14abf15SRobert Mustacchi 
lm_disable_igu_int(struct _lm_device_t * pdev)1297d14abf15SRobert Mustacchi void lm_disable_igu_int(struct _lm_device_t *pdev)
1298d14abf15SRobert Mustacchi {
1299d14abf15SRobert Mustacchi     u32_t val;
1300d14abf15SRobert Mustacchi 
1301d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
1302d14abf15SRobert Mustacchi 
1303d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMnv, "### lm_disable_int\n");
1304d14abf15SRobert Mustacchi 
1305d14abf15SRobert Mustacchi #ifdef VF_INVOLVED
1306d14abf15SRobert Mustacchi     if (IS_VFDEV(pdev)) {
1307d14abf15SRobert Mustacchi         lm_vf_disable_igu_int(pdev);
1308d14abf15SRobert Mustacchi         pdev->vars.enable_intr = 0;
1309d14abf15SRobert Mustacchi         return;
1310d14abf15SRobert Mustacchi     }
1311d14abf15SRobert Mustacchi #endif
1312d14abf15SRobert Mustacchi 
1313d14abf15SRobert Mustacchi     val = REG_RD(pdev, IGU_REG_PF_CONFIGURATION);
1314d14abf15SRobert Mustacchi 
1315d14abf15SRobert Mustacchi     /* disable both bits, for INTA, MSI and MSI-X. */
1316d14abf15SRobert Mustacchi     RESET_FLAGS(val, (IGU_PF_CONF_MSI_MSIX_EN |
1317d14abf15SRobert Mustacchi                       IGU_PF_CONF_INT_LINE_EN |
1318d14abf15SRobert Mustacchi                       IGU_PF_CONF_ATTN_BIT_EN |
1319d14abf15SRobert Mustacchi                       IGU_PF_CONF_SINGLE_ISR_EN |
1320d14abf15SRobert Mustacchi                       IGU_PF_CONF_FUNC_EN));
1321d14abf15SRobert Mustacchi 
1322d14abf15SRobert Mustacchi     REG_WR(pdev,  IGU_REG_PF_CONFIGURATION, val);
1323d14abf15SRobert Mustacchi 
1324d14abf15SRobert Mustacchi     pdev->vars.enable_intr = 0;
1325d14abf15SRobert Mustacchi }
1326d14abf15SRobert Mustacchi 
lm_disable_int(struct _lm_device_t * pdev)1327d14abf15SRobert Mustacchi void lm_disable_int(struct _lm_device_t *pdev)
1328d14abf15SRobert Mustacchi {
1329d14abf15SRobert Mustacchi     if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) {
1330d14abf15SRobert Mustacchi         lm_disable_hc_int(pdev);
1331d14abf15SRobert Mustacchi     } else {
1332d14abf15SRobert Mustacchi         lm_disable_igu_int(pdev);
1333d14abf15SRobert Mustacchi     }
1334d14abf15SRobert Mustacchi }
1335d14abf15SRobert Mustacchi 
lm_init_non_def_status_block(struct _lm_device_t * pdev,u8_t sb_id,u8_t port)1336d14abf15SRobert Mustacchi void lm_init_non_def_status_block(struct _lm_device_t *pdev,
1337d14abf15SRobert Mustacchi                               u8_t  sb_id,
1338d14abf15SRobert Mustacchi                               u8_t  port)
1339d14abf15SRobert Mustacchi {
1340d14abf15SRobert Mustacchi     lm_int_coalesing_info *ic  = &pdev->vars.int_coal;
1341d14abf15SRobert Mustacchi     u8_t index                 = 0;
1342d14abf15SRobert Mustacchi     const u8_t fw_sb_id        = LM_FW_SB_ID(pdev, sb_id);
1343d14abf15SRobert Mustacchi     const u8_t dhc_qzone_id    = LM_FW_DHC_QZONE_ID(pdev, sb_id);
1344d14abf15SRobert Mustacchi     const u8_t byte_counter_id = CHIP_IS_E1x(pdev)? fw_sb_id : dhc_qzone_id;
1345d14abf15SRobert Mustacchi     u8_t igu_sb_id = 0;
1346d14abf15SRobert Mustacchi     u8_t igu_seg_id = 0;
1347d14abf15SRobert Mustacchi     u8_t timeout = 0;
1348d14abf15SRobert Mustacchi     u8_t dhc_enable = FALSE;
1349d14abf15SRobert Mustacchi     u8_t sm_idx;
1350d14abf15SRobert Mustacchi     u8_t hc_sb_max_indices;
1351d14abf15SRobert Mustacchi 
1352d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
1353d14abf15SRobert Mustacchi 
1354d14abf15SRobert Mustacchi     /* CQ#46240: Disable the function in the status-block data before nullifying sync-line + status-block */
1355d14abf15SRobert Mustacchi     LM_INTMEM_WRITE8(pdev, CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fw_sb_id),
1356d14abf15SRobert Mustacchi                       SB_DISABLED, BAR_CSTRORM_INTMEM);
1357d14abf15SRobert Mustacchi 
1358d14abf15SRobert Mustacchi     /* nullify the status block */
1359d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_STATUS_BLOCK_SIZE % 4) != 0);
1360d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_STATUS_BLOCK_DATA_SIZE % 4) != 0);
1361d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_SYNC_BLOCK_SIZE % 4) != 0);
1362*9b622488SToomas Soome 
1363d14abf15SRobert Mustacchi     for (index = 0; index < CSTORM_SYNC_BLOCK_SIZE / sizeof(u32_t); index++) {
1364d14abf15SRobert Mustacchi         LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
1365d14abf15SRobert Mustacchi     }
1366d14abf15SRobert Mustacchi     for (index = 0; index < CSTORM_STATUS_BLOCK_SIZE / sizeof(u32_t); index++) {
1367d14abf15SRobert Mustacchi         LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
1368d14abf15SRobert Mustacchi     }
1369d14abf15SRobert Mustacchi 
1370d14abf15SRobert Mustacchi 
1371d14abf15SRobert Mustacchi     /* Initialize cstorm_status_block_data structure */
1372d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
1373d14abf15SRobert Mustacchi 
1374d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
1375d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.vf_id = 0xff;
1376d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.vf_valid = FALSE;
1377d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.vnic_id = VNIC_ID(pdev);
1378d14abf15SRobert Mustacchi 
1379d14abf15SRobert Mustacchi         if (pdev->params.ndsb_type == LM_DOUBLE_SM_SINGLE_IGU) {
1380d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.same_igu_sb_1b = TRUE;
1381d14abf15SRobert Mustacchi         } else {
1382d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.same_igu_sb_1b = FALSE;
1383d14abf15SRobert Mustacchi         }
1384d14abf15SRobert Mustacchi 
1385d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.state = SB_ENABLED;
1386d14abf15SRobert Mustacchi     } else {
1387d14abf15SRobert Mustacchi 
1388d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
1389d14abf15SRobert Mustacchi         if (IS_PFDEV(pdev)) {
1390d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vf_id = 0xff;
1391d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vf_valid = FALSE;
1392d14abf15SRobert Mustacchi         } else {
1393d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vf_id = ABS_VFID(pdev);
1394d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vf_valid = TRUE;
1395d14abf15SRobert Mustacchi         }
1396d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vnic_id = VNIC_ID(pdev);
1397d14abf15SRobert Mustacchi         if (pdev->params.ndsb_type == LM_DOUBLE_SM_SINGLE_IGU) {
1398d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.same_igu_sb_1b = TRUE;
1399d14abf15SRobert Mustacchi         } else {
1400d14abf15SRobert Mustacchi             pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.same_igu_sb_1b = FALSE;
1401d14abf15SRobert Mustacchi         }
1402d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.dhc_qzone_id = dhc_qzone_id;
1403d14abf15SRobert Mustacchi 
1404d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.state = SB_ENABLED;
1405d14abf15SRobert Mustacchi 
1406d14abf15SRobert Mustacchi     }
1407d14abf15SRobert Mustacchi 
1408d14abf15SRobert Mustacchi     if ((INTR_BLK_TYPE(pdev) == INTR_BLK_IGU) && (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_NORM) ) {
1409d14abf15SRobert Mustacchi         igu_sb_id = IGU_BASE_NDSB(pdev) + /*IGU_U_NDSB_OFFSET(pdev)*/ + sb_id;
1410d14abf15SRobert Mustacchi         igu_seg_id = IGU_SEG_ACCESS_NORM;
1411d14abf15SRobert Mustacchi     } else {
1412d14abf15SRobert Mustacchi         igu_sb_id = sb_id;
1413d14abf15SRobert Mustacchi         igu_seg_id = HC_SEG_ACCESS_NORM;
1414d14abf15SRobert Mustacchi     }
1415d14abf15SRobert Mustacchi 
1416d14abf15SRobert Mustacchi     lm_setup_ndsb_state_machine(pdev, sb_id, SM_RX_ID, igu_sb_id + IGU_U_NDSB_OFFSET(pdev), igu_seg_id);
1417d14abf15SRobert Mustacchi     if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1418d14abf15SRobert Mustacchi         lm_setup_ndsb_state_machine(pdev, sb_id, SM_TX_ID, igu_sb_id,igu_seg_id);
1419d14abf15SRobert Mustacchi     }
1420d14abf15SRobert Mustacchi 
1421d14abf15SRobert Mustacchi     //init host coalescing params - supported dymanicHC indices
1422d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
1423d14abf15SRobert Mustacchi         hc_sb_max_indices = HC_SB_MAX_INDICES_E1X;
1424d14abf15SRobert Mustacchi     } else {
1425d14abf15SRobert Mustacchi         hc_sb_max_indices = HC_SB_MAX_INDICES_E2;
1426d14abf15SRobert Mustacchi     }
1427d14abf15SRobert Mustacchi     for (index = 0; index < hc_sb_max_indices; index++) {
1428d14abf15SRobert Mustacchi         if (index < HC_DHC_SB_NUM_INDICES) {
1429d14abf15SRobert Mustacchi             dhc_enable = (pdev->params.enable_dynamic_hc[index] != 0);
1430d14abf15SRobert Mustacchi             REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(byte_counter_id, index), 0);
1431d14abf15SRobert Mustacchi         } else {
1432d14abf15SRobert Mustacchi             dhc_enable = FALSE;
1433d14abf15SRobert Mustacchi         }
1434d14abf15SRobert Mustacchi         switch (index) {
1435d14abf15SRobert Mustacchi         case HC_INDEX_TOE_RX_CQ_CONS:
1436d14abf15SRobert Mustacchi         case HC_INDEX_ETH_RX_CQ_CONS:
1437d14abf15SRobert Mustacchi         case HC_INDEX_FCOE_EQ_CONS:
1438d14abf15SRobert Mustacchi             sm_idx = SM_RX_ID;
1439d14abf15SRobert Mustacchi             if (dhc_enable && ic->hc_usec_u_sb[index]) {
1440d14abf15SRobert Mustacchi                 timeout = (u8_t)pdev->params.hc_timeout0[SM_RX_ID][index];
1441d14abf15SRobert Mustacchi             } else {
1442d14abf15SRobert Mustacchi                 timeout = (u8_t)(ic->hc_usec_u_sb[index] / HC_TIMEOUT_RESOLUTION_IN_US);
1443d14abf15SRobert Mustacchi             }
1444d14abf15SRobert Mustacchi             break;
1445d14abf15SRobert Mustacchi         case HC_INDEX_TOE_TX_CQ_CONS:
1446d14abf15SRobert Mustacchi             if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1447d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1448d14abf15SRobert Mustacchi             } else {
1449d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1450d14abf15SRobert Mustacchi             }
1451d14abf15SRobert Mustacchi             if (dhc_enable && ic->hc_usec_c_sb[0]) {
1452d14abf15SRobert Mustacchi                 if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1453d14abf15SRobert Mustacchi                     timeout = (u8_t)pdev->params.hc_timeout0[SM_TX_ID][index];
1454d14abf15SRobert Mustacchi                 } else {
1455d14abf15SRobert Mustacchi                     timeout = (u8_t)pdev->params.hc_timeout0[SM_RX_ID][index];
1456d14abf15SRobert Mustacchi                 }
1457d14abf15SRobert Mustacchi             } else {
1458d14abf15SRobert Mustacchi                 timeout = (u8_t)(ic->hc_usec_c_sb[0] / HC_TIMEOUT_RESOLUTION_IN_US);
1459d14abf15SRobert Mustacchi             }
1460d14abf15SRobert Mustacchi             break;
1461d14abf15SRobert Mustacchi 
1462d14abf15SRobert Mustacchi         case HC_INDEX_ETH_TX_CQ_CONS_COS0:
1463*9b622488SToomas Soome         case HC_INDEX_ETH_TX_CQ_CONS_COS1:
1464*9b622488SToomas Soome         case HC_INDEX_ETH_TX_CQ_CONS_COS2:
1465d14abf15SRobert Mustacchi             if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1466d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1467d14abf15SRobert Mustacchi             } else {
1468d14abf15SRobert Mustacchi             sm_idx = SM_RX_ID;
1469d14abf15SRobert Mustacchi             }
1470*9b622488SToomas Soome             // TODO Shayh: HC_PARAMS_ETH_INDEX (DYNAMIC_HC_ETH_INDEX) Should be handled better from registry
1471d14abf15SRobert Mustacchi             // (not as part of this submit) .
1472d14abf15SRobert Mustacchi             timeout = (u8_t)(ic->hc_usec_c_sb[1] / HC_TIMEOUT_RESOLUTION_IN_US);
1473d14abf15SRobert Mustacchi             break;
1474d14abf15SRobert Mustacchi 
1475d14abf15SRobert Mustacchi         case HC_INDEX_ISCSI_EQ_CONS:
1476d14abf15SRobert Mustacchi             if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1477d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1478d14abf15SRobert Mustacchi             } else {
1479d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1480d14abf15SRobert Mustacchi             }
1481d14abf15SRobert Mustacchi             // DYNAMIC_HC_ISCSI_INDEX
1482d14abf15SRobert Mustacchi             timeout = (u8_t)(ic->hc_usec_c_sb[2] / HC_TIMEOUT_RESOLUTION_IN_US);
1483d14abf15SRobert Mustacchi             break;
1484d14abf15SRobert Mustacchi 
1485d14abf15SRobert Mustacchi         default:
1486d14abf15SRobert Mustacchi             if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1487d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1488d14abf15SRobert Mustacchi             } else {
1489d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1490d14abf15SRobert Mustacchi             }
1491d14abf15SRobert Mustacchi             timeout = (u8_t)(ic->hc_usec_c_sb[3] / HC_TIMEOUT_RESOLUTION_IN_US);
1492d14abf15SRobert Mustacchi             dhc_enable = FALSE;
1493d14abf15SRobert Mustacchi             break;
1494d14abf15SRobert Mustacchi         }
1495d14abf15SRobert Mustacchi         lm_setup_ndsb_index(pdev, sb_id, index, sm_idx, timeout, dhc_enable);
1496d14abf15SRobert Mustacchi     }
1497d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
1498d14abf15SRobert Mustacchi         for (index = 0; index < sizeof(struct hc_status_block_data_e1x)/sizeof(u32_t); index++) {
1499d14abf15SRobert Mustacchi             LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + sizeof(u32_t)*index,
1500d14abf15SRobert Mustacchi                               *((u32_t*)(&pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data) + index), BAR_CSTRORM_INTMEM);
1501d14abf15SRobert Mustacchi         }
1502d14abf15SRobert Mustacchi     } else {
1503d14abf15SRobert Mustacchi         for (index = 0; index < sizeof(struct hc_status_block_data_e2)/sizeof(u32_t); index++) {
1504d14abf15SRobert Mustacchi             LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + sizeof(u32_t)*index,
1505d14abf15SRobert Mustacchi                               *((u32_t*)(&pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data) + index), BAR_CSTRORM_INTMEM);
1506d14abf15SRobert Mustacchi         }
1507d14abf15SRobert Mustacchi     }
1508d14abf15SRobert Mustacchi }
1509d14abf15SRobert Mustacchi 
1510d14abf15SRobert Mustacchi /**
1511d14abf15SRobert Mustacchi  * @description
1512*9b622488SToomas Soome  * Get the HC_INDEX_ETH_TX_CQ_CONS_COSX index from chain.
1513*9b622488SToomas Soome  * @param pdev
1514*9b622488SToomas Soome  * @param chain
1515*9b622488SToomas Soome  *
1516*9b622488SToomas Soome  * @return STATIC u8_t
1517d14abf15SRobert Mustacchi  */
1518d14abf15SRobert Mustacchi u8_t
lm_eth_tx_hc_cq_cons_cosx_from_chain(IN lm_device_t * pdev,IN const u32_t chain)1519d14abf15SRobert Mustacchi lm_eth_tx_hc_cq_cons_cosx_from_chain(IN         lm_device_t *pdev,
1520d14abf15SRobert Mustacchi                                      IN const   u32_t        chain)
1521d14abf15SRobert Mustacchi {
1522d14abf15SRobert Mustacchi     u8_t sb_index_number    = HC_INDEX_ETH_TX_CQ_CONS_COS0;
1523d14abf15SRobert Mustacchi     const u8_t cos          = lm_mp_cos_from_chain(pdev,chain);
1524d14abf15SRobert Mustacchi 
1525d14abf15SRobert Mustacchi     DbgBreakIf(lm_chain_type_not_cos == lm_mp_get_chain_type(pdev, chain));
1526d14abf15SRobert Mustacchi 
1527d14abf15SRobert Mustacchi     switch(cos)
1528d14abf15SRobert Mustacchi     {
1529d14abf15SRobert Mustacchi     case 0:
1530d14abf15SRobert Mustacchi         sb_index_number = HC_INDEX_ETH_TX_CQ_CONS_COS0;
1531d14abf15SRobert Mustacchi         break;
1532d14abf15SRobert Mustacchi     case 1:
1533d14abf15SRobert Mustacchi         sb_index_number = HC_INDEX_ETH_TX_CQ_CONS_COS1;
1534d14abf15SRobert Mustacchi         break;
1535d14abf15SRobert Mustacchi     case 2:
1536d14abf15SRobert Mustacchi         sb_index_number = HC_INDEX_ETH_TX_CQ_CONS_COS2;
1537d14abf15SRobert Mustacchi         break;
1538d14abf15SRobert Mustacchi     default:
1539d14abf15SRobert Mustacchi         DbgBreakMsg("Invalid cos");
1540d14abf15SRobert Mustacchi         break;
1541d14abf15SRobert Mustacchi     }
1542d14abf15SRobert Mustacchi 
1543d14abf15SRobert Mustacchi     return sb_index_number;
1544d14abf15SRobert Mustacchi }
1545d14abf15SRobert Mustacchi 
1546d14abf15SRobert Mustacchi #ifdef VF_INVOLVED
1547d14abf15SRobert Mustacchi 
lm_pf_init_vf_non_def_sb(struct _lm_device_t * pdev,lm_vf_info_t * vf_info,u8_t sb_idx,u64 sb_addr)1548d14abf15SRobert Mustacchi lm_status_t lm_pf_init_vf_non_def_sb(struct _lm_device_t *pdev, lm_vf_info_t *vf_info, u8_t sb_idx, u64 sb_addr)
1549d14abf15SRobert Mustacchi {
1550d14abf15SRobert Mustacchi     lm_status_t lm_status = LM_STATUS_SUCCESS;
1551d14abf15SRobert Mustacchi 
1552d14abf15SRobert Mustacchi     lm_int_coalesing_info *ic  = &pdev->vars.int_coal;
1553d14abf15SRobert Mustacchi     u8_t index                 = 0;
1554d14abf15SRobert Mustacchi     const u8_t fw_sb_id        = LM_FW_VF_SB_ID(vf_info, sb_idx);
1555d14abf15SRobert Mustacchi     const u8_t dhc_qzone_id    = LM_FW_VF_DHC_QZONE_ID(vf_info, sb_idx);
1556d14abf15SRobert Mustacchi     const u8_t byte_counter_id = dhc_qzone_id;
1557d14abf15SRobert Mustacchi     u8_t igu_sb_id = 0;
1558d14abf15SRobert Mustacchi     u8_t igu_seg_id = 0;
1559d14abf15SRobert Mustacchi     lm_address_t    sb_phy_address;
1560d14abf15SRobert Mustacchi     u8_t hc_sb_max_indices;
1561d14abf15SRobert Mustacchi     u8_t dhc_enable = FALSE;
1562d14abf15SRobert Mustacchi     u8_t sm_idx;
1563d14abf15SRobert Mustacchi     u8_t timeout = 0;
1564d14abf15SRobert Mustacchi 
1565d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
1566d14abf15SRobert Mustacchi 
1567d14abf15SRobert Mustacchi     /* CQ#46240: Disable the function in the status-block data before nullifying sync-line + status-block */
1568d14abf15SRobert Mustacchi     LM_INTMEM_WRITE8(pdev, CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fw_sb_id),
1569d14abf15SRobert Mustacchi                       SB_DISABLED, BAR_CSTRORM_INTMEM);
1570d14abf15SRobert Mustacchi 
1571d14abf15SRobert Mustacchi     /* nullify the status block */
1572d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_STATUS_BLOCK_SIZE % 4) != 0);
1573d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_STATUS_BLOCK_DATA_SIZE % 4) != 0);
1574d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_SYNC_BLOCK_SIZE % 4) != 0);
1575d14abf15SRobert Mustacchi     if (IS_PFDEV(pdev)) {
1576d14abf15SRobert Mustacchi         for (index = 0; index < CSTORM_SYNC_BLOCK_SIZE / sizeof(u32_t); index++) {
1577d14abf15SRobert Mustacchi             LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
1578d14abf15SRobert Mustacchi         }
1579d14abf15SRobert Mustacchi         for (index = 0; index < CSTORM_STATUS_BLOCK_SIZE / sizeof(u32_t); index++) {
1580d14abf15SRobert Mustacchi             LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
1581d14abf15SRobert Mustacchi         }
1582d14abf15SRobert Mustacchi     } else {
1583d14abf15SRobert Mustacchi         DbgBreak();
1584d14abf15SRobert Mustacchi     }
1585d14abf15SRobert Mustacchi 
1586d14abf15SRobert Mustacchi     sb_phy_address.as_u64 = sb_addr;
1587d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.host_sb_addr.lo = sb_phy_address.as_u32.low;
1588d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.host_sb_addr.hi = sb_phy_address.as_u32.high;
1589d14abf15SRobert Mustacchi 
1590d14abf15SRobert Mustacchi     /* Initialize cstorm_status_block_data structure */
1591d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
1592d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.vf_id = vf_info->abs_vf_id;
1593d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.vf_valid = TRUE;
1594d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.vnic_id = VNIC_ID(pdev);
1595d14abf15SRobert Mustacchi     if (pdev->params.ndsb_type == LM_DOUBLE_SM_SINGLE_IGU) {
1596d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.same_igu_sb_1b = TRUE;
1597d14abf15SRobert Mustacchi     } else {
1598d14abf15SRobert Mustacchi         pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.same_igu_sb_1b = FALSE;
1599d14abf15SRobert Mustacchi     }
1600d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.dhc_qzone_id = dhc_qzone_id;
1601d14abf15SRobert Mustacchi     pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.state = SB_ENABLED;
1602d14abf15SRobert Mustacchi 
1603d14abf15SRobert Mustacchi     if ((INTR_BLK_TYPE(pdev) == INTR_BLK_IGU) && (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_NORM) ) {
1604d14abf15SRobert Mustacchi         igu_sb_id = LM_VF_IGU_SB_ID(vf_info,sb_idx);
1605d14abf15SRobert Mustacchi         igu_seg_id = IGU_SEG_ACCESS_NORM;
1606d14abf15SRobert Mustacchi     } else {
1607d14abf15SRobert Mustacchi         DbgBreak();
1608d14abf15SRobert Mustacchi     }
1609d14abf15SRobert Mustacchi 
1610d14abf15SRobert Mustacchi     lm_setup_ndsb_state_machine(pdev, LM_SW_VF_SB_ID(vf_info,sb_idx), SM_RX_ID, igu_sb_id + IGU_U_NDSB_OFFSET(pdev), igu_seg_id);
1611d14abf15SRobert Mustacchi     if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1612d14abf15SRobert Mustacchi         lm_setup_ndsb_state_machine(pdev, LM_SW_VF_SB_ID(vf_info,sb_idx), SM_TX_ID, igu_sb_id,igu_seg_id);
1613d14abf15SRobert Mustacchi     }
1614d14abf15SRobert Mustacchi 
1615d14abf15SRobert Mustacchi     //init host coalescing params - supported dymanicHC indices
1616d14abf15SRobert Mustacchi     if (CHIP_IS_E1x(pdev)) {
1617d14abf15SRobert Mustacchi         DbgBreak();
1618d14abf15SRobert Mustacchi     } else {
1619d14abf15SRobert Mustacchi         hc_sb_max_indices = HC_SB_MAX_INDICES_E2;
1620d14abf15SRobert Mustacchi     }
1621d14abf15SRobert Mustacchi     for (index = 0; index < hc_sb_max_indices; index++) {
1622d14abf15SRobert Mustacchi         if (index < HC_DHC_SB_NUM_INDICES) {
1623d14abf15SRobert Mustacchi             dhc_enable = (pdev->params.enable_dynamic_hc[index] != 0);
1624d14abf15SRobert Mustacchi         REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(byte_counter_id, index), 0);
1625d14abf15SRobert Mustacchi         } else {
1626d14abf15SRobert Mustacchi             dhc_enable = FALSE;
1627d14abf15SRobert Mustacchi     }
1628d14abf15SRobert Mustacchi         switch (index) {
1629d14abf15SRobert Mustacchi         case HC_INDEX_TOE_RX_CQ_CONS:
1630d14abf15SRobert Mustacchi         case HC_INDEX_ETH_RX_CQ_CONS:
1631d14abf15SRobert Mustacchi         case HC_INDEX_FCOE_EQ_CONS:
1632d14abf15SRobert Mustacchi             sm_idx = SM_RX_ID;
1633d14abf15SRobert Mustacchi             if (dhc_enable && ic->hc_usec_u_sb[index]) {
1634d14abf15SRobert Mustacchi                 timeout = (u8_t)pdev->params.hc_timeout0[SM_RX_ID][index];
1635d14abf15SRobert Mustacchi             } else {
1636d14abf15SRobert Mustacchi                 timeout = (u8_t)(ic->hc_usec_u_sb[index] / HC_TIMEOUT_RESOLUTION_IN_US);
1637d14abf15SRobert Mustacchi             }
1638d14abf15SRobert Mustacchi             break;
1639d14abf15SRobert Mustacchi         case HC_INDEX_TOE_TX_CQ_CONS:
1640d14abf15SRobert Mustacchi             if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1641d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1642d14abf15SRobert Mustacchi             } else {
1643d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1644d14abf15SRobert Mustacchi     }
1645d14abf15SRobert Mustacchi             if (dhc_enable && ic->hc_usec_c_sb[0]) {
1646d14abf15SRobert Mustacchi                 if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1647d14abf15SRobert Mustacchi                     timeout = (u8_t)pdev->params.hc_timeout0[SM_TX_ID][index];
1648d14abf15SRobert Mustacchi                 } else {
1649d14abf15SRobert Mustacchi                     timeout = (u8_t)pdev->params.hc_timeout0[SM_RX_ID][index];
1650d14abf15SRobert Mustacchi                 }
1651d14abf15SRobert Mustacchi             } else {
1652d14abf15SRobert Mustacchi                 timeout = (u8_t)(ic->hc_usec_c_sb[0] / HC_TIMEOUT_RESOLUTION_IN_US);
1653d14abf15SRobert Mustacchi             }
1654d14abf15SRobert Mustacchi             break;
1655d14abf15SRobert Mustacchi 
1656d14abf15SRobert Mustacchi         case HC_INDEX_ETH_TX_CQ_CONS_COS0:
1657d14abf15SRobert Mustacchi         case HC_INDEX_ETH_TX_CQ_CONS_COS1:
1658d14abf15SRobert Mustacchi         case HC_INDEX_ETH_TX_CQ_CONS_COS2:
1659d14abf15SRobert Mustacchi         if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1660d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1661d14abf15SRobert Mustacchi         } else {
1662d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1663d14abf15SRobert Mustacchi         }
1664*9b622488SToomas Soome             // TODO Shayh: HC_PARAMS_ETH_INDEX (DYNAMIC_HC_ETH_INDEX) Should be handled better from registry
1665d14abf15SRobert Mustacchi             // (not as part of this submit) .
1666d14abf15SRobert Mustacchi             timeout = (u8_t)(ic->hc_usec_c_sb[1] / HC_TIMEOUT_RESOLUTION_IN_US);
1667d14abf15SRobert Mustacchi             break;
1668d14abf15SRobert Mustacchi 
1669d14abf15SRobert Mustacchi         case HC_INDEX_ISCSI_EQ_CONS:
1670d14abf15SRobert Mustacchi             if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1671d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1672d14abf15SRobert Mustacchi             } else {
1673d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1674d14abf15SRobert Mustacchi             }
1675d14abf15SRobert Mustacchi             // DYNAMIC_HC_ISCSI_INDEX
1676d14abf15SRobert Mustacchi             timeout = (u8_t)(ic->hc_usec_c_sb[2] / HC_TIMEOUT_RESOLUTION_IN_US);
1677d14abf15SRobert Mustacchi             break;
1678d14abf15SRobert Mustacchi 
1679d14abf15SRobert Mustacchi         default:
1680d14abf15SRobert Mustacchi         if (pdev->params.ndsb_type != LM_SINGLE_SM) {
1681d14abf15SRobert Mustacchi                 sm_idx = SM_TX_ID;
1682d14abf15SRobert Mustacchi         } else {
1683d14abf15SRobert Mustacchi                 sm_idx = SM_RX_ID;
1684d14abf15SRobert Mustacchi     }
1685d14abf15SRobert Mustacchi             timeout = (u8_t)(ic->hc_usec_c_sb[3] / HC_TIMEOUT_RESOLUTION_IN_US);
1686d14abf15SRobert Mustacchi             dhc_enable = FALSE;
1687d14abf15SRobert Mustacchi             break;
1688d14abf15SRobert Mustacchi         }
1689d14abf15SRobert Mustacchi         lm_setup_ndsb_index(pdev, LM_SW_VF_SB_ID(vf_info,sb_idx), index, sm_idx, timeout, dhc_enable);
1690d14abf15SRobert Mustacchi     }
1691d14abf15SRobert Mustacchi 
1692d14abf15SRobert Mustacchi     if (!CHIP_IS_E1x(pdev)) {
1693d14abf15SRobert Mustacchi         for (index = 0; index < sizeof(struct hc_status_block_data_e2)/sizeof(u32_t); index++) {
1694d14abf15SRobert Mustacchi             LM_INTMEM_WRITE32(pdev, CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + sizeof(u32_t)*index,
1695d14abf15SRobert Mustacchi                               *((u32_t*)(&pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data) + index), BAR_CSTRORM_INTMEM);
1696d14abf15SRobert Mustacchi         }
1697d14abf15SRobert Mustacchi     } else {
1698d14abf15SRobert Mustacchi         DbgBreak();
1699d14abf15SRobert Mustacchi     }
1700d14abf15SRobert Mustacchi 
1701d14abf15SRobert Mustacchi 
1702d14abf15SRobert Mustacchi     return lm_status;
1703d14abf15SRobert Mustacchi }
1704d14abf15SRobert Mustacchi 
1705d14abf15SRobert Mustacchi #endif //VF_INVOLVED
1706d14abf15SRobert Mustacchi 
lm_clear_non_def_status_block(struct _lm_device_t * pdev,u8_t fw_sb_id)1707d14abf15SRobert Mustacchi void lm_clear_non_def_status_block(struct _lm_device_t *pdev, u8_t  fw_sb_id)
1708d14abf15SRobert Mustacchi {
1709d14abf15SRobert Mustacchi     u32_t   index    = 0;
1710d14abf15SRobert Mustacchi     u8_t    func     = 0;
1711d14abf15SRobert Mustacchi 
1712d14abf15SRobert Mustacchi     DbgBreakIf(!pdev);
1713d14abf15SRobert Mustacchi     DbgMessage(pdev, INFORMi, "clear_status_block: fw_sb_id:%d\n",fw_sb_id);
1714d14abf15SRobert Mustacchi 
1715d14abf15SRobert Mustacchi     func = FUNC_ID(pdev);
1716d14abf15SRobert Mustacchi 
1717d14abf15SRobert Mustacchi     /* nullify the status block */
1718d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_STATUS_BLOCK_SIZE % 4) != 0);
1719d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_STATUS_BLOCK_DATA_SIZE % 4) != 0);
1720d14abf15SRobert Mustacchi     DbgBreakIf((CSTORM_SYNC_BLOCK_SIZE % 4) != 0);
1721d14abf15SRobert Mustacchi 
1722d14abf15SRobert Mustacchi     LM_INTMEM_WRITE8(pdev, CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fw_sb_id),
1723d14abf15SRobert Mustacchi                       SB_DISABLED, BAR_CSTRORM_INTMEM);
1724d14abf15SRobert Mustacchi 
1725*9b622488SToomas Soome 
1726d14abf15SRobert Mustacchi     for (index = 0; index < CSTORM_SYNC_BLOCK_SIZE / sizeof(u32_t); index++) {
1727d14abf15SRobert Mustacchi         LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
1728d14abf15SRobert Mustacchi     }
1729d14abf15SRobert Mustacchi     for (index = 0; index < CSTORM_STATUS_BLOCK_SIZE / sizeof(u32_t); index++) {
1730d14abf15SRobert Mustacchi         LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
1731d14abf15SRobert Mustacchi     }
1732d14abf15SRobert Mustacchi 
1733d14abf15SRobert Mustacchi }
1734d14abf15SRobert Mustacchi 
1735d14abf15SRobert Mustacchi 
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