1d14abf1Robert Mustacchi/*******************************************************************************
2d14abf1Robert Mustacchi * CDDL HEADER START
3d14abf1Robert Mustacchi *
4d14abf1Robert Mustacchi * The contents of this file are subject to the terms of the
5d14abf1Robert Mustacchi * Common Development and Distribution License (the "License").
6d14abf1Robert Mustacchi * You may not use this file except in compliance with the License.
7d14abf1Robert Mustacchi *
8d14abf1Robert Mustacchi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9d14abf1Robert Mustacchi * or http://www.opensolaris.org/os/licensing.
10d14abf1Robert Mustacchi * See the License for the specific language governing permissions
11d14abf1Robert Mustacchi * and limitations under the License.
12d14abf1Robert Mustacchi *
13d14abf1Robert Mustacchi * When distributing Covered Code, include this CDDL HEADER in each
14d14abf1Robert Mustacchi * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15d14abf1Robert Mustacchi * If applicable, add the following below this CDDL HEADER, with the
16d14abf1Robert Mustacchi * fields enclosed by brackets "[]" replaced with your own identifying
17d14abf1Robert Mustacchi * information: Portions Copyright [yyyy] [name of copyright owner]
18d14abf1Robert Mustacchi *
19d14abf1Robert Mustacchi * CDDL HEADER END
20d14abf1Robert Mustacchi *
21d14abf1Robert Mustacchi * Copyright 2014 QLogic Corporation
22d14abf1Robert Mustacchi * The contents of this file are subject to the terms of the
23d14abf1Robert Mustacchi * QLogic End User License (the "License").
24d14abf1Robert Mustacchi * You may not use this file except in compliance with the License.
25d14abf1Robert Mustacchi *
26d14abf1Robert Mustacchi * You can obtain a copy of the License at
27d14abf1Robert Mustacchi * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
28d14abf1Robert Mustacchi * QLogic_End_User_Software_License.txt
29d14abf1Robert Mustacchi * See the License for the specific language governing permissions
30d14abf1Robert Mustacchi * and limitations under the License.
31d14abf1Robert Mustacchi *
32d14abf1Robert Mustacchi *
33d14abf1Robert Mustacchi * Module Description:
34d14abf1Robert Mustacchi *      This file contains functions that handle HW and FW attention
35d14abf1Robert Mustacchi *
36d14abf1Robert Mustacchi ******************************************************************************/
37d14abf1Robert Mustacchi
38d14abf1Robert Mustacchi#include "lm5710.h"
39d14abf1Robert Mustacchi#include "general_atten_bits.h"
40d14abf1Robert Mustacchi#include "aeu_inputs.h"
41d14abf1Robert Mustacchi#include "command.h"
42d14abf1Robert Mustacchi
43d14abf1Robert Mustacchistatic INLINE void lm_inc_er_debug_idx(lm_device_t * pdev)
44d14abf1Robert Mustacchi{
45d14abf1Robert Mustacchi    pdev->debug_info.curr_er_debug_idx++;
46d14abf1Robert Mustacchi    if (pdev->debug_info.curr_er_debug_idx == MAX_ER_DEBUG_ENTRIES)
47d14abf1Robert Mustacchi    {
48d14abf1Robert Mustacchi        pdev->debug_info.curr_er_debug_idx=0;
49d14abf1Robert Mustacchi    }
50d14abf1Robert Mustacchi}
51d14abf1Robert Mustacchi
52d14abf1Robert Mustacchi/**
53d14abf1Robert Mustacchi * @description
54d14abf1Robert Mustacchi *      called from attention handling routines, checks if the
55d14abf1Robert Mustacchi *      attention received is an error which is recoverable via
56d14abf1Robert Mustacchi *      process kill. If error recovery is disabled this
57d14abf1Robert Mustacchi *      function always returns FALSE;
58d14abf1Robert Mustacchi *
59d14abf1Robert Mustacchi * @param pdev
60d14abf1Robert Mustacchi * @param attn_sig : values of the after_invert registers read
61d14abf1Robert Mustacchi *                 in the misc that indicate which attention
62d14abf1Robert Mustacchi *                 occured
63d14abf1Robert Mustacchi *
64d14abf1Robert Mustacchi *
65d14abf1Robert Mustacchi * @return u8_t TRUE: attention requires process_kill. FALSE o/w
66d14abf1Robert Mustacchi */
67d14abf1Robert Mustacchiu8_t lm_recoverable_error(lm_device_t *pdev, u32_t * attn_sig, u32_t arr_size)
68d14abf1Robert Mustacchi{
69d14abf1Robert Mustacchi    lm_er_debug_info_t * debug_info = NULL;
70d14abf1Robert Mustacchi    u32_t                i;
71d14abf1Robert Mustacchi
72d14abf1Robert Mustacchi    if (!pdev->params.enable_error_recovery || CHIP_IS_E1x(pdev))
73d14abf1Robert Mustacchi    {
74d14abf1Robert Mustacchi        return FALSE;
75d14abf1Robert Mustacchi    }
76d14abf1Robert Mustacchi
77d14abf1Robert Mustacchi    ASSERT_STATIC(ARRSIZE(debug_info->attn_sig) >= MAX_ATTN_REGS);
78d14abf1Robert Mustacchi    DbgBreakIf(arr_size < MAX_ATTN_REGS);
79d14abf1Robert Mustacchi
80d14abf1Robert Mustacchi    if ((attn_sig[0] & HW_PRTY_ASSERT_SET_0) || (attn_sig[1] & HW_PRTY_ASSERT_SET_1) ||
81d14abf1Robert Mustacchi        (attn_sig[2] & HW_PRTY_ASSERT_SET_2) || (attn_sig[3] & HW_PRTY_ASSERT_SET_3))
82d14abf1Robert Mustacchi    {
83d14abf1Robert Mustacchi        /* Parity Error... Assuming we only enable parities we can deal with
84d14abf1Robert Mustacchi         * this is a recoverable error...
85d14abf1Robert Mustacchi         */
86d14abf1Robert Mustacchi        debug_info = &((pdev)->debug_info.er_debug_info[pdev->debug_info.curr_er_debug_idx]);
87d14abf1Robert Mustacchi        for (i = 0; i < arr_size; i++)
88d14abf1Robert Mustacchi        {
89d14abf1Robert Mustacchi            debug_info->attn_sig[i] = attn_sig[i];
90d14abf1Robert Mustacchi        }
91d14abf1Robert Mustacchi        lm_inc_er_debug_idx(pdev);
92d14abf1Robert Mustacchi
93d14abf1Robert Mustacchi        /* TODO: maybe get GRCDump here in the future... */
94d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_recoverable_error: funcid:%d, 0:0x%x, 0:0x%x, 0:0x%x, 0:0x%x\n",
95d14abf1Robert Mustacchi                   ABS_FUNC_ID(pdev), attn_sig[0], attn_sig[1], attn_sig[2], attn_sig[3]);
96d14abf1Robert Mustacchi
97d14abf1Robert Mustacchi        return TRUE;
98d14abf1Robert Mustacchi    }
99d14abf1Robert Mustacchi
100d14abf1Robert Mustacchi    /* HW Attentions (other than parity ) */
101d14abf1Robert Mustacchi    if (attn_sig[1] & HW_INTERRUT_ASSERT_SET_1)
102d14abf1Robert Mustacchi    {
103d14abf1Robert Mustacchi        /* QM Interrupt is recoverable */
104d14abf1Robert Mustacchi        if (attn_sig[1] & AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT)
105d14abf1Robert Mustacchi        {
106d14abf1Robert Mustacchi            debug_info = &((pdev)->debug_info.er_debug_info[pdev->debug_info.curr_er_debug_idx]);
107d14abf1Robert Mustacchi            for (i = 0; i < arr_size; i++)
108d14abf1Robert Mustacchi            {
109d14abf1Robert Mustacchi                debug_info->attn_sig[i] = attn_sig[i];
110d14abf1Robert Mustacchi            }
111d14abf1Robert Mustacchi            lm_inc_er_debug_idx(pdev);
112d14abf1Robert Mustacchi
113d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_recoverable_error: funcid:%d, 0:0x%x, 0:0x%x, 0:0x%x, 0:0x%x\n",
114d14abf1Robert Mustacchi                   ABS_FUNC_ID(pdev), attn_sig[0], attn_sig[1], attn_sig[2], attn_sig[3]);
115d14abf1Robert Mustacchi            return TRUE;
116d14abf1Robert Mustacchi        }
117d14abf1Robert Mustacchi
118d14abf1Robert Mustacchi    }
119d14abf1Robert Mustacchi
120d14abf1Robert Mustacchi    if (attn_sig[3] & EVEREST_GEN_ATTN_IN_USE_MASK)
121d14abf1Robert Mustacchi    {
122d14abf1Robert Mustacchi        if ( GENERAL_ATTEN_OFFSET(ERROR_RECOVERY_ATTENTION_BIT) & attn_sig[3])
123d14abf1Robert Mustacchi        {
124d14abf1Robert Mustacchi            debug_info = &((pdev)->debug_info.er_debug_info[pdev->debug_info.curr_er_debug_idx]);
125d14abf1Robert Mustacchi            for (i = 0; i < arr_size; i++)
126d14abf1Robert Mustacchi            {
127d14abf1Robert Mustacchi                debug_info->attn_sig[i] = attn_sig[i];
128d14abf1Robert Mustacchi            }
129d14abf1Robert Mustacchi            lm_inc_er_debug_idx(pdev);
130d14abf1Robert Mustacchi
131d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_recoverable_error: funcid:%d, 0:0x%x, 0:0x%x, 0:0x%x, 0:0x%x\n",
132d14abf1Robert Mustacchi                   ABS_FUNC_ID(pdev), attn_sig[0], attn_sig[1], attn_sig[2], attn_sig[3]);
133d14abf1Robert Mustacchi            return TRUE;
134d14abf1Robert Mustacchi        }
135d14abf1Robert Mustacchi    }
136d14abf1Robert Mustacchi
137d14abf1Robert Mustacchi    return FALSE;
138d14abf1Robert Mustacchi}
139d14abf1Robert Mustacchi
140d14abf1Robert Mustacchivoid enable_blocks_attention(struct _lm_device_t *pdev)
141d14abf1Robert Mustacchi{
142d14abf1Robert Mustacchi    u32_t val = 0;
143d14abf1Robert Mustacchi
144d14abf1Robert Mustacchi    REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0);
145d14abf1Robert Mustacchi    if (!CHIP_IS_E1x(pdev))
146d14abf1Robert Mustacchi    {
147d14abf1Robert Mustacchi        REG_WR(pdev,PXP_REG_PXP_INT_MASK_1, (PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS
148d14abf1Robert Mustacchi                                             | PXP_PXP_INT_MASK_1_REG_HST_VF_DISABLED_ACCESS /*Temporary solution*/
149d14abf1Robert Mustacchi                                             | PXP_PXP_INT_MASK_1_REG_HST_PERMISSION_VIOLATION) /*Win8 MMIO (security test)???*/);
150d14abf1Robert Mustacchi    }
151d14abf1Robert Mustacchi    REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0);
152d14abf1Robert Mustacchi    /* CFC_REG_CFC_INT_MASK see in init_cfc_common */
153d14abf1Robert Mustacchi
154d14abf1Robert Mustacchi
155d14abf1Robert Mustacchi    //mask read length error interrupts in brb for parser (parsing unit and 'checksum and crc' unit)
156d14abf1Robert Mustacchi    //these errors are legal (PU reads fixe length and CAC can cause read length error on truncated packets)
157d14abf1Robert Mustacchi    REG_WR(pdev,BRB1_REG_BRB1_INT_MASK ,0xFC00);
158d14abf1Robert Mustacchi
159d14abf1Robert Mustacchi    REG_WR(pdev,QM_REG_QM_INT_MASK ,0);
160d14abf1Robert Mustacchi    REG_WR(pdev,TM_REG_TM_INT_MASK ,0);
161d14abf1Robert Mustacchi    REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_0 ,0);
162d14abf1Robert Mustacchi    REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_1 ,0);
163d14abf1Robert Mustacchi    REG_WR(pdev,XCM_REG_XCM_INT_MASK ,0);
164d14abf1Robert Mustacchi    //REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_0 ,0);
165d14abf1Robert Mustacchi    //REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_1 ,0);
166d14abf1Robert Mustacchi    REG_WR(pdev,USDM_REG_USDM_INT_MASK_0 ,0);
167d14abf1Robert Mustacchi    REG_WR(pdev,USDM_REG_USDM_INT_MASK_1 ,0);
168d14abf1Robert Mustacchi    REG_WR(pdev,UCM_REG_UCM_INT_MASK ,0);
169d14abf1Robert Mustacchi    //REG_WR(pdev,USEM_REG_USEM_INT_MASK_0 ,0);
170d14abf1Robert Mustacchi    //REG_WR(pdev,USEM_REG_USEM_INT_MASK_1 ,0);
171d14abf1Robert Mustacchi    REG_WR(pdev,GRCBASE_UPB+PB_REG_PB_INT_MASK ,0);
172d14abf1Robert Mustacchi    REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_0 ,0);
173d14abf1Robert Mustacchi    REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_1 ,0);
174d14abf1Robert Mustacchi    REG_WR(pdev,CCM_REG_CCM_INT_MASK ,0);
175d14abf1Robert Mustacchi    //REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_0 ,0);
176d14abf1Robert Mustacchi    //REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_1 ,0);
177d14abf1Robert Mustacchi    val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
178d14abf1Robert Mustacchi          PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
179d14abf1Robert Mustacchi          PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
180d14abf1Robert Mustacchi    if (!CHIP_IS_E1x(pdev))
181d14abf1Robert Mustacchi    {
182d14abf1Robert Mustacchi        val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
183d14abf1Robert Mustacchi               PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
184d14abf1Robert Mustacchi    }
185d14abf1Robert Mustacchi    REG_WR(pdev, PXP2_REG_PXP2_INT_MASK_0, val);
186d14abf1Robert Mustacchi
187d14abf1Robert Mustacchi    REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_0 ,0);
188d14abf1Robert Mustacchi    REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_1 ,0);
189d14abf1Robert Mustacchi    REG_WR(pdev,TCM_REG_TCM_INT_MASK ,0);
190d14abf1Robert Mustacchi    //REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_0 ,0);
191d14abf1Robert Mustacchi    //REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_1 ,0);
192d14abf1Robert Mustacchi    REG_WR(pdev,CDU_REG_CDU_INT_MASK ,0);
193d14abf1Robert Mustacchi    REG_WR(pdev,DMAE_REG_DMAE_INT_MASK ,0);
194d14abf1Robert Mustacchi    //REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_MISC_INT_MASK ,0);
195d14abf1Robert Mustacchi    //MASK BIT 3,4
196d14abf1Robert Mustacchi    REG_WR(pdev,PBF_REG_PBF_INT_MASK ,0X18);
197d14abf1Robert Mustacchi
198d14abf1Robert Mustacchi}
199d14abf1Robert Mustacchi
200d14abf1Robert Mustacchivoid disable_blocks_attention(struct _lm_device_t *pdev)
201d14abf1Robert Mustacchi{
202d14abf1Robert Mustacchi#define MASK_VALUE_GENERATE(_val) ((u32_t)((((u64_t)0x1)<<_val)-1))
203d14abf1Robert Mustacchi    typedef struct _block_mask_info_t
204d14abf1Robert Mustacchi    {
205d14abf1Robert Mustacchi        u32_t reg_offset;    /* the register offset */
206d14abf1Robert Mustacchi        u32_t mask_value[3]; /* the mask value per hw (e1 =0 /e1.5 = 1/e2 = 2)*/
207d14abf1Robert Mustacchi    } block_mask_info_t;
208d14abf1Robert Mustacchi
209d14abf1Robert Mustacchi    u8_t  chip_idx   = 0;
210d14abf1Robert Mustacchi    u32_t mask_idx   = 0;
211d14abf1Robert Mustacchi    u32_t val        = 0;
212d14abf1Robert Mustacchi    u32_t offset     = 0;
213d14abf1Robert Mustacchi    u32_t mask_value = 0;
214d14abf1Robert Mustacchi
215d14abf1Robert Mustacchi    static const block_mask_info_t init_mask_values_arr[] =
216d14abf1Robert Mustacchi    {
217d14abf1Robert Mustacchi        { ATC_REG_ATC_INT_MASK,           { 0,
218d14abf1Robert Mustacchi                                            0,
219d14abf1Robert Mustacchi                                            6 } },
220d14abf1Robert Mustacchi
221d14abf1Robert Mustacchi        { BRB1_REG_BRB1_INT_MASK,         { 19,
222d14abf1Robert Mustacchi                                            19,
223d14abf1Robert Mustacchi                                            19} },
224d14abf1Robert Mustacchi
225d14abf1Robert Mustacchi        { CCM_REG_CCM_INT_MASK,           { 11,
226d14abf1Robert Mustacchi                                            11,
227d14abf1Robert Mustacchi                                            11 } },
228d14abf1Robert Mustacchi
229d14abf1Robert Mustacchi        { CDU_REG_CDU_INT_MASK,           { 7,
230d14abf1Robert Mustacchi                                            7,
231d14abf1Robert Mustacchi                                            7 } },
232d14abf1Robert Mustacchi
233d14abf1Robert Mustacchi        { CFC_REG_CFC_INT_MASK,           { 2,
234d14abf1Robert Mustacchi                                            2,
235d14abf1Robert Mustacchi                                            2  } },
236d14abf1Robert Mustacchi
237d14abf1Robert Mustacchi        { CSDM_REG_CSDM_INT_MASK_0,       { 32,
238d14abf1Robert Mustacchi                                            32,
239d14abf1Robert Mustacchi                                            32 } },
240d14abf1Robert Mustacchi
241d14abf1Robert Mustacchi        { CSDM_REG_CSDM_INT_MASK_1,       { 10,
242d14abf1Robert Mustacchi                                            10,
243d14abf1Robert Mustacchi                                            11 } },
244d14abf1Robert Mustacchi
245d14abf1Robert Mustacchi#if 0
246d14abf1Robert Mustacchi        { CSEM_REG_CSEM_INT_MASK_0,       { 32,
247d14abf1Robert Mustacchi                                            32,
248d14abf1Robert Mustacchi                                            32 } },
249d14abf1Robert Mustacchi
250d14abf1Robert Mustacchi        { CSEM_REG_CSEM_INT_MASK_1,       { 10,
251d14abf1Robert Mustacchi                                            11,
252d14abf1Robert Mustacchi                                            11} },
253d14abf1Robert Mustacchi
254d14abf1Robert Mustacchi        { DBG_REG_DBG_INT_MASK,           { 2,
255d14abf1Robert Mustacchi                                            2,
256d14abf1Robert Mustacchi                                            2 } },
257d14abf1Robert Mustacchi#endif //0
258d14abf1Robert Mustacchi
259d14abf1Robert Mustacchi        { DMAE_REG_DMAE_INT_MASK,         { 2,
260d14abf1Robert Mustacchi                                            2,
261d14abf1Robert Mustacchi                                            2 } },
262d14abf1Robert Mustacchi
263d14abf1Robert Mustacchi        { DORQ_REG_DORQ_INT_MASK,         { 5,
264d14abf1Robert Mustacchi                                            5,
265d14abf1Robert Mustacchi                                            6 } },
266d14abf1Robert Mustacchi#if 0
267d14abf1Robert Mustacchi        { HC_REG_HC_INT_MASK,             { 7,
268d14abf1Robert Mustacchi                                            7,
269d14abf1Robert Mustacchi                                            7 } },
270d14abf1Robert Mustacchi#endif //0
271d14abf1Robert Mustacchi
272d14abf1Robert Mustacchi        { IGU_REG_IGU_INT_MASK,           { 0,
273d14abf1Robert Mustacchi                                            0,
274d14abf1Robert Mustacchi                                            11 } },
275d14abf1Robert Mustacchi#if 0
276d14abf1Robert Mustacchi        { MISC_REGISTERS_MISC_INT_MASK,   { 4,
277d14abf1Robert Mustacchi                                            4,
278d14abf1Robert Mustacchi                                            8 } },
279d14abf1Robert Mustacchi
280d14abf1Robert Mustacchi        { NIG_REGISTERS_NIG_INT_MASK_0,   { 32,
281d14abf1Robert Mustacchi                                            32,
282d14abf1Robert Mustacchi                                            32 } },
283d14abf1Robert Mustacchi
284d14abf1Robert Mustacchi        { NIG_REGISTERS_NIG_INT_MASK_1,   { 2,
285d14abf1Robert Mustacchi                                            4,
286d14abf1Robert Mustacchi                                            14 } },
287d14abf1Robert Mustacchi
288d14abf1Robert Mustacchi        { PB_REGISTERS_PB_INT_MASK,       { 2,
289d14abf1Robert Mustacchi                                            2,
290d14abf1Robert Mustacchi                                            2} },
291d14abf1Robert Mustacchi#endif // 0
292d14abf1Robert Mustacchi
293d14abf1Robert Mustacchi        { PBF_REG_PBF_INT_MASK,           { 5,
294d14abf1Robert Mustacchi                                            5,
295d14abf1Robert Mustacchi                                            7 } },
296d14abf1Robert Mustacchi
297d14abf1Robert Mustacchi        { PGLUE_B_REG_PGLUE_B_INT_MASK,   { 0,
298d14abf1Robert Mustacchi                                            0,
299d14abf1Robert Mustacchi                                            9 } },
300d14abf1Robert Mustacchi#if 0
301d14abf1Robert Mustacchi        { PRS_REG_PRS_INT_MASK,           { 1,
302d14abf1Robert Mustacchi                                            1,
303d14abf1Robert Mustacchi                                            1 } },
304d14abf1Robert Mustacchi#endif // 0
305d14abf1Robert Mustacchi
306d14abf1Robert Mustacchi        { PXP2_REG_PXP2_INT_MASK_0,       { 25,
307d14abf1Robert Mustacchi                                            32,
308d14abf1Robert Mustacchi                                            32 } },
309d14abf1Robert Mustacchi
310d14abf1Robert Mustacchi#if 0
311d14abf1Robert Mustacchi        { PXP2_REG_PXP2_INT_MASK_1,       { 0,
312d14abf1Robert Mustacchi                                            6,
313d14abf1Robert Mustacchi                                            16} },
314d14abf1Robert Mustacchi#endif //0
315d14abf1Robert Mustacchi
316d14abf1Robert Mustacchi        { PXP_REG_PXP_INT_MASK_0,         { 32,
317d14abf1Robert Mustacchi                                            32,
318d14abf1Robert Mustacchi                                            32 } },
319d14abf1Robert Mustacchi
320d14abf1Robert Mustacchi        { PXP_REG_PXP_INT_MASK_1,         { 5,
321d14abf1Robert Mustacchi                                            5,
322d14abf1Robert Mustacchi                                            8 } },
323d14abf1Robert Mustacchi
324d14abf1Robert Mustacchi        { QM_REG_QM_INT_MASK,             { 2,
325d14abf1Robert Mustacchi                                            2,
326d14abf1Robert Mustacchi                                            14 } },
327d14abf1Robert Mustacchi#if 0
328d14abf1Robert Mustacchi        { SEM_FAST_REG_SEM_FAST_INT_MASK, { 1, // This offset is actually 4 different registers (per SEM)
329d14abf1Robert Mustacchi                                            1,
330d14abf1Robert Mustacchi                                            1} },
331d14abf1Robert Mustacchi
332d14abf1Robert Mustacchi        { SRC_REG_SRC_INT_MASK,           { 1,
333d14abf1Robert Mustacchi                                            3,
334d14abf1Robert Mustacchi                                            3 } },
335d14abf1Robert Mustacchi#endif //0
336d14abf1Robert Mustacchi
337d14abf1Robert Mustacchi        { TCM_REG_TCM_INT_MASK,           { 11,
338d14abf1Robert Mustacchi                                            11,
339d14abf1Robert Mustacchi                                            11 } },
340d14abf1Robert Mustacchi
341d14abf1Robert Mustacchi        { TM_REG_TM_INT_MASK,             { 1,
342d14abf1Robert Mustacchi                                            1,
343d14abf1Robert Mustacchi                                            1} },
344d14abf1Robert Mustacchi
345d14abf1Robert Mustacchi        { TSDM_REG_TSDM_INT_MASK_0,       { 32,
346d14abf1Robert Mustacchi                                            32,
347d14abf1Robert Mustacchi                                            32 } },
348d14abf1Robert Mustacchi
349d14abf1Robert Mustacchi        { TSDM_REG_TSDM_INT_MASK_1,       { 10,
350d14abf1Robert Mustacchi                                            10,
351d14abf1Robert Mustacchi                                            11 } },
352d14abf1Robert Mustacchi#if 0
353d14abf1Robert Mustacchi        { TSEM_REG_TSEM_INT_MASK_0,       { 32,
354d14abf1Robert Mustacchi                                            32,
355d14abf1Robert Mustacchi                                            32 } },
356d14abf1Robert Mustacchi
357d14abf1Robert Mustacchi        { TSEM_REG_TSEM_INT_MASK_1,       { 10,
358d14abf1Robert Mustacchi                                            11,
359d14abf1Robert Mustacchi                                            13 } },
360d14abf1Robert Mustacchi#endif // 0
361d14abf1Robert Mustacchi
362d14abf1Robert Mustacchi        { UCM_REG_UCM_INT_MASK,           { 11,
363d14abf1Robert Mustacchi                                            11,
364d14abf1Robert Mustacchi                                            11} },
365d14abf1Robert Mustacchi
366d14abf1Robert Mustacchi        { USDM_REG_USDM_INT_MASK_0,       { 32,
367d14abf1Robert Mustacchi                                            32,
368d14abf1Robert Mustacchi                                            32 } },
369d14abf1Robert Mustacchi
370d14abf1Robert Mustacchi        { USDM_REG_USDM_INT_MASK_1,       { 10,
371d14abf1Robert Mustacchi                                            10,
372d14abf1Robert Mustacchi                                            11 } },
373d14abf1Robert Mustacchi#if 0
374d14abf1Robert Mustacchi        { USEM_REG_USEM_INT_MASK_0,       { 32,
375d14abf1Robert Mustacchi                                            32,
376d14abf1Robert Mustacchi                                            32 } },
377d14abf1Robert Mustacchi
378d14abf1Robert Mustacchi        { USEM_REG_USEM_INT_MASK_1,       { 10,
379d14abf1Robert Mustacchi                                            11,
380d14abf1Robert Mustacchi                                            11 } },
381d14abf1Robert Mustacchi#endif //0
382d14abf1Robert Mustacchi
383d14abf1Robert Mustacchi        { VFC_REG_VFC_INT_MASK,           { 0,
384d14abf1Robert Mustacchi                                            0,
385d14abf1Robert Mustacchi                                            1 } },
386d14abf1Robert Mustacchi
387d14abf1Robert Mustacchi        { XCM_REG_XCM_INT_MASK,           { 14,
388d14abf1Robert Mustacchi                                            14,
389d14abf1Robert Mustacchi                                            14 } },
390d14abf1Robert Mustacchi
391d14abf1Robert Mustacchi        { XSDM_REG_XSDM_INT_MASK_0,       { 32,
392d14abf1Robert Mustacchi                                            32,
393d14abf1Robert Mustacchi                                            32 } },
394d14abf1Robert Mustacchi
395d14abf1Robert Mustacchi        { XSDM_REG_XSDM_INT_MASK_1,       { 10,
396d14abf1Robert Mustacchi                                            10,
397d14abf1Robert Mustacchi                                            11} },
398d14abf1Robert Mustacchi#if 0
399d14abf1Robert Mustacchi        { XSEM_REG_XSEM_INT_MASK_0,      { 32,
400d14abf1Robert Mustacchi                                           32,
401d14abf1Robert Mustacchi                                           32 } },
402d14abf1Robert Mustacchi
403d14abf1Robert Mustacchi        { XSEM_REG_XSEM_INT_MASK_1,      { 10,
404d14abf1Robert Mustacchi                                           11,
405d14abf1Robert Mustacchi                                           13 } } ,
406d14abf1Robert Mustacchi#endif // 0
407d14abf1Robert Mustacchi    }; // init_mask_values_arr
408d14abf1Robert Mustacchi
409d14abf1Robert Mustacchi    if (IS_VFDEV(pdev))
410d14abf1Robert Mustacchi    {
411d14abf1Robert Mustacchi        return;
412d14abf1Robert Mustacchi    }
413d14abf1Robert Mustacchi    if CHIP_IS_E1( pdev )
414d14abf1Robert Mustacchi    {
415d14abf1Robert Mustacchi        chip_idx = 0; // E1.0
416d14abf1Robert Mustacchi    }
417d14abf1Robert Mustacchi    else if CHIP_IS_E1H(pdev)
418d14abf1Robert Mustacchi    {
419d14abf1Robert Mustacchi        chip_idx = 1; // E1.5
420d14abf1Robert Mustacchi    }
421d14abf1Robert Mustacchi    else if CHIP_IS_E2E3(pdev)
422d14abf1Robert Mustacchi    {
423d14abf1Robert Mustacchi        chip_idx = 2; // E2
424d14abf1Robert Mustacchi    }
425d14abf1Robert Mustacchi    else
426d14abf1Robert Mustacchi    {
427d14abf1Robert Mustacchi        // New chip!!!
428d14abf1Robert Mustacchi        DbgBreakIf(1); // E??
429d14abf1Robert Mustacchi    }
430d14abf1Robert Mustacchi
431d14abf1Robert Mustacchi    DbgBreakIf( chip_idx >= ARRSIZE( init_mask_values_arr[0].mask_value ) );
432d14abf1Robert Mustacchi
433d14abf1Robert Mustacchi    for( mask_idx = 0; mask_idx < ARRSIZE(init_mask_values_arr);  mask_idx++ )
434d14abf1Robert Mustacchi    {
435d14abf1Robert Mustacchi        mask_value = init_mask_values_arr[mask_idx].mask_value[chip_idx] ;
436d14abf1Robert Mustacchi
437d14abf1Robert Mustacchi        if( mask_value )
438d14abf1Robert Mustacchi        {
439d14abf1Robert Mustacchi            val        = MASK_VALUE_GENERATE(mask_value);
440d14abf1Robert Mustacchi            offset     = init_mask_values_arr[mask_idx].reg_offset;
441d14abf1Robert Mustacchi            REG_WR(pdev, offset, val );
442d14abf1Robert Mustacchi        }
443d14abf1Robert Mustacchi    }
444d14abf1Robert Mustacchi    /*
445d14abf1Robert Mustacchi
446d14abf1Robert Mustacchi    REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0xffffffff);
447d14abf1Robert Mustacchi    if (IS_E2(pdev)) {
448d14abf1Robert Mustacchi        REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0xff);
449d14abf1Robert Mustacchi    } else {
450d14abf1Robert Mustacchi    REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0x1f);
451d14abf1Robert Mustacchi    }
452d14abf1Robert Mustacchi    REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0x1f);
453d14abf1Robert Mustacchi    REG_WR(pdev,CFC_REG_CFC_INT_MASK ,0x3);
454d14abf1Robert Mustacchi    REG_WR(pdev,QM_REG_QM_INT_MASK ,0x3);
455d14abf1Robert Mustacchi    REG_WR(pdev,TM_REG_TM_INT_MASK ,0x1);
456d14abf1Robert Mustacchi    REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_0 ,0xffffffff);
457d14abf1Robert Mustacchi    REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_1 ,0x3ff);
458d14abf1Robert Mustacchi    REG_WR(pdev,XCM_REG_XCM_INT_MASK,0x3fff);
459d14abf1Robert Mustacchi    //REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_0 ,0);
460d14abf1Robert Mustacchi    //REG_WR(pdev,XSEM_REG_XSEM_INT_MASK_1 ,0);
461d14abf1Robert Mustacchi    REG_WR(pdev,USDM_REG_USDM_INT_MASK_0 ,0xffffffff);
462d14abf1Robert Mustacchi    REG_WR(pdev,USDM_REG_USDM_INT_MASK_1 ,0x3ff);
463d14abf1Robert Mustacchi    REG_WR(pdev,UCM_REG_UCM_INT_MASK ,0x7ff);
464d14abf1Robert Mustacchi    //REG_WR(pdev,USEM_REG_USEM_INT_MASK_0 ,0);
465d14abf1Robert Mustacchi    //REG_WR(pdev,USEM_REG_USEM_INT_MASK_1 ,0);
466d14abf1Robert Mustacchi    REG_WR(pdev,GRCBASE_UPB+PB_REG_PB_INT_MASK ,0x3);
467d14abf1Robert Mustacchi    REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_0 ,0xffffffff);
468d14abf1Robert Mustacchi    REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_1 ,0x3ff);
469d14abf1Robert Mustacchi    REG_WR(pdev,CCM_REG_CCM_INT_MASK ,0x7ff);
470d14abf1Robert Mustacchi    //REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_0 ,0);
471d14abf1Robert Mustacchi    //REG_WR(pdev,CSEM_REG_CSEM_INT_MASK_1 ,0);
472d14abf1Robert Mustacchi
473d14abf1Robert Mustacchi    REG_WR(pdev,PXP2_REG_PXP2_INT_MASK_0,0xffffffff);
474d14abf1Robert Mustacchi
475d14abf1Robert Mustacchi    REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_0 ,0xffffffff);
476d14abf1Robert Mustacchi    REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_1 ,0x3ff);
477d14abf1Robert Mustacchi    REG_WR(pdev,TCM_REG_TCM_INT_MASK ,0x7ff);
478d14abf1Robert Mustacchi    //REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_0 ,0);
479d14abf1Robert Mustacchi    //REG_WR(pdev,TSEM_REG_TSEM_INT_MASK_1 ,0);
480d14abf1Robert Mustacchi    REG_WR(pdev,CDU_REG_CDU_INT_MASK ,0x7f);
481d14abf1Robert Mustacchi    REG_WR(pdev,DMAE_REG_DMAE_INT_MASK ,0x3);
482d14abf1Robert Mustacchi    //REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_MISC_INT_MASK ,0);
483d14abf1Robert Mustacchi    //MASK BIT 3,4
484d14abf1Robert Mustacchi    REG_WR(pdev,PBF_REG_PBF_INT_MASK ,0x1f);
485d14abf1Robert Mustacchi    */
486d14abf1Robert Mustacchi
487d14abf1Robert Mustacchi    // disable MCP's attentions
488d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,0);
489d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_1,0);
490d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2,0);
491d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_3,0);
492d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,0);
493d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_1,0);
494d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2,0);
495d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_3,0);
496d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4,0);
497d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5,0);
498d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6,0);
499d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7,0);
500d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4,0);
501d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5,0);
502d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6,0);
503d14abf1Robert Mustacchi    REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7,0);
504d14abf1Robert Mustacchi}
505d14abf1Robert Mustacchi
506d14abf1Robert Mustacchivoid lm_reset_mask_attn(struct _lm_device_t *pdev)
507d14abf1Robert Mustacchi{
508d14abf1Robert Mustacchi    // mask the pxp attentions
509d14abf1Robert Mustacchi    REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0xffffffff); // 32 bits
510d14abf1Robert Mustacchi    if (CHIP_IS_E1x(pdev))
511d14abf1Robert Mustacchi    {
512d14abf1Robert Mustacchi        REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0x1f); // 5 bits
513d14abf1Robert Mustacchi    }
514d14abf1Robert Mustacchi    else
515d14abf1Robert Mustacchi    {
516d14abf1Robert Mustacchi        REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0xff); // 8 bits
517d14abf1Robert Mustacchi    }
518d14abf1Robert Mustacchi    REG_WR(pdev,PXP2_REG_PXP2_INT_MASK_0,0xffffffff); // 32 bits
519d14abf1Robert Mustacchi
520d14abf1Robert Mustacchi    /* We never unmask this register so no need to re-mask it*/
521d14abf1Robert Mustacchi    //REG_WR(pdev,PXP2_REG_PXP2_INT_MASK_1,0x3f); // 32 bits
522d14abf1Robert Mustacchi}
523d14abf1Robert Mustacchi
524d14abf1Robert Mustacchistatic void lm_latch_attn_everest_processing(lm_device_t *pdev, u32_t sig_word_aft_inv)
525d14abf1Robert Mustacchi{
526d14abf1Robert Mustacchi    u32_t latch_bit_to_clr = 0;
527d14abf1Robert Mustacchi    u32_t val              = 0;
528d14abf1Robert Mustacchi    u32_t offset           = 0;
529d14abf1Robert Mustacchi
530d14abf1Robert Mustacchi    //pass over all latched attentions
531d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR);
532d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
533d14abf1Robert Mustacchi    {
534d14abf1Robert Mustacchi        latch_bit_to_clr = 0x1;
535d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
536d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_RBCR received!!!\n");
537d14abf1Robert Mustacchi        DbgBreakIfAll(1);
538d14abf1Robert Mustacchi    }
539d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT);
540d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
541d14abf1Robert Mustacchi    {
542d14abf1Robert Mustacchi        latch_bit_to_clr = 0x2;
543d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
544d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_RBCT received!!!\n");
545d14abf1Robert Mustacchi        DbgBreakIfAll(1);
546d14abf1Robert Mustacchi    }
547d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN);
548d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
549d14abf1Robert Mustacchi    {
550d14abf1Robert Mustacchi        latch_bit_to_clr = 0x4;
551d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
552d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_RBCN received!!!\n");
553d14abf1Robert Mustacchi        DbgBreakIfAll(1);
554d14abf1Robert Mustacchi    }
555d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU);
556d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
557d14abf1Robert Mustacchi    {
558d14abf1Robert Mustacchi        latch_bit_to_clr = 0x8;
559d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
560d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_RBCU received!!!\n");
561d14abf1Robert Mustacchi        DbgBreakIfAll(1);
562d14abf1Robert Mustacchi    }
563d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP);
564d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
565d14abf1Robert Mustacchi    {
566d14abf1Robert Mustacchi        latch_bit_to_clr = 0x10;
567d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
568d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_RBCP received!!! \n");
569d14abf1Robert Mustacchi        DbgBreakIfAll(1);
570d14abf1Robert Mustacchi    }
571d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC);
572d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
573d14abf1Robert Mustacchi    {
574d14abf1Robert Mustacchi#define GRC_TIMEOUT_MASK_ADDRESS(_val)  ( (_val)     & ((1<<19)-1)) // 0x000fffff
575d14abf1Robert Mustacchi#define GRC_TIMEOUT_MASK_FUNCTION(_val) ( (_val>>20) & ((1<<3)-1))  // 0x00700000
576d14abf1Robert Mustacchi#define GRC_TIMEOUT_MASK_MASTER(_val)   ( (_val>>24) & ((1<<4)-1))  // 0x0f000000
577d14abf1Robert Mustacchi
578d14abf1Robert Mustacchi        u32_t       addr                            = 0;
579d14abf1Robert Mustacchi        u32_t       func                            = 0;
580d14abf1Robert Mustacchi        u32_t       master                          = 0;
581d14abf1Robert Mustacchi        u32_t       grc_timeout_cnt                 = 0;
582d14abf1Robert Mustacchi        u8_t        b_assert                        = TRUE;
583d14abf1Robert Mustacchi        u8_t        b_nig_reset_called              = lm_is_nig_reset_called(pdev);
584d14abf1Robert Mustacchi        const u32_t grc_timeout_max_ignore          = pdev->params.grc_timeout_max_ignore;
585d14abf1Robert Mustacchi
586d14abf1Robert Mustacchi        latch_bit_to_clr = 0x20;
587d14abf1Robert Mustacchi
588d14abf1Robert Mustacchi        // we check if nig reset was done
589d14abf1Robert Mustacchi        if( b_nig_reset_called )
590d14abf1Robert Mustacchi        {
591d14abf1Robert Mustacchi            b_assert = FALSE;
592d14abf1Robert Mustacchi        }
593d14abf1Robert Mustacchi
594d14abf1Robert Mustacchi        if (!CHIP_IS_E1(pdev))
595d14abf1Robert Mustacchi        {
596d14abf1Robert Mustacchi            val    = REG_RD(pdev, MISC_REG_GRC_TIMEOUT_ATTN);
597d14abf1Robert Mustacchi            addr   = GRC_TIMEOUT_MASK_ADDRESS(val);
598d14abf1Robert Mustacchi            func   = GRC_TIMEOUT_MASK_FUNCTION(val);
599d14abf1Robert Mustacchi            master = GRC_TIMEOUT_MASK_MASTER(val);
600d14abf1Robert Mustacchi
601d14abf1Robert Mustacchi            // in non E1 we can verify it is mcp cause (due to nig probably)
602d14abf1Robert Mustacchi            if( 2 != master ) // 2 is mcp cause
603d14abf1Robert Mustacchi            {
604d14abf1Robert Mustacchi                b_assert = TRUE;
605d14abf1Robert Mustacchi            }
606d14abf1Robert Mustacchi        }
607d14abf1Robert Mustacchi
608d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
609d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_TIMEOUT_GRC received!!! val=0x%08x master=0x%x func=0x%x addr=0x%xx4=0x%X)\n"
610d14abf1Robert Mustacchi                               ,val, master, func, addr, addr*4 );
611d14abf1Robert Mustacchi
612d14abf1Robert Mustacchi        // NOTE: we ignore b_nig_reset_called and ASSERT only according to grc_timeout_max_ignore value (default is 0x10)
613d14abf1Robert Mustacchi
614d14abf1Robert Mustacchi        grc_timeout_cnt = lm_inc_cnt_grc_timeout_ignore(pdev, val);
615d14abf1Robert Mustacchi        // if we are here it means we ignore the ASSERT inc counter
616d14abf1Robert Mustacchi        if( grc_timeout_cnt >= grc_timeout_max_ignore )
617d14abf1Robert Mustacchi        {
618d14abf1Robert Mustacchi            b_assert = TRUE;
619d14abf1Robert Mustacchi        }
620d14abf1Robert Mustacchi        else
621d14abf1Robert Mustacchi        {
622d14abf1Robert Mustacchi            b_assert = FALSE;
623d14abf1Robert Mustacchi        }
624d14abf1Robert Mustacchi
625d14abf1Robert Mustacchi        if( b_assert )
626d14abf1Robert Mustacchi        {
627d14abf1Robert Mustacchi            DbgBreakIf(1);
628d14abf1Robert Mustacchi        }
629d14abf1Robert Mustacchi
630d14abf1Robert Mustacchi        if( b_nig_reset_called )
631d14abf1Robert Mustacchi        {
632d14abf1Robert Mustacchi            // we reset the flag (we "allow" one timeout after nig reset)
633d14abf1Robert Mustacchi            lm_clear_nig_reset_called(pdev);
634d14abf1Robert Mustacchi        }
635d14abf1Robert Mustacchi    }
636d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC);
637d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
638d14abf1Robert Mustacchi    {
639d14abf1Robert Mustacchi        latch_bit_to_clr = 0x40;
640d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
641d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_RSVD_GRC received!!!\n");
642d14abf1Robert Mustacchi        DbgBreakIfAll(1);
643d14abf1Robert Mustacchi    }
644d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_ROM_PARITY_MCP);
645d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
646d14abf1Robert Mustacchi    {
647d14abf1Robert Mustacchi        latch_bit_to_clr = 0x80;
648d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
649d14abf1Robert Mustacchi        val = lm_mcp_check(pdev);
650d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_ROM_PARITY_MCP received!!!\n");
651d14abf1Robert Mustacchi        /* For E2, at the time this code was written (e2-bringup ) the parity is (somehow) expected */
652d14abf1Robert Mustacchi        if (CHIP_IS_E1x(pdev))
653d14abf1Robert Mustacchi        {
654d14abf1Robert Mustacchi            DbgBreakIfAll(1);
655d14abf1Robert Mustacchi        }
656d14abf1Robert Mustacchi        else
657d14abf1Robert Mustacchi        {
658d14abf1Robert Mustacchi            DbgBreakIf(1);
659d14abf1Robert Mustacchi        }
660d14abf1Robert Mustacchi    }
661d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_UM_RX_PARITY_MCP);
662d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
663d14abf1Robert Mustacchi    {
664d14abf1Robert Mustacchi        latch_bit_to_clr = 0x100;
665d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
666d14abf1Robert Mustacchi        val = lm_mcp_check(pdev);
667d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_UM_RX_PARITY_MCP received!!!\n");
668d14abf1Robert Mustacchi        DbgBreakIfAll(1);
669d14abf1Robert Mustacchi    }
670d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_UM_TX_PARITY_MCP);
671d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
672d14abf1Robert Mustacchi    {
673d14abf1Robert Mustacchi        latch_bit_to_clr = 0x200;
674d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
675d14abf1Robert Mustacchi        val = lm_mcp_check(pdev);
676d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_UM_TX_PARITY_MCP received!!!\n");
677d14abf1Robert Mustacchi        DbgBreakIfAll(1);
678d14abf1Robert Mustacchi    }
679d14abf1Robert Mustacchi    offset = GENERAL_ATTEN_OFFSET(LATCHED_ATTN_SCPAD_PARITY_MCP);
680d14abf1Robert Mustacchi    if ( offset & sig_word_aft_inv)
681d14abf1Robert Mustacchi    {
682d14abf1Robert Mustacchi        latch_bit_to_clr = 0x400;
683d14abf1Robert Mustacchi        REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
684d14abf1Robert Mustacchi        val = lm_mcp_check(pdev);
685d14abf1Robert Mustacchi        DbgMessage(pdev, FATAL, "lm_latch_attn_everest_processing: LATCHED_ATTN_SCPAD_PARITY_MCP received!!!\n");
686d14abf1Robert Mustacchi        DbgBreakIfAll(1);
687d14abf1Robert Mustacchi    }
688d14abf1Robert Mustacchi}
689d14abf1Robert Mustacchi
690d14abf1Robert Mustacchistatic void lm_hard_wired_processing(lm_device_t *pdev, u16_t assertion_proc_flgs)
691d14abf1Robert Mustacchi{
692d14abf1Robert Mustacchi    /* processing of highest 8-15 bits of 8 "hard-wired" attention signals toward IGU.
693d14abf1Robert Mustacchi       Excluding NIG & PXP "close the gates"
694d14abf1Robert Mustacchi
695d14abf1Robert Mustacchi       ! No need to lock here since this is an uncommon group whether there is a recovery procedure or not.
696d14abf1Robert Mustacchi
697d14abf1Robert Mustacchi       Signal name         Bit position    SOURCE       Type        Required Destination
698d14abf1Robert Mustacchi       -----------------------------------------------------------------------------
699d14abf1Robert Mustacchi       NIG attention for port0  D8         NIG          Event       MCP/Driver0(PHY)
700d14abf1Robert Mustacchi       SW timer#4 port0         D9         MISC         Event       MCP -> Ignore!
701d14abf1Robert Mustacchi       GPIO#2 port0             D10        MISC         Event       MCP
702d14abf1Robert Mustacchi       GPIO#3 port0             D11        MISC         Event       MCP
703d14abf1Robert Mustacchi       GPIO#4 port0             D12        MISC         Event       MCP
704d14abf1Robert Mustacchi       General attn1            D13        GRC mapped   Attention   MCP/Driver0/Driver1 -> ASSERT!
705d14abf1Robert Mustacchi       General attn2            D14        GRC mapped   Attention   MCP/Driver0/Driver1 -> ASSERT!
706d14abf1Robert Mustacchi       General attn3            D15        GRC mapped   Attention   MCP/Driver0/Driver1 -> ASSERT!
707d14abf1Robert Mustacchi    */
708d14abf1Robert Mustacchi    //TODO: for the required attn signals, need to "clean the hw block" (INT_STS_CLR..)
709d14abf1Robert Mustacchi    if (PORT_ID(pdev) == 0)
710d14abf1Robert Mustacchi    {
711d14abf1Robert Mustacchi#if 0   // Timer 4 is being used by OCBB now
712d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_SW_TIMER_4_FUNC)
713d14abf1Robert Mustacchi        {
714d14abf1Robert Mustacchi            //DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_SW_TIMER_4_FUNC!\n");
715d14abf1Robert Mustacchi            //to deal with this signal, add dispatch func call here
716d14abf1Robert Mustacchi        }
717d14abf1Robert Mustacchi#endif
718d14abf1Robert Mustacchi        if (assertion_proc_flgs & GPIO_2_FUNC)
719d14abf1Robert Mustacchi        {
720d14abf1Robert Mustacchi            DbgMessage(pdev, WARN, "lm_hard_wired_processing: GPIO_1_FUNC!\n");
721d14abf1Robert Mustacchi            //to deal with this signal, add dispatch func call here
722d14abf1Robert Mustacchi        }
723d14abf1Robert Mustacchi        if (assertion_proc_flgs & GPIO_3_FUNC)
724d14abf1Robert Mustacchi        {
725d14abf1Robert Mustacchi            DbgMessage(pdev, WARN, "lm_hard_wired_processing: GPIO_2_FUNC!\n");
726d14abf1Robert Mustacchi            //to deal with this signal, add dispatch func call here
727d14abf1Robert Mustacchi        }
728d14abf1Robert Mustacchi        if (assertion_proc_flgs & GPIO_4_FUNC)
729d14abf1Robert Mustacchi        {
730d14abf1Robert Mustacchi        DbgMessage(pdev, WARN, "lm_hard_wired_processing: GPIO_3_FUNC0!\n");
731d14abf1Robert Mustacchi        // Will be handled in deassertion
732d14abf1Robert Mustacchi        }
733d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_GENERAL_ATTN_1)
734d14abf1Robert Mustacchi        {
735d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_GENERAL_ATTN_1! and clean it!!!\n");
736d14abf1Robert Mustacchi            REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_1,0x0);
737d14abf1Robert Mustacchi        }
738d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_GENERAL_ATTN_2)
739d14abf1Robert Mustacchi        {
740d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_GENERAL_ATTN_2! and clean it!!!\n");
741d14abf1Robert Mustacchi            REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_2,0x0);
742d14abf1Robert Mustacchi        }
743d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_GENERAL_ATTN_3)
744d14abf1Robert Mustacchi        {
745d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_GENERAL_ATTN_3! and clean it!!!\n");
746d14abf1Robert Mustacchi            REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_3,0x0);
747d14abf1Robert Mustacchi        }
748d14abf1Robert Mustacchi    }
749d14abf1Robert Mustacchi    else
750d14abf1Robert Mustacchi    {
751d14abf1Robert Mustacchi        DbgBreakIf(PORT_ID(pdev) != 1);
752d14abf1Robert Mustacchi
753d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_SW_TIMER_4_FUNC1)
754d14abf1Robert Mustacchi        {
755d14abf1Robert Mustacchi            //DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_SW_TIMER_4_FUNC1!\n");
756d14abf1Robert Mustacchi            //to deal with this signal, add dispatch func call here
757d14abf1Robert Mustacchi        }
758d14abf1Robert Mustacchi        if (assertion_proc_flgs & GPIO_2_FUNC1)
759d14abf1Robert Mustacchi        {
760d14abf1Robert Mustacchi            DbgMessage(pdev, WARN, "lm_hard_wired_processing: GPIO_1_FUNC1!\n");
761d14abf1Robert Mustacchi            //to deal with this signal, add dispatch func call here
762d14abf1Robert Mustacchi        }
763d14abf1Robert Mustacchi        if (assertion_proc_flgs & GPIO_3_FUNC1)
764d14abf1Robert Mustacchi        {
765d14abf1Robert Mustacchi            DbgMessage(pdev, WARN, "lm_hard_wired_processing: GPIO_2_FUNC1!\n");
766d14abf1Robert Mustacchi            //to deal with this signal, add dispatch func call here
767d14abf1Robert Mustacchi        }
768d14abf1Robert Mustacchi        if (assertion_proc_flgs & GPIO_4_FUNC1)
769d14abf1Robert Mustacchi        {
770d14abf1Robert Mustacchi            DbgMessage(pdev, WARN, "lm_hard_wired_processing: GPIO_3_FUNC1!\n");
771d14abf1Robert Mustacchi            // Will be handled in deassertion
772d14abf1Robert Mustacchi        }
773d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_GENERAL_ATTN_4)
774d14abf1Robert Mustacchi        {
775d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_GENERAL_ATTN_4! and clean it!!!\n");
776d14abf1Robert Mustacchi            REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_4,0x0);
777d14abf1Robert Mustacchi        }
778d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_GENERAL_ATTN_5)
779d14abf1Robert Mustacchi        {
780d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_GENERAL_ATTN_5! and clean it!!!\n");
781d14abf1Robert Mustacchi            REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_5,0x0);
782d14abf1Robert Mustacchi        }
783d14abf1Robert Mustacchi        if (assertion_proc_flgs & ATTN_GENERAL_ATTN_6)
784d14abf1Robert Mustacchi        {
785d14abf1Robert Mustacchi            DbgMessage(pdev, FATAL, "lm_hard_wired_processing: ATTN_GENERAL_ATTN_6! and clean it!!!\n");
786d14abf1Robert Mustacchi            REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_6,0x0);
787d14abf1Robert Mustacchi        }
788d14abf1Robert Mustacchi    }
789d14abf1Robert Mustacchi}
790d14abf1Robert Mustacchi
791d14abf1Robert Mustacchistatic void lm_nig_processing(lm_device_t *pdev)
792d14abf1Robert Mustacchi{
793d14abf1Robert Mustacchi    u32_t nig_status_port          = 0;
794d14abf1Robert Mustacchi    u32_t unicore_val              = 0;
795d14abf1Robert Mustacchi    u32_t is_unicore_intr_asserted = 0;
796d14abf1Robert Mustacchi    // save nig interrupt mask and set it back later
797d14abf1Robert Mustacchi    lm_link_update(pdev);
798d14abf1Robert Mustacchi    if (PORT_ID(pdev) == 0)
799d14abf1Robert Mustacchi    {
800d14abf1Robert Mustacchi        //read the status interrupt of the NIG for the appropriate port (will do read-modify-write)
801d14abf1Robert Mustacchi        nig_status_port = REG_RD(pdev,  NIG_REG_STATUS_INTERRUPT_PORT0);
802d14abf1Robert Mustacchi
803d14abf1Robert Mustacchi        //pass over each of the 24 NIG REG to find out why the NIG attention was asserted.
804d14abf1Robert Mustacchi        //every unicore interrupt read, in case it differs from the corresponding bit in the
805d14abf1Robert Mustacchi        //NIG_REG_STATUS_INTERRUPT_PORT0, then we need to assign the value read into the apporpriate bit
806d14abf1Robert Mustacchi        // in NIG_REG_STATUS_INTERRUPT_PORT0 register.
807d14abf1Robert Mustacchi
808d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_MI_INT, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT_SIZE);
809d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_MI_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE_SIZE);
810d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_CFG_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE_SIZE);
811d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS_SIZE);
812d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_LINK_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE_SIZE);
813d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC0_STATUS_MISC_ATTN, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN_SIZE);
814d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS_SIZE);
815d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE_SIZE);
816d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT_SIZE);
817d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS_SIZE);
818d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX_SIZE);
819d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE_SIZE);
820d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX_SIZE);
821d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES0_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET_SIZE);
822d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_REMOTEMDIOREQ, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ_SIZE);
823d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_LINK10G, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G_SIZE);
824d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE_SIZE);
825d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT_SIZE);
826d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE);
827d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX_SIZE);
828d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE_SIZE);
829d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX_SIZE);
830d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET_SIZE);
831d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS0_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS_SIZE);
832d14abf1Robert Mustacchi
833d14abf1Robert Mustacchi        //write back the updated status interrupt of the NIG for the appropriate port.
834d14abf1Robert Mustacchi        REG_WR(pdev,  NIG_REG_STATUS_INTERRUPT_PORT0, nig_status_port);
835d14abf1Robert Mustacchi    }
836d14abf1Robert Mustacchi    else
837d14abf1Robert Mustacchi    {
838d14abf1Robert Mustacchi        DbgBreakIf(PORT_ID(pdev) != 1);
839d14abf1Robert Mustacchi        nig_status_port = REG_RD(pdev,  NIG_REG_STATUS_INTERRUPT_PORT1);
840d14abf1Robert Mustacchi
841d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_MI_INT, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT_SIZE);
842d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_MI_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE_SIZE);
843d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_CFG_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE_SIZE);
844d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS_SIZE);
845d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_LINK_CHANGE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE_SIZE);
846d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_EMAC1_STATUS_MISC_ATTN, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN_SIZE);
847d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS_SIZE);
848d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE_SIZE);
849d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT_SIZE);
850d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS_SIZE);
851d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX_SIZE);
852d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE_SIZE);
853d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX_SIZE);
854d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_SERDES1_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET_SIZE);
855d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_REMOTEMDIOREQ, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ_SIZE);
856d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_LINK10G, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G_SIZE);
857d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_AUTONEG_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE_SIZE);
858d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_FIBER_RXACT, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT_SIZE);
859d14abf1Robert Mustacchi        //HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_LINK_STATUS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK_STATUS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK_STATUS_SIZE);
860d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX_SIZE);
861d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_CL73_AN_COMPLETE, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE_SIZE);
862d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_CL73_MR_PAGE_RX, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX_SIZE);
863d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_RX_SIGDET, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET_SIZE);
864d14abf1Robert Mustacchi        HANDLE_UNICORE_INT_ASSERTED(pdev, NIG_REG_XGXS1_STATUS_MAC_CRS, &unicore_val, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS, &nig_status_port, &is_unicore_intr_asserted, NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS_SIZE);
865d14abf1Robert Mustacchi
866d14abf1Robert Mustacchi        REG_WR(pdev,  NIG_REG_STATUS_INTERRUPT_PORT1, nig_status_port);
867d14abf1Robert Mustacchi
868d14abf1Robert Mustacchi    }
869d14abf1Robert Mustacchi}
870d14abf1Robert Mustacchi
871d14abf1Robert Mustacchivoid lm_handle_assertion_processing(lm_device_t *pdev, u16_t assertion_proc_flgs)
872d14abf1Robert Mustacchi{
873d14abf1Robert Mustacchi    u32_t       val           = 0;
874d14abf1Robert Mustacchi    u32_t       port_reg_name = 0;
875d14abf1Robert Mustacchi    u32_t       mask_val      = 0;
876d14abf1Robert Mustacchi    u32_t       nig_mask      = 0;
877d14abf1Robert Mustacchi
878d14abf1Robert Mustacchi    DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: assertion_proc_flgs:%d\n", assertion_proc_flgs);
879d14abf1Robert Mustacchi
880d14abf1Robert Mustacchi    //mask only appropriate attention output signals from configured routing and unifier logic toward IGU.
881d14abf1Robert Mustacchi    //This is for driver/chip sync to eventually return to '00' monitored state
882d14abf1Robert Mustacchi    //in both leading & trailing latch.
883d14abf1Robert Mustacchi    //mask non-hard-wired dynamic groups only
884d14abf1Robert Mustacchi
885d14abf1Robert Mustacchi    DbgBreakIf(pdev->vars.attn_state & assertion_proc_flgs);
886d14abf1Robert Mustacchi
887d14abf1Robert Mustacchi    //mask relevant AEU attn lines
888d14abf1Robert Mustacchi    //             mask  assert_flgs  new mask
889d14abf1Robert Mustacchi    //legal:        0       0       ->    0
890d14abf1Robert Mustacchi    //              1       0       ->    1
891d14abf1Robert Mustacchi    //              1       1       ->    0
892d14abf1Robert Mustacchi    //ASSERT:       0       1 -> this won't change us thanks to & ~
893d14abf1Robert Mustacchi
894d14abf1Robert Mustacchi    ASSERT_STATIC( HW_LOCK_RESOURCE_PORT0_ATT_MASK +1 == HW_LOCK_RESOURCE_PORT1_ATT_MASK );
895d14abf1Robert Mustacchi    ASSERT_STATIC( NIG_REG_MASK_INTERRUPT_PORT0 + 4   == NIG_REG_MASK_INTERRUPT_PORT1 );
896d14abf1Robert Mustacchi
897d14abf1Robert Mustacchi    lm_hw_lock(pdev, HW_LOCK_RESOURCE_PORT0_ATT_MASK + PORT_ID(pdev), TRUE);
898d14abf1Robert Mustacchi    port_reg_name = PORT_ID(pdev) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : MISC_REG_AEU_MASK_ATTN_FUNC_0;
899d14abf1Robert Mustacchi    // read the hw current mask value
900d14abf1Robert Mustacchi    mask_val=REG_RD(pdev, port_reg_name);
901d14abf1Robert Mustacchi    //changed rrom XOR to & ~
902d14abf1Robert Mustacchi    pdev->vars.aeu_mask_attn_func = mask_val & 0xff;
903d14abf1Robert Mustacchi    DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: BEFORE: aeu_mask_attn_func:0x%x\n", pdev->vars.aeu_mask_attn_func);
904d14abf1Robert Mustacchi    //changed rrom XOR to & ~
905d14abf1Robert Mustacchi    pdev->vars.aeu_mask_attn_func &= ~(assertion_proc_flgs & 0xff);
906d14abf1Robert Mustacchi    REG_WR(pdev, port_reg_name, pdev->vars.aeu_mask_attn_func);
907d14abf1Robert Mustacchi    DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: AFTER : aeu_mask_attn_func:0x%x\n", pdev->vars.aeu_mask_attn_func);
908d14abf1Robert Mustacchi    lm_hw_unlock(pdev, HW_LOCK_RESOURCE_PORT0_ATT_MASK + PORT_ID(pdev));
909d14abf1Robert Mustacchi    //update the bits states
910d14abf1Robert Mustacchi
911d14abf1Robert Mustacchi    //        state  assert_flgs  new state
912d14abf1Robert Mustacchi    //legal:    0       0         -> 0
913d14abf1Robert Mustacchi    //          0       1         -> 1
914d14abf1Robert Mustacchi    //          1       0         -> 1
915d14abf1Robert Mustacchi    //error:    1       1 -> this won't change us thanks to |
916d14abf1Robert Mustacchi    DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: BEFORE: attn_state:0x%x\n", pdev->vars.attn_state);
917d14abf1Robert Mustacchi    //changed from XOR to OR for safety
918d14abf1Robert Mustacchi    pdev->vars.attn_state |= assertion_proc_flgs;
919d14abf1Robert Mustacchi
920d14abf1Robert Mustacchi    DbgMessage(pdev, INFORM, "lm_handle_assertion_processing: AFTER : attn_state:0x%x\n", pdev->vars.attn_state);
921d14abf1Robert Mustacchi    //process only hard-wired lines in case any got up
922d14abf1Robert Mustacchi    if (assertion_proc_flgs & ATTN_HARD_WIRED_MASK)
923d14abf1Robert Mustacchi    {
924d14abf1Robert Mustacchi        lm_hard_wired_processing(pdev, assertion_proc_flgs);
925d14abf1Robert Mustacchi    }
926d14abf1Robert Mustacchi
927d14abf1Robert Mustacchi    // now handle nig
928d14abf1Robert Mustacchi    if (assertion_proc_flgs & ATTN_NIG_FOR_FUNC)
929d14abf1Robert Mustacchi    {
930d14abf1Robert Mustacchi        MM_ACQUIRE_PHY_LOCK(pdev);
931d14abf1Robert Mustacchi         // save nig interrupt mask and set it back later
932d14abf1Robert Mustacchi        nig_mask = REG_RD(pdev,  NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev));
933d14abf1Robert Mustacchi        REG_WR(pdev,  NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev), 0);
934d14abf1Robert Mustacchi
935d14abf1Robert Mustacchi        // we'll handle the attention only if mask is not 0
936d14abf1Robert Mustacchi        // if mask is 0, it means that "old" and irrelevant is sent
937d14abf1Robert Mustacchi        // and we should not hnalde it (e.g. CQ48990 - got link down event after loopback mode was set).
938d14abf1Robert Mustacchi        if( nig_mask )
939d14abf1Robert Mustacchi        {
940d14abf1Robert Mustacchi            lm_nig_processing(pdev);
941d14abf1Robert Mustacchi        }
942d14abf1Robert Mustacchi        else
943d14abf1Robert Mustacchi        {
944d14abf1Robert Mustacchi            DbgMessage(pdev, WARN, "lm_handle_deassertion_processing: got attention when nig_mask is 0\n" );
945d14abf1Robert Mustacchi        }
946d14abf1Robert Mustacchi    }
947d14abf1Robert Mustacchi
948d14abf1Robert Mustacchi    //parallel write to IGU to set the attn_ack for _all asserted_ lines.
949d14abf1Robert Mustacchi    val = assertion_proc_flgs;
950d14abf1Robert Mustacchi
951d14abf1Robert Mustacchi    // attntion bits set
952d14abf1Robert Mustacchi    if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC)
953d14abf1Robert Mustacchi    {
954d14abf1Robert Mustacchi        REG_WR(pdev,  HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_ATTN_BITS_SET,val);
955d14abf1Robert Mustacchi    }
956d14abf1Robert Mustacchi    else
957d14abf1Robert Mustacchi    {
958d14abf1Robert Mustacchi        u32_t cmd_addr = IGU_CMD_ATTN_BIT_SET_UPPER;
959d14abf1Robert Mustacchi        if (INTR_BLK_ACCESS(pdev) == INTR_BLK_ACCESS_IGUMEM)
960d14abf1Robert Mustacchi        {
961d14abf1Robert Mustacchi            REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, val);
962d14abf1Robert Mustacchi        }
963d14abf1Robert Mustacchi        else
964d14abf1Robert Mustacchi        {
965d14abf1Robert Mustacchi            struct igu_ctrl_reg cmd_ctrl;
966d14abf1Robert Mustacchi            u8_t                igu_func_id = 0;
967d14abf1Robert Mustacchi            /* GRC ACCESS: */
968d14abf1Robert Mustacchi            /* Write the Data, then the control */
969d14abf1Robert Mustacchi             /* [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:14] = 0; [13:12] = PF number) */
970d14abf1Robert Mustacchi            igu_func_id = IGU_FUNC_ID(pdev);
971d14abf1Robert Mustacchi            cmd_ctrl.ctrl_data =
972d14abf1Robert Mustacchi                ((cmd_addr << IGU_CTRL_REG_ADDRESS_SHIFT) |
973d14abf1Robert Mustacchi                 (igu_func_id << IGU_CTRL_REG_FID_SHIFT) |
974d14abf1Robert Mustacchi                 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
975d14abf1Robert Mustacchi
976d14abf1Robert Mustacchi            REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, val);
977d14abf1Robert Mustacchi            REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
978d14abf1Robert Mustacchi        }
979d14abf1Robert Mustacchi    }
980d14abf1Robert Mustacchi
981d14abf1Robert Mustacchi    // now set back the mask
982d14abf1Robert Mustacchi    if (assertion_proc_flgs & ATTN_NIG_FOR_FUNC)
983d14abf1Robert Mustacchi    {
984d14abf1Robert Mustacchi        u8_t blk_type   = INTR_BLK_TYPE(pdev);
985d14abf1Robert Mustacchi        u8_t blk_access = INTR_BLK_ACCESS(pdev);
986d14abf1Robert Mustacchi
987d14abf1Robert Mustacchi        if ( ( blk_type != INTR_BLK_HC ) && ( blk_access == INTR_BLK_ACCESS_IGUMEM ))
988d14abf1Robert Mustacchi        {
989d14abf1Robert Mustacchi            u32 cnt = 0;
990d14abf1Robert Mustacchi            // Verify that IGU ack through BAR was written before restoring NIG mask.
991d14abf1Robert Mustacchi            // This loop should exit after 2-3 iterations max.
992d14abf1Robert Mustacchi            do
993d14abf1Robert Mustacchi            {
994d14abf1Robert Mustacchi                val = REG_RD(pdev, IGU_REG_ATTENTION_ACK_BITS);
995d14abf1Robert Mustacchi            }
996d14abf1Robert Mustacchi            while (((val & ATTN_NIG_FOR_FUNC) == 0) && (++cnt < MAX_IGU_ATTN_ACK_TO));
997d14abf1Robert Mustacchi
998d14abf1Robert Mustacchi            if (!val)
999d14abf1Robert Mustacchi            {
1000d14abf1Robert Mustacchi                DbgMessage(pdev, FATAL, "Failed to verify IGU ack on time\n");
1001d14abf1Robert Mustacchi            }
1002d14abf1Robert Mustacchi        }
1003d14abf1Robert Mustacchi        REG_WR(pdev,  NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev), nig_mask);
1004d14abf1Robert Mustacchi        MM_RELEASE_PHY_LOCK(pdev);
1005d14abf1Robert Mustacchi    }
1006d14abf1Robert Mustacchi}
1007d14abf1Robert Mustacchi
1008d14abf1Robert Mustacchistatic u32_t lm_cfc_attn_everest_processing(lm_device_t *pdev)
1009d14abf1Robert Mustacchi{
1010d14abf1Robert Mustacchi    u32_t val, valc;
1011d14abf1Robert Mustacchi    val = REG_RD(pdev,CFC_REG_CFC_INT_STS);
1012d14abf1Robert Mustacchi
1013d14abf1Robert Mustacchi    // TODO add defines here
1014d14abf1Robert Mustacchi    DbgMessage(pdev, FATAL, "CFC hw attention 0x%x\n",val);
1015d14abf1Robert Mustacchi    if (val) {
1016d14abf1Robert Mustacchi        pdev->vars.cfc_int_status_cnt++;
1017d14abf1Robert Mustacchi    // CFC error attention
1018d14abf1Robert Mustacchi    if (val & 0x2)
1019d14abf1Robert Mustacchi    {
1020d14abf1Robert Mustacchi                //DbgBreakIfAll(1);
1021d14abf1Robert Mustacchi    }
1022d14abf1Robert Mustacchi}
1023d14abf1Robert Mustacchi    valc = REG_RD(pdev,CFC_REG_CFC_INT_STS_CLR);
1024d14abf1Robert Mustacchi    return val;
1025d14abf1Robert Mustacchi}
1026d14abf1Robert Mustacchistatic void lm_pxp_attn_everest_processing(lm_device_t *pdev)
1027d14abf1Robert Mustacchi{
1028d14abf1Robert Mustacchi    u32_t val = REG_RD(pdev,PXP_REG_PXP_INT_STS_0);
1029d14abf1Robert Mustacchi
1030d14abf1Robert Mustacchi    // TODO add defines here
1031d14abf1Robert Mustacchi    DbgMessage(pdev, FATAL, "PXP hw attention 0x%x\n",val);
1032d14abf1Robert Mustacchi    // RQ_USDMDP_FIFO_OVERFLOW attention
1033d14abf1Robert Mustacchi    if (val & 0x18000)
1034d14abf1Robert Mustacchi    {
1035d14abf1Robert Mustacchi        DbgBreakIfAll(1);
1036d14abf1Robert Mustacchi    }
1037d14abf1Robert Mustacchi
1038d14abf1Robert Mustacchi}
1039d14abf1Robert Mustacchi/*
1040d14abf1Robert Mustacchi *Function Name:lm_spio5_attn_everest_processing
1041d14abf1Robert Mustacchi *
1042d14abf1Robert Mustacchi *Parameters:
1043d14abf1Robert Mustacchi *
1044d14abf1Robert Mustacchi *Description:
1045d14abf1Robert Mustacchi *  Indicates fan failure on specific external_phy_config (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1046d14abf1Robert Mustacchi *Returns:
1047d14abf1Robert Mustacchi *
1048d14abf1Robert Mustacchi */
1049d14abf1Robert Mustacchistatic void lm_spio5_attn_everest_processing(lm_device_t *pdev)
1050d14abf1Robert Mustacchi{
1051d14abf1Robert Mustacchi    u32_t      val            = 0;
1052d14abf1Robert Mustacchi    u32_t      offset         = 0;
1053d14abf1Robert Mustacchi    u32_t      ext_phy_config = 0;
1054d14abf1Robert Mustacchi    const u8_t port_id        = PORT_ID(pdev);
1055d14abf1Robert Mustacchi
1056d14abf1Robert Mustacchi   // Special fan failure handling for boards with external PHY SFX7101 (which include fan)
1057d14abf1Robert Mustacchi    PHY_HW_LOCK(pdev);
1058d14abf1Robert Mustacchi    elink_hw_reset_phy(&pdev->params.link);
1059d14abf1Robert Mustacchi    PHY_HW_UNLOCK(pdev);
1060d14abf1Robert Mustacchi
1061d14abf1Robert Mustacchi    offset = ( 0 == port_id ) ? MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 ;
1062d14abf1Robert Mustacchi
1063d14abf1Robert Mustacchi    val = REG_RD(pdev, offset );
1064d14abf1Robert Mustacchi
1065d14abf1Robert Mustacchi    DbgMessage(pdev, FATAL, "lm_spio5_attn_everest_processing: SPIO5 hw attention 0x%x\n",val);
1066d14abf1Robert Mustacchi
1067d14abf1Robert Mustacchi    // mask flags so we won't get this attention anymore
1068d14abf1Robert Mustacchi    RESET_FLAGS(val, AEU_INPUTS_ATTN_BITS_SPIO5 ) ;
1069d14abf1Robert Mustacchi    REG_WR(pdev, offset, val ) ;
1070d14abf1Robert Mustacchi
1071d14abf1Robert Mustacchi    // change phy_type to type failure (under phy lock)
1072d14abf1Robert Mustacchi    MM_ACQUIRE_PHY_LOCK(pdev);
1073d14abf1Robert Mustacchi
1074d14abf1Robert Mustacchi    offset = OFFSETOF(shmem_region_t,dev_info.port_hw_config[port_id].external_phy_config);
1075d14abf1Robert Mustacchi
1076d14abf1Robert Mustacchi    LM_SHMEM_READ(pdev, offset, &ext_phy_config);
1077d14abf1Robert Mustacchi
1078d14abf1Robert Mustacchi    RESET_FLAGS(ext_phy_config, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK ) ;
1079d14abf1Robert Mustacchi    SET_FLAGS(ext_phy_config, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE ) ;
1080d14abf1Robert Mustacchi
1081d14abf1Robert Mustacchi    // Set external phy type to failure for MCP to know about the failure
1082d14abf1Robert Mustacchi    LM_SHMEM_WRITE(pdev, offset, ext_phy_config);
1083d14abf1Robert Mustacchi
1084d14abf1Robert Mustacchi    DbgMessage(pdev, WARN, "lm_spio5_attn_everest_processing: external_phy_type 0x%x\n",ext_phy_config);
1085d14abf1Robert Mustacchi
1086d14abf1Robert Mustacchi    // Indicate "link-down". elink_hw_reset_phy takes care of the physical part, but part of the function
1087d14abf1Robert Mustacchi    // masks attentions, which means we won't get a link event from anywhere else. Therefore we need to
1088d14abf1Robert Mustacchi    // indicate link down at this point to OS... to supress traffic and upload toe connections...
1089d14abf1Robert Mustacchi    // we do this under lock since we change the link status...
1090d14abf1Robert Mustacchi    pdev->vars.link_status = LM_STATUS_LINK_DOWN;
1091d14abf1Robert Mustacchi
1092d14abf1Robert Mustacchi    mm_indicate_link(pdev, pdev->vars.link_status, pdev->vars.medium);
1093d14abf1Robert Mustacchi
1094d14abf1Robert Mustacchi    MM_RELEASE_PHY_LOCK(pdev);
1095d14abf1Robert Mustacchi
1096d14abf1Robert Mustacchi    // write to the event log!
1097d14abf1Robert Mustacchi    mm_event_log_generic( pdev, LM_LOG_ID_FAN_FAILURE );
1098d14abf1Robert Mustacchi
1099d14abf1Robert Mustacchi    mm_indicate_hw_failure(pdev);
1100d14abf1Robert Mustacchi}
1101d14abf1Robert Mustacchi
1102d14abf1Robert Mustacchi// Check current fan failure state - report in case signaled.
1103d14abf1Robert Mustacchivoid lm_check_fan_failure(struct _lm_device_t *pdev)
1104d14abf1Robert Mustacchi{
1105d14abf1Robert Mustacchi    u32_t val = 0;
1106d14abf1Robert Mustacchi
1107d14abf1Robert Mustacchi    if (IS_VFDEV(pdev))
1108d14abf1Robert Mustacchi    {
1109d14abf1Robert Mustacchi        return;
1110d14abf1Robert Mustacchi    }
1111d14abf1Robert Mustacchi
1112d14abf1Robert Mustacchi    val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + PORT_ID(pdev)*4);
1113d14abf1Robert Mustacchi
1114d14abf1Robert Mustacchi    if( GET_FLAGS(val, AEU_INPUTS_ATTN_BITS_SPIO5))
1115d14abf1Robert Mustacchi    {
1116d14abf1Robert Mustacchi        lm_spio5_attn_everest_processing(pdev);
1117d14abf1Robert Mustacchi    }
1118d14abf1Robert Mustacchi}
1119d14abf1Robert Mustacchi
1120d14abf1Robert Mustacchi// Change PMF or link change
1121d14abf1Robert Mustacchi// PMF sent link updates to all func (but himself) OR I become a PMF from MCP notification
1122d14abf1Robert Mustacchi// on some cases PMF sends link event to himself as well if errors occured in the mac.
1123d14abf1Robert Mustacchistatic void lm_pmf_or_link_event(lm_device_t *pdev, u32_t drv_status)
1124d14abf1Robert Mustacchi{
1125d14abf1Robert Mustacchi    u32_t val = 0;
1126d14abf1Robert Mustacchi
1127d14abf1Robert Mustacchi
1128d14abf1Robert Mustacchi    DbgMessage(pdev, WARN, "lm_pmf_or_link_event: sync general attention received!!! for func%d\n",FUNC_ID(pdev));
1129d14abf1Robert Mustacchi
1130d14abf1Robert Mustacchi    // sync with link
1131d14abf1Robert Mustacchi    MM_ACQUIRE_PHY_LOCK(pdev);
1132d14abf1Robert Mustacchi    elink_link_status_update(&pdev->params.link,&pdev->vars.link);
1133d14abf1