1*d14abf15SRobert Mustacchi #ifndef ECORE_INIT_H
2*d14abf15SRobert Mustacchi #define ECORE_INIT_H
3*d14abf15SRobert Mustacchi
4*d14abf15SRobert Mustacchi #include "init_defs.h"
5*d14abf15SRobert Mustacchi #include "aeu_inputs.h"
6*d14abf15SRobert Mustacchi
7*d14abf15SRobert Mustacchi #if defined(_B10KD_EXT)
8*d14abf15SRobert Mustacchi #include "b10ext_redefs.h"
9*d14abf15SRobert Mustacchi #include "b10ext.h"
10*d14abf15SRobert Mustacchi #endif
11*d14abf15SRobert Mustacchi
12*d14abf15SRobert Mustacchi /* Returns the index of start or end of a specific block stage in ops array*/
13*d14abf15SRobert Mustacchi #define BLOCK_OPS_IDX(block, stage, end) \
14*d14abf15SRobert Mustacchi (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
15*d14abf15SRobert Mustacchi
16*d14abf15SRobert Mustacchi
17*d14abf15SRobert Mustacchi #define INITOP_SET 0 /* set the HW directly */
18*d14abf15SRobert Mustacchi #define INITOP_CLEAR 1 /* clear the HW directly */
19*d14abf15SRobert Mustacchi #define INITOP_INIT 2 /* set the init-value array */
20*d14abf15SRobert Mustacchi
21*d14abf15SRobert Mustacchi /****************************************************************************
22*d14abf15SRobert Mustacchi * ILT management
23*d14abf15SRobert Mustacchi ****************************************************************************/
24*d14abf15SRobert Mustacchi struct ilt_line {
25*d14abf15SRobert Mustacchi lm_address_t page_mapping;
26*d14abf15SRobert Mustacchi void *page;
27*d14abf15SRobert Mustacchi u32 size;
28*d14abf15SRobert Mustacchi };
29*d14abf15SRobert Mustacchi
30*d14abf15SRobert Mustacchi struct ilt_client_info {
31*d14abf15SRobert Mustacchi u32 page_size;
32*d14abf15SRobert Mustacchi u16 start;
33*d14abf15SRobert Mustacchi u16 end;
34*d14abf15SRobert Mustacchi u16 client_num;
35*d14abf15SRobert Mustacchi u16 flags;
36*d14abf15SRobert Mustacchi #define ILT_CLIENT_SKIP_INIT 0x1
37*d14abf15SRobert Mustacchi #define ILT_CLIENT_SKIP_MEM 0x2
38*d14abf15SRobert Mustacchi };
39*d14abf15SRobert Mustacchi
40*d14abf15SRobert Mustacchi struct ecore_ilt {
41*d14abf15SRobert Mustacchi u32 start_line;
42*d14abf15SRobert Mustacchi struct ilt_line *lines;
43*d14abf15SRobert Mustacchi struct ilt_client_info clients[4];
44*d14abf15SRobert Mustacchi #define ILT_CLIENT_CDU 0
45*d14abf15SRobert Mustacchi #define ILT_CLIENT_QM 1
46*d14abf15SRobert Mustacchi #define ILT_CLIENT_SRC 2
47*d14abf15SRobert Mustacchi #define ILT_CLIENT_TM 3
48*d14abf15SRobert Mustacchi };
49*d14abf15SRobert Mustacchi
50*d14abf15SRobert Mustacchi /****************************************************************************
51*d14abf15SRobert Mustacchi * SRC configuration
52*d14abf15SRobert Mustacchi ****************************************************************************/
53*d14abf15SRobert Mustacchi struct src_ent {
54*d14abf15SRobert Mustacchi u8 opaque[56];
55*d14abf15SRobert Mustacchi u64 next;
56*d14abf15SRobert Mustacchi };
57*d14abf15SRobert Mustacchi
58*d14abf15SRobert Mustacchi /****************************************************************************
59*d14abf15SRobert Mustacchi * Parity configuration
60*d14abf15SRobert Mustacchi ****************************************************************************/
61*d14abf15SRobert Mustacchi #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
62*d14abf15SRobert Mustacchi { \
63*d14abf15SRobert Mustacchi block##_REG_##block##_PRTY_MASK, \
64*d14abf15SRobert Mustacchi block##_REG_##block##_PRTY_STS_CLR, \
65*d14abf15SRobert Mustacchi en_mask, {m1, m1h, m2, m3}, #block \
66*d14abf15SRobert Mustacchi }
67*d14abf15SRobert Mustacchi
68*d14abf15SRobert Mustacchi #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
69*d14abf15SRobert Mustacchi { \
70*d14abf15SRobert Mustacchi block##_REG_##block##_PRTY_MASK_0, \
71*d14abf15SRobert Mustacchi block##_REG_##block##_PRTY_STS_CLR_0, \
72*d14abf15SRobert Mustacchi en_mask, {m1, m1h, m2, m3}, #block"_0" \
73*d14abf15SRobert Mustacchi }
74*d14abf15SRobert Mustacchi
75*d14abf15SRobert Mustacchi #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
76*d14abf15SRobert Mustacchi { \
77*d14abf15SRobert Mustacchi block##_REG_##block##_PRTY_MASK_1, \
78*d14abf15SRobert Mustacchi block##_REG_##block##_PRTY_STS_CLR_1, \
79*d14abf15SRobert Mustacchi en_mask, {m1, m1h, m2, m3}, #block"_1" \
80*d14abf15SRobert Mustacchi }
81*d14abf15SRobert Mustacchi
82*d14abf15SRobert Mustacchi static const struct {
83*d14abf15SRobert Mustacchi u32 mask_addr;
84*d14abf15SRobert Mustacchi u32 sts_clr_addr;
85*d14abf15SRobert Mustacchi u32 en_mask; /* Mask to enable parity attentions */
86*d14abf15SRobert Mustacchi struct {
87*d14abf15SRobert Mustacchi u32 e1; /* 57710 */
88*d14abf15SRobert Mustacchi u32 e1h; /* 57711 */
89*d14abf15SRobert Mustacchi u32 e2; /* 57712 */
90*d14abf15SRobert Mustacchi u32 e3; /* 578xx */
91*d14abf15SRobert Mustacchi } reg_mask; /* Register mask (all valid bits) */
92*d14abf15SRobert Mustacchi char name[8]; /* Block's longest name is 7 characters long
93*d14abf15SRobert Mustacchi * (name + suffix)
94*d14abf15SRobert Mustacchi */
95*d14abf15SRobert Mustacchi } ecore_blocks_parity_data[] = {
96*d14abf15SRobert Mustacchi /* bit 19 masked */
97*d14abf15SRobert Mustacchi /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
98*d14abf15SRobert Mustacchi /* bit 5,18,20-31 */
99*d14abf15SRobert Mustacchi /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
100*d14abf15SRobert Mustacchi /* bit 5 */
101*d14abf15SRobert Mustacchi /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
102*d14abf15SRobert Mustacchi /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
103*d14abf15SRobert Mustacchi /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
104*d14abf15SRobert Mustacchi
105*d14abf15SRobert Mustacchi /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
106*d14abf15SRobert Mustacchi * want to handle "system kill" flow at the moment.
107*d14abf15SRobert Mustacchi */
108*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
109*d14abf15SRobert Mustacchi 0x7ffffff),
110*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
111*d14abf15SRobert Mustacchi 0xffffffff),
112*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
113*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
114*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
115*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
116*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
117*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
118*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
119*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
120*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
121*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
122*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
123*d14abf15SRobert Mustacchi {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
124*d14abf15SRobert Mustacchi GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
125*d14abf15SRobert Mustacchi {0xf, 0xf, 0xf, 0xf}, "UPB"},
126*d14abf15SRobert Mustacchi {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
127*d14abf15SRobert Mustacchi GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
128*d14abf15SRobert Mustacchi {0xf, 0xf, 0xf, 0xf}, "XPB"},
129*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
130*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
131*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
132*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
133*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
134*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
135*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
136*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
137*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
138*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
139*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
140*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
141*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
142*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
143*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
144*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
145*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
146*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
147*d14abf15SRobert Mustacchi 0xffffffff),
148*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
149*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
150*d14abf15SRobert Mustacchi 0xffffffff),
151*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
152*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
153*d14abf15SRobert Mustacchi 0xffffffff),
154*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
155*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
156*d14abf15SRobert Mustacchi 0xffffffff),
157*d14abf15SRobert Mustacchi BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
158*d14abf15SRobert Mustacchi };
159*d14abf15SRobert Mustacchi
160*d14abf15SRobert Mustacchi
161*d14abf15SRobert Mustacchi /* [28] MCP Latched rom_parity
162*d14abf15SRobert Mustacchi * [29] MCP Latched ump_rx_parity
163*d14abf15SRobert Mustacchi * [30] MCP Latched ump_tx_parity
164*d14abf15SRobert Mustacchi * [31] MCP Latched scpad_parity
165*d14abf15SRobert Mustacchi */
166*d14abf15SRobert Mustacchi #define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
167*d14abf15SRobert Mustacchi (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
168*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
169*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
170*d14abf15SRobert Mustacchi
171*d14abf15SRobert Mustacchi #define MISC_AEU_ENABLE_MCP_PRTY_BITS \
172*d14abf15SRobert Mustacchi (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
173*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
174*d14abf15SRobert Mustacchi
175*d14abf15SRobert Mustacchi /* Below registers control the MCP parity attention output. When
176*d14abf15SRobert Mustacchi * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
177*d14abf15SRobert Mustacchi * enabled, when cleared - disabled.
178*d14abf15SRobert Mustacchi */
179*d14abf15SRobert Mustacchi static const struct {
180*d14abf15SRobert Mustacchi u32 addr;
181*d14abf15SRobert Mustacchi u32 bits;
182*d14abf15SRobert Mustacchi } mcp_attn_ctl_regs[] = {
183*d14abf15SRobert Mustacchi { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
184*d14abf15SRobert Mustacchi MISC_AEU_ENABLE_MCP_PRTY_BITS },
185*d14abf15SRobert Mustacchi { MISC_REG_AEU_ENABLE4_NIG_0,
186*d14abf15SRobert Mustacchi MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
187*d14abf15SRobert Mustacchi { MISC_REG_AEU_ENABLE4_PXP_0,
188*d14abf15SRobert Mustacchi MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
189*d14abf15SRobert Mustacchi { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
190*d14abf15SRobert Mustacchi MISC_AEU_ENABLE_MCP_PRTY_BITS },
191*d14abf15SRobert Mustacchi { MISC_REG_AEU_ENABLE4_NIG_1,
192*d14abf15SRobert Mustacchi MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
193*d14abf15SRobert Mustacchi { MISC_REG_AEU_ENABLE4_PXP_1,
194*d14abf15SRobert Mustacchi MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
195*d14abf15SRobert Mustacchi };
196*d14abf15SRobert Mustacchi
ecore_set_mcp_parity(struct _lm_device_t * pdev,u8 enable)197*d14abf15SRobert Mustacchi static __inline void ecore_set_mcp_parity(struct _lm_device_t *pdev, u8 enable)
198*d14abf15SRobert Mustacchi {
199*d14abf15SRobert Mustacchi int i;
200*d14abf15SRobert Mustacchi u32 reg_val;
201*d14abf15SRobert Mustacchi
202*d14abf15SRobert Mustacchi for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
203*d14abf15SRobert Mustacchi reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr);
204*d14abf15SRobert Mustacchi
205*d14abf15SRobert Mustacchi if (enable)
206*d14abf15SRobert Mustacchi reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
207*d14abf15SRobert Mustacchi else
208*d14abf15SRobert Mustacchi reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
209*d14abf15SRobert Mustacchi
210*d14abf15SRobert Mustacchi REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val);
211*d14abf15SRobert Mustacchi }
212*d14abf15SRobert Mustacchi }
213*d14abf15SRobert Mustacchi
ecore_parity_reg_mask(struct _lm_device_t * pdev,int idx)214*d14abf15SRobert Mustacchi static __inline u32 ecore_parity_reg_mask(struct _lm_device_t *pdev, int idx)
215*d14abf15SRobert Mustacchi {
216*d14abf15SRobert Mustacchi if (CHIP_IS_E1(pdev))
217*d14abf15SRobert Mustacchi return ecore_blocks_parity_data[idx].reg_mask.e1;
218*d14abf15SRobert Mustacchi else if (CHIP_IS_E1H(pdev))
219*d14abf15SRobert Mustacchi return ecore_blocks_parity_data[idx].reg_mask.e1h;
220*d14abf15SRobert Mustacchi else if (CHIP_IS_E2(pdev))
221*d14abf15SRobert Mustacchi return ecore_blocks_parity_data[idx].reg_mask.e2;
222*d14abf15SRobert Mustacchi else /* CHIP_IS_E3 */
223*d14abf15SRobert Mustacchi return ecore_blocks_parity_data[idx].reg_mask.e3;
224*d14abf15SRobert Mustacchi }
225*d14abf15SRobert Mustacchi
ecore_disable_blocks_parity(struct _lm_device_t * pdev)226*d14abf15SRobert Mustacchi static __inline void ecore_disable_blocks_parity(struct _lm_device_t *pdev)
227*d14abf15SRobert Mustacchi {
228*d14abf15SRobert Mustacchi int i;
229*d14abf15SRobert Mustacchi
230*d14abf15SRobert Mustacchi for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
231*d14abf15SRobert Mustacchi u32 dis_mask = ecore_parity_reg_mask(pdev, i);
232*d14abf15SRobert Mustacchi
233*d14abf15SRobert Mustacchi if (dis_mask) {
234*d14abf15SRobert Mustacchi REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr,
235*d14abf15SRobert Mustacchi dis_mask);
236*d14abf15SRobert Mustacchi DbgMessage(pdev, WARNi, "Setting parity mask "
237*d14abf15SRobert Mustacchi "for %s to\t\t0x%x\n",
238*d14abf15SRobert Mustacchi ecore_blocks_parity_data[i].name, dis_mask);
239*d14abf15SRobert Mustacchi }
240*d14abf15SRobert Mustacchi }
241*d14abf15SRobert Mustacchi
242*d14abf15SRobert Mustacchi /* Disable MCP parity attentions */
243*d14abf15SRobert Mustacchi ecore_set_mcp_parity(pdev, FALSE);
244*d14abf15SRobert Mustacchi }
245*d14abf15SRobert Mustacchi
246*d14abf15SRobert Mustacchi /**
247*d14abf15SRobert Mustacchi * Clear the parity error status registers.
248*d14abf15SRobert Mustacchi */
ecore_clear_blocks_parity(struct _lm_device_t * pdev)249*d14abf15SRobert Mustacchi static __inline void ecore_clear_blocks_parity(struct _lm_device_t *pdev)
250*d14abf15SRobert Mustacchi {
251*d14abf15SRobert Mustacchi int i;
252*d14abf15SRobert Mustacchi u32 reg_val, mcp_aeu_bits =
253*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
254*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
255*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
256*d14abf15SRobert Mustacchi AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
257*d14abf15SRobert Mustacchi
258*d14abf15SRobert Mustacchi /* Clear SEM_FAST parities */
259*d14abf15SRobert Mustacchi REG_WR(pdev, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
260*d14abf15SRobert Mustacchi REG_WR(pdev, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
261*d14abf15SRobert Mustacchi REG_WR(pdev, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
262*d14abf15SRobert Mustacchi REG_WR(pdev, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
263*d14abf15SRobert Mustacchi
264*d14abf15SRobert Mustacchi for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
265*d14abf15SRobert Mustacchi u32 reg_mask = ecore_parity_reg_mask(pdev, i);
266*d14abf15SRobert Mustacchi
267*d14abf15SRobert Mustacchi if (reg_mask) {
268*d14abf15SRobert Mustacchi reg_val = REG_RD(pdev, ecore_blocks_parity_data[i].
269*d14abf15SRobert Mustacchi sts_clr_addr);
270*d14abf15SRobert Mustacchi if (reg_val & reg_mask) {
271*d14abf15SRobert Mustacchi DbgMessage(pdev, WARNi,
272*d14abf15SRobert Mustacchi "Parity errors in %s: 0x%x\n",
273*d14abf15SRobert Mustacchi ecore_blocks_parity_data[i].name,
274*d14abf15SRobert Mustacchi reg_val & reg_mask);
275*d14abf15SRobert Mustacchi }
276*d14abf15SRobert Mustacchi }
277*d14abf15SRobert Mustacchi }
278*d14abf15SRobert Mustacchi
279*d14abf15SRobert Mustacchi /* Check if there were parity attentions in MCP */
280*d14abf15SRobert Mustacchi reg_val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_4_MCP);
281*d14abf15SRobert Mustacchi if (reg_val & mcp_aeu_bits) {
282*d14abf15SRobert Mustacchi DbgMessage(pdev, WARNi, "Parity error in MCP: 0x%x\n",
283*d14abf15SRobert Mustacchi reg_val & mcp_aeu_bits);
284*d14abf15SRobert Mustacchi }
285*d14abf15SRobert Mustacchi
286*d14abf15SRobert Mustacchi /* Clear parity attentions in MCP:
287*d14abf15SRobert Mustacchi * [7] clears Latched rom_parity
288*d14abf15SRobert Mustacchi * [8] clears Latched ump_rx_parity
289*d14abf15SRobert Mustacchi * [9] clears Latched ump_tx_parity
290*d14abf15SRobert Mustacchi * [10] clears Latched scpad_parity (both ports)
291*d14abf15SRobert Mustacchi */
292*d14abf15SRobert Mustacchi REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
293*d14abf15SRobert Mustacchi }
294*d14abf15SRobert Mustacchi
ecore_enable_blocks_parity(struct _lm_device_t * pdev)295*d14abf15SRobert Mustacchi static __inline void ecore_enable_blocks_parity(struct _lm_device_t *pdev)
296*d14abf15SRobert Mustacchi {
297*d14abf15SRobert Mustacchi int i;
298*d14abf15SRobert Mustacchi
299*d14abf15SRobert Mustacchi for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
300*d14abf15SRobert Mustacchi u32 reg_mask = ecore_parity_reg_mask(pdev, i);
301*d14abf15SRobert Mustacchi
302*d14abf15SRobert Mustacchi if (reg_mask)
303*d14abf15SRobert Mustacchi REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr,
304*d14abf15SRobert Mustacchi ecore_blocks_parity_data[i].en_mask & reg_mask);
305*d14abf15SRobert Mustacchi }
306*d14abf15SRobert Mustacchi
307*d14abf15SRobert Mustacchi /* Enable MCP parity attentions */
308*d14abf15SRobert Mustacchi ecore_set_mcp_parity(pdev, TRUE);
309*d14abf15SRobert Mustacchi }
310*d14abf15SRobert Mustacchi
311*d14abf15SRobert Mustacchi
312*d14abf15SRobert Mustacchi #endif /* ECORE_INIT_H */
313*d14abf15SRobert Mustacchi
314