xref: /illumos-gate/usr/src/uts/common/io/bnx/bnx.h (revision ec71f88e58593e3077f03588d3c38e6cbd4e8c1a)
1 /*
2  * Copyright 2014-2017 Cavium, Inc.
3  * The contents of this file are subject to the terms of the Common Development
4  * and Distribution License, v.1,  (the "License").
5  *
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the License at available
9  * at http://opensource.org/licenses/CDDL-1.0
10  *
11  * See the License for the specific language governing permissions and
12  * limitations under the License.
13  */
14 
15 /*
16  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
17  * Copyright (c) 2019, Joyent, Inc.
18  */
19 
20 #ifndef _BNX_H
21 #define	_BNX_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 #include <sys/types.h>
28 #include <sys/stream.h>
29 #include <sys/stropts.h>
30 #include <sys/errno.h>
31 #include <sys/cred.h>
32 #include <sys/poll.h>
33 #include <sys/modctl.h>
34 #ifdef __10u7
35 #include <sys/mac.h>
36 #else
37 #include <sys/mac_provider.h>
38 #endif
39 #include <sys/stat.h>
40 #include <sys/ddi.h>
41 #include <sys/sunddi.h>
42 #include <sys/pattr.h>
43 #include <sys/sysmacros.h>
44 #include <sys/ethernet.h>
45 #include <sys/strsun.h>
46 #include <netinet/in.h>
47 #include <netinet/ip.h>
48 #include <netinet/udp.h>
49 #include <inet/common.h>
50 #include <inet/ip.h>
51 #include <inet/ip_if.h>
52 #include <sys/strsubr.h>
53 #include <sys/pci.h>
54 #include <sys/kstat.h>
55 
56 
57 
58 #include "listq.h"
59 #include "lm5706.h"
60 #include "54xx_reg.h"
61 
62 #define	BNX_MAGIC	0x0feedead
63 #define	BNX_STR_SIZE	32
64 
65 #ifdef __sparc
66 #define	BNX_DMA_ALIGNMENT	0x2000UL
67 #else
68 #define	BNX_DMA_ALIGNMENT	0x1000UL
69 #endif
70 
71 #define	BNX_MAX_SGL_ENTRIES		16
72 #define	BNX_MIN_BYTES_PER_FRAGMENT	32
73 
74 #define	FW_VER_WITH_UNLOAD_POWER_DOWN	0x01090003
75 
76 
77 extern ddi_device_acc_attr_t bnxAccessAttribBAR;
78 extern ddi_device_acc_attr_t bnxAccessAttribBUF;
79 extern ddi_dma_attr_t bnx_std_dma_attrib;
80 
81 
82 typedef struct _bnx_memreq_t {
83 	void   * addr;
84 	size_t   size;
85 } bnx_memreq_t;
86 
87 
88 
89 /*
90  * Transmit queue info structure holds information regarding transmit resources.
91  * This consists of two list, one is a free list of transmit packets and another
92  * a list of pending packets (packets posted to ASIC for transmit). Upon
93  * receiving transmit complete notification from the asic, the message blocks
94  * are freed and and packet structure is moved to the free list.
95  */
96 
97 typedef	struct _um_xmit_qinfo {
98 	ddi_dma_handle_t	dcpyhndl;
99 	ddi_acc_handle_t	dcpyahdl;
100 	caddr_t			dcpyvirt;
101 	lm_u64_t		dcpyphys;
102 	size_t			dcpyhard;
103 
104 	/* Packet descriptor memory. */
105 	u32_t			desc_cnt;
106 	bnx_memreq_t		desc_mem;
107 
108 	/* Low resource water marks. */
109 	u32_t			thresh_pdwm;
110 
111 	/* Free queue mutex */
112 	kmutex_t		free_mutex;
113 
114 	/* Packet descriptors that are free for use. */
115 	s_list_t		free_tx_desc;
116 
117 	/* Packet descriptors that have been setup and are awaiting xmit. */
118 	s_list_t		tx_resc_que;
119 } um_xmit_qinfo;
120 
121 
122 
123 /*
124  * Receive queue is mostly managed by the LM (lm_dev->rx_info.chain[]).
125  * During initialization, UM allocates receive buffers and prepares the
126  * rx descriptions to posts the receive buffers.
127  */
128 typedef	struct _um_recv_qinfo {
129 	volatile boolean_t processing;
130 
131 	/* For packet descriptors that do not have rx buffers assigned. */
132 	s_list_t buffq;
133 
134 	/* For packet descriptors waiting to be sent up. */
135 	s_list_t waitq;
136 } um_recv_qinfo;
137 
138 
139 typedef	struct _os_param {
140 	u32_t active_resc_flag;
141 #define	DRV_RESOURCE_PCICFG_MAPPED	0x0001
142 #define	DRV_RESOURCE_MAP_REGS		0x0002
143 #define	DRV_RESOURCE_INTR_1		0x0004
144 #define	DRV_RESOURCE_MUTEX		0x0008
145 #define	DRV_RESOURCE_HDWR_REGISTER	0x0020
146 #define	DRV_RESOURCE_GLD_REGISTER	0x0040
147 #define	DRV_RESOURCE_KSTAT		0x0080
148 #define	DRV_RESOURCE_TIMER		0x0100
149 #define	DRV_RESOURCE_MINOR_NODE		0x0200
150 #define	DRV_LINK_TIMEOUT_CB		0x0400
151 
152 	dev_info_t *dip;
153 
154 	ddi_acc_handle_t pci_cfg_handle;
155 	ddi_acc_handle_t reg_acc_handle;
156 
157 	mac_handle_t macp;
158 	mac_resource_handle_t rx_resc_handle[NUM_RX_CHAIN];
159 	caddr_t regs_addr;
160 
161 	kmutex_t  gld_mutex;
162 	krwlock_t gld_snd_mutex;
163 	kmutex_t  xmit_mutex;
164 	kmutex_t  rcv_mutex;
165 	kmutex_t  phy_mutex;
166 	kmutex_t  ind_mutex;
167 
168 	/*
169 	 * Following are generic DMA handles used for the following -
170 	 * 1. Status _ Statistic DMA memory
171 	 * 2. TXBD queue
172 	 * 3. RXBD queue
173 	 */
174 #define	BNX_MAX_PHYS_MEMREQS   32
175 	u32_t dma_handles_used;
176 	void *dma_virt[BNX_MAX_PHYS_MEMREQS];
177 	ddi_dma_handle_t dma_handle[BNX_MAX_PHYS_MEMREQS];
178 	ddi_acc_handle_t dma_acc_handle[BNX_MAX_PHYS_MEMREQS];
179 
180 	ddi_dma_handle_t *status_block_dma_hdl;
181 
182 } os_param_t;
183 
184 
185 
186 
187 /*
188  * Following structure hosts attributes related to the device, like media type,
189  * transmit/receive descriptor queue information, last status index
190  * processed/acknowledged, etc'
191  */
192 
193 typedef struct _dev_param {
194 
195 	u32_t mtu;
196 
197 	lm_rx_mask_t rx_filter_mask;
198 	lm_offload_t enabled_oflds;
199 
200 	/*
201 	 * This is the last value of 'status_idx' processed and acknowledged
202 	 * by the driver. This value is compared with current value in the
203 	 * status block to determine if new status block was generated by
204 	 * host coalesce block.
205 	 */
206 	u32_t processed_status_idx;
207 
208 	u32_t fw_ver;
209 
210 	boolean_t isfiber;
211 
212     boolean_t disableMsix;
213 
214     lm_status_t indLink;
215     lm_medium_t indMedium;
216 } device_param_t;
217 
218 
219 typedef struct _bnx_ndd_lnk_tbl_t {
220 	const char **label;
221 	const boolean_t *value;
222 } bnx_ndd_lnk_tbl_t;
223 
224 
225 /* NDD parameters related structure members. */
226 typedef struct _bnx_ndd_t {
227 	caddr_t ndd_data;
228 
229 	bnx_ndd_lnk_tbl_t lnktbl[3];
230 
231 	int link_speed;
232 	boolean_t link_duplex;
233 	boolean_t link_tx_pause;
234 	boolean_t link_rx_pause;
235 } bnx_ndd_t;
236 
237 
238 typedef struct _bnx_lnk_cfg_t {
239 	boolean_t link_autoneg;
240 	boolean_t param_2500fdx;
241 	boolean_t param_1000fdx;
242 	boolean_t param_1000hdx;
243 	boolean_t param_100fdx;
244 	boolean_t param_100hdx;
245 	boolean_t param_10fdx;
246 	boolean_t param_10hdx;
247 	boolean_t param_tx_pause;
248 	boolean_t param_rx_pause;
249 } bnx_lnk_cfg_t;
250 
251 
252 
253 typedef struct _bnx_phy_cfg_t {
254 	bnx_lnk_cfg_t lnkcfg;
255 
256 	boolean_t flow_autoneg;
257 	boolean_t wirespeed;
258 } bnx_phy_cfg_t;
259 
260 
261 
262 typedef	struct _um_device {
263 	/* Lower Module device structure should be the first element */
264 	struct _lm_device_t lm_dev;
265 
266 	u32_t magic;
267 
268 	ddi_intr_handle_t *pIntrBlock;
269 	u32_t intrPriority;
270 	int intrType;
271 
272 	volatile boolean_t intr_enabled;
273 	kmutex_t intr_mutex;
274 	uint32_t intr_count;
275 	uint32_t intr_no_change;
276 	uint32_t intr_in_disabled;
277 
278 	volatile boolean_t timer_enabled;
279 	kmutex_t tmr_mutex;
280 	timeout_id_t tmrtid;
281 	unsigned int timer_link_check_interval;
282 	unsigned int timer_link_check_counter;
283 	unsigned int timer_link_check_interval2;
284 	unsigned int timer_link_check_counter2;
285 
286 	volatile boolean_t dev_start;
287 	volatile boolean_t link_updates_ok;
288 
289 	os_param_t os_param;
290 	device_param_t dev_var;
291 
292 	u32_t tx_copy_threshold;
293 
294 	u32_t no_tx_credits;
295 #define	BNX_TX_RESOURCES_NO_CREDIT	0x01
296 #define	BNX_TX_RESOURCES_NO_DESC	0x02
297 /* Unable to allocate DMA resources. (e.g. bind error) */
298 #define	BNX_TX_RESOURCES_NO_OS_DMA_RES	0x08
299 #define	BNX_TX_RESOURCES_TOO_MANY_FRAGS	0x10
300 
301 	um_xmit_qinfo txq[NUM_TX_CHAIN];
302 #define	_TX_QINFO(pdev, chain)	(pdev->txq[chain])
303 #define	_TXQ_FREE_DESC(pdev, chain) (pdev->txq[chain].free_tx_desc)
304 #define	_TXQ_RESC_DESC(pdev, chain) (pdev->txq[chain].tx_resc_que)
305 
306 	u32_t rx_copy_threshold;
307 	uint32_t recv_discards;
308 
309 	um_recv_qinfo rxq[NUM_RX_CHAIN];
310 #define	_RX_QINFO(pdev, chain)	(pdev->rxq[chain])
311 
312 	bnx_ndd_t nddcfg;
313 
314 	bnx_phy_cfg_t hwinit;
315 	bnx_phy_cfg_t curcfg;
316 	bnx_lnk_cfg_t remote;
317 
318 	char dev_name[BNX_STR_SIZE];
319 	int instance;
320 	char version[BNX_STR_SIZE];
321 	char versionFW[BNX_STR_SIZE];
322 	char chipName[BNX_STR_SIZE];
323 	char intrAlloc[BNX_STR_SIZE];
324 	u64_t intrFired;
325 
326 	kstat_t *kstats;
327 	kmutex_t kstatMutex;
328 
329 #define	BNX_MAX_MEMREQS	2
330 	unsigned int memcnt;
331 	bnx_memreq_t memreq[BNX_MAX_MEMREQS];
332 } um_device_t;
333 
334 
335 
336 /*
337  * Following structure defines the packet descriptor as seen by the UM module.
338  * This is used to map  buffers to lm_packet on xmit path and receive path.
339  */
340 
341 typedef	struct _um_txpacket_t {
342 	/* Must be the first entry in this structure. */
343 	struct _lm_packet_t lm_pkt;
344 
345 	mblk_t			*mp;
346 
347 	ddi_dma_handle_t	*cpyhdl;
348 	caddr_t			cpymem;
349 	lm_u64_t		cpyphy;
350 	off_t			cpyoff;
351 
352 	u32_t			num_handles;
353 	ddi_dma_handle_t	dma_handle[BNX_MAX_SGL_ENTRIES];
354 
355 	lm_frag_list_t		frag_list;
356 	lm_frag_t		frag_list_buffer[BNX_MAX_SGL_ENTRIES];
357 } um_txpacket_t;
358 
359 
360 
361 #define	BNX_RECV_MAX_FRAGS 1
362 typedef struct _um_rxpacket_t {
363 	/* Must be the first entry in this structure. */
364 	struct _lm_packet_t lmpacket;
365 
366 	ddi_dma_handle_t    dma_handle;
367 	ddi_acc_handle_t    dma_acc_handle;
368 } um_rxpacket_t;
369 
370 
371 #define	VLAN_TPID		0x8100u
372 #define	VLAN_TAGSZ		4
373 #define	VLAN_TAG_SIZE		4
374 #define	VLAN_VID_MAX    4094    /* 4095 is reserved */
375 
376 
377 typedef struct ether_vlan_header vlan_hdr_t;
378 #define	DRV_EXTRACT_VLAN_TPID(vhdrp)	htons(vhdrp->ether_tpid)
379 #define	DRV_EXTRACT_VLAN_TCI(vhdrp)	htons(vhdrp->ether_tci)
380 #define	DRV_SET_VLAN_TPID(vhdrp, tpid)	vhdrp->ether_tpid = htons(tpid)
381 #define	DRV_SET_VLAN_TCI(vhdrp, vtag)	vhdrp->ether_tci = htons(vtag)
382 
383 
384 
385 
386 
387 /*
388  *
389  *                      'ndd' Get/Set IOCTL Definition
390  *
391  */
392 
393 
394 /*
395  * (Internal) return values from ioctl subroutines
396  */
397 enum ioc_reply {
398 	IOC_INVAL = -1,			/* bad, NAK with EINVAL */
399 	IOC_DONE,			/* OK, reply sent */
400 	IOC_ACK,			/* OK, just send ACK */
401 	IOC_REPLY,			/* OK, just send reply */
402 	IOC_RESTART_ACK,		/* OK, restart & ACK */
403 	IOC_RESTART_REPLY		/* OK, restart & reply */
404 };
405 
406 /*
407  *			Function Prototypes
408  *
409  */
410 
411 ddi_dma_handle_t *bnx_find_dma_hdl(um_device_t * const umdevice,
412     const void * const virtaddr);
413 
414 void um_send_driver_pulse(um_device_t *udevp);
415 
416 int bnx_find_mchash_collision(lm_mc_table_t *mc_table,
417     const u8_t *const mc_addr);
418 
419 void bnx_update_phy(um_device_t *pdev);
420 
421 
422 boolean_t bnx_kstat_init(um_device_t *pUM);
423 void bnx_kstat_fini(um_device_t *pUM);
424 
425 #ifdef __cplusplus
426 }
427 #endif
428 
429 #endif /* _BNX_H */
430