1eef4f27Robert Mustacchi/*
2eef4f27Robert Mustacchi * Copyright 2014-2017 Cavium, Inc.
3eef4f27Robert Mustacchi * The contents of this file are subject to the terms of the Common Development
4eef4f27Robert Mustacchi * and Distribution License, v.1,  (the "License").
5eef4f27Robert Mustacchi *
6eef4f27Robert Mustacchi * You may not use this file except in compliance with the License.
7eef4f27Robert Mustacchi *
8eef4f27Robert Mustacchi * You can obtain a copy of the License at available
9eef4f27Robert Mustacchi * at http://opensource.org/licenses/CDDL-1.0
10eef4f27Robert Mustacchi *
11eef4f27Robert Mustacchi * See the License for the specific language governing permissions and
12eef4f27Robert Mustacchi * limitations under the License.
13eef4f27Robert Mustacchi */
14eef4f27Robert Mustacchi
15eef4f27Robert Mustacchi#ifndef _LM5706_H
16eef4f27Robert Mustacchi#define _LM5706_H
17eef4f27Robert Mustacchi
18eef4f27Robert Mustacchi
19eef4f27Robert Mustacchi#include "bcmtype.h"
20eef4f27Robert Mustacchi#include "debug.h"
21eef4f27Robert Mustacchi#include "5706_reg.h"
22eef4f27Robert Mustacchi#include "l2_defs.h"
23eef4f27Robert Mustacchi#include "l5_defs.h"
24eef4f27Robert Mustacchi#ifndef EXCLUDE_KQE_SUPPORT
25eef4f27Robert Mustacchi#include "l4_kqe.h"
26eef4f27Robert Mustacchi#endif
27eef4f27Robert Mustacchi#ifndef L2_ONLY
28eef4f27Robert Mustacchi#include "status_code.h"
29eef4f27Robert Mustacchi#endif
30eef4f27Robert Mustacchi#include "shmem.h"
31eef4f27Robert Mustacchi#include "lm_desc.h"
32eef4f27Robert Mustacchi#include "listq.h"
33eef4f27Robert Mustacchi#include "lm.h"
34eef4f27Robert Mustacchi#include "mm.h"
35eef4f27Robert Mustacchi#ifndef L2_ONLY
36eef4f27Robert Mustacchi#include "toe_ctx.h"
37eef4f27Robert Mustacchi#endif
38eef4f27Robert Mustacchi#ifdef UEFI
39eef4f27Robert Mustacchi#include "5706_efi.h"
40eef4f27Robert Mustacchi#endif
41eef4f27Robert Mustacchi#ifdef SOLARIS
42eef4f27Robert Mustacchi#include <sys/ddi.h>
43eef4f27Robert Mustacchi#include <sys/sunddi.h>
44eef4f27Robert Mustacchi#endif
45eef4f27Robert Mustacchi
46eef4f27Robert Mustacchi#ifdef LINUX /*lediag*/
47eef4f27Robert Mustacchi#include "../../mpd_driver_hybrid/pal2.h"
48eef4f27Robert Mustacchi#endif
49eef4f27Robert Mustacchi
50eef4f27Robert Mustacchitypedef struct fw_version
51eef4f27Robert Mustacchi{
52eef4f27Robert Mustacchi    u8_t    name[11];
53eef4f27Robert Mustacchi    u8_t    namez;
54eef4f27Robert Mustacchi    u32_t   version;
55eef4f27Robert Mustacchi} fw_version_t;
56eef4f27Robert Mustacchi
57eef4f27Robert Mustacchi#ifndef PRIVATE_HSI_HEADER
58eef4f27Robert Mustacchi#include "rxp_hsi.h"
59eef4f27Robert Mustacchi#include "com_hsi.h"
60eef4f27Robert Mustacchi#include "cp_hsi.h"
61eef4f27Robert Mustacchi#include "txp_hsi.h"
62eef4f27Robert Mustacchi#include "tpat_hsi.h"
63eef4f27Robert Mustacchi#else
64eef4f27Robert Mustacchi#include "hsi.h"
65eef4f27Robert Mustacchi#endif
66eef4f27Robert Mustacchi
67eef4f27Robert Mustacchi/*******************************************************************************
68eef4f27Robert Mustacchi * Constants.
69eef4f27Robert Mustacchi ******************************************************************************/
70eef4f27Robert Mustacchi
71eef4f27Robert Mustacchi#define MAX_TX_CHAIN                12
72eef4f27Robert Mustacchi#define MAX_RX_CHAIN                12
73eef4f27Robert Mustacchi#define FIRST_RSS_RXQ               4
74eef4f27Robert Mustacchi
75eef4f27Robert Mustacchi#ifndef NUM_RX_CHAIN
76eef4f27Robert Mustacchi#define NUM_RX_CHAIN                1
77eef4f27Robert Mustacchi#endif
78eef4f27Robert Mustacchi
79eef4f27Robert Mustacchi#ifndef NUM_TX_CHAIN
80eef4f27Robert Mustacchi#define NUM_TX_CHAIN                1
81eef4f27Robert Mustacchi#endif
82eef4f27Robert Mustacchi
83eef4f27Robert Mustacchi#if NUM_TX_CHAIN > MAX_TX_CHAIN
84eef4f27Robert Mustacchi#error Exceeded maximum number of tx chains.
85eef4f27Robert Mustacchi#endif
86eef4f27Robert Mustacchi
87eef4f27Robert Mustacchi#if NUM_RX_CHAIN > MAX_RX_CHAIN
88eef4f27Robert Mustacchi#error Exceeded maximum number of rx chains.
89eef4f27Robert Mustacchi#endif
90eef4f27Robert Mustacchi
91eef4f27Robert Mustacchi/* Number of bits must be 10 to 25. */
92eef4f27Robert Mustacchi#ifndef LM_PAGE_BITS
93eef4f27Robert Mustacchi#define LM_PAGE_BITS                            12  /* 4K page. */
94eef4f27Robert Mustacchi#endif
95eef4f27Robert Mustacchi
96eef4f27Robert Mustacchi#define LM_PAGE_SIZE                            (1 << LM_PAGE_BITS)
97eef4f27Robert Mustacchi#define LM_PAGE_MASK                            (LM_PAGE_SIZE - 1)
98eef4f27Robert Mustacchi
99eef4f27Robert Mustacchi
100eef4f27Robert Mustacchi#ifndef CACHE_LINE_SIZE_MASK
101eef4f27Robert Mustacchi#define CACHE_LINE_SIZE_MASK        0x3f
102eef4f27Robert Mustacchi#endif
103eef4f27Robert Mustacchi
104eef4f27Robert Mustacchi
105eef4f27Robert Mustacchi/* Number of packets per indication in calls to mm_indicate_rx/tx. */
106eef4f27Robert Mustacchi#ifndef MAX_PACKETS_PER_INDICATION
107eef4f27Robert Mustacchi#define MAX_PACKETS_PER_INDICATION  50
108eef4f27Robert Mustacchi#endif
109eef4f27Robert Mustacchi
110eef4f27Robert Mustacchi
111eef4f27Robert Mustacchi#ifndef MAX_FRAG_CNT
112eef4f27Robert Mustacchi#define MAX_FRAG_CNT                33
113eef4f27Robert Mustacchi#endif
114eef4f27Robert Mustacchi
115eef4f27Robert Mustacchi/* The maximum is actually 0xffff which can be described by a BD. */
116eef4f27Robert Mustacchi#define MAX_FRAGMENT_SIZE           0xf000
117eef4f27Robert Mustacchi
118eef4f27Robert Mustacchi
119eef4f27Robert Mustacchi/* Context size. */
120eef4f27Robert Mustacchi#define CTX_SHIFT                   7
121eef4f27Robert Mustacchi#define CTX_SIZE                    (1 << CTX_SHIFT)
122eef4f27Robert Mustacchi#define CTX_MASK                    (CTX_SIZE - 1)
123eef4f27Robert Mustacchi#define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)
124eef4f27Robert Mustacchi#define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)
125eef4f27Robert Mustacchi
126eef4f27Robert Mustacchi#define PHY_CTX_SHIFT               6
127eef4f27Robert Mustacchi#define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)
128eef4f27Robert Mustacchi#define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)
129eef4f27Robert Mustacchi#define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)
130eef4f27Robert Mustacchi#define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)
131eef4f27Robert Mustacchi
132eef4f27Robert Mustacchi#define MB_KERNEL_CTX_SHIFT         8
133eef4f27Robert Mustacchi#define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)
134eef4f27Robert Mustacchi#define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)
135eef4f27Robert Mustacchi/* #define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) */
136eef4f27Robert Mustacchi#define MB_GET_CID_ADDR(_p, _c)     lm_mb_get_cid_addr(_p, _c)
137eef4f27Robert Mustacchi
138eef4f27Robert Mustacchi#define MAX_CID_CNT                 0x4000
139eef4f27Robert Mustacchi#define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))
140eef4f27Robert Mustacchi#define INVALID_CID_ADDR            0xffffffff
141eef4f27Robert Mustacchi
142eef4f27Robert Mustacchi
143eef4f27Robert Mustacchi/* The size of the GRC window that appears in 32k-64k. */
144eef4f27Robert Mustacchi#define GRC_WINDOW_BASE             0x8000
145eef4f27Robert Mustacchi#define GRC_WINDOW_SIZE             0x8000
146eef4f27Robert Mustacchi
147eef4f27Robert Mustacchi
148eef4f27Robert Mustacchi/* L2 rx frame header size. */
149eef4f27Robert Mustacchi#define L2RX_FRAME_HDR_LEN          (sizeof(l2_fhdr_t)+2)
150eef4f27Robert Mustacchi
151eef4f27Robert Mustacchi
152eef4f27Robert Mustacchi/* The number of bd's per page including the last bd which is used as
153eef4f27Robert Mustacchi * a pointer to the next bd page. */
154eef4f27Robert Mustacchi#define BD_PER_PAGE                 (LM_PAGE_SIZE/sizeof(tx_bd_t))
155eef4f27Robert Mustacchi
156eef4f27Robert Mustacchi/* The number of useable bd's per page.  This number does not include
157eef4f27Robert Mustacchi * the last bd at the end of the page. */
158eef4f27Robert Mustacchi#define MAX_BD_PER_PAGE             ((u32_t) (BD_PER_PAGE-1))
159eef4f27Robert Mustacchi
160eef4f27Robert Mustacchi
161eef4f27Robert Mustacchi/* Buffer size of the statistics block. */
162eef4f27Robert Mustacchi#define CHIP_STATS_BUFFER_SIZE      ((sizeof(statistics_block_t) + \
163eef4f27Robert Mustacchi                                        CACHE_LINE_SIZE_MASK) & \
164eef4f27Robert Mustacchi                                        ~CACHE_LINE_SIZE_MASK)
165eef4f27Robert Mustacchi
166eef4f27Robert Mustacchi/* Buffer size of the status block. */
167eef4f27Robert Mustacchi#define STATUS_BLOCK_BUFFER_SIZE    ((sizeof(status_blk_combined_t) + \
168eef4f27Robert Mustacchi                                        CACHE_LINE_SIZE_MASK) & \
169eef4f27Robert Mustacchi                                        ~CACHE_LINE_SIZE_MASK)
170eef4f27Robert Mustacchi
171eef4f27Robert Mustacchi
172eef4f27Robert Mustacchi#define RSS_INDIRECTION_TABLE_SIZE  0x80    /* Maximum indirection table. */
173eef4f27Robert Mustacchi#define RSS_HASH_KEY_SIZE           0x40    /* Maximum key size. */
174eef4f27Robert Mustacchi#ifndef RSS_LOOKUP_TABLE_WA
175eef4f27Robert Mustacchi#define RSS_LOOKUP_TABLE_WA         (4*12*256)  /* 0 to disable workaround. */
176eef4f27Robert Mustacchi#endif
177eef4f27Robert Mustacchi
178eef4f27Robert Mustacchi
179eef4f27Robert Mustacchi/* Quick context assigments. */
180eef4f27Robert Mustacchi#define L2RX_CID_BASE               0       /* 0-15 */
181eef4f27Robert Mustacchi#define L2TX_CID_BASE               16      /* 16-23 */
182eef4f27Robert Mustacchi#define KWQ_CID                     24
183eef4f27Robert Mustacchi#define KCQ_CID                     25
184eef4f27Robert Mustacchi#define HCOPY_CID                   26      /* 26-27 */
185eef4f27Robert Mustacchi#define GEN_CHAIN_CID               29
186eef4f27Robert Mustacchi
187eef4f27Robert Mustacchi/* Xinan definitions. */
188eef4f27Robert Mustacchi#define L2TX_TSS_CID_BASE           32      /* 32-43 */
189eef4f27Robert Mustacchi
190eef4f27Robert Mustacchi/* MSIX definitions. */
191eef4f27Robert Mustacchi#define IRQ_MODE_UNKNOWN            0
192eef4f27Robert Mustacchi#define IRQ_MODE_LINE_BASED         1
193eef4f27Robert Mustacchi#define IRQ_MODE_SIMD               2
194eef4f27Robert Mustacchi#define IRQ_MODE_MSI_BASED          3
195eef4f27Robert Mustacchi#define IRQ_MODE_MSIX_BASED         4
196eef4f27Robert Mustacchi#define MAX_MSIX_HW_VEC             9
197eef4f27Robert Mustacchi#define PCI_GRC_WINDOW2_BASE        0xc000
198eef4f27Robert Mustacchi#define PCI_GRC_WINDOW3_BASE        0xe000
199eef4f27Robert Mustacchi#define MSIX_TABLE_ADDR             0x318000
200eef4f27Robert Mustacchi#define MSIX_PBA_ADDR               0x31c000
201eef4f27Robert Mustacchi
202eef4f27Robert Mustacchi/*******************************************************************************
203eef4f27Robert Mustacchi * Macros.
204eef4f27Robert Mustacchi ******************************************************************************/
205eef4f27Robert Mustacchi
206eef4f27Robert Mustacchi/* These macros have been moved to bcmtype.h. */
207eef4f27Robert Mustacchi#if 0
208eef4f27Robert Mustacchi/* Signed subtraction macros with no sign extending.  */
209eef4f27Robert Mustacchi#define S64_SUB(_a, _b)     ((s64_t) ((s64_t) (_a) - (s64_t) (_b)))
210eef4f27Robert Mustacchi#define u64_SUB(_a, _b)     ((u64_t) ((s64_t) (_a) - (s64_t) (_b)))
211eef4f27Robert Mustacchi#define S32_SUB(_a, _b)     ((s32_t) ((s32_t) (_a) - (s32_t) (_b)))
212eef4f27Robert Mustacchi#define uS32_SUB(_a, _b)    ((u32_t) ((s32_t) (_a) - (s32_t) (_b)))
213eef4f27Robert Mustacchi#define S16_SUB(_a, _b)     ((s16_t) ((s16_t) (_a) - (s16_t) (_b)))
214eef4f27Robert Mustacchi#define u16_SUB(_a, _b)     ((u16_t) ((s16_t) (_a) - (s16_t) (_b)))
215eef4f27Robert Mustacchi#define PTR_SUB(_a, _b)     ((u8_t *) (_a) - (u8_t *) (_b))
216eef4f27Robert Mustacchi#endif
217eef4f27Robert Mustacchi
218eef4f27Robert Mustacchi#ifndef OFFSETOF
219eef4f27Robert Mustacchi#define OFFSETOF(_s, _m)    ((u32_t) PTR_SUB(&((_s *) 0)->_m, (u8_t *) 0))
220eef4f27Robert Mustacchi#endif
221eef4f27Robert Mustacchi#define WORD_ALIGNED_OFFSETOF(_s, _m)       (OFFSETOF(_s, _m) & ~0x03)
222eef4f27Robert Mustacchi
223eef4f27Robert Mustacchi
224eef4f27Robert Mustacchi/* STATIC void
225eef4f27Robert Mustacchi * get_attn_chng_bits(
226eef4f27Robert Mustacchi *     lm_device_t *pdev,
227eef4f27Robert Mustacchi *     u32_t *asserted_attns,
228eef4f27Robert Mustacchi *     u32_t *deasserted_attns); */
229eef4f27Robert Mustacchi#define GET_ATTN_CHNG_BITS(_pdev, _asserted_attns_ptr, _deasserted_attns_ptr) \
230eef4f27Robert Mustacchi    {                                                                         \
231eef4f27Robert Mustacchi        u32_t attn_chng;                                                      \
232eef4f27Robert Mustacchi        u32_t attn_bits;                                                      \
233eef4f27Robert Mustacchi        u32_t attn_ack;                                                       \
234eef4f27Robert Mustacchi                                                                              \
235eef4f27Robert Mustacchi        attn_bits = (_pdev)->vars.status_virt->deflt.status_attn_bits;        \
236eef4f27Robert Mustacchi        attn_ack = (_pdev)->vars.status_virt->deflt.status_attn_bits_ack;     \
237eef4f27Robert Mustacchi                                                                              \
238eef4f27Robert Mustacchi        attn_chng = attn_bits ^ attn_ack;                                     \
239eef4f27Robert Mustacchi                                                                              \
240eef4f27Robert Mustacchi        *(_asserted_attns_ptr) = attn_bits & attn_chng;                       \
241eef4f27Robert Mustacchi        *(_deasserted_attns_ptr) = ~attn_bits & attn_chng;                    \
242eef4f27Robert Mustacchi    }
243eef4f27Robert Mustacchi
244eef4f27Robert Mustacchi
245eef4f27Robert Mustacchi
246eef4f27Robert Mustacchi/*******************************************************************************
247eef4f27Robert Mustacchi * Statistics.
248eef4f27Robert Mustacchi ******************************************************************************/
249eef4f27Robert Mustacchi
250eef4f27Robert Mustacchitypedef struct _lm_tx_statistics_t
251eef4f27Robert Mustacchi{
252eef4f27Robert Mustacchi    lm_u64_t ipv4_lso_frames;
253eef4f27Robert Mustacchi    lm_u64_t ipv6_lso_frames;
254eef4f27Robert Mustacchi    lm_u64_t ip_cso_frames;
255eef4f27Robert Mustacchi    lm_u64_t ipv4_tcp_udp_cso_frames;
256eef4f27Robert Mustacchi    lm_u64_t ipv6_tcp_udp_cso_frames;
257eef4f27Robert Mustacchi    u32_t aborted;
258eef4f27Robert Mustacchi    u32_t no_bd;
259eef4f27Robert Mustacchi    u32_t no_desc;
260eef4f27Robert Mustacchi    u32_t no_coalesce_buf;
261eef4f27Robert Mustacchi    u32_t no_map_reg;
262eef4f27Robert Mustacchi} lm_tx_stats_t;
263eef4f27Robert Mustacchi
264eef4f27Robert Mustacchi
265eef4f27Robert Mustacchitypedef struct _lm_rx_statistics_t
266eef4f27Robert Mustacchi{
267eef4f27Robert Mustacchi    u32_t aborted;
268eef4f27Robert Mustacchi    u32_t err;
269eef4f27Robert Mustacchi    u32_t crc;
270eef4f27Robert Mustacchi    u32_t phy_err;
271eef4f27Robert Mustacchi    u32_t alignment;
272eef4f27Robert Mustacchi    u32_t short_packet;
273eef4f27Robert Mustacchi    u32_t giant_packet;
274eef4f27Robert Mustacchi} lm_rx_stats_t;
275eef4f27Robert Mustacchi
276eef4f27Robert Mustacchi
277eef4f27Robert Mustacchi
278eef4f27Robert Mustacchi/*******************************************************************************
279eef4f27Robert Mustacchi * Packet descriptor.
280eef4f27Robert Mustacchi ******************************************************************************/
281eef4f27Robert Mustacchi#if defined(LM_NON_LEGACY_MODE_SUPPORT)
282eef4f27Robert Mustacchitypedef struct _lm_packet_t
283eef4f27Robert Mustacchi{
284eef4f27Robert Mustacchi    /* Must be the first entry in this structure. */
285eef4f27Robert Mustacchi    s_list_entry_t link;
286eef4f27Robert Mustacchi
287eef4f27Robert Mustacchi    lm_status_t status;
288eef4f27Robert Mustacchi
289eef4f27Robert Mustacchi    union _lm_pkt_info_t
290eef4f27Robert Mustacchi    {
291eef4f27Robert Mustacchi        struct _tx_pkt_info_t
292eef4f27Robert Mustacchi        {
293eef4f27Robert Mustacchi            lm_pkt_tx_info_t *tx_pkt_info;
294eef4f27Robert Mustacchi            u16_t next_bd_idx;
295eef4f27Robert Mustacchi            u16_t bd_used;
296eef4f27Robert Mustacchi            u8_t span_pages;
297eef4f27Robert Mustacchi            u8_t  pad;
298eef4f27Robert Mustacchi            u16_t pad1;
299eef4f27Robert Mustacchi            u32_t size;
300eef4f27Robert Mustacchi            #if DBG
301eef4f27Robert Mustacchi            tx_bd_t *dbg_start_bd;
302eef4f27Robert Mustacchi            u16_t dbg_start_bd_idx;
303eef4f27Robert Mustacchi            u16_t dbg_frag_cnt;
304eef4f27Robert Mustacchi            #endif
305eef4f27Robert Mustacchi        } tx;
306eef4f27Robert Mustacchi
307eef4f27Robert Mustacchi        struct _rx_pkt_info_t
308eef4f27Robert Mustacchi        {
309eef4f27Robert Mustacchi            lm_pkt_rx_info_t *rx_pkt_info;
310eef4f27Robert Mustacchi            u16_t next_bd_idx;
311eef4f27Robert Mustacchi            u16_t pad;
312eef4f27Robert Mustacchi            u32_t hash_value;           /* RSS hash value. */
313eef4f27Robert Mustacchi            #if DBG
314eef4f27Robert Mustacchi            rx_bd_t *dbg_bd;
315eef4f27Robert Mustacchi            rx_bd_t *dbg_bd1; /* when vmq header split is enabled */
316eef4f27Robert Mustacchi            #endif
317eef4f27Robert Mustacchi        } rx;
318eef4f27Robert Mustacchi    } u1;
319eef4f27Robert Mustacchi} lm_packet_t;
320eef4f27Robert Mustacchi#else
321eef4f27Robert Mustacchitypedef struct _lm_packet_t
322eef4f27Robert Mustacchi{
323eef4f27Robert Mustacchi    /* Must be the first entry in this structure. */
324eef4f27Robert Mustacchi    s_list_entry_t link;
325eef4f27Robert Mustacchi
326eef4f27Robert Mustacchi    lm_status_t status;
327eef4f27Robert Mustacchi    u32_t size;
328eef4f27Robert Mustacchi
329eef4f27Robert Mustacchi    union _lm_pkt_info_t
330eef4f27Robert Mustacchi    {
331eef4f27Robert Mustacchi        struct _lm_tx_pkt_info_t
332eef4f27Robert Mustacchi        {
333eef4f27Robert Mustacchi            lm_tx_flag_t flags;
334eef4f27Robert Mustacchi
335eef4f27Robert Mustacchi            u16_t vlan_tag;
336eef4f27Robert Mustacchi            u16_t next_bd_idx;
337eef4f27Robert Mustacchi            u16_t bd_used;
338eef4f27Robert Mustacchi            u8_t span_pages;
339eef4f27Robert Mustacchi            u8_t _pad;
340eef4f27Robert Mustacchi
341eef4f27Robert Mustacchi            u16_t lso_mss;
342eef4f27Robert Mustacchi            u16_t _pad2;
343eef4f27Robert Mustacchi
344eef4f27Robert Mustacchi            u16_t lso_ip_hdr_len;
345eef4f27Robert Mustacchi            u16_t lso_tcp_hdr_len;
346eef4f27Robert Mustacchi
347eef4f27Robert Mustacchi            #if DBG
348eef4f27Robert Mustacchi            tx_bd_t *dbg_start_bd;
349eef4f27Robert Mustacchi            u16_t dbg_start_bd_idx;
350eef4f27Robert Mustacchi            u16_t dbg_frag_cnt;
351eef4f27Robert Mustacchi            #endif
352eef4f27Robert Mustacchi        } tx;
353eef4f27Robert Mustacchi
354eef4f27Robert Mustacchi        struct _lm_rx_pkt_info_t
355eef4f27Robert Mustacchi        {
356eef4f27Robert Mustacchi            lm_rx_flag_t flags;
357eef4f27Robert Mustacchi
358eef4f27Robert Mustacchi            u16_t vlan_tag;
359eef4f27Robert Mustacchi            u16_t ip_cksum;
360eef4f27Robert Mustacchi            u16_t tcp_or_udp_cksum;
361eef4f27Robert Mustacchi            u16_t next_bd_idx;
362eef4f27Robert Mustacchi
363eef4f27Robert Mustacchi            u8_t *mem_virt;
364eef4f27Robert Mustacchi            lm_address_t mem_phy;
365eef4f27Robert Mustacchi            u32_t buf_size;
366eef4f27Robert Mustacchi
367eef4f27Robert Mustacchi            u32_t hash_value;           /* RSS hash value. */
368eef4f27Robert Mustacchi
369eef4f27Robert Mustacchi            #if DBG
370eef4f27Robert Mustacchi            rx_bd_t *dbg_bd;
371eef4f27Robert Mustacchi            #endif
372eef4f27Robert Mustacchi        } rx;
373eef4f27Robert Mustacchi    } u1;
374eef4f27Robert Mustacchi} lm_packet_t;
375eef4f27Robert Mustacchi#endif
376eef4f27Robert Mustacchi
377eef4f27Robert MustacchiDECLARE_FRAG_LIST_BUFFER_TYPE(lm_packet_frag_list_t, MAX_FRAG_CNT);
378eef4f27Robert Mustacchi
379eef4f27Robert Mustacchi
380eef4f27Robert Mustacchi
381eef4f27Robert Mustacchi/*******************************************************************************
382eef4f27Robert Mustacchi * Configurable parameters for the hardware dependent module.
383eef4f27Robert Mustacchi ******************************************************************************/
384eef4f27Robert Mustacchi
385eef4f27Robert Mustacchitypedef struct _lm_params_t
386eef4f27Robert Mustacchi{
387eef4f27Robert Mustacchi    /* This value is used by the upper module to inform the protocol
388eef4f27Robert Mustacchi     * of the maximum transmit/receive packet size.  Packet size
389eef4f27Robert Mustacchi     * ranges from 1514-9014 bytes.  This value does not include CRC32 and
390eef4f27Robert Mustacchi     * VLAN tag. */
391eef4f27Robert Mustacchi    u32_t mtu;
392eef4f27Robert Mustacchi    /* Current node address.  The MAC address is initially set to the
393eef4f27Robert Mustacchi     * hardware address.  This entry can be modified to allow the driver
394eef4f27Robert Mustacchi     * to override the default MAC address.  The new MAC address takes
395eef4f27Robert Mustacchi     * effect after a driver reset. */
396eef4f27Robert Mustacchi    u8_t mac_addr[8];
397eef4f27Robert Mustacchi
398eef4f27Robert Mustacchi    u32_t l2_rx_desc_cnt[MAX_RX_CHAIN];
399eef4f27Robert Mustacchi    u32_t l2_tx_bd_page_cnt[MAX_TX_CHAIN];
400eef4f27Robert Mustacchi    u32_t l2_rx_bd_page_cnt[MAX_RX_CHAIN];
401eef4f27Robert Mustacchi
402eef4f27Robert Mustacchi    u32_t l4_tx_bd_page_cnt;
403eef4f27Robert Mustacchi    u32_t limit_l4_tx_bd_cnt;
404eef4f27Robert Mustacchi    u32_t l4_rx_bd_page_cnt;
405eef4f27Robert Mustacchi    u32_t limit_l4_rx_bd_cnt;
406eef4f27Robert Mustacchi
407eef4f27Robert Mustacchi    #ifndef EXCLUDE_KQE_SUPPORT
408eef4f27Robert Mustacchi    u32_t kwq_page_cnt;
409eef4f27Robert Mustacchi    u32_t kcq_page_cnt;
410eef4f27Robert Mustacchi    u32_t kcq_history_size;
411eef4f27Robert Mustacchi    u32_t con_kcqe_history_size;
412eef4f27Robert Mustacchi    u32_t con_kwqe_history_size;
413eef4f27Robert Mustacchi    #endif
414eef4f27Robert Mustacchi
415eef4f27Robert Mustacchi    u32_t gen_bd_page_cnt;
416eef4f27Robert Mustacchi    u32_t max_gen_buf_cnt;
417eef4f27Robert Mustacchi    u32_t gen_buf_per_alloc;
418eef4f27Robert Mustacchi
419eef4f27Robert Mustacchi    /* This parameter controls whether the buffered data (generic buffers)
420eef4f27Robert Mustacchi     * should be copied to a staging buffer for indication. */
421eef4f27Robert Mustacchi    u32_t copy_buffered_data;
422eef4f27Robert Mustacchi
423eef4f27Robert Mustacchi    /* All the L2 receive buffers start at a cache line size aligned
424eef4f27Robert Mustacchi     * address.  This value determines the location of the L2 frame header
425eef4f27Robert Mustacchi     * from the beginning of the receive buffer.  The value must be a
426eef4f27Robert Mustacchi     * multiple of 4. */
427eef4f27Robert Mustacchi    u32_t rcv_buffer_offset;
428eef4f27Robert Mustacchi
429eef4f27Robert Mustacchi    /* Enable a separate receive queue for receiving packets with
430eef4f27Robert Mustacchi     * TCP SYN bit set. */
431eef4f27Robert Mustacchi    u32_t enable_syn_rcvq;
432eef4f27Robert Mustacchi
433eef4f27Robert Mustacchi    /* Buffer of hcopy descriptor to allocate for a connection.  When
434eef4f27Robert Mustacchi     * this value is 0, hcopy is disabled. */
435eef4f27Robert Mustacchi    u32_t hcopy_desc_cnt;
436eef4f27Robert Mustacchi
437eef4f27Robert Mustacchi    /* Number of pages used for the hcopy bd chain. */
438eef4f27Robert Mustacchi    u32_t hcopy_bd_page_cnt;
439eef4f27Robert Mustacchi
440eef4f27Robert Mustacchi    /* This parameter is only valid when enable_hcopy is enabled.
441eef4f27Robert Mustacchi     * When enable_hcopy is enabled, a given connection will not
442eef4f27Robert Mustacchi     * be able to process subsequent kcqe's after the copy_gen kcqe
443eef4f27Robert Mustacchi     * until the hcopy request (for the copy_gen) has completed.
444eef4f27Robert Mustacchi     * The subsequent kcqe's will be copied to a per-connection kcq
445eef4f27Robert Mustacchi     * buffer.  The parameter controls the size of this buffer. */
446eef4f27Robert Mustacchi    u32_t buffered_kcqe_cnt;
447eef4f27Robert Mustacchi
448eef4f27Robert Mustacchi    /* Size of the deferred kcqe queue. */
449eef4f27Robert Mustacchi    u32_t deferred_kcqe_cnt;
450eef4f27Robert Mustacchi
451eef4f27Robert Mustacchi    /* Various test/debug modes.  Any validation failure will cause the
452eef4f27Robert Mustacchi     * driver to write to misc.swap_diag0 with the corresponding flag.
453eef4f27Robert Mustacchi     * The intention is to trigger the bus analyzer. */
454eef4f27Robert Mustacchi    u32_t test_mode;
455eef4f27Robert Mustacchi    #define TEST_MODE_DISABLED                  0x00
456eef4f27Robert Mustacchi    #define TEST_MODE_OBSOLETE_0                0x01    /* was TEST_MODE_IKOS */
457eef4f27Robert Mustacchi    #define TEST_MODE_OBSOLETE_1                0x02    /* was TEST_MODE_FPGA */
458eef4f27Robert Mustacchi    #define TEST_MODE_VERIFY_RX_CRC             0x10
459eef4f27Robert Mustacchi    #define TEST_MODE_RX_BD_TAGGING             0x20
460eef4f27Robert Mustacchi    #define TEST_MODE_TX_BD_TAGGING             0x40
461eef4f27Robert Mustacchi    #define TEST_MODE_LOG_REG_ACCESS            0x80
462eef4f27Robert Mustacchi    #define TEST_MODE_SAVE_DUMMY_DMA_DATA       0x0100
463eef4f27Robert Mustacchi    #define TEST_MODE_INIT_GEN_BUF_DATA         0x0200
464eef4f27Robert Mustacchi    #define TEST_MODE_DRIVER_PULSE_ALWAYS_ALIVE 0x0400
465eef4f27Robert Mustacchi    #define TEST_MODE_IGNORE_SHMEM_SIGNATURE    0x0800
466eef4f27Robert Mustacchi    #define TEST_MODE_XDIAG_ISCSI               0x1000
467eef4f27Robert Mustacchi
468eef4f27Robert Mustacchi    lm_offload_t ofld_cap;
469eef4f27Robert Mustacchi    lm_wake_up_mode_t wol_cap;
470eef4f27Robert Mustacchi    lm_flow_control_t flow_ctrl_cap;
471eef4f27Robert Mustacchi    lm_medium_t req_medium;
472eef4f27Robert Mustacchi
473eef4f27Robert Mustacchi    u32_t selective_autoneg;
474eef4f27Robert Mustacchi    #define SELECTIVE_AUTONEG_OFF                   0
475eef4f27Robert Mustacchi    #define SELECTIVE_AUTONEG_SINGLE_SPEED          1
476eef4f27Robert Mustacchi    #define SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS  2
477eef4f27Robert Mustacchi
478eef4f27Robert Mustacchi    u32_t wire_speed;                           /* Not valid on SERDES. */
479eef4f27Robert Mustacchi    u32_t phy_addr;                             /* PHY address. */
480eef4f27Robert Mustacchi
481eef4f27Robert Mustacchi    /* Ways for the MAC to determine a link change. */
482eef4f27Robert Mustacchi    u32_t phy_int_mode;
483eef4f27Robert Mustacchi    #define PHY_INT_MODE_AUTO                   0
484eef4f27Robert Mustacchi    #define PHY_INT_MODE_MI_INTERRUPT           1
485eef4f27Robert Mustacchi    #define PHY_INT_MODE_LINK_READY             2
486eef4f27Robert Mustacchi    #define PHY_INT_MODE_AUTO_POLLING           3
487eef4f27Robert Mustacchi
488eef4f27Robert Mustacchi    /* Ways for the driver to get the link change event. */
489eef4f27Robert Mustacchi    u32_t link_chng_mode;
490eef4f27Robert Mustacchi    #define LINK_CHNG_MODE_AUTO                 0
491eef4f27Robert Mustacchi    #define LINK_CHNG_MODE_USE_STATUS_REG       1
492eef4f27Robert Mustacchi    #define LINK_CHNG_MODE_USE_STATUS_BLOCK     2
493eef4f27Robert Mustacchi
494eef4f27Robert Mustacchi    /* Coalescing paramers. */
495eef4f27Robert Mustacchi    u32_t hc_timer_mode;
496eef4f27Robert Mustacchi    #define HC_COLLECT_MODE                     0x0000
497eef4f27Robert Mustacchi    #define HC_RX_TIMER_MODE                    0x0001
498eef4f27Robert Mustacchi    #define HC_TX_TIMER_MODE                    0x0002
499eef4f27Robert Mustacchi    #define HC_COM_TIMER_MODE                   0x0004
500eef4f27Robert Mustacchi    #define HC_CMD_TIMER_MODE                   0x0008
501eef4f27Robert Mustacchi    #define HC_TIMER_MODE                       0x000f
502eef4f27Robert Mustacchi
503eef4f27Robert Mustacchi    u32_t ind_comp_limit;
504eef4f27Robert Mustacchi    u32_t tx_quick_cons_trip;
505eef4f27Robert Mustacchi    u32_t tx_quick_cons_trip_int;
506eef4f27Robert Mustacchi    u32_t rx_quick_cons_trip;
507eef4f27Robert Mustacchi    u32_t rx_quick_cons_trip_int;
508eef4f27Robert Mustacchi    u32_t comp_prod_trip;
509eef4f27Robert Mustacchi    u32_t comp_prod_trip_int;
510eef4f27Robert Mustacchi    u32_t tx_ticks;
511eef4f27Robert Mustacchi    u32_t tx_ticks_int;
512eef4f27Robert Mustacchi    u32_t com_ticks;
513eef4f27Robert Mustacchi    u32_t com_ticks_int;
514eef4f27Robert Mustacchi    u32_t cmd_ticks;
515eef4f27Robert Mustacchi    u32_t cmd_ticks_int;
516eef4f27Robert Mustacchi    u32_t rx_ticks;
517eef4f27Robert Mustacchi    u32_t rx_ticks_int;
518eef4f27Robert Mustacchi    u32_t stats_ticks;
519eef4f27Robert Mustacchi
520eef4f27Robert Mustacchi    /* Xinan per-processor HC configuration. */
521eef4f27Robert Mustacchi    u32_t psb_tx_cons_trip;
522eef4f27Robert Mustacchi    u32_t psb_tx_ticks;
523eef4f27Robert Mustacchi    u32_t psb_rx_cons_trip;
524eef4f27Robert Mustacchi    u32_t psb_rx_ticks;
525eef4f27Robert Mustacchi    u32_t psb_comp_prod_trip;
526eef4f27Robert Mustacchi    u32_t psb_com_ticks;
527eef4f27Robert Mustacchi    u32_t psb_cmd_ticks;
528eef4f27Robert Mustacchi    u32_t psb_period_ticks;
529eef4f27Robert Mustacchi
530eef4f27Robert Mustacchi    u32_t enable_fir;
531eef4f27Robert Mustacchi    u32_t num_rchans;
532eef4f27Robert Mustacchi    u32_t num_wchans;
533eef4f27Robert Mustacchi    u32_t one_tdma;
534eef4f27Robert Mustacchi    u32_t ping_pong_dma;
535eef4f27Robert Mustacchi    u32_t serdes_pre_emphasis;
536eef4f27Robert Mustacchi    u32_t tmr_reload_value1;
537eef4f27Robert Mustacchi
538eef4f27Robert Mustacchi    u32_t keep_vlan_tag;
539eef4f27Robert Mustacchi
540eef4f27Robert Mustacchi    u32_t enable_remote_phy;
541eef4f27Robert Mustacchi    u32_t rphy_req_medium;
542eef4f27Robert Mustacchi    u32_t rphy_flow_ctrl_cap;
543eef4f27Robert Mustacchi    u32_t rphy_selective_autoneg;
544eef4f27Robert Mustacchi    u32_t rphy_wire_speed;
545eef4f27Robert Mustacchi
546eef4f27Robert Mustacchi    u32_t bin_mq_mode;
547eef4f27Robert Mustacchi    u32_t validate_l4_data;
548eef4f27Robert Mustacchi
549eef4f27Robert Mustacchi    /* disable PCIe non-FATAL error reporting */
550eef4f27Robert Mustacchi    u32_t disable_pcie_nfr;
551eef4f27Robert Mustacchi
552eef4f27Robert Mustacchi    // setting for L2 flow control 0 for disable 1 for enable:
553eef4f27Robert Mustacchi    u32_t fw_flow_control;
554eef4f27Robert Mustacchi    // This parameter dictates how long to wait before dropping L2 packet
555eef4f27Robert Mustacchi    // due to insufficient posted buffers
556eef4f27Robert Mustacchi    // 0 mean no waiting before dropping, 0xFFFF means maximum wait
557eef4f27Robert Mustacchi    u32_t fw_flow_control_wait;
558eef4f27Robert Mustacchi    // 8 lsb represents watermark for flow control, 0 is disable
559eef4f27Robert Mustacchi    u32_t fw_flow_control_watermarks;
560eef4f27Robert Mustacchi
561eef4f27Robert Mustacchi    u32_t ena_large_grc_timeout;
562eef4f27Robert Mustacchi
563eef4f27Robert Mustacchi    /* 0 causes the driver to report the current flow control configuration.
564eef4f27Robert Mustacchi     * 1 causes the driver to report the flow control autoneg result. */
565eef4f27Robert Mustacchi    u32_t flow_control_reporting_mode;
566eef4f27Robert Mustacchi} lm_params_t;
567eef4f27Robert Mustacchi
568eef4f27Robert Mustacchi
569eef4f27Robert Mustacchi
570eef4f27Robert Mustacchi/*******************************************************************************
571eef4f27Robert Mustacchi * Device NVM info -- The native strapping does not support the new parts, the
572eef4f27Robert Mustacchi *                    software needs to reconfigure for them.
573eef4f27Robert Mustacchi ******************************************************************************/
574eef4f27Robert Mustacchi
575eef4f27Robert Mustacchitypedef struct _flash_spec_t
576eef4f27Robert Mustacchi{
577eef4f27Robert Mustacchi    u32_t buffered;
578eef4f27Robert Mustacchi    u32_t shift_bits;
579eef4f27Robert Mustacchi    u32_t page_size;
580eef4f27Robert Mustacchi    u32_t addr_mask;
581eef4f27Robert Mustacchi    u32_t total_size;
582eef4f27Robert Mustacchi} flash_spec_t;
583eef4f27Robert Mustacchi
584eef4f27Robert Mustacchi
585eef4f27Robert Mustacchi/*******************************************************************************
586eef4f27Robert Mustacchi * Device info.
587eef4f27Robert Mustacchi ******************************************************************************/
588eef4f27Robert Mustacchi
589eef4f27Robert Mustacchitypedef struct _lm_hardware_info_t
590eef4f27Robert Mustacchi{
591eef4f27Robert Mustacchi    /* PCI info. */
592eef4f27Robert Mustacchi    u16_t vid;
593eef4f27Robert Mustacchi    u16_t did;
594eef4f27Robert Mustacchi    u16_t ssid;
595eef4f27Robert Mustacchi    u16_t svid;
596eef4f27Robert Mustacchi
597eef4f27Robert Mustacchi    u8_t irq;
598eef4f27Robert Mustacchi    u8_t int_pin;
599eef4f27Robert Mustacchi    u8_t latency_timer;
600eef4f27Robert Mustacchi    u8_t cache_line_size;
601eef4f27Robert Mustacchi    u8_t rev_id;
602eef4f27Robert Mustacchi    u8_t _pad[3];
603eef4f27Robert Mustacchi
604eef4f27Robert Mustacchi    u8_t mac_id;            /* 5709 function 0 or 1. */
605eef4f27Robert Mustacchi    u8_t bin_size;          /* 5709 bin size in term of context pages. */
606eef4f27Robert Mustacchi    u16_t first_l4_l5_bin;  /* 5709 first bin. */
607eef4f27Robert Mustacchi
608eef4f27Robert Mustacchi    lm_address_t mem_base;
609eef4f27Robert Mustacchi    u32_t bar_size;
610eef4f27Robert Mustacchi
611eef4f27Robert Mustacchi    /* Device info. */
612eef4f27Robert Mustacchi    u32_t phy_id;               /* (phy_reg2 << 16) | phy_reg3 */
613eef4f27Robert Mustacchi    u8_t mac_addr[8];           /* Hardware MAC address. */
614eef4f27Robert Mustacchi    u8_t iscsi_mac_addr[8];     /* Hardware MAC address for iSCSI. */
615eef4f27Robert Mustacchi
616eef4f27Robert Mustacchi    u32_t shmem_base;           /* Firmware share memory base addr. */
617eef4f27Robert Mustacchi
618eef4f27Robert Mustacchi    u32_t chip_id;      /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
619eef4f27Robert Mustacchi    #define CHIP_NUM(_p)                (((_p)->hw_info.chip_id) & 0xffff0000)
620eef4f27Robert Mustacchi    #define CHIP_NUM_5706               0x57060000
621eef4f27Robert Mustacchi    #define CHIP_NUM_5708               0x57080000
622eef4f27Robert Mustacchi    #define CHIP_NUM_5709               0x57090000
623eef4f27Robert Mustacchi    #define CHIP_NUM_57728              0x00000000
624eef4f27Robert Mustacchi
625eef4f27Robert Mustacchi    #define CHIP_REV(_p)                (((_p)->hw_info.chip_id) & 0x0000f000)
626eef4f27Robert Mustacchi    #define CHIP_REV_Ax                 0x00000000
627eef4f27Robert Mustacchi    #define CHIP_REV_Bx                 0x00001000
628eef4f27Robert Mustacchi    #define CHIP_REV_Cx                 0x00002000
629eef4f27Robert Mustacchi    #define CHIP_REV_FPGA               0x0000f000
630eef4f27Robert Mustacchi    #define CHIP_REV_IKOS               0x0000e000
631eef4f27Robert Mustacchi
632eef4f27Robert Mustacchi    #define CHIP_METAL(_p)              (((_p)->hw_info.chip_id) & 0x00000ff0)
633eef4f27Robert Mustacchi    #define CHIP_BONDING(_p)            (((_p)->hw_info.chip_id) & 0x0000000f)
634eef4f27Robert Mustacchi
635eef4f27Robert Mustacchi    #define CHIP_ID(_p)                 (((_p)->hw_info.chip_id) & 0xfffffff0)
636eef4f27Robert Mustacchi    #define CHIP_ID_5706_A0             0x57060000
637eef4f27Robert Mustacchi    #define CHIP_ID_5706_A1             0x57060010
638eef4f27Robert Mustacchi    #define CHIP_ID_5706_FPGA           0x5706f000
639eef4f27Robert Mustacchi    #define CHIP_ID_5706_IKOS           0x5706e000
640eef4f27Robert Mustacchi    #define CHIP_ID_5708_A0             0x57080000
641eef4f27Robert Mustacchi    #define CHIP_ID_5708_B0             0x57081000
642eef4f27Robert Mustacchi    #define CHIP_ID_5708_B1             0x57081010
643eef4f27Robert Mustacchi    #define CHIP_ID_5708_FPGA           0x5708f000
644eef4f27Robert Mustacchi    #define CHIP_ID_5708_IKOS           0x5708e000
645eef4f27Robert Mustacchi    #define CHIP_ID_5709_A0             0x57090000
646eef4f27Robert Mustacchi    #define CHIP_ID_5709_A1             0x57090010
647eef4f27Robert Mustacchi    #define CHIP_ID_5709_B0             0x57091000
648eef4f27Robert Mustacchi    #define CHIP_ID_5709_B1             0x57091010
649eef4f27Robert Mustacchi    #define CHIP_ID_5709_B2             0x57091020
650eef4f27Robert Mustacchi    #define CHIP_ID_5709_FPGA           0x5709f000
651eef4f27Robert Mustacchi    #define CHIP_ID_5709_IKOS           0x5709e000
652eef4f27Robert Mustacchi
653eef4f27Robert Mustacchi    #define CHIP_BOND_ID(_p)            (((_p)->hw_info.chip_id) & 0xf)
654eef4f27Robert Mustacchi
655eef4f27Robert Mustacchi    /* A serdes chip will have the first bit of the bond id set. */
656eef4f27Robert Mustacchi    #define CHIP_BOND_ID_SERDES_BIT     0x01
657eef4f27Robert Mustacchi
658eef4f27Robert Mustacchi    /* HW config from nvram. */
659eef4f27Robert Mustacchi    u32_t nvm_hw_config;
660eef4f27Robert Mustacchi
661eef4f27Robert Mustacchi    u32_t max_toe_conn;
662eef4f27Robert Mustacchi    u32_t max_iscsi_conn;
663eef4f27Robert Mustacchi    u32_t max_iscsi_pending_tasks;
664eef4f27Robert Mustacchi
665eef4f27Robert Mustacchi    /* Bus info. */
666eef4f27Robert Mustacchi    u8_t bus_mode;
667eef4f27Robert Mustacchi    #define BUS_MODE_PCI                0
668eef4f27Robert Mustacchi    #define BUS_MODE_PCIX               1
669eef4f27Robert Mustacchi    #define BUS_MODE_PCIE               2
670eef4f27Robert Mustacchi
671eef4f27Robert Mustacchi    u8_t bus_width;
672eef4f27Robert Mustacchi    #define BUS_WIDTH_32_BIT            32
673eef4f27Robert Mustacchi    #define BUS_WIDTH_64_BIT            64
674eef4f27Robert Mustacchi
675eef4f27Robert Mustacchi    u16_t bus_speed;
676eef4f27Robert Mustacchi    #define BUS_SPEED_33_MHZ            33
677eef4f27Robert Mustacchi    #define BUS_SPEED_50_MHZ            50
678eef4f27Robert Mustacchi    #define BUS_SPEED_66_MHZ            66
679eef4f27Robert Mustacchi    #define BUS_SPEED_100_MHZ           100
680eef4f27Robert Mustacchi    #define BUS_SPEED_133_MHZ           133
681eef4f27Robert Mustacchi
682eef4f27Robert Mustacchi    /* EPB info.  Only valid for 5708. */
683eef4f27Robert Mustacchi    u8_t pcie_bus_num;
684eef4f27Robert Mustacchi
685eef4f27Robert Mustacchi    u8_t pcie_max_width;
686eef4f27Robert Mustacchi    u8_t pcie_width;
687eef4f27Robert Mustacchi    #define PCIE_WIDTH_1                1
688eef4f27Robert Mustacchi    #define PCIE_WIDTH_2                2
689eef4f27Robert Mustacchi    #define PCIE_WIDTH_4                4
690eef4f27Robert Mustacchi    #define PCIE_WIDTH_8                8
691eef4f27Robert Mustacchi    #define PCIE_WIDTH_16               16
692eef4f27Robert Mustacchi    #define PCIE_WIDTH_32               32
693eef4f27Robert Mustacchi
694eef4f27Robert Mustacchi    u8_t _unused_;
695eef4f27Robert Mustacchi
696eef4f27Robert Mustacchi    u16_t pcie_max_speed;
697eef4f27Robert Mustacchi    u16_t pcie_speed;
698eef4f27Robert Mustacchi    #define PCIE_SPEED_2_5_G            25
699eef4f27Robert Mustacchi    #define PCIE_SPEED_5_G              50
700eef4f27Robert Mustacchi
701eef4f27Robert Mustacchi    /* Flash info. */
702eef4f27Robert Mustacchi    flash_spec_t flash_spec;
703eef4f27Robert Mustacchi} lm_hardware_info_t;
704eef4f27Robert Mustacchi
705eef4f27Robert Mustacchi
706eef4f27Robert Mustacchi
707eef4f27Robert Mustacchi/*******************************************************************************
708eef4f27Robert Mustacchi * Device state variables.
709eef4f27Robert Mustacchi ******************************************************************************/
710eef4f27Robert Mustacchi
711eef4f27Robert Mustacchitypedef struct _phy_mem_block_t
712eef4f27Robert Mustacchi{
713eef4f27Robert Mustacchi    lm_address_t start_phy;
714eef4f27Robert Mustacchi    u8_t *start;
715eef4f27Robert Mustacchi    u32_t size;
716eef4f27Robert Mustacchi} phy_mem_block_t;
717eef4f27Robert Mustacchi
718eef4f27Robert Mustacchi
719eef4f27Robert Mustacchitypedef struct _lm_variables_t
720eef4f27Robert Mustacchi{
721eef4f27Robert Mustacchi#ifdef SOLARIS
722eef4f27Robert Mustacchi	ddi_acc_handle_t dmaRegAccHandle;
723eef4f27Robert Mustacchi#endif
724eef4f27Robert Mustacchi    volatile reg_space_t *regview;
725eef4f27Robert Mustacchi
726eef4f27Robert Mustacchi    volatile status_blk_combined_t *status_virt;
727eef4f27Robert Mustacchi    lm_address_t status_phy;
728eef4f27Robert Mustacchi
729eef4f27Robert Mustacchi    lm_status_t link_status;
730eef4f27Robert Mustacchi    lm_medium_t medium;
731eef4f27Robert Mustacchi    lm_flow_control_t flow_control;
732eef4f27Robert Mustacchi
733eef4f27Robert Mustacchi    /* remote phy status. */
734eef4f27Robert Mustacchi    u8_t rphy_status;
735eef4f27Robert Mustacchi    #define RPHY_STATUS_ACTIVE          0x01
736eef4f27Robert Mustacchi    #define RPHY_STATUS_MODULE_PRESENT  0x02
737eef4f27Robert Mustacchi
738eef4f27Robert Mustacchi    u8_t enable_cu_rate_limiter;
739eef4f27Robert Mustacchi
740eef4f27Robert Mustacchi    u16_t bcm5706s_tx_drv_cur;
741eef4f27Robert Mustacchi
742eef4f27Robert Mustacchi    volatile statistics_block_t *stats_virt;
743eef4f27Robert Mustacchi    lm_address_t stats_phy;
744eef4f27Robert Mustacchi
745eef4f27Robert Mustacchi    u16_t fw_wr_seq;
746eef4f27Robert Mustacchi    u8_t fw_timed_out;
747eef4f27Robert Mustacchi
748eef4f27Robert Mustacchi    /* Serdes autonegotiation fallback.  For a serdes medium,
749eef4f27Robert Mustacchi     * if we cannot get link via autonegotiation, we'll force
750eef4f27Robert Mustacchi     * the speed to get link. */
751eef4f27Robert Mustacchi    u8_t serdes_fallback_select;
752eef4f27Robert Mustacchi    u8_t serdes_fallback_status;
753eef4f27Robert Mustacchi    #define SERDES_FALLBACK_NONE            0
754eef4f27Robert Mustacchi    #define SERDES_FALLBACK_1G              1
755eef4f27Robert Mustacchi    #define SERDES_FALLBACK_2_5G            2
756eef4f27Robert Mustacchi
757eef4f27Robert Mustacchi    /* This flag is set if the cable is attached when there
758eef4f27Robert Mustacchi     * is no link.  The upper module could check this flag to
759eef4f27Robert Mustacchi     * determine if there is a need to wait for link. */
760eef4f27Robert Mustacchi    u8_t cable_is_attached;
761eef4f27Robert Mustacchi
762eef4f27Robert Mustacchi    /* Write sequence for driver pulse. */
763eef4f27Robert Mustacchi    u16_t drv_pulse_wr_seq;
764eef4f27Robert Mustacchi
765eef4f27Robert Mustacchi    /* 5708 pre-emphasis. */
766eef4f27Robert Mustacchi    u32_t serdes_pre_emphasis;
767eef4f27Robert Mustacchi
768eef4f27Robert Mustacchi    u32_t interrupt_mode;
769eef4f27Robert Mustacchi
770eef4f27Robert Mustacchi    u32_t cu_mbuf_cnt; /*5709 only */
771eef4f27Robert Mustacchi
772eef4f27Robert Mustacchi    u32_t hw_filter_ctx_offset;
773eef4f27Robert Mustacchi    /* 5709 backing store context memory. */
774eef4f27Robert Mustacchi    #ifndef MAX_CTX
775eef4f27Robert Mustacchi    #define MAX_CTX                         (16 * 1024)
776eef4f27Robert Mustacchi    #endif
777eef4f27Robert Mustacchi    #define ONE_CTX_SIZE                    0x80
778eef4f27Robert Mustacchi    #define NUM_CTX_MBLKS                   16
779eef4f27Robert Mustacchi    #define CTX_MBLK_SIZE                   (128 * 1024)
780eef4f27Robert Mustacchi    phy_mem_block_t ctx_mem[NUM_CTX_MBLKS];
781eef4f27Robert Mustacchi} lm_variables_t;
782eef4f27Robert Mustacchi
783eef4f27Robert Mustacchi
784eef4f27Robert Mustacchi
785eef4f27Robert Mustacchi/*******************************************************************************
786eef4f27Robert Mustacchi * Transmit info.
787eef4f27Robert Mustacchi ******************************************************************************/
788eef4f27Robert Mustacchi
789eef4f27Robert Mustacchitypedef struct _lm_tx_chain_t
790eef4f27Robert Mustacchi{
791eef4f27Robert Mustacchi    u32_t idx;
792eef4f27Robert Mustacchi    #define TX_CHAIN_IDX0                       0
793eef4f27Robert Mustacchi    #define TX_CHAIN_IDX1                       1
794eef4f27Robert Mustacchi    #define TX_CHAIN_IDX2                       2
795eef4f27Robert Mustacchi    #define TX_CHAIN_IDX3                       3
796eef4f27Robert Mustacchi    #define TX_CHAIN_IDX4                       4
797eef4f27Robert Mustacchi    #define TX_CHAIN_IDX5                       5
798eef4f27Robert Mustacchi    #define TX_CHAIN_IDX6                       6
799eef4f27Robert Mustacchi    #define TX_CHAIN_IDX7                       7
800eef4f27Robert Mustacchi    #define TX_CHAIN_IDX8                       8
801eef4f27Robert Mustacchi    #define TX_CHAIN_IDX9                       9
802eef4f27Robert Mustacchi    #define TX_CHAIN_IDX10                      10
803eef4f27Robert Mustacchi    #define TX_CHAIN_IDX11                      11
804eef4f27Robert Mustacchi
805eef4f27Robert Mustacchi    u8_t  cpu_num;
806eef4f27Robert Mustacchi    u8_t  cpu_num_valid;
807eef4f27Robert Mustacchi    u16_t reserve2;
808eef4f27Robert Mustacchi    /* This is a contiguous memory block of params.l2_tx_bd_page_cnt pages
809eef4f27Robert Mustacchi     * used for L2 tx_bd chain.  The BD chain is arranged as a circular
810eef4f27Robert Mustacchi     * chain where the last BD entry of a page points to the next page,
811eef4f27Robert Mustacchi     * and the last BD entry of the last page points to the first. */
812eef4f27Robert Mustacchi    tx_bd_t *bd_chain_virt;
813eef4f27Robert Mustacchi    lm_address_t bd_chain_phy;
814eef4f27Robert Mustacchi
815eef4f27Robert Mustacchi    u32_t cid_addr;
816eef4f27Robert Mustacchi    u16_t prod_idx;
817eef4f27Robert Mustacchi    u16_t con_idx;
818eef4f27Robert Mustacchi    tx_bd_t *prod_bd;
819eef4f27Robert Mustacchi    u32_t prod_bseq;
820eef4f27Robert Mustacchi    volatile u16_t *hw_con_idx_ptr;
821eef4f27Robert Mustacchi    u16_t bd_left;
822eef4f27Robert Mustacchi
823eef4f27Robert Mustacchi    s_list_t active_descq;
824eef4f27Robert Mustacchi} lm_tx_chain_t;
825eef4f27Robert Mustacchi
826eef4f27Robert Mustacchi
827eef4f27Robert Mustacchitypedef struct _lm_tx_info_t
828eef4f27Robert Mustacchi{
829eef4f27Robert Mustacchi    lm_tx_chain_t chain[MAX_TX_CHAIN];
830eef4f27Robert Mustacchi
831eef4f27Robert Mustacchi    u32_t num_txq;
832eef4f27Robert Mustacchi    u32_t cu_idx;
833eef4f27Robert Mustacchi
834eef4f27Robert Mustacchi    lm_tx_stats_t stats;
835eef4f27Robert Mustacchi} lm_tx_info_t;
836eef4f27Robert Mustacchi
837eef4f27Robert Mustacchi
838eef4f27Robert Mustacchi
839eef4f27Robert Mustacchi/*******************************************************************************
840eef4f27Robert Mustacchi * Receive info.
841eef4f27Robert Mustacchi ******************************************************************************/
842eef4f27Robert Mustacchi
843eef4f27Robert Mustacchitypedef struct _lm_rx_chain_t
844eef4f27Robert Mustacchi{
845eef4f27Robert Mustacchi    u32_t idx;
846eef4f27Robert Mustacchi    #define RX_CHAIN_IDX0                       0
847eef4f27Robert Mustacchi    #define RX_CHAIN_IDX1                       1
848eef4f27Robert Mustacchi    #define RX_CHAIN_IDX2                       2
849eef4f27Robert Mustacchi    #define RX_CHAIN_IDX3                       3
850eef4f27Robert Mustacchi    #define RX_CHAIN_IDX4                       4
851eef4f27Robert Mustacchi    #define RX_CHAIN_IDX5                       5
852eef4f27Robert Mustacchi    #define RX_CHAIN_IDX6                       6
853eef4f27Robert Mustacchi    #define RX_CHAIN_IDX7                       7
854eef4f27Robert Mustacchi    #define RX_CHAIN_IDX8                       8
855eef4f27Robert Mustacchi    #define RX_CHAIN_IDX9                       9
856eef4f27Robert Mustacchi    #define RX_CHAIN_IDX10                      10
857eef4f27Robert Mustacchi    #define RX_CHAIN_IDX11                      11
858eef4f27Robert Mustacchi    #define RX_CHAIN_IDX12                      12
859eef4f27Robert Mustacchi    #define RX_CHAIN_IDX13                      13
860eef4f27Robert Mustacchi    #define RX_CHAIN_IDX14                      14
861eef4f27Robert Mustacchi    #define RX_CHAIN_IDX15                      15
862eef4f27Robert Mustacchi
863eef4f27Robert Mustacchi    u8_t  cpu_num;  /* place holder for cpu affinity(msix) */
864eef4f27Robert Mustacchi    u8_t  cpu_num_valid;
865eef4f27Robert Mustacchi    u16_t max_pkt_len;
866eef4f27Robert Mustacchi    /* This is a contiguous memory block of params.l2_rx_bd_page_cnt pages
867eef4f27Robert Mustacchi     * used for rx completion.  The BD chain is arranged as a circular
868eef4f27Robert Mustacchi     * chain where the last BD entry of a page points to the next page,
869eef4f27Robert Mustacchi     * and the last BD entry of the last page points to the first. */
870eef4f27Robert Mustacchi    rx_bd_t *bd_chain_virt;
871eef4f27Robert Mustacchi    lm_address_t bd_chain_phy;
872eef4f27Robert Mustacchi
873eef4f27Robert Mustacchi    u32_t cid_addr;
874eef4f27Robert Mustacchi    u16_t prod_idx;
875eef4f27Robert Mustacchi    u16_t con_idx;
876eef4f27Robert Mustacchi    u16_t hw_con_idx;
877eef4f27Robert Mustacchi    u16_t _pad;
878eef4f27Robert Mustacchi
879eef4f27Robert Mustacchi    rx_bd_t *prod_bd;
880eef4f27Robert Mustacchi    u32_t prod_bseq;
881eef4f27Robert Mustacchi    volatile u16_t *hw_con_idx_ptr;
882eef4f27Robert Mustacchi    u16_t bd_left;
883eef4f27Robert Mustacchi
884eef4f27Robert Mustacchi    u32_t vmq_lookahead_size;
885eef4f27Robert Mustacchi    s_list_t free_descq; /* legacy mode variable */
886eef4f27Robert Mustacchi    s_list_t active_descq;
887eef4f27Robert Mustacchi} lm_rx_chain_t;
888eef4f27Robert Mustacchi
889eef4f27Robert Mustacchi
890eef4f27Robert Mustacchitypedef struct _lm_rx_info_t
891eef4f27Robert Mustacchi{
892eef4f27Robert Mustacchi    lm_rx_chain_t chain[MAX_RX_CHAIN];
893eef4f27Robert Mustacchi
894eef4f27Robert Mustacchi    u32_t num_rxq;
895eef4f27Robert Mustacchi
896eef4f27Robert Mustacchi    #define RX_FILTER_USER_IDX0         0
897eef4f27Robert Mustacchi    #define RX_FILTER_USER_IDX1         1
898eef4f27Robert Mustacchi    #define RX_FILTER_USER_IDX2         2
899eef4f27Robert Mustacchi    #define RX_FILTER_USER_IDX3         3
900eef4f27Robert Mustacchi    #define MAX_RX_FILTER_USER_CNT      4
901eef4f27Robert Mustacchi    lm_rx_mask_t mask[MAX_RX_FILTER_USER_CNT];
902eef4f27Robert Mustacchi
903eef4f27Robert Mustacchi    lm_rx_stats_t stats;
904eef4f27Robert Mustacchi
905eef4f27Robert Mustacchi    #ifndef EXCLUDE_RSS_SUPPORT
906eef4f27Robert Mustacchi    u32_t rss_tbl_size;
907eef4f27Robert Mustacchi    u8_t *rss_ind_table_virt;
908eef4f27Robert Mustacchi    lm_address_t rss_ind_table_phy;
909eef4f27Robert Mustacchi    #endif
910eef4f27Robert Mustacchi} lm_rx_info_t;
911eef4f27Robert Mustacchi
912eef4f27Robert Mustacchi
913eef4f27Robert Mustacchi
914eef4f27Robert Mustacchi#ifndef EXCLUDE_KQE_SUPPORT
915eef4f27Robert Mustacchi/*******************************************************************************
916eef4f27Robert Mustacchi * Kernel work and completion queue info.
917eef4f27Robert Mustacchi ******************************************************************************/
918eef4f27Robert Mustacchi
919eef4f27Robert Mustacchitypedef struct _lm_kq_info_t
920eef4f27Robert Mustacchi{
921eef4f27Robert Mustacchi    u32_t kwq_cid_addr;
922eef4f27Robert Mustacchi    u32_t kcq_cid_addr;
923eef4f27Robert Mustacchi
924eef4f27Robert Mustacchi    kwqe_t *kwq_virt;
925eef4f27Robert Mustacchi    kwqe_t *kwq_prod_qe;
926eef4f27Robert Mustacchi    kwqe_t *kwq_con_qe;
927eef4f27Robert Mustacchi    kwqe_t *kwq_last_qe;
928eef4f27Robert Mustacchi    u16_t kwq_prod_idx;
929eef4f27Robert Mustacchi    u16_t kwq_con_idx;
930eef4f27Robert Mustacchi    u32_t kwqe_left;
931eef4f27Robert Mustacchi
932eef4f27Robert Mustacchi    kcqe_t *kcq_virt;
933eef4f27Robert Mustacchi    kcqe_t *kcq_con_qe;
934eef4f27Robert Mustacchi    kcqe_t *kcq_last_qe;
935eef4f27Robert Mustacchi    u16_t kcq_con_idx;
936eef4f27Robert Mustacchi    u16_t history_kcq_con_idx;
937eef4f27Robert Mustacchi    kcqe_t *history_kcq_con_qe;
938eef4f27Robert Mustacchi
939eef4f27Robert Mustacchi    void *kwq_pgtbl_virt;
940eef4f27Robert Mustacchi    lm_address_t kwq_pgtbl_phy;
941eef4f27Robert Mustacchi    lm_address_t kwq_phy;
942eef4f27Robert Mustacchi
943eef4f27Robert Mustacchi    void *kcq_pgtbl_virt;
944eef4f27Robert Mustacchi    lm_address_t kcq_pgtbl_phy;
945eef4f27Robert Mustacchi    lm_address_t kcq_phy;
946eef4f27Robert Mustacchi
947eef4f27Robert Mustacchi    /* Statistics. */
948eef4f27Robert Mustacchi    u32_t no_kwq_bd_left;
949eef4f27Robert Mustacchi} lm_kq_info_t;
950eef4f27Robert Mustacchi#endif /* EXCLUDE_KQE_SUPPORT */
951eef4f27Robert Mustacchi
952eef4f27Robert Mustacchi
953eef4f27Robert Mustacchi
954eef4f27Robert Mustacchi/*******************************************************************************
955eef4f27Robert Mustacchi * Include the l4 offload header file.
956eef4f27Robert Mustacchi ******************************************************************************/
957eef4f27Robert Mustacchi
958eef4f27Robert Mustacchi#if INCLUDE_OFLD_SUPPORT
959eef4f27Robert Mustacchi#include "lm_ofld.h"
960eef4f27Robert Mustacchi#else
961eef4f27Robert Mustacchi/* This structure is only used as a placed holder and it is not referenced. */
962eef4f27Robert Mustacchitypedef struct _lm_offload_info_t
963eef4f27Robert Mustacchi{
964eef4f27Robert Mustacchi    void *unused;
965eef4f27Robert Mustacchi} lm_offload_info_t;
966eef4f27Robert Mustacchi#endif
967eef4f27Robert Mustacchi
968eef4f27Robert Mustacchi
969eef4f27Robert Mustacchi
970eef4f27Robert Mustacchi/*******************************************************************************
971eef4f27Robert Mustacchi * Main device block.
972eef4f27Robert Mustacchi ******************************************************************************/
973eef4f27Robert Mustacchi
974eef4f27Robert Mustacchitypedef enum
975eef4f27Robert Mustacchi{
976eef4f27Robert Mustacchi    OS_TYPE_UNKNOWN = 0,
977eef4f27Robert Mustacchi    OS_TYPE_W2K     = 1,
978eef4f27Robert Mustacchi    OS_TYPE_WXP     = 2,
979eef4f27Robert Mustacchi    OS_TYPE_W2K3    = 3,
980eef4f27Robert Mustacchi    OS_TYPE_VISTA   = 4,
981eef4f27Robert Mustacchi    OS_TYPE_W2K8    = 5,
982eef4f27Robert Mustacchi    OS_TYPE_WIN7    = 6,
983eef4f27Robert Mustacchi    OS_TYPE_WIN8    = 7,
984eef4f27Robert Mustacchi} lm_os_type_t;
985eef4f27Robert Mustacchi
986eef4f27Robert Mustacchi
987eef4f27Robert Mustacchitypedef struct _lm_device_t
988eef4f27Robert Mustacchi{
989eef4f27Robert Mustacchi    d_list_entry_t link;        /* Link for the device list. */
990eef4f27Robert Mustacchi
991eef4f27Robert Mustacchi    u32_t ver_num;              /* major:8 minor:8 rel:8 fix:8 */
992eef4f27Robert Mustacchi    u8_t ver_str[32];           /* null terminated version string. */
993eef4f27Robert Mustacchi
994eef4f27Robert Mustacchi    lm_os_type_t os_type;
995eef4f27Robert Mustacchi
996eef4f27Robert Mustacchi    lm_variables_t vars;
997eef4f27Robert Mustacchi    lm_tx_info_t tx_info;
998eef4f27Robert Mustacchi    lm_rx_info_t rx_info;
999eef4f27Robert Mustacchi    #ifndef EXCLUDE_KQE_SUPPORT
1000eef4f27Robert Mustacchi    lm_kq_info_t kq_info;
1001eef4f27Robert Mustacchi    #endif
1002eef4f27Robert Mustacchi    lm_offload_info_t ofld;
1003eef4f27Robert Mustacchi    lm_hardware_info_t hw_info;
1004eef4f27Robert Mustacchi    lm_params_t params;
1005eef4f27Robert Mustacchi    lm_mc_table_t mc_table;
1006eef4f27Robert Mustacchi    lm_nwuf_list_t nwuf_list;
1007eef4f27Robert Mustacchi
1008eef4f27Robert Mustacchi    #ifdef UEFI
1009eef4f27Robert Mustacchi    EFI_PCI_IO_PROTOCOL *PciIoFuncs;
1010eef4f27Robert Mustacchi    #endif
1011eef4f27Robert Mustacchi
1012eef4f27Robert Mustacchi    /* Statistics. */
1013eef4f27Robert Mustacchi    u32_t chip_reset_cnt;
1014eef4f27Robert Mustacchi    u32_t fw_timed_out_cnt;
1015eef4f27Robert Mustacchi} lm_device_t;
1016eef4f27Robert Mustacchi
1017eef4f27Robert Mustacchi
1018eef4f27Robert Mustacchi
1019eef4f27Robert Mustacchi/*******************************************************************************
1020eef4f27Robert Mustacchi * Functions exported between file modules.
1021eef4f27Robert Mustacchi ******************************************************************************/
1022eef4f27Robert Mustacchi
1023eef4f27Robert Mustacchilm_status_t
1024eef4f27Robert Mustacchilm_mwrite(
1025eef4f27Robert Mustacchi    lm_device_t *pdev,
1026eef4f27Robert Mustacchi    u32_t phy_addr,
1027eef4f27Robert Mustacchi    u32_t phy_reg,
1028eef4f27Robert Mustacchi    u32_t val);
1029eef4f27Robert Mustacchi
1030eef4f27Robert Mustacchilm_status_t
1031eef4f27Robert Mustacchilm_mread(
1032eef4f27Robert Mustacchi    lm_device_t *pdev,
1033eef4f27Robert Mustacchi    u32_t phy_addr,
1034eef4f27Robert Mustacchi    u32_t phy_reg,
1035eef4f27Robert Mustacchi    u32_t *ret_val);
1036