1eef4f27bSRobert Mustacchi /* 2eef4f27bSRobert Mustacchi * Copyright 2014-2017 Cavium, Inc. 3eef4f27bSRobert Mustacchi * The contents of this file are subject to the terms of the Common Development 4eef4f27bSRobert Mustacchi * and Distribution License, v.1, (the "License"). 5eef4f27bSRobert Mustacchi * 6eef4f27bSRobert Mustacchi * You may not use this file except in compliance with the License. 7eef4f27bSRobert Mustacchi * 8eef4f27bSRobert Mustacchi * You can obtain a copy of the License at available 9eef4f27bSRobert Mustacchi * at http://opensource.org/licenses/CDDL-1.0 10eef4f27bSRobert Mustacchi * 11eef4f27bSRobert Mustacchi * See the License for the specific language governing permissions and 12eef4f27bSRobert Mustacchi * limitations under the License. 13eef4f27bSRobert Mustacchi */ 14eef4f27bSRobert Mustacchi 15eef4f27bSRobert Mustacchi #ifndef _LM5706_H 16eef4f27bSRobert Mustacchi #define _LM5706_H 17eef4f27bSRobert Mustacchi 18eef4f27bSRobert Mustacchi 19eef4f27bSRobert Mustacchi #include "bcmtype.h" 20eef4f27bSRobert Mustacchi #include "debug.h" 21eef4f27bSRobert Mustacchi #include "5706_reg.h" 22eef4f27bSRobert Mustacchi #include "l2_defs.h" 23eef4f27bSRobert Mustacchi #include "l5_defs.h" 24eef4f27bSRobert Mustacchi #ifndef EXCLUDE_KQE_SUPPORT 25eef4f27bSRobert Mustacchi #include "l4_kqe.h" 26eef4f27bSRobert Mustacchi #endif 27eef4f27bSRobert Mustacchi #ifndef L2_ONLY 28eef4f27bSRobert Mustacchi #include "status_code.h" 29eef4f27bSRobert Mustacchi #endif 30eef4f27bSRobert Mustacchi #include "shmem.h" 31eef4f27bSRobert Mustacchi #include "lm_desc.h" 32eef4f27bSRobert Mustacchi #include "listq.h" 33eef4f27bSRobert Mustacchi #include "lm.h" 34eef4f27bSRobert Mustacchi #include "mm.h" 35eef4f27bSRobert Mustacchi #ifndef L2_ONLY 36eef4f27bSRobert Mustacchi #include "toe_ctx.h" 37eef4f27bSRobert Mustacchi #endif 38eef4f27bSRobert Mustacchi #ifdef UEFI 39eef4f27bSRobert Mustacchi #include "5706_efi.h" 40eef4f27bSRobert Mustacchi #endif 41eef4f27bSRobert Mustacchi #ifdef SOLARIS 42eef4f27bSRobert Mustacchi #include <sys/ddi.h> 43eef4f27bSRobert Mustacchi #include <sys/sunddi.h> 44eef4f27bSRobert Mustacchi #endif 45eef4f27bSRobert Mustacchi 46eef4f27bSRobert Mustacchi #ifdef LINUX /*lediag*/ 47eef4f27bSRobert Mustacchi #include "../../mpd_driver_hybrid/pal2.h" 48eef4f27bSRobert Mustacchi #endif 49eef4f27bSRobert Mustacchi 50eef4f27bSRobert Mustacchi typedef struct fw_version 51eef4f27bSRobert Mustacchi { 52eef4f27bSRobert Mustacchi u8_t name[11]; 53eef4f27bSRobert Mustacchi u8_t namez; 54eef4f27bSRobert Mustacchi u32_t version; 55eef4f27bSRobert Mustacchi } fw_version_t; 56eef4f27bSRobert Mustacchi 57eef4f27bSRobert Mustacchi #ifndef PRIVATE_HSI_HEADER 58eef4f27bSRobert Mustacchi #include "rxp_hsi.h" 59eef4f27bSRobert Mustacchi #include "com_hsi.h" 60eef4f27bSRobert Mustacchi #include "cp_hsi.h" 61eef4f27bSRobert Mustacchi #include "txp_hsi.h" 62eef4f27bSRobert Mustacchi #include "tpat_hsi.h" 63eef4f27bSRobert Mustacchi #else 64eef4f27bSRobert Mustacchi #include "hsi.h" 65eef4f27bSRobert Mustacchi #endif 66eef4f27bSRobert Mustacchi 67eef4f27bSRobert Mustacchi /******************************************************************************* 68eef4f27bSRobert Mustacchi * Constants. 69eef4f27bSRobert Mustacchi ******************************************************************************/ 70eef4f27bSRobert Mustacchi 71eef4f27bSRobert Mustacchi #define MAX_TX_CHAIN 12 72eef4f27bSRobert Mustacchi #define MAX_RX_CHAIN 12 73eef4f27bSRobert Mustacchi #define FIRST_RSS_RXQ 4 74eef4f27bSRobert Mustacchi 75eef4f27bSRobert Mustacchi #ifndef NUM_RX_CHAIN 76eef4f27bSRobert Mustacchi #define NUM_RX_CHAIN 1 77eef4f27bSRobert Mustacchi #endif 78eef4f27bSRobert Mustacchi 79eef4f27bSRobert Mustacchi #ifndef NUM_TX_CHAIN 80eef4f27bSRobert Mustacchi #define NUM_TX_CHAIN 1 81eef4f27bSRobert Mustacchi #endif 82eef4f27bSRobert Mustacchi 83eef4f27bSRobert Mustacchi #if NUM_TX_CHAIN > MAX_TX_CHAIN 84eef4f27bSRobert Mustacchi #error Exceeded maximum number of tx chains. 85eef4f27bSRobert Mustacchi #endif 86eef4f27bSRobert Mustacchi 87eef4f27bSRobert Mustacchi #if NUM_RX_CHAIN > MAX_RX_CHAIN 88eef4f27bSRobert Mustacchi #error Exceeded maximum number of rx chains. 89eef4f27bSRobert Mustacchi #endif 90eef4f27bSRobert Mustacchi 91eef4f27bSRobert Mustacchi /* Number of bits must be 10 to 25. */ 92eef4f27bSRobert Mustacchi #ifndef LM_PAGE_BITS 93eef4f27bSRobert Mustacchi #define LM_PAGE_BITS 12 /* 4K page. */ 94eef4f27bSRobert Mustacchi #endif 95eef4f27bSRobert Mustacchi 96eef4f27bSRobert Mustacchi #define LM_PAGE_SIZE (1 << LM_PAGE_BITS) 97eef4f27bSRobert Mustacchi #define LM_PAGE_MASK (LM_PAGE_SIZE - 1) 98eef4f27bSRobert Mustacchi 99eef4f27bSRobert Mustacchi 100eef4f27bSRobert Mustacchi #ifndef CACHE_LINE_SIZE_MASK 101eef4f27bSRobert Mustacchi #define CACHE_LINE_SIZE_MASK 0x3f 102eef4f27bSRobert Mustacchi #endif 103eef4f27bSRobert Mustacchi 104eef4f27bSRobert Mustacchi 105eef4f27bSRobert Mustacchi /* Number of packets per indication in calls to mm_indicate_rx/tx. */ 106eef4f27bSRobert Mustacchi #ifndef MAX_PACKETS_PER_INDICATION 107eef4f27bSRobert Mustacchi #define MAX_PACKETS_PER_INDICATION 50 108eef4f27bSRobert Mustacchi #endif 109eef4f27bSRobert Mustacchi 110eef4f27bSRobert Mustacchi 111eef4f27bSRobert Mustacchi #ifndef MAX_FRAG_CNT 112eef4f27bSRobert Mustacchi #define MAX_FRAG_CNT 33 113eef4f27bSRobert Mustacchi #endif 114eef4f27bSRobert Mustacchi 115eef4f27bSRobert Mustacchi /* The maximum is actually 0xffff which can be described by a BD. */ 116eef4f27bSRobert Mustacchi #define MAX_FRAGMENT_SIZE 0xf000 117eef4f27bSRobert Mustacchi 118eef4f27bSRobert Mustacchi 119eef4f27bSRobert Mustacchi /* Context size. */ 120eef4f27bSRobert Mustacchi #define CTX_SHIFT 7 121eef4f27bSRobert Mustacchi #define CTX_SIZE (1 << CTX_SHIFT) 122eef4f27bSRobert Mustacchi #define CTX_MASK (CTX_SIZE - 1) 123eef4f27bSRobert Mustacchi #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 124eef4f27bSRobert Mustacchi #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 125eef4f27bSRobert Mustacchi 126eef4f27bSRobert Mustacchi #define PHY_CTX_SHIFT 6 127eef4f27bSRobert Mustacchi #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 128eef4f27bSRobert Mustacchi #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 129eef4f27bSRobert Mustacchi #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 130eef4f27bSRobert Mustacchi #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 131eef4f27bSRobert Mustacchi 132eef4f27bSRobert Mustacchi #define MB_KERNEL_CTX_SHIFT 8 133eef4f27bSRobert Mustacchi #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 134eef4f27bSRobert Mustacchi #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 135eef4f27bSRobert Mustacchi /* #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) */ 136eef4f27bSRobert Mustacchi #define MB_GET_CID_ADDR(_p, _c) lm_mb_get_cid_addr(_p, _c) 137eef4f27bSRobert Mustacchi 138eef4f27bSRobert Mustacchi #define MAX_CID_CNT 0x4000 139eef4f27bSRobert Mustacchi #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 140eef4f27bSRobert Mustacchi #define INVALID_CID_ADDR 0xffffffff 141eef4f27bSRobert Mustacchi 142eef4f27bSRobert Mustacchi 143eef4f27bSRobert Mustacchi /* The size of the GRC window that appears in 32k-64k. */ 144eef4f27bSRobert Mustacchi #define GRC_WINDOW_BASE 0x8000 145eef4f27bSRobert Mustacchi #define GRC_WINDOW_SIZE 0x8000 146eef4f27bSRobert Mustacchi 147eef4f27bSRobert Mustacchi 148eef4f27bSRobert Mustacchi /* L2 rx frame header size. */ 149eef4f27bSRobert Mustacchi #define L2RX_FRAME_HDR_LEN (sizeof(l2_fhdr_t)+2) 150eef4f27bSRobert Mustacchi 151eef4f27bSRobert Mustacchi 152eef4f27bSRobert Mustacchi /* The number of bd's per page including the last bd which is used as 153eef4f27bSRobert Mustacchi * a pointer to the next bd page. */ 154eef4f27bSRobert Mustacchi #define BD_PER_PAGE (LM_PAGE_SIZE/sizeof(tx_bd_t)) 155eef4f27bSRobert Mustacchi 156eef4f27bSRobert Mustacchi /* The number of useable bd's per page. This number does not include 157eef4f27bSRobert Mustacchi * the last bd at the end of the page. */ 158eef4f27bSRobert Mustacchi #define MAX_BD_PER_PAGE ((u32_t) (BD_PER_PAGE-1)) 159eef4f27bSRobert Mustacchi 160eef4f27bSRobert Mustacchi 161eef4f27bSRobert Mustacchi /* Buffer size of the statistics block. */ 162eef4f27bSRobert Mustacchi #define CHIP_STATS_BUFFER_SIZE ((sizeof(statistics_block_t) + \ 163eef4f27bSRobert Mustacchi CACHE_LINE_SIZE_MASK) & \ 164eef4f27bSRobert Mustacchi ~CACHE_LINE_SIZE_MASK) 165eef4f27bSRobert Mustacchi 166eef4f27bSRobert Mustacchi /* Buffer size of the status block. */ 167eef4f27bSRobert Mustacchi #define STATUS_BLOCK_BUFFER_SIZE ((sizeof(status_blk_combined_t) + \ 168eef4f27bSRobert Mustacchi CACHE_LINE_SIZE_MASK) & \ 169eef4f27bSRobert Mustacchi ~CACHE_LINE_SIZE_MASK) 170eef4f27bSRobert Mustacchi 171eef4f27bSRobert Mustacchi 172eef4f27bSRobert Mustacchi #define RSS_INDIRECTION_TABLE_SIZE 0x80 /* Maximum indirection table. */ 173eef4f27bSRobert Mustacchi #define RSS_HASH_KEY_SIZE 0x40 /* Maximum key size. */ 174eef4f27bSRobert Mustacchi #ifndef RSS_LOOKUP_TABLE_WA 175eef4f27bSRobert Mustacchi #define RSS_LOOKUP_TABLE_WA (4*12*256) /* 0 to disable workaround. */ 176eef4f27bSRobert Mustacchi #endif 177eef4f27bSRobert Mustacchi 178eef4f27bSRobert Mustacchi 179eef4f27bSRobert Mustacchi /* Quick context assigments. */ 180eef4f27bSRobert Mustacchi #define L2RX_CID_BASE 0 /* 0-15 */ 181eef4f27bSRobert Mustacchi #define L2TX_CID_BASE 16 /* 16-23 */ 182eef4f27bSRobert Mustacchi #define KWQ_CID 24 183eef4f27bSRobert Mustacchi #define KCQ_CID 25 184eef4f27bSRobert Mustacchi #define HCOPY_CID 26 /* 26-27 */ 185eef4f27bSRobert Mustacchi #define GEN_CHAIN_CID 29 186eef4f27bSRobert Mustacchi 187eef4f27bSRobert Mustacchi /* Xinan definitions. */ 188eef4f27bSRobert Mustacchi #define L2TX_TSS_CID_BASE 32 /* 32-43 */ 189eef4f27bSRobert Mustacchi 190eef4f27bSRobert Mustacchi /* MSIX definitions. */ 191eef4f27bSRobert Mustacchi #define IRQ_MODE_UNKNOWN 0 192eef4f27bSRobert Mustacchi #define IRQ_MODE_LINE_BASED 1 193eef4f27bSRobert Mustacchi #define IRQ_MODE_SIMD 2 194eef4f27bSRobert Mustacchi #define IRQ_MODE_MSI_BASED 3 195eef4f27bSRobert Mustacchi #define IRQ_MODE_MSIX_BASED 4 196eef4f27bSRobert Mustacchi #define MAX_MSIX_HW_VEC 9 197eef4f27bSRobert Mustacchi #define PCI_GRC_WINDOW2_BASE 0xc000 198eef4f27bSRobert Mustacchi #define PCI_GRC_WINDOW3_BASE 0xe000 199eef4f27bSRobert Mustacchi #define MSIX_TABLE_ADDR 0x318000 200eef4f27bSRobert Mustacchi #define MSIX_PBA_ADDR 0x31c000 201eef4f27bSRobert Mustacchi 202eef4f27bSRobert Mustacchi /******************************************************************************* 203eef4f27bSRobert Mustacchi * Macros. 204eef4f27bSRobert Mustacchi ******************************************************************************/ 205eef4f27bSRobert Mustacchi 206eef4f27bSRobert Mustacchi /* These macros have been moved to bcmtype.h. */ 207eef4f27bSRobert Mustacchi #if 0 208eef4f27bSRobert Mustacchi /* Signed subtraction macros with no sign extending. */ 209eef4f27bSRobert Mustacchi #define S64_SUB(_a, _b) ((s64_t) ((s64_t) (_a) - (s64_t) (_b))) 210eef4f27bSRobert Mustacchi #define u64_SUB(_a, _b) ((u64_t) ((s64_t) (_a) - (s64_t) (_b))) 211eef4f27bSRobert Mustacchi #define S32_SUB(_a, _b) ((s32_t) ((s32_t) (_a) - (s32_t) (_b))) 212eef4f27bSRobert Mustacchi #define uS32_SUB(_a, _b) ((u32_t) ((s32_t) (_a) - (s32_t) (_b))) 213eef4f27bSRobert Mustacchi #define S16_SUB(_a, _b) ((s16_t) ((s16_t) (_a) - (s16_t) (_b))) 214eef4f27bSRobert Mustacchi #define u16_SUB(_a, _b) ((u16_t) ((s16_t) (_a) - (s16_t) (_b))) 215eef4f27bSRobert Mustacchi #define PTR_SUB(_a, _b) ((u8_t *) (_a) - (u8_t *) (_b)) 216eef4f27bSRobert Mustacchi #endif 217eef4f27bSRobert Mustacchi 218eef4f27bSRobert Mustacchi #ifndef OFFSETOF 219eef4f27bSRobert Mustacchi #define OFFSETOF(_s, _m) ((u32_t) PTR_SUB(&((_s *) 0)->_m, (u8_t *) 0)) 220eef4f27bSRobert Mustacchi #endif 221eef4f27bSRobert Mustacchi #define WORD_ALIGNED_OFFSETOF(_s, _m) (OFFSETOF(_s, _m) & ~0x03) 222eef4f27bSRobert Mustacchi 223eef4f27bSRobert Mustacchi 224eef4f27bSRobert Mustacchi /* STATIC void 225eef4f27bSRobert Mustacchi * get_attn_chng_bits( 226eef4f27bSRobert Mustacchi * lm_device_t *pdev, 227eef4f27bSRobert Mustacchi * u32_t *asserted_attns, 228eef4f27bSRobert Mustacchi * u32_t *deasserted_attns); */ 229eef4f27bSRobert Mustacchi #define GET_ATTN_CHNG_BITS(_pdev, _asserted_attns_ptr, _deasserted_attns_ptr) \ 230eef4f27bSRobert Mustacchi { \ 231eef4f27bSRobert Mustacchi u32_t attn_chng; \ 232eef4f27bSRobert Mustacchi u32_t attn_bits; \ 233eef4f27bSRobert Mustacchi u32_t attn_ack; \ 234eef4f27bSRobert Mustacchi \ 235eef4f27bSRobert Mustacchi attn_bits = (_pdev)->vars.status_virt->deflt.status_attn_bits; \ 236eef4f27bSRobert Mustacchi attn_ack = (_pdev)->vars.status_virt->deflt.status_attn_bits_ack; \ 237eef4f27bSRobert Mustacchi \ 238eef4f27bSRobert Mustacchi attn_chng = attn_bits ^ attn_ack; \ 239eef4f27bSRobert Mustacchi \ 240eef4f27bSRobert Mustacchi *(_asserted_attns_ptr) = attn_bits & attn_chng; \ 241eef4f27bSRobert Mustacchi *(_deasserted_attns_ptr) = ~attn_bits & attn_chng; \ 242eef4f27bSRobert Mustacchi } 243eef4f27bSRobert Mustacchi 244eef4f27bSRobert Mustacchi 245eef4f27bSRobert Mustacchi 246eef4f27bSRobert Mustacchi /******************************************************************************* 247eef4f27bSRobert Mustacchi * Statistics. 248eef4f27bSRobert Mustacchi ******************************************************************************/ 249eef4f27bSRobert Mustacchi 250eef4f27bSRobert Mustacchi typedef struct _lm_tx_statistics_t 251eef4f27bSRobert Mustacchi { 252eef4f27bSRobert Mustacchi lm_u64_t ipv4_lso_frames; 253eef4f27bSRobert Mustacchi lm_u64_t ipv6_lso_frames; 254*55fea89dSDan Cross lm_u64_t ip_cso_frames; 255*55fea89dSDan Cross lm_u64_t ipv4_tcp_udp_cso_frames; 256*55fea89dSDan Cross lm_u64_t ipv6_tcp_udp_cso_frames; 257eef4f27bSRobert Mustacchi u32_t aborted; 258eef4f27bSRobert Mustacchi u32_t no_bd; 259eef4f27bSRobert Mustacchi u32_t no_desc; 260eef4f27bSRobert Mustacchi u32_t no_coalesce_buf; 261eef4f27bSRobert Mustacchi u32_t no_map_reg; 262eef4f27bSRobert Mustacchi } lm_tx_stats_t; 263eef4f27bSRobert Mustacchi 264eef4f27bSRobert Mustacchi 265eef4f27bSRobert Mustacchi typedef struct _lm_rx_statistics_t 266eef4f27bSRobert Mustacchi { 267eef4f27bSRobert Mustacchi u32_t aborted; 268eef4f27bSRobert Mustacchi u32_t err; 269eef4f27bSRobert Mustacchi u32_t crc; 270eef4f27bSRobert Mustacchi u32_t phy_err; 271eef4f27bSRobert Mustacchi u32_t alignment; 272eef4f27bSRobert Mustacchi u32_t short_packet; 273eef4f27bSRobert Mustacchi u32_t giant_packet; 274eef4f27bSRobert Mustacchi } lm_rx_stats_t; 275eef4f27bSRobert Mustacchi 276eef4f27bSRobert Mustacchi 277eef4f27bSRobert Mustacchi 278eef4f27bSRobert Mustacchi /******************************************************************************* 279eef4f27bSRobert Mustacchi * Packet descriptor. 280eef4f27bSRobert Mustacchi ******************************************************************************/ 281eef4f27bSRobert Mustacchi #if defined(LM_NON_LEGACY_MODE_SUPPORT) 282eef4f27bSRobert Mustacchi typedef struct _lm_packet_t 283eef4f27bSRobert Mustacchi { 284eef4f27bSRobert Mustacchi /* Must be the first entry in this structure. */ 285eef4f27bSRobert Mustacchi s_list_entry_t link; 286eef4f27bSRobert Mustacchi 287eef4f27bSRobert Mustacchi lm_status_t status; 288eef4f27bSRobert Mustacchi 289eef4f27bSRobert Mustacchi union _lm_pkt_info_t 290eef4f27bSRobert Mustacchi { 291eef4f27bSRobert Mustacchi struct _tx_pkt_info_t 292eef4f27bSRobert Mustacchi { 293eef4f27bSRobert Mustacchi lm_pkt_tx_info_t *tx_pkt_info; 294eef4f27bSRobert Mustacchi u16_t next_bd_idx; 295eef4f27bSRobert Mustacchi u16_t bd_used; 296eef4f27bSRobert Mustacchi u8_t span_pages; 297eef4f27bSRobert Mustacchi u8_t pad; 298eef4f27bSRobert Mustacchi u16_t pad1; 299eef4f27bSRobert Mustacchi u32_t size; 300eef4f27bSRobert Mustacchi #if DBG 301eef4f27bSRobert Mustacchi tx_bd_t *dbg_start_bd; 302eef4f27bSRobert Mustacchi u16_t dbg_start_bd_idx; 303eef4f27bSRobert Mustacchi u16_t dbg_frag_cnt; 304eef4f27bSRobert Mustacchi #endif 305eef4f27bSRobert Mustacchi } tx; 306eef4f27bSRobert Mustacchi 307eef4f27bSRobert Mustacchi struct _rx_pkt_info_t 308eef4f27bSRobert Mustacchi { 309eef4f27bSRobert Mustacchi lm_pkt_rx_info_t *rx_pkt_info; 310eef4f27bSRobert Mustacchi u16_t next_bd_idx; 311eef4f27bSRobert Mustacchi u16_t pad; 312eef4f27bSRobert Mustacchi u32_t hash_value; /* RSS hash value. */ 313eef4f27bSRobert Mustacchi #if DBG 314eef4f27bSRobert Mustacchi rx_bd_t *dbg_bd; 315eef4f27bSRobert Mustacchi rx_bd_t *dbg_bd1; /* when vmq header split is enabled */ 316eef4f27bSRobert Mustacchi #endif 317eef4f27bSRobert Mustacchi } rx; 318eef4f27bSRobert Mustacchi } u1; 319eef4f27bSRobert Mustacchi } lm_packet_t; 320eef4f27bSRobert Mustacchi #else 321eef4f27bSRobert Mustacchi typedef struct _lm_packet_t 322eef4f27bSRobert Mustacchi { 323eef4f27bSRobert Mustacchi /* Must be the first entry in this structure. */ 324eef4f27bSRobert Mustacchi s_list_entry_t link; 325eef4f27bSRobert Mustacchi 326eef4f27bSRobert Mustacchi lm_status_t status; 327eef4f27bSRobert Mustacchi u32_t size; 328eef4f27bSRobert Mustacchi 329eef4f27bSRobert Mustacchi union _lm_pkt_info_t 330eef4f27bSRobert Mustacchi { 331eef4f27bSRobert Mustacchi struct _lm_tx_pkt_info_t 332eef4f27bSRobert Mustacchi { 333eef4f27bSRobert Mustacchi lm_tx_flag_t flags; 334eef4f27bSRobert Mustacchi 335eef4f27bSRobert Mustacchi u16_t vlan_tag; 336eef4f27bSRobert Mustacchi u16_t next_bd_idx; 337eef4f27bSRobert Mustacchi u16_t bd_used; 338eef4f27bSRobert Mustacchi u8_t span_pages; 339eef4f27bSRobert Mustacchi u8_t _pad; 340eef4f27bSRobert Mustacchi 341eef4f27bSRobert Mustacchi u16_t lso_mss; 342eef4f27bSRobert Mustacchi u16_t _pad2; 343eef4f27bSRobert Mustacchi 344eef4f27bSRobert Mustacchi u16_t lso_ip_hdr_len; 345eef4f27bSRobert Mustacchi u16_t lso_tcp_hdr_len; 346eef4f27bSRobert Mustacchi 347eef4f27bSRobert Mustacchi #if DBG 348eef4f27bSRobert Mustacchi tx_bd_t *dbg_start_bd; 349eef4f27bSRobert Mustacchi u16_t dbg_start_bd_idx; 350eef4f27bSRobert Mustacchi u16_t dbg_frag_cnt; 351eef4f27bSRobert Mustacchi #endif 352eef4f27bSRobert Mustacchi } tx; 353eef4f27bSRobert Mustacchi 354eef4f27bSRobert Mustacchi struct _lm_rx_pkt_info_t 355eef4f27bSRobert Mustacchi { 356eef4f27bSRobert Mustacchi lm_rx_flag_t flags; 357eef4f27bSRobert Mustacchi 358eef4f27bSRobert Mustacchi u16_t vlan_tag; 359eef4f27bSRobert Mustacchi u16_t ip_cksum; 360eef4f27bSRobert Mustacchi u16_t tcp_or_udp_cksum; 361eef4f27bSRobert Mustacchi u16_t next_bd_idx; 362eef4f27bSRobert Mustacchi 363eef4f27bSRobert Mustacchi u8_t *mem_virt; 364eef4f27bSRobert Mustacchi lm_address_t mem_phy; 365eef4f27bSRobert Mustacchi u32_t buf_size; 366eef4f27bSRobert Mustacchi 367eef4f27bSRobert Mustacchi u32_t hash_value; /* RSS hash value. */ 368eef4f27bSRobert Mustacchi 369eef4f27bSRobert Mustacchi #if DBG 370eef4f27bSRobert Mustacchi rx_bd_t *dbg_bd; 371eef4f27bSRobert Mustacchi #endif 372eef4f27bSRobert Mustacchi } rx; 373eef4f27bSRobert Mustacchi } u1; 374eef4f27bSRobert Mustacchi } lm_packet_t; 375eef4f27bSRobert Mustacchi #endif 376eef4f27bSRobert Mustacchi 377eef4f27bSRobert Mustacchi DECLARE_FRAG_LIST_BUFFER_TYPE(lm_packet_frag_list_t, MAX_FRAG_CNT); 378eef4f27bSRobert Mustacchi 379eef4f27bSRobert Mustacchi 380eef4f27bSRobert Mustacchi 381eef4f27bSRobert Mustacchi /******************************************************************************* 382eef4f27bSRobert Mustacchi * Configurable parameters for the hardware dependent module. 383eef4f27bSRobert Mustacchi ******************************************************************************/ 384eef4f27bSRobert Mustacchi 385eef4f27bSRobert Mustacchi typedef struct _lm_params_t 386eef4f27bSRobert Mustacchi { 387eef4f27bSRobert Mustacchi /* This value is used by the upper module to inform the protocol 388eef4f27bSRobert Mustacchi * of the maximum transmit/receive packet size. Packet size 389eef4f27bSRobert Mustacchi * ranges from 1514-9014 bytes. This value does not include CRC32 and 390eef4f27bSRobert Mustacchi * VLAN tag. */ 391eef4f27bSRobert Mustacchi u32_t mtu; 392eef4f27bSRobert Mustacchi /* Current node address. The MAC address is initially set to the 393eef4f27bSRobert Mustacchi * hardware address. This entry can be modified to allow the driver 394eef4f27bSRobert Mustacchi * to override the default MAC address. The new MAC address takes 395eef4f27bSRobert Mustacchi * effect after a driver reset. */ 396eef4f27bSRobert Mustacchi u8_t mac_addr[8]; 397eef4f27bSRobert Mustacchi 398eef4f27bSRobert Mustacchi u32_t l2_rx_desc_cnt[MAX_RX_CHAIN]; 399eef4f27bSRobert Mustacchi u32_t l2_tx_bd_page_cnt[MAX_TX_CHAIN]; 400eef4f27bSRobert Mustacchi u32_t l2_rx_bd_page_cnt[MAX_RX_CHAIN]; 401eef4f27bSRobert Mustacchi 402eef4f27bSRobert Mustacchi u32_t l4_tx_bd_page_cnt; 403eef4f27bSRobert Mustacchi u32_t limit_l4_tx_bd_cnt; 404eef4f27bSRobert Mustacchi u32_t l4_rx_bd_page_cnt; 405eef4f27bSRobert Mustacchi u32_t limit_l4_rx_bd_cnt; 406eef4f27bSRobert Mustacchi 407eef4f27bSRobert Mustacchi #ifndef EXCLUDE_KQE_SUPPORT 408eef4f27bSRobert Mustacchi u32_t kwq_page_cnt; 409eef4f27bSRobert Mustacchi u32_t kcq_page_cnt; 410eef4f27bSRobert Mustacchi u32_t kcq_history_size; 411eef4f27bSRobert Mustacchi u32_t con_kcqe_history_size; 412eef4f27bSRobert Mustacchi u32_t con_kwqe_history_size; 413eef4f27bSRobert Mustacchi #endif 414eef4f27bSRobert Mustacchi 415eef4f27bSRobert Mustacchi u32_t gen_bd_page_cnt; 416eef4f27bSRobert Mustacchi u32_t max_gen_buf_cnt; 417eef4f27bSRobert Mustacchi u32_t gen_buf_per_alloc; 418eef4f27bSRobert Mustacchi 419eef4f27bSRobert Mustacchi /* This parameter controls whether the buffered data (generic buffers) 420eef4f27bSRobert Mustacchi * should be copied to a staging buffer for indication. */ 421eef4f27bSRobert Mustacchi u32_t copy_buffered_data; 422eef4f27bSRobert Mustacchi 423eef4f27bSRobert Mustacchi /* All the L2 receive buffers start at a cache line size aligned 424eef4f27bSRobert Mustacchi * address. This value determines the location of the L2 frame header 425eef4f27bSRobert Mustacchi * from the beginning of the receive buffer. The value must be a 426eef4f27bSRobert Mustacchi * multiple of 4. */ 427eef4f27bSRobert Mustacchi u32_t rcv_buffer_offset; 428eef4f27bSRobert Mustacchi 429eef4f27bSRobert Mustacchi /* Enable a separate receive queue for receiving packets with 430eef4f27bSRobert Mustacchi * TCP SYN bit set. */ 431eef4f27bSRobert Mustacchi u32_t enable_syn_rcvq; 432eef4f27bSRobert Mustacchi 433eef4f27bSRobert Mustacchi /* Buffer of hcopy descriptor to allocate for a connection. When 434eef4f27bSRobert Mustacchi * this value is 0, hcopy is disabled. */ 435eef4f27bSRobert Mustacchi u32_t hcopy_desc_cnt; 436eef4f27bSRobert Mustacchi 437eef4f27bSRobert Mustacchi /* Number of pages used for the hcopy bd chain. */ 438eef4f27bSRobert Mustacchi u32_t hcopy_bd_page_cnt; 439eef4f27bSRobert Mustacchi 440eef4f27bSRobert Mustacchi /* This parameter is only valid when enable_hcopy is enabled. 441eef4f27bSRobert Mustacchi * When enable_hcopy is enabled, a given connection will not 442eef4f27bSRobert Mustacchi * be able to process subsequent kcqe's after the copy_gen kcqe 443eef4f27bSRobert Mustacchi * until the hcopy request (for the copy_gen) has completed. 444eef4f27bSRobert Mustacchi * The subsequent kcqe's will be copied to a per-connection kcq 445eef4f27bSRobert Mustacchi * buffer. The parameter controls the size of this buffer. */ 446eef4f27bSRobert Mustacchi u32_t buffered_kcqe_cnt; 447eef4f27bSRobert Mustacchi 448eef4f27bSRobert Mustacchi /* Size of the deferred kcqe queue. */ 449eef4f27bSRobert Mustacchi u32_t deferred_kcqe_cnt; 450eef4f27bSRobert Mustacchi 451eef4f27bSRobert Mustacchi /* Various test/debug modes. Any validation failure will cause the 452eef4f27bSRobert Mustacchi * driver to write to misc.swap_diag0 with the corresponding flag. 453eef4f27bSRobert Mustacchi * The intention is to trigger the bus analyzer. */ 454eef4f27bSRobert Mustacchi u32_t test_mode; 455eef4f27bSRobert Mustacchi #define TEST_MODE_DISABLED 0x00 456eef4f27bSRobert Mustacchi #define TEST_MODE_OBSOLETE_0 0x01 /* was TEST_MODE_IKOS */ 457eef4f27bSRobert Mustacchi #define TEST_MODE_OBSOLETE_1 0x02 /* was TEST_MODE_FPGA */ 458eef4f27bSRobert Mustacchi #define TEST_MODE_VERIFY_RX_CRC 0x10 459eef4f27bSRobert Mustacchi #define TEST_MODE_RX_BD_TAGGING 0x20 460eef4f27bSRobert Mustacchi #define TEST_MODE_TX_BD_TAGGING 0x40 461eef4f27bSRobert Mustacchi #define TEST_MODE_LOG_REG_ACCESS 0x80 462eef4f27bSRobert Mustacchi #define TEST_MODE_SAVE_DUMMY_DMA_DATA 0x0100 463eef4f27bSRobert Mustacchi #define TEST_MODE_INIT_GEN_BUF_DATA 0x0200 464eef4f27bSRobert Mustacchi #define TEST_MODE_DRIVER_PULSE_ALWAYS_ALIVE 0x0400 465eef4f27bSRobert Mustacchi #define TEST_MODE_IGNORE_SHMEM_SIGNATURE 0x0800 466eef4f27bSRobert Mustacchi #define TEST_MODE_XDIAG_ISCSI 0x1000 467eef4f27bSRobert Mustacchi 468eef4f27bSRobert Mustacchi lm_offload_t ofld_cap; 469eef4f27bSRobert Mustacchi lm_wake_up_mode_t wol_cap; 470eef4f27bSRobert Mustacchi lm_flow_control_t flow_ctrl_cap; 471eef4f27bSRobert Mustacchi lm_medium_t req_medium; 472eef4f27bSRobert Mustacchi 473eef4f27bSRobert Mustacchi u32_t selective_autoneg; 474eef4f27bSRobert Mustacchi #define SELECTIVE_AUTONEG_OFF 0 475eef4f27bSRobert Mustacchi #define SELECTIVE_AUTONEG_SINGLE_SPEED 1 476eef4f27bSRobert Mustacchi #define SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS 2 477eef4f27bSRobert Mustacchi 478eef4f27bSRobert Mustacchi u32_t wire_speed; /* Not valid on SERDES. */ 479eef4f27bSRobert Mustacchi u32_t phy_addr; /* PHY address. */ 480eef4f27bSRobert Mustacchi 481eef4f27bSRobert Mustacchi /* Ways for the MAC to determine a link change. */ 482eef4f27bSRobert Mustacchi u32_t phy_int_mode; 483eef4f27bSRobert Mustacchi #define PHY_INT_MODE_AUTO 0 484eef4f27bSRobert Mustacchi #define PHY_INT_MODE_MI_INTERRUPT 1 485eef4f27bSRobert Mustacchi #define PHY_INT_MODE_LINK_READY 2 486eef4f27bSRobert Mustacchi #define PHY_INT_MODE_AUTO_POLLING 3 487eef4f27bSRobert Mustacchi 488eef4f27bSRobert Mustacchi /* Ways for the driver to get the link change event. */ 489eef4f27bSRobert Mustacchi u32_t link_chng_mode; 490eef4f27bSRobert Mustacchi #define LINK_CHNG_MODE_AUTO 0 491eef4f27bSRobert Mustacchi #define LINK_CHNG_MODE_USE_STATUS_REG 1 492eef4f27bSRobert Mustacchi #define LINK_CHNG_MODE_USE_STATUS_BLOCK 2 493eef4f27bSRobert Mustacchi 494eef4f27bSRobert Mustacchi /* Coalescing paramers. */ 495eef4f27bSRobert Mustacchi u32_t hc_timer_mode; 496eef4f27bSRobert Mustacchi #define HC_COLLECT_MODE 0x0000 497eef4f27bSRobert Mustacchi #define HC_RX_TIMER_MODE 0x0001 498eef4f27bSRobert Mustacchi #define HC_TX_TIMER_MODE 0x0002 499eef4f27bSRobert Mustacchi #define HC_COM_TIMER_MODE 0x0004 500eef4f27bSRobert Mustacchi #define HC_CMD_TIMER_MODE 0x0008 501eef4f27bSRobert Mustacchi #define HC_TIMER_MODE 0x000f 502eef4f27bSRobert Mustacchi 503eef4f27bSRobert Mustacchi u32_t ind_comp_limit; 504eef4f27bSRobert Mustacchi u32_t tx_quick_cons_trip; 505eef4f27bSRobert Mustacchi u32_t tx_quick_cons_trip_int; 506eef4f27bSRobert Mustacchi u32_t rx_quick_cons_trip; 507eef4f27bSRobert Mustacchi u32_t rx_quick_cons_trip_int; 508eef4f27bSRobert Mustacchi u32_t comp_prod_trip; 509eef4f27bSRobert Mustacchi u32_t comp_prod_trip_int; 510eef4f27bSRobert Mustacchi u32_t tx_ticks; 511eef4f27bSRobert Mustacchi u32_t tx_ticks_int; 512eef4f27bSRobert Mustacchi u32_t com_ticks; 513eef4f27bSRobert Mustacchi u32_t com_ticks_int; 514eef4f27bSRobert Mustacchi u32_t cmd_ticks; 515eef4f27bSRobert Mustacchi u32_t cmd_ticks_int; 516eef4f27bSRobert Mustacchi u32_t rx_ticks; 517eef4f27bSRobert Mustacchi u32_t rx_ticks_int; 518eef4f27bSRobert Mustacchi u32_t stats_ticks; 519eef4f27bSRobert Mustacchi 520eef4f27bSRobert Mustacchi /* Xinan per-processor HC configuration. */ 521eef4f27bSRobert Mustacchi u32_t psb_tx_cons_trip; 522eef4f27bSRobert Mustacchi u32_t psb_tx_ticks; 523eef4f27bSRobert Mustacchi u32_t psb_rx_cons_trip; 524eef4f27bSRobert Mustacchi u32_t psb_rx_ticks; 525eef4f27bSRobert Mustacchi u32_t psb_comp_prod_trip; 526eef4f27bSRobert Mustacchi u32_t psb_com_ticks; 527eef4f27bSRobert Mustacchi u32_t psb_cmd_ticks; 528eef4f27bSRobert Mustacchi u32_t psb_period_ticks; 529eef4f27bSRobert Mustacchi 530eef4f27bSRobert Mustacchi u32_t enable_fir; 531eef4f27bSRobert Mustacchi u32_t num_rchans; 532eef4f27bSRobert Mustacchi u32_t num_wchans; 533eef4f27bSRobert Mustacchi u32_t one_tdma; 534eef4f27bSRobert Mustacchi u32_t ping_pong_dma; 535eef4f27bSRobert Mustacchi u32_t serdes_pre_emphasis; 536eef4f27bSRobert Mustacchi u32_t tmr_reload_value1; 537eef4f27bSRobert Mustacchi 538eef4f27bSRobert Mustacchi u32_t keep_vlan_tag; 539eef4f27bSRobert Mustacchi 540eef4f27bSRobert Mustacchi u32_t enable_remote_phy; 541eef4f27bSRobert Mustacchi u32_t rphy_req_medium; 542eef4f27bSRobert Mustacchi u32_t rphy_flow_ctrl_cap; 543eef4f27bSRobert Mustacchi u32_t rphy_selective_autoneg; 544eef4f27bSRobert Mustacchi u32_t rphy_wire_speed; 545eef4f27bSRobert Mustacchi 546eef4f27bSRobert Mustacchi u32_t bin_mq_mode; 547eef4f27bSRobert Mustacchi u32_t validate_l4_data; 548eef4f27bSRobert Mustacchi 549eef4f27bSRobert Mustacchi /* disable PCIe non-FATAL error reporting */ 550eef4f27bSRobert Mustacchi u32_t disable_pcie_nfr; 551eef4f27bSRobert Mustacchi 552*55fea89dSDan Cross // setting for L2 flow control 0 for disable 1 for enable: 553eef4f27bSRobert Mustacchi u32_t fw_flow_control; 554eef4f27bSRobert Mustacchi // This parameter dictates how long to wait before dropping L2 packet 555eef4f27bSRobert Mustacchi // due to insufficient posted buffers 556eef4f27bSRobert Mustacchi // 0 mean no waiting before dropping, 0xFFFF means maximum wait 557eef4f27bSRobert Mustacchi u32_t fw_flow_control_wait; 558eef4f27bSRobert Mustacchi // 8 lsb represents watermark for flow control, 0 is disable 559eef4f27bSRobert Mustacchi u32_t fw_flow_control_watermarks; 560eef4f27bSRobert Mustacchi 561eef4f27bSRobert Mustacchi u32_t ena_large_grc_timeout; 562eef4f27bSRobert Mustacchi 563eef4f27bSRobert Mustacchi /* 0 causes the driver to report the current flow control configuration. 564eef4f27bSRobert Mustacchi * 1 causes the driver to report the flow control autoneg result. */ 565eef4f27bSRobert Mustacchi u32_t flow_control_reporting_mode; 566eef4f27bSRobert Mustacchi } lm_params_t; 567eef4f27bSRobert Mustacchi 568eef4f27bSRobert Mustacchi 569eef4f27bSRobert Mustacchi 570eef4f27bSRobert Mustacchi /******************************************************************************* 571eef4f27bSRobert Mustacchi * Device NVM info -- The native strapping does not support the new parts, the 572eef4f27bSRobert Mustacchi * software needs to reconfigure for them. 573eef4f27bSRobert Mustacchi ******************************************************************************/ 574eef4f27bSRobert Mustacchi 575eef4f27bSRobert Mustacchi typedef struct _flash_spec_t 576eef4f27bSRobert Mustacchi { 577eef4f27bSRobert Mustacchi u32_t buffered; 578eef4f27bSRobert Mustacchi u32_t shift_bits; 579eef4f27bSRobert Mustacchi u32_t page_size; 580eef4f27bSRobert Mustacchi u32_t addr_mask; 581eef4f27bSRobert Mustacchi u32_t total_size; 582eef4f27bSRobert Mustacchi } flash_spec_t; 583eef4f27bSRobert Mustacchi 584eef4f27bSRobert Mustacchi 585eef4f27bSRobert Mustacchi /******************************************************************************* 586eef4f27bSRobert Mustacchi * Device info. 587eef4f27bSRobert Mustacchi ******************************************************************************/ 588eef4f27bSRobert Mustacchi 589eef4f27bSRobert Mustacchi typedef struct _lm_hardware_info_t 590eef4f27bSRobert Mustacchi { 591eef4f27bSRobert Mustacchi /* PCI info. */ 592eef4f27bSRobert Mustacchi u16_t vid; 593eef4f27bSRobert Mustacchi u16_t did; 594eef4f27bSRobert Mustacchi u16_t ssid; 595eef4f27bSRobert Mustacchi u16_t svid; 596eef4f27bSRobert Mustacchi 597eef4f27bSRobert Mustacchi u8_t irq; 598eef4f27bSRobert Mustacchi u8_t int_pin; 599eef4f27bSRobert Mustacchi u8_t latency_timer; 600eef4f27bSRobert Mustacchi u8_t cache_line_size; 601eef4f27bSRobert Mustacchi u8_t rev_id; 602eef4f27bSRobert Mustacchi u8_t _pad[3]; 603eef4f27bSRobert Mustacchi 604eef4f27bSRobert Mustacchi u8_t mac_id; /* 5709 function 0 or 1. */ 605eef4f27bSRobert Mustacchi u8_t bin_size; /* 5709 bin size in term of context pages. */ 606eef4f27bSRobert Mustacchi u16_t first_l4_l5_bin; /* 5709 first bin. */ 607eef4f27bSRobert Mustacchi 608eef4f27bSRobert Mustacchi lm_address_t mem_base; 609eef4f27bSRobert Mustacchi u32_t bar_size; 610eef4f27bSRobert Mustacchi 611eef4f27bSRobert Mustacchi /* Device info. */ 612eef4f27bSRobert Mustacchi u32_t phy_id; /* (phy_reg2 << 16) | phy_reg3 */ 613eef4f27bSRobert Mustacchi u8_t mac_addr[8]; /* Hardware MAC address. */ 614eef4f27bSRobert Mustacchi u8_t iscsi_mac_addr[8]; /* Hardware MAC address for iSCSI. */ 615eef4f27bSRobert Mustacchi 616eef4f27bSRobert Mustacchi u32_t shmem_base; /* Firmware share memory base addr. */ 617eef4f27bSRobert Mustacchi 618eef4f27bSRobert Mustacchi u32_t chip_id; /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 619eef4f27bSRobert Mustacchi #define CHIP_NUM(_p) (((_p)->hw_info.chip_id) & 0xffff0000) 620eef4f27bSRobert Mustacchi #define CHIP_NUM_5706 0x57060000 621eef4f27bSRobert Mustacchi #define CHIP_NUM_5708 0x57080000 622eef4f27bSRobert Mustacchi #define CHIP_NUM_5709 0x57090000 623eef4f27bSRobert Mustacchi #define CHIP_NUM_57728 0x00000000 624eef4f27bSRobert Mustacchi 625eef4f27bSRobert Mustacchi #define CHIP_REV(_p) (((_p)->hw_info.chip_id) & 0x0000f000) 626eef4f27bSRobert Mustacchi #define CHIP_REV_Ax 0x00000000 627eef4f27bSRobert Mustacchi #define CHIP_REV_Bx 0x00001000 628eef4f27bSRobert Mustacchi #define CHIP_REV_Cx 0x00002000 629eef4f27bSRobert Mustacchi #define CHIP_REV_FPGA 0x0000f000 630eef4f27bSRobert Mustacchi #define CHIP_REV_IKOS 0x0000e000 631eef4f27bSRobert Mustacchi 632eef4f27bSRobert Mustacchi #define CHIP_METAL(_p) (((_p)->hw_info.chip_id) & 0x00000ff0) 633eef4f27bSRobert Mustacchi #define CHIP_BONDING(_p) (((_p)->hw_info.chip_id) & 0x0000000f) 634eef4f27bSRobert Mustacchi 635eef4f27bSRobert Mustacchi #define CHIP_ID(_p) (((_p)->hw_info.chip_id) & 0xfffffff0) 636eef4f27bSRobert Mustacchi #define CHIP_ID_5706_A0 0x57060000 637eef4f27bSRobert Mustacchi #define CHIP_ID_5706_A1 0x57060010 638eef4f27bSRobert Mustacchi #define CHIP_ID_5706_FPGA 0x5706f000 639eef4f27bSRobert Mustacchi #define CHIP_ID_5706_IKOS 0x5706e000 640eef4f27bSRobert Mustacchi #define CHIP_ID_5708_A0 0x57080000 641eef4f27bSRobert Mustacchi #define CHIP_ID_5708_B0 0x57081000 642eef4f27bSRobert Mustacchi #define CHIP_ID_5708_B1 0x57081010 643eef4f27bSRobert Mustacchi #define CHIP_ID_5708_FPGA 0x5708f000 644eef4f27bSRobert Mustacchi #define CHIP_ID_5708_IKOS 0x5708e000 645eef4f27bSRobert Mustacchi #define CHIP_ID_5709_A0 0x57090000 646eef4f27bSRobert Mustacchi #define CHIP_ID_5709_A1 0x57090010 647eef4f27bSRobert Mustacchi #define CHIP_ID_5709_B0 0x57091000 648eef4f27bSRobert Mustacchi #define CHIP_ID_5709_B1 0x57091010 649eef4f27bSRobert Mustacchi #define CHIP_ID_5709_B2 0x57091020 650eef4f27bSRobert Mustacchi #define CHIP_ID_5709_FPGA 0x5709f000 651eef4f27bSRobert Mustacchi #define CHIP_ID_5709_IKOS 0x5709e000 652eef4f27bSRobert Mustacchi 653eef4f27bSRobert Mustacchi #define CHIP_BOND_ID(_p) (((_p)->hw_info.chip_id) & 0xf) 654eef4f27bSRobert Mustacchi 655eef4f27bSRobert Mustacchi /* A serdes chip will have the first bit of the bond id set. */ 656eef4f27bSRobert Mustacchi #define CHIP_BOND_ID_SERDES_BIT 0x01 657eef4f27bSRobert Mustacchi 658eef4f27bSRobert Mustacchi /* HW config from nvram. */ 659eef4f27bSRobert Mustacchi u32_t nvm_hw_config; 660eef4f27bSRobert Mustacchi 661eef4f27bSRobert Mustacchi u32_t max_toe_conn; 662eef4f27bSRobert Mustacchi u32_t max_iscsi_conn; 663eef4f27bSRobert Mustacchi u32_t max_iscsi_pending_tasks; 664eef4f27bSRobert Mustacchi 665eef4f27bSRobert Mustacchi /* Bus info. */ 666eef4f27bSRobert Mustacchi u8_t bus_mode; 667eef4f27bSRobert Mustacchi #define BUS_MODE_PCI 0 668eef4f27bSRobert Mustacchi #define BUS_MODE_PCIX 1 669eef4f27bSRobert Mustacchi #define BUS_MODE_PCIE 2 670eef4f27bSRobert Mustacchi 671eef4f27bSRobert Mustacchi u8_t bus_width; 672eef4f27bSRobert Mustacchi #define BUS_WIDTH_32_BIT 32 673eef4f27bSRobert Mustacchi #define BUS_WIDTH_64_BIT 64 674eef4f27bSRobert Mustacchi 675eef4f27bSRobert Mustacchi u16_t bus_speed; 676eef4f27bSRobert Mustacchi #define BUS_SPEED_33_MHZ 33 677eef4f27bSRobert Mustacchi #define BUS_SPEED_50_MHZ 50 678eef4f27bSRobert Mustacchi #define BUS_SPEED_66_MHZ 66 679eef4f27bSRobert Mustacchi #define BUS_SPEED_100_MHZ 100 680eef4f27bSRobert Mustacchi #define BUS_SPEED_133_MHZ 133 681eef4f27bSRobert Mustacchi 682eef4f27bSRobert Mustacchi /* EPB info. Only valid for 5708. */ 683eef4f27bSRobert Mustacchi u8_t pcie_bus_num; 684eef4f27bSRobert Mustacchi 685eef4f27bSRobert Mustacchi u8_t pcie_max_width; 686eef4f27bSRobert Mustacchi u8_t pcie_width; 687eef4f27bSRobert Mustacchi #define PCIE_WIDTH_1 1 688eef4f27bSRobert Mustacchi #define PCIE_WIDTH_2 2 689eef4f27bSRobert Mustacchi #define PCIE_WIDTH_4 4 690eef4f27bSRobert Mustacchi #define PCIE_WIDTH_8 8 691eef4f27bSRobert Mustacchi #define PCIE_WIDTH_16 16 692eef4f27bSRobert Mustacchi #define PCIE_WIDTH_32 32 693eef4f27bSRobert Mustacchi 694eef4f27bSRobert Mustacchi u8_t _unused_; 695eef4f27bSRobert Mustacchi 696eef4f27bSRobert Mustacchi u16_t pcie_max_speed; 697eef4f27bSRobert Mustacchi u16_t pcie_speed; 698eef4f27bSRobert Mustacchi #define PCIE_SPEED_2_5_G 25 699eef4f27bSRobert Mustacchi #define PCIE_SPEED_5_G 50 700eef4f27bSRobert Mustacchi 701eef4f27bSRobert Mustacchi /* Flash info. */ 702eef4f27bSRobert Mustacchi flash_spec_t flash_spec; 703eef4f27bSRobert Mustacchi } lm_hardware_info_t; 704eef4f27bSRobert Mustacchi 705eef4f27bSRobert Mustacchi 706eef4f27bSRobert Mustacchi 707eef4f27bSRobert Mustacchi /******************************************************************************* 708eef4f27bSRobert Mustacchi * Device state variables. 709eef4f27bSRobert Mustacchi ******************************************************************************/ 710eef4f27bSRobert Mustacchi 711eef4f27bSRobert Mustacchi typedef struct _phy_mem_block_t 712eef4f27bSRobert Mustacchi { 713eef4f27bSRobert Mustacchi lm_address_t start_phy; 714eef4f27bSRobert Mustacchi u8_t *start; 715eef4f27bSRobert Mustacchi u32_t size; 716eef4f27bSRobert Mustacchi } phy_mem_block_t; 717eef4f27bSRobert Mustacchi 718eef4f27bSRobert Mustacchi 719eef4f27bSRobert Mustacchi typedef struct _lm_variables_t 720eef4f27bSRobert Mustacchi { 721eef4f27bSRobert Mustacchi #ifdef SOLARIS 722eef4f27bSRobert Mustacchi ddi_acc_handle_t dmaRegAccHandle; 723eef4f27bSRobert Mustacchi #endif 724eef4f27bSRobert Mustacchi volatile reg_space_t *regview; 725eef4f27bSRobert Mustacchi 726eef4f27bSRobert Mustacchi volatile status_blk_combined_t *status_virt; 727eef4f27bSRobert Mustacchi lm_address_t status_phy; 728eef4f27bSRobert Mustacchi 729eef4f27bSRobert Mustacchi lm_status_t link_status; 730eef4f27bSRobert Mustacchi lm_medium_t medium; 731eef4f27bSRobert Mustacchi lm_flow_control_t flow_control; 732eef4f27bSRobert Mustacchi 733eef4f27bSRobert Mustacchi /* remote phy status. */ 734eef4f27bSRobert Mustacchi u8_t rphy_status; 735eef4f27bSRobert Mustacchi #define RPHY_STATUS_ACTIVE 0x01 736eef4f27bSRobert Mustacchi #define RPHY_STATUS_MODULE_PRESENT 0x02 737eef4f27bSRobert Mustacchi 738eef4f27bSRobert Mustacchi u8_t enable_cu_rate_limiter; 739eef4f27bSRobert Mustacchi 740eef4f27bSRobert Mustacchi u16_t bcm5706s_tx_drv_cur; 741eef4f27bSRobert Mustacchi 742eef4f27bSRobert Mustacchi volatile statistics_block_t *stats_virt; 743eef4f27bSRobert Mustacchi lm_address_t stats_phy; 744eef4f27bSRobert Mustacchi 745eef4f27bSRobert Mustacchi u16_t fw_wr_seq; 746eef4f27bSRobert Mustacchi u8_t fw_timed_out; 747eef4f27bSRobert Mustacchi 748eef4f27bSRobert Mustacchi /* Serdes autonegotiation fallback. For a serdes medium, 749eef4f27bSRobert Mustacchi * if we cannot get link via autonegotiation, we'll force 750eef4f27bSRobert Mustacchi * the speed to get link. */ 751eef4f27bSRobert Mustacchi u8_t serdes_fallback_select; 752eef4f27bSRobert Mustacchi u8_t serdes_fallback_status; 753eef4f27bSRobert Mustacchi #define SERDES_FALLBACK_NONE 0 754eef4f27bSRobert Mustacchi #define SERDES_FALLBACK_1G 1 755eef4f27bSRobert Mustacchi #define SERDES_FALLBACK_2_5G 2 756eef4f27bSRobert Mustacchi 757eef4f27bSRobert Mustacchi /* This flag is set if the cable is attached when there 758eef4f27bSRobert Mustacchi * is no link. The upper module could check this flag to 759eef4f27bSRobert Mustacchi * determine if there is a need to wait for link. */ 760eef4f27bSRobert Mustacchi u8_t cable_is_attached; 761eef4f27bSRobert Mustacchi 762eef4f27bSRobert Mustacchi /* Write sequence for driver pulse. */ 763eef4f27bSRobert Mustacchi u16_t drv_pulse_wr_seq; 764eef4f27bSRobert Mustacchi 765eef4f27bSRobert Mustacchi /* 5708 pre-emphasis. */ 766eef4f27bSRobert Mustacchi u32_t serdes_pre_emphasis; 767eef4f27bSRobert Mustacchi 768eef4f27bSRobert Mustacchi u32_t interrupt_mode; 769*55fea89dSDan Cross 770eef4f27bSRobert Mustacchi u32_t cu_mbuf_cnt; /*5709 only */ 771eef4f27bSRobert Mustacchi 772eef4f27bSRobert Mustacchi u32_t hw_filter_ctx_offset; 773eef4f27bSRobert Mustacchi /* 5709 backing store context memory. */ 774eef4f27bSRobert Mustacchi #ifndef MAX_CTX 775eef4f27bSRobert Mustacchi #define MAX_CTX (16 * 1024) 776eef4f27bSRobert Mustacchi #endif 777eef4f27bSRobert Mustacchi #define ONE_CTX_SIZE 0x80 778eef4f27bSRobert Mustacchi #define NUM_CTX_MBLKS 16 779eef4f27bSRobert Mustacchi #define CTX_MBLK_SIZE (128 * 1024) 780eef4f27bSRobert Mustacchi phy_mem_block_t ctx_mem[NUM_CTX_MBLKS]; 781eef4f27bSRobert Mustacchi } lm_variables_t; 782eef4f27bSRobert Mustacchi 783eef4f27bSRobert Mustacchi 784eef4f27bSRobert Mustacchi 785eef4f27bSRobert Mustacchi /******************************************************************************* 786eef4f27bSRobert Mustacchi * Transmit info. 787eef4f27bSRobert Mustacchi ******************************************************************************/ 788eef4f27bSRobert Mustacchi 789eef4f27bSRobert Mustacchi typedef struct _lm_tx_chain_t 790eef4f27bSRobert Mustacchi { 791eef4f27bSRobert Mustacchi u32_t idx; 792eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX0 0 793eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX1 1 794eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX2 2 795eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX3 3 796eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX4 4 797eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX5 5 798eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX6 6 799eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX7 7 800eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX8 8 801eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX9 9 802eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX10 10 803eef4f27bSRobert Mustacchi #define TX_CHAIN_IDX11 11 804eef4f27bSRobert Mustacchi 805eef4f27bSRobert Mustacchi u8_t cpu_num; 806eef4f27bSRobert Mustacchi u8_t cpu_num_valid; 807eef4f27bSRobert Mustacchi u16_t reserve2; 808eef4f27bSRobert Mustacchi /* This is a contiguous memory block of params.l2_tx_bd_page_cnt pages 809eef4f27bSRobert Mustacchi * used for L2 tx_bd chain. The BD chain is arranged as a circular 810eef4f27bSRobert Mustacchi * chain where the last BD entry of a page points to the next page, 811eef4f27bSRobert Mustacchi * and the last BD entry of the last page points to the first. */ 812eef4f27bSRobert Mustacchi tx_bd_t *bd_chain_virt; 813eef4f27bSRobert Mustacchi lm_address_t bd_chain_phy; 814eef4f27bSRobert Mustacchi 815eef4f27bSRobert Mustacchi u32_t cid_addr; 816eef4f27bSRobert Mustacchi u16_t prod_idx; 817eef4f27bSRobert Mustacchi u16_t con_idx; 818eef4f27bSRobert Mustacchi tx_bd_t *prod_bd; 819eef4f27bSRobert Mustacchi u32_t prod_bseq; 820eef4f27bSRobert Mustacchi volatile u16_t *hw_con_idx_ptr; 821eef4f27bSRobert Mustacchi u16_t bd_left; 822eef4f27bSRobert Mustacchi 823eef4f27bSRobert Mustacchi s_list_t active_descq; 824eef4f27bSRobert Mustacchi } lm_tx_chain_t; 825eef4f27bSRobert Mustacchi 826eef4f27bSRobert Mustacchi 827eef4f27bSRobert Mustacchi typedef struct _lm_tx_info_t 828eef4f27bSRobert Mustacchi { 829eef4f27bSRobert Mustacchi lm_tx_chain_t chain[MAX_TX_CHAIN]; 830eef4f27bSRobert Mustacchi 831eef4f27bSRobert Mustacchi u32_t num_txq; 832eef4f27bSRobert Mustacchi u32_t cu_idx; 833eef4f27bSRobert Mustacchi 834eef4f27bSRobert Mustacchi lm_tx_stats_t stats; 835eef4f27bSRobert Mustacchi } lm_tx_info_t; 836eef4f27bSRobert Mustacchi 837eef4f27bSRobert Mustacchi 838eef4f27bSRobert Mustacchi 839eef4f27bSRobert Mustacchi /******************************************************************************* 840eef4f27bSRobert Mustacchi * Receive info. 841eef4f27bSRobert Mustacchi ******************************************************************************/ 842eef4f27bSRobert Mustacchi 843eef4f27bSRobert Mustacchi typedef struct _lm_rx_chain_t 844eef4f27bSRobert Mustacchi { 845eef4f27bSRobert Mustacchi u32_t idx; 846eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX0 0 847eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX1 1 848eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX2 2 849eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX3 3 850eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX4 4 851eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX5 5 852eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX6 6 853eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX7 7 854eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX8 8 855eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX9 9 856eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX10 10 857eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX11 11 858eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX12 12 859eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX13 13 860eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX14 14 861eef4f27bSRobert Mustacchi #define RX_CHAIN_IDX15 15 862eef4f27bSRobert Mustacchi 863eef4f27bSRobert Mustacchi u8_t cpu_num; /* place holder for cpu affinity(msix) */ 864eef4f27bSRobert Mustacchi u8_t cpu_num_valid; 865eef4f27bSRobert Mustacchi u16_t max_pkt_len; 866eef4f27bSRobert Mustacchi /* This is a contiguous memory block of params.l2_rx_bd_page_cnt pages 867eef4f27bSRobert Mustacchi * used for rx completion. The BD chain is arranged as a circular 868eef4f27bSRobert Mustacchi * chain where the last BD entry of a page points to the next page, 869eef4f27bSRobert Mustacchi * and the last BD entry of the last page points to the first. */ 870eef4f27bSRobert Mustacchi rx_bd_t *bd_chain_virt; 871eef4f27bSRobert Mustacchi lm_address_t bd_chain_phy; 872eef4f27bSRobert Mustacchi 873eef4f27bSRobert Mustacchi u32_t cid_addr; 874eef4f27bSRobert Mustacchi u16_t prod_idx; 875eef4f27bSRobert Mustacchi u16_t con_idx; 876eef4f27bSRobert Mustacchi u16_t hw_con_idx; 877eef4f27bSRobert Mustacchi u16_t _pad; 878eef4f27bSRobert Mustacchi 879eef4f27bSRobert Mustacchi rx_bd_t *prod_bd; 880eef4f27bSRobert Mustacchi u32_t prod_bseq; 881eef4f27bSRobert Mustacchi volatile u16_t *hw_con_idx_ptr; 882eef4f27bSRobert Mustacchi u16_t bd_left; 883eef4f27bSRobert Mustacchi 884eef4f27bSRobert Mustacchi u32_t vmq_lookahead_size; 885eef4f27bSRobert Mustacchi s_list_t free_descq; /* legacy mode variable */ 886eef4f27bSRobert Mustacchi s_list_t active_descq; 887eef4f27bSRobert Mustacchi } lm_rx_chain_t; 888eef4f27bSRobert Mustacchi 889eef4f27bSRobert Mustacchi 890eef4f27bSRobert Mustacchi typedef struct _lm_rx_info_t 891eef4f27bSRobert Mustacchi { 892eef4f27bSRobert Mustacchi lm_rx_chain_t chain[MAX_RX_CHAIN]; 893eef4f27bSRobert Mustacchi 894eef4f27bSRobert Mustacchi u32_t num_rxq; 895eef4f27bSRobert Mustacchi 896eef4f27bSRobert Mustacchi #define RX_FILTER_USER_IDX0 0 897eef4f27bSRobert Mustacchi #define RX_FILTER_USER_IDX1 1 898eef4f27bSRobert Mustacchi #define RX_FILTER_USER_IDX2 2 899eef4f27bSRobert Mustacchi #define RX_FILTER_USER_IDX3 3 900eef4f27bSRobert Mustacchi #define MAX_RX_FILTER_USER_CNT 4 901eef4f27bSRobert Mustacchi lm_rx_mask_t mask[MAX_RX_FILTER_USER_CNT]; 902eef4f27bSRobert Mustacchi 903eef4f27bSRobert Mustacchi lm_rx_stats_t stats; 904eef4f27bSRobert Mustacchi 905eef4f27bSRobert Mustacchi #ifndef EXCLUDE_RSS_SUPPORT 906eef4f27bSRobert Mustacchi u32_t rss_tbl_size; 907eef4f27bSRobert Mustacchi u8_t *rss_ind_table_virt; 908eef4f27bSRobert Mustacchi lm_address_t rss_ind_table_phy; 909eef4f27bSRobert Mustacchi #endif 910eef4f27bSRobert Mustacchi } lm_rx_info_t; 911eef4f27bSRobert Mustacchi 912eef4f27bSRobert Mustacchi 913eef4f27bSRobert Mustacchi 914eef4f27bSRobert Mustacchi #ifndef EXCLUDE_KQE_SUPPORT 915eef4f27bSRobert Mustacchi /******************************************************************************* 916eef4f27bSRobert Mustacchi * Kernel work and completion queue info. 917eef4f27bSRobert Mustacchi ******************************************************************************/ 918eef4f27bSRobert Mustacchi 919eef4f27bSRobert Mustacchi typedef struct _lm_kq_info_t 920eef4f27bSRobert Mustacchi { 921eef4f27bSRobert Mustacchi u32_t kwq_cid_addr; 922eef4f27bSRobert Mustacchi u32_t kcq_cid_addr; 923eef4f27bSRobert Mustacchi 924eef4f27bSRobert Mustacchi kwqe_t *kwq_virt; 925eef4f27bSRobert Mustacchi kwqe_t *kwq_prod_qe; 926eef4f27bSRobert Mustacchi kwqe_t *kwq_con_qe; 927eef4f27bSRobert Mustacchi kwqe_t *kwq_last_qe; 928eef4f27bSRobert Mustacchi u16_t kwq_prod_idx; 929eef4f27bSRobert Mustacchi u16_t kwq_con_idx; 930eef4f27bSRobert Mustacchi u32_t kwqe_left; 931eef4f27bSRobert Mustacchi 932eef4f27bSRobert Mustacchi kcqe_t *kcq_virt; 933eef4f27bSRobert Mustacchi kcqe_t *kcq_con_qe; 934eef4f27bSRobert Mustacchi kcqe_t *kcq_last_qe; 935eef4f27bSRobert Mustacchi u16_t kcq_con_idx; 936eef4f27bSRobert Mustacchi u16_t history_kcq_con_idx; 937eef4f27bSRobert Mustacchi kcqe_t *history_kcq_con_qe; 938eef4f27bSRobert Mustacchi 939eef4f27bSRobert Mustacchi void *kwq_pgtbl_virt; 940eef4f27bSRobert Mustacchi lm_address_t kwq_pgtbl_phy; 941eef4f27bSRobert Mustacchi lm_address_t kwq_phy; 942eef4f27bSRobert Mustacchi 943eef4f27bSRobert Mustacchi void *kcq_pgtbl_virt; 944eef4f27bSRobert Mustacchi lm_address_t kcq_pgtbl_phy; 945eef4f27bSRobert Mustacchi lm_address_t kcq_phy; 946eef4f27bSRobert Mustacchi 947eef4f27bSRobert Mustacchi /* Statistics. */ 948eef4f27bSRobert Mustacchi u32_t no_kwq_bd_left; 949eef4f27bSRobert Mustacchi } lm_kq_info_t; 950eef4f27bSRobert Mustacchi #endif /* EXCLUDE_KQE_SUPPORT */ 951eef4f27bSRobert Mustacchi 952eef4f27bSRobert Mustacchi 953eef4f27bSRobert Mustacchi 954eef4f27bSRobert Mustacchi /******************************************************************************* 955eef4f27bSRobert Mustacchi * Include the l4 offload header file. 956eef4f27bSRobert Mustacchi ******************************************************************************/ 957eef4f27bSRobert Mustacchi 958eef4f27bSRobert Mustacchi #if INCLUDE_OFLD_SUPPORT 959eef4f27bSRobert Mustacchi #include "lm_ofld.h" 960eef4f27bSRobert Mustacchi #else 961eef4f27bSRobert Mustacchi /* This structure is only used as a placed holder and it is not referenced. */ 962eef4f27bSRobert Mustacchi typedef struct _lm_offload_info_t 963eef4f27bSRobert Mustacchi { 964eef4f27bSRobert Mustacchi void *unused; 965eef4f27bSRobert Mustacchi } lm_offload_info_t; 966eef4f27bSRobert Mustacchi #endif 967eef4f27bSRobert Mustacchi 968eef4f27bSRobert Mustacchi 969eef4f27bSRobert Mustacchi 970eef4f27bSRobert Mustacchi /******************************************************************************* 971eef4f27bSRobert Mustacchi * Main device block. 972eef4f27bSRobert Mustacchi ******************************************************************************/ 973eef4f27bSRobert Mustacchi 974eef4f27bSRobert Mustacchi typedef enum 975eef4f27bSRobert Mustacchi { 976eef4f27bSRobert Mustacchi OS_TYPE_UNKNOWN = 0, 977eef4f27bSRobert Mustacchi OS_TYPE_W2K = 1, 978eef4f27bSRobert Mustacchi OS_TYPE_WXP = 2, 979eef4f27bSRobert Mustacchi OS_TYPE_W2K3 = 3, 980eef4f27bSRobert Mustacchi OS_TYPE_VISTA = 4, 981eef4f27bSRobert Mustacchi OS_TYPE_W2K8 = 5, 982eef4f27bSRobert Mustacchi OS_TYPE_WIN7 = 6, 983eef4f27bSRobert Mustacchi OS_TYPE_WIN8 = 7, 984eef4f27bSRobert Mustacchi } lm_os_type_t; 985eef4f27bSRobert Mustacchi 986eef4f27bSRobert Mustacchi 987eef4f27bSRobert Mustacchi typedef struct _lm_device_t 988eef4f27bSRobert Mustacchi { 989eef4f27bSRobert Mustacchi d_list_entry_t link; /* Link for the device list. */ 990eef4f27bSRobert Mustacchi 991eef4f27bSRobert Mustacchi u32_t ver_num; /* major:8 minor:8 rel:8 fix:8 */ 992eef4f27bSRobert Mustacchi u8_t ver_str[32]; /* null terminated version string. */ 993eef4f27bSRobert Mustacchi 994eef4f27bSRobert Mustacchi lm_os_type_t os_type; 995eef4f27bSRobert Mustacchi 996eef4f27bSRobert Mustacchi lm_variables_t vars; 997eef4f27bSRobert Mustacchi lm_tx_info_t tx_info; 998eef4f27bSRobert Mustacchi lm_rx_info_t rx_info; 999eef4f27bSRobert Mustacchi #ifndef EXCLUDE_KQE_SUPPORT 1000eef4f27bSRobert Mustacchi lm_kq_info_t kq_info; 1001eef4f27bSRobert Mustacchi #endif 1002eef4f27bSRobert Mustacchi lm_offload_info_t ofld; 1003eef4f27bSRobert Mustacchi lm_hardware_info_t hw_info; 1004eef4f27bSRobert Mustacchi lm_params_t params; 1005eef4f27bSRobert Mustacchi lm_mc_table_t mc_table; 1006eef4f27bSRobert Mustacchi lm_nwuf_list_t nwuf_list; 1007eef4f27bSRobert Mustacchi 1008eef4f27bSRobert Mustacchi #ifdef UEFI 1009eef4f27bSRobert Mustacchi EFI_PCI_IO_PROTOCOL *PciIoFuncs; 1010eef4f27bSRobert Mustacchi #endif 1011eef4f27bSRobert Mustacchi 1012eef4f27bSRobert Mustacchi /* Statistics. */ 1013eef4f27bSRobert Mustacchi u32_t chip_reset_cnt; 1014eef4f27bSRobert Mustacchi u32_t fw_timed_out_cnt; 1015eef4f27bSRobert Mustacchi } lm_device_t; 1016eef4f27bSRobert Mustacchi 1017eef4f27bSRobert Mustacchi 1018eef4f27bSRobert Mustacchi 1019eef4f27bSRobert Mustacchi /******************************************************************************* 1020eef4f27bSRobert Mustacchi * Functions exported between file modules. 1021eef4f27bSRobert Mustacchi ******************************************************************************/ 1022eef4f27bSRobert Mustacchi 1023eef4f27bSRobert Mustacchi lm_status_t 1024eef4f27bSRobert Mustacchi lm_mwrite( 1025eef4f27bSRobert Mustacchi lm_device_t *pdev, 1026eef4f27bSRobert Mustacchi u32_t phy_addr, 1027eef4f27bSRobert Mustacchi u32_t phy_reg, 1028eef4f27bSRobert Mustacchi u32_t val); 1029eef4f27bSRobert Mustacchi 1030eef4f27bSRobert Mustacchi lm_status_t 1031eef4f27bSRobert Mustacchi lm_mread( 1032eef4f27bSRobert Mustacchi lm_device_t *pdev, 1033eef4f27bSRobert Mustacchi u32_t phy_addr, 1034eef4f27bSRobert Mustacchi u32_t phy_reg, 1035eef4f27bSRobert Mustacchi u32_t *ret_val); 1036eef4f27bSRobert Mustacchi 1037eef4f27bSRobert Mustacchi u32_t 1038eef4f27bSRobert Mustacchi lm_nvram_query( 1039eef4f27bSRobert Mustacchi lm_device_t *pdev, 1040eef4f27bSRobert Mustacchi u8_t reset_flash_block, 1041eef4f27bSRobert Mustacchi u8_t no_hw_mod); 1042eef4f27bSRobert Mustacchi 1043eef4f27bSRobert Mustacchi void 1044eef4f27bSRobert Mustacchi lm_nvram_init( 1045eef4f27bSRobert Mustacchi lm_device_t *pdev, 1046eef4f27bSRobert Mustacchi u8_t reset_flash_block); 1047eef4f27bSRobert Mustacchi 1048eef4f27bSRobert Mustacchi lm_status_t 1049eef4f27bSRobert Mustacchi lm_nvram_read( 1050eef4f27bSRobert Mustacchi lm_device_t *pdev, 1051eef4f27bSRobert Mustacchi u32_t offset, 1052eef4f27bSRobert Mustacchi u32_t *ret_buf, 1053eef4f27bSRobert Mustacchi u32_t buf_size); /* Must be a multiple of 4. */ 1054eef4f27bSRobert Mustacchi 1055eef4f27bSRobert Mustacchi lm_status_t 1056eef4f27bSRobert Mustacchi lm_nvram_write( 1057eef4f27bSRobert Mustacchi lm_device_t *pdev, 1058eef4f27bSRobert Mustacchi u32_t offset, 1059eef4f27bSRobert Mustacchi u32_t *data_buf, 1060eef4f27bSRobert Mustacchi u32_t buf_size); /* Must be a multiple of 4. */ 1061eef4f27bSRobert Mustacchi 1062eef4f27bSRobert Mustacchi void 1063eef4f27bSRobert Mustacchi lm_init_cpus( 1064eef4f27bSRobert Mustacchi lm_device_t *pdev, 1065eef4f27bSRobert Mustacchi u32_t cpu_mask); 1066eef4f27bSRobert Mustacchi #define CPU_RV2P_1 0x00000001 1067eef4f27bSRobert Mustacchi #define CPU_RV2P_2 0x00000002 1068eef4f27bSRobert Mustacchi #define CPU_RXP 0x00000004 1069eef4f27bSRobert Mustacchi #define CPU_TXP 0x00000008 1070eef4f27bSRobert Mustacchi #define CPU_TPAT 0x00000010 1071eef4f27bSRobert Mustacchi #define CPU_COM 0x00000020 1072eef4f27bSRobert Mustacchi #define CPU_CP 0x00000040 1073eef4f27bSRobert Mustacchi #define CPU_ALL 0xffffffff 1074eef4f27bSRobert Mustacchi 1075eef4f27bSRobert Mustacchi void 1076eef4f27bSRobert Mustacchi lm_reg_rd_ind( 1077eef4f27bSRobert Mustacchi lm_device_t *pdev, 1078eef4f27bSRobert Mustacchi u32_t offset, 1079eef4f27bSRobert Mustacchi u32_t *ret); 1080eef4f27bSRobert Mustacchi 1081eef4f27bSRobert Mustacchi void 1082eef4f27bSRobert Mustacchi lm_reg_wr_ind( 1083eef4f27bSRobert Mustacchi lm_device_t *pdev, 1084eef4f27bSRobert Mustacchi u32_t offset, 1085eef4f27bSRobert Mustacchi u32_t val); 1086eef4f27bSRobert Mustacchi 1087eef4f27bSRobert Mustacchi void 1088eef4f27bSRobert Mustacchi lm_ctx_wr( 1089eef4f27bSRobert Mustacchi lm_device_t *pdev, 1090eef4f27bSRobert Mustacchi u32_t cid_addr, 1091eef4f27bSRobert Mustacchi u32_t offset, 1092eef4f27bSRobert Mustacchi u32_t val); 1093eef4f27bSRobert Mustacchi 1094eef4f27bSRobert Mustacchi u32_t 1095eef4f27bSRobert Mustacchi lm_ctx_rd( 1096eef4f27bSRobert Mustacchi lm_device_t *pdev, 1097eef4f27bSRobert Mustacchi u32_t cid_addr, 1098eef4f27bSRobert Mustacchi u32_t offset); 1099eef4f27bSRobert Mustacchi 1100eef4f27bSRobert Mustacchi void 1101eef4f27bSRobert Mustacchi lm_setup_bd_chain_ring( 1102eef4f27bSRobert Mustacchi u8_t *mem_virt, 1103eef4f27bSRobert Mustacchi lm_address_t mem_phy, 1104eef4f27bSRobert Mustacchi u32_t page_cnt); 1105eef4f27bSRobert Mustacchi 1106eef4f27bSRobert Mustacchi lm_status_t 1107eef4f27bSRobert Mustacchi lm_init_remote_phy( 1108eef4f27bSRobert Mustacchi lm_device_t *pdev, 1109eef4f27bSRobert Mustacchi lm_link_settings_t *local_link, 1110eef4f27bSRobert Mustacchi lm_link_settings_t *rphy_link); 1111eef4f27bSRobert Mustacchi 1112eef4f27bSRobert Mustacchi lm_status_t 1113eef4f27bSRobert Mustacchi lm_init_mac_link( 1114eef4f27bSRobert Mustacchi lm_device_t *pdev); 1115eef4f27bSRobert Mustacchi 1116eef4f27bSRobert Mustacchi #ifndef EXCLUDE_KQE_SUPPORT 1117eef4f27bSRobert Mustacchi u32_t 1118eef4f27bSRobert Mustacchi lm_submit_kernel_wqes( 1119eef4f27bSRobert Mustacchi lm_device_t *pdev, 1120eef4f27bSRobert Mustacchi kwqe_t *wqes[], 1121eef4f27bSRobert Mustacchi u32_t num_wqes); 1122eef4f27bSRobert Mustacchi 1123eef4f27bSRobert Mustacchi u32_t 1124eef4f27bSRobert Mustacchi lm_get_kernel_cqes( 1125eef4f27bSRobert Mustacchi lm_device_t *pdev, 1126eef4f27bSRobert Mustacchi kcqe_t *cqe_ptr[], 1127eef4f27bSRobert Mustacchi u32_t ptr_cnt); 1128eef4f27bSRobert Mustacchi 1129eef4f27bSRobert Mustacchi u8_t 1130eef4f27bSRobert Mustacchi lm_ack_kernel_cqes( 1131eef4f27bSRobert Mustacchi lm_device_t *pdev, 1132eef4f27bSRobert Mustacchi u32_t num_cqes); 1133eef4f27bSRobert Mustacchi 1134eef4f27bSRobert Mustacchi void 1135eef4f27bSRobert Mustacchi lm_ack_completed_wqes( 1136eef4f27bSRobert Mustacchi lm_device_t *pdev); 1137eef4f27bSRobert Mustacchi #endif /* EXCLUDE_KQE_SUPPORT */ 1138eef4f27bSRobert Mustacchi 1139eef4f27bSRobert Mustacchi u8_t 1140eef4f27bSRobert Mustacchi fw_reset_sync( 1141eef4f27bSRobert Mustacchi lm_device_t *pdev, 1142eef4f27bSRobert Mustacchi lm_reason_t reason, 1143eef4f27bSRobert Mustacchi u32_t msg_data, 1144eef4f27bSRobert Mustacchi u32_t fw_ack_timeout_us); /* timeout in microseconds. */ 1145eef4f27bSRobert Mustacchi 1146eef4f27bSRobert Mustacchi void 1147eef4f27bSRobert Mustacchi lm_reg_rd_blk( 1148eef4f27bSRobert Mustacchi lm_device_t *pdev, 1149eef4f27bSRobert Mustacchi u32_t reg_offset, 1150eef4f27bSRobert Mustacchi u32_t *buf_ptr, 1151eef4f27bSRobert Mustacchi u32_t u32t_cnt); 1152eef4f27bSRobert Mustacchi 1153eef4f27bSRobert Mustacchi void 1154eef4f27bSRobert Mustacchi lm_reg_rd_blk_ind( 1155eef4f27bSRobert Mustacchi lm_device_t *pdev, 1156eef4f27bSRobert Mustacchi u32_t reg_offset, 1157eef4f27bSRobert Mustacchi u32_t *buf_ptr, 1158eef4f27bSRobert Mustacchi u32_t u32t_cnt); 1159eef4f27bSRobert Mustacchi 1160eef4f27bSRobert Mustacchi void 1161eef4f27bSRobert Mustacchi lm_reg_wr_blk( 1162eef4f27bSRobert Mustacchi lm_device_t *pdev, 1163eef4f27bSRobert Mustacchi u32_t reg_offset, 1164eef4f27bSRobert Mustacchi u32_t *data_ptr, 1165eef4f27bSRobert Mustacchi u32_t u32t_cnt); 1166eef4f27bSRobert Mustacchi 1167eef4f27bSRobert Mustacchi void 1168eef4f27bSRobert Mustacchi lm_reg_wr_blk_ind( 1169eef4f27bSRobert Mustacchi lm_device_t *pdev, 1170eef4f27bSRobert Mustacchi u32_t reg_offset, 1171eef4f27bSRobert Mustacchi u32_t *data_ptr, 1172eef4f27bSRobert Mustacchi u32_t u32t_cnt); 1173eef4f27bSRobert Mustacchi 1174eef4f27bSRobert Mustacchi lm_status_t 1175eef4f27bSRobert Mustacchi lm_submit_fw_cmd( 1176eef4f27bSRobert Mustacchi lm_device_t *pdev, 1177eef4f27bSRobert Mustacchi u32_t drv_msg); 1178eef4f27bSRobert Mustacchi 1179eef4f27bSRobert Mustacchi lm_status_t 1180eef4f27bSRobert Mustacchi lm_last_fw_cmd_status( 1181eef4f27bSRobert Mustacchi lm_device_t *pdev); 1182eef4f27bSRobert Mustacchi 1183eef4f27bSRobert Mustacchi #ifndef EXCLUDE_RSS_SUPPORT 1184eef4f27bSRobert Mustacchi 1185eef4f27bSRobert Mustacchi #if defined(LM_NON_LEGACY_MODE_SUPPORT) 1186eef4f27bSRobert Mustacchi lm_status_t 1187eef4f27bSRobert Mustacchi lm_enable_rss( 1188eef4f27bSRobert Mustacchi lm_device_t *pdev, 1189eef4f27bSRobert Mustacchi lm_rss_hash_t hash_type, 1190eef4f27bSRobert Mustacchi PROCESSOR_NUMBER *indirection_table, 1191eef4f27bSRobert Mustacchi u32_t table_size, 1192eef4f27bSRobert Mustacchi u8_t *hash_key, 1193eef4f27bSRobert Mustacchi u32_t key_size, 1194eef4f27bSRobert Mustacchi u8_t *cpu_tbl, 1195eef4f27bSRobert Mustacchi u8_t *rss_qidx_tbl); 1196eef4f27bSRobert Mustacchi #else 1197eef4f27bSRobert Mustacchi lm_status_t 1198eef4f27bSRobert Mustacchi lm_enable_rss( 1199eef4f27bSRobert Mustacchi lm_device_t *pdev, 1200eef4f27bSRobert Mustacchi lm_rss_hash_t hash_type, 1201eef4f27bSRobert Mustacchi u8_t *indirection_table, 1202eef4f27bSRobert Mustacchi u32_t table_size, 1203eef4f27bSRobert Mustacchi u8_t *hash_key, 1204eef4f27bSRobert Mustacchi u32_t key_size); 1205eef4f27bSRobert Mustacchi #endif 1206eef4f27bSRobert Mustacchi 1207eef4f27bSRobert Mustacchi lm_status_t 1208eef4f27bSRobert Mustacchi lm_disable_rss( 1209eef4f27bSRobert Mustacchi lm_device_t *pdev); 1210eef4f27bSRobert Mustacchi #endif /* EXCLUDE_RSS_SUPPORT */ 1211eef4f27bSRobert Mustacchi 1212eef4f27bSRobert Mustacchi lm_medium_t 1213eef4f27bSRobert Mustacchi lm_get_medium( 1214eef4f27bSRobert Mustacchi lm_device_t *pdev); 1215eef4f27bSRobert Mustacchi 1216eef4f27bSRobert Mustacchi u32_t 1217eef4f27bSRobert Mustacchi lm_mb_get_cid_addr( 1218eef4f27bSRobert Mustacchi lm_device_t *pdev, 1219eef4f27bSRobert Mustacchi u32_t cid); 1220eef4f27bSRobert Mustacchi 1221eef4f27bSRobert Mustacchi u32_t 1222eef4f27bSRobert Mustacchi lm_mb_get_bypass_addr( 1223eef4f27bSRobert Mustacchi lm_device_t *pdev, 1224eef4f27bSRobert Mustacchi u32_t cid); 1225eef4f27bSRobert Mustacchi 1226eef4f27bSRobert Mustacchi void 1227eef4f27bSRobert Mustacchi lm_set_pcie_nfe_report( 1228eef4f27bSRobert Mustacchi lm_device_t *pdev); 1229eef4f27bSRobert Mustacchi 1230*55fea89dSDan Cross void 1231eef4f27bSRobert Mustacchi lm_clear_coalescing_ticks( 1232eef4f27bSRobert Mustacchi lm_device_t *pdev); 1233eef4f27bSRobert Mustacchi 1234eef4f27bSRobert Mustacchi void 1235eef4f27bSRobert Mustacchi lm_post_rx_bd( 1236eef4f27bSRobert Mustacchi lm_device_t *pdev, 1237eef4f27bSRobert Mustacchi lm_rx_chain_t *rxq 1238eef4f27bSRobert Mustacchi ); 1239eef4f27bSRobert Mustacchi 1240*55fea89dSDan Cross void 1241eef4f27bSRobert Mustacchi lm_create_q_group( 1242eef4f27bSRobert Mustacchi lm_device_t *pdev, 1243eef4f27bSRobert Mustacchi u32_t q_group_id, 1244*55fea89dSDan Cross u32_t lookahead_sz 1245eef4f27bSRobert Mustacchi ); 1246eef4f27bSRobert Mustacchi 1247*55fea89dSDan Cross lm_status_t 1248eef4f27bSRobert Mustacchi lm_destroy_q_group( 1249eef4f27bSRobert Mustacchi lm_device_t *pdev, 1250eef4f27bSRobert Mustacchi u32_t q_group_id, 1251eef4f27bSRobert Mustacchi u32_t num_queues 1252eef4f27bSRobert Mustacchi ); 1253eef4f27bSRobert Mustacchi 1254*55fea89dSDan Cross void 1255eef4f27bSRobert Mustacchi lm_update_defq_filter_ctx( 1256eef4f27bSRobert Mustacchi lm_device_t *pdev, 1257eef4f27bSRobert Mustacchi u8_t valid 1258eef4f27bSRobert Mustacchi ); 1259eef4f27bSRobert Mustacchi 1260*55fea89dSDan Cross lm_status_t 1261eef4f27bSRobert Mustacchi lm_chng_q_group_filter( 1262eef4f27bSRobert Mustacchi lm_device_t *pdev, 1263eef4f27bSRobert Mustacchi u32_t q_group_id, 1264eef4f27bSRobert Mustacchi u8_t *dest_mac, 1265eef4f27bSRobert Mustacchi u16_t *vlan_ptr, 1266eef4f27bSRobert Mustacchi u32_t filter_id 1267eef4f27bSRobert Mustacchi ); 1268eef4f27bSRobert Mustacchi 1269eef4f27bSRobert Mustacchi #ifndef EXCLUDE_KQE_SUPPORT 1270eef4f27bSRobert Mustacchi u32_t 1271eef4f27bSRobert Mustacchi lm_service_l2_kcqes( 1272eef4f27bSRobert Mustacchi struct _lm_device_t *pdev, 1273eef4f27bSRobert Mustacchi kcqe_t *cqe_ptr[], 1274eef4f27bSRobert Mustacchi u32_t num_cqes); 1275eef4f27bSRobert Mustacchi #endif 1276eef4f27bSRobert Mustacchi 1277eef4f27bSRobert Mustacchi /******************************************************************************* 1278eef4f27bSRobert Mustacchi * Register access macros. 1279eef4f27bSRobert Mustacchi ******************************************************************************/ 1280eef4f27bSRobert Mustacchi 1281eef4f27bSRobert Mustacchi #if DBG && LOG_REG_ACCESS 1282eef4f27bSRobert Mustacchi 1283eef4f27bSRobert Mustacchi #define LOG_REG_RD(_pdev, _offset, _val) \ 1284eef4f27bSRobert Mustacchi if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ 1285eef4f27bSRobert Mustacchi { \ 1286eef4f27bSRobert Mustacchi DbgMessage2(_pdev, INFORM, "rd 0x%04x = 0x%08x\n", _offset, _val); \ 1287eef4f27bSRobert Mustacchi } 1288eef4f27bSRobert Mustacchi 1289eef4f27bSRobert Mustacchi #define LOG_REG_WR(_pdev, _offset, _val) \ 1290eef4f27bSRobert Mustacchi if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ 1291eef4f27bSRobert Mustacchi { \ 1292eef4f27bSRobert Mustacchi DbgMessage2(_pdev, INFORM, "wr 0x%04x 0x%08x\n", _offset, _val); \ 1293eef4f27bSRobert Mustacchi } 1294eef4f27bSRobert Mustacchi 1295eef4f27bSRobert Mustacchi #define LOG_MBQ_WR32(_pdev, _cid, _offset, _val) \ 1296eef4f27bSRobert Mustacchi if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ 1297eef4f27bSRobert Mustacchi { \ 1298eef4f27bSRobert Mustacchi DbgMessage3(_pdev, INFORM, "mbq_wr32 (0x%04x,0x%02x) = 0x%08x\n", \ 1299eef4f27bSRobert Mustacchi _cid, _offset, _val); \ 1300eef4f27bSRobert Mustacchi } 1301eef4f27bSRobert Mustacchi 1302eef4f27bSRobert Mustacchi #define LOG_MBQ_WR32(_pdev, _cid, _offset, _val) \ 1303eef4f27bSRobert Mustacchi if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ 1304eef4f27bSRobert Mustacchi { \ 1305eef4f27bSRobert Mustacchi DbgMessage3(_pdev, INFORM, "mbq_wr32 (0x%04x,0x%02x) = 0x%08x\n", \ 1306eef4f27bSRobert Mustacchi _cid, _offset, _val); \ 1307eef4f27bSRobert Mustacchi } 1308eef4f27bSRobert Mustacchi 1309eef4f27bSRobert Mustacchi #define LOG_MBQ_WR16(_pdev, _cid, _offset, _val) \ 1310eef4f27bSRobert Mustacchi if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ 1311eef4f27bSRobert Mustacchi { \ 1312eef4f27bSRobert Mustacchi DbgMessage3(_pdev, INFORM, "mbq_wr16 (0x%04x,0x%02x) = 0x%04x\n", \ 1313eef4f27bSRobert Mustacchi _cid, _offset, _val); \ 1314eef4f27bSRobert Mustacchi } 1315eef4f27bSRobert Mustacchi 1316eef4f27bSRobert Mustacchi #define LOG_MBQ_WR8(_pdev, _cid, _offset, _val) \ 1317eef4f27bSRobert Mustacchi if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ 1318eef4f27bSRobert Mustacchi { \ 1319eef4f27bSRobert Mustacchi DbgMessage3(_pdev, INFORM, "mbq_wr8 (0x%04x,0x%02x) = 0x%02x\n", \ 1320eef4f27bSRobert Mustacchi _cid, _offset, _val); \ 1321eef4f27bSRobert Mustacchi } 1322eef4f27bSRobert Mustacchi 1323eef4f27bSRobert Mustacchi #else 1324eef4f27bSRobert Mustacchi #define LOG_REG_RD(_pdev, _offset, _val) 1325eef4f27bSRobert Mustacchi #define LOG_REG_WR(_pdev, _offset, _val) 1326eef4f27bSRobert Mustacchi #define LOG_MBQ_WR32(_pdev, _cid, _offset, _val) 1327eef4f27bSRobert Mustacchi #define LOG_MBQ_WR16(_pdev, _cid, _offset, _val) 1328eef4f27bSRobert Mustacchi #define LOG_MBQ_WR8(_pdev, _cid, _offset, _val) 1329eef4f27bSRobert Mustacchi #endif 1330eef4f27bSRobert Mustacchi 1331eef4f27bSRobert Mustacchi /* Indirect register access. */ 1332eef4f27bSRobert Mustacchi #define REG_RD_IND(_pdev, _offset, _ret) lm_reg_rd_ind(_pdev, _offset, _ret) 1333eef4f27bSRobert Mustacchi #define REG_WR_IND(_pdev, _offset, _val) lm_reg_wr_ind(_pdev, _offset, _val) 1334eef4f27bSRobert Mustacchi 1335eef4f27bSRobert Mustacchi #ifdef CONFIG_PPC64 1336eef4f27bSRobert Mustacchi 1337eef4f27bSRobert Mustacchi /* Register access via register name. */ 1338eef4f27bSRobert Mustacchi #define REG_RD(_pdev, _name, _ret) \ 1339eef4f27bSRobert Mustacchi mm_read_barrier(); \ 1340eef4f27bSRobert Mustacchi *(_ret) = pal_readl(&((_pdev)->vars.regview->_name)); \ 1341eef4f27bSRobert Mustacchi LOG_REG_RD( \ 1342eef4f27bSRobert Mustacchi _pdev, \ 1343eef4f27bSRobert Mustacchi OFFSETOF(reg_space_t, _name), \ 1344eef4f27bSRobert Mustacchi (_pdev)->vars.regview->_name) 1345eef4f27bSRobert Mustacchi 1346eef4f27bSRobert Mustacchi #define REG_WR(_pdev, _name, _val) \ 1347eef4f27bSRobert Mustacchi LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \ 1348eef4f27bSRobert Mustacchi pal_writel((_val), &((_pdev)->vars.regview->_name)); \ 1349eef4f27bSRobert Mustacchi mm_write_barrier() 1350eef4f27bSRobert Mustacchi 1351eef4f27bSRobert Mustacchi 1352eef4f27bSRobert Mustacchi /* Register access via register offset. */ 1353eef4f27bSRobert Mustacchi #define REG_RD_OFFSET(_pdev, _offset, _ret) \ 1354eef4f27bSRobert Mustacchi mm_read_barrier(); \ 1355eef4f27bSRobert Mustacchi *(_ret) = pal_readl((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset))); \ 1356eef4f27bSRobert Mustacchi LOG_REG_RD( \ 1357eef4f27bSRobert Mustacchi _pdev, \ 1358eef4f27bSRobert Mustacchi _offset, \ 1359eef4f27bSRobert Mustacchi *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset)))) 1360eef4f27bSRobert Mustacchi 1361eef4f27bSRobert Mustacchi #define REG_WR_OFFSET(_pdev, _offset, _val) \ 1362eef4f27bSRobert Mustacchi LOG_REG_WR(_pdev, _offset, _val); \ 1363eef4f27bSRobert Mustacchi pal_writel((_val), (volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset))); \ 1364eef4f27bSRobert Mustacchi mm_write_barrier() 1365eef4f27bSRobert Mustacchi 1366eef4f27bSRobert Mustacchi 1367eef4f27bSRobert Mustacchi /* Context write via mailbox queue. */ 1368eef4f27bSRobert Mustacchi #define MBQ_WR32(_pdev, _cid, _offset, _val) \ 1369eef4f27bSRobert Mustacchi LOG_MBQ_WR32(_pdev, _cid, _offset, _val); \ 1370eef4f27bSRobert Mustacchi pal_writel((_val), (volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + \ 1371eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset))); \ 1372eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1373eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1374eef4f27bSRobert Mustacchi { \ 1375eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1376eef4f27bSRobert Mustacchi } 1377eef4f27bSRobert Mustacchi 1378eef4f27bSRobert Mustacchi #define MBQ_WR16(_pdev, _cid, _offset, _val) \ 1379eef4f27bSRobert Mustacchi LOG_MBQ_WR16(_pdev, _cid, _offset, _val); \ 1380eef4f27bSRobert Mustacchi pal_writew((_val), (volatile u16_t *) ((u8_t *) (_pdev)->vars.regview + \ 1381eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset))); \ 1382eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1383eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1384eef4f27bSRobert Mustacchi { \ 1385eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1386eef4f27bSRobert Mustacchi } 1387eef4f27bSRobert Mustacchi 1388eef4f27bSRobert Mustacchi #define MBQ_WR8(_pdev, _cid, _offset, _val) \ 1389eef4f27bSRobert Mustacchi LOG_MBQ_WR8(_pdev, _cid, _offset, _val); \ 1390eef4f27bSRobert Mustacchi pal_writeb((_val), (volatile u8_t *) ((u8_t *) (_pdev)->vars.regview + \ 1391eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset))); \ 1392eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1393eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1394eef4f27bSRobert Mustacchi { \ 1395eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1396eef4f27bSRobert Mustacchi } 1397eef4f27bSRobert Mustacchi 1398eef4f27bSRobert Mustacchi #else /* CONFIG_PPC64 */ 1399eef4f27bSRobert Mustacchi 1400eef4f27bSRobert Mustacchi #ifdef SOLARIS 1401eef4f27bSRobert Mustacchi 1402eef4f27bSRobert Mustacchi /* Register access via register name. */ 1403eef4f27bSRobert Mustacchi #define REG_RD(_pdev, _name, _ret) \ 1404eef4f27bSRobert Mustacchi mm_read_barrier(); \ 1405eef4f27bSRobert Mustacchi if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ 1406eef4f27bSRobert Mustacchi { \ 1407eef4f27bSRobert Mustacchi *(_ret) = \ 1408eef4f27bSRobert Mustacchi ddi_get32((_pdev)->vars.dmaRegAccHandle, \ 1409eef4f27bSRobert Mustacchi (u32_t *)&(_pdev)->vars.regview->_name); \ 1410eef4f27bSRobert Mustacchi } \ 1411eef4f27bSRobert Mustacchi else \ 1412eef4f27bSRobert Mustacchi { \ 1413eef4f27bSRobert Mustacchi *(_ret) = \ 1414eef4f27bSRobert Mustacchi ddi_get16((_pdev)->vars.dmaRegAccHandle, \ 1415eef4f27bSRobert Mustacchi (u16_t *)&(_pdev)->vars.regview->_name); \ 1416eef4f27bSRobert Mustacchi } \ 1417eef4f27bSRobert Mustacchi LOG_REG_RD(_pdev, OFFSETOF(reg_space_t, _name), *(_ret)) 1418eef4f27bSRobert Mustacchi 1419eef4f27bSRobert Mustacchi #define REG_WR(_pdev, _name, _val) \ 1420eef4f27bSRobert Mustacchi LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \ 1421eef4f27bSRobert Mustacchi if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ 1422eef4f27bSRobert Mustacchi { \ 1423eef4f27bSRobert Mustacchi ddi_put32((_pdev)->vars.dmaRegAccHandle, \ 1424eef4f27bSRobert Mustacchi (u32_t *)&(_pdev)->vars.regview->_name, \ 1425eef4f27bSRobert Mustacchi (_val)); \ 1426eef4f27bSRobert Mustacchi } \ 1427eef4f27bSRobert Mustacchi else \ 1428eef4f27bSRobert Mustacchi { \ 1429eef4f27bSRobert Mustacchi ddi_put16((_pdev)->vars.dmaRegAccHandle, \ 1430eef4f27bSRobert Mustacchi (u16_t *)&(_pdev)->vars.regview->_name, \ 1431eef4f27bSRobert Mustacchi (u16_t)(_val)); \ 1432eef4f27bSRobert Mustacchi } \ 1433eef4f27bSRobert Mustacchi mm_write_barrier() 1434eef4f27bSRobert Mustacchi 1435eef4f27bSRobert Mustacchi /* Register access via register offset. */ 1436eef4f27bSRobert Mustacchi #define REG_RD_OFFSET(_pdev, _offset, _ret) \ 1437eef4f27bSRobert Mustacchi mm_read_barrier(); \ 1438eef4f27bSRobert Mustacchi *(_ret) = ddi_get32((_pdev)->vars.dmaRegAccHandle, \ 1439eef4f27bSRobert Mustacchi (u32_t *)((u8_t *)(_pdev)->vars.regview + (_offset))); \ 1440eef4f27bSRobert Mustacchi LOG_REG_RD(_pdev, _offset, *(_ret)) 1441eef4f27bSRobert Mustacchi 1442eef4f27bSRobert Mustacchi #define REG_WR_OFFSET(_pdev, _offset, _val) \ 1443eef4f27bSRobert Mustacchi LOG_REG_WR(_pdev, _offset, _val); \ 1444eef4f27bSRobert Mustacchi ddi_put32((_pdev)->vars.dmaRegAccHandle, \ 1445eef4f27bSRobert Mustacchi (u32_t *)((u8_t *)(_pdev)->vars.regview + (_offset)), \ 1446eef4f27bSRobert Mustacchi (_val)); \ 1447eef4f27bSRobert Mustacchi mm_write_barrier() 1448eef4f27bSRobert Mustacchi 1449eef4f27bSRobert Mustacchi /* Context write via mailbox queue. */ 1450eef4f27bSRobert Mustacchi #define MBQ_WR32(_pdev, _cid, _offset, _val) \ 1451eef4f27bSRobert Mustacchi LOG_MBQ_WR32(_pdev, _cid, _offset, _val); \ 1452eef4f27bSRobert Mustacchi ddi_put32((_pdev)->vars.dmaRegAccHandle, \ 1453eef4f27bSRobert Mustacchi (u32_t *)((u8_t *)(_pdev)->vars.regview + \ 1454eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ 1455eef4f27bSRobert Mustacchi (_val)); \ 1456eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1457eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1458eef4f27bSRobert Mustacchi { \ 1459eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1460eef4f27bSRobert Mustacchi } 1461eef4f27bSRobert Mustacchi 1462eef4f27bSRobert Mustacchi #define MBQ_WR16(_pdev, _cid, _offset, _val) \ 1463eef4f27bSRobert Mustacchi LOG_MBQ_WR16(_pdev, _cid, _offset, _val); \ 1464eef4f27bSRobert Mustacchi ddi_put16((_pdev)->vars.dmaRegAccHandle, \ 1465eef4f27bSRobert Mustacchi (u16_t *)((u8_t *)(_pdev)->vars.regview + \ 1466eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ 1467eef4f27bSRobert Mustacchi (u16_t)(_val)); \ 1468eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1469eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1470eef4f27bSRobert Mustacchi { \ 1471eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1472eef4f27bSRobert Mustacchi } 1473eef4f27bSRobert Mustacchi 1474eef4f27bSRobert Mustacchi #define MBQ_WR8(_pdev, _cid, _offset, _val) \ 1475eef4f27bSRobert Mustacchi LOG_MBQ_WR8(_pdev, _cid, _offset, _val); \ 1476eef4f27bSRobert Mustacchi ddi_put8((_pdev)->vars.dmaRegAccHandle, \ 1477eef4f27bSRobert Mustacchi (u8_t *)((u8_t *)(_pdev)->vars.regview + \ 1478eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ 1479eef4f27bSRobert Mustacchi (u8_t)(_val)); \ 1480eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1481eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1482eef4f27bSRobert Mustacchi { \ 1483eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1484eef4f27bSRobert Mustacchi } 1485eef4f27bSRobert Mustacchi 1486eef4f27bSRobert Mustacchi #elif !defined(UEFI) 1487eef4f27bSRobert Mustacchi 1488eef4f27bSRobert Mustacchi /* Register access via register name. */ 1489eef4f27bSRobert Mustacchi #define REG_RD(_pdev, _name, _ret) \ 1490eef4f27bSRobert Mustacchi mm_read_barrier(); \ 1491eef4f27bSRobert Mustacchi *(_ret) = ((_pdev)->vars.regview->_name); \ 1492eef4f27bSRobert Mustacchi LOG_REG_RD( \ 1493eef4f27bSRobert Mustacchi _pdev, \ 1494eef4f27bSRobert Mustacchi OFFSETOF(reg_space_t, _name), \ 1495eef4f27bSRobert Mustacchi (_pdev)->vars.regview->_name) 1496eef4f27bSRobert Mustacchi 1497eef4f27bSRobert Mustacchi #define REG_WR(_pdev, _name, _val) \ 1498eef4f27bSRobert Mustacchi LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \ 1499eef4f27bSRobert Mustacchi (_pdev)->vars.regview->_name = (_val); \ 1500eef4f27bSRobert Mustacchi mm_write_barrier() 1501eef4f27bSRobert Mustacchi 1502eef4f27bSRobert Mustacchi 1503eef4f27bSRobert Mustacchi /* Register access via register offset. */ 1504eef4f27bSRobert Mustacchi #define REG_RD_OFFSET(_pdev, _offset, _ret) \ 1505eef4f27bSRobert Mustacchi mm_read_barrier(); \ 1506eef4f27bSRobert Mustacchi *(_ret) = *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview+(_offset)));\ 1507eef4f27bSRobert Mustacchi LOG_REG_RD( \ 1508eef4f27bSRobert Mustacchi _pdev, \ 1509eef4f27bSRobert Mustacchi _offset, \ 1510eef4f27bSRobert Mustacchi *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset)))) 1511eef4f27bSRobert Mustacchi 1512eef4f27bSRobert Mustacchi #define REG_WR_OFFSET(_pdev, _offset, _val) \ 1513eef4f27bSRobert Mustacchi LOG_REG_WR(_pdev, _offset, _val); \ 1514eef4f27bSRobert Mustacchi *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview+(_offset)))=(_val); \ 1515eef4f27bSRobert Mustacchi mm_write_barrier() 1516eef4f27bSRobert Mustacchi 1517eef4f27bSRobert Mustacchi 1518eef4f27bSRobert Mustacchi /* Context write via mailbox queue. */ 1519eef4f27bSRobert Mustacchi #define MBQ_WR32(_pdev, _cid, _offset, _val) \ 1520eef4f27bSRobert Mustacchi LOG_MBQ_WR32(_pdev, _cid, _offset, _val); \ 1521eef4f27bSRobert Mustacchi *((volatile u32_t *) (((u8_t *) (_pdev)->vars.regview) + \ 1522eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset))) = (_val); \ 1523eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1524eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1525eef4f27bSRobert Mustacchi { \ 1526eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1527eef4f27bSRobert Mustacchi } 1528eef4f27bSRobert Mustacchi 1529eef4f27bSRobert Mustacchi #define MBQ_WR16(_pdev, _cid, _offset, _val) \ 1530eef4f27bSRobert Mustacchi LOG_MBQ_WR16(_pdev, _cid, _offset, _val); \ 1531eef4f27bSRobert Mustacchi *((volatile u16_t *) (((u8_t *) (_pdev)->vars.regview) + \ 1532eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset))) = (u16_t) (_val); \ 1533eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1534eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1535eef4f27bSRobert Mustacchi { \ 1536eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1537eef4f27bSRobert Mustacchi } 1538eef4f27bSRobert Mustacchi 1539eef4f27bSRobert Mustacchi #define MBQ_WR8(_pdev, _cid, _offset, _val) \ 1540eef4f27bSRobert Mustacchi LOG_MBQ_WR8(_pdev, _cid, _offset, _val); \ 1541eef4f27bSRobert Mustacchi *((volatile u8_t *) (((u8_t *) (_pdev)->vars.regview) + \ 1542eef4f27bSRobert Mustacchi MB_GET_CID_ADDR(_pdev, _cid) + (_offset))) = (u8_t) (_val); \ 1543eef4f27bSRobert Mustacchi mm_write_barrier(); \ 1544eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1545eef4f27bSRobert Mustacchi { \ 1546eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1547eef4f27bSRobert Mustacchi } 1548eef4f27bSRobert Mustacchi 1549eef4f27bSRobert Mustacchi #else //UEFI 1550eef4f27bSRobert Mustacchi 1551eef4f27bSRobert Mustacchi /* Register access via register name. */ 1552eef4f27bSRobert Mustacchi #define REG_RD(_pdev, _name, _ret) \ 1553eef4f27bSRobert Mustacchi if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ 1554eef4f27bSRobert Mustacchi { \ 1555eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Read( \ 1556eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1557eef4f27bSRobert Mustacchi EfiPciIoWidthUint32, \ 1558eef4f27bSRobert Mustacchi 0, \ 1559eef4f27bSRobert Mustacchi (UINT64)(OFFSETOF(reg_space_t, _name)), \ 1560eef4f27bSRobert Mustacchi 1, \ 1561eef4f27bSRobert Mustacchi _ret); \ 1562eef4f27bSRobert Mustacchi } \ 1563eef4f27bSRobert Mustacchi else \ 1564eef4f27bSRobert Mustacchi { \ 1565eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Read( \ 1566eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1567eef4f27bSRobert Mustacchi EfiPciIoWidthUint16, \ 1568eef4f27bSRobert Mustacchi 0, \ 1569eef4f27bSRobert Mustacchi (UINT64)(OFFSETOF(reg_space_t, _name)), \ 1570eef4f27bSRobert Mustacchi 1, \ 1571eef4f27bSRobert Mustacchi _ret); \ 1572eef4f27bSRobert Mustacchi } 1573eef4f27bSRobert Mustacchi 1574eef4f27bSRobert Mustacchi #define REG_WR(_pdev, _name, _val) \ 1575eef4f27bSRobert Mustacchi if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ 1576eef4f27bSRobert Mustacchi { \ 1577eef4f27bSRobert Mustacchi { \ 1578eef4f27bSRobert Mustacchi u32_t w_val; \ 1579eef4f27bSRobert Mustacchi w_val = _val; \ 1580eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Write( \ 1581eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1582eef4f27bSRobert Mustacchi EfiPciIoWidthUint32, \ 1583eef4f27bSRobert Mustacchi 0, \ 1584eef4f27bSRobert Mustacchi (UINT64)(OFFSETOF(reg_space_t, _name)), \ 1585eef4f27bSRobert Mustacchi 1, \ 1586eef4f27bSRobert Mustacchi &w_val); \ 1587eef4f27bSRobert Mustacchi } \ 1588eef4f27bSRobert Mustacchi } \ 1589eef4f27bSRobert Mustacchi else \ 1590eef4f27bSRobert Mustacchi { \ 1591eef4f27bSRobert Mustacchi { \ 1592eef4f27bSRobert Mustacchi u16_t w_val; \ 1593eef4f27bSRobert Mustacchi w_val = (u16_t)_val; \ 1594eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Write( \ 1595eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1596eef4f27bSRobert Mustacchi EfiPciIoWidthUint16, \ 1597eef4f27bSRobert Mustacchi 0, \ 1598eef4f27bSRobert Mustacchi (UINT64)(OFFSETOF(reg_space_t, _name)), \ 1599eef4f27bSRobert Mustacchi 1, \ 1600eef4f27bSRobert Mustacchi &w_val); \ 1601eef4f27bSRobert Mustacchi } \ 1602eef4f27bSRobert Mustacchi } 1603eef4f27bSRobert Mustacchi 1604eef4f27bSRobert Mustacchi 1605eef4f27bSRobert Mustacchi /* Register access via register offset. */ 1606eef4f27bSRobert Mustacchi #define REG_RD_OFFSET(_pdev, _offset, _ret) \ 1607eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Read( \ 1608eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1609eef4f27bSRobert Mustacchi EfiPciIoWidthUint32, \ 1610eef4f27bSRobert Mustacchi 0, \ 1611eef4f27bSRobert Mustacchi (UINT64)(_offset), \ 1612eef4f27bSRobert Mustacchi 1, \ 1613eef4f27bSRobert Mustacchi _ret) 1614eef4f27bSRobert Mustacchi 1615eef4f27bSRobert Mustacchi #define REG_WR_OFFSET(_pdev, _offset, _val) \ 1616eef4f27bSRobert Mustacchi { \ 1617eef4f27bSRobert Mustacchi u32_t w_val; \ 1618eef4f27bSRobert Mustacchi w_val = _val; \ 1619eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Write( \ 1620eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1621eef4f27bSRobert Mustacchi EfiPciIoWidthUint32, \ 1622eef4f27bSRobert Mustacchi 0, \ 1623eef4f27bSRobert Mustacchi (UINT64)(_offset), \ 1624eef4f27bSRobert Mustacchi 1, \ 1625eef4f27bSRobert Mustacchi &w_val); \ 1626eef4f27bSRobert Mustacchi } 1627eef4f27bSRobert Mustacchi 1628eef4f27bSRobert Mustacchi 1629eef4f27bSRobert Mustacchi /* Context write via mailbox queue. */ 1630eef4f27bSRobert Mustacchi #define MBQ_WR32(_pdev, _cid, _offset, _val) \ 1631eef4f27bSRobert Mustacchi { \ 1632eef4f27bSRobert Mustacchi u32_t w_val; \ 1633eef4f27bSRobert Mustacchi w_val = _val; \ 1634eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Write( \ 1635eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1636eef4f27bSRobert Mustacchi EfiPciIoWidthUint32, \ 1637eef4f27bSRobert Mustacchi 0, \ 1638eef4f27bSRobert Mustacchi (UINT64)(MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ 1639eef4f27bSRobert Mustacchi 1, \ 1640eef4f27bSRobert Mustacchi &w_val); \ 1641eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1642eef4f27bSRobert Mustacchi { \ 1643eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1644eef4f27bSRobert Mustacchi } \ 1645eef4f27bSRobert Mustacchi } 1646eef4f27bSRobert Mustacchi 1647eef4f27bSRobert Mustacchi #define MBQ_WR16(_pdev, _cid, _offset, _val) \ 1648eef4f27bSRobert Mustacchi { \ 1649eef4f27bSRobert Mustacchi u16_t w_val; \ 1650eef4f27bSRobert Mustacchi w_val = _val; \ 1651eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Write( \ 1652eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1653eef4f27bSRobert Mustacchi EfiPciIoWidthUint16, \ 1654eef4f27bSRobert Mustacchi 0, \ 1655eef4f27bSRobert Mustacchi (UINT64)(MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ 1656eef4f27bSRobert Mustacchi 1, \ 1657eef4f27bSRobert Mustacchi &w_val); \ 1658eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1659eef4f27bSRobert Mustacchi { \ 1660eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1661eef4f27bSRobert Mustacchi } \ 1662eef4f27bSRobert Mustacchi } 1663eef4f27bSRobert Mustacchi 1664eef4f27bSRobert Mustacchi #define MBQ_WR8(_pdev, _cid, _offset, _val) \ 1665eef4f27bSRobert Mustacchi { \ 1666eef4f27bSRobert Mustacchi u8_t w_val; \ 1667eef4f27bSRobert Mustacchi w_val = _val; \ 1668eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs->Mem.Write( \ 1669eef4f27bSRobert Mustacchi (_pdev)->PciIoFuncs, \ 1670eef4f27bSRobert Mustacchi EfiPciIoWidthUint8, \ 1671eef4f27bSRobert Mustacchi 0, \ 1672eef4f27bSRobert Mustacchi (UINT64)(MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ 1673eef4f27bSRobert Mustacchi 1, \ 1674eef4f27bSRobert Mustacchi &w_val); \ 1675eef4f27bSRobert Mustacchi if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ 1676eef4f27bSRobert Mustacchi { \ 1677eef4f27bSRobert Mustacchi mm_wait(_pdev, 1); \ 1678eef4f27bSRobert Mustacchi } \ 1679eef4f27bSRobert Mustacchi } 1680eef4f27bSRobert Mustacchi 1681eef4f27bSRobert Mustacchi #endif //!UEFI 1682eef4f27bSRobert Mustacchi 1683eef4f27bSRobert Mustacchi #endif /* CONFIG_PPC64 */ 1684eef4f27bSRobert Mustacchi 1685eef4f27bSRobert Mustacchi /* Indirect context access. Unlike the MBQ_WR, these macros will not 1686eef4f27bSRobert Mustacchi * trigger a chip event. */ 1687eef4f27bSRobert Mustacchi #define CTX_WR(_pdev, _cid_addr, _offset, _val) \ 1688eef4f27bSRobert Mustacchi lm_ctx_wr(_pdev, _cid_addr, _offset, _val) 1689eef4f27bSRobert Mustacchi 1690eef4f27bSRobert Mustacchi #define CTX_RD(_pdev, _cid_addr, _offset) \ 1691eef4f27bSRobert Mustacchi lm_ctx_rd(_pdev, _cid_addr, _offset) 1692eef4f27bSRobert Mustacchi 1693eef4f27bSRobert Mustacchi 1694eef4f27bSRobert Mustacchi /* Away to trigger the bus analyzer. */ 1695eef4f27bSRobert Mustacchi #define TRIGGER(_pdev, _val) REG_WR(_pdev, misc.misc_id, _val) 1696eef4f27bSRobert Mustacchi 1697eef4f27bSRobert Mustacchi 1698eef4f27bSRobert Mustacchi 1699eef4f27bSRobert Mustacchi #endif /* _LM5706_H */ 1700eef4f27bSRobert Mustacchi 1701