1/*
2 * Copyright 2014-2017 Cavium, Inc.
3 * The contents of this file are subject to the terms of the Common Development
4 * and Distribution License, v.1,  (the "License").
5 *
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the License at available
9 * at http://opensource.org/licenses/CDDL-1.0
10 *
11 * See the License for the specific language governing permissions and
12 * limitations under the License.
13 */
14
15#ifndef _TXP_HSI_H
16#define _TXP_HSI_H
17
18// Offset of xxx_hsi in 32 bit words from beginning of scratchpad
19#define TXP_HSI_OFFSET 0x4
20
21typedef struct _txp_hsi_t {
22    fw_version_t version;
23    u32_t cu_rate_limiter_enable;
24    u32_t min_rto_tick;
25    u32_t max_rto_tick;
26    u32_t txp_os_flag;
27        #define OS_LH      (1<<0)
28    u32_t invalid_ctx_cnt;               // unknown context type entries
29    u32_t cmpl_cnt;            // count of tx completion
30    u32_t non_zero_slot_cnt;
31    u32_t txp_cid_last;
32    u32_t txp_oubits;
33    u32_t txpq_protocol_flags;
34    u32_t txp_append_context;
35    u32_t txp_overide_catchup;
36    u32_t txp_comxq_seq;
37    u32_t tsch_reset;
38    u32_t iscsi_ctx_num_tasks;          // size of task array in iSCSI context
39    u32_t iscsi_ctx_num_ccells;         // size of command queue in iSCSI context
40    u32_t txp_tdbcThrhld;
41    u32_t num_retx_flushes;             // number of retransmit flush
42    u64_t volatile idle_count;
43    u64_t volatile idle_tdma;
44    u64_t volatile idle_ctx_lock;
45    u64_t volatile idle_hdrq;
46    u32_t txp_coalsce_cnt;
47    u32_t iscsi_teton_task_offset;      // Teton only: offset of the task array
48    u32_t iscsi_teton_l5_offset;        // Teton only: offset of L5 section
49    u32_t neg_slot_cnt;
50    u32_t sws_prevention_ticks;  // sws (silly window syndrome) prevention timer (in Timer1 tick resolution)
51    u32_t tx_after_fin_cnt;      // number of tx occurs after FIN
52    u32_t mtu_size;
53    u32_t bd_validation;
54} txp_hsi_t;
55
56// This the default cache line parameter that used by tcp nagle alogrithm
57#define DEFAULT_TDBCTRHLD           29    /* 29 cached line free */
58#define NAGLE_TDBCTRHLD             22    /* 22 cached line free */
59
60// This macro can be used for little or big endian 32-bit system
61#define TXP_HSI_OFFSETOFF(m)  (OFFSETOF(txp_hsi_t,m) + 0x10)
62#define TXP_HSI_SIZEOF(m)     (sizeof (((txp_hsi_t *)0)->m))
63
64// Calling the following macro will actually get optimized during compile
65// time. Its sole purpose is to ensure HSI variables cannot be modified/moved
66// unnoticed   scratch[8192]  0x60000  (RW/Reset: undefined)
67#define TEST_TXP_HSI(){                                                    \
68if (0){                                                                    \
69 1/(TXP_HSI_OFFSETOFF(version)                   == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x000) &&      \
70    TXP_HSI_OFFSETOFF(cu_rate_limiter_enable)    == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x010) &&      \
71    TXP_HSI_OFFSETOFF(min_rto_tick)              == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x014) &&      \
72    TXP_HSI_OFFSETOFF(max_rto_tick)              == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x018) &&      \
73    TXP_HSI_OFFSETOFF(txp_os_flag)               == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x01c) &&      \
74    TXP_HSI_OFFSETOFF(invalid_ctx_cnt)           == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x020) &&      \
75    TXP_HSI_OFFSETOFF(cmpl_cnt)                  == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x024) &&      \
76    TXP_HSI_OFFSETOFF(non_zero_slot_cnt)         == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x028) &&      \
77    TXP_HSI_OFFSETOFF(txp_cid_last)              == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x02c) &&      \
78    TXP_HSI_OFFSETOFF(txp_oubits)                == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x030) &&      \
79    TXP_HSI_OFFSETOFF(txpq_protocol_flags)       == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x034) &&      \
80    TXP_HSI_OFFSETOFF(txp_append_context)        == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x038) &&      \
81    TXP_HSI_OFFSETOFF(txp_overide_catchup)       == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x03c) &&      \
82    TXP_HSI_OFFSETOFF(txp_comxq_seq)             == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x040) &&      \
83    TXP_HSI_OFFSETOFF(tsch_reset)                == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x044) &&      \
84    TXP_HSI_OFFSETOFF(iscsi_ctx_num_tasks)       == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x048) &&      \
85    TXP_HSI_OFFSETOFF(iscsi_ctx_num_ccells)      == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x04c) &&      \
86    TXP_HSI_OFFSETOFF(txp_tdbcThrhld)            == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x050) &&      \
87    TXP_HSI_OFFSETOFF(num_retx_flushes)          == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x054) &&      \
88    TXP_HSI_OFFSETOFF(idle_count)                == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x058) &&      \
89    TXP_HSI_OFFSETOFF(idle_tdma)                 == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x060) &&      \
90    TXP_HSI_OFFSETOFF(idle_ctx_lock)             == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x068) &&      \
91    TXP_HSI_OFFSETOFF(idle_hdrq)                 == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x070) &&      \
92    TXP_HSI_OFFSETOFF(txp_coalsce_cnt)           == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x078) &&      \
93    TXP_HSI_OFFSETOFF(iscsi_teton_task_offset)   == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x07c) &&      \
94    TXP_HSI_OFFSETOFF(iscsi_teton_l5_offset)     == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x080) &&      \
95    TXP_HSI_OFFSETOFF(neg_slot_cnt)              == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x084) &&      \
96    TXP_HSI_OFFSETOFF(sws_prevention_ticks)      == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x088) &&      \
97    TXP_HSI_OFFSETOFF(tx_after_fin_cnt)          == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x08c) &&      \
98    TXP_HSI_OFFSETOFF(mtu_size)                  == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x090) &&      \
99    TXP_HSI_OFFSETOFF(bd_validation)             == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x094) &&      \
100    TXP_HSI_OFFSETOFF(bd_validation)+TXP_HSI_SIZEOF(bd_validation) == (TXP_HSI_OFFSET * sizeof(u32_t) + sizeof(txp_hsi_t)));}}
101
102#endif
103
104