1/*
2 * Copyright 2014-2017 Cavium, Inc.
3 * The contents of this file are subject to the terms of the Common Development
4 * and Distribution License, v.1,  (the "License").
5 *
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the License at available
9 * at http://opensource.org/licenses/CDDL-1.0
10 *
11 * See the License for the specific language governing permissions and
12 * limitations under the License.
13 */
14
15#ifndef _serdes_h_
16#define _serdes_h_
17
18#include "bcmtype.h"
19
20
21/*
22 * This structure defines the MDIO registers for the 2.5G Serdes block
23 *   Only those registers relevant to normal operation and configuration
24 *   are described.  Extra verbage is provided based on TetonII teams
25 *   experience with the core.  Bible for all registers is still
26 *   the spreadsheet provided by the serdes group.
27 */
28typedef struct serdes_reg
29{
30    u16_t mii_ctrl;            /* RW offset 0x00 */
31        #define MII_CTRL_RESET (1<<15)  /* SC */ /* Reset:0 */
32                /* Write of '1' initiate reset and will self clear when reset
33                   is complete.  Read of '1' indicates if PHY is currently
34                   executing reset. */
35        #define MII_CTRL_LOOPBACK (1<<14)  /* RW */
36                /* Value of '1' sets global loopback mode. */
37        #define MII_CTRL_MANUAL_SPD0 (1<<13)  /* RW */
38                /* Combine with <b>MANUAL_SPD1</b> and is valid in SGMII mode
39                   only.<br>
40                   00 = 10Mb/s<br>
41                   01 = 100Mb/s<br>
42                   10 = 1000Mb/s<br>
43                   11 = reserved */
44        #define MII_CTRL_ANEG_ENA (1<<12)  /* Reset:1 */
45        #define MII_CTRL_POWER_DOWN (1<<11)
46                /* Value of '1 enables low power mode. */
47        #define MII_CTRL_RESTART_ANEG (1<<9) /* SC */
48                /* Write of '1' initiate auto-negotiation and will self clear
49                   when auto-negotiation
50                   is complete. */
51        #define MII_CTRL_DUPLEX_MODE (1<<8)
52                /* Value of '1' indicates full duplex mode is set. */
53        #define MII_CTRL_COLLISION_TEST (1<<7)
54                /* Value of '1' enables collision test mode. */
55        #define MII_CTRL_MANUAL_SPD1 (1<<6)  /* RW */
56                /* Combine with <b>MANUAL_SPD0</b> and is valid in SGMII mode
57                   only. */
58        #define MII_CTRL_MANUAL_FORCE_2500 (1<<5)  /* RW */ /* Reset:0 */
59                /* Force 2.5G mode when autoneg is disabled and <b>USE_IEEE</b>
60                   is set.  Otherwise write as 0, ignore on read. */
61                /* Reset value is from <b>serdes_control_reg[13]</b> value in
62                   the misc block. */
63    u16_t mii_status;           /* RO offset 0x01 */
64        #define MII_STAT_100BASE_T4_CAP (1<<15) /* RO */ /* Reset:0 */
65        #define MII_STAT_100BASE_X_FULL_DUP_CAP (1<<14) /* RO */ /* Reset:0 */
66        #define MII_STAT_100BASE_X_HALF_DUP_CAP (1<<13) /* RO */ /* Reset:0 */
67        #define MII_STAT_10BASE_T_FULL_DUP_CAP (1<<12) /* RO */ /* Reset:0 */
68        #define MII_STAT_10BASE_T_HALF_DUP_CAP (1<<11) /* RO */ /* Reset:0 */
69        #define MII_STAT_100BASE_T2_FULL_DUP_CAP (1<<10) /* RO */ /* Reset:0 */
70        #define MII_STAT_100BASE_T2_HALF_DUP_CAP (1<<9) /* RO */ /* Reset:0 */
71        #define MII_STAT_EXT_STATUS (1<<8) /* RO */ /* Reset:1 */
72            /* Indicates that extended status information is in register f'h.
73               */
74        #define MII_STAT_MF_PREAMBLE_SUPP (1<<6) /* RO */ /* Reset:1 */
75            /* Indicates that preamble is not require on all MII accesses. */
76        #define MII_STAT_ANEG_CMPL (1<<5) /* RO */ /* Reset:0 */
77            /* Value of '1' indicates auto-negotiation complete. */
78            /* Value of '0' indicates auto-negotiation is in progress. */
79        #define MII_STAT_REMOTE_FAULT (1<<4) /* AC */ /* Reset:0 */
80            /* Value of '1' indicates remote fault detected. */
81            /* This bit latches high until read. */
82        #define MII_STAT_ANEG_ABILITY (1<<3) /* RO */ /* Reset:1 */
83            /* Value of '1' indicates auto-negotiation capable. */
84        #define MII_STAT_LINK_STATUS (1<<2) /* RO */ /* Reset:0 */
85            /* Value of '1' indicates line pass. */
86            /* Value of '0' indicates line fail. */
87            /* This bit latches low until read. */
88        #define MII_STAT_JABBER_DETECT (1<<1) /* RO */ /* Reset:0 */
89            /* Value of '1' indicates jabber condition detected. */
90        #define MII_STAT_EXTENDED_CAP (1<<0) /* RO */ /* Reset:1 */
91            /* Value of '1' indicates that extended register capabilities are
92               supported. */
93    u16_t mii_phy_id_msb;       /* Reset:0x143 offset 0x02 */
94            /* Bits [3:18] of organizationally unique identifier. */
95    u16_t mii_phy_id_lsb;       /* offset 0x03 */
96       #define MII_PHY_ID_OUI (0x3f<<10) /* RO */ /* Reset:0x2f */
97            /* Bits [19:24] of organizationally unique identifier. */
98       #define MII_PHY_ID_MODEL (0x3f<<4) /* RO */ /* Reset:0x15 */
99            /* Device Mode number. */
100       #define MII_PHY_ID_REV (0xf<<0) /* RO */ /* Reset:0 */
101            /* Device revision number. */
102
103    u16_t mii_aneg_advert;           /* RW offset 0x04 */
104       #define MII_ADVERT_NXT_PG (1<<15) /* RO */
105            /* Value of '0' indicates that next page ability capability can
106               not be advertised. */
107       #define MII_ADVERT_REM_FAULT (0x3<<12) /* RW */
108        #define MII_ADVERT_REM_FAULT_NO_FAULT (0<<12)
109                /* No remote fault */
110        #define MII_ADVERT_REM_FAULT_LINK_FAILURE (1<<12)
111                /* Link failure */
112        #define MII_ADVERT_REM_FAULT_OFFLINE (2<<12)
113                /* offline */
114        #define MII_ADVERT_REM_FAULT_AUTONEG_ERR (3<<12)
115                /* auto-negotiation error */
116       #define MII_ADVERT_PAUSE (3<<7) /* RW */ /* Reset:0x3 */
117        #define MII_ADVERT_NO_PAUSE (0x0<<7)
118                /* Advertise no Pause */
119        #define MII_ADVERT_SYM_PAUSE (0x1<<7)
120                /* Advertise symmetric Pause */
121        #define MII_ADVERT_ASYM_PAUSE (0x2<<7)
122                /* Advertise asymmetric Pause toward link partner */
123//        #define MII_ADVERT_PAUSE (0x3<<7)
124                /* Advertise both symmetric pause and asymmetric pause
125                   toward local device. */
126       #define MII_ADVERT_HALF (1<<6) /* RW */  /* Reset:1 */
127                /* Advertise half duplex capability. */
128       #define MII_ADVERT_FULL (1<<5) /* RW */  /* Reset:1 */
129    u16_t mii_aneg_ability;           /* RW offset 0x05 */
130       #define MII_ABILITY_NXT_PG (1<<15) /* RO */
131            /* Value of '1' indicates that link partner has next page ability.
132               */
133       #define MII_ABILITY_ACKNOWLEDGE (1<<14) /* RO */
134            /* Value of '1' indicates that link partner has receive link code
135               word. */
136       #define MII_ABILITY_REM_FAULT (3<<12) /* RO */
137         #define MII_ABILITY_REM_FAULT_AUTONEG_ERR (0<<12) /* RO */
138            /* auto-negotiation error. */
139         #define MII_ABILITY_REM_FAULT_OFFLINE (1<<12) /* RO */
140            /* Offline. */
141         #define MII_ABILITY_REM_FAULT_LINK_FAILURE (2<<12) /* RO */
142            /* Link Failure. */
143         #define MII_ABILITY_REM_FAULT_NO_FAULT (3<<12) /* RO */
144            /* No remote fault detected. */
145       #define MII_ABILITY_PAUSE (3<<7) /* RO */ /* Reset:0x3 */
146        #define MII_ADVERT_NO_PAUSE (0x0<<7)
147                /* Line partner indicates No Pause capable */
148        #define MII_ADVERT_SYM_PAUSE (0x1<<7)
149                /* Line partner wants Symmetric Pause capable */
150        #define MII_ADVERT_ASYM_PAUSE (0x2<<7)
151                /* Line partner wants Asymetric Pause toward link partner
152                   capable */
153//        #define MII_ADVERT_PAUSE (0x3<<7)
154                /* Line partner wants Both symmetric pause and asymmetric pause
155                   toward local device capable. */
156       #define MII_ABILITY_HALF (1<<6) /* RO */ /* Reset:1 */
157                /* Value of '1' indicates Link partner is half duplex capable.
158                   */
159       #define MII_ABILITY_FULL (1<<5) /* RO */ /* Reset:1 */
160                /* Value of '1' indicates Link partner is full duplex capable.
161                   */
162       #define MII_ABILITY_SGMII (1<<0) /* RO */
163                /* Value of '1' indicates link partner is in SGMII mode. */
164       /* When SGMII mode is enabled, reading values reflect values sent by
165           link partner where:<br>
166           [15] = copper link<br>
167           [14] = acknowledge<br>
168           [12] = copper duplex<br>
169           [11:10] = copper speed<br>
170           [0] = SGMII selector */
171    u16_t mii_aneg_exp;           /* RW offset 0x06 */
172       #define MII_ANEG_EXP_NP_ABLE (1<<2) /* RO */
173            /* Value of '1' indicates local device is next page capable.
174               */
175       #define MII_ANEG_EXP_PG_RCV (1<<1) /* AC */
176            /* Value of '1' indicates a new link code word has been received.
177               */
178    u16_t mii_aneg_nxt_pg;           /* RW offset 0x07 */
179       #define MII_ANEG_NXT_PG_NX_PG (1<<15) /* RW */
180            /* During SW controlled auto-negotiation, this value controls the
181               next_page value in the next page generated. */
182       #define MII_ANEG_NXT_PG_ACK (1<<14) /* RW */
183            /* During SW controlled auto-negotiation, this value is controlled
184               by autoneg state machine to confirm page reception. */
185       #define MII_ANEG_NXT_PG_MP (1<<13) /* RW */
186            /* During SW controlled auto-negotiation, this value controls the
187               message page bit value in the next page generated. */
188       #define MII_ANEG_NXT_PG_ACK2 (1<<12) /* RW */
189            /* During SW controlled auto-negotiation, this value is controlled
190               by autoneg state machine to confirm page reception. */
191       #define MII_ANEG_NXT_PG_TOG (1<<11) /* RW */
192            /* During SW controlled auto-negotiation, this value is controlled
193               by autoneg state machine to confirm page reception. */
194       #define MII_ANEG_NXT_PG_VALUE (0x7ff<<0) /* RW */
195            /* During SW controlled auto-negotiation, this value controls the
196               11-bit message page or unformatted code field in the next page
197               generated. */
198    u16_t mii_aneg_nxt_ability;           /* RW offset 0x08 */
199       #define MII_ANEG_NXT_ABIL_NX_PG (1<<15) /* RW */
200            /* During SW controlled auto-negotiation, this value reflects the
201               next_page value in the last page received. */
202       #define MII_ANEG_NXT_ABIL_ACK (1<<14) /* RW */
203            /* During SW controlled auto-negotiation, this value is used
204               by autoneg state machine to confirm page reception. */
205       #define MII_ANEG_NXT_ABIL_MP (1<<13) /* RW */
206            /* During SW controlled auto-negotiation, this value reflects the
207               message page bit value in the last page received. */
208       #define MII_ANEG_NXT_ABIL_ACK2 (1<<12) /* RW */
209            /* During SW controlled auto-negotiation, this value is used
210               by autoneg state machine to confirm page reception. */
211       #define MII_ANEG_NXT_ABIL_TOG (1<<11) /* RW */
212            /* During SW controlled auto-negotiation, this value is used
213               by autoneg state machine to confirm page reception. */
214       #define MII_ANEG_NXT_ABIL_VALUE (0x7ff<<0) /* RW */
215            /* During SW controlled auto-negotiation, this value reflects the
216               11-bit message page or unformatted code field in the last page
217               received. */
218    u16_t mii_reserved_9[2];               /* offset 0x09-0x0a */
219    u16_t mii_aneg_nxt_pg_xmit1;           /* RW offset 0x0b */
220            /* If <b>USE_IEEE</b> is set, this page is transmitted after
221               the message page of value 1024 is sent.   */
222       #define MII_ANEG_NXT_PG_XMIT1_VALUE (0x3ff<<1) /* RW */
223            /* Advertise reserved BRCM proprietary values. */
224       #define MII_ANEG_NXT_PG_XMIT1_2G5 (1<<0) /* RW */
225            /* Reset value is defined by the
226               value of <b>serdes_control_reg[11]</b> value in the misc block.
227               Value advertizes 2.5G capability by BRCM
228               proprietary convention.
229               */
230    u16_t mii_aneg_nxt_pg_xmit2;           /* RW offset 0x0c */
231            /* If <b>USE_IEEE</b> is set, this page is transmitted after
232               the <b>auto_nxt_pg_xmit1</b> page is sent.   */
233       #define MII_ANEG_NXT_PG_XMIT2_VALUE (0x7ff<<0) /* RW */ /* Reset:0 */
234            /* By BRCM proprietary convention, these bits advertize the
235               pre-compensation value to be used for backplane media and should
236               be non-zero if local end knows the nature of the backplane
237               media. */
238    u16_t mii_aneg_nxt_pg_rcv1;           /* RW offset 0x0d */
239            /* This register shows the value received after the
240               message page of value 1024 is received when
241               <b>USE_IEEE</b> is set. */
242       #define MII_ANEG_NXT_PG_RCV1_VALUE (0x3ff<<1) /* RW */
243            /* The advertized capability of link partner for reserved
244               BRCM proprietary values.
245               */
246       #define MII_ANEG_NXT_PG_RCV1_2G5 (1<<0) /* RW */
247            /* The link partner advertized 2.5G capability by
248               BRCM proprietary convention.
249               */
250    u16_t mii_aneg_nxt_pg_rcv2;           /* RW offset 0x0e */
251            /* This register shows the value received after the
252               <b>auto_nxt_pg_rcv1</b> page is received when
253               <b>USE_IEEE</b> is set. */
254       #define MII_ANEG_NXT_PG_RCV2_VALUE (0x7ff<<0) /* RW */ /* Reset:0 */
255            /* By BRCM proprietary convention, bits [3:0] of this value are the
256               advertized value of pre-emphasis value to be used for backplane
257               media and should be non-zero if remote end knows the nature of
258               the backplane media.
259               Firmware must manually move this value to the <b>PREEMPHASIS</b>
260               value in 5*0x17 and re-start auto-negotiation with the new
261               pre-emphasis value in use.
262             */
263    u16_t mii_extend_stat;           /* RO offset 0x0f */
264       #define MII_EXT_STAT_X_FULL_CAP (1<<15) /* RO */
265                /* This bit indicates that the negotiated link is 1000Base-X
266                   full duplex capable. */
267       #define MII_EXT_STAT_X_HALF_CAP (1<<14) /* RO */
268                /* This bit indicates that the negotiated link is 1000Base-X
269                   half duplex capable. */
270       #define MII_EXT_STAT_T_FULL_CAP (1<<13) /* RO */
271                /* This bit indicates that the negotiated link is 1000Base-T
272                   full duplex capable. */
273       #define MII_EXT_STAT_T_HALF_CAP (1<<12) /* RO */
274                /* This bit indicates that the negotiated link is 1000Base-T
275                   half duplex capable. */
276    u16_t mii_block[15];           /* RW offset 0x10-0x1e */
277    u16_t mii_block_addr;          /* RW offset 0x1f */
278       #define MII_BLK_ADDR_VALUE (0x1f<<0) /* RW */ /* VALUE: */
279                /* Writes to this value set the block address value. */
280            #define MII_BLK_ADDR_DIGITAL (0x0<<0)
281                    /* This block value selects the digital register block. */
282                    /* This block is partially documented in this spec. */
283                    /* See SERDES documentation for full details on this
284                       register block. */
285            #define MII_BLK_ADDR_TEST (0x1<<0)
286                    /* This block value selects the test register block. */
287                    /* See SERDES documentation for details on this register
288                       block. */
289            #define MII_BLK_ADDR_DIGITAL3 (0x2<<0)
290                    /* This block value selects the test register block. */
291                    /* This block is partially documented in this spec. */
292                    /* See SERDES documentation for full details on this
293                       register block. */
294            #define MII_BLK_ADDR_PLL (0x3<<0)
295                    /* This block value selects the PLL register block. */
296                    /* See SERDES documentation for details on this register
297                       block. */
298            #define MII_BLK_ADDR_RX (0x4<<0)
299                    /* This block value selects the RX register block. */
300                    /* See SERDES documentation for details on this register
301                       block. */
302            #define MII_BLK_ADDR_TXMISC (0x5<<0)
303                    /* This block value selects the TX/Misc register block. */
304                    /* This block is partially documented in this spec. */
305                    /* See SERDES documentation for full details on this
306                       register block. */
307
308} serdes_reg_t;
309
310
311/*
312 * DIGITAL Block selected in <b>block</b> section of serdes
313 * registers when <b>block_addr</b> value is 0.
314 */
315typedef struct serdes_digital_reg
316{
317    u16_t mii_1000x_ctl1;            /* RW */
318       #define MII_1000X_CTL1_MSTR_MDIO_PHY_SEL (1<<13) /* RW */
319                    /* When set to '1', all MDIO write accesses to PHY address
320                       "00000" will write this PHY in addition to its own PHY
321                       address. */
322       #define MII_1000X_CTL1_TX_AMPL_ORIDE (1<<12) /* RW */
323                    /* When set to '1', the transmit amplitude of the serdes
324                       will com from register 1*10h, bit 14.
325                       When set to '0', the amplitude is selected by fiber or
326                       SGMII mode. */
327       #define MII_1000X_CTL1_SEL_RX_PKTS_CNT (1<<11) /* RW */
328                    /* When set to '1', received packets will be selected for
329                       the 0*17h counter register. */
330       #define MII_1000X_CTL1_REM_LOOP (1<<10) /* RW */
331                    /* When set to '1', remote loopback is enabled.  This mode
332                       only operates at gigabit speed. */
333       #define MII_1000X_CTL1_ZERO_COMMA_PHASE (1<<9) /* RW */
334                    /* When set to '1', the comma phase detector is forced to
335                       zero. */
336       #define MII_1000X_CTL1_COMMA_DET_EN (1<<8) /* RW */ /* Reset:1 */
337                    /* When set to '1', the comma detector is enabled. */
338       #define MII_1000X_CTL1_CRC_CHK_DIS (1<<7) /* RW */ /* Reset:1 */
339                    /* When set to '1', the CRC checker is disabled by gating
340                       the clock to that logic to save power. */
341       #define MII_1000X_CTL1_PLL_PWR_DWN_DIS (1<<6) /* RW */ /* Reset:0 */
342                    /* When set to '1', the PLL will never be powered down.
343                       This is used when the MAC/Switch uses the tx_wclk_o
344                       output of the SERDES core. */
345       #define MII_1000X_CTL1_SGMII_MSTR (1<<5) /* RW */ /* Reset:0 */
346                    /* When set to '1', the SGMII mode operates in "PHY mode",
347                       sending out link, speed, and duplex settings from
348                       register 0 of the copper PHY to the SERDES link partner.
349                       */
350       #define MII_1000X_CTL1_AUTODET_EN (1<<4) /* RW */ /* Reset:0 */
351                    /* when set to '1', the PHY will switch between SGMII mode
352                       and fiber mode when an auto-negotiation page is
353                       received with the wrong selector field in bit 0.
354                       When set to '0', selection of fiber/SGMII mode is
355                       controlled by <b>FIBER_MODE</b> bit. */
356       #define MII_1000X_CTL1_INV_SIG_DET (1<<3) /* RW */ /* Reset:0 */
357                    /* When set to '1', the signal detect sense of the signal
358                       detect input is active low, instead of active high. */
359       #define MII_1000X_CTL1_SIG_DET_EN (1<<2) /* RW */ /* Reset:1 */
360                    /* When set to '1', the signal detect input of the chip
361                       must be active to link.  In SGMII mode, the signal
362                       detect input is always ignored, regardless of the
363                       setting of this bit. */
364       #define MII_1000X_CTL1_TBI_INTF (1<<1) /* RW */ /* Reset:0 */
365                    /* This bit must always be set to '0' for proper operation
366                       of TetonII. */
367       #define MII_1000X_CTL1_FIBER_MODE (1<<0) /* RW */
368                    /* Reset value of this register is controlled by the
369                       value of <b>serdes_control_reg[12]</b> value in the misc
370                       block.
371                       When this bit is '0', SGMII mode is selected.
372                       When this bit is '1', Fiber mode (Clause 37 mode) is
373                       selected.
374                       Automatic mode selection, overiding this bit's value is
375                       enabled by the <b>AUTONEG_EN</b> bit. */
376    u16_t mii_1000x_ctl2;            /* RW */
377       #define MII_1000X_CTL2_TEST_CNTR (1<<11) /* RW */ /* Reset:0 */
378                    /* When this bit is '1', the counter at location 0*17h
379                       counts on each clock for testing. */
380       #define MII_1000X_CTL2_BYP_PCS_TX (1<<10) /* RW */ /* Reset:0 */
381                    /* When this bit is '1', the PCS transmit section
382                       is bypassed. */
383       #define MII_1000X_CTL2_BYP_PCS_RX (1<<9) /* RW */ /* Reset:0 */
384                    /* When this bit is '1', the PCS receive section
385                       is bypassed. */
386       #define MII_1000X_CTL2_TRRR_GEN_DIS (1<<8) /* RW */ /* Reset:0 */
387                    /* When this bit is '1', the TRRR generation in the PCS
388                       transmit is disabled. */
389       #define MII_1000X_CTL2_CARRIER_EXT_DIS (1<<7) /* RW */ /* Reset:0 */
390                    /* When this bit is '1', carrier extension in the PCS
391                       receive is disabled. */
392       #define MII_1000X_CTL2_FAST_TIMERS (1<<6) /* RW */ /* Reset:0 */
393                    /* When this bit is '1', timers during auto-negotiation are
394                       sped-up for testing. */
395       #define MII_1000X_CTL2_FRCE_XMIT_DATA (1<<5) /* RW */ /* Reset:0 */
396                    /* When this bit is '1', packets are allowed to transmit
397                       regardless of the condition of link or synchronization.
398                       */
399       #define MII_1000X_CTL2_REM_FAULT_SENSE_DIS (1<<4) /* RW */ /* Reset:0 */
400                    /* When this bit is '1', sensing of remote faults such as
401                       auto-negotiation errors is disabled.
402                       When this bit is '0', SERDES automatically detects
403                       remote faults and sends remote fault status to link
404                       partner via auto-negotiation when fiber mode is
405                       selected.  SGMII mode does not support remote faults. */
406       #define MII_1000X_CTL2_ANEG_ERR_TMR_EN (1<<3) /* RW */ /* Reset:0 */
407                    /* When this bit is '1', it enables the auto-negotiation
408                       error timer.  Error occurs when timer expires in
409                       ability-detect, ack-detect, or idle-detect.  When the
410                       error occurs, config words of all zeros are sent until
411                       an ability match occurs, then the autoneg-enable state
412                       is entered. */
413       #define MII_1000X_CTL2_FILTER_FORCE_LINK (1<<2) /* RW */ /* Reset:0 */
414                    /* When this bit is '1', sync-status must be set for a
415                       solid 10ms before a valid link will be established when
416                       auto-negotiation is disabled.  This is useful for fiber
417                       application where the user does not have the signal
418                       detect pin connnection to the fiber module and
419                       auto-negotiation is turned off. */
420       #define MII_1000X_CTL2_FLASE_LINK_DIS (1<<1) /* RW */ /* Reset:0 */
421                    /* When this bit is '1', do not allow link to be
422                       established when auto-negotiation is disabled and
423                       receiving auto-negotiation code words.  The link will
424                       only be established in this case after idles are
425                       received.  This bit does not need to be set if
426                       <b>PAR_DET_EN</b> is set. */
427       #define MII_1000X_CTL2_PAR_DET_EN (1<<0) /* RW */ /* Reset:0 */
428                    /* Reset value of this register is controlled by the
429                       value of <b>serdes_control_reg[15]</b> value in the misc
430                       block.
431                       When this bit is '1', parallel detection will be
432                       enabled.  This will turn auto-negotiation on and off as
433                       needed to properly link up with the link partner.  The
434                       idles and auto-negotiation code words received from the
435                       link partner are used to make decision.   */
436    u16_t mii_1000x_ctl3;            /* RW */
437       #define MII_1000X_CTL3_DIS_TX_CRS (1<<13) /* RW */ /* Reset:0 */
438                    /* When this bit is '1', generating CRS from transmitting
439                       in half duplex mode is disabled.  Only receiving will
440                       generate CRS. */
441       #define MII_1000X_CTL3_INV_EXT_CRS (1<<12) /* RW */ /* Reset:0 */
442                    /* When this bit is '1', the "receive rcs from PHY" pin
443                       value will be inverted. */
444       #define MII_1000X_CTL3_EXT_PHY_CRS (1<<11) /* RW */ /* Reset:0 */
445                    /* When this bit is '1', use external pin for PHY's
446                       "receive only" CRS output.  This is useful in 10/100
447                       half-duplex applications to reduce the collision domain
448                       latency.  This requires a PHY which generates a "receive
449                       only" CRS output to a pin. */
450       #define MII_1000X_CTL3_JAM_FALSE (1<<10) /* RW */ /* Reset:0 */
451                    /* When this bit is '1', change false carriers received
452                       into packets with preamble only.  Not necessary if MAC
453                       uses CRS to determine collision. */
454       #define MII_1000X_CTL3_BLOCK_TXEN (1<<9) /* RW */ /* Reset:0 */
455                    /* When this bit is '1', block TXEN when necessary to
456                       guarantee an IPG of at least 6.5 bytes in 10/100 mode
457                       and 7 byte in 1G mode. */
458       #define MII_1000X_CTL3_FORCE_TXFIFO_ON (1<<8) /* RW */ /* Reset:0 */
459                    /* When this bit is '1', force transmit FIFO to free-run in
460                       1G mode.  This requires clk_IN and tx_wclk_o to be
461                       frequency locked. */
462       #define MII_1000X_CTL3_BYP_TXFIFO1000 (1<<7) /* RW */ /* Reset:0 */
463                    /* When this bit is '1', bypass transmit FIFO in 1G mode.
464                       This is useful for fiber or gigabit only applications
465                       where the MAC is using tx_wclk_o as the clk_in port.
466                       MAC must meet timing to the tx_wclk_o domain. */
467       #define MII_1000X_CTL3_FREQ_LOCK_ELAST_TX (1<<6) /* RW */ /* Reset:0 */
468                    /* When this bit is '1', minimum FIFO latency to properly
469                       handle a clock which is frequency locked, but out of
470                       phase.  This over-rides bits [2:1] of this register.
471                       Note:  tx_wclk_o and clk_in must be using the same
472                       crystal. */
473       #define MII_1000X_CTL3_FREQ_LOCK_ELAST_RX (1<<5) /* RW */ /* Reset:0 */
474                    /* When this bit is '1', minimum FIFO latency to properly
475                       handle a clock which is frequency locked, but out of
476                       phase.  Not necessary if MAC users CRS to determine
477                       collision.  This over-rides bits [2:1] of this register.
478                       Note:  MAC and PHY must be using the same crystal for
479                       this mode to be enabled. */
480       #define MII_1000X_CTL3_ERLY_PREAMBLE_RX (1<<4) /* RW */ /* Reset:0 */
481                    /* When this bit is '1', send extra bytes of preamble to
482                       avoid FIFO latency.  Not needed if MAC uses CRS to
483                       determine collision. */
484       #define MII_1000X_CTL3_ERLY_PREAMBLE_TX (1<<3) /* RW */ /* Reset:0 */
485                    /* When this bit is '1', send extra bytes of preamble to
486                       avoid FIFO latency.  Uses in half-duplex applications to
487                       reduce collision domain latency.  MAC must send 5 bytes
488                       of preamble or less to avoid non-compliant behavior. */
489       #define MII_1000X_CTL3_FIFO_ELAST (3<<1) /* RW */ /* Reset:0 */
490        #define MII_1000X_CTL3_FIFO_ELAST_5K (0<<1)
491            /* Supports packets up to 5k bytes. */
492        #define MII_1000X_CTL3_FIFO_ELAST_10K (1<<1)
493            /* Supports packets up to 10k bytes. */
494        #define MII_1000X_CTL3_FIFO_ELAST_13K5 (2<<1)
495            /* Supports packets up to 13.5k bytes. */
496    #define MII_1000X_CTL3_TX_FIFO_RXT (1<<0)
497                    /* When this bit is set to '1', the transmit FIFO is reset.
498                       FIFO will remain in reset until this bit is cleared. */
499    u16_t mii_reserved1;            /* RW */
500    u16_t mii_1000x_stat1;            /* RO */
501       #define MII_1000X_STAT1_TXFIFO_ERR_DET (1<<15) /* AC */ /* Reset:0 */
502                    /* When this bit is '1', transmit FIFO error has been
503                       detected since last read. */
504       #define MII_1000X_STAT1_RXFIFO_ERR_DET (1<<14) /* AC */ /* Reset:0 */
505                    /* When this bit is '1', receive FIFO error has been
506                       detected since last read. */
507       #define MII_1000X_STAT1_FALSE_CARRIER_DET (1<<13) /* AC */ /* Reset:0 */
508                    /* When this bit is '1', flase carrier has been
509                       detected since last read. */
510       #define MII_1000X_STAT1_CRC_ERR_DET (1<<12) /* AC */ /* Reset:0 */
511                    /* When this bit is '1', CRC error has been detected since
512                       last read. */
513       #define MII_1000X_STAT1_TX_ERR_DET (1<<11) /* AC */ /* Reset:0 */
514                    /* When this bit is '1', a transmit error has been
515                       detected.  This indicates tx_data_error_state in PCS
516                       receive FSM has been reached since the last read. */
517       #define MII_1000X_STAT1_RX_ERR_DET (1<<10) /* AC */ /* Reset:0 */
518                    /* When this bit is '1', a receive error has been
519                       detected.  This indicates early_end_state in PCS
520                       receive FSM has been reached since the last read. */
521       #define MII_1000X_STAT1_CARRIER_EXT_ERR_DET (1<<9) /* AC */ /* Reset:0 */
522                    /* When this bit is '1', a carrier extend error code has
523                       been detected.  This indicates extend_err_state in PCS
524                       receive FSM has been reached since the last read. */
525       #define MII_1000X_STAT1_EARLY_END_EXT_ERR_DET (1<<8) /* AC */ /* Reset:0 */
526                    /* When this bit is '1', a early end extension error code
527                       has been detected.  This indicates early_end_ext_state
528                       in PCS receive FSM has been reached since the last
529                       read. */
530       #define MII_1000X_STAT1_LINK_STATUS (1<<7) /* RO */ /* Reset:0 */
531                    /* When this bit is '1', it indicates that link has been up
532                       the entire time since the last read.
533                       This bit latches low until next read and return to '1'
534                       upon read when link is up. */
535       #define MII_1000X_STAT1_PAUSE_RX_RESOLVE (1<<6) /* RO */ /* Reset:0 */
536                    /* This bit will read as '1' when auto-negotiation has
537                       resolved to allow reception of pause frames locally. */
538       #define MII_1000X_STAT1_PAUSE_TX_RESOLVE (1<<5) /* RO */ /* Reset:0 */
539                    /* This bit will read as '1' when auto-negotiation has
540                       resolved to allow transmission of pause frames
541                       locally. */
542       #define MII_1000X_STAT1_SPEED (3<<3) /* RO */ /* Reset:0 */
543                    /* These bits indicate the current speed status. */
544            #define MII_1000X_STAT1_SPEED_10 (0<<3) /* 10 MBPS */
545            #define MII_1000X_STAT1_SPEED_100 (1<<3) /* 100 MBPS */
546            #define MII_1000X_STAT1_SPEED_1G (2<<3) /* 1 GBPS */
547            #define MII_1000X_STAT1_SPEED_2G5 (3<<3) /* 2.5 GBPS */
548       #define MII_1000X_STAT1_DUPLEX (1<<2) /* RO */ /* Reset:0 */
549                    /* When this bit is '0', half duplex is enabled.
550                       When this bit is '1', full duplex is enabled. */
551       #define MII_1000X_STAT1_LINK (1<<1) /* RO */ /* Reset:0 */
552                    /* When this bit is '1', the link is up.
553                       When this bit is '0', the link is down. */
554       #define MII_1000X_STAT1_SGMII_MODE (1<<0) /* RO */ /* Reset:0 */
555                    /* When this bit is '1', SGMII mode has been selected.
556                       When this bit is '0', Fiber mode has been selected. */
557    u16_t mii_1000x_stat2;            /* RW */
558       #define MII_1000X_STAT2_SGMII_CHG (1<<15) /* AC */ /* Reset:0 */
559                    /* When this bit is '1', SGMII mode has changed since the
560                       last read.  SGMII mode has been enabled or disabled.
561                       This bit is useful when the auto-detection is enabled
562                       in 0*10h, bit 4. */
563       #define MII_1000X_STAT2_CONS_MISMATCH (1<<14) /* AC */ /* Reset:0 */
564                    /* When this bit is '1', a consistency mismatch has been
565                       detected since the last read. */
566       #define MII_1000X_STAT2_ANEG_RES_ERR (1<<13) /* AC */ /* Reset:0 */
567                    /* When this bit is '1', a auto-negotiation HCD error has
568                       been detected since  the last read. */
569       #define MII_1000X_STAT2_SGMII_SEL_MISMATCH (1<<12) /* AC */ /* Reset:0 */
570                    /* When this bit is '1', a SGMII selector mismatch has
571                       been detected since  the last read.  An auto-negotiation
572                       page has been received from link partner with bit 0 = 0
573                       while in SGMII mode.  */
574       #define MII_1000X_STAT2_SYN_STAT_FAIL (1<<11) /* AC */ /* Reset:0 */
575                    /* When this bit is '1', sync_status has failed since the
576                       last read.  Synchronization has been lost. */
577       #define MII_1000X_STAT2_SYN_STAT_OK (1<<10) /* AC */ /* Reset:0 */
578                    /* When this bit is '1', sync_status ok has been detected
579                       since the last read.  Synchronization has been achieved.
580                     */
581       #define MII_1000X_STAT2_RUDI_C (1<<9) /* AC */ /* Reset:0 */
582                    /* When this bit is '1', rudi_c has been detected
583                       since the last read.  */
584       #define MII_1000X_STAT2_RUDI_I (1<<8) /* AC */ /* Reset:0 */
585                    /* When this bit is '1', rudi_i has been detected
586                       since the last read.  */
587       #define MII_1000X_STAT2_RUDI_INVALID (1<<7) /* AC */ /* Reset:0 */
588                    /* When this bit is '1', rudi_invalid has been detected
589                       since the last read.  */
590       #define MII_1000X_STAT2_AN_SYNC_STAT (1<<6) /* RO */ /* Reset:0 */
591                    /* When this bit is '1', an_sync_status in auto-negotiation
592                       block has not failed since last read.
593                       When this bit is '0', an_sync_status in auto-negotiation
594                       block has failed since last read.  Value sticks at '0'
595                       until read. */
596       #define MII_1000X_STAT2_IDLE_DET (1<<5) /* AC */ /* Reset:0 */
597                    /* When this bit is '1', the idle detect state in
598                       auto-negotiation fsm has been entered since last read.
599                     */
600       #define MII_1000X_STAT2_CMPL_ACK (1<<4) /* AC */ /* Reset:0 */
601                    /* When this bit is '1', the complete acknowledge state in
602                       auto-negotiation fsm has been entered since last read. */
603       #define MII_1000X_STAT2_ACK_DET (1<<3) /* AC */ /* Reset:0 */
604                    /* When this bit is '1', the acknowledge detect state in
605                       auto-negotiation fsm has been entered since last read. */
606       #define MII_1000X_STAT2_ABIL_DET (1<<2) /* AC */ /* Reset:0 */
607                    /* When this bit is '1', the ability detect state in
608                       auto-negotiation fsm has been entered since last read. */
609       #define MII_1000X_STAT2_AN_ERR_DET (1<<1) /* AC */ /* Reset:0 */
610                    /* When <b>ANEG_ERR_TMR_EN</b> is '1' and this bit is '1',
611                       the an_error state in auto-negotiation fsm has been
612                       entered since last read. */
613                    /* When <b>ANEG_ERR_TMR_EN</b> is '0' and this bit is '1',
614                       the an_disable_link_ok state in auto-negotiation fsm has
615                       been entered since last read. */
616       #define MII_1000X_STAT2_AN_EN_DET (1<<0) /* AC */ /* Reset:0 */
617                    /* When this bit is '1', the an_enable state in
618                       auto-negotiation fsm has been entered since last read. */
619    u16_t mii_reserved2[9];            /* RW */
620
621} serdes_digital_reg_t;
622
623/*
624 * DIGITAL3 Block selected in <b>block</b> section of serdes
625 * registers when <b>block_addr</b> value is 2.
626 */
627typedef struct serdes_digital3_reg
628{
629    u16_t mii_digctl_3_0;            /* RW */
630       #define MII_DIG3_USE_IEEE (1<<0) /* RW */ /* USE_IEEE: */
631                    /* When this bit is '0', extended auto-negotiation
632                       capabilities
633                       and results are in digital_3 block registers.
634                       When this bit is '1', extended auto-negotiation
635                       capabilities and results are stored in digital block
636                       registers. */
637    u16_t mii_reserved1[14];            /* RW */
638
639} serdes_digital3_reg_t;
640
641/*
642 * TX/Misc Block selected in <b>block</b> section of serdes
643 * registers when <b>block_addr</b> value is 5.
644 */
645typedef struct serdes_tx_misc_reg
646{
647    u16_t mii_2500status1;            /* RW */
648       #define MII_2500STAT1_HCDOVER1G (1<<12) /* RW */
649                    /* When this bit is '1', the HCD is over 1G. */
650       #define MII_2500STAT1_HCDOVER1G_STKY (1<<11) /* AC */
651                    /* When this bit is '1', the HCD has been over 1G since the
652                       last read. */
653       #define MII_2500STAT1_BC_REG_RST (1<<10) /* AC */
654                    /* When this bit is '1', then advertisement of over 1G has
655                       been disabled due to repeated failures to link over 1G
656                       since the last read. */
657       #define MII_2500STAT1_COMPLETE (1<<9) /* AC */
658                    /* 2.5G state machine has reached complete state since last
659                       read. */
660       #define MII_2500STAT1_WAIT4LINK (1<<8) /* AC */
661                    /* 2.5G state machine has reached wait4link state since last
662                       read. */
663       #define MII_2500STAT1_PLLSWIT (1<<7) /* AC */
664                    /* 2.5G state machine has reached pllswit state since last
665                       read. */
666       #define MII_2500STAT1_FORCE2500 (1<<6) /* AC */
667                    /* 2.5G state machine has reached force2500 state since
668                       last read. */
669       #define MII_2500STAT1_DEAD (1<<5) /* AC */
670                    /* 2.5G state machine has reached dead state since
671                       last read. */
672       #define MII_2500STAT1_WAIT2RES (1<<4) /* AC */
673                    /* 2.5G state machine has reached wait2res state since
674                       last read. */
675    u16_t mii_reserved1[4];            /* RW */
676
677    u16_t mii_txactl1;            /* RW */
678        /* Use read-modify-write procedure for changing this register with
679           firmware because default values may change from chip version to chip
680           version, based on foundry, process, etc. */
681       #define MII_TXACTL1_DRIVER_VCM (0x3<<4) /* RW */
682                                               /* Reset:1 */
683       #define MII_TXACTL1_PREEMPHASIS_PRE (0x7<<6) /* RW */
684       #define MII_TXACTL1_DRIVEMODE (0x1<<9) /* RW */
685       #define MII_TXACTL1_TX_TDATAEN (0x1<<10) /* RW */
686       #define MII_TXACTL1_REFH_TX (0x1<<11) /* RW */
687       #define MII_TXACTL1_REFL_TX (0x1<<12) /* RW */
688       #define MII_TXACTL1_ID2C_2 (0x1<<13) /* RW */
689            /* Bits [2] of ID2C. */
690
691    u16_t mii_reserved2;            /* RW */
692
693    u16_t mii_txactl3;            /* RW */
694        /* Use read-modify-write procedure for changing this register with
695           firmware because default values may change from chip version to chip
696           version, based on foundry, process, etc. */
697       #define MII_TXACTL3_PREEMPHASIS (0xf<<12) /* RW */
698                    /* This value controls transmitter pre-emphasis.
699                       Value is A where pre-emphasis=A/(40-A).  For example, if
700                       register is set to 0x1, then pre-empasis co-efficient
701                       is 1/(40-1)=0.025 or 1/39th of main tap current. */
702                    /* This value is bit flipped such that the value is [0:3]
703                       within the field. */
704       #define MII_TXACTL3_IDRIVER (0xf<<8) /* RW */    /* Reset:0xe */
705                    /* This value is bit flipped such that the value is [0:3]
706                       within the field. */
707       #define MII_TXACTL3_IPREDRIVER (0xf<<4) /* RW */    /* Reset:0x9 */
708                    /* This value is bit flipped such that the value is [0:3]
709                       within the field. */
710       #define MII_TXACTL3_IFULLSPD (0x7<<1) /* RW */    /* Reset:0 */
711                    /* This value is bit flipped such that the value is [0:2]
712                       within the field. */
713       #define MII_TXACTL3_ICBUF1T (0x1<<0) /* RW */    /* Reset:0 */
714
715    u16_t mii_reserved3[7];            /* RW */
716
717} serdes_tx_misc_reg_t;
718
719#endif  /* _serdes_h_ */
720
721/****************************************************************************
722 * End of file
723 ****************************************************************************/
724
725