1/*
2 * Copyright 2014-2017 Cavium, Inc.
3 * The contents of this file are subject to the terms of the Common Development
4 * and Distribution License, v.1,  (the "License").
5 *
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the License at available
9 * at http://opensource.org/licenses/CDDL-1.0
10 *
11 * See the License for the specific language governing permissions and
12 * limitations under the License.
13 */
14
15#include "bcmtype.h"
16
17#ifndef _5709_reg_h_
18#define _5709_reg_h_
19
20// ???? #pragma pack(4)
21
22#ifndef STATUS_BLOCK_SPACING
23#define STATUS_BLOCK_SPACING            64
24#endif
25
26#if !defined(LITTLE_ENDIAN) && !defined(BIG_ENDIAN)
27    #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
28#endif
29
30
31
32/*
33 *  tx_bd_b definition
34 */
35typedef struct tx_bd_b
36{
37    u32_t tx_bd_haddr_hi;
38    u32_t tx_bd_haddr_lo;
39    u16_t tx_bd_reserved;
40        #define TX_BD_RESERVED_MSS                          (0x3fff<<0)
41        #define TX_BD_RESERVED_BIT14_15                     (0x03<<14)
42    u16_t tx_bd_nbytes;
43    u16_t tx_bd_vlan_tag;
44    u16_t tx_bd_flags;
45        #define TX_BD_FLAGS_CONN_FAULT                      (1<<0)
46        #define TX_BD_FLAGS_TCP_UDP_CKSUM                   (1<<1)
47        #define TX_BD_FLAGS_IP_CKSUM                        (1<<2)
48        #define TX_BD_FLAGS_VLAN_TAG                        (1<<3)
49        #define TX_BD_FLAGS_COAL_NOW                        (1<<4)
50        #define TX_BD_FLAGS_DONT_GEN_CRC                    (1<<5)
51        #define TX_BD_FLAGS_END                             (1<<6)
52        #define TX_BD_FLAGS_START                           (1<<7)
53        #define TX_BD_FLAGS_SW_OPTION_WORD                  (0x1f<<8)
54        #define TX_BD_FLAGS_SW_OPTION_MSB                   (1<<12)
55        #define TX_BD_FLAGS_SW_END                          (1<<12)
56        #define TX_BD_FLAGS_SW_FLAGS                        (1<<13)
57        #define TX_BD_FLAGS_SW_SNAP                         (1<<14)
58        #define TX_BD_FLAGS_SW_LSO                          (1<<15)
59
60} tx_bd_b_t;
61
62
63/*
64 *  tx_bd_l definition
65 */
66typedef struct tx_bd_l
67{
68    u32_t tx_bd_haddr_hi;
69    u32_t tx_bd_haddr_lo;
70    u16_t tx_bd_nbytes;
71    u16_t tx_bd_reserved;
72        #define TX_BD_RESERVED_MSS                          (0x3fff<<0)
73        #define TX_BD_RESERVED_BIT14_15                     (0x03<<14)
74    u16_t tx_bd_flags;
75        #define TX_BD_FLAGS_CONN_FAULT                      (1<<0)
76        #define TX_BD_FLAGS_TCP_UDP_CKSUM                   (1<<1)
77        #define TX_BD_FLAGS_IP_CKSUM                        (1<<2)
78        #define TX_BD_FLAGS_VLAN_TAG                        (1<<3)
79        #define TX_BD_FLAGS_COAL_NOW                        (1<<4)
80        #define TX_BD_FLAGS_DONT_GEN_CRC                    (1<<5)
81        #define TX_BD_FLAGS_END                             (1<<6)
82        #define TX_BD_FLAGS_START                           (1<<7)
83        #define TX_BD_FLAGS_SW_OPTION_WORD                  (0x1f<<8)
84        #define TX_BD_FLAGS_SW_OPTION_MSB                   (1<<12)
85        #define TX_BD_FLAGS_SW_END                          (1<<12)
86        #define TX_BD_FLAGS_SW_FLAGS                        (1<<13)
87        #define TX_BD_FLAGS_SW_SNAP                         (1<<14)
88        #define TX_BD_FLAGS_SW_LSO                          (1<<15)
89
90    u16_t tx_bd_vlan_tag;
91} tx_bd_l_t;
92
93
94/*
95 * tx_bd select
96 */
97#if defined(LITTLE_ENDIAN)
98    typedef tx_bd_l_t tx_bd_t;
99#elif defined(BIG_ENDIAN)
100    typedef tx_bd_b_t tx_bd_t;
101#endif
102
103
104/*
105 *  tx_bd_next definition
106 */
107typedef struct tx_bd_next
108{
109    u32_t tx_bd_next_paddr_hi;
110    u32_t tx_bd_next_paddr_lo;
111    u8_t tx_bd_next_reserved[8];
112} tx_bd_next_t;
113
114
115/*
116 *  hqc_basic_b definition
117 */
118typedef struct hqc_basic_b
119{
120    u8_t hqc_type;
121        #define HQC_TYPE_N64W                               (0xf<<0)
122        #define HQC_TYPE_VALUE                              (0xf<<4)
123            #define HQC_TYPE_VALUE_BASIC                    (0<<4)
124            #define HQC_TYPE_VALUE_TOE                      (1<<4)
125            #define HQC_TYPE_VALUE_HOLE                     (2<<4)
126            #define HQC_TYPE_VALUE_LSO_CAPTURE              (3<<4)
127            #define HQC_TYPE_VALUE_LSO_DUPLICATE            (4<<4)
128            #define HQC_TYPE_VALUE_IWARP_STD                (5<<4)
129            #define HQC_TYPE_VALUE_IWARP_EDGE               (6<<4)
130
131    u8_t hqc_knum;
132    u16_t hqc_hdr_nbytes;
133    u32_t unused_0;
134} hqc_basic_b_t;
135
136
137/*
138 *  hqc_basic_l definition
139 */
140typedef struct hqc_basic_l
141{
142    u16_t hqc_hdr_nbytes;
143    u8_t hqc_knum;
144    u8_t hqc_type;
145        #define HQC_TYPE_N64W                               (0xf<<0)
146        #define HQC_TYPE_VALUE                              (0xf<<4)
147            #define HQC_TYPE_VALUE_BASIC                    (0<<4)
148            #define HQC_TYPE_VALUE_TOE                      (1<<4)
149            #define HQC_TYPE_VALUE_HOLE                     (2<<4)
150            #define HQC_TYPE_VALUE_LSO_CAPTURE              (3<<4)
151            #define HQC_TYPE_VALUE_LSO_DUPLICATE            (4<<4)
152            #define HQC_TYPE_VALUE_IWARP_STD                (5<<4)
153            #define HQC_TYPE_VALUE_IWARP_EDGE               (6<<4)
154            #define HQC_TYPE_VALUE_ISCSI                    (7<<4)
155    u32_t unused_0;
156} hqc_basic_l_t;
157
158
159/*
160 * hqc_basic select
161 */
162#if defined(LITTLE_ENDIAN)
163    typedef hqc_basic_l_t hqc_basic_t;
164#elif defined(BIG_ENDIAN)
165    typedef hqc_basic_b_t hqc_basic_t;
166#endif
167
168
169/*
170 *  hqc_toe_b definition
171 */
172typedef struct hqc_toe_b
173{
174    u8_t hqt_type;
175    u8_t hqt_knum;
176    u16_t hqt_hdr_nbytes;
177        #define HQT_HDR_NBYTES_VALUE                        (0x3fff<<0)
178        #define HQT_HDR_NBYTES_PLUS_TWO                     (1<<15)
179
180    u16_t unused_0;
181    u16_t hqt_xsum_boff;
182} hqc_toe_b_t;
183
184
185/*
186 *  hqc_toe_l definition
187 */
188typedef struct hqc_toe_l
189{
190    u16_t hqt_hdr_nbytes;
191        #define HQT_HDR_NBYTES_VALUE                        (0x3fff<<0)
192        #define HQT_HDR_NBYTES_PLUS_TWO                     (1<<15)
193
194    u8_t hqt_knum;
195    u8_t hqt_type;
196    u16_t hqt_xsum_boff;
197    u16_t unused_0;
198} hqc_toe_l_t;
199
200
201/*
202 * hqc_toe select
203 */
204#if defined(LITTLE_ENDIAN)
205    typedef hqc_toe_l_t hqc_toe_t;
206#elif defined(BIG_ENDIAN)
207    typedef hqc_toe_b_t hqc_toe_t;
208#endif
209
210
211/*
212 *  hqc_hole_b definition
213 */
214typedef struct hqc_hole_b
215{
216    u8_t hqh_type;
217    u8_t hqh_knum;
218    u16_t hqh_hdr_nbytes;
219        #define HQH_HDR_NBYTES_VALUE                        (0x3fff<<0)
220        #define HQH_HDR_NBYTES_PLUS_TWO                     (1<<15)
221
222    u16_t hqh_hole_bytes;
223    u16_t hqh_hole_pos;
224    u8_t hqh_value[4];
225    u32_t unused_0;
226} hqc_hole_b_t;
227
228
229/*
230 *  hqc_hole_l definition
231 */
232typedef struct hqc_hole_l
233{
234    u16_t hqh_hdr_nbytes;
235        #define HQH_HDR_NBYTES_VALUE                        (0x3fff<<0)
236        #define HQH_HDR_NBYTES_PLUS_TWO                     (1<<15)
237
238    u8_t hqh_knum;
239    u8_t hqh_type;
240    u16_t hqh_hole_pos;
241    u16_t hqh_hole_bytes;
242    u8_t hqh_value[4];
243    u32_t unused_0;
244} hqc_hole_l_t;
245
246
247/*
248 * hqc_hole select
249 */
250#if defined(LITTLE_ENDIAN)
251    typedef hqc_hole_l_t hqc_hole_t;
252#elif defined(BIG_ENDIAN)
253    typedef hqc_hole_b_t hqc_hole_t;
254#endif
255
256
257/*
258 *  hqc_lso_cap_b definition
259 */
260typedef struct hqc_lso_cap_b
261{
262    u8_t hqca_type;
263    u8_t hqca_knum;
264    u16_t hqca_hdr_nbytes;
265        #define HQCA_HDR_NBYTES_VALUE                       (0x3fff<<0)
266        #define HQCA_HDR_NBYTES_PLUS_TWO                    (1<<15)
267
268    u16_t hqca_cap_hdr_nbytes;
269    u16_t hqca_l2hdr_nbytes;
270    u32_t hqca_vlan_tag;
271    u32_t hqca_ipv6_exthdr_len;
272        #define HQDU_FLAGS_IPV6_EXTHDR_LEN                  (0x7fffffffUL<<0)
273        #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT              (1UL<<31)
274} hqc_lso_cap_b_t;
275
276
277/*
278 *  hqc_lso_cap_l definition
279 */
280typedef struct hqc_lso_cap_l
281{
282    u16_t hqca_hdr_nbytes;
283        #define HQCA_HDR_NBYTES_VALUE                       (0x3fff<<0)
284        #define HQCA_HDR_NBYTES_PLUS_TWO                    (1<<15)
285
286    u8_t hqca_knum;
287    u8_t hqca_type;
288    u16_t hqca_l2hdr_nbytes;
289    u16_t hqca_cap_hdr_nbytes;
290    u32_t hqca_vlan_tag;
291    u32_t hqca_ipv6_exthdr_len;
292        #define HQDU_FLAGS_IPV6_EXTHDR_LEN                  (0x7fffffffUL<<0)
293        #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT              (1UL<<31)
294} hqc_lso_cap_l_t;
295
296
297/*
298 * hqc_lso_cap select
299 */
300#if defined(LITTLE_ENDIAN)
301    typedef hqc_lso_cap_l_t hqc_lso_cap_t;
302#elif defined(BIG_ENDIAN)
303    typedef hqc_lso_cap_b_t hqc_lso_cap_t;
304#endif
305
306
307/*
308 *  hqc_lso_dup_b definition
309 */
310typedef struct hqc_lso_dup_b
311{
312    u8_t hqdu_type;
313    u8_t hqdu_knum;
314    u16_t hqdu_hdr_nbytes;
315        #define HQDU_HDR_NBYTES_VALUE                       (0x3fff<<0)
316        #define HQDU_HDR_NBYTES_PLUS_TWO                    (1<<15)
317
318    u32_t hqdu_flags_bseq;
319        #define HQDU_FLAGS_BSEQ_BSEQ_VALUE                  (0x7fffffffUL<<0)
320        #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT              (1UL<<31)
321
322} hqc_lso_dup_b_t;
323
324
325/*
326 *  hqc_lso_dup_l definition
327 */
328typedef struct hqc_lso_dup_l
329{
330    u16_t hqdu_hdr_nbytes;
331        #define HQDU_HDR_NBYTES_VALUE                       (0x3fff<<0)
332        #define HQDU_HDR_NBYTES_PLUS_TWO                    (1<<15)
333
334    u8_t hqdu_knum;
335    u8_t hqdu_type;
336    u32_t hqdu_flags_bseq;
337        #define HQDU_FLAGS_BSEQ_BSEQ_VALUE                  (0x7fffffffUL<<0)
338        #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT              (1UL<<31)
339
340} hqc_lso_dup_l_t;
341
342
343/*
344 * hqc_lso_dup select
345 */
346#if defined(LITTLE_ENDIAN)
347    typedef hqc_lso_dup_l_t hqc_lso_dup_t;
348#elif defined(BIG_ENDIAN)
349    typedef hqc_lso_dup_b_t hqc_lso_dup_t;
350#endif
351
352
353/*
354 *  hqc_iwarp_std_b definition
355 */
356typedef struct hqc_iwarp_std_b
357{
358    u8_t hqis_type;
359    u8_t hqis_knum;
360    u16_t hqis_hdr_nbytes;
361        #define HQIS_HDR_NBYTES_HDR_NBYTES_VALUE            (0x3fff<<0)
362
363    u16_t hqis_l5_hdr_nbytes;
364    u16_t hqis_xsum_boff;
365} hqc_iwarp_std_b_t;
366
367
368/*
369 *  hqc_iwarp_std_l definition
370 */
371typedef struct hqc_iwarp_std_l
372{
373    u16_t hqis_hdr_nbytes;
374        #define HQIS_HDR_NBYTES_HDR_NBYTES_VALUE            (0x3fff<<0)
375
376    u8_t hqis_knum;
377    u8_t hqis_type;
378    u16_t hqis_xsum_boff;
379    u16_t hqis_l5_hdr_nbytes;
380} hqc_iwarp_std_l_t;
381
382
383/*
384 * hqc_iwarp_std select
385 */
386#if defined(LITTLE_ENDIAN)
387    typedef hqc_iwarp_std_l_t hqc_iwarp_std_t;
388#elif defined(BIG_ENDIAN)
389    typedef hqc_iwarp_std_b_t hqc_iwarp_std_t;
390#endif
391
392
393/*
394 *  hqc_iwarp_edge_b definition
395 */
396typedef struct hqc_iwarp_edge_b
397{
398    u8_t hqie_type;
399    u8_t hqie_knum;
400    u16_t hqie_hdr_nbytes;
401        #define HQIE_HDR_NBYTES_HDR_NBYTES_VALUE            (0x3fff<<0)
402
403    u16_t hqie_l5_hdr_nbytes;
404    u16_t hqie_xsum_boff;
405    u32_t hqie_marker_value;
406    u32_t unused_0;
407} hqc_iwarp_edge_b_t;
408
409
410/*
411 *  hqc_iwarp_edge_l definition
412 */
413typedef struct hqc_iwarp_edge_l
414{
415    u16_t hqie_hdr_nbytes;
416        #define HQIE_HDR_NBYTES_HDR_NBYTES_VALUE            (0x3fff<<0)
417
418    u8_t hqie_knum;
419    u8_t hqie_type;
420    u16_t hqie_xsum_boff;
421    u16_t hqie_l5_hdr_nbytes;
422    u32_t hqie_marker_value;
423    u32_t unused_0;
424} hqc_iwarp_edge_l_t;
425
426
427/*
428 * hqc_iwarp_edge select
429 */
430#if defined(LITTLE_ENDIAN)
431    typedef hqc_iwarp_edge_l_t hqc_iwarp_edge_t;
432#elif defined(BIG_ENDIAN)
433    typedef hqc_iwarp_edge_b_t hqc_iwarp_edge_t;
434#endif
435
436
437/*
438 *  rx_bd_b definition
439 */
440typedef struct rx_bd_b
441{
442    u32_t rx_bd_haddr_hi;
443    u32_t rx_bd_haddr_lo;
444    u32_t rx_bd_len;
445    u16_t unused_0;
446    u16_t rx_bd_flags;
447        #define RX_BD_FLAGS_NOPUSH                          (1<<0)
448        #define RX_BD_FLAGS_DUMMY                           (1<<1)
449        #define RX_BD_FLAGS_END                             (1<<2)
450        #define RX_BD_FLAGS_START                           (1<<3)
451        #define RX_BD_FLAGS_INTRMDT                         (1<<4)       // intermediate boundary for partial io buffer
452        #define RX_BD_FLAGS_HEADERSPLIT                     (1<<5)
453} rx_bd_b_t;
454
455
456/*
457 *  rx_bd_l definition
458 */
459typedef struct rx_bd_l
460{
461    u32_t rx_bd_haddr_hi;
462    u32_t rx_bd_haddr_lo;
463    u32_t rx_bd_len;
464    u16_t rx_bd_flags;
465        #define RX_BD_FLAGS_NOPUSH                          (1<<0)
466        #define RX_BD_FLAGS_DUMMY                           (1<<1)
467        #define RX_BD_FLAGS_END                             (1<<2)
468        #define RX_BD_FLAGS_START                           (1<<3)
469        #define RX_BD_FLAGS_INTRMDT                         (1<<4)       // intermediate boundary for partial io buffer
470        #define RX_BD_FLAGS_HEADERSPLIT                     (1<<5)
471    u16_t unused_0;
472} rx_bd_l_t;
473
474
475/*
476 * rx_bd select
477 */
478#if defined(LITTLE_ENDIAN)
479    typedef rx_bd_l_t rx_bd_t;
480#elif defined(BIG_ENDIAN)
481    typedef rx_bd_b_t rx_bd_t;
482#endif
483
484
485/*
486 *  rx_generic_bd_b definition
487 */
488typedef struct rx_generic_bd_b
489{
490    u16_t rx_generic_bd_tag;
491    u16_t rx_generic_bd_haddr_hi;
492    u32_t rx_generic_bd_haddr_lo;
493        #define RX_GENERIC_BD_HADDR_LO_SELECT               (0x3UL<<0)
494        #define RX_GENERIC_BD_HADDR_LO_ADDR                 (0x3fffUL<<2)
495
496    u32_t rx_generic_bd_len;
497    u16_t unused_0;
498    u16_t rx_generic_bd_flags;
499        #define RX_GENERIC_BD_FLAGS_END                     (1<<2)
500        #define RX_GENERIC_BD_FLAGS_START                   (1<<3)
501
502} rx_generic_bd_b_t;
503
504
505/*
506 *  rx_generic_bd_l definition
507 */
508typedef struct rx_generic_bd_l
509{
510    u16_t rx_generic_bd_haddr_hi;
511    u16_t rx_generic_bd_tag;
512    u32_t rx_generic_bd_haddr_lo;
513        #define RX_GENERIC_BD_HADDR_LO_SELECT               (0x3UL<<0)
514        #define RX_GENERIC_BD_HADDR_LO_ADDR                 (0x3fffUL<<2)
515
516    u32_t rx_generic_bd_len;
517    u16_t rx_generic_bd_flags;
518        #define RX_GENERIC_BD_FLAGS_END                     (1<<2)
519        #define RX_GENERIC_BD_FLAGS_START                   (1<<3)
520
521    u16_t unused_0;
522} rx_generic_bd_l_t;
523
524
525/*
526 * rx_generic_bd select
527 */
528#if defined(LITTLE_ENDIAN)
529    typedef rx_generic_bd_l_t rx_generic_bd_t;
530#elif defined(BIG_ENDIAN)
531    typedef rx_generic_bd_b_t rx_generic_bd_t;
532#endif
533
534
535/*
536 *  attentions definition
537 */
538typedef struct attentions
539{
540    u32_t attentions_bits;
541        #define ATTENTIONS_BITS_LINK_STATE                  (1UL<<0)
542        #define ATTENTIONS_BITS_TX_SCHEDULER_ABORT          (1UL<<1)
543        #define ATTENTIONS_BITS_TX_BD_READ_ABORT            (1UL<<2)
544        #define ATTENTIONS_BITS_TX_BD_CACHE_ABORT           (1UL<<3)
545        #define ATTENTIONS_BITS_TX_PROCESSOR_ABORT          (1UL<<4)
546        #define ATTENTIONS_BITS_TX_DMA_ABORT                (1UL<<5)
547        #define ATTENTIONS_BITS_TX_PATCHUP_ABORT            (1UL<<6)
548        #define ATTENTIONS_BITS_TX_ASSEMBLER_ABORT          (1UL<<7)
549        #define ATTENTIONS_BITS_RX_PARSER_MAC_ABORT         (1UL<<8)
550        #define ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT     (1UL<<9)
551        #define ATTENTIONS_BITS_RX_MBUF_ABORT               (1UL<<10)
552        #define ATTENTIONS_BITS_RX_LOOKUP_ABORT             (1UL<<11)
553        #define ATTENTIONS_BITS_RX_PROCESSOR_ABORT          (1UL<<12)
554        #define ATTENTIONS_BITS_RX_V2P_ABORT                (1UL<<13)
555        #define ATTENTIONS_BITS_RX_BD_CACHE_ABORT           (1UL<<14)
556        #define ATTENTIONS_BITS_RX_DMA_ABORT                (1UL<<15)
557        #define ATTENTIONS_BITS_COMPLETION_ABORT            (1UL<<16)
558        #define ATTENTIONS_BITS_HOST_COALESCE_ABORT         (1UL<<17)
559        #define ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT         (1UL<<18)
560        #define ATTENTIONS_BITS_CONTEXT_ABORT               (1UL<<19)
561        #define ATTENTIONS_BITS_CMD_SCHEDULER_ABORT         (1UL<<20)
562        #define ATTENTIONS_BITS_CMD_PROCESSOR_ABORT         (1UL<<21)
563        #define ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT        (1UL<<22)
564        #define ATTENTIONS_BITS_MAC_ABORT                   (1UL<<23)
565        #define ATTENTIONS_BITS_TIMER_ABORT                 (1UL<<24)
566        #define ATTENTIONS_BITS_DMAE_ABORT                  (1UL<<25)
567        #define ATTENTIONS_BITS_FLSH_ABORT                  (1UL<<26)
568        #define ATTENTIONS_BITS_GRC_ABORT                   (1UL<<27)
569        #define ATTENTIONS_BITS_EPB_ERROR                   (1UL<<30)
570        #define ATTENTIONS_BITS_PARITY_ERROR                (1UL<<31)
571
572} attentions_t;
573
574
575/*
576 *  status_block_b definition
577 */
578typedef struct status_block_b
579{
580    u32_t status_attn_bits;
581        #define STATUS_ATTN_BITS_LINK_STATE                 (1UL<<0)
582        #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT         (1UL<<1)
583        #define STATUS_ATTN_BITS_TX_BD_READ_ABORT           (1UL<<2)
584        #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT          (1UL<<3)
585        #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT         (1UL<<4)
586        #define STATUS_ATTN_BITS_TX_DMA_ABORT               (1UL<<5)
587        #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT           (1UL<<6)
588        #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT         (1UL<<7)
589        #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT        (1UL<<8)
590        #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT    (1UL<<9)
591        #define STATUS_ATTN_BITS_RX_MBUF_ABORT              (1UL<<10)
592        #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT            (1UL<<11)
593        #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT         (1UL<<12)
594        #define STATUS_ATTN_BITS_RX_V2P_ABORT               (1UL<<13)
595        #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT          (1UL<<14)
596        #define STATUS_ATTN_BITS_RX_DMA_ABORT               (1UL<<15)
597        #define STATUS_ATTN_BITS_COMPLETION_ABORT           (1UL<<16)
598        #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT        (1UL<<17)
599        #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT        (1UL<<18)
600        #define STATUS_ATTN_BITS_CONTEXT_ABORT              (1UL<<19)
601        #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT        (1UL<<20)
602        #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT        (1UL<<21)
603        #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT       (1UL<<22)
604        #define STATUS_ATTN_BITS_MAC_ABORT                  (1UL<<23)
605        #define STATUS_ATTN_BITS_TIMER_ABORT                (1UL<<24)
606        #define STATUS_ATTN_BITS_DMAE_ABORT                 (1UL<<25)
607        #define STATUS_ATTN_BITS_FLSH_ABORT                 (1UL<<26)
608        #define STATUS_ATTN_BITS_GRC_ABORT                  (1UL<<27)
609        #define STATUS_ATTN_BITS_EPB_ERROR                  (1UL<<30)
610        #define STATUS_ATTN_BITS_PARITY_ERROR               (1UL<<31)
611
612    u32_t status_attn_bits_ack;
613    u16_t status_tx_quick_consumer_index0;
614    u16_t status_tx_quick_consumer_index1;
615    u16_t status_tx_quick_consumer_index2;
616    u16_t status_tx_quick_consumer_index3;
617    u16_t status_rx_quick_consumer_index0;
618    u16_t status_rx_quick_consumer_index1;
619    u16_t status_rx_quick_consumer_index2;
620    u16_t status_rx_quick_consumer_index3;
621    u16_t status_rx_quick_consumer_index4;
622    u16_t status_rx_quick_consumer_index5;
623    u16_t status_rx_quick_consumer_index6;
624    u16_t status_rx_quick_consumer_index7;
625    u16_t status_rx_quick_consumer_index8;
626    u16_t status_rx_quick_consumer_index9;
627    u16_t status_rx_quick_consumer_index10;
628    u16_t status_rx_quick_consumer_index11;
629    u16_t status_rx_quick_consumer_index12;
630    u16_t status_rx_quick_consumer_index13;
631    u16_t status_rx_quick_consumer_index14;
632    u16_t status_rx_quick_consumer_index15;
633    u16_t status_completion_producer_index;
634    u16_t status_cmd_consumer_index;
635    u16_t status_idx;
636    u8_t unused_0;
637    u8_t status_blk_num;
638    u32_t unused_1[2];
639    #if (STATUS_BLOCK_SPACING > 64)
640    u32_t unused_z[STATUS_BLOCK_SPACING/4-64/4];
641    #endif
642
643} status_block_b_t;
644
645
646/*
647 *  status_block_l definition
648 */
649typedef struct status_block_l
650{
651    u32_t status_attn_bits;
652        #define STATUS_ATTN_BITS_LINK_STATE                 (1UL<<0)
653        #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT         (1UL<<1)
654        #define STATUS_ATTN_BITS_TX_BD_READ_ABORT           (1UL<<2)
655        #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT          (1UL<<3)
656        #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT         (1UL<<4)
657        #define STATUS_ATTN_BITS_TX_DMA_ABORT               (1UL<<5)
658        #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT           (1UL<<6)
659        #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT         (1UL<<7)
660        #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT        (1UL<<8)
661        #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT    (1UL<<9)
662        #define STATUS_ATTN_BITS_RX_MBUF_ABORT              (1UL<<10)
663        #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT            (1UL<<11)
664        #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT         (1UL<<12)
665        #define STATUS_ATTN_BITS_RX_V2P_ABORT               (1UL<<13)
666        #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT          (1UL<<14)
667        #define STATUS_ATTN_BITS_RX_DMA_ABORT               (1UL<<15)
668        #define STATUS_ATTN_BITS_COMPLETION_ABORT           (1UL<<16)
669        #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT        (1UL<<17)
670        #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT        (1UL<<18)
671        #define STATUS_ATTN_BITS_CONTEXT_ABORT              (1UL<<19)
672        #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT        (1UL<<20)
673        #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT        (1UL<<21)
674        #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT       (1UL<<22)
675        #define STATUS_ATTN_BITS_MAC_ABORT                  (1UL<<23)
676        #define STATUS_ATTN_BITS_TIMER_ABORT                (1UL<<24)
677        #define STATUS_ATTN_BITS_DMAE_ABORT                 (1UL<<25)
678        #define STATUS_ATTN_BITS_FLSH_ABORT                 (1UL<<26)
679        #define STATUS_ATTN_BITS_GRC_ABORT                  (1UL<<27)
680        #define STATUS_ATTN_BITS_EPB_ERROR                  (1UL<<30)
681        #define STATUS_ATTN_BITS_PARITY_ERROR               (1UL<<31)
682
683    u32_t status_attn_bits_ack;
684    u16_t status_tx_quick_consumer_index1;
685    u16_t status_tx_quick_consumer_index0;
686    u16_t status_tx_quick_consumer_index3;
687    u16_t status_tx_quick_consumer_index2;
688    u16_t status_rx_quick_consumer_index1;
689    u16_t status_rx_quick_consumer_index0;
690    u16_t status_rx_quick_consumer_index3;
691    u16_t status_rx_quick_consumer_index2;
692    u16_t status_rx_quick_consumer_index5;
693    u16_t status_rx_quick_consumer_index4;
694    u16_t status_rx_quick_consumer_index7;
695    u16_t status_rx_quick_consumer_index6;
696    u16_t status_rx_quick_consumer_index9;
697    u16_t status_rx_quick_consumer_index8;
698    u16_t status_rx_quick_consumer_index11;
699    u16_t status_rx_quick_consumer_index10;
700    u16_t status_rx_quick_consumer_index13;
701    u16_t status_rx_quick_consumer_index12;
702    u16_t status_rx_quick_consumer_index15;
703    u16_t status_rx_quick_consumer_index14;
704    u16_t status_cmd_consumer_index;
705    u16_t status_completion_producer_index;
706    u8_t status_blk_num;
707    u8_t unused_0;
708    u16_t status_idx;
709    u32_t unused_1[2];
710    #if (STATUS_BLOCK_SPACING > 64)
711    u32_t unused_z[STATUS_BLOCK_SPACING/4-64/4];
712    #endif
713
714} status_block_l_t;
715
716
717/*
718 * status_block select
719 */
720#if defined(LITTLE_ENDIAN)
721    typedef status_block_l_t status_block_t;
722#elif defined(BIG_ENDIAN)
723    typedef status_block_b_t status_block_t;
724#endif
725
726
727/*
728 *  status_per_cpu_block_b definition
729 */
730typedef struct status_per_cpu_block_b
731{
732    u16_t status_pcpu_tx_quick_consumer_index;
733    u16_t status_pcpu_rx_quick_consumer_index;
734    u16_t status_pcpu_completion_producer_index;
735    u16_t status_pcpu_cmd_consumer_index;
736    u32_t unused_0;
737    u16_t status_pcpu_idx;
738    u8_t unused_1;
739    u8_t status_pcpu_blk_num;
740    u32_t unused_z[STATUS_BLOCK_SPACING/4-16/4];
741
742} status_per_cpu_block_b_t;
743
744
745/*
746 *  status_per_cpu_block_l definition
747 */
748typedef struct status_per_cpu_block_l
749{
750    u16_t status_pcpu_rx_quick_consumer_index;
751    u16_t status_pcpu_tx_quick_consumer_index;
752    u16_t status_pcpu_cmd_consumer_index;
753    u16_t status_pcpu_completion_producer_index;
754    u32_t unused_0;
755    u8_t status_pcpu_blk_num;
756    u8_t unused_1;
757    u16_t status_pcpu_idx;
758    u32_t unused_z[STATUS_BLOCK_SPACING/4-16/4];
759
760} status_per_cpu_block_l_t;
761
762
763/*
764 * status_per_cpu_block select
765 */
766#if defined(LITTLE_ENDIAN)
767    typedef status_per_cpu_block_l_t status_per_cpu_block_t;
768#elif defined(BIG_ENDIAN)
769    typedef status_per_cpu_block_b_t status_per_cpu_block_t;
770#endif
771
772
773/*
774 *  status_blk_combined definition
775 */
776typedef struct status_blk_combined
777{
778    status_block_t deflt;
779    status_per_cpu_block_t proc[8];
780} status_blk_combined_t;
781
782
783/*
784 *  statistics_block definition
785 */
786typedef struct statistics_block
787{
788    u32_t stat_IfHCInOctets_hi;
789    u32_t stat_IfHCInOctets_lo;
790    u32_t stat_IfHCInBadOctets_hi;
791    u32_t stat_IfHCInBadOctets_lo;
792    u32_t stat_IfHCOutOctets_hi;
793    u32_t stat_IfHCOutOctets_lo;
794    u32_t stat_IfHCOutBadOctets_hi;
795    u32_t stat_IfHCOutBadOctets_lo;
796    u32_t stat_IfHCInUcastPkts_hi;
797    u32_t stat_IfHCInUcastPkts_lo;
798    u32_t stat_IfHCInMulticastPkts_hi;
799    u32_t stat_IfHCInMulticastPkts_lo;
800    u32_t stat_IfHCInBroadcastPkts_hi;
801    u32_t stat_IfHCInBroadcastPkts_lo;
802    u32_t stat_IfHCOutUcastPkts_hi;
803    u32_t stat_IfHCOutUcastPkts_lo;
804    u32_t stat_IfHCOutMulticastPkts_hi;
805    u32_t stat_IfHCOutMulticastPkts_lo;
806    u32_t stat_IfHCOutBroadcastPkts_hi;
807    u32_t stat_IfHCOutBroadcastPkts_lo;
808    u32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
809    u32_t stat_Dot3StatsCarrierSenseErrors;
810    u32_t stat_Dot3StatsFCSErrors;
811    u32_t stat_Dot3StatsAlignmentErrors;
812    u32_t stat_Dot3StatsSingleCollisionFrames;
813    u32_t stat_Dot3StatsMultipleCollisionFrames;
814    u32_t stat_Dot3StatsDeferredTransmissions;
815    u32_t stat_Dot3StatsExcessiveCollisions;
816    u32_t stat_Dot3StatsLateCollisions;
817    u32_t stat_EtherStatsCollisions;
818    u32_t stat_EtherStatsFragments;
819    u32_t stat_EtherStatsJabbers;
820    u32_t stat_EtherStatsUndersizePkts;
821    u32_t stat_EtherStatsOverrsizePkts;
822    u32_t stat_EtherStatsPktsRx64Octets;
823    u32_t stat_EtherStatsPktsRx65Octetsto127Octets;
824    u32_t stat_EtherStatsPktsRx128Octetsto255Octets;
825    u32_t stat_EtherStatsPktsRx256Octetsto511Octets;
826    u32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
827    u32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
828    u32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
829    u32_t stat_EtherStatsPktsTx64Octets;
830    u32_t stat_EtherStatsPktsTx65Octetsto127Octets;
831    u32_t stat_EtherStatsPktsTx128Octetsto255Octets;
832    u32_t stat_EtherStatsPktsTx256Octetsto511Octets;
833    u32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
834    u32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
835    u32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
836    u32_t stat_XonPauseFramesReceived;
837    u32_t stat_XoffPauseFramesReceived;
838    u32_t stat_OutXonSent;
839    u32_t stat_OutXoffSent;
840    u32_t stat_FlowControlDone;
841    u32_t stat_MacControlFramesReceived;
842    u32_t stat_XoffStateEntered;
843    u32_t stat_IfInFramesL2FilterDiscards;
844    u32_t stat_IfInRuleCheckerDiscards;
845    u32_t stat_IfInFTQDiscards;
846    u32_t stat_IfInMBUFDiscards;
847    u32_t stat_IfInRuleCheckerP4Hit;
848    u32_t stat_CatchupInRuleCheckerDiscards;
849    u32_t stat_CatchupInFTQDiscards;
850    u32_t stat_CatchupInMBUFDiscards;
851    u32_t stat_CatchupInRuleCheckerP4Hit;
852    u32_t stat_GenStat00;
853    u32_t stat_GenStat01;
854    u32_t stat_GenStat02;
855    u32_t stat_GenStat03;
856    u32_t stat_GenStat04;
857    u32_t stat_GenStat05;
858    u32_t stat_GenStat06;
859    u32_t stat_GenStat07;
860    u32_t stat_GenStat08;
861    u32_t stat_GenStat09;
862    u32_t stat_GenStat10;
863    u32_t stat_GenStat11;
864    u32_t stat_GenStat12;
865    u32_t stat_GenStat13;
866    u32_t stat_GenStat14;
867    u32_t stat_GenStat15;
868} statistics_block_t;
869
870
871/*
872 *  l2_fhdr_b definition
873 */
874typedef struct l2_fhdr_b
875{
876    u16_t l2_fhdr_errors;
877        #define L2_FHDR_ERRORS_ABORT_PKT                    (1<<0)
878        #define L2_FHDR_ERRORS_BAD_CRC                      (1<<1)
879        #define L2_FHDR_ERRORS_PHY_DECODE                   (1<<2)
880        #define L2_FHDR_ERRORS_ALIGNMENT                    (1<<3)
881        #define L2_FHDR_ERRORS_TOO_SHORT                    (1<<4)
882        #define L2_FHDR_ERRORS_GIANT_FRAME                  (1<<5)
883        #define L2_FHDR_ERRORS_IP_BAD_XSUM                  (1<<10)
884        #define L2_FHDR_ERRORS_TCP_BAD_XSUM                 (1<<12)
885        #define L2_FHDR_ERRORS_UDP_BAD_XSUM                 (1<<15)
886
887    u16_t l2_fhdr_status;
888        #define L2_FHDR_STATUS_RULE_CLASS                   (0x7<<0)
889        #define L2_FHDR_STATUS_RULE_P2                      (1<<3)
890        #define L2_FHDR_STATUS_RULE_P3                      (1<<4)
891        #define L2_FHDR_STATUS_RULE_P4                      (1<<5)
892        #define L2_FHDR_STATUS_L2_VLAN_TAG                  (1<<6)
893        #define L2_FHDR_STATUS_L2_LLC_SNAP                  (1<<7)
894        #define L2_FHDR_STATUS_RSS_HASH                     (1<<8)
895        #define L2_FHDR_STATUS_IP_DATAGRAM                  (1<<13)
896        #define L2_FHDR_STATUS_TCP_SEGMENT                  (1<<14)
897        #define L2_FHDR_STATUS_UDP_DATAGRAM                 (1<<15)
898
899    u32_t l2_fhdr_hash;
900    u16_t l2_fhdr_pkt_len;
901    u16_t l2_fhdr_vlan_tag;
902    u16_t l2_fhdr_ip_xsum;
903    u16_t l2_fhdr_tcp_udp_xsum;
904} l2_fhdr_b_t;
905
906
907/*
908 *  l2_fhdr_l definition
909 */
910typedef struct l2_fhdr_l
911{
912    u16_t l2_fhdr_status;
913        #define L2_FHDR_STATUS_RULE_CLASS                   (0x7<<0)
914        #define L2_FHDR_STATUS_RULE_P2                      (1<<3)
915        #define L2_FHDR_STATUS_RULE_P3                      (1<<4)
916        #define L2_FHDR_STATUS_RULE_P4                      (1<<5)
917        #define L2_FHDR_STATUS_L2_VLAN_TAG                  (1<<6)
918        #define L2_FHDR_STATUS_L2_LLC_SNAP                  (1<<7)
919        #define L2_FHDR_STATUS_RSS_HASH                     (1<<8)
920        #define L2_FHDR_STATUS_IP_DATAGRAM                  (1<<13)
921        #define L2_FHDR_STATUS_TCP_SEGMENT                  (1<<14)
922        #define L2_FHDR_STATUS_UDP_DATAGRAM                 (1<<15)
923
924    u16_t l2_fhdr_errors;
925        #define L2_FHDR_ERRORS_ABORT_PKT                    (1<<0)
926        #define L2_FHDR_ERRORS_BAD_CRC                      (1<<1)
927        #define L2_FHDR_ERRORS_PHY_DECODE                   (1<<2)
928        #define L2_FHDR_ERRORS_ALIGNMENT                    (1<<3)
929        #define L2_FHDR_ERRORS_TOO_SHORT                    (1<<4)
930        #define L2_FHDR_ERRORS_GIANT_FRAME                  (1<<5)
931        #define L2_FHDR_ERRORS_IP_BAD_XSUM                  (1<<10)
932        #define L2_FHDR_ERRORS_TCP_BAD_XSUM                 (1<<12)
933        #define L2_FHDR_ERRORS_UDP_BAD_XSUM                 (1<<15)
934
935    u32_t l2_fhdr_hash;
936    u16_t l2_fhdr_vlan_tag;
937    u16_t l2_fhdr_pkt_len;
938    u16_t l2_fhdr_tcp_udp_xsum;
939    u16_t l2_fhdr_ip_xsum;
940} l2_fhdr_l_t;
941
942
943/*
944 * l2_fhdr select
945 */
946#if defined(LITTLE_ENDIAN)
947    typedef l2_fhdr_l_t l2_fhdr_t;
948#elif defined(BIG_ENDIAN)
949    typedef l2_fhdr_b_t l2_fhdr_t;
950#endif
951
952/*
953 *  l2_fhdr_ooo_b definition
954 */
955typedef struct l2_fhdr_ooo_b
956{
957    u8_t  l2_fhdr_block_idx;
958    u8_t  l2_fhdr_opcode;
959        #define L2_FHDR_OPCODE_ADD_PEN         (0)
960        #define L2_FHDR_OPCODE_ADD_NEW         (1)
961        #define L2_FHDR_OPCODE_ADD_RIGHT       (2)
962        #define L2_FHDR_OPCODE_ADD_LEFT        (3)
963        #define L2_FHDR_OPCODE_JOIN            (4)
964        #define L2_FHDR_OPCODE_NOOP            (5)
965        #define L2_FHDR_OPCODE_CLEAN_UP        (10)
966    u8_t  l2_fhdr_drop_size;
967    u8_t  l2_fhdr_drop_block_idx;
968    u32_t l2_fhdr_icid;
969
970    u16_t l2_fhdr_pkt_len;
971    u16_t l2_fhdr_vlan_tag;
972    u16_t l2_fhdr_ip_xsum;
973    u16_t l2_fhdr_tcp_udp_xsum;
974} l2_fhdr_ooo_b_t;
975
976
977/*
978 *  l2_fhdr_ooo_l definition
979 */
980typedef struct l2_fhdr_ooo_l
981{
982    u8_t  l2_fhdr_drop_block_idx;
983    u8_t  l2_fhdr_drop_size;
984    u8_t  l2_fhdr_opcode;
985    u8_t  l2_fhdr_block_idx;
986    u32_t l2_fhdr_icid;
987
988    u16_t l2_fhdr_vlan_tag;
989    u16_t l2_fhdr_pkt_len;
990    u16_t l2_fhdr_tcp_udp_xsum;
991    u16_t l2_fhdr_ip_xsum;
992} l2_fhdr_ooo_l_t;
993
994/*
995 * l2_fhdr_ooo select
996 */
997#if defined(LITTLE_ENDIAN)
998    typedef l2_fhdr_ooo_l_t l2_fhdr_ooo_t;
999#elif defined(BIG_ENDIAN)
1000    typedef l2_fhdr_ooo_b_t l2_fhdr_ooo_t;
1001#endif
1002
1003/*
1004 *  pci_config definition
1005 *  offset: 0000
1006 */
1007typedef struct pci_config
1008{
1009    u16_t pcicfg_vendor_id;
1010    u16_t pcicfg_device_id;
1011    u16_t pcicfg_command;
1012        #define PCICFG_COMMAND_IO_SPACE                     (1<<0)
1013        #define PCICFG_COMMAND_MEM_SPACE                    (1<<1)
1014        #define PCICFG_COMMAND_BUS_MASTER                   (1<<2)
1015        #define PCICFG_COMMAND_SPECIAL_CYCLES               (1<<3)
1016        #define PCICFG_COMMAND_MWI_CYCLES                   (1<<4)
1017        #define PCICFG_COMMAND_VGA_SNOOP                    (1<<5)
1018        #define PCICFG_COMMAND_PERR_ENA                     (1<<6)
1019        #define PCICFG_COMMAND_STEPPING                     (1<<7)
1020        #define PCICFG_COMMAND_SERR_ENA                     (1<<8)
1021        #define PCICFG_COMMAND_FAST_B2B                     (1<<9)
1022        #define PCICFG_COMMAND_INT_DISABLE                  (1<<10)
1023        #define PCICFG_COMMAND_RESERVED                     (0x1f<<11)
1024
1025    u16_t pcicfg_status;
1026        #define PCICFG_STATUS_RESERVED1                     (0x7<<0)
1027        #define PCICFG_STATUS_INT_STATUS                    (1<<3)
1028        #define PCICFG_STATUS_CAP_LIST                      (1<<4)
1029        #define PCICFG_STATUS_66MHZ_CAP                     (1<<5)
1030        #define PCICFG_STATUS_RESERVED2                     (1<<6)
1031        #define PCICFG_STATUS_FAST_B2B_CAP                  (1<<7)
1032        #define PCICFG_STATUS_SIG_PERR_TE                      (1<<8)
1033        #define PCICFG_STATUS_MSTR_PERR_XI                     (1<<8)
1034        #define PCICFG_STATUS_DEVSEL_TIMING                 (0x3<<9)
1035        #define PCICFG_STATUS_SIG_TGT_ABT                   (1<<11)
1036        #define PCICFG_STATUS_RCV_TGT_ABT                   (1<<12)
1037        #define PCICFG_STATUS_RCV_MSTR_ABT                  (1<<13)
1038        #define PCICFG_STATUS_SIG_SERR                      (1<<14)
1039        #define PCICFG_STATUS_PAR_ERR                       (1<<15)
1040
1041    u32_t pcicfg_class_code;
1042        #define PCICFG_CLASS_CODE_REV_ID                    (0xffUL<<0)
1043        #define PCICFG_CLASS_CODE_VALUE                     (0xffffffUL<<8)
1044
1045    u8_t pcicfg_cache_line_size;
1046    u8_t pcicfg_latency_timer;
1047    u8_t pcicfg_header_type;
1048    u8_t pcicfg_bist;
1049    u32_t pcicfg_bar_1;
1050        #define PCICFG_BAR_1_MEM_SPACE                      (1UL<<0)
1051        #define PCICFG_BAR_1_SPACE_TYPE                     (0x3UL<<1)
1052        #define PCICFG_BAR_1_PREFETCH                       (1UL<<3)
1053        #define PCICFG_BAR_1_ADDRESS                        (0xfffffffUL<<4)
1054
1055    u32_t pcicfg_bar_2;
1056        #define PCICFG_BAR_2_ADDR                           (0xffffffffUL<<0)
1057
1058    u32_t pcicfg_bar_3;
1059        #define PCICFG_BAR_3_MEM_SPACE                      (1UL<<0)
1060        #define PCICFG_BAR_3_SPACE_TYPE                     (0x3UL<<1)
1061        #define PCICFG_BAR_3_PREFETCH                       (1UL<<3)
1062        #define PCICFG_BAR_3_ADDRESS                        (0xfffffffUL<<4)
1063
1064    u32_t pcicfg_bar_4;
1065        #define PCICFG_BAR_4_ADDR                           (0xffffffffUL<<0)
1066
1067    u32_t pcicfg_bar_5;
1068    u32_t pcicfg_bar_6;
1069    u32_t pcicfg_cardbus_cis;
1070    u16_t pcicfg_subsystem_vendor_id;
1071    u16_t pcicfg_subsystem_id;
1072    u32_t pcicfg_exp_rom_bar;
1073        #define PCICFG_EXP_ROM_BAR_BAR_ENA                  (1UL<<0)
1074        #define PCICFG_EXP_ROM_BAR_LOW_TE                      (0x1ffUL<<1)
1075        #define PCICFG_EXP_ROM_BAR_SIZE_TE                     (0x3fffUL<<10)
1076        #define PCICFG_EXP_ROM_BAR_LOW_XI                      (0x3ffUL<<1)
1077        #define PCICFG_EXP_ROM_BAR_SIZE_XI                     (0x1fffUL<<11)
1078        #define PCICFG_EXP_ROM_BAR_ADDRESS                  (0xffUL<<24)
1079
1080    u8_t pcicfg_cap_pointer;
1081    u8_t unused_0;
1082    u16_t unused_1;
1083    u32_t unused_2;
1084    u8_t pcicfg_int_line;
1085    u8_t pcicfg_int_pin;
1086    u8_t pcicfg_min_grant;
1087    u8_t pcicfg_maximum_latency;
1088    u8_t pcicfg_pcix_cap_id;
1089    u8_t pcicfg_pcix_next_cap_ptr;
1090    u16_t pcicfg_pcix_command;
1091        #define PCICFG_PCIX_COMMAND_DATA_PAR_ERR            (1<<0)
1092        #define PCICFG_PCIX_COMMAND_RELAX_ORDER             (1<<1)
1093        #define PCICFG_PCIX_COMMAND_MAX_MEM_READ            (0x3<<2)
1094            #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_512    (0<<2)
1095            #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_1K     (1<<2)
1096            #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_2K     (2<<2)
1097            #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_4K     (3<<2)
1098        #define PCICFG_PCIX_COMMAND_MAX_SPLIT               (0x7<<4)
1099            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_1  (0<<4)
1100            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_2  (1<<4)
1101            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_3  (2<<4)
1102            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_4  (3<<4)
1103            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_8  (4<<4)
1104            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_12  (5<<4)
1105            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_16  (6<<4)
1106            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_32  (7<<4)
1107            #define PCICFG_PCIX_COMMAND_MAX_SPLIT_RESERVED  (511<<4)
1108
1109    u32_t pcicfg_pcix_status;
1110        #define PCICFG_PCIX_STATUS_FUNC_NUM                 (0x7UL<<0)
1111        #define PCICFG_PCIX_STATUS_DEV_NUM                  (0x1fUL<<3)
1112        #define PCICFG_PCIX_STATUS_BUS_NUM                  (0xffUL<<8)
1113        #define PCICFG_PCIX_STATUS_64_BIT                   (1UL<<16)
1114        #define PCICFG_PCIX_STATUS_MAX_133_ADVERTIZE        (1UL<<17)
1115        #define PCICFG_PCIX_STATUS_SPLIT_DISCARD            (1UL<<18)
1116        #define PCICFG_PCIX_STATUS_UNEXPECTED_SPLIT         (1UL<<19)
1117        #define PCICFG_PCIX_STATUS_DEV_COMPLEX              (1UL<<20)
1118        #define PCICFG_PCIX_STATUS_MAX_MEM_READ             (0x3UL<<21)
1119            #define PCICFG_PCIX_STATUS_MAX_MEM_READ_512     (0UL<<21)
1120            #define PCICFG_PCIX_STATUS_MAX_MEM_READ_1K      (1UL<<21)
1121            #define PCICFG_PCIX_STATUS_MAX_MEM_READ_2K      (2UL<<21)
1122            #define PCICFG_PCIX_STATUS_MAX_MEM_READ_4K      (3UL<<21)
1123        #define PCICFG_PCIX_STATUS_MAX_SPLIT                (0x7UL<<23)
1124            #define PCICFG_PCIX_STATUS_MAX_SPLIT_1          (0UL<<23)
1125            #define PCICFG_PCIX_STATUS_MAX_SPLIT_2          (1UL<<23)
1126            #define PCICFG_PCIX_STATUS_MAX_SPLIT_3          (2UL<<23)
1127            #define PCICFG_PCIX_STATUS_MAX_SPLIT_4          (3UL<<23)
1128            #define PCICFG_PCIX_STATUS_MAX_SPLIT_8          (4UL<<23)
1129            #define PCICFG_PCIX_STATUS_MAX_SPLIT_12         (5UL<<23)
1130            #define PCICFG_PCIX_STATUS_MAX_SPLIT_16         (6UL<<23)
1131            #define PCICFG_PCIX_STATUS_MAX_SPLIT_32         (7UL<<23)
1132        #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE             (0x7UL<<26)
1133            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_1KB     (0UL<<26)
1134            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_2KB     (1UL<<26)
1135            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_4KB     (2UL<<26)
1136            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_8KB     (3UL<<26)
1137            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_16KB    (4UL<<26)
1138            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_32KB    (5UL<<26)
1139            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_64KB    (6UL<<26)
1140            #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_128KB   (7UL<<26)
1141        #define PCICFG_PCIX_STATUS_SPLIT_ERR                (1UL<<29)
1142        #define PCICFG_PCIX_STATUS_RESERVED                 (0x3UL<<30)
1143
1144    u8_t pcicfg_pm_cap_id;
1145    u8_t pcicfg_pm_next_cap_ptr;
1146    u16_t pcicfg_pm_capability;
1147        #define PCICFG_PM_CAPABILITY_VERSION                (0x3<<0)
1148        #define PCICFG_PM_CAPABILITY_CLOCK                  (1<<3)
1149        #define PCICFG_PM_CAPABILITY_RESERVED               (1<<4)
1150        #define PCICFG_PM_CAPABILITY_DSI                    (1<<5)
1151        #define PCICFG_PM_CAPABILITY_AUX_CURRENT            (0x7<<6)
1152        #define PCICFG_PM_CAPABILITY_D1_SUPPORT             (1<<9)
1153        #define PCICFG_PM_CAPABILITY_D2_SUPPORT             (1<<10)
1154        #define PCICFG_PM_CAPABILITY_PME_IN_D0              (1<<11)
1155        #define PCICFG_PM_CAPABILITY_PME_IN_D1              (1<<12)
1156        #define PCICFG_PM_CAPABILITY_PME_IN_D2              (1<<13)
1157        #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT          (1<<14)
1158        #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD         (1<<15)
1159
1160    u16_t pcicfg_pm_csr;
1161        #define PCICFG_PM_CSR_STATE                         (0x3<<0)
1162            #define PCICFG_PM_CSR_STATE_D0                  (0<<0)
1163            #define PCICFG_PM_CSR_STATE_D1                  (1<<0)
1164            #define PCICFG_PM_CSR_STATE_D2                  (2<<0)
1165            #define PCICFG_PM_CSR_STATE_D3_HOT              (3<<0)
1166        #define PCICFG_PM_CSR_RESERVED_TE                      (0x3f<<2)
1167        #define PCICFG_PM_CSR_RESERVED0_XI                     (1<<2)
1168        #define PCICFG_PM_CSR_NO_SOFT_RESET_XI                 (1<<3)
1169        #define PCICFG_PM_CSR_RESERVED1_XI                     (0xf<<4)
1170        #define PCICFG_PM_CSR_PME_ENABLE                    (1<<8)
1171        #define PCICFG_PM_CSR_DATA_SEL                      (0xf<<9)
1172            #define PCICFG_PM_CSR_DATA_SEL_0                (0<<9)
1173            #define PCICFG_PM_CSR_DATA_SEL_1                (1<<9)
1174            #define PCICFG_PM_CSR_DATA_SEL_2                (2<<9)
1175            #define PCICFG_PM_CSR_DATA_SEL_3                (3<<9)
1176            #define PCICFG_PM_CSR_DATA_SEL_4                (4<<9)
1177            #define PCICFG_PM_CSR_DATA_SEL_5                (5<<9)
1178            #define PCICFG_PM_CSR_DATA_SEL_6                (6<<9)
1179            #define PCICFG_PM_CSR_DATA_SEL_7                (7<<9)
1180        #define PCICFG_PM_CSR_DATA_SCALE                    (0x3<<13)
1181            #define PCICFG_PM_CSR_DATA_SCALE_0              (0<<13)
1182            #define PCICFG_PM_CSR_DATA_SCALE_1              (1<<13)
1183            #define PCICFG_PM_CSR_DATA_SCALE_2              (2<<13)
1184            #define PCICFG_PM_CSR_DATA_SCALE_3              (3<<13)
1185        #define PCICFG_PM_CSR_PME_STATUS                    (1<<15)
1186
1187    u8_t pcicfg_pm_csr_bse;
1188    u8_t pcicfg_pm_data;
1189    u8_t pcicfg_vpd_cap_id;
1190    u8_t pcicfg_vpd_next_cap_ptr;
1191    u16_t pcicfg_vpd_flag_addr;
1192        #define PCICFG_VPD_FLAG_ADDR_ADDRESS                (0x1fff<<2)
1193        #define PCICFG_VPD_FLAG_ADDR_FLAG                   (1<<15)
1194
1195    u32_t pcicfg_vpd_data;
1196    u8_t pcicfg_msi_cap_id;
1197    u8_t pcicfg_msi_next_cap_ptr;
1198    u16_t pcicfg_msi_control;
1199        #define PCICFG_MSI_CONTROL_ENABLE                   (1<<0)
1200        #define PCICFG_MSI_CONTROL_MCAP                     (0x7<<1)
1201            #define PCICFG_MSI_CONTROL_MCAP_1               (0<<1)
1202            #define PCICFG_MSI_CONTROL_MCAP_2               (1<<1)
1203            #define PCICFG_MSI_CONTROL_MCAP_4               (2<<1)
1204            #define PCICFG_MSI_CONTROL_MCAP_8               (3<<1)
1205            #define PCICFG_MSI_CONTROL_MCAP_16              (4<<1)
1206            #define PCICFG_MSI_CONTROL_MCAP_32              (5<<1)
1207        #define PCICFG_MSI_CONTROL_MENA                     (0x7<<4)
1208            #define PCICFG_MSI_CONTROL_MENA_1               (0<<4)
1209            #define PCICFG_MSI_CONTROL_MENA_2               (1<<4)
1210            #define PCICFG_MSI_CONTROL_MENA_4               (2<<4)
1211            #define PCICFG_MSI_CONTROL_MENA_8               (3<<4)
1212            #define PCICFG_MSI_CONTROL_MENA_16              (4<<4)
1213            #define PCICFG_MSI_CONTROL_MENA_32              (5<<4)
1214        #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP          (1<<7)
1215        #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE       (1<<8)
1216
1217    u32_t pcicfg_msi_addr_l;
1218        #define PCICFG_MSI_ADDR_L_VAL                       (0x3fffffffUL<<2)
1219
1220    u32_t pcicfg_msi_addr_h;
1221    u16_t pcicfg_msi_data;
1222    u16_t pcicfg_reserved;
1223    u32_t pcicfg_misc_config;
1224        #define PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1UL<<2)
1225        #define PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1UL<<3)
1226        #define PCICFG_MISC_CONFIG_RESERVED1                (1UL<<4)
1227        #define PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1UL<<5)
1228        #define PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1UL<<6)
1229        #define PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1UL<<7)
1230        #define PCICFG_MISC_CONFIG_CORE_RST_REQ             (1UL<<8)
1231        #define PCICFG_MISC_CONFIG_CORE_RST_BSY             (1UL<<9)
1232        #define PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1UL<<10)
1233        #define PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1UL<<11)
1234        #define PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1UL<<12)
1235        #define PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffUL<<16)
1236        #define PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfUL<<24)
1237        #define PCICFG_MISC_CONFIG_ASIC_ID                  (0xfUL<<28)
1238
1239    u32_t pcicfg_misc_status;
1240        #define PCICFG_MISC_STATUS_INTA_VALUE               (1UL<<0)
1241        #define PCICFG_MISC_STATUS_32BIT_DET                (1UL<<1)
1242        #define PCICFG_MISC_STATUS_M66EN                    (1UL<<2)
1243        #define PCICFG_MISC_STATUS_PCIX_DET                 (1UL<<3)
1244        #define PCICFG_MISC_STATUS_PCIX_SPEED               (0x3UL<<4)
1245            #define PCICFG_MISC_STATUS_PCIX_SPEED_66        (0UL<<4)
1246            #define PCICFG_MISC_STATUS_PCIX_SPEED_100       (1UL<<4)
1247            #define PCICFG_MISC_STATUS_PCIX_SPEED_133       (2UL<<4)
1248            #define PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE  (3UL<<4)
1249        #define PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1UL<<8)
1250
1251    u32_t pcicfg_pci_clock_control_bits;
1252        #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET  (0xfUL<<0)
1253            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ  (0UL<<0)
1254            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ  (1UL<<0)
1255            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ  (2UL<<0)
1256            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ  (3UL<<0)
1257            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ  (4UL<<0)
1258            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ  (5UL<<0)
1259            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ  (6UL<<0)
1260            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ  (7UL<<0)
1261            #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW  (15UL<<0)
1262        #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE  (1UL<<6)
1263        #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1UL<<7)
1264        #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC  (0x7UL<<8)
1265            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF  (0UL<<8)
1266            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12  (1UL<<8)
1267            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2UL<<8)
1268            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62  (4UL<<8)
1269        #define PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1UL<<11)
1270        #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfUL<<12)
1271            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100  (0UL<<12)
1272            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80  (1UL<<12)
1273            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50  (2UL<<12)
1274            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40  (4UL<<12)
1275            #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25  (8UL<<12)
1276        #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP  (1UL<<16)
1277        #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1UL<<17)
1278        #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1UL<<18)
1279        #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1UL<<19)
1280        #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffUL<<20)
1281
1282    u32_t unused_3;
1283    u32_t pcicfg_reg_window_address;
1284        #define PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffUL<<2)
1285
1286    u32_t unused_4;
1287    u32_t pcicfg_reg_window;
1288    u32_t pcicfg_int_ack_cmd;
1289        #define PCICFG_INT_ACK_CMD_INDEX                    (0xffffUL<<0)
1290        #define PCICFG_INT_ACK_CMD_INDEX_VALID              (1UL<<16)
1291        #define PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1UL<<17)
1292        #define PCICFG_INT_ACK_CMD_MASK_INT                 (1UL<<18)
1293        #define PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfUL<<24)
1294
1295    u32_t pcicfg_status_bit_set_cmd;
1296    u32_t pcicfg_status_bit_clear_cmd;
1297    u32_t pcicfg_mailbox_queue_addr;
1298    u32_t pcicfg_mailbox_queue_data;
1299    u32_t unused_5[2];
1300    u8_t pcicfg_msix_cap_id;
1301    u8_t pcicfg_msix_next_cap_ptr;
1302    u16_t pcicfg_msix_control;
1303        #define PCICFG_MSIX_CONTROL_TABLE_SIZE              (0x7ff<<0)
1304        #define PCICFG_MSIX_CONTROL_RESERVED                (0x7<<11)
1305        #define PCICFG_MSIX_CONTROL_FUNC_MASK               (1<<14)
1306        #define PCICFG_MSIX_CONTROL_MSIX_ENABLE             (1<<15)
1307
1308    u32_t pcicfg_msix_tbl_off_bir;
1309        #define PCICFG_MSIX_TBL_OFF_BIR_TABLE_BIR           (0x7UL<<0)
1310        #define PCICFG_MSIX_TBL_OFF_BIR_TABLE_OFFSET        (0x1fffffffUL<<3)
1311
1312    u32_t pcicfg_msix_pba_off_bir;
1313        #define PCICFG_MSIX_PBA_OFF_BIR_PBA_BIR             (0x7UL<<0)
1314        #define PCICFG_MSIX_PBA_OFF_BIR_PBA_OFFSET          (0x1fffffffUL<<3)
1315
1316    u8_t pcicfg_pcie_cap_id;
1317    u8_t pcicfg_pcie_next_cap_ptr;
1318    u16_t pcicfg_pcie_capability;
1319        #define PCICFG_PCIE_CAPABILITY_VER                  (0xf<<0)
1320        #define PCICFG_PCIE_CAPABILITY_TYPE                 (0xf<<4)
1321
1322    u32_t pcicfg_device_capability;
1323        #define PCICFG_DEVICE_CAPABILITY_MAX_PAYLOAD        (0x7UL<<0)
1324        #define PCICFG_DEVICE_CAPABILITY_PHANTOM_SUPPT      (0x3UL<<3)
1325        #define PCICFG_DEVICE_CAPABILITY_EXT_TAG_SUPPT      (1UL<<5)
1326        #define PCICFG_DEVICE_CAPABILITY_EP_L0S_ACCP_LAT    (0x7UL<<6)
1327        #define PCICFG_DEVICE_CAPABILITY_EP_L1_ACCP_LAT     (0x7UL<<9)
1328
1329    u16_t pcicfg_device_control;
1330        #define PCICFG_DEVICE_CONTROL_CORR_ERR_REP_ENA      (1<<0)
1331        #define PCICFG_DEVICE_CONTROL_NON_FATAL_REP_ENA     (1<<1)
1332        #define PCICFG_DEVICE_CONTROL_FATAL_REP_ENA         (1<<2)
1333        #define PCICFG_DEVICE_CONTROL_UNSUP_REQ_ENA         (1<<3)
1334        #define PCICFG_DEVICE_CONTROL_RELAX_ENA             (1<<4)
1335        #define PCICFG_DEVICE_CONTROL_MAX_PAYLOAD           (0x7<<5)
1336        #define PCICFG_DEVICE_CONTROL_EXT_TAG_ENA           (1<<8)
1337        #define PCICFG_DEVICE_CONTROL_AUX_PWR_PM_ENA        (1<<10)
1338        #define PCICFG_DEVICE_CONTROL_ENA_NO_SNOOP          (1<<11)
1339        #define PCICFG_DEVICE_CONTROL_MAX_RD_REQ            (0x7<<12)
1340
1341    u16_t pcicfg_device_status;
1342        #define PCICFG_DEVICE_STATUS_CORR_ERR_DET           (1<<0)
1343        #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET      (1<<1)
1344        #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET          (1<<2)
1345        #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET          (1<<3)
1346        #define PCICFG_DEVICE_STATUS_AUX_PWR_DET            (1<<4)
1347        #define PCICFG_DEVICE_STATUS_NO_PEND                (1<<5)
1348
1349    u32_t pcicfg_link_capability;
1350        #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED       (0xfUL<<0)
1351            #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5  (1UL<<0)
1352            #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_5  (2UL<<0)
1353        #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH       (0x3fUL<<4)
1354            #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_1  (1UL<<4)
1355            #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_2  (2UL<<4)
1356            #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_4  (4UL<<4)
1357            #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_8  (8UL<<4)
1358        #define PCICFG_LINK_CAPABILITY_ASPM_SUPT            (0x3UL<<10)
1359            #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_RES_0  (0UL<<10)
1360            #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_L0S    (0UL<<10)
1361            #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_RES_2  (0UL<<10)
1362            #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_L0S_L1  (0UL<<10)
1363        #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT         (0x7UL<<12)
1364            #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT_1_2  (5UL<<12)
1365            #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT_2_4  (6UL<<12)
1366        #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT          (0x7UL<<15)
1367            #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT_1_2  (1UL<<15)
1368            #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT_2_4  (2UL<<15)
1369        #define PCICFG_LINK_CAPABILITY_CLK_PWR_MGMT         (1UL<<18)
1370        #define PCICFG_LINK_CAPABILITY_PORT_NUMBER          (0xffUL<<24)
1371
1372    u16_t pcicfg_link_control;
1373        #define PCICFG_LINK_CONTROL_ASPM_CTRL               (0x3<<0)
1374        #define PCICFG_LINK_CONTROL_RD_COMP_BOUND           (1<<3)
1375            #define PCICFG_LINK_CONTROL_RD_COMP_BOUND_64    (0<<3)
1376            #define PCICFG_LINK_CONTROL_RD_COMP_BOUND_128   (1<<3)
1377        #define PCICFG_LINK_CONTROL_LINK_CR_COMMON_CLK      (1<<6)
1378        #define PCICFG_LINK_CONTROL_LINK_CR_EXT_SYNC        (1<<7)
1379
1380    u16_t pcicfg_link_status;
1381        #define PCICFG_LINK_STATUS_SPEED                    (0xf<<0)
1382        #define PCICFG_LINK_STATUS_NEG_LINK_WIDTH           (0x3f<<4)
1383        #define PCICFG_LINK_STATUS_TRAINING_ERR             (1<<10)
1384        #define PCICFG_LINK_STATUS_TRAINING                 (1<<11)
1385        #define PCICFG_LINK_STATUS_SLOT_CLK                 (1<<12)
1386
1387    u32_t pcicfg_slot_capability;
1388    u16_t pcicfg_slot_control;
1389    u16_t pcicfg_slot_status;
1390    u16_t pcicfg_root_control;
1391    u16_t pcicfg_root_cap;
1392    u32_t pcicfg_root_status;
1393    u32_t pcicfg_device_capability_2;
1394        #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP  (0xfUL<<0)
1395            #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_ABCD  (15UL<<0)
1396        #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP  (1UL<<4)
1397
1398    u16_t pcicfg_device_control_2;
1399        #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE       (0xf<<0)
1400            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_50MS  (0<<0)
1401            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_100US  (1<<0)
1402            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_10MS  (2<<0)
1403            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_55MS  (3<<0)
1404            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_210MS  (4<<0)
1405            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_900MS  (5<<0)
1406            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_3_5S  (6<<0)
1407            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_13S  (7<<0)
1408            #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_64S  (8<<0)
1409        #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_DISABLE     (1<<4)
1410
1411    u16_t pcicfg_device_status_2;
1412    u32_t pcicfg_link_capability_2;
1413    u16_t pcicfg_link_control_2;
1414        #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED     (0xf<<0)
1415            #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED_2_5  (0<<0)
1416            #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED_5_0  (1<<0)
1417        #define PCICFG_LINK_CONTROL_2_ENTER_COMPLIANCE      (1<<4)
1418        #define PCICFG_LINK_CONTROL_2_HW_AUTO_SPEED_DISABLE  (1<<5)
1419        #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS        (1<<6)
1420            #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS_0  (0<<6)
1421            #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS_1  (1<<6)
1422        #define PCICFG_LINK_CONTROL_2_TX_MARGIN             (0x7<<7)
1423            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_000     (0<<7)
1424            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_001     (1<<7)
1425            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_010     (2<<7)
1426            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_011     (3<<7)
1427            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_100     (4<<7)
1428            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_101     (5<<7)
1429            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_110     (6<<7)
1430            #define PCICFG_LINK_CONTROL_2_TX_MARGIN_111     (7<<7)
1431
1432    u16_t pcicfg_link_status_2;
1433    u32_t unused_6[8];
1434    u16_t pcicfg_device_ser_num_cap_id;
1435    u16_t pcicfg_device_ser_num_cap_off;
1436        #define PCICFG_DEVICE_SER_NUM_CAP_OFF_VER           (0xf<<0)
1437        #define PCICFG_DEVICE_SER_NUM_CAP_OFF_NEXT          (0xfff<<4)
1438
1439    u32_t pcicfg_lower_ser_num;
1440    u32_t pcicfg_upper_ser_num;
1441    u32_t unused_7;
1442    u16_t pcicfg_adv_err_cap_id;
1443    u16_t pcicfg_adv_err_cap_off;
1444        #define PCICFG_ADV_ERR_CAP_OFF_VER                  (0xf<<0)
1445        #define PCICFG_ADV_ERR_CAP_OFF_NEXT                 (0xfff<<4)
1446
1447    u32_t pcicfg_ucorr_err_status;
1448        #define PCICFG_UCORR_ERR_STATUS_DLPES               (1UL<<4)
1449        #define PCICFG_UCORR_ERR_STATUS_PTLPS               (1UL<<12)
1450        #define PCICFG_UCORR_ERR_STATUS_FCPES               (1UL<<13)
1451        #define PCICFG_UCORR_ERR_STATUS_CTS                 (1UL<<14)
1452        #define PCICFG_UCORR_ERR_STATUS_CAS                 (1UL<<15)
1453        #define PCICFG_UCORR_ERR_STATUS_UCS                 (1UL<<16)
1454        #define PCICFG_UCORR_ERR_STATUS_ROS                 (1UL<<17)
1455        #define PCICFG_UCORR_ERR_STATUS_MTLPS               (1UL<<18)
1456        #define PCICFG_UCORR_ERR_STATUS_ECRCS               (1UL<<19)
1457        #define PCICFG_UCORR_ERR_STATUS_URES                (1UL<<20)
1458
1459    u32_t pcicfg_ucorr_err_mask;
1460        #define PCICFG_UCORR_ERR_MASK_DLPEM                 (1UL<<4)
1461        #define PCICFG_UCORR_ERR_MASK_SDEM                  (1UL<<5)
1462        #define PCICFG_UCORR_ERR_MASK_PTLPM                 (1UL<<12)
1463        #define PCICFG_UCORR_ERR_MASK_FCPEM                 (1UL<<13)
1464        #define PCICFG_UCORR_ERR_MASK_CTM                   (1UL<<14)
1465        #define PCICFG_UCORR_ERR_MASK_CAM                   (1UL<<15)
1466        #define PCICFG_UCORR_ERR_MASK_UCM                   (1UL<<16)
1467        #define PCICFG_UCORR_ERR_MASK_ROM                   (1UL<<17)
1468        #define PCICFG_UCORR_ERR_MASK_MTLPM                 (1UL<<18)
1469        #define PCICFG_UCORR_ERR_MASK_ECRCEM                (1UL<<19)
1470        #define PCICFG_UCORR_ERR_MASK_UREM                  (1UL<<20)
1471
1472    u32_t pcicfg_ucorr_err_sevr;
1473        #define PCICFG_UCORR_ERR_SEVR_DLPES                 (1UL<<4)
1474        #define PCICFG_UCORR_ERR_SEVR_SDES                  (1UL<<5)
1475        #define PCICFG_UCORR_ERR_SEVR_PTLPS                 (1UL<<12)
1476        #define PCICFG_UCORR_ERR_SEVR_FCPES                 (1UL<<13)
1477        #define PCICFG_UCORR_ERR_SEVR_CTS                   (1UL<<14)
1478        #define PCICFG_UCORR_ERR_SEVR_CAS                   (1UL<<15)
1479        #define PCICFG_UCORR_ERR_SEVR_UCS                   (1UL<<16)
1480        #define PCICFG_UCORR_ERR_SEVR_ROS                   (1UL<<17)
1481        #define PCICFG_UCORR_ERR_SEVR_MTLPS                 (1UL<<18)
1482        #define PCICFG_UCORR_ERR_SEVR_ECRCES                (1UL<<19)
1483        #define PCICFG_UCORR_ERR_SEVR_URES                  (1UL<<20)
1484
1485    u32_t pcicfg_corr_err_status;
1486        #define PCICFG_CORR_ERR_STATUS_RES                  (1UL<<0)
1487        #define PCICFG_CORR_ERR_STATUS_BDLLPS               (1UL<<7)
1488        #define PCICFG_CORR_ERR_STATUS_BTLPS                (1UL<<7)
1489        #define PCICFG_CORR_ERR_STATUS_RNRS                 (1UL<<8)
1490        #define PCICFG_CORR_ERR_STATUS_RTTS                 (1UL<<12)
1491        #define PCICFG_CORR_ERR_STATUS_ANFS                 (1UL<<13)
1492
1493    u32_t pcicfg_corr_err_mask;
1494        #define PCICFG_CORR_ERR_MASK_RES                    (1UL<<0)
1495        #define PCICFG_CORR_ERR_MASK_BTLPS                  (1UL<<6)
1496        #define PCICFG_CORR_ERR_MASK_BDLLPS                 (1UL<<7)
1497        #define PCICFG_CORR_ERR_MASK_RNRS                   (1UL<<8)
1498        #define PCICFG_CORR_ERR_MASK_RTTS                   (1UL<<12)
1499        #define PCICFG_CORR_ERR_MASK_ANFM                   (1UL<<13)
1500
1501    u32_t pcicfg_adv_err_cap_control;
1502        #define PCICFG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR   (0x1fUL<<0)
1503        #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCGCAP         (1UL<<5)
1504        #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCGEN          (1UL<<6)
1505        #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCCAP          (1UL<<7)
1506        #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCEN           (1UL<<8)
1507
1508    u32_t pcicfg_header_log1;
1509    u32_t pcicfg_header_log2;
1510    u32_t pcicfg_header_log3;
1511    u32_t pcicfg_header_log4;
1512    u32_t unused_8[5];
1513    u16_t pcicfg_pwr_bdgt_cap_id;
1514    u16_t pcicfg_pwr_bdgt_cap_off;
1515        #define PCICFG_PWR_BDGT_CAP_OFF_VER                 (0xf<<0)
1516        #define PCICFG_PWR_BDGT_CAP_OFF_NEXT                (0xfff<<4)
1517
1518    u32_t pcicfg_pwr_bdgt_data_sel;
1519        #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE           (0xffUL<<0)
1520            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_0     (0UL<<0)
1521            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_1     (1UL<<0)
1522            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_2     (2UL<<0)
1523            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_3     (3UL<<0)
1524            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_4     (4UL<<0)
1525            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_5     (5UL<<0)
1526            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_6     (6UL<<0)
1527            #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_7     (7UL<<0)
1528
1529    u32_t pcicfg_pwr_bdgt_data;
1530        #define PCICFG_PWR_BDGT_DATA_BASE_PWR               (0xffUL<<0)
1531        #define PCICFG_PWR_BDGT_DATA_DSCALE                 (0x3UL<<8)
1532        #define PCICFG_PWR_BDGT_DATA_PM_STATE               (0x3UL<<13)
1533        #define PCICFG_PWR_BDGT_DATA_TYPE                   (0x7UL<<15)
1534        #define PCICFG_PWR_BDGT_DATA_RAIL                   (0x7UL<<18)
1535
1536    u32_t pcicfg_pwr_bdgt_capability;
1537        #define PCICFG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC  (1UL<<0)
1538
1539    u16_t pcicfg_vc_cap_id;
1540    u16_t pcicfg_vc_cap_off;
1541        #define PCICFG_VC_CAP_OFF_VER                       (0xf<<0)
1542        #define PCICFG_VC_CAP_OFF_NEXT                      (0xfff<<4)
1543
1544    u32_t pcicfg_port_vc_capability;
1545    u32_t pcicfg_port_vc_capability2;
1546    u16_t pcicfg_port_vc_control;
1547    u16_t pcicfg_port_vc_status;
1548    u32_t pcicfg_port_arb_table;
1549    u32_t pcicfg_vc_rsrc_control;
1550        #define PCICFG_VC_RSRC_CONTROL_TC_VC_MAP            (0xffUL<<0)
1551        #define PCICFG_VC_RSRC_CONTROL_VC_ENABLE            (1UL<<31)
1552
1553    u16_t pcicfg_rsvdp;
1554    u16_t pcicfg_vc_rsrc_status;
1555    u32_t unused_9[161];
1556} pci_config_t;
1557
1558
1559/*
1560 *  pci_reg definition
1561 *  offset: 0x400
1562 */
1563typedef struct pci_reg
1564{
1565    u32_t pci_grc_window_addr;
1566        #define PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffUL<<13)
1567        #define PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1UL<<31)
1568
1569    u32_t pci_config_1;
1570        #define PCI_CONFIG_1_RESERVED0                      (0xffUL<<0)
1571        #define PCI_CONFIG_1_READ_BOUNDARY                  (0x7UL<<8)
1572            #define PCI_CONFIG_1_READ_BOUNDARY_OFF          (0UL<<8)
1573            #define PCI_CONFIG_1_READ_BOUNDARY_16           (1UL<<8)
1574            #define PCI_CONFIG_1_READ_BOUNDARY_32           (2UL<<8)
1575            #define PCI_CONFIG_1_READ_BOUNDARY_64           (3UL<<8)
1576            #define PCI_CONFIG_1_READ_BOUNDARY_128          (4UL<<8)
1577            #define PCI_CONFIG_1_READ_BOUNDARY_256          (5UL<<8)
1578            #define PCI_CONFIG_1_READ_BOUNDARY_512          (6UL<<8)
1579            #define PCI_CONFIG_1_READ_BOUNDARY_1024         (7UL<<8)
1580        #define PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7UL<<11)
1581            #define PCI_CONFIG_1_WRITE_BOUNDARY_OFF         (0UL<<11)
1582            #define PCI_CONFIG_1_WRITE_BOUNDARY_16          (1UL<<11)
1583            #define PCI_CONFIG_1_WRITE_BOUNDARY_32          (2UL<<11)
1584            #define PCI_CONFIG_1_WRITE_BOUNDARY_64          (3UL<<11)
1585            #define PCI_CONFIG_1_WRITE_BOUNDARY_128         (4UL<<11)
1586            #define PCI_CONFIG_1_WRITE_BOUNDARY_256         (5UL<<11)
1587            #define PCI_CONFIG_1_WRITE_BOUNDARY_512         (6UL<<11)
1588            #define PCI_CONFIG_1_WRITE_BOUNDARY_1024        (7UL<<11)
1589        #define PCI_CONFIG_1_RESERVED1                      (0x3ffffUL<<14)
1590
1591    u32_t pci_config_2;
1592        #define PCI_CONFIG_2_BAR1_SIZE                      (0xfUL<<0)
1593            #define PCI_CONFIG_2_BAR1_SIZE_DISABLED         (0UL<<0)
1594            #define PCI_CONFIG_2_BAR1_SIZE_64K              (1UL<<0)
1595            #define PCI_CONFIG_2_BAR1_SIZE_128K             (2UL<<0)
1596            #define PCI_CONFIG_2_BAR1_SIZE_256K             (3UL<<0)
1597            #define PCI_CONFIG_2_BAR1_SIZE_512K             (4UL<<0)
1598            #define PCI_CONFIG_2_BAR1_SIZE_1M               (5UL<<0)
1599            #define PCI_CONFIG_2_BAR1_SIZE_2M               (6UL<<0)
1600            #define PCI_CONFIG_2_BAR1_SIZE_4M               (7UL<<0)
1601            #define PCI_CONFIG_2_BAR1_SIZE_8M               (8UL<<0)
1602            #define PCI_CONFIG_2_BAR1_SIZE_16M              (9UL<<0)
1603            #define PCI_CONFIG_2_BAR1_SIZE_32M              (10UL<<0)
1604            #define PCI_CONFIG_2_BAR1_SIZE_64M              (11UL<<0)
1605            #define PCI_CONFIG_2_BAR1_SIZE_128M             (12UL<<0)
1606            #define PCI_CONFIG_2_BAR1_SIZE_256M             (13UL<<0)
1607            #define PCI_CONFIG_2_BAR1_SIZE_512M             (14UL<<0)
1608            #define PCI_CONFIG_2_BAR1_SIZE_1G               (15UL<<0)
1609        #define PCI_CONFIG_2_BAR1_64ENA                     (1UL<<4)
1610        #define PCI_CONFIG_2_EXP_ROM_RETRY                  (1UL<<5)
1611        #define PCI_CONFIG_2_CFG_CYCLE_RETRY                (1UL<<6)
1612        #define PCI_CONFIG_2_FIRST_CFG_DONE                 (1UL<<7)
1613        #define PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffUL<<8)
1614            #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED      (0UL<<8)
1615            #define PCI_CONFIG_2_EXP_ROM_SIZE_1K_TE            (1UL<<8)
1616            #define PCI_CONFIG_2_EXP_ROM_SIZE_2K_TE            (2UL<<8)
1617            #define PCI_CONFIG_2_EXP_ROM_SIZE_4K_TE            (3UL<<8)
1618            #define PCI_CONFIG_2_EXP_ROM_SIZE_8K_TE            (4UL<<8)
1619            #define PCI_CONFIG_2_EXP_ROM_SIZE_16K_TE           (5UL<<8)
1620            #define PCI_CONFIG_2_EXP_ROM_SIZE_32K_TE           (6UL<<8)
1621            #define PCI_CONFIG_2_EXP_ROM_SIZE_64K_TE           (7UL<<8)
1622            #define PCI_CONFIG_2_EXP_ROM_SIZE_128K_TE          (8UL<<8)
1623            #define PCI_CONFIG_2_EXP_ROM_SIZE_256K_TE          (9UL<<8)
1624            #define PCI_CONFIG_2_EXP_ROM_SIZE_512K_TE          (10UL<<8)
1625            #define PCI_CONFIG_2_EXP_ROM_SIZE_1M_TE            (11UL<<8)
1626            #define PCI_CONFIG_2_EXP_ROM_SIZE_2M_TE            (12UL<<8)
1627            #define PCI_CONFIG_2_EXP_ROM_SIZE_4M_TE            (13UL<<8)
1628            #define PCI_CONFIG_2_EXP_ROM_SIZE_8M_TE            (14UL<<8)
1629            #define PCI_CONFIG_2_EXP_ROM_SIZE_16M_TE           (15UL<<8)
1630            #define PCI_CONFIG_2_EXP_ROM_SIZE_2K_XI            (1UL<<8)
1631            #define PCI_CONFIG_2_EXP_ROM_SIZE_4K_XI            (2UL<<8)
1632            #define PCI_CONFIG_2_EXP_ROM_SIZE_8K_XI            (3UL<<8)
1633            #define PCI_CONFIG_2_EXP_ROM_SIZE_16K_XI           (4UL<<8)
1634            #define PCI_CONFIG_2_EXP_ROM_SIZE_32K_XI           (5UL<<8)
1635            #define PCI_CONFIG_2_EXP_ROM_SIZE_64K_XI           (6UL<<8)
1636            #define PCI_CONFIG_2_EXP_ROM_SIZE_128K_XI          (7UL<<8)
1637            #define PCI_CONFIG_2_EXP_ROM_SIZE_256K_XI          (8UL<<8)
1638            #define PCI_CONFIG_2_EXP_ROM_SIZE_512K_XI          (9UL<<8)
1639            #define PCI_CONFIG_2_EXP_ROM_SIZE_1M_XI            (10UL<<8)
1640            #define PCI_CONFIG_2_EXP_ROM_SIZE_2M_XI            (11UL<<8)
1641            #define PCI_CONFIG_2_EXP_ROM_SIZE_4M_XI            (12UL<<8)
1642            #define PCI_CONFIG_2_EXP_ROM_SIZE_8M_XI            (13UL<<8)
1643            #define PCI_CONFIG_2_EXP_ROM_SIZE_16M_XI           (14UL<<8)
1644            #define PCI_CONFIG_2_EXP_ROM_SIZE_32M_XI           (15UL<<8)
1645        #define PCI_CONFIG_2_MAX_SPLIT_LIMIT_TE                (0x1fUL<<16)
1646        #define PCI_CONFIG_2_MAX_READ_LIMIT_TE                 (0x3UL<<21)
1647            #define PCI_CONFIG_2_MAX_READ_LIMIT_512_TE         (0UL<<21)
1648            #define PCI_CONFIG_2_MAX_READ_LIMIT_1K_TE          (1UL<<21)
1649            #define PCI_CONFIG_2_MAX_READ_LIMIT_2K_TE          (2UL<<21)
1650            #define PCI_CONFIG_2_MAX_READ_LIMIT_4K_TE          (3UL<<21)
1651        #define PCI_CONFIG_2_FORCE_32_BIT_MSTR_TE              (1UL<<23)
1652        #define PCI_CONFIG_2_FORCE_32_BIT_TGT_TE               (1UL<<24)
1653        #define PCI_CONFIG_2_KEEP_REQ_ASSERT_TE                (1UL<<25)
1654        #define PCI_CONFIG_2_RESERVED0_TE                      (0x3fUL<<26)
1655        #define PCI_CONFIG_2_BAR_PREFETCH_XI                   (1UL<<16)
1656        #define PCI_CONFIG_2_RESERVED0_XI                      (0x7fffUL<<17)
1657
1658    u32_t pci_config_3;
1659        #define PCI_CONFIG_3_STICKY_BYTE                    (0xffUL<<0)
1660        #define PCI_CONFIG_3_REG_STICKY_BYTE                (0xffUL<<8)
1661        #define PCI_CONFIG_3_FORCE_PME                      (1UL<<24)
1662        #define PCI_CONFIG_3_PME_STATUS                     (1UL<<25)
1663        #define PCI_CONFIG_3_PME_ENABLE                     (1UL<<26)
1664        #define PCI_CONFIG_3_PM_STATE                       (0x3UL<<27)
1665        #define PCI_CONFIG_3_VAUX_PRESET                    (1UL<<30)
1666        #define PCI_CONFIG_3_PCI_POWER                      (1UL<<31)
1667
1668    u32_t pci_pm_data_a;
1669        #define PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffUL<<0)
1670        #define PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffUL<<8)
1671        #define PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffUL<<16)
1672        #define PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffUL<<24)
1673
1674    u32_t pci_pm_data_b;
1675        #define PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffUL<<0)
1676        #define PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffUL<<8)
1677        #define PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffUL<<16)
1678        #define PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffUL<<24)
1679
1680    u32_t pci_swap_diag0;
1681    u32_t pci_swap_diag1;
1682    u32_t pci_exp_rom_addr;
1683        #define PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffUL<<2)
1684        #define PCI_EXP_ROM_ADDR_REQ                        (1UL<<31)
1685
1686    u32_t pci_exp_rom_data;
1687    u32_t pci_vpd_intf;
1688        #define PCI_VPD_INTF_INTF_REQ                       (1UL<<0)
1689
1690    u16_t unused_0;
1691    u16_t pci_vpd_addr_flag;
1692        #define PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
1693        #define PCI_VPD_ADDR_FLAG_WR                        (1<<15)
1694
1695    u32_t pci_vpd_data;
1696    u32_t pci_id_val1;
1697        #define PCI_ID_VAL1_DEVICE_ID                       (0xffffUL<<0)
1698        #define PCI_ID_VAL1_VENDOR_ID                       (0xffffUL<<16)
1699
1700    u32_t pci_id_val2;
1701        #define PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffUL<<0)
1702        #define PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffUL<<16)
1703
1704    u32_t pci_id_val3;
1705        #define PCI_ID_VAL3_CLASS_CODE                      (0xffffffUL<<0)
1706        #define PCI_ID_VAL3_REVISION_ID                     (0xffUL<<24)
1707
1708    u32_t pci_id_val4;
1709        #define PCI_ID_VAL4_CAP_ENA                         (0xfUL<<0)
1710            #define PCI_ID_VAL4_CAP_ENA_0                   (0UL<<0)
1711            #define PCI_ID_VAL4_CAP_ENA_1                   (1UL<<0)
1712            #define PCI_ID_VAL4_CAP_ENA_2                   (2UL<<0)
1713            #define PCI_ID_VAL4_CAP_ENA_3                   (3UL<<0)
1714            #define PCI_ID_VAL4_CAP_ENA_4                   (4UL<<0)
1715            #define PCI_ID_VAL4_CAP_ENA_5                   (5UL<<0)
1716            #define PCI_ID_VAL4_CAP_ENA_6                   (6UL<<0)
1717            #define PCI_ID_VAL4_CAP_ENA_7                   (7UL<<0)
1718            #define PCI_ID_VAL4_CAP_ENA_8                   (8UL<<0)
1719            #define PCI_ID_VAL4_CAP_ENA_9                   (9UL<<0)
1720            #define PCI_ID_VAL4_CAP_ENA_10                  (10UL<<0)
1721            #define PCI_ID_VAL4_CAP_ENA_11                  (11UL<<0)
1722            #define PCI_ID_VAL4_CAP_ENA_12                  (12UL<<0)
1723            #define PCI_ID_VAL4_CAP_ENA_13                  (13UL<<0)
1724            #define PCI_ID_VAL4_CAP_ENA_14                  (14UL<<0)
1725            #define PCI_ID_VAL4_CAP_ENA_15                  (15UL<<0)
1726        #define PCI_ID_VAL4_RESERVED0                       (0x3UL<<4)
1727        #define PCI_ID_VAL4_PM_SCALE_PRG                    (0x3UL<<6)
1728            #define PCI_ID_VAL4_PM_SCALE_PRG_0              (0UL<<6)
1729            #define PCI_ID_VAL4_PM_SCALE_PRG_1              (1UL<<6)
1730            #define PCI_ID_VAL4_PM_SCALE_PRG_2              (2UL<<6)
1731            #define PCI_ID_VAL4_PM_SCALE_PRG_3              (3UL<<6)
1732        #define PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1UL<<8)
1733        #define PCI_ID_VAL4_MSI_LIMIT                       (0x7UL<<9)
1734        #define PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7UL<<12)
1735        #define PCI_ID_VAL4_MSI_ENABLE                      (1UL<<15)
1736        #define PCI_ID_VAL4_MAX_64_ADVERTIZE_TE                (1UL<<16)
1737        #define PCI_ID_VAL4_MAX_133_ADVERTIZE_TE               (1UL<<17)
1738        #define PCI_ID_VAL4_RESERVED2_TE                       (0x7UL<<18)
1739        #define PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21_TE         (0x3UL<<21)
1740        #define PCI_ID_VAL4_MAX_SPLIT_SIZE_B21_TE              (0x3UL<<23)
1741        #define PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0_TE          (1UL<<25)
1742        #define PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10_TE           (0x3UL<<26)
1743        #define PCI_ID_VAL4_MAX_SPLIT_SIZE_B0_TE               (1UL<<28)
1744        #define PCI_ID_VAL4_RESERVED3_TE                       (0x7UL<<29)
1745        #define PCI_ID_VAL4_RESERVED3_XI                       (0xffffUL<<16)
1746
1747    u32_t pci_id_val5;
1748        #define PCI_ID_VAL5_D1_SUPPORT                      (1UL<<0)
1749        #define PCI_ID_VAL5_D2_SUPPORT                      (1UL<<1)
1750        #define PCI_ID_VAL5_PME_IN_D0                       (1UL<<2)
1751        #define PCI_ID_VAL5_PME_IN_D1                       (1UL<<3)
1752        #define PCI_ID_VAL5_PME_IN_D2                       (1UL<<4)
1753        #define PCI_ID_VAL5_PME_IN_D3_HOT                   (1UL<<5)
1754        #define PCI_ID_VAL5_RESERVED0_TE                       (0x3ffffffUL<<6)
1755        #define PCI_ID_VAL5_PM_VERSION_XI                      (0x7UL<<6)
1756        #define PCI_ID_VAL5_NO_SOFT_RESET_XI                   (1UL<<9)
1757        #define PCI_ID_VAL5_RESERVED0_XI                       (0x3fffffUL<<10)
1758
1759    u32_t pci_pcix_extended_status;
1760        #define PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1UL<<8)
1761        #define PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1UL<<9)
1762        #define PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS  (0xfUL<<16)
1763        #define PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX  (0xffUL<<24)
1764
1765    u32_t pci_id_val6;
1766        #define PCI_ID_VAL6_MAX_LAT                         (0xffUL<<0)
1767        #define PCI_ID_VAL6_MIN_GNT                         (0xffUL<<8)
1768        #define PCI_ID_VAL6_BIST                            (0xffUL<<16)
1769        #define PCI_ID_VAL6_RESERVED0                       (0xffUL<<24)
1770
1771    u32_t pci_msi_data;
1772        #define PCI_MSI_DATA_MSI_DATA                       (0xffffUL<<0)
1773
1774    u32_t pci_msi_addr_h;
1775    u32_t pci_msi_addr_l;
1776        #define PCI_MSI_ADDR_L_VAL                          (0x3fffffffUL<<2)
1777
1778    u32_t pci_cfg_access_cmd;
1779        #define PCI_CFG_ACCESS_CMD_ADR                      (0x3fUL<<2)
1780        #define PCI_CFG_ACCESS_CMD_RD_REQ                   (1UL<<27)
1781        #define PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfUL<<28)
1782
1783    u32_t pci_cfg_access_data;
1784    u32_t pci_msi_mask;
1785        #define PCI_MSI_MASK_MSI_MASK                       (0xffffffffUL<<0)
1786
1787    u32_t pci_msi_pend;
1788        #define PCI_MSI_PEND_MSI_PEND                       (0xffffffffUL<<0)
1789
1790    u32_t pci_pm_data_c;
1791        #define PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffUL<<0)
1792        #define PCI_PM_DATA_C_RESERVED0                     (0xffffffUL<<8)
1793
1794    u32_t unused_1[20];
1795    u32_t pci_msix_control;
1796        #define PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffUL<<0)
1797        #define PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffUL<<11)
1798
1799    u32_t pci_msix_tbl_off_bir;
1800        #define PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7UL<<0)
1801        #define PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffUL<<3)
1802
1803    u32_t pci_msix_pba_off_bit;
1804        #define PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7UL<<0)
1805        #define PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffUL<<3)
1806
1807    u32_t unused_2;
1808    u32_t pci_pcie_capability;
1809        #define PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fUL<<0)
1810        #define PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1UL<<5)
1811
1812    u32_t pci_device_capability;
1813        #define PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7UL<<0)
1814        #define PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1UL<<5)
1815        #define PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY  (0x7UL<<6)
1816        #define PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY  (0x7UL<<9)
1817        #define PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1UL<<15)
1818
1819    u32_t unused_3;
1820    u32_t pci_link_capability;
1821        #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfUL<<0)
1822            #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001  (1UL<<0)
1823            #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010  (2UL<<0)
1824        #define PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fUL<<4)
1825        #define PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1UL<<9)
1826        #define PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3UL<<10)
1827        #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7UL<<12)
1828            #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101    (5UL<<12)
1829            #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110    (6UL<<12)
1830        #define PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7UL<<15)
1831            #define PCI_LINK_CAPABILITY_L1_EXIT_LAT_001     (1UL<<15)
1832            #define PCI_LINK_CAPABILITY_L1_EXIT_LAT_010     (2UL<<15)
1833        #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7UL<<18)
1834            #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101  (5UL<<18)
1835            #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110  (6UL<<18)
1836        #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7UL<<21)
1837            #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001  (1UL<<21)
1838            #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010  (2UL<<21)
1839        #define PCI_LINK_CAPABILITY_PORT_NUM                (0xffUL<<24)
1840
1841    u32_t pci_bar2_config;
1842        #define PCI_BAR2_CONFIG_BAR2_SIZE                   (0xfUL<<0)
1843            #define PCI_BAR2_CONFIG_BAR2_SIZE_DISABLED      (0UL<<0)
1844            #define PCI_BAR2_CONFIG_BAR2_SIZE_64K           (1UL<<0)
1845            #define PCI_BAR2_CONFIG_BAR2_SIZE_128K          (2UL<<0)
1846            #define PCI_BAR2_CONFIG_BAR2_SIZE_256K          (3UL<<0)
1847            #define PCI_BAR2_CONFIG_BAR2_SIZE_512K          (4UL<<0)
1848            #define PCI_BAR2_CONFIG_BAR2_SIZE_1M            (5UL<<0)
1849            #define PCI_BAR2_CONFIG_BAR2_SIZE_2M            (6UL<<0)
1850            #define PCI_BAR2_CONFIG_BAR2_SIZE_4M            (7UL<<0)
1851            #define PCI_BAR2_CONFIG_BAR2_SIZE_8M            (8UL<<0)
1852            #define PCI_BAR2_CONFIG_BAR2_SIZE_16M           (9UL<<0)
1853            #define PCI_BAR2_CONFIG_BAR2_SIZE_32M           (10UL<<0)
1854            #define PCI_BAR2_CONFIG_BAR2_SIZE_64M           (11UL<<0)
1855            #define PCI_BAR2_CONFIG_BAR2_SIZE_128M          (12UL<<0)
1856            #define PCI_BAR2_CONFIG_BAR2_SIZE_256M          (13UL<<0)
1857            #define PCI_BAR2_CONFIG_BAR2_SIZE_512M          (14UL<<0)
1858            #define PCI_BAR2_CONFIG_BAR2_SIZE_1G            (15UL<<0)
1859        #define PCI_BAR2_CONFIG_BAR2_64ENA                  (1UL<<4)
1860        #define PCI_BAR2_CONFIG_BAR2_PREFETCH               (1UL<<5)
1861        #define PCI_BAR2_CONFIG_RESERVED                    (0x3ffffffUL<<6)
1862
1863    u32_t pci_pcie_device_capability_2;
1864        #define PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP  (0xfUL<<0)
1865        #define PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP  (1UL<<4)
1866        #define PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffUL<<5)
1867
1868    u32_t pci_pcie_link_capability_2;
1869        #define PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffUL<<0)
1870
1871    u32_t unused_4[5];
1872    u32_t pci_dev_ser_num_cap_id;
1873        #define PCI_DEV_SER_NUM_CAP_ID_CAP_ID               (0xffffUL<<0)
1874        #define PCI_DEV_SER_NUM_CAP_ID_CAP_VER              (0xfUL<<16)
1875        #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA          (0xfUL<<20)
1876            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_8    (8UL<<20)
1877            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_9    (9UL<<20)
1878            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_10   (10UL<<20)
1879            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_11   (11UL<<20)
1880            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_12   (12UL<<20)
1881            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_13   (13UL<<20)
1882            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_14   (14UL<<20)
1883            #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_15   (15UL<<20)
1884
1885    u32_t pci_lower_ser_num;
1886        #define PCI_LOWER_SER_NUM_LOWER_SER_NUM             (0xffffffffUL<<0)
1887
1888    u32_t pci_upper_ser_num;
1889        #define PCI_UPPER_SER_NUM_UPPER_SER_NUM             (0xffffffffUL<<0)
1890
1891    u32_t pci_adv_err_cap;
1892        #define PCI_ADV_ERR_CAP_ECRC_CHK_CAP                (1UL<<0)
1893        #define PCI_ADV_ERR_CAP_ECRC_GEN_CAP                (1UL<<1)
1894
1895    u32_t pci_pwr_bdgt_data_0;
1896        #define PCI_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0         (0x1fffffUL<<0)
1897        #define PCI_PWR_BDGT_DATA_0_RESERVED                (0x7ffUL<<21)
1898
1899    u32_t pci_pwr_bdgt_data_1;
1900        #define PCI_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1         (0x1fffffUL<<0)
1901        #define PCI_PWR_BDGT_DATA_1_RW                      (0x7ffUL<<21)
1902
1903    u32_t pci_pwr_bdgt_data_2;
1904        #define PCI_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2         (0x1fffffUL<<0)
1905        #define PCI_PWR_BDGT_DATA_2_RW                      (0x7ffUL<<21)
1906
1907    u32_t pci_pwd_bdgt_data_3;
1908        #define PCI_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3         (0x1fffffUL<<0)
1909        #define PCI_PWD_BDGT_DATA_3_RW                      (0x7ffUL<<21)
1910
1911    u32_t pci_pwr_bdgt_data_4;
1912        #define PCI_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4         (0x1fffffUL<<0)
1913        #define PCI_PWR_BDGT_DATA_4_RW                      (0x7ffUL<<21)
1914
1915    u32_t pci_pwr_bdgt_data_5;
1916        #define PCI_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5         (0x1fffffUL<<0)
1917        #define PCI_PWR_BDGT_DATA_5_RW                      (0x7ffUL<<21)
1918
1919    u32_t pci_pwr_bdgt_data_6;
1920        #define PCI_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6         (0x1fffffUL<<0)
1921        #define PCI_PWR_BDGT_DATA_6_RW                      (0x7ffUL<<21)
1922
1923    u32_t pci_pwr_bdgt_data_7;
1924        #define PCI_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7         (0x1fffffUL<<0)
1925        #define PCI_PWR_BDGT_DATA_7_RW                      (0x7ffUL<<21)
1926
1927    u32_t unused_5[8];
1928    u32_t pci_pwr_bdgt_capability_ctl;
1929        #define PCI_PWR_BDGT_CAPABILITY_CTL_PWR_SYSTEM_ALLOC  (1UL<<0)
1930        #define PCI_PWR_BDGT_CAPABILITY_CTL_RESERVED        (0x7fffffffUL<<1)
1931
1932    u32_t unused_6[47];
1933    u32_t pci_grc_window1_addr;
1934        #define PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffUL<<13)
1935
1936    u32_t pci_grc_window2_addr;
1937        #define PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffUL<<13)
1938
1939    u32_t pci_grc_window3_addr;
1940        #define PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffUL<<13)
1941
1942    u32_t unused_7[9];
1943    u32_t pci_exp_rom_adr;
1944        #define PCI_EXP_ROM_ADR_ADDRESS                     (0x3fffffUL<<2)
1945        #define PCI_EXP_ROM_ADR_ADDR_SIZE                   (0x3UL<<24)
1946        #define PCI_EXP_ROM_ADR_REQ                         (1UL<<31)
1947
1948    u32_t pci_exp_rom_data0;
1949    u32_t pci_exp_rom_data1;
1950    u32_t pci_exp_rom_data2;
1951    u32_t pci_exp_rom_ctrl;
1952        #define PCI_EXP_ROM_CTRL_ENA                        (1UL<<0)
1953        #define PCI_EXP_ROM_CTRL_BFRD                       (1UL<<1)
1954        #define PCI_EXP_ROM_CTRL_ARB_NUM                    (0x3UL<<4)
1955        #define PCI_EXP_ROM_CTRL_STATE                      (0xfUL<<16)
1956        #define PCI_EXP_ROM_CTRL_CACHE_VALID                (1UL<<28)
1957        #define PCI_EXP_ROM_CTRL_ARB_TIMEOUT                (1UL<<29)
1958        #define PCI_EXP_ROM_CTRL_READ_TIMEOUT               (1UL<<30)
1959        #define PCI_EXP_ROM_CTRL_ACTIVE                     (1UL<<31)
1960
1961    u32_t pci_exp_rom_baddr;
1962        #define PCI_EXP_ROM_BADDR_VALUE                     (0x3fffffUL<<2)
1963
1964    u32_t pci_exp_rom_cfg;
1965        #define PCI_EXP_ROM_CFG_ARB_TIMEOUT_SHFT            (0xfUL<<0)
1966        #define PCI_EXP_ROM_CFG_READ_TIMEOUT_SHFT           (0xfUL<<4)
1967
1968    u32_t unused_8[41];
1969    u32_t pci_debug_vect_peek;
1970        #define PCI_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffUL<<0)
1971        #define PCI_DEBUG_VECT_PEEK_1_EN                    (1UL<<11)
1972        #define PCI_DEBUG_VECT_PEEK_1_SEL                   (0xfUL<<12)
1973        #define PCI_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffUL<<16)
1974        #define PCI_DEBUG_VECT_PEEK_2_EN                    (1UL<<27)
1975        #define PCI_DEBUG_VECT_PEEK_2_SEL                   (0xfUL<<28)
1976
1977    u32_t unused_9[63];
1978} pci_reg_t;
1979
1980
1981/*
1982 *  pcie_reg definition
1983 *  offset: 0x300000
1984 */
1985typedef struct pcie_reg
1986{
1987    u16_t pci1_cfg_device_id;
1988    u16_t pci1_cfg_vendor_id;
1989    u16_t pci1_cfg_status;
1990        #define PCI1_CFG_STATUS_RESERVED1                   (0x7<<0)
1991        #define PCI1_CFG_STATUS_INT_STATUS                  (1<<3)
1992        #define PCI1_CFG_STATUS_CAP_LIST                    (1<<4)
1993        #define PCI1_CFG_STATUS_66MHZ_CAP                   (1<<5)
1994        #define PCI1_CFG_STATUS_RESERVED2                   (1<<6)
1995        #define PCI1_CFG_STATUS_FAST_B2B_CAP                (1<<7)
1996        #define PCI1_CFG_STATUS_MSTR_PERR                   (1<<8)
1997        #define PCI1_CFG_STATUS_DEVSEL_TIMING               (0x3<<9)
1998        #define PCI1_CFG_STATUS_SIG_TGT_ABT                 (1<<11)
1999        #define PCI1_CFG_STATUS_RCV_TGT_ABT                 (1<<12)
2000        #define PCI1_CFG_STATUS_RCV_MSTR_ABT                (1<<13)
2001        #define PCI1_CFG_STATUS_SIG_SERR                    (1<<14)
2002        #define PCI1_CFG_STATUS_PAR_ERR                     (1<<15)
2003
2004    u16_t pci1_cfg_command;
2005        #define PCI1_CFG_COMMAND_IO_SPACE                   (1<<0)
2006        #define PCI1_CFG_COMMAND_MEM_SPACE                  (1<<1)
2007        #define PCI1_CFG_COMMAND_BUS_MASTER                 (1<<2)
2008        #define PCI1_CFG_COMMAND_SPECIAL_CYCLES             (1<<3)
2009        #define PCI1_CFG_COMMAND_MWI_CYCLES                 (1<<4)
2010        #define PCI1_CFG_COMMAND_VGA_SNOOP                  (1<<5)
2011        #define PCI1_CFG_COMMAND_PERR_ENA                   (1<<6)
2012        #define PCI1_CFG_COMMAND_STEPPING                   (1<<7)
2013        #define PCI1_CFG_COMMAND_SERR_ENA                   (1<<8)
2014        #define PCI1_CFG_COMMAND_FAST_B2B                   (1<<9)
2015        #define PCI1_CFG_COMMAND_INT_DISABLE                (1<<10)
2016        #define PCI1_CFG_COMMAND_RESERVED                   (0x1f<<11)
2017
2018    u32_t pci1_cfg_class_code;
2019        #define PCI1_CFG_CLASS_CODE_REV_ID                  (0xffUL<<0)
2020        #define PCI1_CFG_CLASS_CODE_VALUE                   (0xffffffUL<<8)
2021
2022    u8_t pci1_cfg_bist;
2023    u8_t pci1_cfg_header_type;
2024    u8_t pci1_cfg_latency_timer;
2025    u8_t pci1_cfg_cache_line_size;
2026    u32_t pci1_cfg_bar_1;
2027        #define PCI1_CFG_BAR_1_MEM_SPACE                    (1UL<<0)
2028        #define PCI1_CFG_BAR_1_SPACE_TYPE                   (0x3UL<<1)
2029        #define PCI1_CFG_BAR_1_PREFETCH                     (1UL<<3)
2030        #define PCI1_CFG_BAR_1_ADDRESS                      (0xfffffffUL<<4)
2031
2032    u32_t pci1_cfg_bar_2;
2033        #define PCI1_CFG_BAR_2_ADDR                         (0xffffffffUL<<0)
2034
2035    u32_t pci1_cfg_bar_3;
2036        #define PCI1_CFG_BAR_3_MEM_SPACE                    (1UL<<0)
2037        #define PCI1_CFG_BAR_3_SPACE_TYPE                   (0x3UL<<1)
2038        #define PCI1_CFG_BAR_3_PREFETCH                     (1UL<<3)
2039        #define PCI1_CFG_BAR_3_ADDRESS                      (0xfffffffUL<<4)
2040
2041    u32_t pci1_cfg_bar_4;
2042        #define PCI1_CFG_BAR_4_ADDR                         (0xffffffffUL<<0)
2043
2044    u32_t pci1_cfg_bar_5;
2045    u32_t pci1_cfg_bar_6;
2046    u32_t pci1_cfg_cardbus_cis;
2047    u16_t pci1_cfg_subsystem_id;
2048    u16_t pci1_cfg_subsystem_vendor_id;
2049    u32_t pci1_cfg_exp_rom_bar;
2050        #define PCI1_CFG_EXP_ROM_BAR_BAR_ENA                (1UL<<0)
2051        #define PCI1_CFG_EXP_ROM_BAR_LOW                    (0x3ffUL<<1)
2052        #define PCI1_CFG_EXP_ROM_BAR_SIZE                   (0x1fffUL<<11)
2053        #define PCI1_CFG_EXP_ROM_BAR_ADDRESS                (0xffUL<<24)
2054
2055    u16_t unused_0;
2056    u8_t unused_1;
2057    u8_t pci1_cfg_cap_pointer;
2058    u32_t unused_2;
2059    u8_t pci1_cfg_maximum_latency;
2060    u8_t pci1_cfg_min_grant;
2061    u8_t pci1_cfg_int_pin;
2062    u8_t pci1_cfg_int_line;
2063    u32_t unused_3[2];
2064    u16_t pci1_cfg_pm_capability;
2065        #define PCI1_CFG_PM_CAPABILITY_VERSION              (0x3<<0)
2066        #define PCI1_CFG_PM_CAPABILITY_CLOCK                (1<<3)
2067        #define PCI1_CFG_PM_CAPABILITY_RESERVED             (1<<4)
2068        #define PCI1_CFG_PM_CAPABILITY_DSI                  (1<<5)
2069        #define PCI1_CFG_PM_CAPABILITY_AUX_CURRENT          (0x7<<6)
2070        #define PCI1_CFG_PM_CAPABILITY_D1_SUPPORT           (1<<9)
2071        #define PCI1_CFG_PM_CAPABILITY_D2_SUPPORT           (1<<10)
2072        #define PCI1_CFG_PM_CAPABILITY_PME_IN_D0            (1<<11)
2073        #define PCI1_CFG_PM_CAPABILITY_PME_IN_D1            (1<<12)
2074        #define PCI1_CFG_PM_CAPABILITY_PME_IN_D2            (1<<13)
2075        #define PCI1_CFG_PM_CAPABILITY_PME_IN_D3_HOT        (1<<14)
2076        #define PCI1_CFG_PM_CAPABILITY_PME_IN_D3_COLD       (1<<15)
2077
2078    u8_t pci1_cfg_pm_next_cap_ptr;
2079    u8_t pci1_cfg_pm_cap_id;
2080    u8_t pci1_cfg_pm_data;
2081    u8_t pci1_cfg_pm_csr_bse;
2082    u16_t pci1_cfg_pm_csr;
2083        #define PCI1_CFG_PM_CSR_STATE                       (0x3<<0)
2084            #define PCI1_CFG_PM_CSR_STATE_D0                (0<<0)
2085            #define PCI1_CFG_PM_CSR_STATE_D1                (1<<0)
2086            #define PCI1_CFG_PM_CSR_STATE_D2                (2<<0)
2087            #define PCI1_CFG_PM_CSR_STATE_D3_HOT            (3<<0)
2088        #define PCI1_CFG_PM_CSR_RESERVED0                   (1<<2)
2089        #define PCI1_CFG_PM_CSR_NO_SOFT_RESET               (1<<3)
2090        #define PCI1_CFG_PM_CSR_RESERVED1                   (0xf<<4)
2091        #define PCI1_CFG_PM_CSR_PME_ENABLE                  (1<<8)
2092        #define PCI1_CFG_PM_CSR_DATA_SEL                    (0xf<<9)
2093            #define PCI1_CFG_PM_CSR_DATA_SEL_0              (0<<9)
2094            #define PCI1_CFG_PM_CSR_DATA_SEL_1              (1<<9)
2095            #define PCI1_CFG_PM_CSR_DATA_SEL_2              (2<<9)
2096            #define PCI1_CFG_PM_CSR_DATA_SEL_3              (3<<9)
2097            #define PCI1_CFG_PM_CSR_DATA_SEL_4              (4<<9)
2098            #define PCI1_CFG_PM_CSR_DATA_SEL_5              (5<<9)
2099            #define PCI1_CFG_PM_CSR_DATA_SEL_6              (6<<9)
2100            #define PCI1_CFG_PM_CSR_DATA_SEL_7              (7<<9)
2101        #define PCI1_CFG_PM_CSR_DATA_SCALE                  (0x3<<13)
2102            #define PCI1_CFG_PM_CSR_DATA_SCALE_0            (0<<13)
2103            #define PCI1_CFG_PM_CSR_DATA_SCALE_1            (1<<13)
2104            #define PCI1_CFG_PM_CSR_DATA_SCALE_2            (2<<13)
2105            #define PCI1_CFG_PM_CSR_DATA_SCALE_3            (3<<13)
2106        #define PCI1_CFG_PM_CSR_PME_STATUS                  (1<<15)
2107
2108    u16_t pci1_cfg_vpd_flag_addr;
2109        #define PCI1_CFG_VPD_FLAG_ADDR_ADDRESS              (0x1fff<<2)
2110        #define PCI1_CFG_VPD_FLAG_ADDR_FLAG                 (1<<15)
2111
2112    u8_t pci1_cfg_vpd_next_cap_ptr;
2113    u8_t pci1_cfg_vpd_cap_id;
2114    u32_t pci1_cfg_vpd_data;
2115    u16_t pci1_cfg_msi_control;
2116        #define PCI1_CFG_MSI_CONTROL_ENABLE                 (1<<0)
2117        #define PCI1_CFG_MSI_CONTROL_MCAP                   (0x7<<1)
2118            #define PCI1_CFG_MSI_CONTROL_MCAP_1             (0<<1)
2119            #define PCI1_CFG_MSI_CONTROL_MCAP_2             (1<<1)
2120            #define PCI1_CFG_MSI_CONTROL_MCAP_4             (2<<1)
2121            #define PCI1_CFG_MSI_CONTROL_MCAP_8             (3<<1)
2122            #define PCI1_CFG_MSI_CONTROL_MCAP_16            (4<<1)
2123            #define PCI1_CFG_MSI_CONTROL_MCAP_32            (5<<1)
2124        #define PCI1_CFG_MSI_CONTROL_MENA                   (0x7<<4)
2125            #define PCI1_CFG_MSI_CONTROL_MENA_1             (0<<4)
2126            #define PCI1_CFG_MSI_CONTROL_MENA_2             (1<<4)
2127            #define PCI1_CFG_MSI_CONTROL_MENA_4             (2<<4)
2128            #define PCI1_CFG_MSI_CONTROL_MENA_8             (3<<4)
2129            #define PCI1_CFG_MSI_CONTROL_MENA_16            (4<<4)
2130            #define PCI1_CFG_MSI_CONTROL_MENA_32            (5<<4)
2131        #define PCI1_CFG_MSI_CONTROL_64_BIT_ADDR_CAP        (1<<7)
2132        #define PCI1_CFG_MSI_CONTROL_MSI_PVMASK_CAPABLE     (1<<8)
2133
2134    u8_t pci1_cfg_msi_next_cap_ptr;
2135    u8_t pci1_cfg_msi_cap_id;
2136    u32_t pci1_cfg_msi_addr_l;
2137        #define PCI1_CFG_MSI_ADDR_L_VAL                     (0x3fffffffUL<<2)
2138
2139    u32_t pci1_cfg_msi_addr_h;
2140    u16_t unused_4;
2141    u16_t pci1_cfg_msi_data;
2142    u32_t pci1_cfg_misc_config;
2143        #define PCI1_CFG_MISC_CONFIG_TARGET_BYTE_SWAP       (1UL<<2)
2144        #define PCI1_CFG_MISC_CONFIG_TARGET_MB_WORD_SWAP    (1UL<<3)
2145        #define PCI1_CFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP   (1UL<<6)
2146        #define PCI1_CFG_MISC_CONFIG_REG_WINDOW_ENA         (1UL<<7)
2147        #define PCI1_CFG_MISC_CONFIG_GRC_WIN1_SWAP_EN       (1UL<<10)
2148        #define PCI1_CFG_MISC_CONFIG_GRC_WIN2_SWAP_EN       (1UL<<11)
2149        #define PCI1_CFG_MISC_CONFIG_GRC_WIN3_SWAP_EN       (1UL<<12)
2150        #define PCI1_CFG_MISC_CONFIG_ASIC_METAL_REV         (0xffUL<<16)
2151        #define PCI1_CFG_MISC_CONFIG_ASIC_BASE_REV          (0xfUL<<24)
2152        #define PCI1_CFG_MISC_CONFIG_ASIC_ID                (0xfUL<<28)
2153
2154    u32_t pci1_cfg_misc_status;
2155        #define PCI1_CFG_MISC_STATUS_INTA_VALUE             (1UL<<0)
2156        #define PCI1_CFG_MISC_STATUS_BAD_MEM_WRITE_BE       (1UL<<8)
2157
2158    u32_t unused_5[2];
2159    u32_t pci1_cfg_reg_window_address;
2160    u32_t unused_6;
2161    u32_t pci1_cfg_reg_window;
2162    u32_t pci1_cfg_int_ack_cmd;
2163        #define PCI1_CFG_INT_ACK_CMD_INDEX                  (0xffffUL<<0)
2164        #define PCI1_CFG_INT_ACK_CMD_INDEX_VALID            (1UL<<16)
2165        #define PCI1_CFG_INT_ACK_CMD_USE_INT_HC_PARAM       (1UL<<17)
2166        #define PCI1_CFG_INT_ACK_CMD_MASK_INT               (1UL<<18)
2167        #define PCI1_CFG_INT_ACK_CMD_INTERRUPT_NUM          (0xfUL<<24)
2168
2169    u32_t pci1_cfg_status_bit_set_cmd;
2170    u32_t pci1_cfg_status_bit_clear_cmd;
2171    u32_t pci1_cfg_mailbox_queue_addr;
2172    u32_t pci1_cfg_mailbox_queue_data;
2173    u32_t unused_7[2];
2174    u16_t pci1_cfg_msix_control;
2175        #define PCI1_CFG_MSIX_CONTROL_TABLE_SIZE            (0x7ff<<0)
2176        #define PCI1_CFG_MSIX_CONTROL_RESERVED              (0x7<<11)
2177        #define PCI1_CFG_MSIX_CONTROL_FUNC_MASK             (1<<14)
2178        #define PCI1_CFG_MSIX_CONTROL_MSIX_ENABLE           (1<<15)
2179
2180    u8_t pci1_cfg_msix_next_cap_ptr;
2181    u8_t pci1_cfg_msix_cap_id;
2182    u32_t pci1_cfg_msix_tbl_off_bir;
2183        #define PCI1_CFG_MSIX_TBL_OFF_BIR_TABLE_BIR         (0x7UL<<0)
2184        #define PCI1_CFG_MSIX_TBL_OFF_BIR_TABLE_OFFSET      (0x1fffffffUL<<3)
2185
2186    u32_t pci1_cfg_msix_pba_off_bir;
2187        #define PCI1_CFG_MSIX_PBA_OFF_BIR_PBA_BIR           (0x7UL<<0)
2188        #define PCI1_CFG_MSIX_PBA_OFF_BIR_PBA_OFFSET        (0x1fffffffUL<<3)
2189
2190    u16_t pci1_cfg_pcie_capability;
2191        #define PCI1_CFG_PCIE_CAPABILITY_VER                (0xf<<0)
2192        #define PCI1_CFG_PCIE_CAPABILITY_TYPE               (0xf<<4)
2193
2194    u8_t pci1_cfg_pcie_next_cap_ptr;
2195    u8_t pci1_cfg_pcie_cap_id;
2196    u32_t pci1_cfg_device_capability;
2197        #define PCI1_CFG_DEVICE_CAPABILITY_MAX_PAYLOAD      (0x7UL<<0)
2198        #define PCI1_CFG_DEVICE_CAPABILITY_PHANTOM_SUPPT    (0x3UL<<3)
2199        #define PCI1_CFG_DEVICE_CAPABILITY_EXT_TAG_SUPPT    (1UL<<5)
2200        #define PCI1_CFG_DEVICE_CAPABILITY_EP_L0S_ACCP_LAT  (0x7UL<<6)
2201        #define PCI1_CFG_DEVICE_CAPABILITY_EP_L1_ACCP_LAT   (0x7UL<<9)
2202
2203    u16_t pci1_cfg_device_status;
2204        #define PCI1_CFG_DEVICE_STATUS_CORR_ERR_DET         (1<<0)
2205        #define PCI1_CFG_DEVICE_STATUS_NON_FATAL_ERR_DET    (1<<1)
2206        #define PCI1_CFG_DEVICE_STATUS_FATAL_ERR_DET        (1<<2)
2207        #define PCI1_CFG_DEVICE_STATUS_UNSUP_REQ_DET        (1<<3)
2208        #define PCI1_CFG_DEVICE_STATUS_AUX_PWR_DET          (1<<4)
2209        #define PCI1_CFG_DEVICE_STATUS_NO_PEND              (1<<5)
2210
2211    u16_t pci1_cfg_device_control;
2212        #define PCI1_CFG_DEVICE_CONTROL_CORR_ERR_REP_ENA    (1<<0)
2213        #define PCI1_CFG_DEVICE_CONTROL_NON_FATAL_REP_ENA   (1<<1)
2214        #define PCI1_CFG_DEVICE_CONTROL_FATAL_REP_ENA       (1<<2)
2215        #define PCI1_CFG_DEVICE_CONTROL_UNSUP_REQ_ENA       (1<<3)
2216        #define PCI1_CFG_DEVICE_CONTROL_RELAX_ENA           (1<<4)
2217        #define PCI1_CFG_DEVICE_CONTROL_MAX_PAYLOAD         (0x7<<5)
2218        #define PCI1_CFG_DEVICE_CONTROL_EXT_TAG_ENA         (1<<8)
2219        #define PCI1_CFG_DEVICE_CONTROL_AUX_PWR_PM_ENA      (1<<10)
2220        #define PCI1_CFG_DEVICE_CONTROL_ENA_NO_SNOOP        (1<<11)
2221        #define PCI1_CFG_DEVICE_CONTROL_MAX_RD_REQ          (0x7<<12)
2222
2223    u32_t pci1_cfg_link_capability;
2224        #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED     (0xfUL<<0)
2225            #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5  (1UL<<0)
2226            #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED_5  (2UL<<0)
2227        #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH     (0x3fUL<<4)
2228            #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_1  (1UL<<4)
2229            #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_2  (2UL<<4)
2230            #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_4  (4UL<<4)
2231            #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_8  (8UL<<4)
2232        #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT          (0x3UL<<10)
2233            #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_RES_0  (0UL<<10)
2234            #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_L0S  (0UL<<10)
2235            #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_RES_2  (0UL<<10)
2236            #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_L0S_L1  (0UL<<10)
2237        #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT       (0x7UL<<12)
2238            #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT_1_2  (5UL<<12)
2239            #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT_2_4  (6UL<<12)
2240        #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT        (0x7UL<<15)
2241            #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT_1_2  (1UL<<15)
2242            #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT_2_4  (2UL<<15)
2243        #define PCI1_CFG_LINK_CAPABILITY_CLK_PWR_MGMT       (1UL<<18)
2244        #define PCI1_CFG_LINK_CAPABILITY_PORT_NUMBER        (0xffUL<<24)
2245
2246    u16_t pci1_cfg_link_status;
2247        #define PCI1_CFG_LINK_STATUS_SPEED                  (0xf<<0)
2248        #define PCI1_CFG_LINK_STATUS_NEG_LINK_WIDTH         (0x3f<<4)
2249        #define PCI1_CFG_LINK_STATUS_TRAINING_ERR           (1<<10)
2250        #define PCI1_CFG_LINK_STATUS_TRAINING               (1<<11)
2251        #define PCI1_CFG_LINK_STATUS_SLOT_CLK               (1<<12)
2252
2253    u16_t pci1_cfg_link_control;
2254        #define PCI1_CFG_LINK_CONTROL_ASPM_CTRL             (0x3<<0)
2255        #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND         (1<<3)
2256            #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND_64  (0<<3)
2257            #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND_128  (1<<3)
2258        #define PCI1_CFG_LINK_CONTROL_LINK_CR_COMMON_CLK    (1<<6)
2259        #define PCI1_CFG_LINK_CONTROL_LINK_CR_EXT_SYNC      (1<<7)
2260
2261    u32_t pci1_cfg_slot_capability;
2262    u16_t pci1_cfg_slot_status;
2263    u16_t pci1_cfg_slot_control;
2264    u16_t pci1_cfg_root_cap;
2265    u16_t pci1_cfg_root_control;
2266    u32_t pci1_cfg_root_status;
2267    u32_t pci1_cfg_device_capability_2;
2268        #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP  (0xfUL<<0)
2269            #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_ABCD  (15UL<<0)
2270        #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP  (1UL<<4)
2271
2272    u16_t pci1_cfg_device_status_2;
2273    u16_t pci1_cfg_device_control_2;
2274        #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE     (0xf<<0)
2275            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_50MS  (0<<0)
2276            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_100US  (1<<0)
2277            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_10MS  (2<<0)
2278            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_55MS  (3<<0)
2279            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_210MS  (4<<0)
2280            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_900MS  (5<<0)
2281            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_3_5S  (6<<0)
2282            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_13S  (7<<0)
2283            #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_64S  (8<<0)
2284        #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_DISABLE   (1<<4)
2285
2286    u32_t pci1_cfg_link_capability_2;
2287    u16_t pci1_cfg_link_status_2;
2288    u16_t pci1_cfg_link_control_2;
2289        #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED   (0xf<<0)
2290            #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED_2_5  (0<<0)
2291            #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED_5_0  (1<<0)
2292        #define PCI1_CFG_LINK_CONTROL_2_ENTER_COMPLIANCE    (1<<4)
2293        #define PCI1_CFG_LINK_CONTROL_2_HW_AUTO_SPEED_DISABLE  (1<<5)
2294        #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS      (1<<6)
2295            #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS_0  (0<<6)
2296            #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS_1  (1<<6)
2297        #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN           (0x7<<7)
2298            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_000   (0<<7)
2299            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_001   (1<<7)
2300            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_010   (2<<7)
2301            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_011   (3<<7)
2302            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_100   (4<<7)
2303            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_101   (5<<7)
2304            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_110   (6<<7)
2305            #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_111   (7<<7)
2306
2307    u32_t unused_8[8];
2308    u16_t pci1_cfg_device_ser_num_cap_off;
2309        #define PCI1_CFG_DEVICE_SER_NUM_CAP_OFF_VER         (0xf<<0)
2310        #define PCI1_CFG_DEVICE_SER_NUM_CAP_OFF_NEXT        (0xfff<<4)
2311
2312    u16_t pci1_cfg_device_ser_num_cap_id;
2313    u32_t pci1_cfg_lower_ser_num;
2314    u32_t pci1_cfg_upper_ser_num;
2315    u32_t unused_9;
2316    u16_t pci1_cfg_adv_err_cap_off;
2317        #define PCI1_CFG_ADV_ERR_CAP_OFF_VER                (0xf<<0)
2318        #define PCI1_CFG_ADV_ERR_CAP_OFF_NEXT               (0xfff<<4)
2319
2320    u16_t pci1_cfg_adv_err_cap_id;
2321    u32_t pci1_cfg_ucorr_err_status;
2322        #define PCI1_CFG_UCORR_ERR_STATUS_DLPES             (1UL<<4)
2323        #define PCI1_CFG_UCORR_ERR_STATUS_PTLPS             (1UL<<12)
2324        #define PCI1_CFG_UCORR_ERR_STATUS_FCPES             (1UL<<13)
2325        #define PCI1_CFG_UCORR_ERR_STATUS_CTS               (1UL<<14)
2326        #define PCI1_CFG_UCORR_ERR_STATUS_CAS               (1UL<<15)
2327        #define PCI1_CFG_UCORR_ERR_STATUS_UCS               (1UL<<16)
2328        #define PCI1_CFG_UCORR_ERR_STATUS_ROS               (1UL<<17)
2329        #define PCI1_CFG_UCORR_ERR_STATUS_MTLPS             (1UL<<18)
2330        #define PCI1_CFG_UCORR_ERR_STATUS_ECRCS             (1UL<<19)
2331        #define PCI1_CFG_UCORR_ERR_STATUS_URES              (1UL<<20)
2332
2333    u32_t pci1_cfg_ucorr_err_mask;
2334        #define PCI1_CFG_UCORR_ERR_MASK_DLPEM               (1UL<<4)
2335        #define PCI1_CFG_UCORR_ERR_MASK_SDEM                (1UL<<5)
2336        #define PCI1_CFG_UCORR_ERR_MASK_PTLPM               (1UL<<12)
2337        #define PCI1_CFG_UCORR_ERR_MASK_FCPEM               (1UL<<13)
2338        #define PCI1_CFG_UCORR_ERR_MASK_CTM                 (1UL<<14)
2339        #define PCI1_CFG_UCORR_ERR_MASK_CAM                 (1UL<<15)
2340        #define PCI1_CFG_UCORR_ERR_MASK_UCM                 (1UL<<16)
2341        #define PCI1_CFG_UCORR_ERR_MASK_ROM                 (1UL<<17)
2342        #define PCI1_CFG_UCORR_ERR_MASK_MTLPM               (1UL<<18)
2343        #define PCI1_CFG_UCORR_ERR_MASK_ECRCEM              (1UL<<19)
2344        #define PCI1_CFG_UCORR_ERR_MASK_UREM                (1UL<<20)
2345
2346    u32_t pci1_cfg_ucorr_err_sevr;
2347        #define PCI1_CFG_UCORR_ERR_SEVR_DLPES               (1UL<<4)
2348        #define PCI1_CFG_UCORR_ERR_SEVR_SDES                (1UL<<5)
2349        #define PCI1_CFG_UCORR_ERR_SEVR_PTLPS               (1UL<<12)
2350        #define PCI1_CFG_UCORR_ERR_SEVR_FCPES               (1UL<<13)
2351        #define PCI1_CFG_UCORR_ERR_SEVR_CTS                 (1UL<<14)
2352        #define PCI1_CFG_UCORR_ERR_SEVR_CAS                 (1UL<<15)
2353        #define PCI1_CFG_UCORR_ERR_SEVR_UCS                 (1UL<<16)
2354        #define PCI1_CFG_UCORR_ERR_SEVR_ROS                 (1UL<<17)
2355        #define PCI1_CFG_UCORR_ERR_SEVR_MTLPS               (1UL<<18)
2356        #define PCI1_CFG_UCORR_ERR_SEVR_ECRCES              (1UL<<19)
2357        #define PCI1_CFG_UCORR_ERR_SEVR_URES                (1UL<<20)
2358
2359    u32_t pci1_cfg_corr_err_status;