1*6716431bSRobert Mustacchi /* 2*6716431bSRobert Mustacchi * @(#)ax88172reg.h 1.1 09/06/15 3*6716431bSRobert Mustacchi * Macro definitions for ASIX AX88172 USB to fast ethernet controler 4*6716431bSRobert Mustacchi * based on ASIX AX88172/88772 data sheet 5*6716431bSRobert Mustacchi * This file is public domain. Coded by M.Murayama (KHF04453@nifty.com) 6*6716431bSRobert Mustacchi */ 7*6716431bSRobert Mustacchi 8*6716431bSRobert Mustacchi #ifndef __AX88172_H__ 9*6716431bSRobert Mustacchi #define __AX88172_H__ 10*6716431bSRobert Mustacchi 11*6716431bSRobert Mustacchi /* 12*6716431bSRobert Mustacchi * Vendor command definitions 13*6716431bSRobert Mustacchi */ 14*6716431bSRobert Mustacchi #define VCMD_READ_SRAM 0x02 15*6716431bSRobert Mustacchi #define VCMD_WRITE_RXSRAM 0x03 16*6716431bSRobert Mustacchi #define VCMD_WRITE_TXSRAM 0x04 17*6716431bSRobert Mustacchi #define VCMD_SOFTWARE_MII_OP 0x06 18*6716431bSRobert Mustacchi #define VCMD_READ_MII_REG 0x07 19*6716431bSRobert Mustacchi #define VCMD_WRITE_MII_REG 0x08 20*6716431bSRobert Mustacchi #define VCMD_READ_MII_OPMODE 0x09 21*6716431bSRobert Mustacchi #define VCMD_HARDWARE_MII_OP 0x0a 22*6716431bSRobert Mustacchi #define VCMD_READ_SROM 0x0b 23*6716431bSRobert Mustacchi #define VCMD_WRITE_SROM 0x0c 24*6716431bSRobert Mustacchi #define VCMD_WRITE_SROM_ENABLE 0x0d 25*6716431bSRobert Mustacchi #define VCMD_WRITE_SROM_DISABLE 0x0e 26*6716431bSRobert Mustacchi #define VCMD_READ_RXCTRL 0x0f 27*6716431bSRobert Mustacchi #define VCMD_WRITE_RXCTRL 0x10 28*6716431bSRobert Mustacchi #define VCMD_READ_IPGS 0x11 29*6716431bSRobert Mustacchi #define VCMD_WRITE_IPG 0x12 30*6716431bSRobert Mustacchi #define VCMD_WRITE_IPG1 0x13 31*6716431bSRobert Mustacchi #define VCMD_WRITE_IPG2 0x14 32*6716431bSRobert Mustacchi #define VCMD_READ_MCAST_FILTER 0x15 33*6716431bSRobert Mustacchi #define VCMD_WRITE_MCAST_FILTER 0x16 34*6716431bSRobert Mustacchi #define VCMD_READ_NODE_ID 0x17 35*6716431bSRobert Mustacchi #define VCMD_READ_PHY_IDS 0x19 36*6716431bSRobert Mustacchi #define VCMD_READ_MEDIUM_STATUS 0x1a 37*6716431bSRobert Mustacchi #define VCMD_WRITE_MEDIUM_STATUS 0x1b 38*6716431bSRobert Mustacchi #define VCMD_SET_MONITOR_MODE 0x1c 39*6716431bSRobert Mustacchi #define VCMD_GET_MONITOR_MODE 0x1d 40*6716431bSRobert Mustacchi #define VCMD_READ_GPIO 0x1e 41*6716431bSRobert Mustacchi #define VCMD_WRITE_GPIO 0x1f 42*6716431bSRobert Mustacchi 43*6716431bSRobert Mustacchi /* ax88772 only, currently not supported */ 44*6716431bSRobert Mustacchi #define VCMD_WRITE_IPGS_88772 0x12 45*6716431bSRobert Mustacchi #define VCMD_READ_NODE_ID_88772 0x13 46*6716431bSRobert Mustacchi #define VCMD_WRITE_NODE_ID_88772 0x14 47*6716431bSRobert Mustacchi #define VCMD_WRITE_TEST_REG_88772 0x17 48*6716431bSRobert Mustacchi #define VCMD_SOFTWARE_RESET_88772 0x20 49*6716431bSRobert Mustacchi #define VCMD_READ_PHY_SELECT_88772 0x21 50*6716431bSRobert Mustacchi #define VCMD_WRITE_PHY_SELECT_88772 0x22 51*6716431bSRobert Mustacchi 52*6716431bSRobert Mustacchi 53*6716431bSRobert Mustacchi /* 54*6716431bSRobert Mustacchi * Register definitions 55*6716431bSRobert Mustacchi */ 56*6716431bSRobert Mustacchi 57*6716431bSRobert Mustacchi /* Rx control register */ 58*6716431bSRobert Mustacchi #define RCR_SO 0x80 /* Start Operation */ 59*6716431bSRobert Mustacchi #define RCR_AP_88772 0x20 /* accept physical address from mcast filter */ 60*6716431bSRobert Mustacchi #define RCR_AM 0x10 /* accept multicast address */ 61*6716431bSRobert Mustacchi #define RCR_AB 0x08 /* accept broadcast address */ 62*6716431bSRobert Mustacchi #define RCR_SEP 0x04 /* save error packet */ 63*6716431bSRobert Mustacchi #define RCR_AMALL 0x02 /* accept all multicast address */ 64*6716431bSRobert Mustacchi #define RCR_PRO 0x01 /* promiscious, all frames received */ 65*6716431bSRobert Mustacchi 66*6716431bSRobert Mustacchi #define RCR_MFB 0x0300 67*6716431bSRobert Mustacchi #define RCR_MFB_SHIFT 8 68*6716431bSRobert Mustacchi #define RCR_MFB_2K (0U << RCR_MFB_SHIFT) 69*6716431bSRobert Mustacchi #define RCR_MFB_4K (1U << RCR_MFB_SHIFT) 70*6716431bSRobert Mustacchi #define RCR_MFB_8K (2U << RCR_MFB_SHIFT) 71*6716431bSRobert Mustacchi #define RCR_MFB_16K (3U << RCR_MFB_SHIFT) 72*6716431bSRobert Mustacchi 73*6716431bSRobert Mustacchi #define RCR_BITS \ 74*6716431bSRobert Mustacchi "\020" \ 75*6716431bSRobert Mustacchi "\010SO" \ 76*6716431bSRobert Mustacchi "\006AP" \ 77*6716431bSRobert Mustacchi "\005AM" \ 78*6716431bSRobert Mustacchi "\004AB" \ 79*6716431bSRobert Mustacchi "\003SEP" \ 80*6716431bSRobert Mustacchi "\002AMALL" \ 81*6716431bSRobert Mustacchi "\001PRO" 82*6716431bSRobert Mustacchi 83*6716431bSRobert Mustacchi /* Medium status register */ 84*6716431bSRobert Mustacchi #define MSR_SM 0x1000 /* super mac support */ 85*6716431bSRobert Mustacchi #define MSR_SBP 0x0800 /* stop backpressure */ 86*6716431bSRobert Mustacchi #define MSR_PS 0x0200 /* port speed in mii mode */ 87*6716431bSRobert Mustacchi #define MSR_RE 0x0100 /* rx enable */ 88*6716431bSRobert Mustacchi #define MSR_PF 0x0080 /* check only length/type for pause frame */ 89*6716431bSRobert Mustacchi #define MSR_JFE 0x0040 /* jumbo frame enable */ 90*6716431bSRobert Mustacchi #define MSR_TFC 0x0020 /* tx flow control enable */ 91*6716431bSRobert Mustacchi #define MSR_RFC 0x0010 /* rx flow control enable (178) */ 92*6716431bSRobert Mustacchi #define MSR_FCEN 0x0010 /* flow control enable (172/772) */ 93*6716431bSRobert Mustacchi #define MSR_ENCK 0x0008 /* Enable GTX_CLK and TXC clock output (178) */ 94*6716431bSRobert Mustacchi #define MSR_TXABT 0x0004 /* Tx abort allow, always set */ 95*6716431bSRobert Mustacchi #define MSR_FDPX 0x0002 /* full duplex */ 96*6716431bSRobert Mustacchi #define MSR_GM 0x0001 /* Gigabit mode (178) */ 97*6716431bSRobert Mustacchi 98*6716431bSRobert Mustacchi #define MSR_BITS \ 99*6716431bSRobert Mustacchi "\020" \ 100*6716431bSRobert Mustacchi "\015SM" \ 101*6716431bSRobert Mustacchi "\014SBP" \ 102*6716431bSRobert Mustacchi "\012PS" \ 103*6716431bSRobert Mustacchi "\011RE" \ 104*6716431bSRobert Mustacchi "\005FCEN" \ 105*6716431bSRobert Mustacchi "\004ENCK" \ 106*6716431bSRobert Mustacchi "\003TXABT" \ 107*6716431bSRobert Mustacchi "\002FDPX" \ 108*6716431bSRobert Mustacchi "\001GM" 109*6716431bSRobert Mustacchi 110*6716431bSRobert Mustacchi /* monitor mode register */ 111*6716431bSRobert Mustacchi #define MMR_RWMP 0x04 /* remote wakeup by magic pkt */ 112*6716431bSRobert Mustacchi #define MMR_RWLU 0x02 /* remote wakeup by linkup */ 113*6716431bSRobert Mustacchi #define MMR_MOM 0x01 /* monitor mode 1:en, 0:dis */ 114*6716431bSRobert Mustacchi 115*6716431bSRobert Mustacchi #define MMR_BITS \ 116*6716431bSRobert Mustacchi "\020" \ 117*6716431bSRobert Mustacchi "\003RWMP" \ 118*6716431bSRobert Mustacchi "\002RWLU" \ 119*6716431bSRobert Mustacchi "\001MOM" 120*6716431bSRobert Mustacchi 121*6716431bSRobert Mustacchi /* GPIO register */ 122*6716431bSRobert Mustacchi #define GPIO_RSE 0x80 /* reload serial eeprom (88772) */ 123*6716431bSRobert Mustacchi #define GPIO_DATA2 0x20 124*6716431bSRobert Mustacchi #define GPIO_EN2 0x10 125*6716431bSRobert Mustacchi #define GPIO_DATA1 0x08 126*6716431bSRobert Mustacchi #define GPIO_EN1 0x04 127*6716431bSRobert Mustacchi #define GPIO_DATA0 0x02 128*6716431bSRobert Mustacchi #define GPIO_EN0 0x01 129*6716431bSRobert Mustacchi 130*6716431bSRobert Mustacchi #define GPIO_BITS \ 131*6716431bSRobert Mustacchi "\020" \ 132*6716431bSRobert Mustacchi "\010RSE" \ 133*6716431bSRobert Mustacchi "\006DATA2" \ 134*6716431bSRobert Mustacchi "\005EN2" \ 135*6716431bSRobert Mustacchi "\004DATA1" \ 136*6716431bSRobert Mustacchi "\003EN1" \ 137*6716431bSRobert Mustacchi "\002DATA0" \ 138*6716431bSRobert Mustacchi "\001EN0" 139*6716431bSRobert Mustacchi 140*6716431bSRobert Mustacchi /* Software reset register */ 141*6716431bSRobert Mustacchi #define SWRST_IPPD 0x40 /* internal phy power down control */ 142*6716431bSRobert Mustacchi #define SWRST_IPRL 0x20 /* internal phy reset control */ 143*6716431bSRobert Mustacchi #define SWRST_BZ 0x10 /* force Bulk In to return zero-length pkt */ 144*6716431bSRobert Mustacchi #define SWRST_PRL 0x08 /* external phy reset pin level */ 145*6716431bSRobert Mustacchi #define SWRST_PRTE 0x04 /* external phy tri-state enable */ 146*6716431bSRobert Mustacchi #define SWRST_RT 0x02 /* clear frame length error for Bulk-Out */ 147*6716431bSRobert Mustacchi #define SWRST_RR 0x01 /* clear frame length error for Bulk-In */ 148*6716431bSRobert Mustacchi 149*6716431bSRobert Mustacchi #define SWRST_BITS \ 150*6716431bSRobert Mustacchi "\020" \ 151*6716431bSRobert Mustacchi "\007IPPD" \ 152*6716431bSRobert Mustacchi "\006IPRL" \ 153*6716431bSRobert Mustacchi "\005BZ" \ 154*6716431bSRobert Mustacchi "\004PRL" \ 155*6716431bSRobert Mustacchi "\003PRTE" \ 156*6716431bSRobert Mustacchi "\002RT" \ 157*6716431bSRobert Mustacchi "\001RR" 158*6716431bSRobert Mustacchi 159*6716431bSRobert Mustacchi /* Software PHY Select Status register */ 160*6716431bSRobert Mustacchi #define SPSS_ASEL 0x02 /* 1:auto select 0:manual select */ 161*6716431bSRobert Mustacchi #define SPSS_PSEL 0x01 /* 1:intenal phy, 0:external (when ASEL=0) */ 162*6716431bSRobert Mustacchi 163*6716431bSRobert Mustacchi #endif /* __AX88172_H__ */ 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