188447a05SGarrett D'Amore /* 288447a05SGarrett D'Amore * CDDL HEADER START 388447a05SGarrett D'Amore * 488447a05SGarrett D'Amore * The contents of this file are subject to the terms of the 588447a05SGarrett D'Amore * Common Development and Distribution License (the "License"). 688447a05SGarrett D'Amore * You may not use this file except in compliance with the License. 788447a05SGarrett D'Amore * 888447a05SGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 988447a05SGarrett D'Amore * or http://www.opensolaris.org/os/licensing. 1088447a05SGarrett D'Amore * See the License for the specific language governing permissions 1188447a05SGarrett D'Amore * and limitations under the License. 1288447a05SGarrett D'Amore * 1388447a05SGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each 1488447a05SGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1588447a05SGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the 1688447a05SGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying 1788447a05SGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner] 1888447a05SGarrett D'Amore * 1988447a05SGarrett D'Amore * CDDL HEADER END 2088447a05SGarrett D'Amore */ 2188447a05SGarrett D'Amore 2288447a05SGarrett D'Amore /* 23*68c47f65SGarrett D'Amore * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 2488447a05SGarrett D'Amore * Use is subject to license terms. 2588447a05SGarrett D'Amore */ 2688447a05SGarrett D'Amore 2788447a05SGarrett D'Amore /* 2888447a05SGarrett D'Amore * Purpose: Definitions for the via8233 driver 2988447a05SGarrett D'Amore */ 3088447a05SGarrett D'Amore /* 3188447a05SGarrett D'Amore * This file is part of Open Sound System 3288447a05SGarrett D'Amore * 3388447a05SGarrett D'Amore * Copyright (C) 4Front Technologies 1996-2008. 3488447a05SGarrett D'Amore * 3588447a05SGarrett D'Amore * This software is released under CDDL 1.0 source license. 3688447a05SGarrett D'Amore * See the COPYING file included in the main directory of this source 3788447a05SGarrett D'Amore * distribution for the license terms and conditions. 3888447a05SGarrett D'Amore */ 3988447a05SGarrett D'Amore #ifndef AUDIOVIA823X_H 4088447a05SGarrett D'Amore #define AUDIOVIA823X_H 4188447a05SGarrett D'Amore 4288447a05SGarrett D'Amore #define AUVIA_NAME "audiovia823x" 4388447a05SGarrett D'Amore 4488447a05SGarrett D'Amore #define VIA_VENDOR_ID 0x1106 4588447a05SGarrett D'Amore #define VIA_8233_ID 0x3059 4688447a05SGarrett D'Amore #define VIA_8233A_ID 0x7059 4788447a05SGarrett D'Amore 4888447a05SGarrett D'Amore /* pci configuration registers */ 4988447a05SGarrett D'Amore #define AUVIA_PCICFG 0x40 /* Via chip specific cfg reg */ 5088447a05SGarrett D'Amore #define AUVIA_PCICFG_LEGACY 0x00ff0000 /* legacy enables mask */ 5188447a05SGarrett D'Amore #define AUVIA_PCICFG_ACLINKEN 0x00008000 /* AC'97 link enable */ 5288447a05SGarrett D'Amore #define AUVIA_PCICFG_NRST 0x00004000 /* inverse of AC'97 reset */ 5388447a05SGarrett D'Amore #define AUVIA_PCICFG_ACSYNC 0x00002000 /* AC'97 sync */ 5488447a05SGarrett D'Amore #define AUVIA_PCICFG_SRCEN 0x00000800 /* sample rate converter en */ 5588447a05SGarrett D'Amore #define AUVIA_PCICFG_SGDEN 0x00000400 /* SGD enable */ 5688447a05SGarrett D'Amore #define AUVIA_PCICFG_FMEN 0x00000200 /* FM synth enable (legacy) */ 5788447a05SGarrett D'Amore #define AUVIA_PCICFG_SBEN 0x00000100 /* SB compat enable (legacy) */ 5888447a05SGarrett D'Amore #define AUVIA_PCICFG_PRIVALID 0x00000001 /* primary codec ready */ 5988447a05SGarrett D'Amore 6088447a05SGarrett D'Amore #define AUVIA_PLAY_SGD_NUM 1 6188447a05SGarrett D'Amore #define AUVIA_REC_SGD_NUM 0 6288447a05SGarrett D'Amore #define AUVIA_NUM_PORTC 2 6388447a05SGarrett D'Amore #define AUVIA_NUM_SGD 16 /* number of fragments */ 6488447a05SGarrett D'Amore 6588447a05SGarrett D'Amore #define AUVIA_SGD_EOL 0x80000000 6688447a05SGarrett D'Amore #define AUVIA_SGD_FLAG 0x40000000 6788447a05SGarrett D'Amore 6888447a05SGarrett D'Amore #define CODEC_TIMEOUT_COUNT 500 6988447a05SGarrett D'Amore 7088447a05SGarrett D'Amore #define REG_PLAYBASE 0x40 /* Multichannel SGD */ 7188447a05SGarrett D'Amore #define REG_RECBASE 0x60 7288447a05SGarrett D'Amore #define REG_CODEC 0x80 /* Access AC97 Codec */ 7388447a05SGarrett D'Amore #define REG_GSTAT 0x84 /* Global status */ 7488447a05SGarrett D'Amore 7588447a05SGarrett D'Amore /* REG_CODEC */ 7688447a05SGarrett D'Amore #define CODEC_IN_CMD 0x01000000 /* busy in sending */ 7788447a05SGarrett D'Amore #define CODEC_STA_VALID 0x02000000 /* 1:status data is valid */ 7888447a05SGarrett D'Amore #define CODEC_RD 0x00800000 /* Read CODEC status */ 7988447a05SGarrett D'Amore #define CODEC_WR 0x00000000 /* Write CODEC status */ 8088447a05SGarrett D'Amore #define CODEC_INDEX 0x007F0000 /* Index of command register */ 8188447a05SGarrett D'Amore #define CODEC_DATA 0x0000FFFF /* AC97 status register data */ 8288447a05SGarrett D'Amore 8388447a05SGarrett D'Amore /* registers that are offsets relative to a port */ 8488447a05SGarrett D'Amore #define OFF_STATUS 0x00 8588447a05SGarrett D'Amore #define OFF_CTRL 0x01 8688447a05SGarrett D'Amore #define OFF_PLAYFMT 0x02 8788447a05SGarrett D'Amore #define OFF_RECFIFO 0x02 8888447a05SGarrett D'Amore #define OFF_DMA 0x04 8988447a05SGarrett D'Amore #define OFF_CHANNELS 0x08 9088447a05SGarrett D'Amore #define OFF_RECFMT 0x08 9188447a05SGarrett D'Amore #define OFF_COUNT 0x0C 9288447a05SGarrett D'Amore 9388447a05SGarrett D'Amore /* bits for above offsets */ 9488447a05SGarrett D'Amore #define STATUS_INTR 0x3 9588447a05SGarrett D'Amore 9688447a05SGarrett D'Amore #define CTRL_START 0x80 9788447a05SGarrett D'Amore #define CTRL_TERMINATE 0x40 9888447a05SGarrett D'Amore #define CTRL_AUTOSTART 0x20 9988447a05SGarrett D'Amore #define CTRL_MULTICHORDER 0x10 /* SGD 0x40 only, Center/LFE order */ 10088447a05SGarrett D'Amore #define CTRL_FLAG 0x01 10188447a05SGarrett D'Amore 10288447a05SGarrett D'Amore #define PLAYFMT_16BIT 0x80 10388447a05SGarrett D'Amore #define PLAYFMT_STEREO 0x20 /* Num channels (1-6), upper nybble */ 10488447a05SGarrett D'Amore #define PLAYFMT_6CH 0x60 10588447a05SGarrett D'Amore #define PLAYFMT_4CH 0x40 10688447a05SGarrett D'Amore 10788447a05SGarrett D'Amore #define RECFIFO_ENABLE 0x40 10888447a05SGarrett D'Amore 10988447a05SGarrett D'Amore #define RECFMT_48K 0x00ffffff 11088447a05SGarrett D'Amore #define RECFMT_STEREO 0x00100000 11188447a05SGarrett D'Amore #define RECFMT_16BIT 0x00200000 11288447a05SGarrett D'Amore 11388447a05SGarrett D'Amore 11488447a05SGarrett D'Amore typedef struct { 11588447a05SGarrett D'Amore unsigned int phaddr; 11688447a05SGarrett D'Amore unsigned int flags; 11788447a05SGarrett D'Amore } SGD_entry; 11888447a05SGarrett D'Amore 11988447a05SGarrett D'Amore typedef struct auvia_portc auvia_portc_t; 12088447a05SGarrett D'Amore typedef struct auvia_devc auvia_devc_t; 12188447a05SGarrett D'Amore 12288447a05SGarrett D'Amore struct auvia_portc { 12388447a05SGarrett D'Amore auvia_devc_t *devc; 12488447a05SGarrett D'Amore audio_engine_t *engine; 12588447a05SGarrett D'Amore caddr_t base; /* base for registers */ 12688447a05SGarrett D'Amore int nchan; 12788447a05SGarrett D'Amore 12888447a05SGarrett D'Amore ddi_dma_handle_t sgd_dmah; /* dma for descriptors */ 12988447a05SGarrett D'Amore ddi_acc_handle_t sgd_acch; 13088447a05SGarrett D'Amore uint32_t sgd_paddr; 13188447a05SGarrett D'Amore caddr_t sgd_kaddr; 13288447a05SGarrett D'Amore 13388447a05SGarrett D'Amore ddi_dma_handle_t buf_dmah; /* dma for buffers */ 13488447a05SGarrett D'Amore ddi_acc_handle_t buf_acch; 13588447a05SGarrett D'Amore uint32_t buf_paddr; 13688447a05SGarrett D'Amore caddr_t buf_kaddr; 13788447a05SGarrett D'Amore size_t buf_size; 13888447a05SGarrett D'Amore int syncdir; 13988447a05SGarrett D'Amore 140*68c47f65SGarrett D'Amore unsigned nframes; 141*68c47f65SGarrett D'Amore unsigned pos; 14288447a05SGarrett D'Amore 14388447a05SGarrett D'Amore uint64_t count; 14488447a05SGarrett D'Amore 14588447a05SGarrett D'Amore /* helper functions */ 14688447a05SGarrett D'Amore void (*reset)(auvia_portc_t *); 14788447a05SGarrett D'Amore }; 14888447a05SGarrett D'Amore 14988447a05SGarrett D'Amore 15088447a05SGarrett D'Amore struct auvia_devc { 15188447a05SGarrett D'Amore dev_info_t *dip; 15288447a05SGarrett D'Amore audio_dev_t *adev; 15388447a05SGarrett D'Amore ac97_t *ac97; 15488447a05SGarrett D'Amore 15588447a05SGarrett D'Amore char *chip_name; 15688447a05SGarrett D'Amore int chip_type; 15788447a05SGarrett D'Amore #define CHIP_8233 0 15888447a05SGarrett D'Amore #define CHIP_8233A 1 15988447a05SGarrett D'Amore 16088447a05SGarrett D'Amore /* registers */ 16188447a05SGarrett D'Amore ddi_acc_handle_t pcih; 16288447a05SGarrett D'Amore ddi_acc_handle_t regsh; 16388447a05SGarrett D'Amore caddr_t base; 16488447a05SGarrett D'Amore 16588447a05SGarrett D'Amore auvia_portc_t *portc[AUVIA_NUM_PORTC]; 16688447a05SGarrett D'Amore }; 16788447a05SGarrett D'Amore 16888447a05SGarrett D'Amore #define AUVIA_KIOP(X) ((kstat_intr_t *)(X->ksp->ks_data)) 16988447a05SGarrett D'Amore 17088447a05SGarrett D'Amore #define INL(devc, reg) ddi_get32(devc->regsh, (void *)(reg)) 17188447a05SGarrett D'Amore 17288447a05SGarrett D'Amore #define INB(devc, reg) ddi_get8(devc->regsh, (void *)(reg)) 17388447a05SGarrett D'Amore 17488447a05SGarrett D'Amore #define OUTL(devc, reg, val) ddi_put32(devc->regsh, (void *)(reg), (val)) 17588447a05SGarrett D'Amore 17688447a05SGarrett D'Amore #define OUTB(devc, reg, val) ddi_put8(devc->regsh, (void *)(reg), (val)) 17788447a05SGarrett D'Amore 17888447a05SGarrett D'Amore #endif /* AUDIOVIA823X_H */ 179