148722b5fSGarrett D'Amore /*
248722b5fSGarrett D'Amore  * CDDL HEADER START
348722b5fSGarrett D'Amore  *
448722b5fSGarrett D'Amore  * The contents of this file are subject to the terms of the
548722b5fSGarrett D'Amore  * Common Development and Distribution License (the "License").
648722b5fSGarrett D'Amore  * You may not use this file except in compliance with the License.
748722b5fSGarrett D'Amore  *
848722b5fSGarrett D'Amore  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
948722b5fSGarrett D'Amore  * or http://www.opensolaris.org/os/licensing.
1048722b5fSGarrett D'Amore  * See the License for the specific language governing permissions
1148722b5fSGarrett D'Amore  * and limitations under the License.
1248722b5fSGarrett D'Amore  *
1348722b5fSGarrett D'Amore  * When distributing Covered Code, include this CDDL HEADER in each
1448722b5fSGarrett D'Amore  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1548722b5fSGarrett D'Amore  * If applicable, add the following below this CDDL HEADER, with the
1648722b5fSGarrett D'Amore  * fields enclosed by brackets "[]" replaced with your own identifying
1748722b5fSGarrett D'Amore  * information: Portions Copyright [yyyy] [name of copyright owner]
1848722b5fSGarrett D'Amore  *
1948722b5fSGarrett D'Amore  * CDDL HEADER END
2048722b5fSGarrett D'Amore  */
2148722b5fSGarrett D'Amore 
2248722b5fSGarrett D'Amore /*
23*68c47f65SGarrett D'Amore  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
2448722b5fSGarrett D'Amore  * Use is subject to license terms.
2548722b5fSGarrett D'Amore  */
2648722b5fSGarrett D'Amore 
2748722b5fSGarrett D'Amore /*
2848722b5fSGarrett D'Amore  * Purpose: Definitions for the Creative Audigy LS driver
2948722b5fSGarrett D'Amore  */
3048722b5fSGarrett D'Amore /*
3148722b5fSGarrett D'Amore  * This file is part of Open Sound System
3248722b5fSGarrett D'Amore  *
3348722b5fSGarrett D'Amore  * Copyright (C) 4Front Technologies 1996-2009.
3448722b5fSGarrett D'Amore  *
3548722b5fSGarrett D'Amore  * This software is released under CDDL 1.0 source license.
3648722b5fSGarrett D'Amore  * See the COPYING file included in the main directory of this source
3748722b5fSGarrett D'Amore  * distribution for the license terms and conditions.
3848722b5fSGarrett D'Amore  */
3948722b5fSGarrett D'Amore #ifndef	AUDIGYLS_H
4048722b5fSGarrett D'Amore #define	AUDIGYLS_H
4148722b5fSGarrett D'Amore 
4248722b5fSGarrett D'Amore #define	AUDIGYLS_NAME		"audiols"
4348722b5fSGarrett D'Amore 
4448722b5fSGarrett D'Amore #define	AUDIGYLS_NUM_PORT	2
4548722b5fSGarrett D'Amore #define	AUDIGYLS_PLAY_PORT	0
4648722b5fSGarrett D'Amore #define	AUDIGYLS_REC_PORT	1
4748722b5fSGarrett D'Amore 
4848722b5fSGarrett D'Amore #define	PCI_VENDOR_ID_CREATIVE 		0x1102
4948722b5fSGarrett D'Amore #define	PCI_DEVICE_ID_CREATIVE_AUDIGYLS 0x0007
5048722b5fSGarrett D'Amore 
5148722b5fSGarrett D'Amore /*
5248722b5fSGarrett D'Amore  * PCI registers
5348722b5fSGarrett D'Amore  */
5448722b5fSGarrett D'Amore 
5548722b5fSGarrett D'Amore #define	PR 	0x00
5648722b5fSGarrett D'Amore #define	DR	0x04
5748722b5fSGarrett D'Amore #define	IPR	0x08
5848722b5fSGarrett D'Amore #define	IER	0x0C
5948722b5fSGarrett D'Amore #define		INTR_PCI	(1 << 0)
6048722b5fSGarrett D'Amore #define		INTR_TXA	(1 << 1)	/* midi-a tx */
6148722b5fSGarrett D'Amore #define		INTR_RXA	(1 << 2)	/* midi-a rx */
6248722b5fSGarrett D'Amore #define		INTR_IT2	(1 << 3)	/* timer 2, 44.1 kHz */
6348722b5fSGarrett D'Amore #define		INTR_IT1	(1 << 4)	/* timer 1, 192 kHz */
6448722b5fSGarrett D'Amore #define		INTR_SS_	(1 << 5)	/* spdif status */
6548722b5fSGarrett D'Amore #define		INTR_SRT	(1 << 6)	/* sample rate status */
6648722b5fSGarrett D'Amore #define		INTR_GP		(1 << 7)
6748722b5fSGarrett D'Amore #define		INTR_AI		(1 << 8)	/* audio pending interrupt */
6848722b5fSGarrett D'Amore #define		INTR_I2CDAC	(1 << 9)
6948722b5fSGarrett D'Amore #define		INTR_I2CEE	(1 << 10)
7048722b5fSGarrett D'Amore #define		INTR_SPI	(1 << 11)
7148722b5fSGarrett D'Amore #define		INTR_SPF	(1 << 12)
7248722b5fSGarrett D'Amore #define		INTR_SUO	(1 << 13)
7348722b5fSGarrett D'Amore #define		INTR_SUI	(1 << 14)
7448722b5fSGarrett D'Amore #define		INTR_TXB	(1 << 16)	/* midi-b tx */
7548722b5fSGarrett D'Amore #define		INTR_RXB	(1 << 17)	/* midi-b rx */
7648722b5fSGarrett D'Amore 
7748722b5fSGarrett D'Amore #define	HC	0x14
7848722b5fSGarrett D'Amore #define		HC_PF		(1 << 11)	/* play fmt 1 = 32b, 0 = 16b */
7948722b5fSGarrett D'Amore #define		HC_RF		(1 << 10)	/* rec fmt 1 = 32b, 0 = 16b */
8048722b5fSGarrett D'Amore #define		HC_AC97		(1 << 3)
8148722b5fSGarrett D'Amore #define		HC_AEN		(1 << 0)	/* audio enable */
8248722b5fSGarrett D'Amore 
8348722b5fSGarrett D'Amore #define	GPIO	0x18
8448722b5fSGarrett D'Amore #define	AC97D	0x1C
8548722b5fSGarrett D'Amore #define	AC97A	0x1E
8648722b5fSGarrett D'Amore /*
8748722b5fSGarrett D'Amore  * Indirect registers
8848722b5fSGarrett D'Amore  */
8948722b5fSGarrett D'Amore 
9048722b5fSGarrett D'Amore #define	PTBA		0x000	/* gather play table base address */
9148722b5fSGarrett D'Amore #define	PTBS		0x001	/* gather play table buffer size */
9248722b5fSGarrett D'Amore #define	PTCA		0x002	/* gather play table current addr ptr */
9348722b5fSGarrett D'Amore #define	PFBA		0x004	/* play fifo base address */
9448722b5fSGarrett D'Amore #define	PFBS		0x005	/* play fifo buffer size */
9548722b5fSGarrett D'Amore #define	CPFA		0x006	/* current play fifo address */
9648722b5fSGarrett D'Amore #define	PFEA		0x007	/* play fifo end address */
9748722b5fSGarrett D'Amore #define	CPCAV		0x008	/* current play fifo offset/cache sz valid */
9848722b5fSGarrett D'Amore #define	RFBA		0x010	/* record fifo base address */
9948722b5fSGarrett D'Amore #define	RFBS		0x011	/* record fifo buffer size */
10048722b5fSGarrett D'Amore #define	CRFA		0x012	/* current record fifo address */
10148722b5fSGarrett D'Amore #define	CRCAV		0x013	/* current record fifo offset/cache sz valid */
10248722b5fSGarrett D'Amore #define	CDL		0x020	/* play fifo cache data, 0x20-0x2f */
10348722b5fSGarrett D'Amore #define	SA		0x040	/* start audio */
10448722b5fSGarrett D'Amore #define	SCS3		0x041
10548722b5fSGarrett D'Amore #define	SCS0		0x042
10648722b5fSGarrett D'Amore #define	SCS1		0x043
10748722b5fSGarrett D'Amore #define	SCS2		0x044
10848722b5fSGarrett D'Amore #define	SPC		0x045	/* spdif output control */
10948722b5fSGarrett D'Amore #define	WMARK		0x046	/* test purposes only */
11048722b5fSGarrett D'Amore #define	SPSC		0x049	/* spdif input control */
11148722b5fSGarrett D'Amore #define	RCD		0x050	/* record cache data, 0x50-0x5f */
11248722b5fSGarrett D'Amore #define	P17RECSEL	0x060	/* record fifo map address */
11348722b5fSGarrett D'Amore #define	P17RECVOLL	0x061	/* record fifo volume control (lo) */
11448722b5fSGarrett D'Amore #define	P17RECVOLH	0x062	/* record fifo volume control (hi) */
11548722b5fSGarrett D'Amore 
11648722b5fSGarrett D'Amore #define	HMIXMAP_SPDIF	0x063	/* spdif router map address */
11748722b5fSGarrett D'Amore #define	SMIXMAP_SPDIF	0x064	/* spdif router map address */
11848722b5fSGarrett D'Amore #define	MIXCTL_SPDIF	0x065	/* spdif mixer control */
11948722b5fSGarrett D'Amore #define	MIXVOL_SPDIF	0x066	/* spdif mixer input volume control */
12048722b5fSGarrett D'Amore #define	HMIXMAP_I2S	0x067	/* i2s router map address */
12148722b5fSGarrett D'Amore #define	SMIXMAP_I2S	0x068	/* i2s router map address */
12248722b5fSGarrett D'Amore #define	MIXCTL_I2S	0x069	/* i2s mixer control */
12348722b5fSGarrett D'Amore #define	MIXVOL_I2S	0x06a	/* i2s mixer input volume control */
12448722b5fSGarrett D'Amore 
12548722b5fSGarrett D'Amore /* MIDI UART */
12648722b5fSGarrett D'Amore #define	MUDATA		0x06c	/* midi uart a data */
12748722b5fSGarrett D'Amore #define	MUCMDA		0x06d	/* midi uart a command/status */
12848722b5fSGarrett D'Amore #define	MUDATB		0x06e	/* midi uart b data */
12948722b5fSGarrett D'Amore #define	MUCMDB		0x06f	/* midi uart b command/status */
13048722b5fSGarrett D'Amore 
13148722b5fSGarrett D'Amore #define	SRT		0x070	/* sample rate tracker status */
13248722b5fSGarrett D'Amore #define	SRCTL		0x071	/* sample rate control */
13348722b5fSGarrett D'Amore #define	AUDCTL		0x072	/* audio output control */
13448722b5fSGarrett D'Amore #define	CHIP_ID		0x074	/* chip id */
13548722b5fSGarrett D'Amore #define	AIE		0x075	/* audio interrupt enable */
13648722b5fSGarrett D'Amore #define	AIP		0x076	/* audio interrupt */
13748722b5fSGarrett D'Amore #define	WALL192		0x077	/* wall clock @ 192 kHz */
13848722b5fSGarrett D'Amore #define	WALL441		0x078	/* wall clock @ 44.1 kHz */
13948722b5fSGarrett D'Amore #define	IT		0x079	/* interval timer */
14048722b5fSGarrett D'Amore #define	SPI		0x07a	/* spi interface */
14148722b5fSGarrett D'Amore #define	I2C_A		0x07b	/* i2c address */
14248722b5fSGarrett D'Amore #define	I2C_0		0x07c	/* i2c data */
14348722b5fSGarrett D'Amore #define	I2C_1		0x07d	/* i2c data */
14448722b5fSGarrett D'Amore 
14548722b5fSGarrett D'Amore /*
14648722b5fSGarrett D'Amore  * Audio interrupt bits
14748722b5fSGarrett D'Amore  */
14848722b5fSGarrett D'Amore 
14948722b5fSGarrett D'Amore #define	AI_PFH		0x00000001	/* playback fifo half loop */
15048722b5fSGarrett D'Amore #define	AI_PFF		0x00000010	/* playback fifo loop */
15148722b5fSGarrett D'Amore #define	AI_TFH		0x00000100	/* playback table half loop */
15248722b5fSGarrett D'Amore #define	AI_TFF		0x00001000	/* playback table loop */
15348722b5fSGarrett D'Amore #define	AI_RFH		0x00010000	/* capture table half loop */
15448722b5fSGarrett D'Amore #define	AI_RFF		0x00100000	/* capture fifo loop */
15548722b5fSGarrett D'Amore #define	AI_EAI		0x01000000	/* enables audio end interrupt */
15648722b5fSGarrett D'Amore 
15748722b5fSGarrett D'Amore #define	SA_48K		0
15848722b5fSGarrett D'Amore #define	SA_44K		1
15948722b5fSGarrett D'Amore #define	SA_96K		2
16048722b5fSGarrett D'Amore #define	SA_192K		3
16148722b5fSGarrett D'Amore 
16248722b5fSGarrett D'Amore #define	SA_MIX_OUT_EN(ch)	(1 << ((ch) + 28))
16348722b5fSGarrett D'Amore #define	SA_MIX_IN_EN(ch)	(1 << ((ch) + 24))
16448722b5fSGarrett D'Amore #define	SA_PLAY_RATE(ch, rate)	((rate) << (((ch) * 2) + 16))
16548722b5fSGarrett D'Amore #define	SA_PLAY_START(ch)	(1 << (ch))
16648722b5fSGarrett D'Amore #define	SA_RECORD_START(ch)	(1 << ((ch) + 8))
16748722b5fSGarrett D'Amore 
16848722b5fSGarrett D'Amore #define	SA_SPA(ch)	(1U << (ch))
16948722b5fSGarrett D'Amore #define	SA_SRA(ch)	(1U << ((ch) + 8))
17048722b5fSGarrett D'Amore 
17148722b5fSGarrett D'Amore #define	RECSEL_SPDIFOUT	0
17248722b5fSGarrett D'Amore #define	RECSEL_I2SOUT	1
17348722b5fSGarrett D'Amore #define	RECSEL_SPDIFIN	2
17448722b5fSGarrett D'Amore #define	RECSEL_I2SIN	3
17548722b5fSGarrett D'Amore #define	RECSEL_AC97	4
17648722b5fSGarrett D'Amore #define	RECSEL_SRC	5
17748722b5fSGarrett D'Amore 
17848722b5fSGarrett D'Amore typedef struct _audigyls_dev_t audigyls_dev_t;
17948722b5fSGarrett D'Amore typedef struct _audigyls_port_t audigyls_port_t;
18048722b5fSGarrett D'Amore 
18148722b5fSGarrett D'Amore typedef enum {
18248722b5fSGarrett D'Amore 	CTL_FRONT = 0,
18348722b5fSGarrett D'Amore 	CTL_SURROUND,
18448722b5fSGarrett D'Amore 	CTL_CENTER,
18548722b5fSGarrett D'Amore 	CTL_LFE,
18648722b5fSGarrett D'Amore 	CTL_RECORDVOL,
18748722b5fSGarrett D'Amore 	CTL_MONGAIN,
18848722b5fSGarrett D'Amore 	CTL_RECSRC,
18948722b5fSGarrett D'Amore 	CTL_SPREAD,
19048722b5fSGarrett D'Amore 	CTL_LOOP,
19148722b5fSGarrett D'Amore 	CTL_NUM		/* must be last */
19248722b5fSGarrett D'Amore } audigyls_ctrl_num_t;
19348722b5fSGarrett D'Amore 
19448722b5fSGarrett D'Amore typedef struct audigyls_ctrl
19548722b5fSGarrett D'Amore {
19648722b5fSGarrett D'Amore 	audigyls_dev_t		*dev;
19748722b5fSGarrett D'Amore 	audio_ctrl_t		*ctrl;
19848722b5fSGarrett D'Amore 	audigyls_ctrl_num_t	num;
19948722b5fSGarrett D'Amore 	uint64_t		val;
20048722b5fSGarrett D'Amore } audigyls_ctrl_t;
20148722b5fSGarrett D'Amore 
20248722b5fSGarrett D'Amore struct _audigyls_port_t
20348722b5fSGarrett D'Amore {
20448722b5fSGarrett D'Amore 	audigyls_dev_t *dev;
20548722b5fSGarrett D'Amore 	audio_engine_t *engine;
20648722b5fSGarrett D'Amore 
20748722b5fSGarrett D'Amore 	int			direction;
20848722b5fSGarrett D'Amore 
20948722b5fSGarrett D'Amore 	unsigned		nchan;
21048722b5fSGarrett D'Amore 
21148722b5fSGarrett D'Amore 	ddi_dma_handle_t	buf_dmah;	/* dma for buffers */
21248722b5fSGarrett D'Amore 	ddi_acc_handle_t	buf_acch;
21348722b5fSGarrett D'Amore 	uint32_t		buf_paddr;
21448722b5fSGarrett D'Amore 	caddr_t			buf_kaddr;
21548722b5fSGarrett D'Amore 	uint32_t		buf_size;
21648722b5fSGarrett D'Amore 	uint32_t		buf_frames;	/* Buffer size in frames */
21748722b5fSGarrett D'Amore 	uint32_t		offset;
21848722b5fSGarrett D'Amore 	int			syncdir;
21948722b5fSGarrett D'Amore 	uint64_t		count;
22048722b5fSGarrett D'Amore };
22148722b5fSGarrett D'Amore 
22248722b5fSGarrett D'Amore struct _audigyls_dev_t
22348722b5fSGarrett D'Amore {
22448722b5fSGarrett D'Amore 	dev_info_t		*dip;
22548722b5fSGarrett D'Amore 	audio_dev_t		*adev;
22648722b5fSGarrett D'Amore 	ac97_t			*ac97;
22748722b5fSGarrett D'Amore 
22848722b5fSGarrett D'Amore 	int			nactive;	/* Num active ports */
22948722b5fSGarrett D'Amore 	char			digital_enable;	/* Orange combo-jack mode */
23048722b5fSGarrett D'Amore 
23148722b5fSGarrett D'Amore 	ddi_acc_handle_t	pcih;
23248722b5fSGarrett D'Amore 	ddi_acc_handle_t	regsh;
23348722b5fSGarrett D'Amore 	caddr_t			base;
23448722b5fSGarrett D'Amore 	kmutex_t		mutex;		/* For normal locking */
23548722b5fSGarrett D'Amore 	kmutex_t		low_mutex;	/* For low level routines */
23648722b5fSGarrett D'Amore 
23748722b5fSGarrett D'Amore 	audigyls_port_t		*port[AUDIGYLS_NUM_PORT];
23848722b5fSGarrett D'Amore 	audigyls_ctrl_t		controls[CTL_NUM];
23948722b5fSGarrett D'Amore 
24048722b5fSGarrett D'Amore 	ac97_ctrl_t		*ac97_recgain;
24148722b5fSGarrett D'Amore 	ac97_ctrl_t		*ac97_recsrc;
24248722b5fSGarrett D'Amore 	uint64_t		recmask;
24348722b5fSGarrett D'Amore };
24448722b5fSGarrett D'Amore 
24548722b5fSGarrett D'Amore #define	INB(dev, reg)		\
24648722b5fSGarrett D'Amore 	ddi_get8(dev->regsh, (void *)(dev->base + reg))
24748722b5fSGarrett D'Amore #define	OUTB(dev, reg, val)	\
24848722b5fSGarrett D'Amore 	ddi_put8(dev->regsh, (void *)(dev->base + reg), (val))
24948722b5fSGarrett D'Amore 
25048722b5fSGarrett D'Amore #define	INW(dev, reg)		\
25148722b5fSGarrett D'Amore 	ddi_get16(dev->regsh, (void *)(dev->base + reg))
25248722b5fSGarrett D'Amore #define	OUTW(dev, reg, val)	\
25348722b5fSGarrett D'Amore 	ddi_put16(dev->regsh, (void *)(dev->base + reg), (val))
25448722b5fSGarrett D'Amore 
25548722b5fSGarrett D'Amore #define	INL(dev, reg)		\
25648722b5fSGarrett D'Amore 	ddi_get32(dev->regsh, (void *)(dev->base + reg))
25748722b5fSGarrett D'Amore #define	OUTL(dev, reg, val)	\
25848722b5fSGarrett D'Amore 	ddi_put32(dev->regsh, (void *)(dev->base + reg), (val))
25948722b5fSGarrett D'Amore 
26048722b5fSGarrett D'Amore #endif /* AUDIGYLS_H */