xref: /illumos-gate/usr/src/uts/common/io/ath/ath_hal.h (revision 129d67ac)
17a1306a7Sxc /*
2*129d67acSlin wang - Sun Microsystems - Beijing China  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros
37a1306a7Sxc  * Communications, Inc.  All rights reserved.
47a1306a7Sxc  *
57a1306a7Sxc  * Use is subject to license terms.
67a1306a7Sxc  *
77a1306a7Sxc  * Redistribution and use in source and binary forms are permitted
87a1306a7Sxc  * provided that the following conditions are met:
97a1306a7Sxc  * 1. The materials contained herein are unmodified and are used
107a1306a7Sxc  * unmodified.
117a1306a7Sxc  * 2. Redistributions of source code must retain the above copyright
127a1306a7Sxc  * notice, this list of conditions and the following NO
137a1306a7Sxc  * ''WARRANTY'' disclaimer below (''Disclaimer''), without
147a1306a7Sxc  * modification.
157a1306a7Sxc  * 3. Redistributions in binary form must reproduce at minimum a
167a1306a7Sxc  * disclaimer similar to the Disclaimer below and any redistribution
177a1306a7Sxc  * must be conditioned upon including a substantially similar
187a1306a7Sxc  * Disclaimer requirement for further binary redistribution.
197a1306a7Sxc  * 4. Neither the names of the above-listed copyright holders nor the
207a1306a7Sxc  * names of any contributors may be used to endorse or promote
217a1306a7Sxc  * product derived from this software without specific prior written
227a1306a7Sxc  * permission.
237a1306a7Sxc  *
247a1306a7Sxc  * NO WARRANTY
257a1306a7Sxc  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
267a1306a7Sxc  * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
277a1306a7Sxc  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
287a1306a7Sxc  * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
297a1306a7Sxc  * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
307a1306a7Sxc  * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
317a1306a7Sxc  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
327a1306a7Sxc  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
337a1306a7Sxc  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
347a1306a7Sxc  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
357a1306a7Sxc  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
367a1306a7Sxc  * SUCH DAMAGES.
377a1306a7Sxc  *
387a1306a7Sxc  */
397a1306a7Sxc 
407a1306a7Sxc #ifndef _ATH_HAL_H
417a1306a7Sxc #define	_ATH_HAL_H
427a1306a7Sxc 
437a1306a7Sxc /*
447a1306a7Sxc  * ath_hal.h is released by Atheros and used to describe the Atheros
457a1306a7Sxc  * Hardware Access Layer(HAL) interface. All kinds of data structures,
467a1306a7Sxc  * constant definition, APIs declaration are defined here.Clients of
477a1306a7Sxc  * the HAL call ath_hal_attach() to obtain a reference to an ath_hal
487a1306a7Sxc  * structure for use with the device. Hardware-related operations that
497a1306a7Sxc  * follow must call back into the HAL through interface, supplying the
507a1306a7Sxc  * reference as the first parameter.
517a1306a7Sxc  */
527a1306a7Sxc 
537a1306a7Sxc #ifdef __cplusplus
547a1306a7Sxc extern "C" {
557a1306a7Sxc #endif
567a1306a7Sxc 
577a1306a7Sxc /* HAL version of this release */
58*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_ABI_VERSION	0x08052700	/* YYMMDDnn */
597a1306a7Sxc 
607a1306a7Sxc /* HAL data type definition */
610ba2cbe9Sxc typedef void *		HAL_SOFTC;	/* pointer to driver/OS state */
620ba2cbe9Sxc typedef void *		HAL_BUS_TAG;	/* opaque bus i/o id tag */
630ba2cbe9Sxc typedef void *		HAL_BUS_HANDLE;	/* opaque bus i/o handle */
647a1306a7Sxc typedef uint32_t 	HAL_BUS_ADDR;
657a1306a7Sxc typedef uint16_t 	HAL_CTRY_CODE;	/* country code */
667a1306a7Sxc typedef uint16_t 	HAL_REG_DOMAIN;	/* regulatory domain code */
677a1306a7Sxc 
687a1306a7Sxc #define	HAL_NUM_TX_QUEUES	10		/* max number of tx queues */
697a1306a7Sxc 
707a1306a7Sxc #define	HAL_BEACON_PERIOD	0x0000ffff	/* beacon interval period */
717a1306a7Sxc #define	HAL_BEACON_ENA		0x00800000	/* beacon xmit enable */
727a1306a7Sxc #define	HAL_BEACON_RESET_TSF	0x01000000	/* clear TSF */
737a1306a7Sxc 
74*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_RAD_INT	0x00001	/* Radar interference detected on channel */
75*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_CW_INT	0x00002	/* CW interference detected on channel */
76*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_BUSY	0x00004	/* Busy, occupied or overlap with adjoin chan */
77*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_TURBO	0x00010	/* Turbo Channel */
78*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_CCK	0x00020	/* CCK channel */
79*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_OFDM	0x00040	/* OFDM channel */
80*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_2GHZ	0x00080	/* 2 GHz spectrum channel. */
81*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_5GHZ	0x00100	/* 5 GHz spectrum channel */
82*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_PASSIVE	0x00200	/* Only passive scan allowed in the channel */
83*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_DYN	0x00400	/* dynamic CCK-OFDM channel */
84*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_XR	0x00800	/* XR channel */
85*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_STURBO	0x02000	/* Static turbo, no 11a-only usage */
86*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_HALF	0x04000 /* Half rate channel */
87*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_QUARTER	0x08000 /* Quarter rate channel */
88*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_HT20	0x10000	/* 11n 20MHZ channel */
89*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_HT40PLUS	0x20000	/* 11n 40MHZ chan w/ ext chan above */
90*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_HT40MINUS	0x40000	/* 11n 40MHZ chan w/ ext chan below */
917a1306a7Sxc 
927a1306a7Sxc #define	CHANNEL_A	(CHANNEL_5GHZ|CHANNEL_OFDM)
937a1306a7Sxc #define	CHANNEL_B	(CHANNEL_2GHZ|CHANNEL_CCK)
947a1306a7Sxc #define	CHANNEL_PUREG	(CHANNEL_2GHZ|CHANNEL_OFDM)
957a1306a7Sxc #define	CHANNEL_G	(CHANNEL_2GHZ|CHANNEL_OFDM)
967a1306a7Sxc #define	CHANNEL_T	(CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
970ba2cbe9Sxc #define	CHANNEL_ST	(CHANNEL_T|CHANNEL_STURBO)
987a1306a7Sxc #define	CHANNEL_108G	(CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
990ba2cbe9Sxc #define	CHANNEL_108A	CHANNEL_T
1007a1306a7Sxc #define	CHANNEL_X	(CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
101*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_G_HT20	(CHANNEL_G|CHANNEL_HT20)
102*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_A_HT20	(CHANNEL_A|CHANNEL_HT20)
103*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_G_HT40PLUS	(CHANNEL_G_HT20|CHANNEL_HT40PLUS)
104*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_A_HT40PLUS	(CHANNEL_A_HT20|CHANNEL_HT40PLUS)
105*129d67acSlin wang - Sun Microsystems - Beijing China #define	CHANNEL_A_HT40MINUS	(CHANNEL_A_HT20|CHANNEL_HT40MINUS)
1067a1306a7Sxc #define	CHANNEL_ALL \
107*129d67acSlin wang - Sun Microsystems - Beijing China 	(CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ| \
108*129d67acSlin wang - Sun Microsystems - Beijing China 	CHANNEL_TURBO|CHANNEL_HT20|CHANNEL_HT40PLUS|CHANNEL_HT40MINUS)
1097a1306a7Sxc #define	CHANNEL_ALL_NOTURBO 	(CHANNEL_ALL &~ CHANNEL_TURBO)
1107a1306a7Sxc 
1110ba2cbe9Sxc #define	CHANNEL_COMPAT	(CHANNEL_ALL_NOTURBO | CHANNEL_PASSIVE)
1120ba2cbe9Sxc 
1130ba2cbe9Sxc /* privFlags */
1140ba2cbe9Sxc /*
1150ba2cbe9Sxc  * Software use: channel interference used for AR as well as RADAR
1160ba2cbe9Sxc  * interference detection
1170ba2cbe9Sxc  */
1180ba2cbe9Sxc #define	CHANNEL_INTERFERENCE	0x01
1190ba2cbe9Sxc #define	CHANNEL_DFS		0x02	/* DFS required on channel */
1200ba2cbe9Sxc #define	CHANNEL_4MS_LIMIT	0x04	/* 4msec packet limit on this channel */
1210ba2cbe9Sxc #define	CHANNEL_DFS_CLEAR	0x08	/* if channel has been checked DFS */
1220ba2cbe9Sxc 
1237a1306a7Sxc #define	HAL_RSSI_EP_MULTIPLIER	(1<<7)	/* pow2 to optimize out * and / */
1247a1306a7Sxc 
1257a1306a7Sxc /* flags passed to tx descriptor setup methods */
1267a1306a7Sxc #define	HAL_TXDESC_CLRDMASK	0x0001	/* clear destination filter mask */
1277a1306a7Sxc #define	HAL_TXDESC_NOACK	0x0002	/* don't wait for ACK */
1287a1306a7Sxc #define	HAL_TXDESC_RTSENA	0x0004	/* enable RTS */
1297a1306a7Sxc #define	HAL_TXDESC_CTSENA	0x0008	/* enable CTS */
1307a1306a7Sxc #define	HAL_TXDESC_INTREQ	0x0010	/* enable per-descriptor interrupt */
1317a1306a7Sxc #define	HAL_TXDESC_VEOL		0x0020	/* mark virtual EOL */
1320ba2cbe9Sxc /* NB: this only affects frame, not any RTS/CTS */
1330ba2cbe9Sxc #define	HAL_TXDESC_DURENA	0x0040	/* enable h/w write of duration field */
134*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXDESC_EXT_ONLY	0x0080	/* send on ext channel only (11n) */
135*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXDESC_EXT_AND_CTL	0x0100	/* send on ext + ctl channels (11n) */
136*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXDESC_VMF		0x0200	/* virtual more frag */
1377a1306a7Sxc 
1387a1306a7Sxc /* flags passed to rx descriptor setup methods */
1397a1306a7Sxc #define	HAL_RXDESC_INTREQ	0x0020	/* enable per-descriptor interrupt */
1407a1306a7Sxc 
1417a1306a7Sxc /* tx error flags */
1427a1306a7Sxc #define	HAL_TXERR_XRETRY	0x01	/* excessive retries */
1437a1306a7Sxc #define	HAL_TXERR_FILT		0x02	/* blocked by tx filtering */
1447a1306a7Sxc #define	HAL_TXERR_FIFO		0x04	/* fifo underrun */
145*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXERR_XTXOP		0x08	/* txop exceeded */
146*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXERR_DESC_CFG_ERR	0x10	/* Error in 20/40 desc config */
147*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXERR_DATA_UNDERRUN	0x20	/* Tx buffer underrun */
148*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TXERR_DELIM_UNDERRUN 0x40	/* Tx delimiter underrun */
1497a1306a7Sxc #define	HAL_TXSTAT_ALTRATE	0x80	/* alternate xmit rate used */
1507a1306a7Sxc 
151*129d67acSlin wang - Sun Microsystems - Beijing China /* bits found in ts_flags */
152*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TX_BA		0x01	/* Block Ack seen */
153*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_TX_AGGR		0x02	/* Aggregate */
154*129d67acSlin wang - Sun Microsystems - Beijing China 
1557a1306a7Sxc /* rx error flags */
1567a1306a7Sxc #define	HAL_RXERR_CRC		0x01	/* CRC error on frame */
1577a1306a7Sxc #define	HAL_RXERR_PHY		0x02	/* PHY error, rs_phyerr is valid */
1587a1306a7Sxc #define	HAL_RXERR_FIFO		0x04	/* fifo overrun */
1597a1306a7Sxc #define	HAL_RXERR_DECRYPT	0x08	/* non-Michael decrypt error */
1607a1306a7Sxc #define	HAL_RXERR_MIC		0x10	/* Michael MIC decrypt error */
1617a1306a7Sxc 
162*129d67acSlin wang - Sun Microsystems - Beijing China /* bits found in rs_flags */
163*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_MORE		0x01	/* more descriptors follow */
164*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_MORE_AGGR	0x02	/* more frames in aggr */
165*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_GI		0x04	/* full gi */
166*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_2040		0x08	/* 40 Mhz */
167*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_DELIM_CRC_PRE	0x10	/* crc error in delimiter pre */
168*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_DELIM_CRC_POST	0x20	/* crc error in delim after */
169*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_DECRYPT_BUSY	0x40	/* decrypt was too slow */
170*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RX_DUP_FRAME	0x80	/* Dup frame rx'd on control channel */
171*129d67acSlin wang - Sun Microsystems - Beijing China 
1727a1306a7Sxc /* value found in rs_keyix to mark invalid entries */
1737a1306a7Sxc #define	HAL_RXKEYIX_INVALID	((uint8_t)-1)
1747a1306a7Sxc 
1757a1306a7Sxc /* value used to specify no encryption key for xmit */
1767a1306a7Sxc #define	HAL_TXKEYIX_INVALID	((uint32_t)-1)
1777a1306a7Sxc 
1780ba2cbe9Sxc /* compression definitions */
1790ba2cbe9Sxc #define	HAL_COMP_BUF_MAX_SIZE	9216	/* 9k */
1800ba2cbe9Sxc #define	HAL_COMP_BUF_ALIGN_SIZE	512
1810ba2cbe9Sxc 
1820ba2cbe9Sxc #define	HAL_ANTENNA_MIN_MODE	0
1830ba2cbe9Sxc #define	HAL_ANTENNA_FIXED_A	1
1840ba2cbe9Sxc #define	HAL_ANTENNA_FIXED_B	2
1850ba2cbe9Sxc #define	HAL_ANTENNA_MAX_MODE	3
1860ba2cbe9Sxc 
1877a1306a7Sxc /*
1887a1306a7Sxc  * Status codes that may be returned by the HAL.  Note that
1897a1306a7Sxc  * interfaces that return a status code set it only when an
1907a1306a7Sxc  * error occurs--i.e. you cannot check it for success.
1917a1306a7Sxc  */
1927a1306a7Sxc typedef enum {
1937a1306a7Sxc 	HAL_OK		= 0,	/* No error */
1947a1306a7Sxc 	HAL_ENXIO	= 1,	/* No hardware present */
1957a1306a7Sxc 	HAL_ENOMEM	= 2,	/* Memory allocation failed */
1967a1306a7Sxc 	HAL_EIO		= 3,	/* Hardware didn't respond as expected */
1977a1306a7Sxc 	HAL_EEMAGIC	= 4,	/* EEPROM magic number invalid */
1987a1306a7Sxc 	HAL_EEVERSION	= 5,	/* EEPROM version invalid */
1997a1306a7Sxc 	HAL_EELOCKED	= 6,	/* EEPROM unreadable */
2007a1306a7Sxc 	HAL_EEBADSUM	= 7,	/* EEPROM checksum invalid */
2017a1306a7Sxc 	HAL_EEREAD	= 8,	/* EEPROM read problem */
2027a1306a7Sxc 	HAL_EEBADMAC	= 9,	/* EEPROM mac address invalid */
2037a1306a7Sxc 	HAL_EESIZE	= 10,	/* EEPROM size not supported */
2047a1306a7Sxc 	HAL_EEWRITE	= 11,	/* Attempt to change write-locked EEPROM */
2057a1306a7Sxc 	HAL_EINVAL	= 12,	/* Invalid parameter to function */
2067a1306a7Sxc 	HAL_ENOTSUPP	= 13,	/* Hardware revision not supported */
2077a1306a7Sxc 	HAL_ESELFTEST	= 14,	/* Hardware self-test failed */
2087a1306a7Sxc 	HAL_EINPROGRESS	= 15	/* Operation incomplete */
2097a1306a7Sxc } HAL_STATUS;
2107a1306a7Sxc 
2117a1306a7Sxc typedef enum {
2127a1306a7Sxc 	AH_FALSE = 0,		/* NB: lots of code assumes false is zero */
2137a1306a7Sxc 	AH_TRUE  = 1
2147a1306a7Sxc } HAL_BOOL;
2157a1306a7Sxc 
2167a1306a7Sxc typedef enum {
2177a1306a7Sxc 	HAL_CAP_REG_DMN		= 0,	/* current regulatory domain */
2187a1306a7Sxc 	HAL_CAP_CIPHER		= 1,	/* hardware supports cipher */
2197a1306a7Sxc 	HAL_CAP_TKIP_MIC	= 2,	/* handle TKIP MIC in hardware */
2207a1306a7Sxc 	HAL_CAP_TKIP_SPLIT	= 3,	/* hardware TKIP uses split keys */
2217a1306a7Sxc 	HAL_CAP_PHYCOUNTERS	= 4,	/* hardware PHY error counters */
2227a1306a7Sxc 	HAL_CAP_DIVERSITY	= 5,	/* hardware supports fast diversity */
2237a1306a7Sxc 	HAL_CAP_KEYCACHE_SIZE	= 6,	/* number of entries in key cache */
2247a1306a7Sxc 	HAL_CAP_NUM_TXQUEUES	= 7,	/* number of hardware xmit queues */
2257a1306a7Sxc 	HAL_CAP_VEOL		= 9,	/* hardware supports virtual EOL */
2267a1306a7Sxc 	HAL_CAP_PSPOLL		= 10,	/* hardware has working PS-Poll */
2277a1306a7Sxc 					/* support */
2287a1306a7Sxc 	HAL_CAP_DIAG		= 11,	/* hardware diagnostic support */
2297a1306a7Sxc 	HAL_CAP_COMPRESSION	= 12,	/* hardware supports compression */
2307a1306a7Sxc 	HAL_CAP_BURST		= 13,	/* hardware supports packet bursting */
2317a1306a7Sxc 	HAL_CAP_FASTFRAME	= 14,	/* hardware supoprts fast frames */
2327a1306a7Sxc 	HAL_CAP_TXPOW		= 15,	/* global tx power limit  */
2330ba2cbe9Sxc 	HAL_CAP_TPC		= 16,	/* per-packet tx power control  */
2340ba2cbe9Sxc 	HAL_CAP_PHYDIAG		= 17,	/* hardware phy error diagnostic */
2350ba2cbe9Sxc 	HAL_CAP_BSSIDMASK	= 18,	/* hardware supports bssid mask */
2360ba2cbe9Sxc 	HAL_CAP_MCAST_KEYSRCH	= 19,	/* hardware has multicast key search */
2370ba2cbe9Sxc 	HAL_CAP_TSF_ADJUST	= 20,	/* hardware has beacon tsf adjust */
2380ba2cbe9Sxc 	HAL_CAP_XR		= 21,	/* hardware has XR support  */
2390ba2cbe9Sxc 	/* hardware can support TKIP MIC when WMM is turned on */
2400ba2cbe9Sxc 	HAL_CAP_WME_TKIPMIC	= 22,
2410ba2cbe9Sxc 	/* hardware can support half rate channels */
2420ba2cbe9Sxc 	HAL_CAP_CHAN_HALFRATE	= 23,
2430ba2cbe9Sxc 	/* hardware can support quarter rate channels */
2440ba2cbe9Sxc 	HAL_CAP_CHAN_QUARTERRATE = 24,
2450ba2cbe9Sxc 	HAL_CAP_RFSILENT	= 25,	/* hardware has rfsilent support  */
2460ba2cbe9Sxc 	HAL_CAP_TPC_ACK		= 26,	/* ack txpower with per-packet tpc */
2470ba2cbe9Sxc 	HAL_CAP_TPC_CTS		= 27,	/* cts txpower with per-packet tpc */
2480ba2cbe9Sxc 	HAL_CAP_11D		= 28,	/* 11d beacon support for changing cc */
249*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CAP_INTMIT		= 29,	/* interference mitigation */
250*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CAP_RXORN_FATAL	= 30,	/* HAL_INT_RXORN treated as fatal */
251*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CAP_HT		= 31,	/* hardware can support HT */
252*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CAP_NUMTXCHAIN	= 32,	/* TX chains supported */
253*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CAP_NUMRXCHAIN	= 33,	/* RX chains supported */
254*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CAP_RXTSTAMP_PREC	= 34	/* rx desc tstamp precision (bits) */
2557a1306a7Sxc } HAL_CAPABILITY_TYPE;
2567a1306a7Sxc 
2577a1306a7Sxc /*
2587a1306a7Sxc  * "States" for setting the LED.  These correspond to
2597a1306a7Sxc  * the possible 802.11 operational states and there may
2607a1306a7Sxc  * be a many-to-one mapping between these states and the
2617a1306a7Sxc  * actual hardware states for the LED's (i.e. the hardware
2627a1306a7Sxc  * may have fewer states).
2637a1306a7Sxc  */
2647a1306a7Sxc typedef enum {
2657a1306a7Sxc 	HAL_LED_INIT	= 0,
2667a1306a7Sxc 	HAL_LED_SCAN	= 1,
2677a1306a7Sxc 	HAL_LED_AUTH	= 2,
2687a1306a7Sxc 	HAL_LED_ASSOC	= 3,
2697a1306a7Sxc 	HAL_LED_RUN	= 4
2707a1306a7Sxc } HAL_LED_STATE;
2717a1306a7Sxc 
2727a1306a7Sxc /*
2737a1306a7Sxc  * Transmit queue types/numbers.  These are used to tag
2747a1306a7Sxc  * each transmit queue in the hardware and to identify a set
2757a1306a7Sxc  * of transmit queues for operations such as start/stop dma.
2767a1306a7Sxc  */
2777a1306a7Sxc typedef enum {
2787a1306a7Sxc 	HAL_TX_QUEUE_INACTIVE	= 0,	/* queue is inactive/unused */
2797a1306a7Sxc 	HAL_TX_QUEUE_DATA	= 1,	/* data xmit q's */
2807a1306a7Sxc 	HAL_TX_QUEUE_BEACON	= 2,	/* beacon xmit q */
2817a1306a7Sxc 	HAL_TX_QUEUE_CAB	= 3,	/* "crap after beacon" xmit q */
2820ba2cbe9Sxc 	HAL_TX_QUEUE_UAPSD	= 4	/* u-apsd power save xmit q */
2837a1306a7Sxc } HAL_TX_QUEUE;
2847a1306a7Sxc 
2857a1306a7Sxc 
2867a1306a7Sxc /*
2877a1306a7Sxc  * Transmit queue subtype.  These map directly to
2887a1306a7Sxc  * WME Access Categories (except for UPSD).  Refer
2897a1306a7Sxc  * to Table 5 of the WME spec.
2907a1306a7Sxc  */
2917a1306a7Sxc typedef enum {
2927a1306a7Sxc 	HAL_WME_AC_BK	= 0,		/* background access category */
2937a1306a7Sxc 	HAL_WME_AC_BE	= 1, 		/* best effort access category */
2947a1306a7Sxc 	HAL_WME_AC_VI	= 2,		/* video access category */
2957a1306a7Sxc 	HAL_WME_AC_VO	= 3,		/* voice access category */
2960ba2cbe9Sxc 	HAL_WME_UPSD	= 4,		/* uplink power save */
2970ba2cbe9Sxc 	HAL_XR_DATA	= 5		/* entended range data */
2987a1306a7Sxc } HAL_TX_QUEUE_SUBTYPE;
2997a1306a7Sxc 
3007a1306a7Sxc /*
3017a1306a7Sxc  * Transmit queue flags that control various
3027a1306a7Sxc  * operational parameters.
3037a1306a7Sxc  */
3047a1306a7Sxc typedef enum {
3050ba2cbe9Sxc 	/*
3060ba2cbe9Sxc 	 * Per queue interrupt enables.  When set the associated
3070ba2cbe9Sxc 	 * interrupt may be delivered for packets sent through
3080ba2cbe9Sxc 	 * the queue.  Without these enabled no interrupts will
3090ba2cbe9Sxc 	 * be delivered for transmits through the queue.
3100ba2cbe9Sxc 	 *
3110ba2cbe9Sxc 	 * When 0x0001 is set, both TXQ_TXOKINT and TXQ_TXERRINT
3120ba2cbe9Sxc 	 * will be enabled.
3130ba2cbe9Sxc 	 */
3140ba2cbe9Sxc 	HAL_TXQ_TXOKINT_ENABLE	   = 0x0001,	/* enable TXOK interrupt */
3150ba2cbe9Sxc 	HAL_TXQ_TXERRINT_ENABLE    = 0x0001,	/* enable TXERR interrupt */
3160ba2cbe9Sxc 	HAL_TXQ_TXDESCINT_ENABLE   = 0x0002,	/* enable TXDESC interrupt */
3170ba2cbe9Sxc 	HAL_TXQ_TXEOLINT_ENABLE    = 0x0004,	/* enable TXEOL interrupt */
3180ba2cbe9Sxc 	HAL_TXQ_TXURNINT_ENABLE    = 0x0008,	/* enable TXURN interrupt */
3190ba2cbe9Sxc 	/*
3200ba2cbe9Sxc 	 * Enable hardware compression for packets sent through
3210ba2cbe9Sxc 	 * the queue.  The compression buffer must be setup and
3220ba2cbe9Sxc 	 * packets must have a key entry marked in the tx descriptor.
3230ba2cbe9Sxc 	 */
3240ba2cbe9Sxc 	HAL_TXQ_COMPRESSION_ENABLE = 0x0010,	/* enable h/w compression */
3250ba2cbe9Sxc 	/*
3260ba2cbe9Sxc 	 * Disable queue when veol is hit or ready time expires.
3270ba2cbe9Sxc 	 * By default the queue is disabled only on reaching the
3280ba2cbe9Sxc 	 * physical end of queue (i.e. a null link ptr in the
3290ba2cbe9Sxc 	 * descriptor chain).
3300ba2cbe9Sxc 	 */
3310ba2cbe9Sxc 	HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
3320ba2cbe9Sxc 	/*
3330ba2cbe9Sxc 	 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
3340ba2cbe9Sxc 	 * event.  Frames will be transmitted only when this timer
3350ba2cbe9Sxc 	 * fires, e.g to transmit a beacon in ap or adhoc modes.
3360ba2cbe9Sxc 	 */
3370ba2cbe9Sxc 	HAL_TXQ_DBA_GATED	   = 0x0040,	/* schedule based on DBA */
3380ba2cbe9Sxc 	/*
3390ba2cbe9Sxc 	 * Each transmit queue has a counter that is incremented
3400ba2cbe9Sxc 	 * each time the queue is enabled and decremented when
3410ba2cbe9Sxc 	 * the list of frames to transmit is traversed (or when
3420ba2cbe9Sxc 	 * the ready time for the queue expires).  This counter
3430ba2cbe9Sxc 	 * must be non-zero for frames to be scheduled for
3440ba2cbe9Sxc 	 * transmission.  The following controls disable bumping
3450ba2cbe9Sxc 	 * this counter under certain conditions.  Typically this
3460ba2cbe9Sxc 	 * is used to gate frames based on the contents of another
3470ba2cbe9Sxc 	 * queue (e.g. CAB traffic may only follow a beacon frame).
3480ba2cbe9Sxc 	 * These are meaningful only when frames are scheduled
3490ba2cbe9Sxc 	 * with a non-ASAP policy (e.g. DBA-gated).
3500ba2cbe9Sxc 	 */
3510ba2cbe9Sxc 	HAL_TXQ_CBR_DIS_QEMPTY	   = 0x0080,	/* disable on this q empty */
3520ba2cbe9Sxc 	HAL_TXQ_CBR_DIS_BEMPTY	   = 0x0100,	/* disable on beacon q empty */
3530ba2cbe9Sxc 
3540ba2cbe9Sxc 	/*
3550ba2cbe9Sxc 	 * Fragment burst backoff policy.   Normally no backoff
3560ba2cbe9Sxc 	 * is done after a successful transmission, the next fragment
3570ba2cbe9Sxc 	 * is sent at SIFS.  If this flag is set backoff is done
3580ba2cbe9Sxc 	 * after each fragment, regardless whether it was ack'd or
3590ba2cbe9Sxc 	 * not, after the backoff count reaches zero a normal channel
3600ba2cbe9Sxc 	 * access procedure is done before the next transmit (i.e.
3610ba2cbe9Sxc 	 * wait AIFS instead of SIFS).
3620ba2cbe9Sxc 	 */
3630ba2cbe9Sxc 	HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
3640ba2cbe9Sxc 	/*
3650ba2cbe9Sxc 	 * Disable post-tx backoff following each frame.
3660ba2cbe9Sxc 	 */
3670ba2cbe9Sxc 	HAL_TXQ_BACKOFF_DISABLE    =  0x00010000, /* disable post backoff  */
3680ba2cbe9Sxc 	/*
3690ba2cbe9Sxc 	 * DCU arbiter lockout control.  This controls how
3700ba2cbe9Sxc 	 * lower priority tx queues are handled with respect
3710ba2cbe9Sxc 	 * to a specific queue when multiple queues have frames
3720ba2cbe9Sxc 	 * to send.  No lockout means lower priority queues arbitrate
3730ba2cbe9Sxc 	 * concurrently with this queue.  Intra-frame lockout
3740ba2cbe9Sxc 	 * means lower priority queues are locked out until the
3750ba2cbe9Sxc 	 * current frame transmits (e.g. including backoffs and bursting).
3760ba2cbe9Sxc 	 * Global lockout means nothing lower can arbitrary so
3770ba2cbe9Sxc 	 * long as there is traffic activity on this queue (frames,
3780ba2cbe9Sxc 	 * backoff, etc).
3790ba2cbe9Sxc 	 */
3800ba2cbe9Sxc 	HAL_TXQ_ARB_LOCKOUT_INTRA  = 0x00020000, /* intra-frame lockout */
3810ba2cbe9Sxc 	HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
3820ba2cbe9Sxc 
3830ba2cbe9Sxc 	HAL_TXQ_IGNORE_VIRTCOL	   = 0x00080000, /* ignore virt collisions */
3840ba2cbe9Sxc 	HAL_TXQ_SEQNUM_INC_DIS	   = 0x00100000  /* disable seqnum increment */
3857a1306a7Sxc } HAL_TX_QUEUE_FLAGS;
3867a1306a7Sxc 
3877a1306a7Sxc typedef struct {
3887a1306a7Sxc 	uint32_t	tqi_ver;		/* hal TXQ version */
3897a1306a7Sxc 	HAL_TX_QUEUE_SUBTYPE tqi_subtype;	/* subtype if applicable */
3907a1306a7Sxc 	HAL_TX_QUEUE_FLAGS tqi_qflags;		/* flags (see above) */
3917a1306a7Sxc 	uint32_t	tqi_priority;		/* (not used) */
3927a1306a7Sxc 	uint32_t	tqi_aifs;		/* AIFS shift */
3937a1306a7Sxc 	int32_t		tqi_cwmin;		/* cwMin shift */
3947a1306a7Sxc 	int32_t		tqi_cwmax;		/* cwMax shift */
3957a1306a7Sxc 	uint16_t	tqi_shretry;		/* rts retry limit */
3967a1306a7Sxc 	uint16_t	tqi_lgretry;		/* long retry limit(not used) */
3977a1306a7Sxc 	uint32_t	tqi_cbrPeriod;
3987a1306a7Sxc 	uint32_t	tqi_cbrOverflowLimit;
3997a1306a7Sxc 	uint32_t	tqi_burstTime;
4007a1306a7Sxc 	uint32_t	tqi_readyTime;
4010ba2cbe9Sxc 	uint32_t	tqi_compBuf;		/* compress buffer phys addr */
4027a1306a7Sxc } HAL_TXQ_INFO;
4037a1306a7Sxc 
4040ba2cbe9Sxc #define	HAL_TQI_NONVAL		0xffff
4050ba2cbe9Sxc 
4067a1306a7Sxc /* token to use for aifs, cwmin, cwmax */
4077a1306a7Sxc #define	HAL_TXQ_USEDEFAULT	((uint32_t)-1)
4087a1306a7Sxc 
4097a1306a7Sxc /*
4107a1306a7Sxc  * Transmit packet types.  This belongs in ah_desc.h, but
4117a1306a7Sxc  * is here so we can give a proper type to various parameters
4127a1306a7Sxc  * (and not require everyone include the file).
4137a1306a7Sxc  *
4147a1306a7Sxc  * NB: These values are intentionally assigned for
4157a1306a7Sxc  *     direct use when setting up h/w descriptors.
4167a1306a7Sxc  */
4177a1306a7Sxc typedef enum {
4187a1306a7Sxc 	HAL_PKT_TYPE_NORMAL	= 0,
4197a1306a7Sxc 	HAL_PKT_TYPE_ATIM	= 1,
4207a1306a7Sxc 	HAL_PKT_TYPE_PSPOLL	= 2,
4217a1306a7Sxc 	HAL_PKT_TYPE_BEACON	= 3,
4220ba2cbe9Sxc 	HAL_PKT_TYPE_PROBE_RESP	= 4,
4230ba2cbe9Sxc 	HAL_PKT_TYPE_CHIRP	= 5,
424*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_PKT_TYPE_GRP_POLL	= 6,
425*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_PKT_TYPE_AMPDU	= 7
4267a1306a7Sxc } HAL_PKT_TYPE;
4277a1306a7Sxc 
4287a1306a7Sxc /* Rx Filter Frame Types */
4297a1306a7Sxc typedef enum {
4307a1306a7Sxc 	HAL_RX_FILTER_UCAST	= 0x00000001,	/* Allow unicast frames */
4317a1306a7Sxc 	HAL_RX_FILTER_MCAST	= 0x00000002,	/* Allow multicast frames */
4327a1306a7Sxc 	HAL_RX_FILTER_BCAST	= 0x00000004,	/* Allow broadcast frames */
4337a1306a7Sxc 	HAL_RX_FILTER_CONTROL	= 0x00000008,	/* Allow control frames */
4347a1306a7Sxc 	HAL_RX_FILTER_BEACON	= 0x00000010,	/* Allow beacon frames */
4357a1306a7Sxc 	HAL_RX_FILTER_PROM	= 0x00000020,	/* Promiscuous mode */
4360ba2cbe9Sxc 	HAL_RX_FILTER_XRPOLL	= 0x00000040,	/* Allow XR poll frmae */
4377a1306a7Sxc 	HAL_RX_FILTER_PROBEREQ	= 0x00000080,	/* Allow probe request frames */
4387a1306a7Sxc 	HAL_RX_FILTER_PHYERR	= 0x00000100,	/* Allow phy errors */
4397a1306a7Sxc 	HAL_RX_FILTER_PHYRADAR	= 0x00000200	/* Allow phy radar errors */
4407a1306a7Sxc } HAL_RX_FILTER;
4417a1306a7Sxc 
4427a1306a7Sxc typedef enum {
4430ba2cbe9Sxc 	HAL_PM_AWAKE		= 0,
4440ba2cbe9Sxc 	HAL_PM_FULL_SLEEP	= 1,
4450ba2cbe9Sxc 	HAL_PM_NETWORK_SLEEP	= 2,
4460ba2cbe9Sxc 	HAL_PM_UNDEFINED	= 3
4477a1306a7Sxc } HAL_POWER_MODE;
4487a1306a7Sxc 
4497a1306a7Sxc /*
4507a1306a7Sxc  * NOTE WELL:
4517a1306a7Sxc  * These are mapped to take advantage of the common locations for many of
4527a1306a7Sxc  * the bits on all of the currently supported MAC chips. This is to make
4537a1306a7Sxc  * the ISR as efficient as possible, while still abstracting HW differences.
4547a1306a7Sxc  * When new hardware breaks this commonality this enumerated type, as well
4557a1306a7Sxc  * as the HAL functions using it, must be modified. All values are directly
4567a1306a7Sxc  * mapped unless commented otherwise.
4577a1306a7Sxc  */
4587a1306a7Sxc typedef enum {
4597a1306a7Sxc 	HAL_INT_RX	= 0x00000001,	/* Non-common mapping */
4607a1306a7Sxc 	HAL_INT_RXDESC	= 0x00000002,
4617a1306a7Sxc 	HAL_INT_RXNOFRM	= 0x00000008,
4627a1306a7Sxc 	HAL_INT_RXEOL	= 0x00000010,
4637a1306a7Sxc 	HAL_INT_RXORN	= 0x00000020,
4647a1306a7Sxc 	HAL_INT_TX	= 0x00000040,	/* Non-common mapping */
4657a1306a7Sxc 	HAL_INT_TXDESC	= 0x00000080,
4667a1306a7Sxc 	HAL_INT_TXURN	= 0x00000800,
4677a1306a7Sxc 	HAL_INT_MIB	= 0x00001000,
4687a1306a7Sxc 	HAL_INT_RXPHY	= 0x00004000,
4697a1306a7Sxc 	HAL_INT_RXKCM	= 0x00008000,
4707a1306a7Sxc 	HAL_INT_SWBA	= 0x00010000,
4717a1306a7Sxc 	HAL_INT_BMISS	= 0x00040000,
4727a1306a7Sxc 	HAL_INT_BNR	= 0x00100000,	/* Non-common mapping */
4730ba2cbe9Sxc 	HAL_INT_TIM	= 0x00200000,	/* Non-common mapping */
4740ba2cbe9Sxc 	HAL_INT_DTIM	= 0x00400000,	/* Non-common mapping */
4750ba2cbe9Sxc 	HAL_INT_DTIMSYNC = 0x00800000,	/* Non-common mapping */
4767a1306a7Sxc 	HAL_INT_GPIO	= 0x01000000,
4770ba2cbe9Sxc 	HAL_INT_CABEND	= 0x02000000,	/* Non-common mapping */
478*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_INT_CST	= 0x10000000,	/* Non-common mapping */
479*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_INT_GTT	= 0x20000000,	/* Non-common mapping */
4807a1306a7Sxc 	HAL_INT_FATAL	= 0x40000000,	/* Non-common mapping */
4817a1306a7Sxc 	HAL_INT_GLOBAL	= INT_MIN,	/* Set/clear IER */
4820ba2cbe9Sxc 	HAL_INT_BMISC	= HAL_INT_TIM
4830ba2cbe9Sxc 			| HAL_INT_DTIM
4840ba2cbe9Sxc 			| HAL_INT_DTIMSYNC
4850ba2cbe9Sxc 			| HAL_INT_CABEND,
4867a1306a7Sxc 
4877a1306a7Sxc 	/* Interrupt bits that map directly to ISR/IMR bits */
4887a1306a7Sxc 	HAL_INT_COMMON  = HAL_INT_RXNOFRM
4897a1306a7Sxc 			| HAL_INT_RXDESC
4907a1306a7Sxc 			| HAL_INT_RXEOL
4917a1306a7Sxc 			| HAL_INT_RXORN
4927a1306a7Sxc 			| HAL_INT_TXURN
4937a1306a7Sxc 			| HAL_INT_TXDESC
4947a1306a7Sxc 			| HAL_INT_MIB
4957a1306a7Sxc 			| HAL_INT_RXPHY
4967a1306a7Sxc 			| HAL_INT_RXKCM
4977a1306a7Sxc 			| HAL_INT_SWBA
4987a1306a7Sxc 			| HAL_INT_BMISS
4997a1306a7Sxc 			| HAL_INT_GPIO,
5007a1306a7Sxc } HAL_INT;
5017a1306a7Sxc 
5027a1306a7Sxc typedef enum {
5037a1306a7Sxc 	HAL_RFGAIN_INACTIVE		= 0,
5047a1306a7Sxc 	HAL_RFGAIN_READ_REQUESTED	= 1,
5057a1306a7Sxc 	HAL_RFGAIN_NEED_CHANGE		= 2
5067a1306a7Sxc } HAL_RFGAIN;
5077a1306a7Sxc 
5087a1306a7Sxc typedef enum {
5097a1306a7Sxc 	HAL_PHYERR_UNDERRUN		= 0,	/* Transmit underrun */
5107a1306a7Sxc 	HAL_PHYERR_TIMING		= 1,	/* Timing error */
5117a1306a7Sxc 	HAL_PHYERR_PARITY		= 2,	/* Illegal parity */
5127a1306a7Sxc 	HAL_PHYERR_RATE			= 3,	/* Illegal rate */
5137a1306a7Sxc 	HAL_PHYERR_LENGTH		= 4,	/* Illegal length */
5147a1306a7Sxc 	HAL_PHYERR_RADAR		= 5,	/* Radar detect */
5157a1306a7Sxc 	HAL_PHYERR_SERVICE		= 6,	/* Illegal service */
5167a1306a7Sxc 	HAL_PHYERR_TOR			= 7,	/* Transmit override receive */
5177a1306a7Sxc 	/* NB: these are specific to the 5212 */
5187a1306a7Sxc 	HAL_PHYERR_OFDM_TIMING		= 17,	/* */
5197a1306a7Sxc 	HAL_PHYERR_OFDM_SIGNAL_PARITY	= 18,	/* */
5207a1306a7Sxc 	HAL_PHYERR_OFDM_RATE_ILLEGAL	= 19,	/* */
5217a1306a7Sxc 	HAL_PHYERR_OFDM_LENGTH_ILLEGAL	= 20,	/* */
5227a1306a7Sxc 	HAL_PHYERR_OFDM_POWER_DROP	= 21,	/* */
5237a1306a7Sxc 	HAL_PHYERR_OFDM_SERVICE		= 22,	/* */
5247a1306a7Sxc 	HAL_PHYERR_OFDM_RESTART		= 23,	/* */
5257a1306a7Sxc 	HAL_PHYERR_CCK_TIMING		= 25,	/* */
5267a1306a7Sxc 	HAL_PHYERR_CCK_HEADER_CRC	= 26,	/* */
5277a1306a7Sxc 	HAL_PHYERR_CCK_RATE_ILLEGAL	= 27,	/* */
5287a1306a7Sxc 	HAL_PHYERR_CCK_SERVICE		= 30,	/* */
5297a1306a7Sxc 	HAL_PHYERR_CCK_RESTART		= 31	/* */
5307a1306a7Sxc }HAL_PHYERR;
5317a1306a7Sxc 
5327a1306a7Sxc /*
5337a1306a7Sxc  * Channels are specified by frequency.
5347a1306a7Sxc  */
5357a1306a7Sxc typedef struct {
536*129d67acSlin wang - Sun Microsystems - Beijing China 	uint32_t	channelFlags;
5377a1306a7Sxc 	uint16_t	channel;	/* setting in Mhz */
5380ba2cbe9Sxc 	uint8_t		privFlags;
5390ba2cbe9Sxc 	int8_t		maxRegTxPower;	/* max regulatory tx power in dBm */
5400ba2cbe9Sxc 	int8_t		maxTxPower;	/* max true tx power in 0.5 dBm */
5410ba2cbe9Sxc 	int8_t		minTxPower;	/* min true tx power in 0.5 dBm */
5427a1306a7Sxc } HAL_CHANNEL;
5437a1306a7Sxc 
5447a1306a7Sxc 
5457a1306a7Sxc typedef struct {
5467a1306a7Sxc 	uint32_t	ackrcv_bad;
5477a1306a7Sxc 	uint32_t	rts_bad;
5487a1306a7Sxc 	uint32_t	rts_good;
5497a1306a7Sxc 	uint32_t	fcs_bad;
5507a1306a7Sxc 	uint32_t	beacons;
5517a1306a7Sxc } HAL_MIB_STATS;
5527a1306a7Sxc 
5537a1306a7Sxc 
5547a1306a7Sxc enum {
5557a1306a7Sxc 	CTRY_DEBUG	= 0x1ff,		/* debug country code */
5567a1306a7Sxc 	CTRY_DEFAULT	= 0			/* default country code */
5577a1306a7Sxc };
5587a1306a7Sxc 
5597a1306a7Sxc enum {
5600ba2cbe9Sxc 	HAL_MODE_11A	= 0x001,	/* 11a channels */
5610ba2cbe9Sxc 	HAL_MODE_TURBO	= 0x002,	/* 11a turbo-only channels */
5620ba2cbe9Sxc 	HAL_MODE_11B	= 0x004,	/* 11b channels */
5630ba2cbe9Sxc 	HAL_MODE_PUREG	= 0x008,	/* 11g channels (OFDM only) */
5640ba2cbe9Sxc 	HAL_MODE_11G	= 0x008,	/* XXX historical */
5650ba2cbe9Sxc 	HAL_MODE_108G	= 0x020,	/* 11g+Turbo channels */
5660ba2cbe9Sxc 	HAL_MODE_108A	= 0x040,	/* 11a+Turbo channels */
5670ba2cbe9Sxc 	HAL_MODE_XR	= 0x100,	/* XR channels */
5680ba2cbe9Sxc 	HAL_MODE_11A_HALF_RATE = 0x200,	/* 11A half rate channels */
5690ba2cbe9Sxc 	HAL_MODE_11A_QUARTER_RATE = 0x400,	/* 11A quarter rate channels */
570*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_11NG_HT20	= 0x8000,
571*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_11NA_HT20	= 0x10000,
572*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_11NG_HT40PLUS	= 0x20000,
573*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_11NG_HT40MINUS	= 0x40000,
574*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_11NA_HT40PLUS	= 0x80000,
575*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_11NA_HT40MINUS	= 0x100000,
576*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_MODE_ALL	= 0xffffff
5777a1306a7Sxc };
5787a1306a7Sxc 
5797a1306a7Sxc typedef struct {
5807a1306a7Sxc 	int		rateCount;		/* NB: for proper padding */
581*129d67acSlin wang - Sun Microsystems - Beijing China 	uint8_t	rateCodeToIndex[144];	/* back mapping */
5827a1306a7Sxc 	struct {
5837a1306a7Sxc 		uint8_t	valid;		/* valid for rate control use */
5847a1306a7Sxc 		uint8_t	phy;		/* CCK/OFDM/XR */
585*129d67acSlin wang - Sun Microsystems - Beijing China 		uint32_t rateKbps;	/* transfer rate in kbs */
5867a1306a7Sxc 		uint8_t	rateCode;	/* rate for h/w descriptors */
5877a1306a7Sxc 		/* mask for enabling short preamble in CCK rate code */
5887a1306a7Sxc 		uint8_t	shortPreamble;
5897a1306a7Sxc 		/* value for supported rates info element of MLME */
5907a1306a7Sxc 		uint8_t	dot11Rate;
5917a1306a7Sxc 		/* index of next lower basic rate; used for dur. calcs */
5927a1306a7Sxc 		uint8_t	controlRate;
5937a1306a7Sxc 		uint16_t lpAckDuration;	/* long preamble ACK duration */
5947a1306a7Sxc 		uint16_t spAckDuration;	/* short preamble ACK duration */
5957a1306a7Sxc 	} info[32];
5967a1306a7Sxc } HAL_RATE_TABLE;
5977a1306a7Sxc 
5987a1306a7Sxc typedef struct {
5997a1306a7Sxc 	uint32_t	rs_count;	/* number of valid entries */
6007a1306a7Sxc 	uint8_t	rs_rates[32];		/* rates */
6017a1306a7Sxc } HAL_RATE_SET;
6027a1306a7Sxc 
603*129d67acSlin wang - Sun Microsystems - Beijing China /*
604*129d67acSlin wang - Sun Microsystems - Beijing China  * 802.11n specific structures and enums
605*129d67acSlin wang - Sun Microsystems - Beijing China  */
606*129d67acSlin wang - Sun Microsystems - Beijing China typedef enum {
607*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CHAINTYPE_TX	= 1,	/* Tx chain type */
608*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_CHAINTYPE_RX	= 2,	/* RX chain type */
609*129d67acSlin wang - Sun Microsystems - Beijing China } HAL_CHAIN_TYPE;
610*129d67acSlin wang - Sun Microsystems - Beijing China 
611*129d67acSlin wang - Sun Microsystems - Beijing China typedef struct {
612*129d67acSlin wang - Sun Microsystems - Beijing China 	uint_t	Tries;
613*129d67acSlin wang - Sun Microsystems - Beijing China 	uint_t	Rate;
614*129d67acSlin wang - Sun Microsystems - Beijing China 	uint_t	PktDuration;
615*129d67acSlin wang - Sun Microsystems - Beijing China 	uint_t	ChSel;
616*129d67acSlin wang - Sun Microsystems - Beijing China 	uint_t	RateFlags;
617*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RATESERIES_RTS_CTS	0x0001	/* use rts/cts w/this series */
618*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RATESERIES_2040	0x0002	/* use ext channel for series */
619*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_RATESERIES_HALFGI	0x0004	/* use half-gi for series */
620*129d67acSlin wang - Sun Microsystems - Beijing China } HAL_11N_RATE_SERIES;
621*129d67acSlin wang - Sun Microsystems - Beijing China 
622*129d67acSlin wang - Sun Microsystems - Beijing China typedef enum {
623*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_HT_MACMODE_20	= 0,	/* 20 MHz operation */
624*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_HT_MACMODE_2040	= 1	/* 20/40 MHz operation */
625*129d67acSlin wang - Sun Microsystems - Beijing China } HAL_HT_MACMODE;
626*129d67acSlin wang - Sun Microsystems - Beijing China 
627*129d67acSlin wang - Sun Microsystems - Beijing China typedef enum {
628*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_HT_PHYMODE_20	= 0,	/* 20 MHz operation */
629*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_HT_PHYMODE_2040	= 1	/* 20/40 MHz operation */
630*129d67acSlin wang - Sun Microsystems - Beijing China } HAL_HT_PHYMODE;
631*129d67acSlin wang - Sun Microsystems - Beijing China 
632*129d67acSlin wang - Sun Microsystems - Beijing China typedef enum {
633*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_HT_EXTPROTSPACING_20 = 0,	/* 20 MHz spacing */
634*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_HT_EXTPROTSPACING_25 = 1	/* 25 MHz spacing */
635*129d67acSlin wang - Sun Microsystems - Beijing China } HAL_HT_EXTPROTSPACING;
636*129d67acSlin wang - Sun Microsystems - Beijing China 
637*129d67acSlin wang - Sun Microsystems - Beijing China typedef enum {
638*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_RX_CLEAR_CTL_LOW	= 1,	/* force control chan to appear busy */
639*129d67acSlin wang - Sun Microsystems - Beijing China 	HAL_RX_CLEAR_EXT_LOW	= 2	/* force ext chan to appear busy */
640*129d67acSlin wang - Sun Microsystems - Beijing China } HAL_HT_RXCLEAR;
641*129d67acSlin wang - Sun Microsystems - Beijing China 
6420ba2cbe9Sxc /*
6430ba2cbe9Sxc  * Antenna switch control.  By default antenna selection
6440ba2cbe9Sxc  * enables multiple (2) antenna use.  To force use of the
6450ba2cbe9Sxc  * A or B antenna only specify a fixed setting.  Fixing
6460ba2cbe9Sxc  * the antenna will also disable any diversity support.
6470ba2cbe9Sxc  */
6487a1306a7Sxc typedef enum {
6497a1306a7Sxc 	HAL_ANT_VARIABLE = 0,		/* variable by programming */
6500ba2cbe9Sxc 	HAL_ANT_FIXED_A	 = 1,		/* fixed antenna A */
6510ba2cbe9Sxc 	HAL_ANT_FIXED_B	 = 2		/* fixed antenna B */
6527a1306a7Sxc } HAL_ANT_SETTING;
6537a1306a7Sxc 
6547a1306a7Sxc typedef enum {
6557a1306a7Sxc 	HAL_M_STA	= 1,		/* infrastructure station */
6567a1306a7Sxc 	HAL_M_IBSS	= 0,		/* IBSS (adhoc) station */
6577a1306a7Sxc 	HAL_M_HOSTAP	= 6,		/* Software Access Point */
6587a1306a7Sxc 	HAL_M_MONITOR	= 8		/* Monitor mode */
6597a1306a7Sxc } HAL_OPMODE;
6607a1306a7Sxc 
6617a1306a7Sxc typedef struct {
6627a1306a7Sxc 	uint8_t	kv_type;		/* one of HAL_CIPHER */
6637a1306a7Sxc 	uint8_t	kv_pad;
6647a1306a7Sxc 	uint16_t	kv_len;		/* length in bits */
6657a1306a7Sxc 	uint8_t	kv_val[16];		/* enough for 128-bit keys */
6667a1306a7Sxc 	uint8_t	kv_mic[8];		/* TKIP MIC key */
667*129d67acSlin wang - Sun Microsystems - Beijing China 	uint8_t	kv_txmic[8];		/* TKIP TX MIC key (optional) */
6687a1306a7Sxc } HAL_KEYVAL;
6697a1306a7Sxc 
6707a1306a7Sxc typedef enum {
6717a1306a7Sxc 	HAL_CIPHER_WEP		= 0,
6727a1306a7Sxc 	HAL_CIPHER_AES_OCB	= 1,
6737a1306a7Sxc 	HAL_CIPHER_AES_CCM	= 2,
6747a1306a7Sxc 	HAL_CIPHER_CKIP		= 3,
6757a1306a7Sxc 	HAL_CIPHER_TKIP		= 4,
6767a1306a7Sxc 	HAL_CIPHER_CLR		= 5,	/* no encryption */
6777a1306a7Sxc 
6787a1306a7Sxc 	HAL_CIPHER_MIC		= 127	/* TKIP-MIC, not a cipher */
6797a1306a7Sxc } HAL_CIPHER;
6807a1306a7Sxc 
6817a1306a7Sxc enum {
6820ba2cbe9Sxc 	HAL_SLOT_TIME_6  = 6,		/* NB: for turbo mode */
6837a1306a7Sxc 	HAL_SLOT_TIME_9	 = 9,
6847a1306a7Sxc 	HAL_SLOT_TIME_20 = 20
6857a1306a7Sxc };
6867a1306a7Sxc 
6877a1306a7Sxc /*
6887a1306a7Sxc  * Per-station beacon timer state.  Note that the specified
6897a1306a7Sxc  * beacon interval (given in TU's) can also include flags
6907a1306a7Sxc  * to force a TSF reset and to enable the beacon xmit logic.
6917a1306a7Sxc  * If bs_cfpmaxduration is non-zero the hardware is setup to
6927a1306a7Sxc  * coexist with a PCF-capable AP.
6937a1306a7Sxc  */
6947a1306a7Sxc typedef struct {
6957a1306a7Sxc 	uint32_t	bs_nexttbtt;		/* next beacon in TU */
6967a1306a7Sxc 	uint32_t	bs_nextdtim;		/* next DTIM in TU */
6977a1306a7Sxc 	uint32_t	bs_intval;		/* beacon interval+flags */
6987a1306a7Sxc 	uint32_t	bs_dtimperiod;
6997a1306a7Sxc 	uint16_t	bs_cfpperiod;		/* CFP period in TU */
7007a1306a7Sxc 	uint16_t	bs_cfpmaxduration;	/* max CFP duration in TU */
7017a1306a7Sxc 	uint32_t	bs_cfpnext;		/* next CFP in TU */
7027a1306a7Sxc 	uint16_t	bs_timoffset;		/* byte offset to TIM bitmap */
7037a1306a7Sxc 	uint16_t	bs_bmissthreshold;	/* beacon miss threshold */
7047a1306a7Sxc 	uint32_t	bs_sleepduration;	/* max sleep duration */
7057a1306a7Sxc } HAL_BEACON_STATE;
7067a1306a7Sxc 
7070ba2cbe9Sxc /*
7080ba2cbe9Sxc  * Like HAL_BEACON_STATE but for non-station mode setup.
7090ba2cbe9Sxc  * NB: see above flag definitions
7100ba2cbe9Sxc  */
7110ba2cbe9Sxc typedef struct {
7120ba2cbe9Sxc 	uint32_t	bt_intval;		/* beacon interval+flags */
7130ba2cbe9Sxc 	uint32_t	bt_nexttbtt;		/* next beacon in TU */
7140ba2cbe9Sxc 	uint32_t	bt_nextatim;		/* next ATIM in TU */
7150ba2cbe9Sxc 	uint32_t	bt_nextdba;		/* next DBA in 1/8th TU */
7160ba2cbe9Sxc 	uint32_t	bt_nextswba;		/* next SWBA in 1/8th TU */
717*129d67acSlin wang - Sun Microsystems - Beijing China 	uint32_t	bt_flags;		/* timer enables */
718*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_BEACON_TBTT_EN	0x00000001
719*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_BEACON_DBA_EN	0x00000002
720*129d67acSlin wang - Sun Microsystems - Beijing China #define	HAL_BEACON_SWBA_EN	0x00000004
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