17a1306a7Sxc /* 2*0ba2cbe9Sxc * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros 37a1306a7Sxc * Communications, Inc. All rights reserved. 47a1306a7Sxc * 57a1306a7Sxc * Use is subject to license terms. 67a1306a7Sxc * 77a1306a7Sxc * Redistribution and use in source and binary forms are permitted 87a1306a7Sxc * provided that the following conditions are met: 97a1306a7Sxc * 1. The materials contained herein are unmodified and are used 107a1306a7Sxc * unmodified. 117a1306a7Sxc * 2. Redistributions of source code must retain the above copyright 127a1306a7Sxc * notice, this list of conditions and the following NO 137a1306a7Sxc * ''WARRANTY'' disclaimer below (''Disclaimer''), without 147a1306a7Sxc * modification. 157a1306a7Sxc * 3. Redistributions in binary form must reproduce at minimum a 167a1306a7Sxc * disclaimer similar to the Disclaimer below and any redistribution 177a1306a7Sxc * must be conditioned upon including a substantially similar 187a1306a7Sxc * Disclaimer requirement for further binary redistribution. 197a1306a7Sxc * 4. Neither the names of the above-listed copyright holders nor the 207a1306a7Sxc * names of any contributors may be used to endorse or promote 217a1306a7Sxc * product derived from this software without specific prior written 227a1306a7Sxc * permission. 237a1306a7Sxc * 247a1306a7Sxc * NO WARRANTY 257a1306a7Sxc * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267a1306a7Sxc * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277a1306a7Sxc * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 287a1306a7Sxc * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 297a1306a7Sxc * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 307a1306a7Sxc * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317a1306a7Sxc * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 327a1306a7Sxc * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 337a1306a7Sxc * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 347a1306a7Sxc * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 357a1306a7Sxc * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 367a1306a7Sxc * SUCH DAMAGES. 377a1306a7Sxc * 387a1306a7Sxc */ 397a1306a7Sxc 407a1306a7Sxc #ifndef _ATH_HAL_H 417a1306a7Sxc #define _ATH_HAL_H 427a1306a7Sxc 437a1306a7Sxc #pragma ident "%Z%%M% %I% %E% SMI" 447a1306a7Sxc 457a1306a7Sxc /* 467a1306a7Sxc * ath_hal.h is released by Atheros and used to describe the Atheros 477a1306a7Sxc * Hardware Access Layer(HAL) interface. All kinds of data structures, 487a1306a7Sxc * constant definition, APIs declaration are defined here.Clients of 497a1306a7Sxc * the HAL call ath_hal_attach() to obtain a reference to an ath_hal 507a1306a7Sxc * structure for use with the device. Hardware-related operations that 517a1306a7Sxc * follow must call back into the HAL through interface, supplying the 527a1306a7Sxc * reference as the first parameter. 537a1306a7Sxc */ 547a1306a7Sxc 557a1306a7Sxc #ifdef __cplusplus 567a1306a7Sxc extern "C" { 577a1306a7Sxc #endif 587a1306a7Sxc 597a1306a7Sxc /* HAL version of this release */ 60*0ba2cbe9Sxc #define HAL_ABI_VERSION 0x06052200 /* YYMMDDnn */ 617a1306a7Sxc 627a1306a7Sxc /* HAL data type definition */ 63*0ba2cbe9Sxc typedef void * HAL_SOFTC; /* pointer to driver/OS state */ 64*0ba2cbe9Sxc typedef void * HAL_BUS_TAG; /* opaque bus i/o id tag */ 65*0ba2cbe9Sxc typedef void * HAL_BUS_HANDLE; /* opaque bus i/o handle */ 667a1306a7Sxc typedef uint32_t HAL_BUS_ADDR; 677a1306a7Sxc typedef uint16_t HAL_CTRY_CODE; /* country code */ 687a1306a7Sxc typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 697a1306a7Sxc 707a1306a7Sxc #define HAL_NUM_TX_QUEUES 10 /* max number of tx queues */ 717a1306a7Sxc 727a1306a7Sxc #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 737a1306a7Sxc #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 747a1306a7Sxc #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 757a1306a7Sxc 767a1306a7Sxc #define CHANNEL_RAD_INT 0x0001 /* Radar interference detected on channel */ 777a1306a7Sxc #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ 787a1306a7Sxc #define CHANNEL_BUSY 0x0004 /* Busy, occupied or overlap with adjoin chan */ 797a1306a7Sxc #define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 807a1306a7Sxc #define CHANNEL_CCK 0x0020 /* CCK channel */ 817a1306a7Sxc #define CHANNEL_OFDM 0x0040 /* OFDM channel */ 827a1306a7Sxc #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ 837a1306a7Sxc #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ 847a1306a7Sxc #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ 857a1306a7Sxc #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ 867a1306a7Sxc #define CHANNEL_XR 0x0800 /* XR channel */ 87*0ba2cbe9Sxc #define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ 88*0ba2cbe9Sxc #define CHANNEL_HALF 0x4000 /* Half rate channel */ 89*0ba2cbe9Sxc #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ 907a1306a7Sxc 917a1306a7Sxc #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 927a1306a7Sxc #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 937a1306a7Sxc #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) 947a1306a7Sxc #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 957a1306a7Sxc #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 96*0ba2cbe9Sxc #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) 977a1306a7Sxc #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 98*0ba2cbe9Sxc #define CHANNEL_108A CHANNEL_T 997a1306a7Sxc #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 1007a1306a7Sxc #define CHANNEL_ALL \ 1017a1306a7Sxc (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ|CHANNEL_TURBO) 1027a1306a7Sxc #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) 1037a1306a7Sxc 104*0ba2cbe9Sxc #define CHANNEL_COMPAT (CHANNEL_ALL_NOTURBO | CHANNEL_PASSIVE) 105*0ba2cbe9Sxc 106*0ba2cbe9Sxc /* privFlags */ 107*0ba2cbe9Sxc /* 108*0ba2cbe9Sxc * Software use: channel interference used for AR as well as RADAR 109*0ba2cbe9Sxc * interference detection 110*0ba2cbe9Sxc */ 111*0ba2cbe9Sxc #define CHANNEL_INTERFERENCE 0x01 112*0ba2cbe9Sxc #define CHANNEL_DFS 0x02 /* DFS required on channel */ 113*0ba2cbe9Sxc #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ 114*0ba2cbe9Sxc #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked DFS */ 115*0ba2cbe9Sxc 1167a1306a7Sxc #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 1177a1306a7Sxc 1187a1306a7Sxc /* flags passed to tx descriptor setup methods */ 1197a1306a7Sxc #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 1207a1306a7Sxc #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 1217a1306a7Sxc #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 1227a1306a7Sxc #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 1237a1306a7Sxc #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 1247a1306a7Sxc #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 125*0ba2cbe9Sxc /* NB: this only affects frame, not any RTS/CTS */ 126*0ba2cbe9Sxc #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 1277a1306a7Sxc 1287a1306a7Sxc /* flags passed to rx descriptor setup methods */ 1297a1306a7Sxc #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 1307a1306a7Sxc 1317a1306a7Sxc /* tx error flags */ 1327a1306a7Sxc #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 1337a1306a7Sxc #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 1347a1306a7Sxc #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 1357a1306a7Sxc #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */ 1367a1306a7Sxc 1377a1306a7Sxc /* rx error flags */ 1387a1306a7Sxc #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 1397a1306a7Sxc #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 1407a1306a7Sxc #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 1417a1306a7Sxc #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 1427a1306a7Sxc #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 1437a1306a7Sxc 1447a1306a7Sxc /* value found in rs_keyix to mark invalid entries */ 1457a1306a7Sxc #define HAL_RXKEYIX_INVALID ((uint8_t)-1) 1467a1306a7Sxc 1477a1306a7Sxc /* value used to specify no encryption key for xmit */ 1487a1306a7Sxc #define HAL_TXKEYIX_INVALID ((uint32_t)-1) 1497a1306a7Sxc 150*0ba2cbe9Sxc /* compression definitions */ 151*0ba2cbe9Sxc #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9k */ 152*0ba2cbe9Sxc #define HAL_COMP_BUF_ALIGN_SIZE 512 153*0ba2cbe9Sxc #define HAL_DECOMP_MASK_SIZE 128 154*0ba2cbe9Sxc 155*0ba2cbe9Sxc #define HAL_ANTENNA_MIN_MODE 0 156*0ba2cbe9Sxc #define HAL_ANTENNA_FIXED_A 1 157*0ba2cbe9Sxc #define HAL_ANTENNA_FIXED_B 2 158*0ba2cbe9Sxc #define HAL_ANTENNA_MAX_MODE 3 159*0ba2cbe9Sxc 1607a1306a7Sxc /* 1617a1306a7Sxc * Status codes that may be returned by the HAL. Note that 1627a1306a7Sxc * interfaces that return a status code set it only when an 1637a1306a7Sxc * error occurs--i.e. you cannot check it for success. 1647a1306a7Sxc */ 1657a1306a7Sxc typedef enum { 1667a1306a7Sxc HAL_OK = 0, /* No error */ 1677a1306a7Sxc HAL_ENXIO = 1, /* No hardware present */ 1687a1306a7Sxc HAL_ENOMEM = 2, /* Memory allocation failed */ 1697a1306a7Sxc HAL_EIO = 3, /* Hardware didn't respond as expected */ 1707a1306a7Sxc HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 1717a1306a7Sxc HAL_EEVERSION = 5, /* EEPROM version invalid */ 1727a1306a7Sxc HAL_EELOCKED = 6, /* EEPROM unreadable */ 1737a1306a7Sxc HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 1747a1306a7Sxc HAL_EEREAD = 8, /* EEPROM read problem */ 1757a1306a7Sxc HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 1767a1306a7Sxc HAL_EESIZE = 10, /* EEPROM size not supported */ 1777a1306a7Sxc HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 1787a1306a7Sxc HAL_EINVAL = 12, /* Invalid parameter to function */ 1797a1306a7Sxc HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 1807a1306a7Sxc HAL_ESELFTEST = 14, /* Hardware self-test failed */ 1817a1306a7Sxc HAL_EINPROGRESS = 15 /* Operation incomplete */ 1827a1306a7Sxc } HAL_STATUS; 1837a1306a7Sxc 1847a1306a7Sxc typedef enum { 1857a1306a7Sxc AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 1867a1306a7Sxc AH_TRUE = 1 1877a1306a7Sxc } HAL_BOOL; 1887a1306a7Sxc 1897a1306a7Sxc typedef enum { 1907a1306a7Sxc HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 1917a1306a7Sxc HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 1927a1306a7Sxc HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 1937a1306a7Sxc HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 1947a1306a7Sxc HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 1957a1306a7Sxc HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 1967a1306a7Sxc HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 1977a1306a7Sxc HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 1987a1306a7Sxc HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 1997a1306a7Sxc HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll */ 2007a1306a7Sxc /* support */ 2017a1306a7Sxc HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 2027a1306a7Sxc HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 2037a1306a7Sxc HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 2047a1306a7Sxc HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 2057a1306a7Sxc HAL_CAP_TXPOW = 15, /* global tx power limit */ 206*0ba2cbe9Sxc HAL_CAP_TPC = 16, /* per-packet tx power control */ 207*0ba2cbe9Sxc HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 208*0ba2cbe9Sxc HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 209*0ba2cbe9Sxc HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 210*0ba2cbe9Sxc HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 211*0ba2cbe9Sxc HAL_CAP_XR = 21, /* hardware has XR support */ 212*0ba2cbe9Sxc /* hardware can support TKIP MIC when WMM is turned on */ 213*0ba2cbe9Sxc HAL_CAP_WME_TKIPMIC = 22, 214*0ba2cbe9Sxc /* hardware can support half rate channels */ 215*0ba2cbe9Sxc HAL_CAP_CHAN_HALFRATE = 23, 216*0ba2cbe9Sxc /* hardware can support quarter rate channels */ 217*0ba2cbe9Sxc HAL_CAP_CHAN_QUARTERRATE = 24, 218*0ba2cbe9Sxc HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 219*0ba2cbe9Sxc HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 220*0ba2cbe9Sxc HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 221*0ba2cbe9Sxc HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 222*0ba2cbe9Sxc HAL_CAP_INTMIT = 29 /* interference mitigation */ 2237a1306a7Sxc } HAL_CAPABILITY_TYPE; 2247a1306a7Sxc 2257a1306a7Sxc /* 2267a1306a7Sxc * "States" for setting the LED. These correspond to 2277a1306a7Sxc * the possible 802.11 operational states and there may 2287a1306a7Sxc * be a many-to-one mapping between these states and the 2297a1306a7Sxc * actual hardware states for the LED's (i.e. the hardware 2307a1306a7Sxc * may have fewer states). 2317a1306a7Sxc */ 2327a1306a7Sxc typedef enum { 2337a1306a7Sxc HAL_LED_INIT = 0, 2347a1306a7Sxc HAL_LED_SCAN = 1, 2357a1306a7Sxc HAL_LED_AUTH = 2, 2367a1306a7Sxc HAL_LED_ASSOC = 3, 2377a1306a7Sxc HAL_LED_RUN = 4 2387a1306a7Sxc } HAL_LED_STATE; 2397a1306a7Sxc 2407a1306a7Sxc /* 2417a1306a7Sxc * Transmit queue types/numbers. These are used to tag 2427a1306a7Sxc * each transmit queue in the hardware and to identify a set 2437a1306a7Sxc * of transmit queues for operations such as start/stop dma. 2447a1306a7Sxc */ 2457a1306a7Sxc typedef enum { 2467a1306a7Sxc HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 2477a1306a7Sxc HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 2487a1306a7Sxc HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 2497a1306a7Sxc HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 250*0ba2cbe9Sxc HAL_TX_QUEUE_UAPSD = 4 /* u-apsd power save xmit q */ 2517a1306a7Sxc } HAL_TX_QUEUE; 2527a1306a7Sxc 2537a1306a7Sxc 2547a1306a7Sxc /* 2557a1306a7Sxc * Transmit queue subtype. These map directly to 2567a1306a7Sxc * WME Access Categories (except for UPSD). Refer 2577a1306a7Sxc * to Table 5 of the WME spec. 2587a1306a7Sxc */ 2597a1306a7Sxc typedef enum { 2607a1306a7Sxc HAL_WME_AC_BK = 0, /* background access category */ 2617a1306a7Sxc HAL_WME_AC_BE = 1, /* best effort access category */ 2627a1306a7Sxc HAL_WME_AC_VI = 2, /* video access category */ 2637a1306a7Sxc HAL_WME_AC_VO = 3, /* voice access category */ 264*0ba2cbe9Sxc HAL_WME_UPSD = 4, /* uplink power save */ 265*0ba2cbe9Sxc HAL_XR_DATA = 5 /* entended range data */ 2667a1306a7Sxc } HAL_TX_QUEUE_SUBTYPE; 2677a1306a7Sxc 2687a1306a7Sxc /* 2697a1306a7Sxc * Transmit queue flags that control various 2707a1306a7Sxc * operational parameters. 2717a1306a7Sxc */ 2727a1306a7Sxc typedef enum { 273*0ba2cbe9Sxc /* 274*0ba2cbe9Sxc * Per queue interrupt enables. When set the associated 275*0ba2cbe9Sxc * interrupt may be delivered for packets sent through 276*0ba2cbe9Sxc * the queue. Without these enabled no interrupts will 277*0ba2cbe9Sxc * be delivered for transmits through the queue. 278*0ba2cbe9Sxc * 279*0ba2cbe9Sxc * When 0x0001 is set, both TXQ_TXOKINT and TXQ_TXERRINT 280*0ba2cbe9Sxc * will be enabled. 281*0ba2cbe9Sxc */ 282*0ba2cbe9Sxc HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 283*0ba2cbe9Sxc HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 284*0ba2cbe9Sxc HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 285*0ba2cbe9Sxc HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 286*0ba2cbe9Sxc HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 287*0ba2cbe9Sxc /* 288*0ba2cbe9Sxc * Enable hardware compression for packets sent through 289*0ba2cbe9Sxc * the queue. The compression buffer must be setup and 290*0ba2cbe9Sxc * packets must have a key entry marked in the tx descriptor. 291*0ba2cbe9Sxc */ 292*0ba2cbe9Sxc HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 293*0ba2cbe9Sxc /* 294*0ba2cbe9Sxc * Disable queue when veol is hit or ready time expires. 295*0ba2cbe9Sxc * By default the queue is disabled only on reaching the 296*0ba2cbe9Sxc * physical end of queue (i.e. a null link ptr in the 297*0ba2cbe9Sxc * descriptor chain). 298*0ba2cbe9Sxc */ 299*0ba2cbe9Sxc HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 300*0ba2cbe9Sxc /* 301*0ba2cbe9Sxc * Schedule frames on delivery of a DBA (DMA Beacon Alert) 302*0ba2cbe9Sxc * event. Frames will be transmitted only when this timer 303*0ba2cbe9Sxc * fires, e.g to transmit a beacon in ap or adhoc modes. 304*0ba2cbe9Sxc */ 305*0ba2cbe9Sxc HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 306*0ba2cbe9Sxc /* 307*0ba2cbe9Sxc * Each transmit queue has a counter that is incremented 308*0ba2cbe9Sxc * each time the queue is enabled and decremented when 309*0ba2cbe9Sxc * the list of frames to transmit is traversed (or when 310*0ba2cbe9Sxc * the ready time for the queue expires). This counter 311*0ba2cbe9Sxc * must be non-zero for frames to be scheduled for 312*0ba2cbe9Sxc * transmission. The following controls disable bumping 313*0ba2cbe9Sxc * this counter under certain conditions. Typically this 314*0ba2cbe9Sxc * is used to gate frames based on the contents of another 315*0ba2cbe9Sxc * queue (e.g. CAB traffic may only follow a beacon frame). 316*0ba2cbe9Sxc * These are meaningful only when frames are scheduled 317*0ba2cbe9Sxc * with a non-ASAP policy (e.g. DBA-gated). 318*0ba2cbe9Sxc */ 319*0ba2cbe9Sxc HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 320*0ba2cbe9Sxc HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 321*0ba2cbe9Sxc 322*0ba2cbe9Sxc /* 323*0ba2cbe9Sxc * Fragment burst backoff policy. Normally no backoff 324*0ba2cbe9Sxc * is done after a successful transmission, the next fragment 325*0ba2cbe9Sxc * is sent at SIFS. If this flag is set backoff is done 326*0ba2cbe9Sxc * after each fragment, regardless whether it was ack'd or 327*0ba2cbe9Sxc * not, after the backoff count reaches zero a normal channel 328*0ba2cbe9Sxc * access procedure is done before the next transmit (i.e. 329*0ba2cbe9Sxc * wait AIFS instead of SIFS). 330*0ba2cbe9Sxc */ 331*0ba2cbe9Sxc HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 332*0ba2cbe9Sxc /* 333*0ba2cbe9Sxc * Disable post-tx backoff following each frame. 334*0ba2cbe9Sxc */ 335*0ba2cbe9Sxc HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 336*0ba2cbe9Sxc /* 337*0ba2cbe9Sxc * DCU arbiter lockout control. This controls how 338*0ba2cbe9Sxc * lower priority tx queues are handled with respect 339*0ba2cbe9Sxc * to a specific queue when multiple queues have frames 340*0ba2cbe9Sxc * to send. No lockout means lower priority queues arbitrate 341*0ba2cbe9Sxc * concurrently with this queue. Intra-frame lockout 342*0ba2cbe9Sxc * means lower priority queues are locked out until the 343*0ba2cbe9Sxc * current frame transmits (e.g. including backoffs and bursting). 344*0ba2cbe9Sxc * Global lockout means nothing lower can arbitrary so 345*0ba2cbe9Sxc * long as there is traffic activity on this queue (frames, 346*0ba2cbe9Sxc * backoff, etc). 347*0ba2cbe9Sxc */ 348*0ba2cbe9Sxc HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 349*0ba2cbe9Sxc HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 350*0ba2cbe9Sxc 351*0ba2cbe9Sxc HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 352*0ba2cbe9Sxc HAL_TXQ_SEQNUM_INC_DIS = 0x00100000 /* disable seqnum increment */ 3537a1306a7Sxc } HAL_TX_QUEUE_FLAGS; 3547a1306a7Sxc 3557a1306a7Sxc typedef struct { 3567a1306a7Sxc uint32_t tqi_ver; /* hal TXQ version */ 3577a1306a7Sxc HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 3587a1306a7Sxc HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 3597a1306a7Sxc uint32_t tqi_priority; /* (not used) */ 3607a1306a7Sxc uint32_t tqi_aifs; /* AIFS shift */ 3617a1306a7Sxc int32_t tqi_cwmin; /* cwMin shift */ 3627a1306a7Sxc int32_t tqi_cwmax; /* cwMax shift */ 3637a1306a7Sxc uint16_t tqi_shretry; /* rts retry limit */ 3647a1306a7Sxc uint16_t tqi_lgretry; /* long retry limit(not used) */ 3657a1306a7Sxc uint32_t tqi_cbrPeriod; 3667a1306a7Sxc uint32_t tqi_cbrOverflowLimit; 3677a1306a7Sxc uint32_t tqi_burstTime; 3687a1306a7Sxc uint32_t tqi_readyTime; 369*0ba2cbe9Sxc uint32_t tqi_compBuf; /* compress buffer phys addr */ 3707a1306a7Sxc } HAL_TXQ_INFO; 3717a1306a7Sxc 372*0ba2cbe9Sxc #define HAL_TQI_NONVAL 0xffff 373*0ba2cbe9Sxc 3747a1306a7Sxc /* token to use for aifs, cwmin, cwmax */ 3757a1306a7Sxc #define HAL_TXQ_USEDEFAULT ((uint32_t)-1) 3767a1306a7Sxc 3777a1306a7Sxc /* 3787a1306a7Sxc * Transmit packet types. This belongs in ah_desc.h, but 3797a1306a7Sxc * is here so we can give a proper type to various parameters 3807a1306a7Sxc * (and not require everyone include the file). 3817a1306a7Sxc * 3827a1306a7Sxc * NB: These values are intentionally assigned for 3837a1306a7Sxc * direct use when setting up h/w descriptors. 3847a1306a7Sxc */ 3857a1306a7Sxc typedef enum { 3867a1306a7Sxc HAL_PKT_TYPE_NORMAL = 0, 3877a1306a7Sxc HAL_PKT_TYPE_ATIM = 1, 3887a1306a7Sxc HAL_PKT_TYPE_PSPOLL = 2, 3897a1306a7Sxc HAL_PKT_TYPE_BEACON = 3, 390*0ba2cbe9Sxc HAL_PKT_TYPE_PROBE_RESP = 4, 391*0ba2cbe9Sxc HAL_PKT_TYPE_CHIRP = 5, 392*0ba2cbe9Sxc HAL_PKT_TYPE_GRP_POLL = 6 3937a1306a7Sxc } HAL_PKT_TYPE; 3947a1306a7Sxc 3957a1306a7Sxc /* Rx Filter Frame Types */ 3967a1306a7Sxc typedef enum { 3977a1306a7Sxc HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 3987a1306a7Sxc HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 3997a1306a7Sxc HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 4007a1306a7Sxc HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 4017a1306a7Sxc HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 4027a1306a7Sxc HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 403*0ba2cbe9Sxc HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ 4047a1306a7Sxc HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 4057a1306a7Sxc HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 4067a1306a7Sxc HAL_RX_FILTER_PHYRADAR = 0x00000200 /* Allow phy radar errors */ 4077a1306a7Sxc } HAL_RX_FILTER; 4087a1306a7Sxc 4097a1306a7Sxc typedef enum { 410*0ba2cbe9Sxc HAL_PM_AWAKE = 0, 411*0ba2cbe9Sxc HAL_PM_FULL_SLEEP = 1, 412*0ba2cbe9Sxc HAL_PM_NETWORK_SLEEP = 2, 413*0ba2cbe9Sxc HAL_PM_UNDEFINED = 3 4147a1306a7Sxc } HAL_POWER_MODE; 4157a1306a7Sxc 4167a1306a7Sxc /* 4177a1306a7Sxc * NOTE WELL: 4187a1306a7Sxc * These are mapped to take advantage of the common locations for many of 4197a1306a7Sxc * the bits on all of the currently supported MAC chips. This is to make 4207a1306a7Sxc * the ISR as efficient as possible, while still abstracting HW differences. 4217a1306a7Sxc * When new hardware breaks this commonality this enumerated type, as well 4227a1306a7Sxc * as the HAL functions using it, must be modified. All values are directly 4237a1306a7Sxc * mapped unless commented otherwise. 4247a1306a7Sxc */ 4257a1306a7Sxc typedef enum { 4267a1306a7Sxc HAL_INT_RX = 0x00000001, /* Non-common mapping */ 4277a1306a7Sxc HAL_INT_RXDESC = 0x00000002, 4287a1306a7Sxc HAL_INT_RXNOFRM = 0x00000008, 4297a1306a7Sxc HAL_INT_RXEOL = 0x00000010, 4307a1306a7Sxc HAL_INT_RXORN = 0x00000020, 4317a1306a7Sxc HAL_INT_TX = 0x00000040, /* Non-common mapping */ 4327a1306a7Sxc HAL_INT_TXDESC = 0x00000080, 4337a1306a7Sxc HAL_INT_TXURN = 0x00000800, 4347a1306a7Sxc HAL_INT_MIB = 0x00001000, 4357a1306a7Sxc HAL_INT_RXPHY = 0x00004000, 4367a1306a7Sxc HAL_INT_RXKCM = 0x00008000, 4377a1306a7Sxc HAL_INT_SWBA = 0x00010000, 4387a1306a7Sxc HAL_INT_BMISS = 0x00040000, 4397a1306a7Sxc HAL_INT_BNR = 0x00100000, /* Non-common mapping */ 440*0ba2cbe9Sxc HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 441*0ba2cbe9Sxc HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 442*0ba2cbe9Sxc HAL_INT_DTIMSYNC = 0x00800000, /* Non-common mapping */ 4437a1306a7Sxc HAL_INT_GPIO = 0x01000000, 444*0ba2cbe9Sxc HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 4457a1306a7Sxc HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 4467a1306a7Sxc HAL_INT_GLOBAL = INT_MIN, /* Set/clear IER */ 447*0ba2cbe9Sxc HAL_INT_BMISC = HAL_INT_TIM 448*0ba2cbe9Sxc | HAL_INT_DTIM 449*0ba2cbe9Sxc | HAL_INT_DTIMSYNC 450*0ba2cbe9Sxc | HAL_INT_CABEND, 4517a1306a7Sxc 4527a1306a7Sxc /* Interrupt bits that map directly to ISR/IMR bits */ 4537a1306a7Sxc HAL_INT_COMMON = HAL_INT_RXNOFRM 4547a1306a7Sxc | HAL_INT_RXDESC 4557a1306a7Sxc | HAL_INT_RXEOL 4567a1306a7Sxc | HAL_INT_RXORN 4577a1306a7Sxc | HAL_INT_TXURN 4587a1306a7Sxc | HAL_INT_TXDESC 4597a1306a7Sxc | HAL_INT_MIB 4607a1306a7Sxc | HAL_INT_RXPHY 4617a1306a7Sxc | HAL_INT_RXKCM 4627a1306a7Sxc | HAL_INT_SWBA 4637a1306a7Sxc | HAL_INT_BMISS 4647a1306a7Sxc | HAL_INT_GPIO, 4657a1306a7Sxc HAL_INT_NOCARD = -1 /* To signal the card was removed */ 4667a1306a7Sxc } HAL_INT; 4677a1306a7Sxc 4687a1306a7Sxc typedef enum { 4697a1306a7Sxc HAL_RFGAIN_INACTIVE = 0, 4707a1306a7Sxc HAL_RFGAIN_READ_REQUESTED = 1, 4717a1306a7Sxc HAL_RFGAIN_NEED_CHANGE = 2 4727a1306a7Sxc } HAL_RFGAIN; 4737a1306a7Sxc 4747a1306a7Sxc typedef enum { 4757a1306a7Sxc HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 4767a1306a7Sxc HAL_PHYERR_TIMING = 1, /* Timing error */ 4777a1306a7Sxc HAL_PHYERR_PARITY = 2, /* Illegal parity */ 4787a1306a7Sxc HAL_PHYERR_RATE = 3, /* Illegal rate */ 4797a1306a7Sxc HAL_PHYERR_LENGTH = 4, /* Illegal length */ 4807a1306a7Sxc HAL_PHYERR_RADAR = 5, /* Radar detect */ 4817a1306a7Sxc HAL_PHYERR_SERVICE = 6, /* Illegal service */ 4827a1306a7Sxc HAL_PHYERR_TOR = 7, /* Transmit override receive */ 4837a1306a7Sxc /* NB: these are specific to the 5212 */ 4847a1306a7Sxc HAL_PHYERR_OFDM_TIMING = 17, /* */ 4857a1306a7Sxc HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 4867a1306a7Sxc HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 4877a1306a7Sxc HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 4887a1306a7Sxc HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 4897a1306a7Sxc HAL_PHYERR_OFDM_SERVICE = 22, /* */ 4907a1306a7Sxc HAL_PHYERR_OFDM_RESTART = 23, /* */ 4917a1306a7Sxc HAL_PHYERR_CCK_TIMING = 25, /* */ 4927a1306a7Sxc HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 4937a1306a7Sxc HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 4947a1306a7Sxc HAL_PHYERR_CCK_SERVICE = 30, /* */ 4957a1306a7Sxc HAL_PHYERR_CCK_RESTART = 31 /* */ 4967a1306a7Sxc }HAL_PHYERR; 4977a1306a7Sxc 4987a1306a7Sxc /* 4997a1306a7Sxc * Channels are specified by frequency. 5007a1306a7Sxc */ 5017a1306a7Sxc typedef struct { 5027a1306a7Sxc uint16_t channel; /* setting in Mhz */ 5037a1306a7Sxc uint16_t channelFlags; /* see below */ 504*0ba2cbe9Sxc uint8_t privFlags; 505*0ba2cbe9Sxc int8_t maxRegTxPower; /* max regulatory tx power in dBm */ 506*0ba2cbe9Sxc int8_t maxTxPower; /* max true tx power in 0.5 dBm */ 507*0ba2cbe9Sxc int8_t minTxPower; /* min true tx power in 0.5 dBm */ 5087a1306a7Sxc } HAL_CHANNEL; 5097a1306a7Sxc 5107a1306a7Sxc 5117a1306a7Sxc typedef struct { 5127a1306a7Sxc uint32_t ackrcv_bad; 5137a1306a7Sxc uint32_t rts_bad; 5147a1306a7Sxc uint32_t rts_good; 5157a1306a7Sxc uint32_t fcs_bad; 5167a1306a7Sxc uint32_t beacons; 5177a1306a7Sxc } HAL_MIB_STATS; 5187a1306a7Sxc 5197a1306a7Sxc 5207a1306a7Sxc enum { 5217a1306a7Sxc CTRY_DEBUG = 0x1ff, /* debug country code */ 5227a1306a7Sxc CTRY_DEFAULT = 0 /* default country code */ 5237a1306a7Sxc }; 5247a1306a7Sxc 5257a1306a7Sxc enum { 526*0ba2cbe9Sxc HAL_MODE_11A = 0x001, /* 11a channels */ 527*0ba2cbe9Sxc HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 528*0ba2cbe9Sxc HAL_MODE_11B = 0x004, /* 11b channels */ 529*0ba2cbe9Sxc HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 530*0ba2cbe9Sxc HAL_MODE_11G = 0x008, /* XXX historical */ 531*0ba2cbe9Sxc HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 532*0ba2cbe9Sxc HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 533*0ba2cbe9Sxc HAL_MODE_XR = 0x100, /* XR channels */ 534*0ba2cbe9Sxc HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ 535*0ba2cbe9Sxc HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ 5367a1306a7Sxc HAL_MODE_ALL = 0xfff 5377a1306a7Sxc }; 5387a1306a7Sxc 5397a1306a7Sxc typedef struct { 5407a1306a7Sxc int rateCount; /* NB: for proper padding */ 5417a1306a7Sxc uint8_t rateCodeToIndex[32]; /* back mapping */ 5427a1306a7Sxc struct { 5437a1306a7Sxc uint8_t valid; /* valid for rate control use */ 5447a1306a7Sxc uint8_t phy; /* CCK/OFDM/XR */ 5457a1306a7Sxc uint16_t rateKbps; /* transfer rate in kbs */ 5467a1306a7Sxc uint8_t rateCode; /* rate for h/w descriptors */ 5477a1306a7Sxc /* mask for enabling short preamble in CCK rate code */ 5487a1306a7Sxc uint8_t shortPreamble; 5497a1306a7Sxc /* value for supported rates info element of MLME */ 5507a1306a7Sxc uint8_t dot11Rate; 5517a1306a7Sxc /* index of next lower basic rate; used for dur. calcs */ 5527a1306a7Sxc uint8_t controlRate; 5537a1306a7Sxc uint16_t lpAckDuration; /* long preamble ACK duration */ 5547a1306a7Sxc uint16_t spAckDuration; /* short preamble ACK duration */ 5557a1306a7Sxc } info[32]; 5567a1306a7Sxc } HAL_RATE_TABLE; 5577a1306a7Sxc 5587a1306a7Sxc typedef struct { 5597a1306a7Sxc uint32_t rs_count; /* number of valid entries */ 5607a1306a7Sxc uint8_t rs_rates[32]; /* rates */ 5617a1306a7Sxc } HAL_RATE_SET; 5627a1306a7Sxc 563*0ba2cbe9Sxc /* 564*0ba2cbe9Sxc * Antenna switch control. By default antenna selection 565*0ba2cbe9Sxc * enables multiple (2) antenna use. To force use of the 566*0ba2cbe9Sxc * A or B antenna only specify a fixed setting. Fixing 567*0ba2cbe9Sxc * the antenna will also disable any diversity support. 568*0ba2cbe9Sxc */ 5697a1306a7Sxc typedef enum { 5707a1306a7Sxc HAL_ANT_VARIABLE = 0, /* variable by programming */ 571*0ba2cbe9Sxc HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 572*0ba2cbe9Sxc HAL_ANT_FIXED_B = 2 /* fixed antenna B */ 5737a1306a7Sxc } HAL_ANT_SETTING; 5747a1306a7Sxc 5757a1306a7Sxc typedef enum { 5767a1306a7Sxc HAL_M_STA = 1, /* infrastructure station */ 5777a1306a7Sxc HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 5787a1306a7Sxc HAL_M_HOSTAP = 6, /* Software Access Point */ 5797a1306a7Sxc HAL_M_MONITOR = 8 /* Monitor mode */ 5807a1306a7Sxc } HAL_OPMODE; 5817a1306a7Sxc 5827a1306a7Sxc typedef struct { 5837a1306a7Sxc uint8_t kv_type; /* one of HAL_CIPHER */ 5847a1306a7Sxc uint8_t kv_pad; 5857a1306a7Sxc uint16_t kv_len; /* length in bits */ 5867a1306a7Sxc uint8_t kv_val[16]; /* enough for 128-bit keys */ 5877a1306a7Sxc uint8_t kv_mic[8]; /* TKIP MIC key */ 5887a1306a7Sxc } HAL_KEYVAL; 5897a1306a7Sxc 5907a1306a7Sxc typedef enum { 5917a1306a7Sxc HAL_CIPHER_WEP = 0, 5927a1306a7Sxc HAL_CIPHER_AES_OCB = 1, 5937a1306a7Sxc HAL_CIPHER_AES_CCM = 2, 5947a1306a7Sxc HAL_CIPHER_CKIP = 3, 5957a1306a7Sxc HAL_CIPHER_TKIP = 4, 5967a1306a7Sxc HAL_CIPHER_CLR = 5, /* no encryption */ 5977a1306a7Sxc 5987a1306a7Sxc HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 5997a1306a7Sxc } HAL_CIPHER; 6007a1306a7Sxc 6017a1306a7Sxc enum { 602*0ba2cbe9Sxc HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 6037a1306a7Sxc HAL_SLOT_TIME_9 = 9, 6047a1306a7Sxc HAL_SLOT_TIME_20 = 20 6057a1306a7Sxc }; 6067a1306a7Sxc 6077a1306a7Sxc /* 6087a1306a7Sxc * Per-station beacon timer state. Note that the specified 6097a1306a7Sxc * beacon interval (given in TU's) can also include flags 6107a1306a7Sxc * to force a TSF reset and to enable the beacon xmit logic. 6117a1306a7Sxc * If bs_cfpmaxduration is non-zero the hardware is setup to 6127a1306a7Sxc * coexist with a PCF-capable AP. 6137a1306a7Sxc */ 6147a1306a7Sxc typedef struct { 6157a1306a7Sxc uint32_t bs_nexttbtt; /* next beacon in TU */ 6167a1306a7Sxc uint32_t bs_nextdtim; /* next DTIM in TU */ 6177a1306a7Sxc uint32_t bs_intval; /* beacon interval+flags */ 6187a1306a7Sxc uint32_t bs_dtimperiod; 6197a1306a7Sxc uint16_t bs_cfpperiod; /* CFP period in TU */ 6207a1306a7Sxc uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 6217a1306a7Sxc uint32_t bs_cfpnext; /* next CFP in TU */ 6227a1306a7Sxc uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 6237a1306a7Sxc uint16_t bs_bmissthreshold; /* beacon miss threshold */ 6247a1306a7Sxc uint32_t bs_sleepduration; /* max sleep duration */ 6257a1306a7Sxc } HAL_BEACON_STATE; 6267a1306a7Sxc 627*0ba2cbe9Sxc /* 628*0ba2cbe9Sxc * Like HAL_BEACON_STATE but for non-station mode setup. 629*0ba2cbe9Sxc * NB: see above flag definitions 630*0ba2cbe9Sxc */ 631*0ba2cbe9Sxc typedef struct { 632*0ba2cbe9Sxc uint32_t bt_intval; /* beacon interval+flags */ 633*0ba2cbe9Sxc uint32_t bt_nexttbtt; /* next beacon in TU */ 634*0ba2cbe9Sxc uint32_t bt_nextatim; /* next ATIM in TU */ 635*0ba2cbe9Sxc uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 636*0ba2cbe9Sxc uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 637*0ba2cbe9Sxc } HAL_BEACON_TIMERS; 638*0ba2cbe9Sxc 6397a1306a7Sxc /* 6407a1306a7Sxc * Per-node statistics maintained by the driver for use in 6417a1306a7Sxc * optimizing signal quality and other operational aspects. 6427a1306a7Sxc */ 6437a1306a7Sxc typedef struct { 6447a1306a7Sxc uint32_t ns_avgbrssi; /* average beacon rssi */ 6457a1306a7Sxc uint32_t ns_avgrssi; /* average data rssi */ 6467a1306a7Sxc uint32_t ns_avgtxrssi; /* average tx rssi */ 6477a1306a7Sxc } HAL_NODE_STATS; 6487a1306a7Sxc 6497a1306a7Sxc /* 6507a1306a7Sxc * Transmit descriptor status. This structure is filled 6517a1306a7Sxc * in only after the tx descriptor process method finds a 6527a1306a7Sxc * ``done'' descriptor; at which point it returns something 6537a1306a7Sxc * other than HAL_EINPROGRESS. 6547a1306a7Sxc * 6557a1306a7Sxc * Note that ts_antenna may not be valid for all h/w. It 6567a1306a7Sxc * should be used only if non-zero. 6577a1306a7Sxc */ 6587a1306a7Sxc struct ath_tx_status { 6597a1306a7Sxc uint16_t ts_seqnum; /* h/w assigned sequence number */ 6607a1306a7Sxc uint16_t ts_tstamp; /* h/w assigned timestamp */ 6617a1306a7Sxc uint8_t ts_status; /* frame status, 0 => xmit ok */ 6627a1306a7Sxc uint8_t ts_rate; /* h/w transmit rate index */ 6637a1306a7Sxc int8_t ts_rssi; /* tx ack RSSI */ 6647a1306a7Sxc uint8_t ts_shortretry; /* # short retries */ 6657a1306a7Sxc uint8_t ts_longretry; /* # long retries */ 6667a1306a7Sxc uint8_t ts_virtcol; /* virtual collision count */ 6677a1306a7Sxc uint8_t ts_antenna; /* antenna information */ 6687a1306a7Sxc }; 6697a1306a7Sxc 6707a1306a7Sxc 6717a1306a7Sxc /* 6727a1306a7Sxc * Receive descriptor status. This structure is filled 6737a1306a7Sxc * in only after the rx descriptor process method finds a 6747a1306a7Sxc * ``done'' descriptor; at which point it returns something 6757a1306a7Sxc * other than HAL_EINPROGRESS. 6767a1306a7Sxc * 6777a1306a7Sxc * If rx_status is zero, then the frame was received ok; 6787a1306a7Sxc * otherwise the error information is indicated and rs_phyerr 6797a1306a7Sxc * contains a phy error code if HAL_RXERR_PHY is set. In general 6807a1306a7Sxc * the frame contents is undefined when an error occurred thought 6817a1306a7Sxc * for some errors (e.g. a decryption error), it may be meaningful. 6827a1306a7Sxc * 6837a1306a7Sxc * Note that the receive timestamp is expanded using the TSF to 6847a1306a7Sxc * a full 16 bits (regardless of what the h/w provides directly). 6857a1306a7Sxc * 6867a1306a7Sxc * rx_rssi is in units of dbm above the noise floor. This value 6877a1306a7Sxc * is measured during the preamble and PLCP; i.e. with the initial 6887a1306a7Sxc * 4us of detection. The noise floor is typically a consistent 6897a1306a7Sxc * -96dBm absolute power in a 20MHz channel. 6907a1306a7Sxc */ 6917a1306a7Sxc struct ath_rx_status { 6927a1306a7Sxc uint16_t rs_datalen; /* rx frame length */ 6937a1306a7Sxc uint16_t rs_tstamp; /* h/w assigned timestamp */ 6947a1306a7Sxc uint8_t rs_status; /* rx status, 0 => recv ok */ 6957a1306a7Sxc uint8_t rs_phyerr; /* phy error code */ 6967a1306a7Sxc int8_t rs_rssi; /* rx frame RSSI */ 6977a1306a7Sxc uint8_t rs_keyix; /* key cache index */ 6987a1306a7Sxc uint8_t rs_rate; /* h/w receive rate index */ 6997a1306a7Sxc uint8_t rs_antenna; /* antenna information */ 7007a1306a7Sxc uint8_t rs_more; /* see HAL_RXERR_XXX definition */ 7017a1306a7Sxc }; 7027a1306a7Sxc 7037a1306a7Sxc /* 7047a1306a7Sxc * Definitions for the software frame/packet descriptors used by 7057a1306a7Sxc * the Atheros HAL. This definition obscures hardware-specific 7067a1306a7Sxc * details from the driver. Drivers are expected to fillin the 7077a1306a7Sxc * portions of a descriptor that are not opaque then use HAL calls 7087a1306a7Sxc * to complete the work. Status for completed frames is returned 7097a1306a7Sxc * in a device-independent format. 7107a1306a7Sxc */ 7117a1306a7Sxc #pragma pack(1) 7127a1306a7Sxc struct ath_desc { 7137a1306a7Sxc /* 7147a1306a7Sxc * The following definitions are passed directly 7157a1306a7Sxc * the hardware and managed by the HAL. Drivers 7167a1306a7Sxc * should not touch those elements marked opaque. 7177a1306a7Sxc */ 7187a1306a7Sxc uint32_t ds_link; /* phys address of next descriptor */ 7197a1306a7Sxc uint32_t ds_data; /* phys address of data buffer */ 7207a1306a7Sxc uint32_t ds_ctl0; /* opaque DMA control 0 */ 7217a1306a7Sxc uint32_t ds_ctl1; /* opaque DMA control 1 */ 7227a1306a7Sxc uint32_t ds_hw[4]; /* opaque h/w region */ 7237a1306a7Sxc /* 7247a1306a7Sxc * The remaining definitions are managed by software; 7257a1306a7Sxc * these are valid only after the rx/tx process descriptor 7267a1306a7Sxc * methods return a non-EINPROGRESS code. 7277a1306a7Sxc */ 7287a1306a7Sxc union { 7297a1306a7Sxc struct ath_tx_status tx; /* xmit status */ 7307a1306a7Sxc struct ath_rx_status rx; /* recv status */ 7317a1306a7Sxc } ds_us; 732*0ba2cbe9Sxc void *ds_vdata; /* virtual addr of data buffer */ 7337a1306a7Sxc }; 7347a1306a7Sxc #pragma pack() 7357a1306a7Sxc 7367a1306a7Sxc #define ds_txstat ds_us.tx 7377a1306a7Sxc #define ds_rxstat ds_us.rx 7387a1306a7Sxc 7397a1306a7Sxc /* 7407a1306a7Sxc * Hardware Access Layer (HAL) API. 7417a1306a7Sxc * 7427a1306a7Sxc * Clients of the HAL call ath_hal_attach to obtain a reference to an 7437a1306a7Sxc * ath_hal structure for use with the device. Hardware-related operations 7447a1306a7Sxc * that follow must call back into the HAL through interface, supplying 7457a1306a7Sxc * the reference as the first parameter. Note that before using the 7467a1306a7Sxc * reference returned by ath_hal_attach the caller should verify the 7477a1306a7Sxc * ABI version number. 7487a1306a7Sxc */ 7497a1306a7Sxc struct ath_hal { 7507a1306a7Sxc uint32_t ah_magic; /* consistency check magic number */ 7517a1306a7Sxc uint32_t ah_abi; /* HAL ABI version */ 7527a1306a7Sxc uint16_t ah_devid; /* PCI device ID */ 7537a1306a7Sxc uint16_t ah_subvendorid; /* PCI subvendor ID */ 7547a1306a7Sxc HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 7557a1306a7Sxc HAL_BUS_TAG ah_st; /* params for register r+w */ 7567a1306a7Sxc HAL_BUS_HANDLE ah_sh; 7577a1306a7Sxc HAL_CTRY_CODE ah_countryCode; 7587a1306a7Sxc 7597a1306a7Sxc uint32_t ah_macVersion; /* MAC version id */ 7607a1306a7Sxc uint16_t ah_macRev; /* MAC revision */ 7617a1306a7Sxc uint16_t ah_phyRev; /* PHY revision */ 762*0ba2cbe9Sxc /* NB: when only one radio is present the rev is in 5Ghz */ 763*0ba2cbe9Sxc uint16_t ah_analog5GhzRev; /* 5GHz radio revision */ 764*0ba2cbe9Sxc uint16_t ah_analog2GhzRev; /* 2GHz radio revision */ 765*0ba2cbe9Sxc /* decomp mask array */ 766*0ba2cbe9Sxc uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 7677a1306a7Sxc 7687a1306a7Sxc const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *, 7697a1306a7Sxc uint32_t mode); 7707a1306a7Sxc void (*ah_detach) (struct ath_hal *); 7717a1306a7Sxc 7727a1306a7Sxc /* Reset functions */ 7737a1306a7Sxc HAL_BOOL (*ah_reset) (struct ath_hal *, HAL_OPMODE, 7747a1306a7Sxc HAL_CHANNEL *, HAL_BOOL bChannelChange, 7757a1306a7Sxc HAL_STATUS *status); 776*0ba2cbe9Sxc HAL_BOOL (*ah_phyDisable) (struct ath_hal *); 777*0ba2cbe9Sxc HAL_BOOL (*ah_disable) (struct ath_hal *); 778*0ba2cbe9Sxc void (*ah_setPCUConfig) (struct ath_hal *); 779*0ba2cbe9Sxc HAL_BOOL (*ah_perCalibration) (struct ath_hal *, HAL_CHANNEL *, 780*0ba2cbe9Sxc HAL_BOOL *); 7817a1306a7Sxc HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 7827a1306a7Sxc 783*0ba2cbe9Sxc void (*ah_arEnable)(struct ath_hal *); 784*0ba2cbe9Sxc void (*ah_arDisable)(struct ath_hal *); 785*0ba2cbe9Sxc void (*ah_arReset)(struct ath_hal *); 786*0ba2cbe9Sxc HAL_BOOL (*ah_radarHaveEvent)(struct ath_hal *); 787*0ba2cbe9Sxc HAL_BOOL (*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *); 788*0ba2cbe9Sxc uint32_t (*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, uint32_t); 789*0ba2cbe9Sxc HAL_BOOL (*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); 790*0ba2cbe9Sxc 7917a1306a7Sxc /* Transmit functions */ 7927a1306a7Sxc HAL_BOOL (*ah_updateTxTrigLevel) (struct ath_hal *, 7937a1306a7Sxc HAL_BOOL incTrigLevel); 7947a1306a7Sxc int (*ah_setupTxQueue) (struct ath_hal *, HAL_TX_QUEUE, 7957a1306a7Sxc const HAL_TXQ_INFO *qInfo); 7967a1306a7Sxc HAL_BOOL (*ah_setTxQueueProps) (struct ath_hal *, int q, 7977a1306a7Sxc const HAL_TXQ_INFO *qInfo); 7987a1306a7Sxc HAL_BOOL (*ah_getTxQueueProps)(struct ath_hal *, int q, 7997a1306a7Sxc HAL_TXQ_INFO *qInfo); 8007a1306a7Sxc HAL_BOOL (*ah_releaseTxQueue) (struct ath_hal *ah, uint32_t q); 8017a1306a7Sxc HAL_BOOL (*ah_resetTxQueue) (struct ath_hal *ah, uint32_t q); 8027a1306a7Sxc uint32_t (*ah_getTxDP) (struct ath_hal *, uint32_t); 8037a1306a7Sxc HAL_BOOL (*ah_setTxDP) (struct ath_hal *, uint32_t, uint32_t txdp); 8047a1306a7Sxc uint32_t (*ah_numTxPending)(struct ath_hal *, uint32_t q); 8057a1306a7Sxc HAL_BOOL (*ah_startTxDma) (struct ath_hal *, uint32_t); 8067a1306a7Sxc HAL_BOOL (*ah_stopTxDma) (struct ath_hal *, uint32_t); 8077a1306a7Sxc HAL_BOOL (*ah_setupTxDesc) (struct ath_hal *, struct ath_desc *, 8087a1306a7Sxc uint32_t pktLen, uint32_t hdrLen, 8097a1306a7Sxc HAL_PKT_TYPE type, uint32_t txPower, 8107a1306a7Sxc uint32_t txRate0, uint32_t txTries0, 8117a1306a7Sxc uint32_t keyIx, uint32_t antMode, 8127a1306a7Sxc uint32_t flags, uint32_t rtsctsRate, 813*0ba2cbe9Sxc uint32_t rtsctsDuration, 814*0ba2cbe9Sxc uint32_t compicvLen, uint32_t compivLen, 815*0ba2cbe9Sxc uint32_t comp); 8167a1306a7Sxc HAL_BOOL (*ah_setupXTxDesc) (struct ath_hal *, struct ath_desc *, 8177a1306a7Sxc uint32_t txRate1, uint32_t txTries1, 8187a1306a7Sxc uint32_t txRate2, uint32_t txTries2, 8197a1306a7Sxc uint32_t txRate3, uint32_t txTries3); 8207a1306a7Sxc HAL_BOOL (*ah_fillTxDesc) (struct ath_hal *, struct ath_desc *, 8217a1306a7Sxc uint32_t segLen, HAL_BOOL firstSeg, 8227a1306a7Sxc HAL_BOOL lastSeg, const struct ath_desc *); 8237a1306a7Sxc HAL_STATUS (*ah_procTxDesc) (struct ath_hal *, struct ath_desc *); 8247a1306a7Sxc void (*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 825*0ba2cbe9Sxc void (*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc *); 8267a1306a7Sxc 8277a1306a7Sxc /* Receive Functions */ 8287a1306a7Sxc uint32_t (*ah_getRxDP) (struct ath_hal *); 8297a1306a7Sxc void (*ah_setRxDP) (struct ath_hal *, uint32_t rxdp); 8307a1306a7Sxc void (*ah_enableReceive) (struct ath_hal *); 8317a1306a7Sxc HAL_BOOL (*ah_stopDmaReceive) (struct ath_hal *); 8327a1306a7Sxc void (*ah_startPcuReceive) (struct ath_hal *); 8337a1306a7Sxc void (*ah_stopPcuReceive) (struct ath_hal *); 8347a1306a7Sxc void (*ah_setMulticastFilter) (struct ath_hal *, 8357a1306a7Sxc uint32_t filter0, uint32_t filter1); 8367a1306a7Sxc HAL_BOOL (*ah_setMulticastFilterIndex) (struct ath_hal *, 8377a1306a7Sxc uint32_t index); 8387a1306a7Sxc HAL_BOOL (*ah_clrMulticastFilterIndex) (struct ath_hal *, 8397a1306a7Sxc uint32_t index); 8407a1306a7Sxc uint32_t (*ah_getRxFilter) (struct ath_hal *); 8417a1306a7Sxc void (*ah_setRxFilter) (struct ath_hal *, uint32_t); 8427a1306a7Sxc HAL_BOOL (*ah_setupRxDesc) (struct ath_hal *, struct ath_desc *, 8437a1306a7Sxc uint32_t size, uint32_t flags); 8447a1306a7Sxc HAL_STATUS (*ah_procRxDesc) (struct ath_hal *, struct ath_desc *, 845*0ba2cbe9Sxc uint32_t phyAddr, struct ath_desc *next, 846*0ba2cbe9Sxc uint64_t tsf); 8477a1306a7Sxc void (*ah_rxMonitor) (struct ath_hal *, 848*0ba2cbe9Sxc const HAL_NODE_STATS *, HAL_CHANNEL *); 8497a1306a7Sxc void (*ah_procMibEvent) (struct ath_hal *, 8507a1306a7Sxc const HAL_NODE_STATS *); 8517a1306a7Sxc 8527a1306a7Sxc /* Misc Functions */ 8537a1306a7Sxc HAL_STATUS (*ah_getCapability) (struct ath_hal *, 8547a1306a7Sxc HAL_CAPABILITY_TYPE, uint32_t capability, 8557a1306a7Sxc uint32_t *result); 8567a1306a7Sxc HAL_BOOL (*ah_setCapability) (struct ath_hal *, 8577a1306a7Sxc HAL_CAPABILITY_TYPE, uint32_t capability, 8587a1306a7Sxc uint32_t setting, HAL_STATUS *); 8597a1306a7Sxc HAL_BOOL (*ah_getDiagState) (struct ath_hal *, int request, 8607a1306a7Sxc const void *args, uint32_t argsize, 8617a1306a7Sxc void **result, uint32_t *resultsize); 8627a1306a7Sxc void (*ah_getMacAddress) (struct ath_hal *, uint8_t *); 8637a1306a7Sxc HAL_BOOL (*ah_setMacAddress) (struct ath_hal *, const uint8_t *); 864*0ba2cbe9Sxc void (*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 865*0ba2cbe9Sxc HAL_BOOL (*ah_setBssIdMask)(struct ath_hal *, const uint8_t *); 8667a1306a7Sxc HAL_BOOL (*ah_setRegulatoryDomain) (struct ath_hal *, 8677a1306a7Sxc uint16_t, HAL_STATUS *); 8687a1306a7Sxc void (*ah_setLedState) (struct ath_hal *, HAL_LED_STATE); 8697a1306a7Sxc void (*ah_writeAssocid) (struct ath_hal *, 8707a1306a7Sxc const uint8_t *bssid, uint16_t assocId); 8717a1306a7Sxc HAL_BOOL (*ah_gpioCfgOutput) (struct ath_hal *, uint32_t gpio); 8727a1306a7Sxc HAL_BOOL (*ah_gpioCfgInput) (struct ath_hal *, uint32_t gpio); 8737a1306a7Sxc uint32_t (*ah_gpioGet) (struct ath_hal *, uint32_t gpio); 8747a1306a7Sxc HAL_BOOL (*ah_gpioSet) (struct ath_hal *, 8757a1306a7Sxc uint32_t gpio, uint32_t val); 8767a1306a7Sxc void (*ah_gpioSetIntr) (struct ath_hal *, uint32_t, uint32_t); 8777a1306a7Sxc uint32_t (*ah_getTsf32) (struct ath_hal *); 8787a1306a7Sxc uint64_t (*ah_getTsf64) (struct ath_hal *); 8797a1306a7Sxc void (*ah_resetTsf) (struct ath_hal *); 8807a1306a7Sxc HAL_BOOL (*ah_detectCardPresent) (struct ath_hal *); 8817a1306a7Sxc void (*ah_updateMibCounters) (struct ath_hal *, HAL_MIB_STATS *); 8827a1306a7Sxc HAL_RFGAIN (*ah_getRfGain) (struct ath_hal *); 8837a1306a7Sxc uint32_t (*ah_getDefAntenna) (struct ath_hal *); 8847a1306a7Sxc void (*ah_setDefAntenna) (struct ath_hal *, uint32_t); 885*0ba2cbe9Sxc HAL_ANT_SETTING (*ah_getAntennaSwitch) (struct ath_hal *); 886*0ba2cbe9Sxc HAL_BOOL (*ah_setAntennaSwitch) (struct ath_hal *, HAL_ANT_SETTING); 8877a1306a7Sxc HAL_BOOL (*ah_setSlotTime) (struct ath_hal *, uint32_t); 8887a1306a7Sxc uint32_t (*ah_getSlotTime) (struct ath_hal *); 8897a1306a7Sxc HAL_BOOL (*ah_setAckTimeout) (struct ath_hal *, uint32_t); 8907a1306a7Sxc uint32_t (*ah_getAckTimeout) (struct ath_hal *); 891*0ba2cbe9Sxc HAL_BOOL (*ah_setAckCTSRate) (struct ath_hal *, uint32_t); 892*0ba2cbe9Sxc uint32_t (*ah_getAckCTSRate) (struct ath_hal *); 8937a1306a7Sxc HAL_BOOL (*ah_setCTSTimeout) (struct ath_hal *, uint32_t); 8947a1306a7Sxc uint32_t (*ah_getCTSTimeout) (struct ath_hal *); 895*0ba2cbe9Sxc HAL_BOOL (*ah_setDecompMask)(struct ath_hal *, uint16_t, int); 896*0ba2cbe9Sxc void (*ah_setCoverageClass)(struct ath_hal *, uint8_t, int); 8977a1306a7Sxc /* Key Cache Functions */ 8987a1306a7Sxc uint32_t (*ah_getKeyCacheSize) (struct ath_hal *); 8997a1306a7Sxc HAL_BOOL (*ah_resetKeyCacheEntry) (struct ath_hal *, uint16_t); 9007a1306a7Sxc HAL_BOOL (*ah_isKeyCacheEntryValid) (struct ath_hal *, uint16_t); 9017a1306a7Sxc HAL_BOOL (*ah_setKeyCacheEntry) (struct ath_hal *, 9027a1306a7Sxc uint16_t, const HAL_KEYVAL *, 9037a1306a7Sxc const uint8_t *, int); 9047a1306a7Sxc HAL_BOOL (*ah_setKeyCacheEntryMac) (struct ath_hal *, 9057a1306a7Sxc uint16_t, const uint8_t *); 9067a1306a7Sxc 9077a1306a7Sxc /* Power Management Functions */ 9087a1306a7Sxc HAL_BOOL (*ah_setPowerMode) (struct ath_hal *, 909*0ba2cbe9Sxc HAL_POWER_MODE mode, int setChip); 9107a1306a7Sxc HAL_POWER_MODE (*ah_getPowerMode) (struct ath_hal *); 911*0ba2cbe9Sxc int16_t (*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *); 9127a1306a7Sxc 9137a1306a7Sxc /* Beacon Management Functions */ 914*0ba2cbe9Sxc void (*ah_setBeaconTimers) (struct ath_hal *, 915*0ba2cbe9Sxc const HAL_BEACON_TIMERS *); 916*0ba2cbe9Sxc /* NB: deprecated, use ah_setBeaconTimers instead */ 9177a1306a7Sxc void (*ah_beaconInit) (struct ath_hal *, 9187a1306a7Sxc uint32_t nexttbtt, uint32_t intval); 9197a1306a7Sxc void (*ah_setStationBeaconTimers) (struct ath_hal *, 9207a1306a7Sxc const HAL_BEACON_STATE *); 9217a1306a7Sxc void (*ah_resetStationBeaconTimers) (struct ath_hal *); 9227a1306a7Sxc 9237a1306a7Sxc /* Interrupt functions */ 9247a1306a7Sxc HAL_BOOL (*ah_isInterruptPending) (struct ath_hal *); 9257a1306a7Sxc HAL_BOOL (*ah_getPendingInterrupts) (struct ath_hal *, HAL_INT *); 9267a1306a7Sxc HAL_INT (*ah_getInterrupts) (struct ath_hal *); 9277a1306a7Sxc HAL_INT (*ah_setInterrupts) (struct ath_hal *, HAL_INT); 9287a1306a7Sxc }; 9297a1306a7Sxc 9307a1306a7Sxc /* 9317a1306a7Sxc * Check the PCI vendor ID and device ID against Atheros' values 9327a1306a7Sxc * and return a printable description for any Atheros hardware. 9337a1306a7Sxc * AH_NULL is returned if the ID's do not describe Atheros hardware. 9347a1306a7Sxc */ 9357a1306a7Sxc extern const char *ath_hal_probe(uint16_t vendorid, uint16_t devid); 9367a1306a7Sxc 9377a1306a7Sxc /* 9387a1306a7Sxc * Attach the HAL for use with the specified device. The device is 9397a1306a7Sxc * defined by the PCI device ID. The caller provides an opaque pointer 9407a1306a7Sxc * to an upper-layer data structure (HAL_SOFTC) that is stored in the 9417a1306a7Sxc * HAL state block for later use. Hardware register accesses are done 9427a1306a7Sxc * using the specified bus tag and handle. On successful return a 9437a1306a7Sxc * reference to a state block is returned that must be supplied in all 9447a1306a7Sxc * subsequent HAL calls. Storage associated with this reference is 9457a1306a7Sxc * dynamically allocated and must be freed by calling the ah_detach 9467a1306a7Sxc * method when the client is done. If the attach operation fails a 9477a1306a7Sxc * null (AH_NULL) reference will be returned and a status code will 9487a1306a7Sxc * be returned if the status parameter is non-zero. 9497a1306a7Sxc */ 9507a1306a7Sxc extern struct ath_hal *ath_hal_attach(uint16_t devid, HAL_SOFTC, 9517a1306a7Sxc HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *status); 9527a1306a7Sxc 953*0ba2cbe9Sxc /* 954*0ba2cbe9Sxc * Set the Vendor ID for Vendor SKU's which can modify the 955*0ba2cbe9Sxc * channel properties returned by ath_hal_init_channels. 956*0ba2cbe9Sxc * Return AH_TRUE if set succeeds 957*0ba2cbe9Sxc */ 958*0ba2cbe9Sxc extern HAL_BOOL ath_hal_setvendor(struct ath_hal *, uint32_t); 959*0ba2cbe9Sxc 9607a1306a7Sxc /* 9617a1306a7Sxc * Return a list of channels available for use with the hardware. 9627a1306a7Sxc * The list is based on what the hardware is capable of, the specified 9637a1306a7Sxc * country code, the modeSelect mask, and whether or not outdoor 9647a1306a7Sxc * channels are to be permitted. 9657a1306a7Sxc * 9667a1306a7Sxc * The channel list is returned in the supplied array. maxchans 9677a1306a7Sxc * defines the maximum size of this array. nchans contains the actual 9687a1306a7Sxc * number of channels returned. If a problem occurred or there were 9697a1306a7Sxc * no channels that met the criteria then AH_FALSE is returned. 9707a1306a7Sxc */ 9717a1306a7Sxc extern HAL_BOOL ath_hal_init_channels(struct ath_hal *, 9727a1306a7Sxc HAL_CHANNEL *chans, uint32_t maxchans, uint32_t *nchans, 973*0ba2cbe9Sxc uint8_t *regclassids, uint32_t maxregids, uint32_t *nregids, 9747a1306a7Sxc HAL_CTRY_CODE cc, uint16_t modeSelect, 9757a1306a7Sxc HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); 9767a1306a7Sxc 977*0ba2cbe9Sxc /* 978*0ba2cbe9Sxc * Calibrate noise floor data following a channel scan or similar. 979*0ba2cbe9Sxc * This must be called prior retrieving noise floor data. 980*0ba2cbe9Sxc */ 981*0ba2cbe9Sxc extern void ath_hal_process_noisefloor(struct ath_hal *ah); 982*0ba2cbe9Sxc 9837a1306a7Sxc /* 9847a1306a7Sxc * Return bit mask of wireless modes supported by the hardware. 9857a1306a7Sxc */ 9867a1306a7Sxc extern uint32_t ath_hal_getwirelessmodes(struct ath_hal *, HAL_CTRY_CODE); 9877a1306a7Sxc 9887a1306a7Sxc /* 9897a1306a7Sxc * Return rate table for specified mode (11a, 11b, 11g, etc). 9907a1306a7Sxc */ 9917a1306a7Sxc extern const HAL_RATE_TABLE * ath_hal_getratetable(struct ath_hal *, 9927a1306a7Sxc uint32_t mode); 9937a1306a7Sxc 9947a1306a7Sxc /* 9957a1306a7Sxc * Calculate the transmit duration of a frame. 9967a1306a7Sxc */ 9977a1306a7Sxc extern uint16_t ath_hal_computetxtime(struct ath_hal *, 9987a1306a7Sxc const HAL_RATE_TABLE *rates, uint32_t frameLen, 9997a1306a7Sxc uint16_t rateix, HAL_BOOL shortPreamble); 10007a1306a7Sxc 1001*0ba2cbe9Sxc /* 1002*0ba2cbe9Sxc * Return if device is public safety. 1003*0ba2cbe9Sxc */ 1004*0ba2cbe9Sxc extern HAL_BOOL ath_hal_ispublicsafetysku(struct ath_hal *); 1005*0ba2cbe9Sxc 10067a1306a7Sxc /* 10077a1306a7Sxc * Convert between IEEE channel number and channel frequency 10087a1306a7Sxc * using the specified channel flags; e.g. CHANNEL_2GHZ. 10097a1306a7Sxc */ 1010*0ba2cbe9Sxc extern int ath_hal_mhz2ieee(struct ath_hal *, uint32_t mhz, uint32_t flags); 10117a1306a7Sxc 10127a1306a7Sxc /* 10137a1306a7Sxc * Return a version string for the HAL release. 10147a1306a7Sxc */ 10157a1306a7Sxc extern char ath_hal_version[]; 10167a1306a7Sxc 10177a1306a7Sxc /* 10187a1306a7Sxc * Return a NULL-terminated array of build/configuration options. 10197a1306a7Sxc */ 10207a1306a7Sxc extern const char *ath_hal_buildopts[]; 10217a1306a7Sxc 10227a1306a7Sxc /* 10237a1306a7Sxc * Macros to encapsulated HAL functions. 10247a1306a7Sxc */ 10257a1306a7Sxc #define ATH_HAL_RESET(_ah, _opmode, _chan, _outdoor, _pstatus) \ 10267a1306a7Sxc ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 1027*0ba2cbe9Sxc #define ATH_HAL_PHYDISABLE(_ah) \ 1028*0ba2cbe9Sxc ((*(_ah)->ah_phyDisable)((_ah))) 10297a1306a7Sxc #define ATH_HAL_GETCAPABILITY(_ah, _cap, _param, _result) \ 10307a1306a7Sxc ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1031*0ba2cbe9Sxc #define ATH_HAL_SETCAPABILITY(_ah, _type, _cap, _param, _status) \ 1032*0ba2cbe9Sxc ((*ah_setCapability)((_ah), (_type), (_cap), (_param), (_status))) 10337a1306a7Sxc #define ATH_HAL_GETREGDOMAIN(_ah, _prd) \ 10347a1306a7Sxc ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 10357a1306a7Sxc #define ATH_HAL_GETCOUNTRYCODE(_ah, _pcc) \ 10367a1306a7Sxc (*(_pcc) = (_ah)->ah_countryCode) 10377a1306a7Sxc #define ATH_HAL_GETRATETABLE(_ah, _mode) \ 10387a1306a7Sxc ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 10397a1306a7Sxc #define ATH_HAL_GETMAC(_ah, _mac) \ 10407a1306a7Sxc ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 10417a1306a7Sxc #define ATH_HAL_SETMAC(_ah, _mac) \ 10427a1306a7Sxc ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 10437a1306a7Sxc #define ATH_HAL_INTRSET(_ah, _mask) \ 10447a1306a7Sxc ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 10457a1306a7Sxc #define ATH_HAL_INTRGET(_ah) \ 10467a1306a7Sxc ((*(_ah)->ah_getInterrupts)((_ah))) 10477a1306a7Sxc #define ATH_HAL_INTRPEND(_ah) \ 10487a1306a7Sxc ((*(_ah)->ah_isInterruptPending)((_ah))) 10497a1306a7Sxc #define ATH_HAL_GETISR(_ah, _pmask) \ 10507a1306a7Sxc ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 10517a1306a7Sxc #define ATH_HAL_UPDATETXTRIGLEVEL(_ah, _inc) \ 10527a1306a7Sxc ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1053*0ba2cbe9Sxc #define ATH_HAL_SETPOWER(_ah, _mode) \ 1054*0ba2cbe9Sxc ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 10557a1306a7Sxc #define ATH_HAL_KEYRESET(_ah, _ix) \ 10567a1306a7Sxc ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1057*0ba2cbe9Sxc #define ATH_HAL_KEYSET(_ah, _ix, _pk, _mac) \ 1058*0ba2cbe9Sxc ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 10597a1306a7Sxc #define ATH_HAL_KEYISVALID(_ah, _ix) \ 10607a1306a7Sxc (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 10617a1306a7Sxc #define ATH_HAL_KEYSETMAC(_ah, _ix, _mac) \ 10627a1306a7Sxc ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 10637a1306a7Sxc #define ATH_HAL_KEYCACHESIZE(_ah) \ 10647a1306a7Sxc ((*(_ah)->ah_getKeyCacheSize)((_ah))) 10657a1306a7Sxc #define ATH_HAL_GETRXFILTER(_ah) \ 10667a1306a7Sxc ((*(_ah)->ah_getRxFilter)((_ah))) 10677a1306a7Sxc #define ATH_HAL_SETRXFILTER(_ah, _filter) \ 10687a1306a7Sxc ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 10697a1306a7Sxc #define ATH_HAL_SETMCASTFILTER(_ah, _mfilt0, _mfilt1) \ 10707a1306a7Sxc ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 10717a1306a7Sxc #define ATH_HAL_WAITFORBEACON(_ah, _bf) \ 10727a1306a7Sxc ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 10737a1306a7Sxc #define ATH_HAL_PUTRXBUF(_ah, _bufaddr) \ 10747a1306a7Sxc ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 10757a1306a7Sxc #define ATH_HAL_GETTSF32(_ah) \ 10767a1306a7Sxc ((*(_ah)->ah_getTsf32)((_ah))) 10777a1306a7Sxc #define ATH_HAL_GETTSF64(_ah) \ 10787a1306a7Sxc ((*(_ah)->ah_getTsf64)((_ah))) 10797a1306a7Sxc #define ATH_HAL_RESETTSF(_ah) \ 10807a1306a7Sxc ((*(_ah)->ah_resetTsf)((_ah))) 10817a1306a7Sxc #define ATH_HAL_RXENA(_ah) \ 10827a1306a7Sxc ((*(_ah)->ah_enableReceive)((_ah))) 10837a1306a7Sxc #define ATH_HAL_PUTTXBUF(_ah, _q, _bufaddr) \ 10847a1306a7Sxc ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 10857a1306a7Sxc #define ATH_HAL_GETTXBUF(_ah, _q) \ 10867a1306a7Sxc ((*(_ah)->ah_getTxDP)((_ah), (_q))) 10877a1306a7Sxc #define ATH_HAL_GETRXBUF(_ah) \ 10887a1306a7Sxc ((*(_ah)->ah_getRxDP)((_ah))) 10897a1306a7Sxc #define ATH_HAL_TXSTART(_ah, _q) \ 10907a1306a7Sxc ((*(_ah)->ah_startTxDma)((_ah), (_q))) 10917a1306a7Sxc #define ATH_HAL_SETCHANNEL(_ah, _chan) \ 10927a1306a7Sxc ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1093*0ba2cbe9Sxc #define ATH_HAL_CALIBRATE(_ah, _chan, _iqcal) \ 1094*0ba2cbe9Sxc ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 10957a1306a7Sxc #define ATH_HAL_SETLEDSTATE(_ah, _state) \ 10967a1306a7Sxc ((*(_ah)->ah_setLedState)((_ah), (_state))) 10977a1306a7Sxc #define ATH_HAL_BEACONINIT(_ah, _nextb, _bperiod) \ 10987a1306a7Sxc ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 10997a1306a7Sxc #define ATH_HAL_BEACONRESET(_ah) \ 11007a1306a7Sxc ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 11017a1306a7Sxc #define ATH_HAL_BEACONTIMERS(_ah, _beacon_state) \ 11027a1306a7Sxc ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_beacon_state))) 11037a1306a7Sxc #define ATH_HAL_SETASSOCID(_ah, _bss, _associd) \ 11047a1306a7Sxc ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 11057a1306a7Sxc #define ATH_HAL_SETOPMODE(_ah) \ 11067a1306a7Sxc ((*(_ah)->ah_setPCUConfig)((_ah))) 11077a1306a7Sxc #define ATH_HAL_STOPTXDMA(_ah, _qnum) \ 11087a1306a7Sxc ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 11097a1306a7Sxc #define ATH_HAL_STOPPCURECV(_ah) \ 11107a1306a7Sxc ((*(_ah)->ah_stopPcuReceive)((_ah))) 11117a1306a7Sxc #define ATH_HAL_STARTPCURECV(_ah) \ 11127a1306a7Sxc ((*(_ah)->ah_startPcuReceive)((_ah))) 11137a1306a7Sxc #define ATH_HAL_STOPDMARECV(_ah) \ 11147a1306a7Sxc ((*(_ah)->ah_stopDmaReceive)((_ah))) 11157a1306a7Sxc #define ATH_HAL_DUMPSTATE(_ah) \ 11167a1306a7Sxc ((*(_ah)->ah_dumpState)((_ah))) 11177a1306a7Sxc #define ATH_HAL_DUMPEEPROM(_ah) \ 11187a1306a7Sxc ((*(_ah)->ah_dumpEeprom)((_ah))) 11197a1306a7Sxc #define ATH_HAL_DUMPRFGAIN(_ah) \ 11207a1306a7Sxc ((*(_ah)->ah_dumpRfGain)((_ah))) 11217a1306a7Sxc #define ATH_HAL_DUMPANI(_ah) \ 11227a1306a7Sxc ((*(_ah)->ah_dumpAni)((_ah))) 11237a1306a7Sxc #define ATH_HAL_SETUPTXQUEUE(_ah, _type, _irq) \ 11247a1306a7Sxc ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 11257a1306a7Sxc #define ATH_HAL_RESETTXQUEUE(_ah, _q) \ 11267a1306a7Sxc ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 11277a1306a7Sxc #define ATH_HAL_RELEASETXQUEUE(_ah, _q) \ 11287a1306a7Sxc ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 11297a1306a7Sxc #define ATH_HAL_HASVEOL \ 11307a1306a7Sxc ((*(_ah)->ah_hasVEOL)((_ah))) 11317a1306a7Sxc #define ATH_HAL_GETRFGAIN(_ah) \ 11327a1306a7Sxc ((*(_ah)->ah_getRfGain)((_ah))) 1133*0ba2cbe9Sxc #define ATH_HAL_RXMONITOR(_ah, _arg, _chan) \ 1134*0ba2cbe9Sxc ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1135*0ba2cbe9Sxc #define ATH_HAL_SETSLOTTIME(_ah, _us) \ 1136*0ba2cbe9Sxc ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 11377a1306a7Sxc #define ATH_HAL_SETUPBEACONDESC(_ah, _ds, _opmode, _flen, _hlen, \ 11387a1306a7Sxc _rate, _antmode) \ 11397a1306a7Sxc ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 11407a1306a7Sxc (_flen), (_hlen), (_rate), (_antmode))) 11417a1306a7Sxc #define ATH_HAL_SETUPRXDESC(_ah, _ds, _size, _intreq) \ 11427a1306a7Sxc ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 11437a1306a7Sxc #define ATH_HAL_RXPROCDESC(_ah, _ds, _dspa, _dsnext) \ 1144*0ba2cbe9Sxc ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0)) 11457a1306a7Sxc #define ATH_HAL_SETUPTXDESC(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 11467a1306a7Sxc _txr0, _txtr0, _keyix, _ant, _flags, \ 11477a1306a7Sxc _rtsrate, _rtsdura) \ 11487a1306a7Sxc ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 11497a1306a7Sxc (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1150*0ba2cbe9Sxc (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 11517a1306a7Sxc #define ATH_HAL_SETUPXTXDESC(_ah, _ds, \ 11527a1306a7Sxc _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 11537a1306a7Sxc ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 11547a1306a7Sxc (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 11557a1306a7Sxc #define ATH_HAL_FILLTXDESC(_ah, _ds, _l, _first, _last, _ath_desc) \ 11567a1306a7Sxc ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), \ 11577a1306a7Sxc (_ath_desc))) 11587a1306a7Sxc #define ATH_HAL_TXPROCDESC(_ah, _ds) \ 11597a1306a7Sxc ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 11607a1306a7Sxc #define ATH_HAL_CIPHERSUPPORTED(_ah, _cipher) \ 11617a1306a7Sxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 11627a1306a7Sxc #define ATH_HAL_TKIPSPLIT(_ah) \ 11637a1306a7Sxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1164*0ba2cbe9Sxc #define ATH_HAL_HASRFSILENT(ah) \ 1165*0ba2cbe9Sxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1166*0ba2cbe9Sxc #define ATH_HAL_GETRFKILL(_ah) \ 1167*0ba2cbe9Sxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1168*0ba2cbe9Sxc #define ATH_HAL_SETRFKILL(_ah, _onoff) \ 1169*0ba2cbe9Sxc (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)) 1170*0ba2cbe9Sxc #define ATH_HAL_GETRFSILENT(_ah, _prfsilent) \ 1171*0ba2cbe9Sxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1172*0ba2cbe9Sxc #define ATH_HAL_SETRFSILENT(_ah, _rfsilent) \ 1173*0ba2cbe9Sxc (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)) 1174*0ba2cbe9Sxc 1175*0ba2cbe9Sxc #if HAL_ABI_VERSION < 0x05120700 1176*0ba2cbe9Sxc #define ATH_HAL_PROCESS_NOISEFLOOR(_ah) 1177*0ba2cbe9Sxc #define ATH_HAL_GETCHANNOISE(_ah, _c) (-96) 1178*0ba2cbe9Sxc #define HAL_CAP_TPC_ACK 100 1179*0ba2cbe9Sxc #define HAL_CAP_TPC_CTS 101 1180*0ba2cbe9Sxc #else 1181*0ba2cbe9Sxc #define ATH_HAL_GETCHANNOISE(_ah, _c) \ 1182*0ba2cbe9Sxc ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1183*0ba2cbe9Sxc #endif 1184*0ba2cbe9Sxc 1185*0ba2cbe9Sxc #if HAL_ABI_VERSION < 0x05122200 1186*0ba2cbe9Sxc #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 1187*0ba2cbe9Sxc #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 1188*0ba2cbe9Sxc #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 1189*0ba2cbe9Sxc #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 1190*0ba2cbe9Sxc #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 1191*0ba2cbe9Sxc #endif 11927a1306a7Sxc 11937a1306a7Sxc #ifdef __cplusplus 11947a1306a7Sxc } 11957a1306a7Sxc #endif 11967a1306a7Sxc 11977a1306a7Sxc #endif /* _ATH_HAL_H */ 1198