10eb090a7SSaurabh Misra /* 20eb090a7SSaurabh Misra * CDDL HEADER START 30eb090a7SSaurabh Misra * 40eb090a7SSaurabh Misra * The contents of this file are subject to the terms of the 50eb090a7SSaurabh Misra * Common Development and Distribution License (the "License"). 60eb090a7SSaurabh Misra * You may not use this file except in compliance with the License. 70eb090a7SSaurabh Misra * 80eb090a7SSaurabh Misra * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90eb090a7SSaurabh Misra * or http://www.opensolaris.org/os/licensing. 100eb090a7SSaurabh Misra * See the License for the specific language governing permissions 110eb090a7SSaurabh Misra * and limitations under the License. 120eb090a7SSaurabh Misra * 130eb090a7SSaurabh Misra * When distributing Covered Code, include this CDDL HEADER in each 140eb090a7SSaurabh Misra * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150eb090a7SSaurabh Misra * If applicable, add the following below this CDDL HEADER, with the 160eb090a7SSaurabh Misra * fields enclosed by brackets "[]" replaced with your own identifying 170eb090a7SSaurabh Misra * information: Portions Copyright [yyyy] [name of copyright owner] 180eb090a7SSaurabh Misra * 190eb090a7SSaurabh Misra * CDDL HEADER END 200eb090a7SSaurabh Misra */ 210eb090a7SSaurabh Misra /* 220eb090a7SSaurabh Misra * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 230eb090a7SSaurabh Misra * Use is subject to license terms. 24*5e8715b9SGary Mills * Copyright (c) 2012 Gary Mills 250eb090a7SSaurabh Misra */ 260eb090a7SSaurabh Misra 270eb090a7SSaurabh Misra #ifndef _ATGE_L1_REG_H 280eb090a7SSaurabh Misra #define _ATGE_L1_REG_H 290eb090a7SSaurabh Misra 300eb090a7SSaurabh Misra #ifdef __cplusplus 310eb090a7SSaurabh Misra extern "C" { 320eb090a7SSaurabh Misra #endif 330eb090a7SSaurabh Misra 340eb090a7SSaurabh Misra #pragma pack(1) 350eb090a7SSaurabh Misra typedef struct l1_cmb { 360eb090a7SSaurabh Misra uint32_t intr_status; 370eb090a7SSaurabh Misra uint32_t rx_prod_cons; 380eb090a7SSaurabh Misra uint32_t tx_prod_cons; 390eb090a7SSaurabh Misra } l1_cmb_t; 400eb090a7SSaurabh Misra 410eb090a7SSaurabh Misra typedef struct l1_rx_desc { 420eb090a7SSaurabh Misra uint64_t addr; 430eb090a7SSaurabh Misra uint32_t len; 440eb090a7SSaurabh Misra } l1_rx_desc_t; 450eb090a7SSaurabh Misra 460eb090a7SSaurabh Misra typedef struct l1_rx_rdesc { 470eb090a7SSaurabh Misra uint32_t index; 480eb090a7SSaurabh Misra uint32_t len; 490eb090a7SSaurabh Misra uint32_t flags; 500eb090a7SSaurabh Misra uint32_t vtags; 510eb090a7SSaurabh Misra } l1_rx_rdesc_t; 520eb090a7SSaurabh Misra 530eb090a7SSaurabh Misra /* 540eb090a7SSaurabh Misra * Statistics counters collected by the MAC 550eb090a7SSaurabh Misra */ 560eb090a7SSaurabh Misra typedef struct l1_smb { 570eb090a7SSaurabh Misra /* Rx stats. */ 580eb090a7SSaurabh Misra uint32_t rx_frames; 590eb090a7SSaurabh Misra uint32_t rx_bcast_frames; 600eb090a7SSaurabh Misra uint32_t rx_mcast_frames; 610eb090a7SSaurabh Misra uint32_t rx_pause_frames; 620eb090a7SSaurabh Misra uint32_t rx_control_frames; 630eb090a7SSaurabh Misra uint32_t rx_crcerrs; 640eb090a7SSaurabh Misra uint32_t rx_lenerrs; 650eb090a7SSaurabh Misra uint32_t rx_bytes; 660eb090a7SSaurabh Misra uint32_t rx_runts; 670eb090a7SSaurabh Misra uint32_t rx_fragments; 680eb090a7SSaurabh Misra uint32_t rx_pkts_64; 690eb090a7SSaurabh Misra uint32_t rx_pkts_65_127; 700eb090a7SSaurabh Misra uint32_t rx_pkts_128_255; 710eb090a7SSaurabh Misra uint32_t rx_pkts_256_511; 720eb090a7SSaurabh Misra uint32_t rx_pkts_512_1023; 730eb090a7SSaurabh Misra uint32_t rx_pkts_1024_1518; 740eb090a7SSaurabh Misra uint32_t rx_pkts_1519_max; 750eb090a7SSaurabh Misra uint32_t rx_pkts_truncated; 760eb090a7SSaurabh Misra uint32_t rx_fifo_oflows; 770eb090a7SSaurabh Misra uint32_t rx_desc_oflows; 780eb090a7SSaurabh Misra uint32_t rx_alignerrs; 790eb090a7SSaurabh Misra uint32_t rx_bcast_bytes; 800eb090a7SSaurabh Misra uint32_t rx_mcast_bytes; 810eb090a7SSaurabh Misra uint32_t rx_pkts_filtered; 820eb090a7SSaurabh Misra /* Tx stats. */ 830eb090a7SSaurabh Misra uint32_t tx_frames; 840eb090a7SSaurabh Misra uint32_t tx_bcast_frames; 850eb090a7SSaurabh Misra uint32_t tx_mcast_frames; 860eb090a7SSaurabh Misra uint32_t tx_pause_frames; 870eb090a7SSaurabh Misra uint32_t tx_excess_defer; 880eb090a7SSaurabh Misra uint32_t tx_control_frames; 890eb090a7SSaurabh Misra uint32_t tx_deferred; 900eb090a7SSaurabh Misra uint32_t tx_bytes; 910eb090a7SSaurabh Misra uint32_t tx_pkts_64; 920eb090a7SSaurabh Misra uint32_t tx_pkts_65_127; 930eb090a7SSaurabh Misra uint32_t tx_pkts_128_255; 940eb090a7SSaurabh Misra uint32_t tx_pkts_256_511; 950eb090a7SSaurabh Misra uint32_t tx_pkts_512_1023; 960eb090a7SSaurabh Misra uint32_t tx_pkts_1024_1518; 970eb090a7SSaurabh Misra uint32_t tx_pkts_1519_max; 980eb090a7SSaurabh Misra uint32_t tx_single_colls; 990eb090a7SSaurabh Misra uint32_t tx_multi_colls; 1000eb090a7SSaurabh Misra uint32_t tx_late_colls; 1010eb090a7SSaurabh Misra uint32_t tx_excess_colls; 1020eb090a7SSaurabh Misra uint32_t tx_underrun; 1030eb090a7SSaurabh Misra uint32_t tx_desc_underrun; 1040eb090a7SSaurabh Misra uint32_t tx_lenerrs; 1050eb090a7SSaurabh Misra uint32_t tx_pkts_truncated; 1060eb090a7SSaurabh Misra uint32_t tx_bcast_bytes; 1070eb090a7SSaurabh Misra uint32_t tx_mcast_bytes; 1080eb090a7SSaurabh Misra uint32_t updated; 1090eb090a7SSaurabh Misra } atge_l1_smb_t; 1100eb090a7SSaurabh Misra #pragma pack() 1110eb090a7SSaurabh Misra 1120eb090a7SSaurabh Misra #define L1_RX_RING_CNT 256 1130eb090a7SSaurabh Misra #define L1_RR_RING_CNT (ATGE_TX_RING_CNT + L1_RX_RING_CNT) 1140eb090a7SSaurabh Misra 1150eb090a7SSaurabh Misra #define L1_RING_ALIGN 16 1160eb090a7SSaurabh Misra #define L1_TX_RING_ALIGN 16 1170eb090a7SSaurabh Misra #define L1_RX_RING_ALIGN 16 1180eb090a7SSaurabh Misra #define L1_RR_RING_ALIGN 16 1190eb090a7SSaurabh Misra #define L1_CMB_ALIGN 16 1200eb090a7SSaurabh Misra #define L1_SMB_ALIGN 16 1210eb090a7SSaurabh Misra 1220eb090a7SSaurabh Misra #define L1_CMB_BLOCK_SZ sizeof (struct l1_cmb) 1230eb090a7SSaurabh Misra #define L1_SMB_BLOCK_SZ sizeof (struct l1_smb) 1240eb090a7SSaurabh Misra 1250eb090a7SSaurabh Misra #define L1_RX_RING_SZ \ 1260eb090a7SSaurabh Misra (sizeof (struct l1_rx_desc) * L1_RX_RING_CNT) 1270eb090a7SSaurabh Misra 1280eb090a7SSaurabh Misra #define L1_RR_RING_SZ \ 1290eb090a7SSaurabh Misra (sizeof (struct l1_rx_rdesc) * L1_RR_RING_CNT) 1300eb090a7SSaurabh Misra 1310eb090a7SSaurabh Misra /* 1320eb090a7SSaurabh Misra * For RX 1330eb090a7SSaurabh Misra */ 1340eb090a7SSaurabh Misra #define L1_RRD_CONS_SHIFT 16 1350eb090a7SSaurabh Misra #define L1_RRD_NSEGS_MASK 0x000000FF 1360eb090a7SSaurabh Misra #define L1_RRD_CONS_MASK 0xFFFF0000 1370eb090a7SSaurabh Misra #define L1_RRD_NSEGS_SHIFT 0 1380eb090a7SSaurabh Misra #define L1_RRD_LEN_MASK 0xFFFF0000 1390eb090a7SSaurabh Misra #define L1_RRD_CSUM_MASK 0x0000FFFF 1400eb090a7SSaurabh Misra #define L1_RRD_CSUM_SHIFT 0 1410eb090a7SSaurabh Misra #define L1_RRD_LEN_SHIFT 16 1420eb090a7SSaurabh Misra #define L1_RRD_ETHERNET 0x00000080 1430eb090a7SSaurabh Misra #define L1_RRD_VLAN 0x00000100 1440eb090a7SSaurabh Misra #define L1_RRD_ERROR 0x00000200 1450eb090a7SSaurabh Misra #define L1_RRD_IPV4 0x00000400 1460eb090a7SSaurabh Misra #define L1_RRD_UDP 0x00000800 1470eb090a7SSaurabh Misra #define L1_RRD_TCP 0x00001000 1480eb090a7SSaurabh Misra #define L1_RRD_BCAST 0x00002000 1490eb090a7SSaurabh Misra #define L1_RRD_MCAST 0x00004000 1500eb090a7SSaurabh Misra #define L1_RRD_PAUSE 0x00008000 1510eb090a7SSaurabh Misra #define L1_RRD_CRC 0x00010000 1520eb090a7SSaurabh Misra #define L1_RRD_CODE 0x00020000 1530eb090a7SSaurabh Misra #define L1_RRD_DRIBBLE 0x00040000 1540eb090a7SSaurabh Misra #define L1_RRD_RUNT 0x00080000 1550eb090a7SSaurabh Misra #define L1_RRD_OFLOW 0x00100000 1560eb090a7SSaurabh Misra #define L1_RRD_TRUNC 0x00200000 1570eb090a7SSaurabh Misra #define L1_RRD_IPCSUM_NOK 0x00400000 1580eb090a7SSaurabh Misra #define L1_RRD_TCP_UDPCSUM_NOK 0x00800000 1590eb090a7SSaurabh Misra #define L1_RRD_LENGTH_NOK 0x01000000 1600eb090a7SSaurabh Misra #define L1_RRD_DES_ADDR_FILTERED 0x02000000 1610eb090a7SSaurabh Misra #define RRD_PROD_MASK 0x0000FFFF 1620eb090a7SSaurabh Misra #define TPD_CONS_MASK 0xFFFF0000 1630eb090a7SSaurabh Misra #define TPD_CONS_SHIFT 16 1640eb090a7SSaurabh Misra #define CMB_UPDATED 0x00000001 1650eb090a7SSaurabh Misra #define RRD_PROD_SHIFT 0 1660eb090a7SSaurabh Misra 1670eb090a7SSaurabh Misra /* 1680eb090a7SSaurabh Misra * All descriptors and CMB/SMB share the same high address. 1690eb090a7SSaurabh Misra */ 1700eb090a7SSaurabh Misra #define L1_DESC_ADDR_HI 0x1540 1710eb090a7SSaurabh Misra #define L1_DESC_RD_ADDR_LO 0x1544 1720eb090a7SSaurabh Misra #define L1_DESC_RRD_ADDR_LO 0x1548 1730eb090a7SSaurabh Misra #define L1_DESC_TPD_ADDR_LO 0x154C 1740eb090a7SSaurabh Misra #define L1_DESC_CMB_ADDR_LO 0x1550 1750eb090a7SSaurabh Misra #define L1_DESC_SMB_ADDR_LO 0x1554 1760eb090a7SSaurabh Misra #define L1_DESC_RRD_RD_CNT 0x1558 1770eb090a7SSaurabh Misra #define DESC_RRD_CNT_SHIFT 16 1780eb090a7SSaurabh Misra #define DESC_RRD_CNT_MASK 0x07FF0000 1790eb090a7SSaurabh Misra #define DESC_RD_CNT_SHIFT 0 1800eb090a7SSaurabh Misra #define DESC_RD_CNT_MASK 0x000007FF 1810eb090a7SSaurabh Misra 1820eb090a7SSaurabh Misra /* 1830eb090a7SSaurabh Misra * PHY registers. 1840eb090a7SSaurabh Misra */ 1850eb090a7SSaurabh Misra #define PHY_CDTS_STAT_OK 0x0000 1860eb090a7SSaurabh Misra #define PHY_CDTS_STAT_SHORT 0x0100 1870eb090a7SSaurabh Misra #define PHY_CDTS_STAT_OPEN 0x0200 1880eb090a7SSaurabh Misra #define PHY_CDTS_STAT_INVAL 0x0300 1890eb090a7SSaurabh Misra #define PHY_CDTS_STAT_MASK 0x0300 1900eb090a7SSaurabh Misra 1910eb090a7SSaurabh Misra /* 1920eb090a7SSaurabh Misra * DMA CFG registers (L1 specific) 1930eb090a7SSaurabh Misra */ 1940eb090a7SSaurabh Misra #define DMA_CFG_RD_ENB 0x00000400 1950eb090a7SSaurabh Misra #define DMA_CFG_WR_ENB 0x00000800 1960eb090a7SSaurabh Misra #define DMA_CFG_RD_BURST_MASK 0x07 1970eb090a7SSaurabh Misra #define DMA_CFG_RD_BURST_SHIFT 4 1980eb090a7SSaurabh Misra #define DMA_CFG_WR_BURST_MASK 0x07 1990eb090a7SSaurabh Misra #define DMA_CFG_WR_BURST_SHIFT 7 2000eb090a7SSaurabh Misra 2010eb090a7SSaurabh Misra #define L1_RD_LEN_MASK 0x0000FFFF 2020eb090a7SSaurabh Misra #define L1_RD_LEN_SHIFT 0 2030eb090a7SSaurabh Misra 2040eb090a7SSaurabh Misra #define L1_SRAM_RD_ADDR 0x1500 2050eb090a7SSaurabh Misra #define L1_SRAM_RD_LEN 0x1504 2060eb090a7SSaurabh Misra #define L1_SRAM_RRD_ADDR 0x1508 2070eb090a7SSaurabh Misra #define L1_SRAM_RRD_LEN 0x150C 2080eb090a7SSaurabh Misra #define L1_SRAM_TPD_ADDR 0x1510 2090eb090a7SSaurabh Misra #define L1_SRAM_TPD_LEN 0x1514 2100eb090a7SSaurabh Misra #define L1_SRAM_TRD_ADDR 0x1518 2110eb090a7SSaurabh Misra #define L1_SRAM_TRD_LEN 0x151C 2120eb090a7SSaurabh Misra #define L1_SRAM_RX_FIFO_ADDR 0x1520 2130eb090a7SSaurabh Misra #define L1_SRAM_RX_FIFO_LEN 0x1524 2140eb090a7SSaurabh Misra #define L1_SRAM_TX_FIFO_ADDR 0x1528 2150eb090a7SSaurabh Misra #define L1_SRAM_TX_FIFO_LEN 0x152C 2160eb090a7SSaurabh Misra 2170eb090a7SSaurabh Misra #define RXQ_CFG_RD_BURST_MASK 0x000000FF 2180eb090a7SSaurabh Misra #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 2190eb090a7SSaurabh Misra #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 2200eb090a7SSaurabh Misra #define RXQ_CFG_RD_BURST_SHIFT 0 2210eb090a7SSaurabh Misra #define RXQ_CFG_RD_BURST_DEFAULT 8 2220eb090a7SSaurabh Misra #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 2230eb090a7SSaurabh Misra #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 2240eb090a7SSaurabh Misra #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 2250eb090a7SSaurabh Misra #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 2260eb090a7SSaurabh Misra 2270eb090a7SSaurabh Misra #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 2280eb090a7SSaurabh Misra #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 2290eb090a7SSaurabh Misra #define TXQ_CFG_TPD_FETCH_DEFAULT 16 2300eb090a7SSaurabh Misra 2310eb090a7SSaurabh Misra #define L1_TX_JUMBO_TPD_TH_IPG 0x1584 2320eb090a7SSaurabh Misra #define TX_JUMBO_TPD_TH_MASK 0x000007FF 2330eb090a7SSaurabh Misra #define TX_JUMBO_TPD_IPG_MASK 0x001F0000 2340eb090a7SSaurabh Misra #define TX_JUMBO_TPD_TH_SHIFT 0 2350eb090a7SSaurabh Misra #define TX_JUMBO_TPD_IPG_SHIFT 16 2360eb090a7SSaurabh Misra #define TX_JUMBO_TPD_IPG_DEFAULT 1 2370eb090a7SSaurabh Misra 2380eb090a7SSaurabh Misra /* CMB DMA Write Threshold Register */ 2390eb090a7SSaurabh Misra #define L1_CMB_WR_THRESH 0x15D4 2400eb090a7SSaurabh Misra #define CMB_WR_THRESH_RRD_MASK 0x000007FF 2410eb090a7SSaurabh Misra #define CMB_WR_THRESH_TPD_MASK 0x07FF0000 2420eb090a7SSaurabh Misra #define CMB_WR_THRESH_RRD_SHIFT 0 2430eb090a7SSaurabh Misra #define CMB_WR_THRESH_RRD_DEFAULT 4 2440eb090a7SSaurabh Misra #define CMB_WR_THRESH_TPD_SHIFT 16 2450eb090a7SSaurabh Misra #define CMB_WR_THRESH_TPD_DEFAULT 4 2460eb090a7SSaurabh Misra 2470eb090a7SSaurabh Misra /* SMB auto DMA timer register */ 2480eb090a7SSaurabh Misra #define L1_SMB_TIMER 0x15E4 2490eb090a7SSaurabh Misra 2500eb090a7SSaurabh Misra #define L1_CSMB_CTRL 0x15D0 2510eb090a7SSaurabh Misra #define CSMB_CTRL_CMB_KICK 0x00000001 2520eb090a7SSaurabh Misra #define CSMB_CTRL_SMB_KICK 0x00000002 2530eb090a7SSaurabh Misra #define CSMB_CTRL_CMB_ENB 0x00000004 2540eb090a7SSaurabh Misra #define CSMB_CTRL_SMB_ENB 0x00000008 2550eb090a7SSaurabh Misra 2560eb090a7SSaurabh Misra #define INTR_RX_DMA 0x00080000 2570eb090a7SSaurabh Misra #define INTR_CMB_RX 0x00100000 2580eb090a7SSaurabh Misra #define INTR_CMB_TX 0x00200000 2590eb090a7SSaurabh Misra #define INTR_DIS_SMB 0x20000000 2600eb090a7SSaurabh Misra 2610eb090a7SSaurabh Misra #define L1_INTRS \ 2620eb090a7SSaurabh Misra (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 2630eb090a7SSaurabh Misra INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN) 2640eb090a7SSaurabh Misra 2650eb090a7SSaurabh Misra #define L1_RXQ_RRD_PAUSE_THRESH 0x15AC 2660eb090a7SSaurabh Misra #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 2670eb090a7SSaurabh Misra #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 2680eb090a7SSaurabh Misra #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 2690eb090a7SSaurabh Misra #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 2700eb090a7SSaurabh Misra 2710eb090a7SSaurabh Misra /* RX/TX count-down timer to trigger CMB-write. */ 2720eb090a7SSaurabh Misra #define L1_CMB_WR_TIMER 0x15D8 2730eb090a7SSaurabh Misra #define CMB_WR_TIMER_RX_MASK 0x0000FFFF 2740eb090a7SSaurabh Misra #define CMB_WR_TIMER_TX_MASK 0xFFFF0000 2750eb090a7SSaurabh Misra #define CMB_WR_TIMER_RX_SHIFT 0 2760eb090a7SSaurabh Misra #define CMB_WR_TIMER_TX_SHIFT 16 2770eb090a7SSaurabh Misra 2780eb090a7SSaurabh Misra /* 2790eb090a7SSaurabh Misra * Useful macros. 2800eb090a7SSaurabh Misra */ 2810eb090a7SSaurabh Misra #define L1_RX_NSEGS(x) \ 2820eb090a7SSaurabh Misra (((x) & L1_RRD_NSEGS_MASK) >> L1_RRD_NSEGS_SHIFT) 2830eb090a7SSaurabh Misra #define L1_RX_CONS(x) \ 2840eb090a7SSaurabh Misra (((x) & L1_RRD_CONS_MASK) >> L1_RRD_CONS_SHIFT) 2850eb090a7SSaurabh Misra #define L1_RX_CSUM(x) \ 2860eb090a7SSaurabh Misra (((x) & L1_RRD_CSUM_MASK) >> L1_RRD_CSUM_SHIFT) 2870eb090a7SSaurabh Misra #define L1_RX_BYTES(x) \ 2880eb090a7SSaurabh Misra (((x) & L1_RRD_LEN_MASK) >> L1_RRD_LEN_SHIFT) 2890eb090a7SSaurabh Misra 2900eb090a7SSaurabh Misra 2910eb090a7SSaurabh Misra #ifdef __cplusplus 2920eb090a7SSaurabh Misra } 2930eb090a7SSaurabh Misra #endif 2940eb090a7SSaurabh Misra 2950eb090a7SSaurabh Misra #endif /* _ATGE_L1_REG_H */ 296