1*8eea8e29Sap /*
2*8eea8e29Sap * CDDL HEADER START
3*8eea8e29Sap *
4*8eea8e29Sap * The contents of this file are subject to the terms of the
5*8eea8e29Sap * Common Development and Distribution License, Version 1.0 only
6*8eea8e29Sap * (the "License"). You may not use this file except in compliance
7*8eea8e29Sap * with the License.
8*8eea8e29Sap *
9*8eea8e29Sap * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*8eea8e29Sap * or http://www.opensolaris.org/os/licensing.
11*8eea8e29Sap * See the License for the specific language governing permissions
12*8eea8e29Sap * and limitations under the License.
13*8eea8e29Sap *
14*8eea8e29Sap * When distributing Covered Code, include this CDDL HEADER in each
15*8eea8e29Sap * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*8eea8e29Sap * If applicable, add the following below this CDDL HEADER, with the
17*8eea8e29Sap * fields enclosed by brackets "[]" replaced with your own identifying
18*8eea8e29Sap * information: Portions Copyright [yyyy] [name of copyright owner]
19*8eea8e29Sap *
20*8eea8e29Sap * CDDL HEADER END
21*8eea8e29Sap */
22*8eea8e29Sap /*
23*8eea8e29Sap * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24*8eea8e29Sap * Use is subject to license terms.
25*8eea8e29Sap */
26*8eea8e29Sap
27*8eea8e29Sap /*
28*8eea8e29Sap * dcam_reg.c
29*8eea8e29Sap *
30*8eea8e29Sap * dcam1394 driver. Control register access support.
31*8eea8e29Sap */
32*8eea8e29Sap
33*8eea8e29Sap #include <sys/1394/targets/dcam1394/dcam_reg.h>
34*8eea8e29Sap
35*8eea8e29Sap
36*8eea8e29Sap /*
37*8eea8e29Sap * dcam_reg_read
38*8eea8e29Sap */
39*8eea8e29Sap int
dcam_reg_read(dcam_state_t * soft_state,dcam1394_reg_io_t * arg)40*8eea8e29Sap dcam_reg_read(dcam_state_t *soft_state, dcam1394_reg_io_t *arg)
41*8eea8e29Sap {
42*8eea8e29Sap cmd1394_cmd_t *cmdp;
43*8eea8e29Sap
44*8eea8e29Sap if (t1394_alloc_cmd(soft_state->sl_handle, 1, &cmdp) != DDI_SUCCESS) {
45*8eea8e29Sap return (-1);
46*8eea8e29Sap }
47*8eea8e29Sap
48*8eea8e29Sap cmdp->cmd_type = CMD1394_ASYNCH_RD_QUAD;
49*8eea8e29Sap cmdp->cmd_addr = 0x0000FFFFF0F00000 |
50*8eea8e29Sap (uint64_t)(arg->offs & 0x00000FFC);
51*8eea8e29Sap cmdp->cmd_options = CMD1394_BLOCKING;
52*8eea8e29Sap
53*8eea8e29Sap #ifdef GRAPHICS_DELAY
54*8eea8e29Sap /*
55*8eea8e29Sap * This delay should not be necessary, but was added for some
56*8eea8e29Sap * unknown reason. Should it ever be determined that it
57*8eea8e29Sap * is necessary, this delay should be reenabled.
58*8eea8e29Sap */
59*8eea8e29Sap delay(drv_usectohz(500));
60*8eea8e29Sap #endif
61*8eea8e29Sap
62*8eea8e29Sap if (t1394_read(soft_state->sl_handle, cmdp) != DDI_SUCCESS) {
63*8eea8e29Sap (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
64*8eea8e29Sap return (-1);
65*8eea8e29Sap }
66*8eea8e29Sap
67*8eea8e29Sap if (cmdp->cmd_result != DDI_SUCCESS) {
68*8eea8e29Sap (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
69*8eea8e29Sap return (-1);
70*8eea8e29Sap }
71*8eea8e29Sap
72*8eea8e29Sap /* perform endian adjustment */
73*8eea8e29Sap cmdp->cmd_u.q.quadlet_data = T1394_DATA32(cmdp->cmd_u.q.quadlet_data);
74*8eea8e29Sap arg->val = cmdp->cmd_u.q.quadlet_data;
75*8eea8e29Sap
76*8eea8e29Sap (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
77*8eea8e29Sap
78*8eea8e29Sap return (0);
79*8eea8e29Sap }
80*8eea8e29Sap
81*8eea8e29Sap
82*8eea8e29Sap /*
83*8eea8e29Sap * dcam_reg_write
84*8eea8e29Sap */
85*8eea8e29Sap int
dcam_reg_write(dcam_state_t * soft_state,dcam1394_reg_io_t * arg)86*8eea8e29Sap dcam_reg_write(dcam_state_t *soft_state, dcam1394_reg_io_t *arg)
87*8eea8e29Sap {
88*8eea8e29Sap cmd1394_cmd_t *cmdp;
89*8eea8e29Sap
90*8eea8e29Sap if (t1394_alloc_cmd(soft_state->sl_handle, 0, &cmdp) != DDI_SUCCESS) {
91*8eea8e29Sap return (-1);
92*8eea8e29Sap }
93*8eea8e29Sap
94*8eea8e29Sap cmdp->cmd_type = CMD1394_ASYNCH_WR_QUAD;
95*8eea8e29Sap cmdp->cmd_addr = 0x0000FFFFF0F00000 |
96*8eea8e29Sap (uint64_t)(arg->offs & 0x00000FFC);
97*8eea8e29Sap cmdp->cmd_options = CMD1394_BLOCKING;
98*8eea8e29Sap
99*8eea8e29Sap /* perform endian adjustment */
100*8eea8e29Sap cmdp->cmd_u.q.quadlet_data = T1394_DATA32(arg->val);
101*8eea8e29Sap
102*8eea8e29Sap #ifdef GRAPHICS_DELAY
103*8eea8e29Sap /*
104*8eea8e29Sap * See the description in dcam_reg_read() above.
105*8eea8e29Sap */
106*8eea8e29Sap delay(drv_usectohz(500));
107*8eea8e29Sap #endif
108*8eea8e29Sap
109*8eea8e29Sap if (t1394_write(soft_state->sl_handle, cmdp) != DDI_SUCCESS) {
110*8eea8e29Sap (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
111*8eea8e29Sap return (-1);
112*8eea8e29Sap }
113*8eea8e29Sap
114*8eea8e29Sap if (cmdp->cmd_result != DDI_SUCCESS) {
115*8eea8e29Sap (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
116*8eea8e29Sap return (-1);
117*8eea8e29Sap }
118*8eea8e29Sap
119*8eea8e29Sap (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
120*8eea8e29Sap
121*8eea8e29Sap return (0);
122*8eea8e29Sap }
123